drivers/gpu/drm/amd/amdgpu/nv.c

   1 /*
   2  * Copyright 2019 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23 #include <linux/firmware.h>
  24 #include <linux/slab.h>
  25 #include <linux/module.h>
  26 #include <linux/pci.h>
  27
  28 #include "amdgpu.h"
  29 #include "amdgpu_atombios.h"
  30 #include "amdgpu_ih.h"
  31 #include "amdgpu_uvd.h"
  32 #include "amdgpu_vce.h"
  33 #include "amdgpu_ucode.h"
  34 #include "amdgpu_psp.h"
  35 #include "amdgpu_smu.h"
  36 #include "atom.h"
  37 #include "amd_pcie.h"
  38
  39 #include "gc/gc_10_1_0_offset.h"
  40 #include "gc/gc_10_1_0_sh_mask.h"
  41 #include "hdp/hdp_5_0_0_offset.h"
  42 #include "hdp/hdp_5_0_0_sh_mask.h"
  43 #include "smuio/smuio_11_0_0_offset.h"
  44
  45 #include "soc15.h"
  46 #include "soc15_common.h"
  47 #include "gmc_v10_0.h"
  48 #include "gfxhub_v2_0.h"
  49 #include "mmhub_v2_0.h"
  50 #include "nbio_v2_3.h"
  51 #include "nv.h"
  52 #include "navi10_ih.h"
  53 #include "gfx_v10_0.h"
  54 #include "sdma_v5_0.h"
  55 #include "vcn_v2_0.h"
  56 #include "jpeg_v2_0.h"
  57 #include "dce_virtual.h"
  58 #include "mes_v10_1.h"
  59 #include "mxgpu_nv.h"
  60
  61 static const struct amd_ip_funcs nv_common_ip_funcs;
  62
  63 /*
  64  * Indirect registers accessor
  65  */
  66 static u32 nv_pcie_rreg(struct amdgpu_device *adev, u32 reg)
  67 {
  68         unsigned long flags, address, data;
  69         u32 r;
  70         address = adev->nbio.funcs->get_pcie_index_offset(adev);
  71         data = adev->nbio.funcs->get_pcie_data_offset(adev);
  72
  73         spin_lock_irqsave(&adev->pcie_idx_lock, flags);
  74         WREG32(address, reg);
  75         (void)RREG32(address);
  76         r = RREG32(data);
  77         spin_unlock_irqrestore(&adev->pcie_idx_lock, flags);
  78         return r;
  79 }
  80
  81 static void nv_pcie_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
  82 {
  83         unsigned long flags, address, data;
  84
  85         address = adev->nbio.funcs->get_pcie_index_offset(adev);
  86         data = adev->nbio.funcs->get_pcie_data_offset(adev);
  87
  88         spin_lock_irqsave(&adev->pcie_idx_lock, flags);
  89         WREG32(address, reg);
  90         (void)RREG32(address);
  91         WREG32(data, v);
  92         (void)RREG32(data);
  93         spin_unlock_irqrestore(&adev->pcie_idx_lock, flags);
  94 }
  95
  96 static u32 nv_didt_rreg(struct amdgpu_device *adev, u32 reg)
  97 {
  98         unsigned long flags, address, data;
  99         u32 r;
 100
 101         address = SOC15_REG_OFFSET(GC, 0, mmDIDT_IND_INDEX);
 102         data = SOC15_REG_OFFSET(GC, 0, mmDIDT_IND_DATA);
 103
 104         spin_lock_irqsave(&adev->didt_idx_lock, flags);
 105         WREG32(address, (reg));
 106         r = RREG32(data);
 107         spin_unlock_irqrestore(&adev->didt_idx_lock, flags);
 108         return r;
 109 }
 110
 111 static void nv_didt_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
 112 {
 113         unsigned long flags, address, data;
 114
 115         address = SOC15_REG_OFFSET(GC, 0, mmDIDT_IND_INDEX);
 116         data = SOC15_REG_OFFSET(GC, 0, mmDIDT_IND_DATA);
 117
 118         spin_lock_irqsave(&adev->didt_idx_lock, flags);
 119         WREG32(address, (reg));
 120         WREG32(data, (v));
 121         spin_unlock_irqrestore(&adev->didt_idx_lock, flags);
 122 }
 123
 124 static u32 nv_get_config_memsize(struct amdgpu_device *adev)
 125 {
 126         return adev->nbio.funcs->get_memsize(adev);
 127 }
 128
 129 static u32 nv_get_xclk(struct amdgpu_device *adev)
 130 {
 131         return adev->clock.spll.reference_freq;
 132 }
 133
 134
 135 void nv_grbm_select(struct amdgpu_device *adev,
 136                      u32 me, u32 pipe, u32 queue, u32 vmid)
 137 {
 138         u32 grbm_gfx_cntl = 0;
 139         grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, PIPEID, pipe);
 140         grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, MEID, me);
 141         grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, VMID, vmid);
 142         grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, QUEUEID, queue);
 143
 144         WREG32(SOC15_REG_OFFSET(GC, 0, mmGRBM_GFX_CNTL), grbm_gfx_cntl);
 145 }
 146
 147 static void nv_vga_set_state(struct amdgpu_device *adev, bool state)
 148 {
 149         /* todo */
 150 }
 151
 152 static bool nv_read_disabled_bios(struct amdgpu_device *adev)
 153 {
 154         /* todo */
 155         return false;
 156 }
 157
 158 static bool nv_read_bios_from_rom(struct amdgpu_device *adev,
 159                                   u8 *bios, u32 length_bytes)
 160 {
 161         u32 *dw_ptr;
 162         u32 i, length_dw;
 163
 164         if (bios == NULL)
 165                 return false;
 166         if (length_bytes == 0)
 167                 return false;
 168         /* APU vbios image is part of sbios image */
 169         if (adev->flags & AMD_IS_APU)
 170                 return false;
 171
 172         dw_ptr = (u32 *)bios;
 173         length_dw = ALIGN(length_bytes, 4) / 4;
 174
 175         /* set rom index to 0 */
 176         WREG32(SOC15_REG_OFFSET(SMUIO, 0, mmROM_INDEX), 0);
 177         /* read out the rom data */
 178         for (i = 0; i < length_dw; i++)
 179                 dw_ptr[i] = RREG32(SOC15_REG_OFFSET(SMUIO, 0, mmROM_DATA));
 180
 181         return true;
 182 }
 183
 184 static struct soc15_allowed_register_entry nv_allowed_read_registers[] = {
 185         { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS)},
 186         { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS2)},
 187         { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS_SE0)},
 188         { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS_SE1)},
 189         { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS_SE2)},
 190         { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS_SE3)},
 191 #if 0   /* TODO: will set it when SDMA header is available */
 192         { SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_STATUS_REG)},
 193         { SOC15_REG_ENTRY(SDMA1, 0, mmSDMA1_STATUS_REG)},
 194 #endif
 195         { SOC15_REG_ENTRY(GC, 0, mmCP_STAT)},
 196         { SOC15_REG_ENTRY(GC, 0, mmCP_STALLED_STAT1)},
 197         { SOC15_REG_ENTRY(GC, 0, mmCP_STALLED_STAT2)},
 198         { SOC15_REG_ENTRY(GC, 0, mmCP_STALLED_STAT3)},
 199         { SOC15_REG_ENTRY(GC, 0, mmCP_CPF_BUSY_STAT)},
 200         { SOC15_REG_ENTRY(GC, 0, mmCP_CPF_STALLED_STAT1)},
 201         { SOC15_REG_ENTRY(GC, 0, mmCP_CPF_STATUS)},
 202         { SOC15_REG_ENTRY(GC, 0, mmCP_CPC_BUSY_STAT)},
 203         { SOC15_REG_ENTRY(GC, 0, mmCP_CPC_STALLED_STAT1)},
 204         { SOC15_REG_ENTRY(GC, 0, mmCP_CPC_STATUS)},
 205         { SOC15_REG_ENTRY(GC, 0, mmGB_ADDR_CONFIG)},
 206 };
 207
 208 static uint32_t nv_read_indexed_register(struct amdgpu_device *adev, u32 se_num,
 209                                          u32 sh_num, u32 reg_offset)
 210 {
 211         uint32_t val;
 212
 213         mutex_lock(&adev->grbm_idx_mutex);
 214         if (se_num != 0xffffffff || sh_num != 0xffffffff)
 215                 amdgpu_gfx_select_se_sh(adev, se_num, sh_num, 0xffffffff);
 216
 217         val = RREG32(reg_offset);
 218
 219         if (se_num != 0xffffffff || sh_num != 0xffffffff)
 220                 amdgpu_gfx_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
 221         mutex_unlock(&adev->grbm_idx_mutex);
 222         return val;
 223 }
 224
 225 static uint32_t nv_get_register_value(struct amdgpu_device *adev,
 226                                       bool indexed, u32 se_num,
 227                                       u32 sh_num, u32 reg_offset)
 228 {
 229         if (indexed) {
 230                 return nv_read_indexed_register(adev, se_num, sh_num, reg_offset);
 231         } else {
 232                 if (reg_offset == SOC15_REG_OFFSET(GC, 0, mmGB_ADDR_CONFIG))
 233                         return adev->gfx.config.gb_addr_config;
 234                 return RREG32(reg_offset);
 235         }
 236 }
 237
 238 static int nv_read_register(struct amdgpu_device *adev, u32 se_num,
 239                             u32 sh_num, u32 reg_offset, u32 *value)
 240 {
 241         uint32_t i;
 242         struct soc15_allowed_register_entry  *en;
 243
 244         *value = 0;
 245         for (i = 0; i < ARRAY_SIZE(nv_allowed_read_registers); i++) {
 246                 en = &nv_allowed_read_registers[i];
 247                 if (reg_offset !=
 248                     (adev->reg_offset[en->hwip][en->inst][en->seg] + en->reg_offset))
 249                         continue;
 250
 251                 *value = nv_get_register_value(adev,
 252                                                nv_allowed_read_registers[i].grbm_indexed,
 253                                                se_num, sh_num, reg_offset);
 254                 return 0;
 255         }
 256         return -EINVAL;
 257 }
 258
 259 #if 0
 260 static void nv_gpu_pci_config_reset(struct amdgpu_device *adev)
 261 {
 262         u32 i;
 263
 264         dev_info(adev->dev, "GPU pci config reset\n");
 265
 266         /* disable BM */
 267         pci_clear_master(adev->pdev);
 268         /* reset */
 269         amdgpu_pci_config_reset(adev);
 270
 271         udelay(100);
 272
 273         /* wait for asic to come out of reset */
 274         for (i = 0; i < adev->usec_timeout; i++) {
 275                 u32 memsize = nbio_v2_3_get_memsize(adev);
 276                 if (memsize != 0xffffffff)
 277                         break;
 278                 udelay(1);
 279         }
 280
 281 }
 282 #endif
 283
 284 static int nv_asic_mode1_reset(struct amdgpu_device *adev)
 285 {
 286         u32 i;
 287         int ret = 0;
 288
 289         amdgpu_atombios_scratch_regs_engine_hung(adev, true);
 290
 291         dev_info(adev->dev, "GPU mode1 reset\n");
 292
 293         /* disable BM */
 294         pci_clear_master(adev->pdev);
 295
 296         pci_save_state(adev->pdev);
 297
 298         ret = psp_gpu_reset(adev);
 299         if (ret)
 300                 dev_err(adev->dev, "GPU mode1 reset failed\n");
 301
 302         pci_restore_state(adev->pdev);
 303
 304         /* wait for asic to come out of reset */
 305         for (i = 0; i < adev->usec_timeout; i++) {
 306                 u32 memsize = adev->nbio.funcs->get_memsize(adev);
 307
 308                 if (memsize != 0xffffffff)
 309                         break;
 310                 udelay(1);
 311         }
 312
 313         amdgpu_atombios_scratch_regs_engine_hung(adev, false);
 314
 315         return ret;
 316 }
 317
 318 static enum amd_reset_method
 319 nv_asic_reset_method(struct amdgpu_device *adev)
 320 {
 321         struct smu_context *smu = &adev->smu;
 322
 323         if (!amdgpu_sriov_vf(adev) && smu_baco_is_support(smu))
 324                 return AMD_RESET_METHOD_BACO;
 325         else
 326                 return AMD_RESET_METHOD_MODE1;
 327 }
 328
 329 static int nv_asic_reset(struct amdgpu_device *adev)
 330 {
 331
 332         /* FIXME: it doesn't work since vega10 */
 333 #if 0
 334         amdgpu_atombios_scratch_regs_engine_hung(adev, true);
 335
 336         nv_gpu_pci_config_reset(adev);
 337
 338         amdgpu_atombios_scratch_regs_engine_hung(adev, false);
 339 #endif
 340         int ret = 0;
 341         struct smu_context *smu = &adev->smu;
 342
 343         if (nv_asic_reset_method(adev) == AMD_RESET_METHOD_BACO) {
 344                 if (!adev->in_suspend)
 345                         amdgpu_inc_vram_lost(adev);
 346                 ret = smu_baco_reset(smu);
 347         } else {
 348                 if (!adev->in_suspend)
 349                         amdgpu_inc_vram_lost(adev);
 350                 ret = nv_asic_mode1_reset(adev);
 351         }
 352
 353         return ret;
 354 }
 355
 356 static int nv_set_uvd_clocks(struct amdgpu_device *adev, u32 vclk, u32 dclk)
 357 {
 358         /* todo */
 359         return 0;
 360 }
 361
 362 static int nv_set_vce_clocks(struct amdgpu_device *adev, u32 evclk, u32 ecclk)
 363 {
 364         /* todo */
 365         return 0;
 366 }
 367
 368 static void nv_pcie_gen3_enable(struct amdgpu_device *adev)
 369 {
 370         if (pci_is_root_bus(adev->pdev->bus))
 371                 return;
 372
 373         if (amdgpu_pcie_gen2 == 0)
 374                 return;
 375
 376         if (!(adev->pm.pcie_gen_mask & (CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2 |
 377                                         CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3)))
 378                 return;
 379
 380         /* todo */
 381 }
 382
 383 static void nv_program_aspm(struct amdgpu_device *adev)
 384 {
 385
 386         if (amdgpu_aspm == 0)
 387                 return;
 388
 389         /* todo */
 390 }
 391
 392 static void nv_enable_doorbell_aperture(struct amdgpu_device *adev,
 393                                         bool enable)
 394 {
 395         adev->nbio.funcs->enable_doorbell_aperture(adev, enable);
 396         adev->nbio.funcs->enable_doorbell_selfring_aperture(adev, enable);
 397 }
 398
 399 static const struct amdgpu_ip_block_version nv_common_ip_block =
 400 {
 401         .type = AMD_IP_BLOCK_TYPE_COMMON,
 402         .major = 1,
 403         .minor = 0,
 404         .rev = 0,
 405         .funcs = &nv_common_ip_funcs,
 406 };
 407
 408 static int nv_reg_base_init(struct amdgpu_device *adev)
 409 {
 410         int r;
 411
 412         if (amdgpu_discovery) {
 413                 r = amdgpu_discovery_reg_base_init(adev);
 414                 if (r) {
 415                         DRM_WARN("failed to init reg base from ip discovery table, "
 416                                         "fallback to legacy init method\n");
 417                         goto legacy_init;
 418                 }
 419
 420                 return 0;
 421         }
 422
 423 legacy_init:
 424         switch (adev->asic_type) {
 425         case CHIP_NAVI10:
 426                 navi10_reg_base_init(adev);
 427                 break;
 428         case CHIP_NAVI14:
 429                 navi14_reg_base_init(adev);
 430                 break;
 431         case CHIP_NAVI12:
 432                 navi12_reg_base_init(adev);
 433                 break;
 434         default:
 435                 return -EINVAL;
 436         }
 437
 438         return 0;
 439 }
 440
 441 int nv_set_ip_blocks(struct amdgpu_device *adev)
 442 {
 443         int r;
 444
 445         /* Set IP register base before any HW register access */
 446         r = nv_reg_base_init(adev);
 447         if (r)
 448                 return r;
 449
 450         adev->nbio.funcs = &nbio_v2_3_funcs;
 451         adev->nbio.hdp_flush_reg = &nbio_v2_3_hdp_flush_reg;
 452
 453         adev->nbio.funcs->detect_hw_virt(adev);
 454
 455         if (amdgpu_sriov_vf(adev))
 456                 adev->virt.ops = &xgpu_nv_virt_ops;
 457
 458         switch (adev->asic_type) {
 459         case CHIP_NAVI10:
 460         case CHIP_NAVI14:
 461                 amdgpu_device_ip_block_add(adev, &nv_common_ip_block);
 462                 amdgpu_device_ip_block_add(adev, &gmc_v10_0_ip_block);
 463                 amdgpu_device_ip_block_add(adev, &navi10_ih_ip_block);
 464                 amdgpu_device_ip_block_add(adev, &psp_v11_0_ip_block);
 465                 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP &&
 466                     is_support_sw_smu(adev) && !amdgpu_sriov_vf(adev))
 467                         amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block);
 468                 if (adev->enable_virtual_display || amdgpu_sriov_vf(adev))
 469                         amdgpu_device_ip_block_add(adev, &dce_virtual_ip_block);
 470 #if defined(CONFIG_DRM_AMD_DC)
 471                 else if (amdgpu_device_has_dc_support(adev))
 472                         amdgpu_device_ip_block_add(adev, &dm_ip_block);
 473 #endif
 474                 amdgpu_device_ip_block_add(adev, &gfx_v10_0_ip_block);
 475                 amdgpu_device_ip_block_add(adev, &sdma_v5_0_ip_block);
 476                 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT &&
 477                     is_support_sw_smu(adev) && !amdgpu_sriov_vf(adev))
 478                         amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block);
 479                 amdgpu_device_ip_block_add(adev, &vcn_v2_0_ip_block);
 480                 amdgpu_device_ip_block_add(adev, &jpeg_v2_0_ip_block);
 481                 if (adev->enable_mes)
 482                         amdgpu_device_ip_block_add(adev, &mes_v10_1_ip_block);
 483                 break;
 484         case CHIP_NAVI12:
 485                 amdgpu_device_ip_block_add(adev, &nv_common_ip_block);
 486                 amdgpu_device_ip_block_add(adev, &gmc_v10_0_ip_block);
 487                 amdgpu_device_ip_block_add(adev, &navi10_ih_ip_block);
 488                 amdgpu_device_ip_block_add(adev, &psp_v11_0_ip_block);
 489                 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP &&
 490                     is_support_sw_smu(adev) && !amdgpu_sriov_vf(adev))
 491                         amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block);
 492                 if (adev->enable_virtual_display || amdgpu_sriov_vf(adev))
 493                         amdgpu_device_ip_block_add(adev, &dce_virtual_ip_block);
 494 #if defined(CONFIG_DRM_AMD_DC)
 495                 else if (amdgpu_device_has_dc_support(adev))
 496                         amdgpu_device_ip_block_add(adev, &dm_ip_block);
 497 #endif
 498                 amdgpu_device_ip_block_add(adev, &gfx_v10_0_ip_block);
 499                 amdgpu_device_ip_block_add(adev, &sdma_v5_0_ip_block);
 500                 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT &&
 501                     is_support_sw_smu(adev) && !amdgpu_sriov_vf(adev))
 502                         amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block);
 503                 amdgpu_device_ip_block_add(adev, &vcn_v2_0_ip_block);
 504                 amdgpu_device_ip_block_add(adev, &jpeg_v2_0_ip_block);
 505                 break;
 506         default:
 507                 return -EINVAL;
 508         }
 509
 510         return 0;
 511 }
 512
 513 static uint32_t nv_get_rev_id(struct amdgpu_device *adev)
 514 {
 515         return adev->nbio.funcs->get_rev_id(adev);
 516 }
 517
 518 static void nv_flush_hdp(struct amdgpu_device *adev, struct amdgpu_ring *ring)
 519 {
 520         adev->nbio.funcs->hdp_flush(adev, ring);
 521 }
 522
 523 static void nv_invalidate_hdp(struct amdgpu_device *adev,
 524                                 struct amdgpu_ring *ring)
 525 {
 526         if (!ring || !ring->funcs->emit_wreg) {
 527                 WREG32_SOC15_NO_KIQ(NBIO, 0, mmHDP_READ_CACHE_INVALIDATE, 1);
 528         } else {
 529                 amdgpu_ring_emit_wreg(ring, SOC15_REG_OFFSET(
 530                                         HDP, 0, mmHDP_READ_CACHE_INVALIDATE), 1);
 531         }
 532 }
 533
 534 static bool nv_need_full_reset(struct amdgpu_device *adev)
 535 {
 536         return true;
 537 }
 538
 539 static void nv_get_pcie_usage(struct amdgpu_device *adev,
 540                               uint64_t *count0,
 541                               uint64_t *count1)
 542 {
 543         /*TODO*/
 544 }
 545
 546 static bool nv_need_reset_on_init(struct amdgpu_device *adev)
 547 {
 548 #if 0
 549         u32 sol_reg;
 550
 551         if (adev->flags & AMD_IS_APU)
 552                 return false;
 553
 554         /* Check sOS sign of life register to confirm sys driver and sOS
 555          * are already been loaded.
 556          */
 557         sol_reg = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_81);
 558         if (sol_reg)
 559                 return true;
 560 #endif
 561         /* TODO: re-enable it when mode1 reset is functional */
 562         return false;
 563 }
 564
 565 static uint64_t nv_get_pcie_replay_count(struct amdgpu_device *adev)
 566 {
 567
 568         /* TODO
 569          * dummy implement for pcie_replay_count sysfs interface
 570          * */
 571
 572         return 0;
 573 }
 574
 575 static void nv_init_doorbell_index(struct amdgpu_device *adev)
 576 {
 577         adev->doorbell_index.kiq = AMDGPU_NAVI10_DOORBELL_KIQ;
 578         adev->doorbell_index.mec_ring0 = AMDGPU_NAVI10_DOORBELL_MEC_RING0;
 579         adev->doorbell_index.mec_ring1 = AMDGPU_NAVI10_DOORBELL_MEC_RING1;
 580         adev->doorbell_index.mec_ring2 = AMDGPU_NAVI10_DOORBELL_MEC_RING2;
 581         adev->doorbell_index.mec_ring3 = AMDGPU_NAVI10_DOORBELL_MEC_RING3;
 582         adev->doorbell_index.mec_ring4 = AMDGPU_NAVI10_DOORBELL_MEC_RING4;
 583         adev->doorbell_index.mec_ring5 = AMDGPU_NAVI10_DOORBELL_MEC_RING5;
 584         adev->doorbell_index.mec_ring6 = AMDGPU_NAVI10_DOORBELL_MEC_RING6;
 585         adev->doorbell_index.mec_ring7 = AMDGPU_NAVI10_DOORBELL_MEC_RING7;
 586         adev->doorbell_index.userqueue_start = AMDGPU_NAVI10_DOORBELL_USERQUEUE_START;
 587         adev->doorbell_index.userqueue_end = AMDGPU_NAVI10_DOORBELL_USERQUEUE_END;
 588         adev->doorbell_index.gfx_ring0 = AMDGPU_NAVI10_DOORBELL_GFX_RING0;
 589         adev->doorbell_index.gfx_ring1 = AMDGPU_NAVI10_DOORBELL_GFX_RING1;
 590         adev->doorbell_index.sdma_engine[0] = AMDGPU_NAVI10_DOORBELL_sDMA_ENGINE0;
 591         adev->doorbell_index.sdma_engine[1] = AMDGPU_NAVI10_DOORBELL_sDMA_ENGINE1;
 592         adev->doorbell_index.ih = AMDGPU_NAVI10_DOORBELL_IH;
 593         adev->doorbell_index.vcn.vcn_ring0_1 = AMDGPU_NAVI10_DOORBELL64_VCN0_1;
 594         adev->doorbell_index.vcn.vcn_ring2_3 = AMDGPU_NAVI10_DOORBELL64_VCN2_3;
 595         adev->doorbell_index.vcn.vcn_ring4_5 = AMDGPU_NAVI10_DOORBELL64_VCN4_5;
 596         adev->doorbell_index.vcn.vcn_ring6_7 = AMDGPU_NAVI10_DOORBELL64_VCN6_7;
 597         adev->doorbell_index.first_non_cp = AMDGPU_NAVI10_DOORBELL64_FIRST_NON_CP;
 598         adev->doorbell_index.last_non_cp = AMDGPU_NAVI10_DOORBELL64_LAST_NON_CP;
 599
 600         adev->doorbell_index.max_assignment = AMDGPU_NAVI10_DOORBELL_MAX_ASSIGNMENT << 1;
 601         adev->doorbell_index.sdma_doorbell_range = 20;
 602 }
 603
 604 static const struct amdgpu_asic_funcs nv_asic_funcs =
 605 {
 606         .read_disabled_bios = &nv_read_disabled_bios,
 607         .read_bios_from_rom = &nv_read_bios_from_rom,
 608         .read_register = &nv_read_register,
 609         .reset = &nv_asic_reset,
 610         .reset_method = &nv_asic_reset_method,
 611         .set_vga_state = &nv_vga_set_state,
 612         .get_xclk = &nv_get_xclk,
 613         .set_uvd_clocks = &nv_set_uvd_clocks,
 614         .set_vce_clocks = &nv_set_vce_clocks,
 615         .get_config_memsize = &nv_get_config_memsize,
 616         .flush_hdp = &nv_flush_hdp,
 617         .invalidate_hdp = &nv_invalidate_hdp,
 618         .init_doorbell_index = &nv_init_doorbell_index,
 619         .need_full_reset = &nv_need_full_reset,
 620         .get_pcie_usage = &nv_get_pcie_usage,
 621         .need_reset_on_init = &nv_need_reset_on_init,
 622         .get_pcie_replay_count = &nv_get_pcie_replay_count,
 623 };
 624
 625 static int nv_common_early_init(void *handle)
 626 {
 627 #define MMIO_REG_HOLE_OFFSET (0x80000 - PAGE_SIZE)
 628         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 629
 630         adev->rmmio_remap.reg_offset = MMIO_REG_HOLE_OFFSET;
 631         adev->rmmio_remap.bus_addr = adev->rmmio_base + MMIO_REG_HOLE_OFFSET;
 632         adev->smc_rreg = NULL;
 633         adev->smc_wreg = NULL;
 634         adev->pcie_rreg = &nv_pcie_rreg;
 635         adev->pcie_wreg = &nv_pcie_wreg;
 636
 637         /* TODO: will add them during VCN v2 implementation */
 638         adev->uvd_ctx_rreg = NULL;
 639         adev->uvd_ctx_wreg = NULL;
 640
 641         adev->didt_rreg = &nv_didt_rreg;
 642         adev->didt_wreg = &nv_didt_wreg;
 643
 644         adev->asic_funcs = &nv_asic_funcs;
 645
 646         adev->rev_id = nv_get_rev_id(adev);
 647         adev->external_rev_id = 0xff;
 648         switch (adev->asic_type) {
 649         case CHIP_NAVI10:
 650                 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
 651                         AMD_CG_SUPPORT_GFX_CGCG |
 652                         AMD_CG_SUPPORT_IH_CG |
 653                         AMD_CG_SUPPORT_HDP_MGCG |
 654                         AMD_CG_SUPPORT_HDP_LS |
 655                         AMD_CG_SUPPORT_SDMA_MGCG |
 656                         AMD_CG_SUPPORT_SDMA_LS |
 657                         AMD_CG_SUPPORT_MC_MGCG |
 658                         AMD_CG_SUPPORT_MC_LS |
 659                         AMD_CG_SUPPORT_ATHUB_MGCG |
 660                         AMD_CG_SUPPORT_ATHUB_LS |
 661                         AMD_CG_SUPPORT_VCN_MGCG |
 662                         AMD_CG_SUPPORT_JPEG_MGCG |
 663                         AMD_CG_SUPPORT_BIF_MGCG |
 664                         AMD_CG_SUPPORT_BIF_LS;
 665                 adev->pg_flags = AMD_PG_SUPPORT_VCN |
 666                         AMD_PG_SUPPORT_VCN_DPG |
 667                         AMD_PG_SUPPORT_JPEG |
 668                         AMD_PG_SUPPORT_ATHUB;
 669                 adev->external_rev_id = adev->rev_id + 0x1;
 670                 break;
 671         case CHIP_NAVI14:
 672                 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
 673                         AMD_CG_SUPPORT_GFX_CGCG |
 674                         AMD_CG_SUPPORT_IH_CG |
 675                         AMD_CG_SUPPORT_HDP_MGCG |
 676                         AMD_CG_SUPPORT_HDP_LS |
 677                         AMD_CG_SUPPORT_SDMA_MGCG |
 678                         AMD_CG_SUPPORT_SDMA_LS |
 679                         AMD_CG_SUPPORT_MC_MGCG |
 680                         AMD_CG_SUPPORT_MC_LS |
 681                         AMD_CG_SUPPORT_ATHUB_MGCG |
 682                         AMD_CG_SUPPORT_ATHUB_LS |
 683                         AMD_CG_SUPPORT_VCN_MGCG |
 684                         AMD_CG_SUPPORT_JPEG_MGCG |
 685                         AMD_CG_SUPPORT_BIF_MGCG |
 686                         AMD_CG_SUPPORT_BIF_LS;
 687                 adev->pg_flags = AMD_PG_SUPPORT_VCN |
 688                         AMD_PG_SUPPORT_JPEG |
 689                         AMD_PG_SUPPORT_VCN_DPG;
 690                 adev->external_rev_id = adev->rev_id + 20;
 691                 break;
 692         case CHIP_NAVI12:
 693                 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
 694                         AMD_CG_SUPPORT_GFX_MGLS |
 695                         AMD_CG_SUPPORT_GFX_CGCG |
 696                         AMD_CG_SUPPORT_GFX_CP_LS |
 697                         AMD_CG_SUPPORT_GFX_RLC_LS |
 698                         AMD_CG_SUPPORT_IH_CG |
 699                         AMD_CG_SUPPORT_HDP_MGCG |
 700                         AMD_CG_SUPPORT_HDP_LS |
 701                         AMD_CG_SUPPORT_SDMA_MGCG |
 702                         AMD_CG_SUPPORT_SDMA_LS |
 703                         AMD_CG_SUPPORT_MC_MGCG |
 704                         AMD_CG_SUPPORT_MC_LS |
 705                         AMD_CG_SUPPORT_ATHUB_MGCG |
 706                         AMD_CG_SUPPORT_ATHUB_LS |
 707                         AMD_CG_SUPPORT_VCN_MGCG |
 708                         AMD_CG_SUPPORT_JPEG_MGCG;
 709                 adev->pg_flags = AMD_PG_SUPPORT_VCN |
 710                         AMD_PG_SUPPORT_VCN_DPG |
 711                         AMD_PG_SUPPORT_JPEG |
 712                         AMD_PG_SUPPORT_ATHUB;
 713                 adev->external_rev_id = adev->rev_id + 0xa;
 714                 break;
 715         default:
 716                 /* FIXME: not supported yet */
 717                 return -EINVAL;
 718         }
 719
 720         if (amdgpu_sriov_vf(adev)) {
 721                 amdgpu_virt_init_setting(adev);
 722                 xgpu_nv_mailbox_set_irq_funcs(adev);
 723         }
 724
 725         return 0;
 726 }
 727
 728 static int nv_common_late_init(void *handle)
 729 {
 730         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 731
 732         if (amdgpu_sriov_vf(adev))
 733                 xgpu_nv_mailbox_get_irq(adev);
 734
 735         return 0;
 736 }
 737
 738 static int nv_common_sw_init(void *handle)
 739 {
 740         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 741
 742         if (amdgpu_sriov_vf(adev))
 743                 xgpu_nv_mailbox_add_irq_id(adev);
 744
 745         return 0;
 746 }
 747
 748 static int nv_common_sw_fini(void *handle)
 749 {
 750         return 0;
 751 }
 752
 753 static int nv_common_hw_init(void *handle)
 754 {
 755         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 756
 757         /* enable pcie gen2/3 link */
 758         nv_pcie_gen3_enable(adev);
 759         /* enable aspm */
 760         nv_program_aspm(adev);
 761         /* setup nbio registers */
 762         adev->nbio.funcs->init_registers(adev);
 763         /* remap HDP registers to a hole in mmio space,
 764          * for the purpose of expose those registers
 765          * to process space
 766          */
 767         if (adev->nbio.funcs->remap_hdp_registers)
 768                 adev->nbio.funcs->remap_hdp_registers(adev);
 769         /* enable the doorbell aperture */
 770         nv_enable_doorbell_aperture(adev, true);
 771
 772         return 0;
 773 }
 774
 775 static int nv_common_hw_fini(void *handle)
 776 {
 777         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 778
 779         /* disable the doorbell aperture */
 780         nv_enable_doorbell_aperture(adev, false);
 781
 782         return 0;
 783 }
 784
 785 static int nv_common_suspend(void *handle)
 786 {
 787         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 788
 789         return nv_common_hw_fini(adev);
 790 }
 791
 792 static int nv_common_resume(void *handle)
 793 {
 794         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 795
 796         return nv_common_hw_init(adev);
 797 }
 798
 799 static bool nv_common_is_idle(void *handle)
 800 {
 801         return true;
 802 }
 803
 804 static int nv_common_wait_for_idle(void *handle)
 805 {
 806         return 0;
 807 }
 808
 809 static int nv_common_soft_reset(void *handle)
 810 {
 811         return 0;
 812 }
 813
 814 static void nv_update_hdp_mem_power_gating(struct amdgpu_device *adev,
 815                                            bool enable)
 816 {
 817         uint32_t hdp_clk_cntl, hdp_clk_cntl1;
 818         uint32_t hdp_mem_pwr_cntl;
 819
 820         if (!(adev->cg_flags & (AMD_CG_SUPPORT_HDP_LS |
 821                                 AMD_CG_SUPPORT_HDP_DS |
 822                                 AMD_CG_SUPPORT_HDP_SD)))
 823                 return;
 824
 825         hdp_clk_cntl = hdp_clk_cntl1 = RREG32_SOC15(HDP, 0, mmHDP_CLK_CNTL);
 826         hdp_mem_pwr_cntl = RREG32_SOC15(HDP, 0, mmHDP_MEM_POWER_CTRL);
 827
 828         /* Before doing clock/power mode switch,
 829          * forced on IPH & RC clock */
 830         hdp_clk_cntl = REG_SET_FIELD(hdp_clk_cntl, HDP_CLK_CNTL,
 831                                      IPH_MEM_CLK_SOFT_OVERRIDE, 1);
 832         hdp_clk_cntl = REG_SET_FIELD(hdp_clk_cntl, HDP_CLK_CNTL,
 833                                      RC_MEM_CLK_SOFT_OVERRIDE, 1);
 834         WREG32_SOC15(HDP, 0, mmHDP_CLK_CNTL, hdp_clk_cntl);
 835
 836         /* HDP 5.0 doesn't support dynamic power mode switch,
 837          * disable clock and power gating before any changing */
 838         hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, HDP_MEM_POWER_CTRL,
 839                                          IPH_MEM_POWER_CTRL_EN, 0);
 840         hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, HDP_MEM_POWER_CTRL,
 841                                          IPH_MEM_POWER_LS_EN, 0);
 842         hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, HDP_MEM_POWER_CTRL,
 843                                          IPH_MEM_POWER_DS_EN, 0);
 844         hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, HDP_MEM_POWER_CTRL,
 845                                          IPH_MEM_POWER_SD_EN, 0);
 846         hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, HDP_MEM_POWER_CTRL,
 847                                          RC_MEM_POWER_CTRL_EN, 0);
 848         hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, HDP_MEM_POWER_CTRL,
 849                                          RC_MEM_POWER_LS_EN, 0);
 850         hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, HDP_MEM_POWER_CTRL,
 851                                          RC_MEM_POWER_DS_EN, 0);
 852         hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, HDP_MEM_POWER_CTRL,
 853                                          RC_MEM_POWER_SD_EN, 0);
 854         WREG32_SOC15(HDP, 0, mmHDP_MEM_POWER_CTRL, hdp_mem_pwr_cntl);
 855
 856         /* only one clock gating mode (LS/DS/SD) can be enabled */
 857         if (adev->cg_flags & AMD_CG_SUPPORT_HDP_LS) {
 858                 hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl,
 859                                                  HDP_MEM_POWER_CTRL,
 860                                                  IPH_MEM_POWER_LS_EN, enable);
 861                 hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl,
 862                                                  HDP_MEM_POWER_CTRL,
 863                                                  RC_MEM_POWER_LS_EN, enable);
 864         } else if (adev->cg_flags & AMD_CG_SUPPORT_HDP_DS) {
 865                 hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl,
 866                                                  HDP_MEM_POWER_CTRL,
 867                                                  IPH_MEM_POWER_DS_EN, enable);
 868                 hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl,
 869                                                  HDP_MEM_POWER_CTRL,
 870                                                  RC_MEM_POWER_DS_EN, enable);
 871         } else if (adev->cg_flags & AMD_CG_SUPPORT_HDP_SD) {
 872                 hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl,
 873                                                  HDP_MEM_POWER_CTRL,
 874                                                  IPH_MEM_POWER_SD_EN, enable);
 875                 /* RC should not use shut down mode, fallback to ds */
 876                 hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl,
 877                                                  HDP_MEM_POWER_CTRL,
 878                                                  RC_MEM_POWER_DS_EN, enable);
 879         }
 880
 881         WREG32_SOC15(HDP, 0, mmHDP_MEM_POWER_CTRL, hdp_mem_pwr_cntl);
 882
 883         /* restore IPH & RC clock override after clock/power mode changing */
 884         WREG32_SOC15(HDP, 0, mmHDP_CLK_CNTL, hdp_clk_cntl1);
 885 }
 886
 887 static void nv_update_hdp_clock_gating(struct amdgpu_device *adev,
 888                                        bool enable)
 889 {
 890         uint32_t hdp_clk_cntl;
 891
 892         if (!(adev->cg_flags & AMD_CG_SUPPORT_HDP_MGCG))
 893                 return;
 894
 895         hdp_clk_cntl = RREG32_SOC15(HDP, 0, mmHDP_CLK_CNTL);
 896
 897         if (enable) {
 898                 hdp_clk_cntl &=
 899                         ~(uint32_t)
 900                           (HDP_CLK_CNTL__IPH_MEM_CLK_SOFT_OVERRIDE_MASK |
 901                            HDP_CLK_CNTL__RC_MEM_CLK_SOFT_OVERRIDE_MASK |
 902                            HDP_CLK_CNTL__DBUS_CLK_SOFT_OVERRIDE_MASK |
 903                            HDP_CLK_CNTL__DYN_CLK_SOFT_OVERRIDE_MASK |
 904                            HDP_CLK_CNTL__XDP_REG_CLK_SOFT_OVERRIDE_MASK |
 905                            HDP_CLK_CNTL__HDP_REG_CLK_SOFT_OVERRIDE_MASK);
 906         } else {
 907                 hdp_clk_cntl |= HDP_CLK_CNTL__IPH_MEM_CLK_SOFT_OVERRIDE_MASK |
 908                         HDP_CLK_CNTL__RC_MEM_CLK_SOFT_OVERRIDE_MASK |
 909                         HDP_CLK_CNTL__DBUS_CLK_SOFT_OVERRIDE_MASK |
 910                         HDP_CLK_CNTL__DYN_CLK_SOFT_OVERRIDE_MASK |
 911                         HDP_CLK_CNTL__XDP_REG_CLK_SOFT_OVERRIDE_MASK |
 912                         HDP_CLK_CNTL__HDP_REG_CLK_SOFT_OVERRIDE_MASK;
 913         }
 914
 915         WREG32_SOC15(HDP, 0, mmHDP_CLK_CNTL, hdp_clk_cntl);
 916 }
 917
 918 static int nv_common_set_clockgating_state(void *handle,
 919                                            enum amd_clockgating_state state)
 920 {
 921         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 922
 923         if (amdgpu_sriov_vf(adev))
 924                 return 0;
 925
 926         switch (adev->asic_type) {
 927         case CHIP_NAVI10:
 928         case CHIP_NAVI14:
 929         case CHIP_NAVI12:
 930                 adev->nbio.funcs->update_medium_grain_clock_gating(adev,
 931                                 state == AMD_CG_STATE_GATE ? true : false);
 932                 adev->nbio.funcs->update_medium_grain_light_sleep(adev,
 933                                 state == AMD_CG_STATE_GATE ? true : false);
 934                 nv_update_hdp_mem_power_gating(adev,
 935                                    state == AMD_CG_STATE_GATE ? true : false);
 936                 nv_update_hdp_clock_gating(adev,
 937                                 state == AMD_CG_STATE_GATE ? true : false);
 938                 break;
 939         default:
 940                 break;
 941         }
 942         return 0;
 943 }
 944
 945 static int nv_common_set_powergating_state(void *handle,
 946                                            enum amd_powergating_state state)
 947 {
 948         /* TODO */
 949         return 0;
 950 }
 951
 952 static void nv_common_get_clockgating_state(void *handle, u32 *flags)
 953 {
 954         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 955         uint32_t tmp;
 956
 957         if (amdgpu_sriov_vf(adev))
 958                 *flags = 0;
 959
 960         adev->nbio.funcs->get_clockgating_state(adev, flags);
 961
 962         /* AMD_CG_SUPPORT_HDP_MGCG */
 963         tmp = RREG32_SOC15(HDP, 0, mmHDP_CLK_CNTL);
 964         if (!(tmp & (HDP_CLK_CNTL__IPH_MEM_CLK_SOFT_OVERRIDE_MASK |
 965                      HDP_CLK_CNTL__RC_MEM_CLK_SOFT_OVERRIDE_MASK |
 966                      HDP_CLK_CNTL__DBUS_CLK_SOFT_OVERRIDE_MASK |
 967                      HDP_CLK_CNTL__DYN_CLK_SOFT_OVERRIDE_MASK |
 968                      HDP_CLK_CNTL__XDP_REG_CLK_SOFT_OVERRIDE_MASK |
 969                      HDP_CLK_CNTL__HDP_REG_CLK_SOFT_OVERRIDE_MASK)))
 970                 *flags |= AMD_CG_SUPPORT_HDP_MGCG;
 971
 972         /* AMD_CG_SUPPORT_HDP_LS/DS/SD */
 973         tmp = RREG32_SOC15(HDP, 0, mmHDP_MEM_POWER_CTRL);
 974         if (tmp & HDP_MEM_POWER_CTRL__IPH_MEM_POWER_LS_EN_MASK)
 975                 *flags |= AMD_CG_SUPPORT_HDP_LS;
 976         else if (tmp & HDP_MEM_POWER_CTRL__IPH_MEM_POWER_DS_EN_MASK)
 977                 *flags |= AMD_CG_SUPPORT_HDP_DS;
 978         else if (tmp & HDP_MEM_POWER_CTRL__IPH_MEM_POWER_SD_EN_MASK)
 979                 *flags |= AMD_CG_SUPPORT_HDP_SD;
 980
 981         return;
 982 }
 983
 984 static const struct amd_ip_funcs nv_common_ip_funcs = {
 985         .name = "nv_common",
 986         .early_init = nv_common_early_init,
 987         .late_init = nv_common_late_init,
 988         .sw_init = nv_common_sw_init,
 989         .sw_fini = nv_common_sw_fini,
 990         .hw_init = nv_common_hw_init,
 991         .hw_fini = nv_common_hw_fini,
 992         .suspend = nv_common_suspend,
 993         .resume = nv_common_resume,
 994         .is_idle = nv_common_is_idle,
 995         .wait_for_idle = nv_common_wait_for_idle,
 996         .soft_reset = nv_common_soft_reset,
 997         .set_clockgating_state = nv_common_set_clockgating_state,
 998         .set_powergating_state = nv_common_set_powergating_state,
 999         .get_clockgating_state = nv_common_get_clockgating_state,
1000 };