drivers/gpu/drm/amd/amdgpu/psp_v11_0.c

   1 /*
   2  * Copyright 2018 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  */
  22
  23 #include <linux/firmware.h>
  24 #include <linux/module.h>
  25
  26 #include "amdgpu.h"
  27 #include "amdgpu_psp.h"
  28 #include "amdgpu_ucode.h"
  29 #include "soc15_common.h"
  30 #include "psp_v11_0.h"
  31
  32 #include "mp/mp_11_0_offset.h"
  33 #include "mp/mp_11_0_sh_mask.h"
  34 #include "gc/gc_9_0_offset.h"
  35 #include "sdma0/sdma0_4_0_offset.h"
  36 #include "nbio/nbio_7_4_offset.h"
  37
  38 #include "oss/osssys_4_0_offset.h"
  39 #include "oss/osssys_4_0_sh_mask.h"
  40
  41 MODULE_FIRMWARE("amdgpu/vega20_sos.bin");
  42 MODULE_FIRMWARE("amdgpu/vega20_asd.bin");
  43 MODULE_FIRMWARE("amdgpu/vega20_ta.bin");
  44 MODULE_FIRMWARE("amdgpu/navi10_sos.bin");
  45 MODULE_FIRMWARE("amdgpu/navi10_asd.bin");
  46 MODULE_FIRMWARE("amdgpu/navi14_sos.bin");
  47 MODULE_FIRMWARE("amdgpu/navi14_asd.bin");
  48 MODULE_FIRMWARE("amdgpu/navi12_sos.bin");
  49 MODULE_FIRMWARE("amdgpu/navi12_asd.bin");
  50 MODULE_FIRMWARE("amdgpu/arcturus_sos.bin");
  51 MODULE_FIRMWARE("amdgpu/arcturus_asd.bin");
  52 MODULE_FIRMWARE("amdgpu/arcturus_ta.bin");
  53
  54 /* address block */
  55 #define smnMP1_FIRMWARE_FLAGS           0x3010024
  56 /* navi10 reg offset define */
  57 #define mmRLC_GPM_UCODE_ADDR_NV10       0x5b61
  58 #define mmRLC_GPM_UCODE_DATA_NV10       0x5b62
  59 #define mmSDMA0_UCODE_ADDR_NV10         0x5880
  60 #define mmSDMA0_UCODE_DATA_NV10         0x5881
  61 /* memory training timeout define */
  62 #define MEM_TRAIN_SEND_MSG_TIMEOUT_US   3000000
  63
  64 static int psp_v11_0_init_microcode(struct psp_context *psp)
  65 {
  66         struct amdgpu_device *adev = psp->adev;
  67         const char *chip_name;
  68         char fw_name[30];
  69         int err = 0;
  70         const struct psp_firmware_header_v1_0 *sos_hdr;
  71         const struct psp_firmware_header_v1_1 *sos_hdr_v1_1;
  72         const struct psp_firmware_header_v1_2 *sos_hdr_v1_2;
  73         const struct psp_firmware_header_v1_0 *asd_hdr;
  74         const struct ta_firmware_header_v1_0 *ta_hdr;
  75
  76         DRM_DEBUG("\n");
  77
  78         switch (adev->asic_type) {
  79         case CHIP_VEGA20:
  80                 chip_name = "vega20";
  81                 break;
  82         case CHIP_NAVI10:
  83                 chip_name = "navi10";
  84                 break;
  85         case CHIP_NAVI14:
  86                 chip_name = "navi14";
  87                 break;
  88         case CHIP_NAVI12:
  89                 chip_name = "navi12";
  90                 break;
  91         case CHIP_ARCTURUS:
  92                 chip_name = "arcturus";
  93                 break;
  94         default:
  95                 BUG();
  96         }
  97
  98         snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_sos.bin", chip_name);
  99         err = request_firmware(&adev->psp.sos_fw, fw_name, adev->dev);
 100         if (err)
 101                 goto out;
 102
 103         err = amdgpu_ucode_validate(adev->psp.sos_fw);
 104         if (err)
 105                 goto out;
 106
 107         sos_hdr = (const struct psp_firmware_header_v1_0 *)adev->psp.sos_fw->data;
 108         amdgpu_ucode_print_psp_hdr(&sos_hdr->header);
 109
 110         switch (sos_hdr->header.header_version_major) {
 111         case 1:
 112                 adev->psp.sos_fw_version = le32_to_cpu(sos_hdr->header.ucode_version);
 113                 adev->psp.sos_feature_version = le32_to_cpu(sos_hdr->ucode_feature_version);
 114                 adev->psp.sos_bin_size = le32_to_cpu(sos_hdr->sos_size_bytes);
 115                 adev->psp.sys_bin_size = le32_to_cpu(sos_hdr->sos_offset_bytes);
 116                 adev->psp.sys_start_addr = (uint8_t *)sos_hdr +
 117                                 le32_to_cpu(sos_hdr->header.ucode_array_offset_bytes);
 118                 adev->psp.sos_start_addr = (uint8_t *)adev->psp.sys_start_addr +
 119                                 le32_to_cpu(sos_hdr->sos_offset_bytes);
 120                 if (sos_hdr->header.header_version_minor == 1) {
 121                         sos_hdr_v1_1 = (const struct psp_firmware_header_v1_1 *)adev->psp.sos_fw->data;
 122                         adev->psp.toc_bin_size = le32_to_cpu(sos_hdr_v1_1->toc_size_bytes);
 123                         adev->psp.toc_start_addr = (uint8_t *)adev->psp.sys_start_addr +
 124                                         le32_to_cpu(sos_hdr_v1_1->toc_offset_bytes);
 125                         adev->psp.kdb_bin_size = le32_to_cpu(sos_hdr_v1_1->kdb_size_bytes);
 126                         adev->psp.kdb_start_addr = (uint8_t *)adev->psp.sys_start_addr +
 127                                         le32_to_cpu(sos_hdr_v1_1->kdb_offset_bytes);
 128                 }
 129                 if (sos_hdr->header.header_version_minor == 2) {
 130                         sos_hdr_v1_2 = (const struct psp_firmware_header_v1_2 *)adev->psp.sos_fw->data;
 131                         adev->psp.kdb_bin_size = le32_to_cpu(sos_hdr_v1_2->kdb_size_bytes);
 132                         adev->psp.kdb_start_addr = (uint8_t *)adev->psp.sys_start_addr +
 133                                                     le32_to_cpu(sos_hdr_v1_2->kdb_offset_bytes);
 134                 }
 135                 break;
 136         default:
 137                 dev_err(adev->dev,
 138                         "Unsupported psp sos firmware\n");
 139                 err = -EINVAL;
 140                 goto out;
 141         }
 142
 143         snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_asd.bin", chip_name);
 144         err = request_firmware(&adev->psp.asd_fw, fw_name, adev->dev);
 145         if (err)
 146                 goto out1;
 147
 148         err = amdgpu_ucode_validate(adev->psp.asd_fw);
 149         if (err)
 150                 goto out1;
 151
 152         asd_hdr = (const struct psp_firmware_header_v1_0 *)adev->psp.asd_fw->data;
 153         adev->psp.asd_fw_version = le32_to_cpu(asd_hdr->header.ucode_version);
 154         adev->psp.asd_feature_version = le32_to_cpu(asd_hdr->ucode_feature_version);
 155         adev->psp.asd_ucode_size = le32_to_cpu(asd_hdr->header.ucode_size_bytes);
 156         adev->psp.asd_start_addr = (uint8_t *)asd_hdr +
 157                                 le32_to_cpu(asd_hdr->header.ucode_array_offset_bytes);
 158
 159         switch (adev->asic_type) {
 160         case CHIP_VEGA20:
 161         case CHIP_ARCTURUS:
 162                 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_ta.bin", chip_name);
 163                 err = request_firmware(&adev->psp.ta_fw, fw_name, adev->dev);
 164                 if (err) {
 165                         release_firmware(adev->psp.ta_fw);
 166                         adev->psp.ta_fw = NULL;
 167                         dev_info(adev->dev,
 168                                  "psp v11.0: Failed to load firmware \"%s\"\n", fw_name);
 169                 } else {
 170                         err = amdgpu_ucode_validate(adev->psp.ta_fw);
 171                         if (err)
 172                                 goto out2;
 173
 174                         ta_hdr = (const struct ta_firmware_header_v1_0 *)adev->psp.ta_fw->data;
 175                         adev->psp.ta_xgmi_ucode_version = le32_to_cpu(ta_hdr->ta_xgmi_ucode_version);
 176                         adev->psp.ta_xgmi_ucode_size = le32_to_cpu(ta_hdr->ta_xgmi_size_bytes);
 177                         adev->psp.ta_xgmi_start_addr = (uint8_t *)ta_hdr +
 178                                 le32_to_cpu(ta_hdr->header.ucode_array_offset_bytes);
 179                         adev->psp.ta_fw_version = le32_to_cpu(ta_hdr->header.ucode_version);
 180                         adev->psp.ta_ras_ucode_version = le32_to_cpu(ta_hdr->ta_ras_ucode_version);
 181                         adev->psp.ta_ras_ucode_size = le32_to_cpu(ta_hdr->ta_ras_size_bytes);
 182                         adev->psp.ta_ras_start_addr = (uint8_t *)adev->psp.ta_xgmi_start_addr +
 183                                 le32_to_cpu(ta_hdr->ta_ras_offset_bytes);
 184                 }
 185                 break;
 186         case CHIP_NAVI10:
 187         case CHIP_NAVI14:
 188         case CHIP_NAVI12:
 189                 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_ta.bin", chip_name);
 190                 err = request_firmware(&adev->psp.ta_fw, fw_name, adev->dev);
 191                 if (err) {
 192                         release_firmware(adev->psp.ta_fw);
 193                         adev->psp.ta_fw = NULL;
 194                         dev_info(adev->dev,
 195                                  "psp v11.0: Failed to load firmware \"%s\"\n", fw_name);
 196                 } else {
 197                         err = amdgpu_ucode_validate(adev->psp.ta_fw);
 198                         if (err)
 199                                 goto out2;
 200
 201                         ta_hdr = (const struct ta_firmware_header_v1_0 *)adev->psp.ta_fw->data;
 202                         adev->psp.ta_hdcp_ucode_version = le32_to_cpu(ta_hdr->ta_hdcp_ucode_version);
 203                         adev->psp.ta_hdcp_ucode_size = le32_to_cpu(ta_hdr->ta_hdcp_size_bytes);
 204                         adev->psp.ta_hdcp_start_addr = (uint8_t *)ta_hdr +
 205                                 le32_to_cpu(ta_hdr->header.ucode_array_offset_bytes);
 206
 207                         adev->psp.ta_fw_version = le32_to_cpu(ta_hdr->header.ucode_version);
 208
 209                         adev->psp.ta_dtm_ucode_version = le32_to_cpu(ta_hdr->ta_dtm_ucode_version);
 210                         adev->psp.ta_dtm_ucode_size = le32_to_cpu(ta_hdr->ta_dtm_size_bytes);
 211                         adev->psp.ta_dtm_start_addr = (uint8_t *)adev->psp.ta_hdcp_start_addr +
 212                                 le32_to_cpu(ta_hdr->ta_dtm_offset_bytes);
 213                 }
 214                 break;
 215         default:
 216                 BUG();
 217         }
 218
 219         return 0;
 220
 221 out2:
 222         release_firmware(adev->psp.ta_fw);
 223         adev->psp.ta_fw = NULL;
 224 out1:
 225         release_firmware(adev->psp.asd_fw);
 226         adev->psp.asd_fw = NULL;
 227 out:
 228         dev_err(adev->dev,
 229                 "psp v11.0: Failed to load firmware \"%s\"\n", fw_name);
 230         release_firmware(adev->psp.sos_fw);
 231         adev->psp.sos_fw = NULL;
 232
 233         return err;
 234 }
 235
 236 int psp_v11_0_wait_for_bootloader(struct psp_context *psp)
 237 {
 238         struct amdgpu_device *adev = psp->adev;
 239
 240         int ret;
 241         int retry_loop;
 242
 243         for (retry_loop = 0; retry_loop < 10; retry_loop++) {
 244                 /* Wait for bootloader to signify that is
 245                     ready having bit 31 of C2PMSG_35 set to 1 */
 246                 ret = psp_wait_for(psp,
 247                                    SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_35),
 248                                    0x80000000,
 249                                    0x80000000,
 250                                    false);
 251
 252                 if (ret == 0)
 253                         return 0;
 254         }
 255
 256         return ret;
 257 }
 258
 259 static bool psp_v11_0_is_sos_alive(struct psp_context *psp)
 260 {
 261         struct amdgpu_device *adev = psp->adev;
 262         uint32_t sol_reg;
 263
 264         sol_reg = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_81);
 265
 266         return sol_reg != 0x0;
 267 }
 268
 269 static int psp_v11_0_bootloader_load_kdb(struct psp_context *psp)
 270 {
 271         int ret;
 272         uint32_t psp_gfxdrv_command_reg = 0;
 273         struct amdgpu_device *adev = psp->adev;
 274
 275         /* Check tOS sign of life register to confirm sys driver and sOS
 276          * are already been loaded.
 277          */
 278         if (psp_v11_0_is_sos_alive(psp)) {
 279                 psp->sos_fw_version = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_58);
 280                 dev_info(adev->dev, "sos fw version = 0x%x.\n", psp->sos_fw_version);
 281                 return 0;
 282         }
 283
 284         ret = psp_v11_0_wait_for_bootloader(psp);
 285         if (ret)
 286                 return ret;
 287
 288         memset(psp->fw_pri_buf, 0, PSP_1_MEG);
 289
 290         /* Copy PSP KDB binary to memory */
 291         memcpy(psp->fw_pri_buf, psp->kdb_start_addr, psp->kdb_bin_size);
 292
 293         /* Provide the PSP KDB to bootloader */
 294         WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_36,
 295                (uint32_t)(psp->fw_pri_mc_addr >> 20));
 296         psp_gfxdrv_command_reg = PSP_BL__LOAD_KEY_DATABASE;
 297         WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_35,
 298                psp_gfxdrv_command_reg);
 299
 300         ret = psp_v11_0_wait_for_bootloader(psp);
 301
 302         return ret;
 303 }
 304
 305 static int psp_v11_0_bootloader_load_sysdrv(struct psp_context *psp)
 306 {
 307         int ret;
 308         uint32_t psp_gfxdrv_command_reg = 0;
 309         struct amdgpu_device *adev = psp->adev;
 310
 311         /* Check sOS sign of life register to confirm sys driver and sOS
 312          * are already been loaded.
 313          */
 314         if (psp_v11_0_is_sos_alive(psp)) {
 315                 psp->sos_fw_version = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_58);
 316                 dev_info(adev->dev, "sos fw version = 0x%x.\n", psp->sos_fw_version);
 317                 return 0;
 318         }
 319
 320         ret = psp_v11_0_wait_for_bootloader(psp);
 321         if (ret)
 322                 return ret;
 323
 324         memset(psp->fw_pri_buf, 0, PSP_1_MEG);
 325
 326         /* Copy PSP System Driver binary to memory */
 327         memcpy(psp->fw_pri_buf, psp->sys_start_addr, psp->sys_bin_size);
 328
 329         /* Provide the sys driver to bootloader */
 330         WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_36,
 331                (uint32_t)(psp->fw_pri_mc_addr >> 20));
 332         psp_gfxdrv_command_reg = PSP_BL__LOAD_SYSDRV;
 333         WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_35,
 334                psp_gfxdrv_command_reg);
 335
 336         /* there might be handshake issue with hardware which needs delay */
 337         mdelay(20);
 338
 339         ret = psp_v11_0_wait_for_bootloader(psp);
 340
 341         return ret;
 342 }
 343
 344 static int psp_v11_0_bootloader_load_sos(struct psp_context *psp)
 345 {
 346         int ret;
 347         unsigned int psp_gfxdrv_command_reg = 0;
 348         struct amdgpu_device *adev = psp->adev;
 349
 350         /* Check sOS sign of life register to confirm sys driver and sOS
 351          * are already been loaded.
 352          */
 353         if (psp_v11_0_is_sos_alive(psp))
 354                 return 0;
 355
 356         ret = psp_v11_0_wait_for_bootloader(psp);
 357         if (ret)
 358                 return ret;
 359
 360         memset(psp->fw_pri_buf, 0, PSP_1_MEG);
 361
 362         /* Copy Secure OS binary to PSP memory */
 363         memcpy(psp->fw_pri_buf, psp->sos_start_addr, psp->sos_bin_size);
 364
 365         /* Provide the PSP secure OS to bootloader */
 366         WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_36,
 367                (uint32_t)(psp->fw_pri_mc_addr >> 20));
 368         psp_gfxdrv_command_reg = PSP_BL__LOAD_SOSDRV;
 369         WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_35,
 370                psp_gfxdrv_command_reg);
 371
 372         /* there might be handshake issue with hardware which needs delay */
 373         mdelay(20);
 374         ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_81),
 375                            RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_81),
 376                            0, true);
 377
 378         return ret;
 379 }
 380
 381 static void psp_v11_0_reroute_ih(struct psp_context *psp)
 382 {
 383         struct amdgpu_device *adev = psp->adev;
 384         uint32_t tmp;
 385
 386         /* Change IH ring for VMC */
 387         tmp = REG_SET_FIELD(0, IH_CLIENT_CFG_DATA, CREDIT_RETURN_ADDR, 0x1244b);
 388         tmp = REG_SET_FIELD(tmp, IH_CLIENT_CFG_DATA, CLIENT_TYPE, 1);
 389         tmp = REG_SET_FIELD(tmp, IH_CLIENT_CFG_DATA, RING_ID, 1);
 390
 391         WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_69, 3);
 392         WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_70, tmp);
 393         WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_64, GFX_CTRL_CMD_ID_GBR_IH_SET);
 394
 395         mdelay(20);
 396         psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64),
 397                      0x80000000, 0x8000FFFF, false);
 398
 399         /* Change IH ring for UMC */
 400         tmp = REG_SET_FIELD(0, IH_CLIENT_CFG_DATA, CREDIT_RETURN_ADDR, 0x1216b);
 401         tmp = REG_SET_FIELD(tmp, IH_CLIENT_CFG_DATA, RING_ID, 1);
 402
 403         WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_69, 4);
 404         WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_70, tmp);
 405         WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_64, GFX_CTRL_CMD_ID_GBR_IH_SET);
 406
 407         mdelay(20);
 408         psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64),
 409                      0x80000000, 0x8000FFFF, false);
 410 }
 411
 412 static int psp_v11_0_ring_init(struct psp_context *psp,
 413                               enum psp_ring_type ring_type)
 414 {
 415         int ret = 0;
 416         struct psp_ring *ring;
 417         struct amdgpu_device *adev = psp->adev;
 418
 419         psp_v11_0_reroute_ih(psp);
 420
 421         ring = &psp->km_ring;
 422
 423         ring->ring_type = ring_type;
 424
 425         /* allocate 4k Page of Local Frame Buffer memory for ring */
 426         ring->ring_size = 0x1000;
 427         ret = amdgpu_bo_create_kernel(adev, ring->ring_size, PAGE_SIZE,
 428                                       AMDGPU_GEM_DOMAIN_VRAM,
 429                                       &adev->firmware.rbuf,
 430                                       &ring->ring_mem_mc_addr,
 431                                       (void **)&ring->ring_mem);
 432         if (ret) {
 433                 ring->ring_size = 0;
 434                 return ret;
 435         }
 436
 437         return 0;
 438 }
 439
 440 static bool psp_v11_0_support_vmr_ring(struct psp_context *psp)
 441 {
 442         if (amdgpu_sriov_vf(psp->adev) && psp->sos_fw_version > 0x80045)
 443                 return true;
 444         return false;
 445 }
 446
 447 static int psp_v11_0_ring_stop(struct psp_context *psp,
 448                               enum psp_ring_type ring_type)
 449 {
 450         int ret = 0;
 451         struct amdgpu_device *adev = psp->adev;
 452
 453         /* Write the ring destroy command*/
 454         if (psp_v11_0_support_vmr_ring(psp))
 455                 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_101,
 456                                      GFX_CTRL_CMD_ID_DESTROY_GPCOM_RING);
 457         else
 458                 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_64,
 459                                      GFX_CTRL_CMD_ID_DESTROY_RINGS);
 460
 461         /* there might be handshake issue with hardware which needs delay */
 462         mdelay(20);
 463
 464         /* Wait for response flag (bit 31) */
 465         if (psp_v11_0_support_vmr_ring(psp))
 466                 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_101),
 467                                    0x80000000, 0x80000000, false);
 468         else
 469                 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64),
 470                                    0x80000000, 0x80000000, false);
 471
 472         return ret;
 473 }
 474
 475 static int psp_v11_0_ring_create(struct psp_context *psp,
 476                                 enum psp_ring_type ring_type)
 477 {
 478         int ret = 0;
 479         unsigned int psp_ring_reg = 0;
 480         struct psp_ring *ring = &psp->km_ring;
 481         struct amdgpu_device *adev = psp->adev;
 482
 483         if (psp_v11_0_support_vmr_ring(psp)) {
 484                 ret = psp_v11_0_ring_stop(psp, ring_type);
 485                 if (ret) {
 486                         DRM_ERROR("psp_v11_0_ring_stop_sriov failed!\n");
 487                         return ret;
 488                 }
 489
 490                 /* Write low address of the ring to C2PMSG_102 */
 491                 psp_ring_reg = lower_32_bits(ring->ring_mem_mc_addr);
 492                 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_102, psp_ring_reg);
 493                 /* Write high address of the ring to C2PMSG_103 */
 494                 psp_ring_reg = upper_32_bits(ring->ring_mem_mc_addr);
 495                 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_103, psp_ring_reg);
 496
 497                 /* Write the ring initialization command to C2PMSG_101 */
 498                 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_101,
 499                                              GFX_CTRL_CMD_ID_INIT_GPCOM_RING);
 500
 501                 /* there might be handshake issue with hardware which needs delay */
 502                 mdelay(20);
 503
 504                 /* Wait for response flag (bit 31) in C2PMSG_101 */
 505                 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_101),
 506                                    0x80000000, 0x8000FFFF, false);
 507
 508         } else {
 509                 /* Wait for sOS ready for ring creation */
 510                 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64),
 511                                    0x80000000, 0x80000000, false);
 512                 if (ret) {
 513                         DRM_ERROR("Failed to wait for sOS ready for ring creation\n");
 514                         return ret;
 515                 }
 516
 517                 /* Write low address of the ring to C2PMSG_69 */
 518                 psp_ring_reg = lower_32_bits(ring->ring_mem_mc_addr);
 519                 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_69, psp_ring_reg);
 520                 /* Write high address of the ring to C2PMSG_70 */
 521                 psp_ring_reg = upper_32_bits(ring->ring_mem_mc_addr);
 522                 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_70, psp_ring_reg);
 523                 /* Write size of ring to C2PMSG_71 */
 524                 psp_ring_reg = ring->ring_size;
 525                 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_71, psp_ring_reg);
 526                 /* Write the ring initialization command to C2PMSG_64 */
 527                 psp_ring_reg = ring_type;
 528                 psp_ring_reg = psp_ring_reg << 16;
 529                 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_64, psp_ring_reg);
 530
 531                 /* there might be handshake issue with hardware which needs delay */
 532                 mdelay(20);
 533
 534                 /* Wait for response flag (bit 31) in C2PMSG_64 */
 535                 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64),
 536                                    0x80000000, 0x8000FFFF, false);
 537         }
 538
 539         return ret;
 540 }
 541
 542
 543 static int psp_v11_0_ring_destroy(struct psp_context *psp,
 544                                  enum psp_ring_type ring_type)
 545 {
 546         int ret = 0;
 547         struct psp_ring *ring = &psp->km_ring;
 548         struct amdgpu_device *adev = psp->adev;
 549
 550         ret = psp_v11_0_ring_stop(psp, ring_type);
 551         if (ret)
 552                 DRM_ERROR("Fail to stop psp ring\n");
 553
 554         amdgpu_bo_free_kernel(&adev->firmware.rbuf,
 555                               &ring->ring_mem_mc_addr,
 556                               (void **)&ring->ring_mem);
 557
 558         return ret;
 559 }
 560
 561 static int
 562 psp_v11_0_sram_map(struct amdgpu_device *adev,
 563                   unsigned int *sram_offset, unsigned int *sram_addr_reg_offset,
 564                   unsigned int *sram_data_reg_offset,
 565                   enum AMDGPU_UCODE_ID ucode_id)
 566 {
 567         int ret = 0;
 568
 569         switch (ucode_id) {
 570 /* TODO: needs to confirm */
 571 #if 0
 572         case AMDGPU_UCODE_ID_SMC:
 573                 *sram_offset = 0;
 574                 *sram_addr_reg_offset = 0;
 575                 *sram_data_reg_offset = 0;
 576                 break;
 577 #endif
 578
 579         case AMDGPU_UCODE_ID_CP_CE:
 580                 *sram_offset = 0x0;
 581                 *sram_addr_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_CE_UCODE_ADDR);
 582                 *sram_data_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_CE_UCODE_DATA);
 583                 break;
 584
 585         case AMDGPU_UCODE_ID_CP_PFP:
 586                 *sram_offset = 0x0;
 587                 *sram_addr_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_PFP_UCODE_ADDR);
 588                 *sram_data_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_PFP_UCODE_DATA);
 589                 break;
 590
 591         case AMDGPU_UCODE_ID_CP_ME:
 592                 *sram_offset = 0x0;
 593                 *sram_addr_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_HYP_ME_UCODE_ADDR);
 594                 *sram_data_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_HYP_ME_UCODE_DATA);
 595                 break;
 596
 597         case AMDGPU_UCODE_ID_CP_MEC1:
 598                 *sram_offset = 0x10000;
 599                 *sram_addr_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_MEC_ME1_UCODE_ADDR);
 600                 *sram_data_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_MEC_ME1_UCODE_DATA);
 601                 break;
 602
 603         case AMDGPU_UCODE_ID_CP_MEC2:
 604                 *sram_offset = 0x10000;
 605                 *sram_addr_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_HYP_MEC2_UCODE_ADDR);
 606                 *sram_data_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_HYP_MEC2_UCODE_DATA);
 607                 break;
 608
 609         case AMDGPU_UCODE_ID_RLC_G:
 610                 *sram_offset = 0x2000;
 611                 if (adev->asic_type < CHIP_NAVI10) {
 612                         *sram_addr_reg_offset = SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_UCODE_ADDR);
 613                         *sram_data_reg_offset = SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_UCODE_DATA);
 614                 } else {
 615                         *sram_addr_reg_offset = adev->reg_offset[GC_HWIP][0][1] + mmRLC_GPM_UCODE_ADDR_NV10;
 616                         *sram_data_reg_offset = adev->reg_offset[GC_HWIP][0][1] + mmRLC_GPM_UCODE_DATA_NV10;
 617                 }
 618                 break;
 619
 620         case AMDGPU_UCODE_ID_SDMA0:
 621                 *sram_offset = 0x0;
 622                 if (adev->asic_type < CHIP_NAVI10) {
 623                         *sram_addr_reg_offset = SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_UCODE_ADDR);
 624                         *sram_data_reg_offset = SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_UCODE_DATA);
 625                 } else {
 626                         *sram_addr_reg_offset = adev->reg_offset[GC_HWIP][0][1] + mmSDMA0_UCODE_ADDR_NV10;
 627                         *sram_data_reg_offset = adev->reg_offset[GC_HWIP][0][1] + mmSDMA0_UCODE_DATA_NV10;
 628                 }
 629                 break;
 630
 631 /* TODO: needs to confirm */
 632 #if 0
 633         case AMDGPU_UCODE_ID_SDMA1:
 634                 *sram_offset = ;
 635                 *sram_addr_reg_offset = ;
 636                 break;
 637
 638         case AMDGPU_UCODE_ID_UVD:
 639                 *sram_offset = ;
 640                 *sram_addr_reg_offset = ;
 641                 break;
 642
 643         case AMDGPU_UCODE_ID_VCE:
 644                 *sram_offset = ;
 645                 *sram_addr_reg_offset = ;
 646                 break;
 647 #endif
 648
 649         case AMDGPU_UCODE_ID_MAXIMUM:
 650         default:
 651                 ret = -EINVAL;
 652                 break;
 653         }
 654
 655         return ret;
 656 }
 657
 658 static bool psp_v11_0_compare_sram_data(struct psp_context *psp,
 659                                        struct amdgpu_firmware_info *ucode,
 660                                        enum AMDGPU_UCODE_ID ucode_type)
 661 {
 662         int err = 0;
 663         unsigned int fw_sram_reg_val = 0;
 664         unsigned int fw_sram_addr_reg_offset = 0;
 665         unsigned int fw_sram_data_reg_offset = 0;
 666         unsigned int ucode_size;
 667         uint32_t *ucode_mem = NULL;
 668         struct amdgpu_device *adev = psp->adev;
 669
 670         err = psp_v11_0_sram_map(adev, &fw_sram_reg_val, &fw_sram_addr_reg_offset,
 671                                 &fw_sram_data_reg_offset, ucode_type);
 672         if (err)
 673                 return false;
 674
 675         WREG32(fw_sram_addr_reg_offset, fw_sram_reg_val);
 676
 677         ucode_size = ucode->ucode_size;
 678         ucode_mem = (uint32_t *)ucode->kaddr;
 679         while (ucode_size) {
 680                 fw_sram_reg_val = RREG32(fw_sram_data_reg_offset);
 681
 682                 if (*ucode_mem != fw_sram_reg_val)
 683                         return false;
 684
 685                 ucode_mem++;
 686                 /* 4 bytes */
 687                 ucode_size -= 4;
 688         }
 689
 690         return true;
 691 }
 692
 693 static int psp_v11_0_mode1_reset(struct psp_context *psp)
 694 {
 695         int ret;
 696         uint32_t offset;
 697         struct amdgpu_device *adev = psp->adev;
 698
 699         offset = SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64);
 700
 701         ret = psp_wait_for(psp, offset, 0x80000000, 0x8000FFFF, false);
 702
 703         if (ret) {
 704                 DRM_INFO("psp is not working correctly before mode1 reset!\n");
 705                 return -EINVAL;
 706         }
 707
 708         /*send the mode 1 reset command*/
 709         WREG32(offset, GFX_CTRL_CMD_ID_MODE1_RST);
 710
 711         msleep(500);
 712
 713         offset = SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_33);
 714
 715         ret = psp_wait_for(psp, offset, 0x80000000, 0x80000000, false);
 716
 717         if (ret) {
 718                 DRM_INFO("psp mode 1 reset failed!\n");
 719                 return -EINVAL;
 720         }
 721
 722         DRM_INFO("psp mode1 reset succeed \n");
 723
 724         return 0;
 725 }
 726
 727 /* TODO: Fill in follow functions once PSP firmware interface for XGMI is ready.
 728  * For now, return success and hack the hive_id so high level code can
 729  * start testing
 730  */
 731 static int psp_v11_0_xgmi_get_topology_info(struct psp_context *psp,
 732         int number_devices, struct psp_xgmi_topology_info *topology)
 733 {
 734         struct ta_xgmi_shared_memory *xgmi_cmd;
 735         struct ta_xgmi_cmd_get_topology_info_input *topology_info_input;
 736         struct ta_xgmi_cmd_get_topology_info_output *topology_info_output;
 737         int i;
 738         int ret;
 739
 740         if (!topology || topology->num_nodes > TA_XGMI__MAX_CONNECTED_NODES)
 741                 return -EINVAL;
 742
 743         xgmi_cmd = (struct ta_xgmi_shared_memory*)psp->xgmi_context.xgmi_shared_buf;
 744         memset(xgmi_cmd, 0, sizeof(struct ta_xgmi_shared_memory));
 745
 746         /* Fill in the shared memory with topology information as input */
 747         topology_info_input = &xgmi_cmd->xgmi_in_message.get_topology_info;
 748         xgmi_cmd->cmd_id = TA_COMMAND_XGMI__GET_GET_TOPOLOGY_INFO;
 749         topology_info_input->num_nodes = number_devices;
 750
 751         for (i = 0; i < topology_info_input->num_nodes; i++) {
 752                 topology_info_input->nodes[i].node_id = topology->nodes[i].node_id;
 753                 topology_info_input->nodes[i].num_hops = topology->nodes[i].num_hops;
 754                 topology_info_input->nodes[i].is_sharing_enabled = topology->nodes[i].is_sharing_enabled;
 755                 topology_info_input->nodes[i].sdma_engine = topology->nodes[i].sdma_engine;
 756         }
 757
 758         /* Invoke xgmi ta to get the topology information */
 759         ret = psp_xgmi_invoke(psp, TA_COMMAND_XGMI__GET_GET_TOPOLOGY_INFO);
 760         if (ret)
 761                 return ret;
 762
 763         /* Read the output topology information from the shared memory */
 764         topology_info_output = &xgmi_cmd->xgmi_out_message.get_topology_info;
 765         topology->num_nodes = xgmi_cmd->xgmi_out_message.get_topology_info.num_nodes;
 766         for (i = 0; i < topology->num_nodes; i++) {
 767                 topology->nodes[i].node_id = topology_info_output->nodes[i].node_id;
 768                 topology->nodes[i].num_hops = topology_info_output->nodes[i].num_hops;
 769                 topology->nodes[i].is_sharing_enabled = topology_info_output->nodes[i].is_sharing_enabled;
 770                 topology->nodes[i].sdma_engine = topology_info_output->nodes[i].sdma_engine;
 771         }
 772
 773         return 0;
 774 }
 775
 776 static int psp_v11_0_xgmi_set_topology_info(struct psp_context *psp,
 777         int number_devices, struct psp_xgmi_topology_info *topology)
 778 {
 779         struct ta_xgmi_shared_memory *xgmi_cmd;
 780         struct ta_xgmi_cmd_get_topology_info_input *topology_info_input;
 781         int i;
 782
 783         if (!topology || topology->num_nodes > TA_XGMI__MAX_CONNECTED_NODES)
 784                 return -EINVAL;
 785
 786         xgmi_cmd = (struct ta_xgmi_shared_memory*)psp->xgmi_context.xgmi_shared_buf;
 787         memset(xgmi_cmd, 0, sizeof(struct ta_xgmi_shared_memory));
 788
 789         topology_info_input = &xgmi_cmd->xgmi_in_message.get_topology_info;
 790         xgmi_cmd->cmd_id = TA_COMMAND_XGMI__SET_TOPOLOGY_INFO;
 791         topology_info_input->num_nodes = number_devices;
 792
 793         for (i = 0; i < topology_info_input->num_nodes; i++) {
 794                 topology_info_input->nodes[i].node_id = topology->nodes[i].node_id;
 795                 topology_info_input->nodes[i].num_hops = topology->nodes[i].num_hops;
 796                 topology_info_input->nodes[i].is_sharing_enabled = 1;
 797                 topology_info_input->nodes[i].sdma_engine = topology->nodes[i].sdma_engine;
 798         }
 799
 800         /* Invoke xgmi ta to set topology information */
 801         return psp_xgmi_invoke(psp, TA_COMMAND_XGMI__SET_TOPOLOGY_INFO);
 802 }
 803
 804 static int psp_v11_0_xgmi_get_hive_id(struct psp_context *psp, uint64_t *hive_id)
 805 {
 806         struct ta_xgmi_shared_memory *xgmi_cmd;
 807         int ret;
 808
 809         xgmi_cmd = (struct ta_xgmi_shared_memory*)psp->xgmi_context.xgmi_shared_buf;
 810         memset(xgmi_cmd, 0, sizeof(struct ta_xgmi_shared_memory));
 811
 812         xgmi_cmd->cmd_id = TA_COMMAND_XGMI__GET_HIVE_ID;
 813
 814         /* Invoke xgmi ta to get hive id */
 815         ret = psp_xgmi_invoke(psp, xgmi_cmd->cmd_id);
 816         if (ret)
 817                 return ret;
 818
 819         *hive_id = xgmi_cmd->xgmi_out_message.get_hive_id.hive_id;
 820
 821         return 0;
 822 }
 823
 824 static int psp_v11_0_xgmi_get_node_id(struct psp_context *psp, uint64_t *node_id)
 825 {
 826         struct ta_xgmi_shared_memory *xgmi_cmd;
 827         int ret;
 828
 829         xgmi_cmd = (struct ta_xgmi_shared_memory*)psp->xgmi_context.xgmi_shared_buf;
 830         memset(xgmi_cmd, 0, sizeof(struct ta_xgmi_shared_memory));
 831
 832         xgmi_cmd->cmd_id = TA_COMMAND_XGMI__GET_NODE_ID;
 833
 834         /* Invoke xgmi ta to get the node id */
 835         ret = psp_xgmi_invoke(psp, xgmi_cmd->cmd_id);
 836         if (ret)
 837                 return ret;
 838
 839         *node_id = xgmi_cmd->xgmi_out_message.get_node_id.node_id;
 840
 841         return 0;
 842 }
 843
 844 static int psp_v11_0_ras_trigger_error(struct psp_context *psp,
 845                 struct ta_ras_trigger_error_input *info)
 846 {
 847         struct ta_ras_shared_memory *ras_cmd;
 848         int ret;
 849
 850         if (!psp->ras.ras_initialized)
 851                 return -EINVAL;
 852
 853         ras_cmd = (struct ta_ras_shared_memory *)psp->ras.ras_shared_buf;
 854         memset(ras_cmd, 0, sizeof(struct ta_ras_shared_memory));
 855
 856         ras_cmd->cmd_id = TA_RAS_COMMAND__TRIGGER_ERROR;
 857         ras_cmd->ras_in_message.trigger_error = *info;
 858
 859         ret = psp_ras_invoke(psp, ras_cmd->cmd_id);
 860         if (ret)
 861                 return -EINVAL;
 862
 863         return ras_cmd->ras_status;
 864 }
 865
 866 static int psp_v11_0_ras_cure_posion(struct psp_context *psp, uint64_t *mode_ptr)
 867 {
 868 #if 0
 869         // not support yet.
 870         struct ta_ras_shared_memory *ras_cmd;
 871         int ret;
 872
 873         if (!psp->ras.ras_initialized)
 874                 return -EINVAL;
 875
 876         ras_cmd = (struct ta_ras_shared_memory *)psp->ras.ras_shared_buf;
 877         memset(ras_cmd, 0, sizeof(struct ta_ras_shared_memory));
 878
 879         ras_cmd->cmd_id = TA_RAS_COMMAND__CURE_POISON;
 880         ras_cmd->ras_in_message.cure_poison.mode_ptr = mode_ptr;
 881
 882         ret = psp_ras_invoke(psp, ras_cmd->cmd_id);
 883         if (ret)
 884                 return -EINVAL;
 885
 886         return ras_cmd->ras_status;
 887 #else
 888         return -EINVAL;
 889 #endif
 890 }
 891
 892 static int psp_v11_0_rlc_autoload_start(struct psp_context *psp)
 893 {
 894         return psp_rlc_autoload_start(psp);
 895 }
 896
 897 static int psp_v11_0_memory_training_send_msg(struct psp_context *psp, int msg)
 898 {
 899         int ret;
 900         int i;
 901         uint32_t data_32;
 902         int max_wait;
 903         struct amdgpu_device *adev = psp->adev;
 904
 905         data_32 = (psp->mem_train_ctx.c2p_train_data_offset >> 20);
 906         WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_36, data_32);
 907         WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_35, msg);
 908
 909         max_wait = MEM_TRAIN_SEND_MSG_TIMEOUT_US / adev->usec_timeout;
 910         for (i = 0; i < max_wait; i++) {
 911                 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_35),
 912                                    0x80000000, 0x80000000, false);
 913                 if (ret == 0)
 914                         break;
 915         }
 916         if (i < max_wait)
 917                 ret = 0;
 918         else
 919                 ret = -ETIME;
 920
 921         DRM_DEBUG("training %s %s, cost %d @ %d ms\n",
 922                   (msg == PSP_BL__DRAM_SHORT_TRAIN) ? "short" : "long",
 923                   (ret == 0) ? "succeed" : "failed",
 924                   i, adev->usec_timeout/1000);
 925         return ret;
 926 }
 927
 928 static void psp_v11_0_memory_training_fini(struct psp_context *psp)
 929 {
 930         struct psp_memory_training_context *ctx = &psp->mem_train_ctx;
 931
 932         ctx->init = PSP_MEM_TRAIN_NOT_SUPPORT;
 933         kfree(ctx->sys_cache);
 934         ctx->sys_cache = NULL;
 935 }
 936
 937 static int psp_v11_0_memory_training_init(struct psp_context *psp)
 938 {
 939         int ret;
 940         struct psp_memory_training_context *ctx = &psp->mem_train_ctx;
 941
 942         if (ctx->init != PSP_MEM_TRAIN_RESERVE_SUCCESS) {
 943                 DRM_DEBUG("memory training is not supported!\n");
 944                 return 0;
 945         }
 946
 947         ctx->sys_cache = kzalloc(ctx->train_data_size, GFP_KERNEL);
 948         if (ctx->sys_cache == NULL) {
 949                 DRM_ERROR("alloc mem_train_ctx.sys_cache failed!\n");
 950                 ret = -ENOMEM;
 951                 goto Err_out;
 952         }
 953
 954         DRM_DEBUG("train_data_size:%llx,p2c_train_data_offset:%llx,c2p_train_data_offset:%llx.\n",
 955                   ctx->train_data_size,
 956                   ctx->p2c_train_data_offset,
 957                   ctx->c2p_train_data_offset);
 958         ctx->init = PSP_MEM_TRAIN_INIT_SUCCESS;
 959         return 0;
 960
 961 Err_out:
 962         psp_v11_0_memory_training_fini(psp);
 963         return ret;
 964 }
 965
 966 /*
 967  * save and restore proces
 968  */
 969 static int psp_v11_0_memory_training(struct psp_context *psp, uint32_t ops)
 970 {
 971         int ret;
 972         uint32_t p2c_header[4];
 973         struct psp_memory_training_context *ctx = &psp->mem_train_ctx;
 974         uint32_t *pcache = (uint32_t*)ctx->sys_cache;
 975
 976         if (ctx->init == PSP_MEM_TRAIN_NOT_SUPPORT) {
 977                 DRM_DEBUG("Memory training is not supported.\n");
 978                 return 0;
 979         } else if (ctx->init != PSP_MEM_TRAIN_INIT_SUCCESS) {
 980                 DRM_ERROR("Memory training initialization failure.\n");
 981                 return -EINVAL;
 982         }
 983
 984         if (psp_v11_0_is_sos_alive(psp)) {
 985                 DRM_DEBUG("SOS is alive, skip memory training.\n");
 986                 return 0;
 987         }
 988
 989         amdgpu_device_vram_access(psp->adev, ctx->p2c_train_data_offset, p2c_header, sizeof(p2c_header), false);
 990         DRM_DEBUG("sys_cache[%08x,%08x,%08x,%08x] p2c_header[%08x,%08x,%08x,%08x]\n",
 991                   pcache[0], pcache[1], pcache[2], pcache[3],
 992                   p2c_header[0], p2c_header[1], p2c_header[2], p2c_header[3]);
 993
 994         if (ops & PSP_MEM_TRAIN_SEND_SHORT_MSG) {
 995                 DRM_DEBUG("Short training depends on restore.\n");
 996                 ops |= PSP_MEM_TRAIN_RESTORE;
 997         }
 998
 999         if ((ops & PSP_MEM_TRAIN_RESTORE) &&
1000             pcache[0] != MEM_TRAIN_SYSTEM_SIGNATURE) {
1001                 DRM_DEBUG("sys_cache[0] is invalid, restore depends on save.\n");
1002                 ops |= PSP_MEM_TRAIN_SAVE;
1003         }
1004
1005         if (p2c_header[0] == MEM_TRAIN_SYSTEM_SIGNATURE &&
1006             !(pcache[0] == MEM_TRAIN_SYSTEM_SIGNATURE &&
1007               pcache[3] == p2c_header[3])) {
1008                 DRM_DEBUG("sys_cache is invalid or out-of-date, need save training data to sys_cache.\n");
1009                 ops |= PSP_MEM_TRAIN_SAVE;
1010         }
1011
1012         if ((ops & PSP_MEM_TRAIN_SAVE) &&
1013             p2c_header[0] != MEM_TRAIN_SYSTEM_SIGNATURE) {
1014                 DRM_DEBUG("p2c_header[0] is invalid, save depends on long training.\n");
1015                 ops |= PSP_MEM_TRAIN_SEND_LONG_MSG;
1016         }
1017
1018         if (ops & PSP_MEM_TRAIN_SEND_LONG_MSG) {
1019                 ops &= ~PSP_MEM_TRAIN_SEND_SHORT_MSG;
1020                 ops |= PSP_MEM_TRAIN_SAVE;
1021         }
1022
1023         DRM_DEBUG("Memory training ops:%x.\n", ops);
1024
1025         if (ops & PSP_MEM_TRAIN_SEND_LONG_MSG) {
1026                 ret = psp_v11_0_memory_training_send_msg(psp, PSP_BL__DRAM_LONG_TRAIN);
1027                 if (ret) {
1028                         DRM_ERROR("Send long training msg failed.\n");
1029                         return ret;
1030                 }
1031         }
1032
1033         if (ops & PSP_MEM_TRAIN_SAVE) {
1034                 amdgpu_device_vram_access(psp->adev, ctx->p2c_train_data_offset, ctx->sys_cache, ctx->train_data_size, false);
1035         }
1036
1037         if (ops & PSP_MEM_TRAIN_RESTORE) {
1038                 amdgpu_device_vram_access(psp->adev, ctx->c2p_train_data_offset, ctx->sys_cache, ctx->train_data_size, true);
1039         }
1040
1041         if (ops & PSP_MEM_TRAIN_SEND_SHORT_MSG) {
1042                 ret = psp_v11_0_memory_training_send_msg(psp, (amdgpu_force_long_training > 0) ?
1043                                                          PSP_BL__DRAM_LONG_TRAIN : PSP_BL__DRAM_SHORT_TRAIN);
1044                 if (ret) {
1045                         DRM_ERROR("send training msg failed.\n");
1046                         return ret;
1047                 }
1048         }
1049         ctx->training_cnt++;
1050         return 0;
1051 }
1052
1053 static uint32_t psp_v11_0_ring_get_wptr(struct psp_context *psp)
1054 {
1055         uint32_t data;
1056         struct amdgpu_device *adev = psp->adev;
1057
1058         if (psp_v11_0_support_vmr_ring(psp))
1059                 data = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_102);
1060         else
1061                 data = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_67);
1062
1063         return data;
1064 }
1065
1066 static void psp_v11_0_ring_set_wptr(struct psp_context *psp, uint32_t value)
1067 {
1068         struct amdgpu_device *adev = psp->adev;
1069
1070         if (psp_v11_0_support_vmr_ring(psp)) {
1071                 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_102, value);
1072                 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_101, GFX_CTRL_CMD_ID_CONSUME_CMD);
1073         } else
1074                 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_67, value);
1075 }
1076
1077 static const struct psp_funcs psp_v11_0_funcs = {
1078         .init_microcode = psp_v11_0_init_microcode,
1079         .bootloader_load_kdb = psp_v11_0_bootloader_load_kdb,
1080         .bootloader_load_sysdrv = psp_v11_0_bootloader_load_sysdrv,
1081         .bootloader_load_sos = psp_v11_0_bootloader_load_sos,
1082         .ring_init = psp_v11_0_ring_init,
1083         .ring_create = psp_v11_0_ring_create,
1084         .ring_stop = psp_v11_0_ring_stop,
1085         .ring_destroy = psp_v11_0_ring_destroy,
1086         .compare_sram_data = psp_v11_0_compare_sram_data,
1087         .mode1_reset = psp_v11_0_mode1_reset,
1088         .xgmi_get_topology_info = psp_v11_0_xgmi_get_topology_info,
1089         .xgmi_set_topology_info = psp_v11_0_xgmi_set_topology_info,
1090         .xgmi_get_hive_id = psp_v11_0_xgmi_get_hive_id,
1091         .xgmi_get_node_id = psp_v11_0_xgmi_get_node_id,
1092         .support_vmr_ring = psp_v11_0_support_vmr_ring,
1093         .ras_trigger_error = psp_v11_0_ras_trigger_error,
1094         .ras_cure_posion = psp_v11_0_ras_cure_posion,
1095         .rlc_autoload_start = psp_v11_0_rlc_autoload_start,
1096         .mem_training_init = psp_v11_0_memory_training_init,
1097         .mem_training_fini = psp_v11_0_memory_training_fini,
1098         .mem_training = psp_v11_0_memory_training,
1099         .ring_get_wptr = psp_v11_0_ring_get_wptr,
1100         .ring_set_wptr = psp_v11_0_ring_set_wptr,
1101 };
1102
1103 void psp_v11_0_set_psp_funcs(struct psp_context *psp)
1104 {
1105         psp->funcs = &psp_v11_0_funcs;
1106 }