drivers/gpu/drm/amd/amdgpu/psp_v11_0.c

   1 /*
   2  * Copyright 2018 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  */
  22
  23 #include <linux/firmware.h>
  24 #include <linux/module.h>
  25
  26 #include "amdgpu.h"
  27 #include "amdgpu_psp.h"
  28 #include "amdgpu_ucode.h"
  29 #include "soc15_common.h"
  30 #include "psp_v11_0.h"
  31
  32 #include "mp/mp_11_0_offset.h"
  33 #include "mp/mp_11_0_sh_mask.h"
  34 #include "gc/gc_9_0_offset.h"
  35 #include "sdma0/sdma0_4_0_offset.h"
  36 #include "nbio/nbio_7_4_offset.h"
  37
  38 #include "oss/osssys_4_0_offset.h"
  39 #include "oss/osssys_4_0_sh_mask.h"
  40
  41 MODULE_FIRMWARE("amdgpu/vega20_sos.bin");
  42 MODULE_FIRMWARE("amdgpu/vega20_asd.bin");
  43 MODULE_FIRMWARE("amdgpu/vega20_ta.bin");
  44
  45 /* address block */
  46 #define smnMP1_FIRMWARE_FLAGS           0x3010024
  47
  48 static int psp_v11_0_init_microcode(struct psp_context *psp)
  49 {
  50         struct amdgpu_device *adev = psp->adev;
  51         const char *chip_name;
  52         char fw_name[30];
  53         int err = 0;
  54         const struct psp_firmware_header_v1_0 *sos_hdr;
  55         const struct psp_firmware_header_v1_0 *asd_hdr;
  56         const struct ta_firmware_header_v1_0 *ta_hdr;
  57
  58         DRM_DEBUG("\n");
  59
  60         switch (adev->asic_type) {
  61         case CHIP_VEGA20:
  62                 chip_name = "vega20";
  63                 break;
  64         default:
  65                 BUG();
  66         }
  67
  68         snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_sos.bin", chip_name);
  69         err = request_firmware(&adev->psp.sos_fw, fw_name, adev->dev);
  70         if (err)
  71                 goto out;
  72
  73         err = amdgpu_ucode_validate(adev->psp.sos_fw);
  74         if (err)
  75                 goto out;
  76
  77         sos_hdr = (const struct psp_firmware_header_v1_0 *)adev->psp.sos_fw->data;
  78         adev->psp.sos_fw_version = le32_to_cpu(sos_hdr->header.ucode_version);
  79         adev->psp.sos_feature_version = le32_to_cpu(sos_hdr->ucode_feature_version);
  80         adev->psp.sos_bin_size = le32_to_cpu(sos_hdr->sos_size_bytes);
  81         adev->psp.sys_bin_size = le32_to_cpu(sos_hdr->header.ucode_size_bytes) -
  82                                         le32_to_cpu(sos_hdr->sos_size_bytes);
  83         adev->psp.sys_start_addr = (uint8_t *)sos_hdr +
  84                                 le32_to_cpu(sos_hdr->header.ucode_array_offset_bytes);
  85         adev->psp.sos_start_addr = (uint8_t *)adev->psp.sys_start_addr +
  86                                 le32_to_cpu(sos_hdr->sos_offset_bytes);
  87
  88         snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_asd.bin", chip_name);
  89         err = request_firmware(&adev->psp.asd_fw, fw_name, adev->dev);
  90         if (err)
  91                 goto out1;
  92
  93         err = amdgpu_ucode_validate(adev->psp.asd_fw);
  94         if (err)
  95                 goto out1;
  96
  97         asd_hdr = (const struct psp_firmware_header_v1_0 *)adev->psp.asd_fw->data;
  98         adev->psp.asd_fw_version = le32_to_cpu(asd_hdr->header.ucode_version);
  99         adev->psp.asd_feature_version = le32_to_cpu(asd_hdr->ucode_feature_version);
 100         adev->psp.asd_ucode_size = le32_to_cpu(asd_hdr->header.ucode_size_bytes);
 101         adev->psp.asd_start_addr = (uint8_t *)asd_hdr +
 102                                 le32_to_cpu(asd_hdr->header.ucode_array_offset_bytes);
 103
 104         snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_ta.bin", chip_name);
 105         err = request_firmware(&adev->psp.ta_fw, fw_name, adev->dev);
 106         if (err) {
 107                 release_firmware(adev->psp.ta_fw);
 108                 adev->psp.ta_fw = NULL;
 109                 dev_info(adev->dev,
 110                          "psp v11.0: Failed to load firmware \"%s\"\n", fw_name);
 111         } else {
 112                 err = amdgpu_ucode_validate(adev->psp.ta_fw);
 113                 if (err)
 114                         goto out2;
 115
 116                 ta_hdr = (const struct ta_firmware_header_v1_0 *)adev->psp.ta_fw->data;
 117                 adev->psp.ta_xgmi_ucode_version = le32_to_cpu(ta_hdr->ta_xgmi_ucode_version);
 118                 adev->psp.ta_xgmi_ucode_size = le32_to_cpu(ta_hdr->ta_xgmi_size_bytes);
 119                 adev->psp.ta_xgmi_start_addr = (uint8_t *)ta_hdr +
 120                         le32_to_cpu(ta_hdr->header.ucode_array_offset_bytes);
 121
 122                 adev->psp.ta_fw_version = le32_to_cpu(ta_hdr->header.ucode_version);
 123
 124                 adev->psp.ta_ras_ucode_version = le32_to_cpu(ta_hdr->ta_ras_ucode_version);
 125                 adev->psp.ta_ras_ucode_size = le32_to_cpu(ta_hdr->ta_ras_size_bytes);
 126                 adev->psp.ta_ras_start_addr = (uint8_t *)adev->psp.ta_xgmi_start_addr +
 127                         le32_to_cpu(ta_hdr->ta_ras_offset_bytes);
 128         }
 129
 130         return 0;
 131
 132 out2:
 133         release_firmware(adev->psp.ta_fw);
 134         adev->psp.ta_fw = NULL;
 135 out1:
 136         release_firmware(adev->psp.asd_fw);
 137         adev->psp.asd_fw = NULL;
 138 out:
 139         dev_err(adev->dev,
 140                 "psp v11.0: Failed to load firmware \"%s\"\n", fw_name);
 141         release_firmware(adev->psp.sos_fw);
 142         adev->psp.sos_fw = NULL;
 143
 144         return err;
 145 }
 146
 147 static int psp_v11_0_bootloader_load_sysdrv(struct psp_context *psp)
 148 {
 149         int ret;
 150         uint32_t psp_gfxdrv_command_reg = 0;
 151         struct amdgpu_device *adev = psp->adev;
 152         uint32_t sol_reg;
 153
 154         /* Check sOS sign of life register to confirm sys driver and sOS
 155          * are already been loaded.
 156          */
 157         sol_reg = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_81);
 158         if (sol_reg) {
 159                 psp->sos_fw_version = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_58);
 160                 printk("sos fw version = 0x%x.\n", psp->sos_fw_version);
 161                 return 0;
 162         }
 163
 164         /* Wait for bootloader to signify that is ready having bit 31 of C2PMSG_35 set to 1 */
 165         ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_35),
 166                            0x80000000, 0x80000000, false);
 167         if (ret)
 168                 return ret;
 169
 170         memset(psp->fw_pri_buf, 0, PSP_1_MEG);
 171
 172         /* Copy PSP System Driver binary to memory */
 173         memcpy(psp->fw_pri_buf, psp->sys_start_addr, psp->sys_bin_size);
 174
 175         /* Provide the sys driver to bootloader */
 176         WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_36,
 177                (uint32_t)(psp->fw_pri_mc_addr >> 20));
 178         psp_gfxdrv_command_reg = 1 << 16;
 179         WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_35,
 180                psp_gfxdrv_command_reg);
 181
 182         /* there might be handshake issue with hardware which needs delay */
 183         mdelay(20);
 184
 185         ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_35),
 186                            0x80000000, 0x80000000, false);
 187
 188         return ret;
 189 }
 190
 191 static int psp_v11_0_bootloader_load_sos(struct psp_context *psp)
 192 {
 193         int ret;
 194         unsigned int psp_gfxdrv_command_reg = 0;
 195         struct amdgpu_device *adev = psp->adev;
 196         uint32_t sol_reg;
 197
 198         /* Check sOS sign of life register to confirm sys driver and sOS
 199          * are already been loaded.
 200          */
 201         sol_reg = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_81);
 202         if (sol_reg)
 203                 return 0;
 204
 205         /* Wait for bootloader to signify that is ready having bit 31 of C2PMSG_35 set to 1 */
 206         ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_35),
 207                            0x80000000, 0x80000000, false);
 208         if (ret)
 209                 return ret;
 210
 211         memset(psp->fw_pri_buf, 0, PSP_1_MEG);
 212
 213         /* Copy Secure OS binary to PSP memory */
 214         memcpy(psp->fw_pri_buf, psp->sos_start_addr, psp->sos_bin_size);
 215
 216         /* Provide the PSP secure OS to bootloader */
 217         WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_36,
 218                (uint32_t)(psp->fw_pri_mc_addr >> 20));
 219         psp_gfxdrv_command_reg = 2 << 16;
 220         WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_35,
 221                psp_gfxdrv_command_reg);
 222
 223         /* there might be handshake issue with hardware which needs delay */
 224         mdelay(20);
 225         ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_81),
 226                            RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_81),
 227                            0, true);
 228
 229         return ret;
 230 }
 231
 232 static void psp_v11_0_reroute_ih(struct psp_context *psp)
 233 {
 234         struct amdgpu_device *adev = psp->adev;
 235         uint32_t tmp;
 236
 237         /* Change IH ring for VMC */
 238         tmp = REG_SET_FIELD(0, IH_CLIENT_CFG_DATA, CREDIT_RETURN_ADDR, 0x1244b);
 239         tmp = REG_SET_FIELD(tmp, IH_CLIENT_CFG_DATA, CLIENT_TYPE, 1);
 240         tmp = REG_SET_FIELD(tmp, IH_CLIENT_CFG_DATA, RING_ID, 1);
 241
 242         WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_69, 3);
 243         WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_70, tmp);
 244         WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_64, GFX_CTRL_CMD_ID_GBR_IH_SET);
 245
 246         mdelay(20);
 247         psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64),
 248                      0x80000000, 0x8000FFFF, false);
 249
 250         /* Change IH ring for UMC */
 251         tmp = REG_SET_FIELD(0, IH_CLIENT_CFG_DATA, CREDIT_RETURN_ADDR, 0x1216b);
 252         tmp = REG_SET_FIELD(tmp, IH_CLIENT_CFG_DATA, RING_ID, 1);
 253
 254         WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_69, 4);
 255         WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_70, tmp);
 256         WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_64, GFX_CTRL_CMD_ID_GBR_IH_SET);
 257
 258         mdelay(20);
 259         psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64),
 260                      0x80000000, 0x8000FFFF, false);
 261 }
 262
 263 static int psp_v11_0_ring_init(struct psp_context *psp,
 264                               enum psp_ring_type ring_type)
 265 {
 266         int ret = 0;
 267         struct psp_ring *ring;
 268         struct amdgpu_device *adev = psp->adev;
 269
 270         psp_v11_0_reroute_ih(psp);
 271
 272         ring = &psp->km_ring;
 273
 274         ring->ring_type = ring_type;
 275
 276         /* allocate 4k Page of Local Frame Buffer memory for ring */
 277         ring->ring_size = 0x1000;
 278         ret = amdgpu_bo_create_kernel(adev, ring->ring_size, PAGE_SIZE,
 279                                       AMDGPU_GEM_DOMAIN_VRAM,
 280                                       &adev->firmware.rbuf,
 281                                       &ring->ring_mem_mc_addr,
 282                                       (void **)&ring->ring_mem);
 283         if (ret) {
 284                 ring->ring_size = 0;
 285                 return ret;
 286         }
 287
 288         return 0;
 289 }
 290
 291 static bool psp_v11_0_support_vmr_ring(struct psp_context *psp)
 292 {
 293         if (amdgpu_sriov_vf(psp->adev) && psp->sos_fw_version > 0x80045)
 294                 return true;
 295         return false;
 296 }
 297
 298 static int psp_v11_0_ring_create(struct psp_context *psp,
 299                                 enum psp_ring_type ring_type)
 300 {
 301         int ret = 0;
 302         unsigned int psp_ring_reg = 0;
 303         struct psp_ring *ring = &psp->km_ring;
 304         struct amdgpu_device *adev = psp->adev;
 305
 306         if (psp_v11_0_support_vmr_ring(psp)) {
 307                 /* Write low address of the ring to C2PMSG_102 */
 308                 psp_ring_reg = lower_32_bits(ring->ring_mem_mc_addr);
 309                 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_102, psp_ring_reg);
 310                 /* Write high address of the ring to C2PMSG_103 */
 311                 psp_ring_reg = upper_32_bits(ring->ring_mem_mc_addr);
 312                 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_103, psp_ring_reg);
 313
 314                 /* Write the ring initialization command to C2PMSG_101 */
 315                 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_101,
 316                                              GFX_CTRL_CMD_ID_INIT_GPCOM_RING);
 317
 318                 /* there might be handshake issue with hardware which needs delay */
 319                 mdelay(20);
 320
 321                 /* Wait for response flag (bit 31) in C2PMSG_101 */
 322                 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_101),
 323                                    0x80000000, 0x8000FFFF, false);
 324
 325         } else {
 326                 /* Write low address of the ring to C2PMSG_69 */
 327                 psp_ring_reg = lower_32_bits(ring->ring_mem_mc_addr);
 328                 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_69, psp_ring_reg);
 329                 /* Write high address of the ring to C2PMSG_70 */
 330                 psp_ring_reg = upper_32_bits(ring->ring_mem_mc_addr);
 331                 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_70, psp_ring_reg);
 332                 /* Write size of ring to C2PMSG_71 */
 333                 psp_ring_reg = ring->ring_size;
 334                 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_71, psp_ring_reg);
 335                 /* Write the ring initialization command to C2PMSG_64 */
 336                 psp_ring_reg = ring_type;
 337                 psp_ring_reg = psp_ring_reg << 16;
 338                 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_64, psp_ring_reg);
 339
 340                 /* there might be handshake issue with hardware which needs delay */
 341                 mdelay(20);
 342
 343                 /* Wait for response flag (bit 31) in C2PMSG_64 */
 344                 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64),
 345                                    0x80000000, 0x8000FFFF, false);
 346         }
 347
 348         return ret;
 349 }
 350
 351 static int psp_v11_0_ring_stop(struct psp_context *psp,
 352                               enum psp_ring_type ring_type)
 353 {
 354         int ret = 0;
 355         struct amdgpu_device *adev = psp->adev;
 356
 357         /* Write the ring destroy command*/
 358         if (psp_v11_0_support_vmr_ring(psp))
 359                 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_101,
 360                                      GFX_CTRL_CMD_ID_DESTROY_GPCOM_RING);
 361         else
 362                 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_64,
 363                                      GFX_CTRL_CMD_ID_DESTROY_RINGS);
 364
 365         /* there might be handshake issue with hardware which needs delay */
 366         mdelay(20);
 367
 368         /* Wait for response flag (bit 31) */
 369         if (psp_v11_0_support_vmr_ring(psp))
 370                 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_101),
 371                                    0x80000000, 0x80000000, false);
 372         else
 373                 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64),
 374                                    0x80000000, 0x80000000, false);
 375
 376         return ret;
 377 }
 378
 379 static int psp_v11_0_ring_destroy(struct psp_context *psp,
 380                                  enum psp_ring_type ring_type)
 381 {
 382         int ret = 0;
 383         struct psp_ring *ring = &psp->km_ring;
 384         struct amdgpu_device *adev = psp->adev;
 385
 386         ret = psp_v11_0_ring_stop(psp, ring_type);
 387         if (ret)
 388                 DRM_ERROR("Fail to stop psp ring\n");
 389
 390         amdgpu_bo_free_kernel(&adev->firmware.rbuf,
 391                               &ring->ring_mem_mc_addr,
 392                               (void **)&ring->ring_mem);
 393
 394         return ret;
 395 }
 396
 397 static int psp_v11_0_cmd_submit(struct psp_context *psp,
 398                                struct amdgpu_firmware_info *ucode,
 399                                uint64_t cmd_buf_mc_addr, uint64_t fence_mc_addr,
 400                                int index)
 401 {
 402         unsigned int psp_write_ptr_reg = 0;
 403         struct psp_gfx_rb_frame *write_frame = psp->km_ring.ring_mem;
 404         struct psp_ring *ring = &psp->km_ring;
 405         struct psp_gfx_rb_frame *ring_buffer_start = ring->ring_mem;
 406         struct psp_gfx_rb_frame *ring_buffer_end = ring_buffer_start +
 407                 ring->ring_size / sizeof(struct psp_gfx_rb_frame) - 1;
 408         struct amdgpu_device *adev = psp->adev;
 409         uint32_t ring_size_dw = ring->ring_size / 4;
 410         uint32_t rb_frame_size_dw = sizeof(struct psp_gfx_rb_frame) / 4;
 411
 412         /* KM (GPCOM) prepare write pointer */
 413         if (psp_v11_0_support_vmr_ring(psp))
 414                 psp_write_ptr_reg = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_102);
 415         else
 416                 psp_write_ptr_reg = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_67);
 417
 418         /* Update KM RB frame pointer to new frame */
 419         /* write_frame ptr increments by size of rb_frame in bytes */
 420         /* psp_write_ptr_reg increments by size of rb_frame in DWORDs */
 421         if ((psp_write_ptr_reg % ring_size_dw) == 0)
 422                 write_frame = ring_buffer_start;
 423         else
 424                 write_frame = ring_buffer_start + (psp_write_ptr_reg / rb_frame_size_dw);
 425         /* Check invalid write_frame ptr address */
 426         if ((write_frame < ring_buffer_start) || (ring_buffer_end < write_frame)) {
 427                 DRM_ERROR("ring_buffer_start = %p; ring_buffer_end = %p; write_frame = %p\n",
 428                           ring_buffer_start, ring_buffer_end, write_frame);
 429                 DRM_ERROR("write_frame is pointing to address out of bounds\n");
 430                 return -EINVAL;
 431         }
 432
 433         /* Initialize KM RB frame */
 434         memset(write_frame, 0, sizeof(struct psp_gfx_rb_frame));
 435
 436         /* Update KM RB frame */
 437         write_frame->cmd_buf_addr_hi = upper_32_bits(cmd_buf_mc_addr);
 438         write_frame->cmd_buf_addr_lo = lower_32_bits(cmd_buf_mc_addr);
 439         write_frame->fence_addr_hi = upper_32_bits(fence_mc_addr);
 440         write_frame->fence_addr_lo = lower_32_bits(fence_mc_addr);
 441         write_frame->fence_value = index;
 442
 443         /* Update the write Pointer in DWORDs */
 444         psp_write_ptr_reg = (psp_write_ptr_reg + rb_frame_size_dw) % ring_size_dw;
 445         if (psp_v11_0_support_vmr_ring(psp)) {
 446                 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_102, psp_write_ptr_reg);
 447                 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_101, GFX_CTRL_CMD_ID_CONSUME_CMD);
 448         } else
 449                 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_67, psp_write_ptr_reg);
 450
 451         return 0;
 452 }
 453
 454 static int
 455 psp_v11_0_sram_map(struct amdgpu_device *adev,
 456                   unsigned int *sram_offset, unsigned int *sram_addr_reg_offset,
 457                   unsigned int *sram_data_reg_offset,
 458                   enum AMDGPU_UCODE_ID ucode_id)
 459 {
 460         int ret = 0;
 461
 462         switch (ucode_id) {
 463 /* TODO: needs to confirm */
 464 #if 0
 465         case AMDGPU_UCODE_ID_SMC:
 466                 *sram_offset = 0;
 467                 *sram_addr_reg_offset = 0;
 468                 *sram_data_reg_offset = 0;
 469                 break;
 470 #endif
 471
 472         case AMDGPU_UCODE_ID_CP_CE:
 473                 *sram_offset = 0x0;
 474                 *sram_addr_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_CE_UCODE_ADDR);
 475                 *sram_data_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_CE_UCODE_DATA);
 476                 break;
 477
 478         case AMDGPU_UCODE_ID_CP_PFP:
 479                 *sram_offset = 0x0;
 480                 *sram_addr_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_PFP_UCODE_ADDR);
 481                 *sram_data_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_PFP_UCODE_DATA);
 482                 break;
 483
 484         case AMDGPU_UCODE_ID_CP_ME:
 485                 *sram_offset = 0x0;
 486                 *sram_addr_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_HYP_ME_UCODE_ADDR);
 487                 *sram_data_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_HYP_ME_UCODE_DATA);
 488                 break;
 489
 490         case AMDGPU_UCODE_ID_CP_MEC1:
 491                 *sram_offset = 0x10000;
 492                 *sram_addr_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_MEC_ME1_UCODE_ADDR);
 493                 *sram_data_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_MEC_ME1_UCODE_DATA);
 494                 break;
 495
 496         case AMDGPU_UCODE_ID_CP_MEC2:
 497                 *sram_offset = 0x10000;
 498                 *sram_addr_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_HYP_MEC2_UCODE_ADDR);
 499                 *sram_data_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_HYP_MEC2_UCODE_DATA);
 500                 break;
 501
 502         case AMDGPU_UCODE_ID_RLC_G:
 503                 *sram_offset = 0x2000;
 504                 *sram_addr_reg_offset = SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_UCODE_ADDR);
 505                 *sram_data_reg_offset = SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_UCODE_DATA);
 506                 break;
 507
 508         case AMDGPU_UCODE_ID_SDMA0:
 509                 *sram_offset = 0x0;
 510                 *sram_addr_reg_offset = SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_UCODE_ADDR);
 511                 *sram_data_reg_offset = SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_UCODE_DATA);
 512                 break;
 513
 514 /* TODO: needs to confirm */
 515 #if 0
 516         case AMDGPU_UCODE_ID_SDMA1:
 517                 *sram_offset = ;
 518                 *sram_addr_reg_offset = ;
 519                 break;
 520
 521         case AMDGPU_UCODE_ID_UVD:
 522                 *sram_offset = ;
 523                 *sram_addr_reg_offset = ;
 524                 break;
 525
 526         case AMDGPU_UCODE_ID_VCE:
 527                 *sram_offset = ;
 528                 *sram_addr_reg_offset = ;
 529                 break;
 530 #endif
 531
 532         case AMDGPU_UCODE_ID_MAXIMUM:
 533         default:
 534                 ret = -EINVAL;
 535                 break;
 536         }
 537
 538         return ret;
 539 }
 540
 541 static bool psp_v11_0_compare_sram_data(struct psp_context *psp,
 542                                        struct amdgpu_firmware_info *ucode,
 543                                        enum AMDGPU_UCODE_ID ucode_type)
 544 {
 545         int err = 0;
 546         unsigned int fw_sram_reg_val = 0;
 547         unsigned int fw_sram_addr_reg_offset = 0;
 548         unsigned int fw_sram_data_reg_offset = 0;
 549         unsigned int ucode_size;
 550         uint32_t *ucode_mem = NULL;
 551         struct amdgpu_device *adev = psp->adev;
 552
 553         err = psp_v11_0_sram_map(adev, &fw_sram_reg_val, &fw_sram_addr_reg_offset,
 554                                 &fw_sram_data_reg_offset, ucode_type);
 555         if (err)
 556                 return false;
 557
 558         WREG32(fw_sram_addr_reg_offset, fw_sram_reg_val);
 559
 560         ucode_size = ucode->ucode_size;
 561         ucode_mem = (uint32_t *)ucode->kaddr;
 562         while (ucode_size) {
 563                 fw_sram_reg_val = RREG32(fw_sram_data_reg_offset);
 564
 565                 if (*ucode_mem != fw_sram_reg_val)
 566                         return false;
 567
 568                 ucode_mem++;
 569                 /* 4 bytes */
 570                 ucode_size -= 4;
 571         }
 572
 573         return true;
 574 }
 575
 576 static int psp_v11_0_mode1_reset(struct psp_context *psp)
 577 {
 578         int ret;
 579         uint32_t offset;
 580         struct amdgpu_device *adev = psp->adev;
 581
 582         offset = SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64);
 583
 584         ret = psp_wait_for(psp, offset, 0x80000000, 0x8000FFFF, false);
 585
 586         if (ret) {
 587                 DRM_INFO("psp is not working correctly before mode1 reset!\n");
 588                 return -EINVAL;
 589         }
 590
 591         /*send the mode 1 reset command*/
 592         WREG32(offset, GFX_CTRL_CMD_ID_MODE1_RST);
 593
 594         msleep(500);
 595
 596         offset = SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_33);
 597
 598         ret = psp_wait_for(psp, offset, 0x80000000, 0x80000000, false);
 599
 600         if (ret) {
 601                 DRM_INFO("psp mode 1 reset failed!\n");
 602                 return -EINVAL;
 603         }
 604
 605         DRM_INFO("psp mode1 reset succeed \n");
 606
 607         return 0;
 608 }
 609
 610 /* TODO: Fill in follow functions once PSP firmware interface for XGMI is ready.
 611  * For now, return success and hack the hive_id so high level code can
 612  * start testing
 613  */
 614 static int psp_v11_0_xgmi_get_topology_info(struct psp_context *psp,
 615         int number_devices, struct psp_xgmi_topology_info *topology)
 616 {
 617         struct ta_xgmi_shared_memory *xgmi_cmd;
 618         struct ta_xgmi_cmd_get_topology_info_input *topology_info_input;
 619         struct ta_xgmi_cmd_get_topology_info_output *topology_info_output;
 620         int i;
 621         int ret;
 622
 623         if (!topology || topology->num_nodes > TA_XGMI__MAX_CONNECTED_NODES)
 624                 return -EINVAL;
 625
 626         xgmi_cmd = (struct ta_xgmi_shared_memory*)psp->xgmi_context.xgmi_shared_buf;
 627         memset(xgmi_cmd, 0, sizeof(struct ta_xgmi_shared_memory));
 628
 629         /* Fill in the shared memory with topology information as input */
 630         topology_info_input = &xgmi_cmd->xgmi_in_message.get_topology_info;
 631         xgmi_cmd->cmd_id = TA_COMMAND_XGMI__GET_GET_TOPOLOGY_INFO;
 632         topology_info_input->num_nodes = number_devices;
 633
 634         for (i = 0; i < topology_info_input->num_nodes; i++) {
 635                 topology_info_input->nodes[i].node_id = topology->nodes[i].node_id;
 636                 topology_info_input->nodes[i].num_hops = topology->nodes[i].num_hops;
 637                 topology_info_input->nodes[i].is_sharing_enabled = topology->nodes[i].is_sharing_enabled;
 638                 topology_info_input->nodes[i].sdma_engine = topology->nodes[i].sdma_engine;
 639         }
 640
 641         /* Invoke xgmi ta to get the topology information */
 642         ret = psp_xgmi_invoke(psp, TA_COMMAND_XGMI__GET_GET_TOPOLOGY_INFO);
 643         if (ret)
 644                 return ret;
 645
 646         /* Read the output topology information from the shared memory */
 647         topology_info_output = &xgmi_cmd->xgmi_out_message.get_topology_info;
 648         topology->num_nodes = xgmi_cmd->xgmi_out_message.get_topology_info.num_nodes;
 649         for (i = 0; i < topology->num_nodes; i++) {
 650                 topology->nodes[i].node_id = topology_info_output->nodes[i].node_id;
 651                 topology->nodes[i].num_hops = topology_info_output->nodes[i].num_hops;
 652                 topology->nodes[i].is_sharing_enabled = topology_info_output->nodes[i].is_sharing_enabled;
 653                 topology->nodes[i].sdma_engine = topology_info_output->nodes[i].sdma_engine;
 654         }
 655
 656         return 0;
 657 }
 658
 659 static int psp_v11_0_xgmi_set_topology_info(struct psp_context *psp,
 660         int number_devices, struct psp_xgmi_topology_info *topology)
 661 {
 662         struct ta_xgmi_shared_memory *xgmi_cmd;
 663         struct ta_xgmi_cmd_get_topology_info_input *topology_info_input;
 664         int i;
 665
 666         if (!topology || topology->num_nodes > TA_XGMI__MAX_CONNECTED_NODES)
 667                 return -EINVAL;
 668
 669         xgmi_cmd = (struct ta_xgmi_shared_memory*)psp->xgmi_context.xgmi_shared_buf;
 670         memset(xgmi_cmd, 0, sizeof(struct ta_xgmi_shared_memory));
 671
 672         topology_info_input = &xgmi_cmd->xgmi_in_message.get_topology_info;
 673         xgmi_cmd->cmd_id = TA_COMMAND_XGMI__SET_TOPOLOGY_INFO;
 674         topology_info_input->num_nodes = number_devices;
 675
 676         for (i = 0; i < topology_info_input->num_nodes; i++) {
 677                 topology_info_input->nodes[i].node_id = topology->nodes[i].node_id;
 678                 topology_info_input->nodes[i].num_hops = topology->nodes[i].num_hops;
 679                 topology_info_input->nodes[i].is_sharing_enabled = 1;
 680                 topology_info_input->nodes[i].sdma_engine = topology->nodes[i].sdma_engine;
 681         }
 682
 683         /* Invoke xgmi ta to set topology information */
 684         return psp_xgmi_invoke(psp, TA_COMMAND_XGMI__SET_TOPOLOGY_INFO);
 685 }
 686
 687 static int psp_v11_0_xgmi_get_hive_id(struct psp_context *psp, uint64_t *hive_id)
 688 {
 689         struct ta_xgmi_shared_memory *xgmi_cmd;
 690         int ret;
 691
 692         xgmi_cmd = (struct ta_xgmi_shared_memory*)psp->xgmi_context.xgmi_shared_buf;
 693         memset(xgmi_cmd, 0, sizeof(struct ta_xgmi_shared_memory));
 694
 695         xgmi_cmd->cmd_id = TA_COMMAND_XGMI__GET_HIVE_ID;
 696
 697         /* Invoke xgmi ta to get hive id */
 698         ret = psp_xgmi_invoke(psp, xgmi_cmd->cmd_id);
 699         if (ret)
 700                 return ret;
 701
 702         *hive_id = xgmi_cmd->xgmi_out_message.get_hive_id.hive_id;
 703
 704         return 0;
 705 }
 706
 707 static int psp_v11_0_xgmi_get_node_id(struct psp_context *psp, uint64_t *node_id)
 708 {
 709         struct ta_xgmi_shared_memory *xgmi_cmd;
 710         int ret;
 711
 712         xgmi_cmd = (struct ta_xgmi_shared_memory*)psp->xgmi_context.xgmi_shared_buf;
 713         memset(xgmi_cmd, 0, sizeof(struct ta_xgmi_shared_memory));
 714
 715         xgmi_cmd->cmd_id = TA_COMMAND_XGMI__GET_NODE_ID;
 716
 717         /* Invoke xgmi ta to get the node id */
 718         ret = psp_xgmi_invoke(psp, xgmi_cmd->cmd_id);
 719         if (ret)
 720                 return ret;
 721
 722         *node_id = xgmi_cmd->xgmi_out_message.get_node_id.node_id;
 723
 724         return 0;
 725 }
 726
 727 static int psp_v11_0_ras_trigger_error(struct psp_context *psp,
 728                 struct ta_ras_trigger_error_input *info)
 729 {
 730         struct ta_ras_shared_memory *ras_cmd;
 731         int ret;
 732
 733         if (!psp->ras.ras_initialized)
 734                 return -EINVAL;
 735
 736         ras_cmd = (struct ta_ras_shared_memory *)psp->ras.ras_shared_buf;
 737         memset(ras_cmd, 0, sizeof(struct ta_ras_shared_memory));
 738
 739         ras_cmd->cmd_id = TA_RAS_COMMAND__TRIGGER_ERROR;
 740         ras_cmd->ras_in_message.trigger_error = *info;
 741
 742         ret = psp_ras_invoke(psp, ras_cmd->cmd_id);
 743         if (ret)
 744                 return -EINVAL;
 745
 746         return ras_cmd->ras_status;
 747 }
 748
 749 static int psp_v11_0_ras_cure_posion(struct psp_context *psp, uint64_t *mode_ptr)
 750 {
 751 #if 0
 752         // not support yet.
 753         struct ta_ras_shared_memory *ras_cmd;
 754         int ret;
 755
 756         if (!psp->ras.ras_initialized)
 757                 return -EINVAL;
 758
 759         ras_cmd = (struct ta_ras_shared_memory *)psp->ras.ras_shared_buf;
 760         memset(ras_cmd, 0, sizeof(struct ta_ras_shared_memory));
 761
 762         ras_cmd->cmd_id = TA_RAS_COMMAND__CURE_POISON;
 763         ras_cmd->ras_in_message.cure_poison.mode_ptr = mode_ptr;
 764
 765         ret = psp_ras_invoke(psp, ras_cmd->cmd_id);
 766         if (ret)
 767                 return -EINVAL;
 768
 769         return ras_cmd->ras_status;
 770 #else
 771         return -EINVAL;
 772 #endif
 773 }
 774
 775 static const struct psp_funcs psp_v11_0_funcs = {
 776         .init_microcode = psp_v11_0_init_microcode,
 777         .bootloader_load_sysdrv = psp_v11_0_bootloader_load_sysdrv,
 778         .bootloader_load_sos = psp_v11_0_bootloader_load_sos,
 779         .ring_init = psp_v11_0_ring_init,
 780         .ring_create = psp_v11_0_ring_create,
 781         .ring_stop = psp_v11_0_ring_stop,
 782         .ring_destroy = psp_v11_0_ring_destroy,
 783         .cmd_submit = psp_v11_0_cmd_submit,
 784         .compare_sram_data = psp_v11_0_compare_sram_data,
 785         .mode1_reset = psp_v11_0_mode1_reset,
 786         .xgmi_get_topology_info = psp_v11_0_xgmi_get_topology_info,
 787         .xgmi_set_topology_info = psp_v11_0_xgmi_set_topology_info,
 788         .xgmi_get_hive_id = psp_v11_0_xgmi_get_hive_id,
 789         .xgmi_get_node_id = psp_v11_0_xgmi_get_node_id,
 790         .support_vmr_ring = psp_v11_0_support_vmr_ring,
 791         .ras_trigger_error = psp_v11_0_ras_trigger_error,
 792         .ras_cure_posion = psp_v11_0_ras_cure_posion,
 793 };
 794
 795 void psp_v11_0_set_psp_funcs(struct psp_context *psp)
 796 {
 797         psp->funcs = &psp_v11_0_funcs;
 798 }