2 * Copyright 2019 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
23 #include <linux/firmware.h>
25 #include "amdgpu_psp.h"
26 #include "amdgpu_ucode.h"
27 #include "soc15_common.h"
28 #include "psp_v12_0.h"
30 #include "mp/mp_12_0_0_offset.h"
31 #include "mp/mp_12_0_0_sh_mask.h"
32 #include "gc/gc_9_0_offset.h"
33 #include "sdma0/sdma0_4_0_offset.h"
34 #include "nbio/nbio_7_4_offset.h"
36 #include "oss/osssys_4_0_offset.h"
37 #include "oss/osssys_4_0_sh_mask.h"
39 MODULE_FIRMWARE("amdgpu/renoir_asd.bin");
41 #define smnMP1_FIRMWARE_FLAGS 0x3010024
43 static int psp_v12_0_init_microcode(struct psp_context *psp)
45 struct amdgpu_device *adev = psp->adev;
46 const char *chip_name;
49 const struct psp_firmware_header_v1_0 *asd_hdr;
53 switch (adev->asic_type) {
61 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_asd.bin", chip_name);
62 err = request_firmware(&adev->psp.asd_fw, fw_name, adev->dev);
66 err = amdgpu_ucode_validate(adev->psp.asd_fw);
70 asd_hdr = (const struct psp_firmware_header_v1_0 *)adev->psp.asd_fw->data;
71 adev->psp.asd_fw_version = le32_to_cpu(asd_hdr->header.ucode_version);
72 adev->psp.asd_feature_version = le32_to_cpu(asd_hdr->ucode_feature_version);
73 adev->psp.asd_ucode_size = le32_to_cpu(asd_hdr->header.ucode_size_bytes);
74 adev->psp.asd_start_addr = (uint8_t *)asd_hdr +
75 le32_to_cpu(asd_hdr->header.ucode_array_offset_bytes);
80 release_firmware(adev->psp.asd_fw);
81 adev->psp.asd_fw = NULL;
86 static int psp_v12_0_bootloader_load_sysdrv(struct psp_context *psp)
89 uint32_t psp_gfxdrv_command_reg = 0;
90 struct amdgpu_device *adev = psp->adev;
93 /* Check sOS sign of life register to confirm sys driver and sOS
94 * are already been loaded.
96 sol_reg = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_81);
98 psp->sos_fw_version = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_58);
99 printk("sos fw version = 0x%x.\n", psp->sos_fw_version);
103 /* Wait for bootloader to signify that is ready having bit 31 of C2PMSG_35 set to 1 */
104 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_35),
105 0x80000000, 0x80000000, false);
109 memset(psp->fw_pri_buf, 0, PSP_1_MEG);
111 /* Copy PSP System Driver binary to memory */
112 memcpy(psp->fw_pri_buf, psp->sys_start_addr, psp->sys_bin_size);
114 /* Provide the sys driver to bootloader */
115 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_36,
116 (uint32_t)(psp->fw_pri_mc_addr >> 20));
117 psp_gfxdrv_command_reg = 1 << 16;
118 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_35,
119 psp_gfxdrv_command_reg);
121 /* there might be handshake issue with hardware which needs delay */
124 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_35),
125 0x80000000, 0x80000000, false);
130 static int psp_v12_0_bootloader_load_sos(struct psp_context *psp)
133 unsigned int psp_gfxdrv_command_reg = 0;
134 struct amdgpu_device *adev = psp->adev;
137 /* Check sOS sign of life register to confirm sys driver and sOS
138 * are already been loaded.
140 sol_reg = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_81);
144 /* Wait for bootloader to signify that is ready having bit 31 of C2PMSG_35 set to 1 */
145 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_35),
146 0x80000000, 0x80000000, false);
150 memset(psp->fw_pri_buf, 0, PSP_1_MEG);
152 /* Copy Secure OS binary to PSP memory */
153 memcpy(psp->fw_pri_buf, psp->sos_start_addr, psp->sos_bin_size);
155 /* Provide the PSP secure OS to bootloader */
156 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_36,
157 (uint32_t)(psp->fw_pri_mc_addr >> 20));
158 psp_gfxdrv_command_reg = 2 << 16;
159 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_35,
160 psp_gfxdrv_command_reg);
162 /* there might be handshake issue with hardware which needs delay */
164 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_81),
165 RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_81),
171 static void psp_v12_0_reroute_ih(struct psp_context *psp)
173 struct amdgpu_device *adev = psp->adev;
176 /* Change IH ring for VMC */
177 tmp = REG_SET_FIELD(0, IH_CLIENT_CFG_DATA, CREDIT_RETURN_ADDR, 0x1244b);
178 tmp = REG_SET_FIELD(tmp, IH_CLIENT_CFG_DATA, CLIENT_TYPE, 1);
179 tmp = REG_SET_FIELD(tmp, IH_CLIENT_CFG_DATA, RING_ID, 1);
181 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_69, 3);
182 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_70, tmp);
183 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_64, GFX_CTRL_CMD_ID_GBR_IH_SET);
186 psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64),
187 0x80000000, 0x8000FFFF, false);
189 /* Change IH ring for UMC */
190 tmp = REG_SET_FIELD(0, IH_CLIENT_CFG_DATA, CREDIT_RETURN_ADDR, 0x1216b);
191 tmp = REG_SET_FIELD(tmp, IH_CLIENT_CFG_DATA, RING_ID, 1);
193 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_69, 4);
194 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_70, tmp);
195 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_64, GFX_CTRL_CMD_ID_GBR_IH_SET);
198 psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64),
199 0x80000000, 0x8000FFFF, false);
202 static int psp_v12_0_ring_init(struct psp_context *psp,
203 enum psp_ring_type ring_type)
206 struct psp_ring *ring;
207 struct amdgpu_device *adev = psp->adev;
209 psp_v12_0_reroute_ih(psp);
211 ring = &psp->km_ring;
213 ring->ring_type = ring_type;
215 /* allocate 4k Page of Local Frame Buffer memory for ring */
216 ring->ring_size = 0x1000;
217 ret = amdgpu_bo_create_kernel(adev, ring->ring_size, PAGE_SIZE,
218 AMDGPU_GEM_DOMAIN_VRAM,
219 &adev->firmware.rbuf,
220 &ring->ring_mem_mc_addr,
221 (void **)&ring->ring_mem);
230 static bool psp_v12_0_support_vmr_ring(struct psp_context *psp)
232 if (amdgpu_sriov_vf(psp->adev) && psp->sos_fw_version > 0x80045)
237 static int psp_v12_0_ring_create(struct psp_context *psp,
238 enum psp_ring_type ring_type)
241 unsigned int psp_ring_reg = 0;
242 struct psp_ring *ring = &psp->km_ring;
243 struct amdgpu_device *adev = psp->adev;
245 if (psp_v12_0_support_vmr_ring(psp)) {
246 /* Write low address of the ring to C2PMSG_102 */
247 psp_ring_reg = lower_32_bits(ring->ring_mem_mc_addr);
248 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_102, psp_ring_reg);
249 /* Write high address of the ring to C2PMSG_103 */
250 psp_ring_reg = upper_32_bits(ring->ring_mem_mc_addr);
251 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_103, psp_ring_reg);
253 /* Write the ring initialization command to C2PMSG_101 */
254 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_101,
255 GFX_CTRL_CMD_ID_INIT_GPCOM_RING);
257 /* there might be handshake issue with hardware which needs delay */
260 /* Wait for response flag (bit 31) in C2PMSG_101 */
261 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_101),
262 0x80000000, 0x8000FFFF, false);
265 /* Write low address of the ring to C2PMSG_69 */
266 psp_ring_reg = lower_32_bits(ring->ring_mem_mc_addr);
267 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_69, psp_ring_reg);
268 /* Write high address of the ring to C2PMSG_70 */
269 psp_ring_reg = upper_32_bits(ring->ring_mem_mc_addr);
270 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_70, psp_ring_reg);
271 /* Write size of ring to C2PMSG_71 */
272 psp_ring_reg = ring->ring_size;
273 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_71, psp_ring_reg);
274 /* Write the ring initialization command to C2PMSG_64 */
275 psp_ring_reg = ring_type;
276 psp_ring_reg = psp_ring_reg << 16;
277 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_64, psp_ring_reg);
279 /* there might be handshake issue with hardware which needs delay */
282 /* Wait for response flag (bit 31) in C2PMSG_64 */
283 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64),
284 0x80000000, 0x8000FFFF, false);
290 static int psp_v12_0_ring_stop(struct psp_context *psp,
291 enum psp_ring_type ring_type)
294 struct amdgpu_device *adev = psp->adev;
296 /* Write the ring destroy command*/
297 if (psp_v12_0_support_vmr_ring(psp))
298 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_101,
299 GFX_CTRL_CMD_ID_DESTROY_GPCOM_RING);
301 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_64,
302 GFX_CTRL_CMD_ID_DESTROY_RINGS);
304 /* there might be handshake issue with hardware which needs delay */
307 /* Wait for response flag (bit 31) */
308 if (psp_v12_0_support_vmr_ring(psp))
309 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_101),
310 0x80000000, 0x80000000, false);
312 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64),
313 0x80000000, 0x80000000, false);
318 static int psp_v12_0_ring_destroy(struct psp_context *psp,
319 enum psp_ring_type ring_type)
322 struct psp_ring *ring = &psp->km_ring;
323 struct amdgpu_device *adev = psp->adev;
325 ret = psp_v12_0_ring_stop(psp, ring_type);
327 DRM_ERROR("Fail to stop psp ring\n");
329 amdgpu_bo_free_kernel(&adev->firmware.rbuf,
330 &ring->ring_mem_mc_addr,
331 (void **)&ring->ring_mem);
336 static int psp_v12_0_cmd_submit(struct psp_context *psp,
337 struct amdgpu_firmware_info *ucode,
338 uint64_t cmd_buf_mc_addr, uint64_t fence_mc_addr,
341 unsigned int psp_write_ptr_reg = 0;
342 struct psp_gfx_rb_frame *write_frame = psp->km_ring.ring_mem;
343 struct psp_ring *ring = &psp->km_ring;
344 struct psp_gfx_rb_frame *ring_buffer_start = ring->ring_mem;
345 struct psp_gfx_rb_frame *ring_buffer_end = ring_buffer_start +
346 ring->ring_size / sizeof(struct psp_gfx_rb_frame) - 1;
347 struct amdgpu_device *adev = psp->adev;
348 uint32_t ring_size_dw = ring->ring_size / 4;
349 uint32_t rb_frame_size_dw = sizeof(struct psp_gfx_rb_frame) / 4;
351 /* KM (GPCOM) prepare write pointer */
352 if (psp_v12_0_support_vmr_ring(psp))
353 psp_write_ptr_reg = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_102);
355 psp_write_ptr_reg = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_67);
357 /* Update KM RB frame pointer to new frame */
358 /* write_frame ptr increments by size of rb_frame in bytes */
359 /* psp_write_ptr_reg increments by size of rb_frame in DWORDs */
360 if ((psp_write_ptr_reg % ring_size_dw) == 0)
361 write_frame = ring_buffer_start;
363 write_frame = ring_buffer_start + (psp_write_ptr_reg / rb_frame_size_dw);
364 /* Check invalid write_frame ptr address */
365 if ((write_frame < ring_buffer_start) || (ring_buffer_end < write_frame)) {
366 DRM_ERROR("ring_buffer_start = %p; ring_buffer_end = %p; write_frame = %p\n",
367 ring_buffer_start, ring_buffer_end, write_frame);
368 DRM_ERROR("write_frame is pointing to address out of bounds\n");
372 /* Initialize KM RB frame */
373 memset(write_frame, 0, sizeof(struct psp_gfx_rb_frame));
375 /* Update KM RB frame */
376 write_frame->cmd_buf_addr_hi = upper_32_bits(cmd_buf_mc_addr);
377 write_frame->cmd_buf_addr_lo = lower_32_bits(cmd_buf_mc_addr);
378 write_frame->fence_addr_hi = upper_32_bits(fence_mc_addr);
379 write_frame->fence_addr_lo = lower_32_bits(fence_mc_addr);
380 write_frame->fence_value = index;
382 /* Update the write Pointer in DWORDs */
383 psp_write_ptr_reg = (psp_write_ptr_reg + rb_frame_size_dw) % ring_size_dw;
384 if (psp_v12_0_support_vmr_ring(psp)) {
385 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_102, psp_write_ptr_reg);
386 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_101, GFX_CTRL_CMD_ID_CONSUME_CMD);
388 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_67, psp_write_ptr_reg);
394 psp_v12_0_sram_map(struct amdgpu_device *adev,
395 unsigned int *sram_offset, unsigned int *sram_addr_reg_offset,
396 unsigned int *sram_data_reg_offset,
397 enum AMDGPU_UCODE_ID ucode_id)
402 /* TODO: needs to confirm */
404 case AMDGPU_UCODE_ID_SMC:
406 *sram_addr_reg_offset = 0;
407 *sram_data_reg_offset = 0;
411 case AMDGPU_UCODE_ID_CP_CE:
413 *sram_addr_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_CE_UCODE_ADDR);
414 *sram_data_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_CE_UCODE_DATA);
417 case AMDGPU_UCODE_ID_CP_PFP:
419 *sram_addr_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_PFP_UCODE_ADDR);
420 *sram_data_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_PFP_UCODE_DATA);
423 case AMDGPU_UCODE_ID_CP_ME:
425 *sram_addr_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_HYP_ME_UCODE_ADDR);
426 *sram_data_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_HYP_ME_UCODE_DATA);
429 case AMDGPU_UCODE_ID_CP_MEC1:
430 *sram_offset = 0x10000;
431 *sram_addr_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_MEC_ME1_UCODE_ADDR);
432 *sram_data_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_MEC_ME1_UCODE_DATA);
435 case AMDGPU_UCODE_ID_CP_MEC2:
436 *sram_offset = 0x10000;
437 *sram_addr_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_HYP_MEC2_UCODE_ADDR);
438 *sram_data_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_HYP_MEC2_UCODE_DATA);
441 case AMDGPU_UCODE_ID_RLC_G:
442 *sram_offset = 0x2000;
443 *sram_addr_reg_offset = SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_UCODE_ADDR);
444 *sram_data_reg_offset = SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_UCODE_DATA);
447 case AMDGPU_UCODE_ID_SDMA0:
449 *sram_addr_reg_offset = SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_UCODE_ADDR);
450 *sram_data_reg_offset = SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_UCODE_DATA);
453 /* TODO: needs to confirm */
455 case AMDGPU_UCODE_ID_SDMA1:
457 *sram_addr_reg_offset = ;
460 case AMDGPU_UCODE_ID_UVD:
462 *sram_addr_reg_offset = ;
465 case AMDGPU_UCODE_ID_VCE:
467 *sram_addr_reg_offset = ;
471 case AMDGPU_UCODE_ID_MAXIMUM:
480 static bool psp_v12_0_compare_sram_data(struct psp_context *psp,
481 struct amdgpu_firmware_info *ucode,
482 enum AMDGPU_UCODE_ID ucode_type)
485 unsigned int fw_sram_reg_val = 0;
486 unsigned int fw_sram_addr_reg_offset = 0;
487 unsigned int fw_sram_data_reg_offset = 0;
488 unsigned int ucode_size;
489 uint32_t *ucode_mem = NULL;
490 struct amdgpu_device *adev = psp->adev;
492 err = psp_v12_0_sram_map(adev, &fw_sram_reg_val, &fw_sram_addr_reg_offset,
493 &fw_sram_data_reg_offset, ucode_type);
497 WREG32(fw_sram_addr_reg_offset, fw_sram_reg_val);
499 ucode_size = ucode->ucode_size;
500 ucode_mem = (uint32_t *)ucode->kaddr;
502 fw_sram_reg_val = RREG32(fw_sram_data_reg_offset);
504 if (*ucode_mem != fw_sram_reg_val)
515 static int psp_v12_0_mode1_reset(struct psp_context *psp)
519 struct amdgpu_device *adev = psp->adev;
521 offset = SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64);
523 ret = psp_wait_for(psp, offset, 0x80000000, 0x8000FFFF, false);
526 DRM_INFO("psp is not working correctly before mode1 reset!\n");
530 /*send the mode 1 reset command*/
531 WREG32(offset, GFX_CTRL_CMD_ID_MODE1_RST);
535 offset = SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_33);
537 ret = psp_wait_for(psp, offset, 0x80000000, 0x80000000, false);
540 DRM_INFO("psp mode 1 reset failed!\n");
544 DRM_INFO("psp mode1 reset succeed \n");
549 static const struct psp_funcs psp_v12_0_funcs = {
550 .init_microcode = psp_v12_0_init_microcode,
551 .bootloader_load_sysdrv = psp_v12_0_bootloader_load_sysdrv,
552 .bootloader_load_sos = psp_v12_0_bootloader_load_sos,
553 .ring_init = psp_v12_0_ring_init,
554 .ring_create = psp_v12_0_ring_create,
555 .ring_stop = psp_v12_0_ring_stop,
556 .ring_destroy = psp_v12_0_ring_destroy,
557 .cmd_submit = psp_v12_0_cmd_submit,
558 .compare_sram_data = psp_v12_0_compare_sram_data,
559 .mode1_reset = psp_v12_0_mode1_reset,
562 void psp_v12_0_set_psp_funcs(struct psp_context *psp)
564 psp->funcs = &psp_v12_0_funcs;