2 * Copyright 2014 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
22 * Authors: Alex Deucher
24 #include <linux/firmware.h>
27 #include "amdgpu_ucode.h"
28 #include "amdgpu_trace.h"
32 #include "oss/oss_2_4_d.h"
33 #include "oss/oss_2_4_sh_mask.h"
35 #include "gmc/gmc_7_1_d.h"
36 #include "gmc/gmc_7_1_sh_mask.h"
38 #include "gca/gfx_8_0_d.h"
39 #include "gca/gfx_8_0_enum.h"
40 #include "gca/gfx_8_0_sh_mask.h"
42 #include "bif/bif_5_0_d.h"
43 #include "bif/bif_5_0_sh_mask.h"
45 #include "iceland_sdma_pkt_open.h"
47 static void sdma_v2_4_set_ring_funcs(struct amdgpu_device *adev);
48 static void sdma_v2_4_set_buffer_funcs(struct amdgpu_device *adev);
49 static void sdma_v2_4_set_vm_pte_funcs(struct amdgpu_device *adev);
50 static void sdma_v2_4_set_irq_funcs(struct amdgpu_device *adev);
52 MODULE_FIRMWARE("amdgpu/topaz_sdma.bin");
53 MODULE_FIRMWARE("amdgpu/topaz_sdma1.bin");
55 static const u32 sdma_offsets[SDMA_MAX_INSTANCE] =
57 SDMA0_REGISTER_OFFSET,
61 static const u32 golden_settings_iceland_a11[] =
63 mmSDMA0_CHICKEN_BITS, 0xfc910007, 0x00810007,
64 mmSDMA0_CLK_CTRL, 0xff000fff, 0x00000000,
65 mmSDMA1_CHICKEN_BITS, 0xfc910007, 0x00810007,
66 mmSDMA1_CLK_CTRL, 0xff000fff, 0x00000000,
69 static const u32 iceland_mgcg_cgcg_init[] =
71 mmSDMA0_CLK_CTRL, 0xff000ff0, 0x00000100,
72 mmSDMA1_CLK_CTRL, 0xff000ff0, 0x00000100
77 * Starting with CIK, the GPU has new asynchronous
78 * DMA engines. These engines are used for compute
79 * and gfx. There are two DMA engines (SDMA0, SDMA1)
80 * and each one supports 1 ring buffer used for gfx
81 * and 2 queues used for compute.
83 * The programming model is very similar to the CP
84 * (ring buffer, IBs, etc.), but sDMA has it's own
85 * packet format that is different from the PM4 format
86 * used by the CP. sDMA supports copying data, writing
87 * embedded data, solid fills, and a number of other
88 * things. It also has support for tiling/detiling of
92 static void sdma_v2_4_init_golden_registers(struct amdgpu_device *adev)
94 switch (adev->asic_type) {
96 amdgpu_program_register_sequence(adev,
97 iceland_mgcg_cgcg_init,
98 (const u32)ARRAY_SIZE(iceland_mgcg_cgcg_init));
99 amdgpu_program_register_sequence(adev,
100 golden_settings_iceland_a11,
101 (const u32)ARRAY_SIZE(golden_settings_iceland_a11));
108 static void sdma_v2_4_free_microcode(struct amdgpu_device *adev)
111 for (i = 0; i < adev->sdma.num_instances; i++) {
112 release_firmware(adev->sdma.instance[i].fw);
113 adev->sdma.instance[i].fw = NULL;
118 * sdma_v2_4_init_microcode - load ucode images from disk
120 * @adev: amdgpu_device pointer
122 * Use the firmware interface to load the ucode images into
123 * the driver (not loaded into hw).
124 * Returns 0 on success, error on failure.
126 static int sdma_v2_4_init_microcode(struct amdgpu_device *adev)
128 const char *chip_name;
131 struct amdgpu_firmware_info *info = NULL;
132 const struct common_firmware_header *header = NULL;
133 const struct sdma_firmware_header_v1_0 *hdr;
137 switch (adev->asic_type) {
144 for (i = 0; i < adev->sdma.num_instances; i++) {
146 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_sdma.bin", chip_name);
148 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_sdma1.bin", chip_name);
149 err = request_firmware(&adev->sdma.instance[i].fw, fw_name, adev->dev);
152 err = amdgpu_ucode_validate(adev->sdma.instance[i].fw);
155 hdr = (const struct sdma_firmware_header_v1_0 *)adev->sdma.instance[i].fw->data;
156 adev->sdma.instance[i].fw_version = le32_to_cpu(hdr->header.ucode_version);
157 adev->sdma.instance[i].feature_version = le32_to_cpu(hdr->ucode_feature_version);
158 if (adev->sdma.instance[i].feature_version >= 20)
159 adev->sdma.instance[i].burst_nop = true;
161 if (adev->firmware.smu_load) {
162 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_SDMA0 + i];
163 info->ucode_id = AMDGPU_UCODE_ID_SDMA0 + i;
164 info->fw = adev->sdma.instance[i].fw;
165 header = (const struct common_firmware_header *)info->fw->data;
166 adev->firmware.fw_size +=
167 ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
174 "sdma_v2_4: Failed to load firmware \"%s\"\n",
176 for (i = 0; i < adev->sdma.num_instances; i++) {
177 release_firmware(adev->sdma.instance[i].fw);
178 adev->sdma.instance[i].fw = NULL;
185 * sdma_v2_4_ring_get_rptr - get the current read pointer
187 * @ring: amdgpu ring pointer
189 * Get the current rptr from the hardware (VI+).
191 static uint32_t sdma_v2_4_ring_get_rptr(struct amdgpu_ring *ring)
195 /* XXX check if swapping is necessary on BE */
196 rptr = ring->adev->wb.wb[ring->rptr_offs] >> 2;
202 * sdma_v2_4_ring_get_wptr - get the current write pointer
204 * @ring: amdgpu ring pointer
206 * Get the current wptr from the hardware (VI+).
208 static uint32_t sdma_v2_4_ring_get_wptr(struct amdgpu_ring *ring)
210 struct amdgpu_device *adev = ring->adev;
211 int me = (ring == &ring->adev->sdma.instance[0].ring) ? 0 : 1;
212 u32 wptr = RREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[me]) >> 2;
218 * sdma_v2_4_ring_set_wptr - commit the write pointer
220 * @ring: amdgpu ring pointer
222 * Write the wptr back to the hardware (VI+).
224 static void sdma_v2_4_ring_set_wptr(struct amdgpu_ring *ring)
226 struct amdgpu_device *adev = ring->adev;
227 int me = (ring == &ring->adev->sdma.instance[0].ring) ? 0 : 1;
229 WREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[me], ring->wptr << 2);
232 static void sdma_v2_4_ring_insert_nop(struct amdgpu_ring *ring, uint32_t count)
234 struct amdgpu_sdma_instance *sdma = amdgpu_get_sdma_instance(ring);
237 for (i = 0; i < count; i++)
238 if (sdma && sdma->burst_nop && (i == 0))
239 amdgpu_ring_write(ring, ring->nop |
240 SDMA_PKT_NOP_HEADER_COUNT(count - 1));
242 amdgpu_ring_write(ring, ring->nop);
246 * sdma_v2_4_ring_emit_ib - Schedule an IB on the DMA engine
248 * @ring: amdgpu ring pointer
249 * @ib: IB object to schedule
251 * Schedule an IB in the DMA ring (VI).
253 static void sdma_v2_4_ring_emit_ib(struct amdgpu_ring *ring,
254 struct amdgpu_ib *ib,
255 unsigned vm_id, bool ctx_switch)
257 u32 vmid = vm_id & 0xf;
258 u32 next_rptr = ring->wptr + 5;
260 while ((next_rptr & 7) != 2)
265 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) |
266 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR));
267 amdgpu_ring_write(ring, lower_32_bits(ring->next_rptr_gpu_addr) & 0xfffffffc);
268 amdgpu_ring_write(ring, upper_32_bits(ring->next_rptr_gpu_addr));
269 amdgpu_ring_write(ring, SDMA_PKT_WRITE_UNTILED_DW_3_COUNT(1));
270 amdgpu_ring_write(ring, next_rptr);
272 /* IB packet must end on a 8 DW boundary */
273 sdma_v2_4_ring_insert_nop(ring, (10 - (ring->wptr & 7)) % 8);
275 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_INDIRECT) |
276 SDMA_PKT_INDIRECT_HEADER_VMID(vmid));
277 /* base must be 32 byte aligned */
278 amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr) & 0xffffffe0);
279 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr));
280 amdgpu_ring_write(ring, ib->length_dw);
281 amdgpu_ring_write(ring, 0);
282 amdgpu_ring_write(ring, 0);
287 * sdma_v2_4_hdp_flush_ring_emit - emit an hdp flush on the DMA ring
289 * @ring: amdgpu ring pointer
291 * Emit an hdp flush packet on the requested DMA ring.
293 static void sdma_v2_4_ring_emit_hdp_flush(struct amdgpu_ring *ring)
295 u32 ref_and_mask = 0;
297 if (ring == &ring->adev->sdma.instance[0].ring)
298 ref_and_mask = REG_SET_FIELD(ref_and_mask, GPU_HDP_FLUSH_DONE, SDMA0, 1);
300 ref_and_mask = REG_SET_FIELD(ref_and_mask, GPU_HDP_FLUSH_DONE, SDMA1, 1);
302 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_POLL_REGMEM) |
303 SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(1) |
304 SDMA_PKT_POLL_REGMEM_HEADER_FUNC(3)); /* == */
305 amdgpu_ring_write(ring, mmGPU_HDP_FLUSH_DONE << 2);
306 amdgpu_ring_write(ring, mmGPU_HDP_FLUSH_REQ << 2);
307 amdgpu_ring_write(ring, ref_and_mask); /* reference */
308 amdgpu_ring_write(ring, ref_and_mask); /* mask */
309 amdgpu_ring_write(ring, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) |
310 SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(10)); /* retry count, poll interval */
313 static void sdma_v2_4_ring_emit_hdp_invalidate(struct amdgpu_ring *ring)
315 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_SRBM_WRITE) |
316 SDMA_PKT_SRBM_WRITE_HEADER_BYTE_EN(0xf));
317 amdgpu_ring_write(ring, mmHDP_DEBUG0);
318 amdgpu_ring_write(ring, 1);
321 * sdma_v2_4_ring_emit_fence - emit a fence on the DMA ring
323 * @ring: amdgpu ring pointer
324 * @fence: amdgpu fence object
326 * Add a DMA fence packet to the ring to write
327 * the fence seq number and DMA trap packet to generate
328 * an interrupt if needed (VI).
330 static void sdma_v2_4_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 seq,
333 bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT;
334 /* write the fence */
335 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_FENCE));
336 amdgpu_ring_write(ring, lower_32_bits(addr));
337 amdgpu_ring_write(ring, upper_32_bits(addr));
338 amdgpu_ring_write(ring, lower_32_bits(seq));
340 /* optionally write high bits as well */
343 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_FENCE));
344 amdgpu_ring_write(ring, lower_32_bits(addr));
345 amdgpu_ring_write(ring, upper_32_bits(addr));
346 amdgpu_ring_write(ring, upper_32_bits(seq));
349 /* generate an interrupt */
350 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_TRAP));
351 amdgpu_ring_write(ring, SDMA_PKT_TRAP_INT_CONTEXT_INT_CONTEXT(0));
355 * sdma_v2_4_gfx_stop - stop the gfx async dma engines
357 * @adev: amdgpu_device pointer
359 * Stop the gfx async dma ring buffers (VI).
361 static void sdma_v2_4_gfx_stop(struct amdgpu_device *adev)
363 struct amdgpu_ring *sdma0 = &adev->sdma.instance[0].ring;
364 struct amdgpu_ring *sdma1 = &adev->sdma.instance[1].ring;
365 u32 rb_cntl, ib_cntl;
368 if ((adev->mman.buffer_funcs_ring == sdma0) ||
369 (adev->mman.buffer_funcs_ring == sdma1))
370 amdgpu_ttm_set_active_vram_size(adev, adev->mc.visible_vram_size);
372 for (i = 0; i < adev->sdma.num_instances; i++) {
373 rb_cntl = RREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i]);
374 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_ENABLE, 0);
375 WREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i], rb_cntl);
376 ib_cntl = RREG32(mmSDMA0_GFX_IB_CNTL + sdma_offsets[i]);
377 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_ENABLE, 0);
378 WREG32(mmSDMA0_GFX_IB_CNTL + sdma_offsets[i], ib_cntl);
380 sdma0->ready = false;
381 sdma1->ready = false;
385 * sdma_v2_4_rlc_stop - stop the compute async dma engines
387 * @adev: amdgpu_device pointer
389 * Stop the compute async dma queues (VI).
391 static void sdma_v2_4_rlc_stop(struct amdgpu_device *adev)
397 * sdma_v2_4_enable - stop the async dma engines
399 * @adev: amdgpu_device pointer
400 * @enable: enable/disable the DMA MEs.
402 * Halt or unhalt the async dma engines (VI).
404 static void sdma_v2_4_enable(struct amdgpu_device *adev, bool enable)
409 if (enable == false) {
410 sdma_v2_4_gfx_stop(adev);
411 sdma_v2_4_rlc_stop(adev);
414 for (i = 0; i < adev->sdma.num_instances; i++) {
415 f32_cntl = RREG32(mmSDMA0_F32_CNTL + sdma_offsets[i]);
417 f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_F32_CNTL, HALT, 0);
419 f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_F32_CNTL, HALT, 1);
420 WREG32(mmSDMA0_F32_CNTL + sdma_offsets[i], f32_cntl);
425 * sdma_v2_4_gfx_resume - setup and start the async dma engines
427 * @adev: amdgpu_device pointer
429 * Set up the gfx DMA ring buffers and enable them (VI).
430 * Returns 0 for success, error for failure.
432 static int sdma_v2_4_gfx_resume(struct amdgpu_device *adev)
434 struct amdgpu_ring *ring;
435 u32 rb_cntl, ib_cntl;
440 for (i = 0; i < adev->sdma.num_instances; i++) {
441 ring = &adev->sdma.instance[i].ring;
442 wb_offset = (ring->rptr_offs * 4);
444 mutex_lock(&adev->srbm_mutex);
445 for (j = 0; j < 16; j++) {
446 vi_srbm_select(adev, 0, 0, 0, j);
448 WREG32(mmSDMA0_GFX_VIRTUAL_ADDR + sdma_offsets[i], 0);
449 WREG32(mmSDMA0_GFX_APE1_CNTL + sdma_offsets[i], 0);
451 vi_srbm_select(adev, 0, 0, 0, 0);
452 mutex_unlock(&adev->srbm_mutex);
454 WREG32(mmSDMA0_TILING_CONFIG + sdma_offsets[i],
455 adev->gfx.config.gb_addr_config & 0x70);
457 WREG32(mmSDMA0_SEM_WAIT_FAIL_TIMER_CNTL + sdma_offsets[i], 0);
459 /* Set ring buffer size in dwords */
460 rb_bufsz = order_base_2(ring->ring_size / 4);
461 rb_cntl = RREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i]);
462 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_SIZE, rb_bufsz);
464 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_SWAP_ENABLE, 1);
465 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL,
466 RPTR_WRITEBACK_SWAP_ENABLE, 1);
468 WREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i], rb_cntl);
470 /* Initialize the ring buffer's read and write pointers */
471 WREG32(mmSDMA0_GFX_RB_RPTR + sdma_offsets[i], 0);
472 WREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[i], 0);
473 WREG32(mmSDMA0_GFX_IB_RPTR + sdma_offsets[i], 0);
474 WREG32(mmSDMA0_GFX_IB_OFFSET + sdma_offsets[i], 0);
476 /* set the wb address whether it's enabled or not */
477 WREG32(mmSDMA0_GFX_RB_RPTR_ADDR_HI + sdma_offsets[i],
478 upper_32_bits(adev->wb.gpu_addr + wb_offset) & 0xFFFFFFFF);
479 WREG32(mmSDMA0_GFX_RB_RPTR_ADDR_LO + sdma_offsets[i],
480 lower_32_bits(adev->wb.gpu_addr + wb_offset) & 0xFFFFFFFC);
482 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RPTR_WRITEBACK_ENABLE, 1);
484 WREG32(mmSDMA0_GFX_RB_BASE + sdma_offsets[i], ring->gpu_addr >> 8);
485 WREG32(mmSDMA0_GFX_RB_BASE_HI + sdma_offsets[i], ring->gpu_addr >> 40);
488 WREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[i], ring->wptr << 2);
491 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_ENABLE, 1);
492 WREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i], rb_cntl);
494 ib_cntl = RREG32(mmSDMA0_GFX_IB_CNTL + sdma_offsets[i]);
495 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_ENABLE, 1);
497 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_SWAP_ENABLE, 1);
500 WREG32(mmSDMA0_GFX_IB_CNTL + sdma_offsets[i], ib_cntl);
505 sdma_v2_4_enable(adev, true);
506 for (i = 0; i < adev->sdma.num_instances; i++) {
507 ring = &adev->sdma.instance[i].ring;
508 r = amdgpu_ring_test_ring(ring);
514 if (adev->mman.buffer_funcs_ring == ring)
515 amdgpu_ttm_set_active_vram_size(adev, adev->mc.real_vram_size);
522 * sdma_v2_4_rlc_resume - setup and start the async dma engines
524 * @adev: amdgpu_device pointer
526 * Set up the compute DMA queues and enable them (VI).
527 * Returns 0 for success, error for failure.
529 static int sdma_v2_4_rlc_resume(struct amdgpu_device *adev)
536 * sdma_v2_4_load_microcode - load the sDMA ME ucode
538 * @adev: amdgpu_device pointer
540 * Loads the sDMA0/1 ucode.
541 * Returns 0 for success, -EINVAL if the ucode is not available.
543 static int sdma_v2_4_load_microcode(struct amdgpu_device *adev)
545 const struct sdma_firmware_header_v1_0 *hdr;
546 const __le32 *fw_data;
551 sdma_v2_4_enable(adev, false);
553 for (i = 0; i < adev->sdma.num_instances; i++) {
554 if (!adev->sdma.instance[i].fw)
556 hdr = (const struct sdma_firmware_header_v1_0 *)adev->sdma.instance[i].fw->data;
557 amdgpu_ucode_print_sdma_hdr(&hdr->header);
558 fw_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4;
559 fw_data = (const __le32 *)
560 (adev->sdma.instance[i].fw->data +
561 le32_to_cpu(hdr->header.ucode_array_offset_bytes));
562 WREG32(mmSDMA0_UCODE_ADDR + sdma_offsets[i], 0);
563 for (j = 0; j < fw_size; j++)
564 WREG32(mmSDMA0_UCODE_DATA + sdma_offsets[i], le32_to_cpup(fw_data++));
565 WREG32(mmSDMA0_UCODE_ADDR + sdma_offsets[i], adev->sdma.instance[i].fw_version);
572 * sdma_v2_4_start - setup and start the async dma engines
574 * @adev: amdgpu_device pointer
576 * Set up the DMA engines and enable them (VI).
577 * Returns 0 for success, error for failure.
579 static int sdma_v2_4_start(struct amdgpu_device *adev)
583 if (!adev->firmware.smu_load) {
584 r = sdma_v2_4_load_microcode(adev);
588 r = adev->smu.smumgr_funcs->check_fw_load_finish(adev,
589 AMDGPU_UCODE_ID_SDMA0);
592 r = adev->smu.smumgr_funcs->check_fw_load_finish(adev,
593 AMDGPU_UCODE_ID_SDMA1);
598 /* halt the engine before programing */
599 sdma_v2_4_enable(adev, false);
601 /* start the gfx rings and rlc compute queues */
602 r = sdma_v2_4_gfx_resume(adev);
605 r = sdma_v2_4_rlc_resume(adev);
613 * sdma_v2_4_ring_test_ring - simple async dma engine test
615 * @ring: amdgpu_ring structure holding ring information
617 * Test the DMA engine by writing using it to write an
618 * value to memory. (VI).
619 * Returns 0 for success, error for failure.
621 static int sdma_v2_4_ring_test_ring(struct amdgpu_ring *ring)
623 struct amdgpu_device *adev = ring->adev;
630 r = amdgpu_wb_get(adev, &index);
632 dev_err(adev->dev, "(%d) failed to allocate wb slot\n", r);
636 gpu_addr = adev->wb.gpu_addr + (index * 4);
638 adev->wb.wb[index] = cpu_to_le32(tmp);
640 r = amdgpu_ring_alloc(ring, 5);
642 DRM_ERROR("amdgpu: dma failed to lock ring %d (%d).\n", ring->idx, r);
643 amdgpu_wb_free(adev, index);
647 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) |
648 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR));
649 amdgpu_ring_write(ring, lower_32_bits(gpu_addr));
650 amdgpu_ring_write(ring, upper_32_bits(gpu_addr));
651 amdgpu_ring_write(ring, SDMA_PKT_WRITE_UNTILED_DW_3_COUNT(1));
652 amdgpu_ring_write(ring, 0xDEADBEEF);
653 amdgpu_ring_commit(ring);
655 for (i = 0; i < adev->usec_timeout; i++) {
656 tmp = le32_to_cpu(adev->wb.wb[index]);
657 if (tmp == 0xDEADBEEF)
662 if (i < adev->usec_timeout) {
663 DRM_INFO("ring test on %d succeeded in %d usecs\n", ring->idx, i);
665 DRM_ERROR("amdgpu: ring %d test failed (0x%08X)\n",
669 amdgpu_wb_free(adev, index);
675 * sdma_v2_4_ring_test_ib - test an IB on the DMA engine
677 * @ring: amdgpu_ring structure holding ring information
679 * Test a simple IB in the DMA ring (VI).
680 * Returns 0 on success, error on failure.
682 static int sdma_v2_4_ring_test_ib(struct amdgpu_ring *ring)
684 struct amdgpu_device *adev = ring->adev;
686 struct fence *f = NULL;
693 r = amdgpu_wb_get(adev, &index);
695 dev_err(adev->dev, "(%d) failed to allocate wb slot\n", r);
699 gpu_addr = adev->wb.gpu_addr + (index * 4);
701 adev->wb.wb[index] = cpu_to_le32(tmp);
702 memset(&ib, 0, sizeof(ib));
703 r = amdgpu_ib_get(adev, NULL, 256, &ib);
705 DRM_ERROR("amdgpu: failed to get ib (%d).\n", r);
709 ib.ptr[0] = SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) |
710 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR);
711 ib.ptr[1] = lower_32_bits(gpu_addr);
712 ib.ptr[2] = upper_32_bits(gpu_addr);
713 ib.ptr[3] = SDMA_PKT_WRITE_UNTILED_DW_3_COUNT(1);
714 ib.ptr[4] = 0xDEADBEEF;
715 ib.ptr[5] = SDMA_PKT_HEADER_OP(SDMA_OP_NOP);
716 ib.ptr[6] = SDMA_PKT_HEADER_OP(SDMA_OP_NOP);
717 ib.ptr[7] = SDMA_PKT_HEADER_OP(SDMA_OP_NOP);
720 r = amdgpu_ib_schedule(ring, 1, &ib, NULL, NULL, &f);
724 r = fence_wait(f, false);
726 DRM_ERROR("amdgpu: fence wait failed (%d).\n", r);
729 for (i = 0; i < adev->usec_timeout; i++) {
730 tmp = le32_to_cpu(adev->wb.wb[index]);
731 if (tmp == 0xDEADBEEF)
735 if (i < adev->usec_timeout) {
736 DRM_INFO("ib test on ring %d succeeded in %u usecs\n",
740 DRM_ERROR("amdgpu: ib test failed (0x%08X)\n", tmp);
746 amdgpu_ib_free(adev, &ib, NULL);
749 amdgpu_wb_free(adev, index);
754 * sdma_v2_4_vm_copy_pte - update PTEs by copying them from the GART
756 * @ib: indirect buffer to fill with commands
757 * @pe: addr of the page entry
758 * @src: src addr to copy from
759 * @count: number of page entries to update
761 * Update PTEs by copying them from the GART using sDMA (CIK).
763 static void sdma_v2_4_vm_copy_pte(struct amdgpu_ib *ib,
764 uint64_t pe, uint64_t src,
768 unsigned bytes = count * 8;
769 if (bytes > 0x1FFFF8)
772 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_COPY) |
773 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_COPY_LINEAR);
774 ib->ptr[ib->length_dw++] = bytes;
775 ib->ptr[ib->length_dw++] = 0; /* src/dst endian swap */
776 ib->ptr[ib->length_dw++] = lower_32_bits(src);
777 ib->ptr[ib->length_dw++] = upper_32_bits(src);
778 ib->ptr[ib->length_dw++] = lower_32_bits(pe);
779 ib->ptr[ib->length_dw++] = upper_32_bits(pe);
788 * sdma_v2_4_vm_write_pte - update PTEs by writing them manually
790 * @ib: indirect buffer to fill with commands
791 * @pe: addr of the page entry
792 * @addr: dst addr to write into pe
793 * @count: number of page entries to update
794 * @incr: increase next addr by incr bytes
795 * @flags: access flags
797 * Update PTEs by writing them manually using sDMA (CIK).
799 static void sdma_v2_4_vm_write_pte(struct amdgpu_ib *ib,
800 const dma_addr_t *pages_addr, uint64_t pe,
801 uint64_t addr, unsigned count,
802 uint32_t incr, uint32_t flags)
812 /* for non-physically contiguous pages (system) */
813 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) |
814 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_COPY_LINEAR);
815 ib->ptr[ib->length_dw++] = pe;
816 ib->ptr[ib->length_dw++] = upper_32_bits(pe);
817 ib->ptr[ib->length_dw++] = ndw;
818 for (; ndw > 0; ndw -= 2, --count, pe += 8) {
819 value = amdgpu_vm_map_gart(pages_addr, addr);
822 ib->ptr[ib->length_dw++] = value;
823 ib->ptr[ib->length_dw++] = upper_32_bits(value);
829 * sdma_v2_4_vm_set_pte_pde - update the page tables using sDMA
831 * @ib: indirect buffer to fill with commands
832 * @pe: addr of the page entry
833 * @addr: dst addr to write into pe
834 * @count: number of page entries to update
835 * @incr: increase next addr by incr bytes
836 * @flags: access flags
838 * Update the page tables using sDMA (CIK).
840 static void sdma_v2_4_vm_set_pte_pde(struct amdgpu_ib *ib,
842 uint64_t addr, unsigned count,
843 uint32_t incr, uint32_t flags)
853 if (flags & AMDGPU_PTE_VALID)
858 /* for physically contiguous pages (vram) */
859 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_GEN_PTEPDE);
860 ib->ptr[ib->length_dw++] = pe; /* dst addr */
861 ib->ptr[ib->length_dw++] = upper_32_bits(pe);
862 ib->ptr[ib->length_dw++] = flags; /* mask */
863 ib->ptr[ib->length_dw++] = 0;
864 ib->ptr[ib->length_dw++] = value; /* value */
865 ib->ptr[ib->length_dw++] = upper_32_bits(value);
866 ib->ptr[ib->length_dw++] = incr; /* increment size */
867 ib->ptr[ib->length_dw++] = 0;
868 ib->ptr[ib->length_dw++] = ndw; /* number of entries */
877 * sdma_v2_4_ring_pad_ib - pad the IB to the required number of dw
879 * @ib: indirect buffer to fill with padding
882 static void sdma_v2_4_ring_pad_ib(struct amdgpu_ring *ring, struct amdgpu_ib *ib)
884 struct amdgpu_sdma_instance *sdma = amdgpu_get_sdma_instance(ring);
888 pad_count = (8 - (ib->length_dw & 0x7)) % 8;
889 for (i = 0; i < pad_count; i++)
890 if (sdma && sdma->burst_nop && (i == 0))
891 ib->ptr[ib->length_dw++] =
892 SDMA_PKT_HEADER_OP(SDMA_OP_NOP) |
893 SDMA_PKT_NOP_HEADER_COUNT(pad_count - 1);
895 ib->ptr[ib->length_dw++] =
896 SDMA_PKT_HEADER_OP(SDMA_OP_NOP);
900 * sdma_v2_4_ring_emit_pipeline_sync - sync the pipeline
902 * @ring: amdgpu_ring pointer
904 * Make sure all previous operations are completed (CIK).
906 static void sdma_v2_4_ring_emit_pipeline_sync(struct amdgpu_ring *ring)
908 uint32_t seq = ring->fence_drv.sync_seq;
909 uint64_t addr = ring->fence_drv.gpu_addr;
912 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_POLL_REGMEM) |
913 SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(0) |
914 SDMA_PKT_POLL_REGMEM_HEADER_FUNC(3) | /* equal */
915 SDMA_PKT_POLL_REGMEM_HEADER_MEM_POLL(1));
916 amdgpu_ring_write(ring, addr & 0xfffffffc);
917 amdgpu_ring_write(ring, upper_32_bits(addr) & 0xffffffff);
918 amdgpu_ring_write(ring, seq); /* reference */
919 amdgpu_ring_write(ring, 0xfffffff); /* mask */
920 amdgpu_ring_write(ring, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) |
921 SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(4)); /* retry count, poll interval */
925 * sdma_v2_4_ring_emit_vm_flush - cik vm flush using sDMA
927 * @ring: amdgpu_ring pointer
928 * @vm: amdgpu_vm pointer
930 * Update the page table base and flush the VM TLB
933 static void sdma_v2_4_ring_emit_vm_flush(struct amdgpu_ring *ring,
934 unsigned vm_id, uint64_t pd_addr)
936 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_SRBM_WRITE) |
937 SDMA_PKT_SRBM_WRITE_HEADER_BYTE_EN(0xf));
939 amdgpu_ring_write(ring, (mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR + vm_id));
941 amdgpu_ring_write(ring, (mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR + vm_id - 8));
943 amdgpu_ring_write(ring, pd_addr >> 12);
946 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_SRBM_WRITE) |
947 SDMA_PKT_SRBM_WRITE_HEADER_BYTE_EN(0xf));
948 amdgpu_ring_write(ring, mmVM_INVALIDATE_REQUEST);
949 amdgpu_ring_write(ring, 1 << vm_id);
952 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_POLL_REGMEM) |
953 SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(0) |
954 SDMA_PKT_POLL_REGMEM_HEADER_FUNC(0)); /* always */
955 amdgpu_ring_write(ring, mmVM_INVALIDATE_REQUEST << 2);
956 amdgpu_ring_write(ring, 0);
957 amdgpu_ring_write(ring, 0); /* reference */
958 amdgpu_ring_write(ring, 0); /* mask */
959 amdgpu_ring_write(ring, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) |
960 SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(10)); /* retry count, poll interval */
963 static int sdma_v2_4_early_init(void *handle)
965 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
967 adev->sdma.num_instances = SDMA_MAX_INSTANCE;
969 sdma_v2_4_set_ring_funcs(adev);
970 sdma_v2_4_set_buffer_funcs(adev);
971 sdma_v2_4_set_vm_pte_funcs(adev);
972 sdma_v2_4_set_irq_funcs(adev);
977 static int sdma_v2_4_sw_init(void *handle)
979 struct amdgpu_ring *ring;
981 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
983 /* SDMA trap event */
984 r = amdgpu_irq_add_id(adev, 224, &adev->sdma.trap_irq);
988 /* SDMA Privileged inst */
989 r = amdgpu_irq_add_id(adev, 241, &adev->sdma.illegal_inst_irq);
993 /* SDMA Privileged inst */
994 r = amdgpu_irq_add_id(adev, 247, &adev->sdma.illegal_inst_irq);
998 r = sdma_v2_4_init_microcode(adev);
1000 DRM_ERROR("Failed to load sdma firmware!\n");
1004 for (i = 0; i < adev->sdma.num_instances; i++) {
1005 ring = &adev->sdma.instance[i].ring;
1006 ring->ring_obj = NULL;
1007 ring->use_doorbell = false;
1008 sprintf(ring->name, "sdma%d", i);
1009 r = amdgpu_ring_init(adev, ring, 1024,
1010 SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP), 0xf,
1011 &adev->sdma.trap_irq,
1013 AMDGPU_SDMA_IRQ_TRAP0 : AMDGPU_SDMA_IRQ_TRAP1,
1014 AMDGPU_RING_TYPE_SDMA);
1022 static int sdma_v2_4_sw_fini(void *handle)
1024 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1027 for (i = 0; i < adev->sdma.num_instances; i++)
1028 amdgpu_ring_fini(&adev->sdma.instance[i].ring);
1030 sdma_v2_4_free_microcode(adev);
1034 static int sdma_v2_4_hw_init(void *handle)
1037 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1039 sdma_v2_4_init_golden_registers(adev);
1041 r = sdma_v2_4_start(adev);
1048 static int sdma_v2_4_hw_fini(void *handle)
1050 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1052 sdma_v2_4_enable(adev, false);
1057 static int sdma_v2_4_suspend(void *handle)
1059 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1061 return sdma_v2_4_hw_fini(adev);
1064 static int sdma_v2_4_resume(void *handle)
1066 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1068 return sdma_v2_4_hw_init(adev);
1071 static bool sdma_v2_4_is_idle(void *handle)
1073 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1074 u32 tmp = RREG32(mmSRBM_STATUS2);
1076 if (tmp & (SRBM_STATUS2__SDMA_BUSY_MASK |
1077 SRBM_STATUS2__SDMA1_BUSY_MASK))
1083 static int sdma_v2_4_wait_for_idle(void *handle)
1087 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1089 for (i = 0; i < adev->usec_timeout; i++) {
1090 tmp = RREG32(mmSRBM_STATUS2) & (SRBM_STATUS2__SDMA_BUSY_MASK |
1091 SRBM_STATUS2__SDMA1_BUSY_MASK);
1100 static int sdma_v2_4_soft_reset(void *handle)
1102 u32 srbm_soft_reset = 0;
1103 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1104 u32 tmp = RREG32(mmSRBM_STATUS2);
1106 if (tmp & SRBM_STATUS2__SDMA_BUSY_MASK) {
1108 tmp = RREG32(mmSDMA0_F32_CNTL + SDMA0_REGISTER_OFFSET);
1109 tmp = REG_SET_FIELD(tmp, SDMA0_F32_CNTL, HALT, 0);
1110 WREG32(mmSDMA0_F32_CNTL + SDMA0_REGISTER_OFFSET, tmp);
1111 srbm_soft_reset |= SRBM_SOFT_RESET__SOFT_RESET_SDMA_MASK;
1113 if (tmp & SRBM_STATUS2__SDMA1_BUSY_MASK) {
1115 tmp = RREG32(mmSDMA0_F32_CNTL + SDMA1_REGISTER_OFFSET);
1116 tmp = REG_SET_FIELD(tmp, SDMA0_F32_CNTL, HALT, 0);
1117 WREG32(mmSDMA0_F32_CNTL + SDMA1_REGISTER_OFFSET, tmp);
1118 srbm_soft_reset |= SRBM_SOFT_RESET__SOFT_RESET_SDMA1_MASK;
1121 if (srbm_soft_reset) {
1122 tmp = RREG32(mmSRBM_SOFT_RESET);
1123 tmp |= srbm_soft_reset;
1124 dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp);
1125 WREG32(mmSRBM_SOFT_RESET, tmp);
1126 tmp = RREG32(mmSRBM_SOFT_RESET);
1130 tmp &= ~srbm_soft_reset;
1131 WREG32(mmSRBM_SOFT_RESET, tmp);
1132 tmp = RREG32(mmSRBM_SOFT_RESET);
1134 /* Wait a little for things to settle down */
1141 static int sdma_v2_4_set_trap_irq_state(struct amdgpu_device *adev,
1142 struct amdgpu_irq_src *src,
1144 enum amdgpu_interrupt_state state)
1149 case AMDGPU_SDMA_IRQ_TRAP0:
1151 case AMDGPU_IRQ_STATE_DISABLE:
1152 sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET);
1153 sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE, 0);
1154 WREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET, sdma_cntl);
1156 case AMDGPU_IRQ_STATE_ENABLE:
1157 sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET);
1158 sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE, 1);
1159 WREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET, sdma_cntl);
1165 case AMDGPU_SDMA_IRQ_TRAP1:
1167 case AMDGPU_IRQ_STATE_DISABLE:
1168 sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET);
1169 sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE, 0);
1170 WREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET, sdma_cntl);
1172 case AMDGPU_IRQ_STATE_ENABLE:
1173 sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET);
1174 sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE, 1);
1175 WREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET, sdma_cntl);
1187 static int sdma_v2_4_process_trap_irq(struct amdgpu_device *adev,
1188 struct amdgpu_irq_src *source,
1189 struct amdgpu_iv_entry *entry)
1191 u8 instance_id, queue_id;
1193 instance_id = (entry->ring_id & 0x3) >> 0;
1194 queue_id = (entry->ring_id & 0xc) >> 2;
1195 DRM_DEBUG("IH: SDMA trap\n");
1196 switch (instance_id) {
1200 amdgpu_fence_process(&adev->sdma.instance[0].ring);
1213 amdgpu_fence_process(&adev->sdma.instance[1].ring);
1227 static int sdma_v2_4_process_illegal_inst_irq(struct amdgpu_device *adev,
1228 struct amdgpu_irq_src *source,
1229 struct amdgpu_iv_entry *entry)
1231 DRM_ERROR("Illegal instruction in SDMA command stream\n");
1232 schedule_work(&adev->reset_work);
1236 static int sdma_v2_4_set_clockgating_state(void *handle,
1237 enum amd_clockgating_state state)
1239 /* XXX handled via the smc on VI */
1243 static int sdma_v2_4_set_powergating_state(void *handle,
1244 enum amd_powergating_state state)
1249 const struct amd_ip_funcs sdma_v2_4_ip_funcs = {
1250 .name = "sdma_v2_4",
1251 .early_init = sdma_v2_4_early_init,
1253 .sw_init = sdma_v2_4_sw_init,
1254 .sw_fini = sdma_v2_4_sw_fini,
1255 .hw_init = sdma_v2_4_hw_init,
1256 .hw_fini = sdma_v2_4_hw_fini,
1257 .suspend = sdma_v2_4_suspend,
1258 .resume = sdma_v2_4_resume,
1259 .is_idle = sdma_v2_4_is_idle,
1260 .wait_for_idle = sdma_v2_4_wait_for_idle,
1261 .soft_reset = sdma_v2_4_soft_reset,
1262 .set_clockgating_state = sdma_v2_4_set_clockgating_state,
1263 .set_powergating_state = sdma_v2_4_set_powergating_state,
1266 static const struct amdgpu_ring_funcs sdma_v2_4_ring_funcs = {
1267 .get_rptr = sdma_v2_4_ring_get_rptr,
1268 .get_wptr = sdma_v2_4_ring_get_wptr,
1269 .set_wptr = sdma_v2_4_ring_set_wptr,
1271 .emit_ib = sdma_v2_4_ring_emit_ib,
1272 .emit_fence = sdma_v2_4_ring_emit_fence,
1273 .emit_pipeline_sync = sdma_v2_4_ring_emit_pipeline_sync,
1274 .emit_vm_flush = sdma_v2_4_ring_emit_vm_flush,
1275 .emit_hdp_flush = sdma_v2_4_ring_emit_hdp_flush,
1276 .emit_hdp_invalidate = sdma_v2_4_ring_emit_hdp_invalidate,
1277 .test_ring = sdma_v2_4_ring_test_ring,
1278 .test_ib = sdma_v2_4_ring_test_ib,
1279 .insert_nop = sdma_v2_4_ring_insert_nop,
1280 .pad_ib = sdma_v2_4_ring_pad_ib,
1283 static void sdma_v2_4_set_ring_funcs(struct amdgpu_device *adev)
1287 for (i = 0; i < adev->sdma.num_instances; i++)
1288 adev->sdma.instance[i].ring.funcs = &sdma_v2_4_ring_funcs;
1291 static const struct amdgpu_irq_src_funcs sdma_v2_4_trap_irq_funcs = {
1292 .set = sdma_v2_4_set_trap_irq_state,
1293 .process = sdma_v2_4_process_trap_irq,
1296 static const struct amdgpu_irq_src_funcs sdma_v2_4_illegal_inst_irq_funcs = {
1297 .process = sdma_v2_4_process_illegal_inst_irq,
1300 static void sdma_v2_4_set_irq_funcs(struct amdgpu_device *adev)
1302 adev->sdma.trap_irq.num_types = AMDGPU_SDMA_IRQ_LAST;
1303 adev->sdma.trap_irq.funcs = &sdma_v2_4_trap_irq_funcs;
1304 adev->sdma.illegal_inst_irq.funcs = &sdma_v2_4_illegal_inst_irq_funcs;
1308 * sdma_v2_4_emit_copy_buffer - copy buffer using the sDMA engine
1310 * @ring: amdgpu_ring structure holding ring information
1311 * @src_offset: src GPU address
1312 * @dst_offset: dst GPU address
1313 * @byte_count: number of bytes to xfer
1315 * Copy GPU buffers using the DMA engine (VI).
1316 * Used by the amdgpu ttm implementation to move pages if
1317 * registered as the asic copy callback.
1319 static void sdma_v2_4_emit_copy_buffer(struct amdgpu_ib *ib,
1320 uint64_t src_offset,
1321 uint64_t dst_offset,
1322 uint32_t byte_count)
1324 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_COPY) |
1325 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_COPY_LINEAR);
1326 ib->ptr[ib->length_dw++] = byte_count;
1327 ib->ptr[ib->length_dw++] = 0; /* src/dst endian swap */
1328 ib->ptr[ib->length_dw++] = lower_32_bits(src_offset);
1329 ib->ptr[ib->length_dw++] = upper_32_bits(src_offset);
1330 ib->ptr[ib->length_dw++] = lower_32_bits(dst_offset);
1331 ib->ptr[ib->length_dw++] = upper_32_bits(dst_offset);
1335 * sdma_v2_4_emit_fill_buffer - fill buffer using the sDMA engine
1337 * @ring: amdgpu_ring structure holding ring information
1338 * @src_data: value to write to buffer
1339 * @dst_offset: dst GPU address
1340 * @byte_count: number of bytes to xfer
1342 * Fill GPU buffers using the DMA engine (VI).
1344 static void sdma_v2_4_emit_fill_buffer(struct amdgpu_ib *ib,
1346 uint64_t dst_offset,
1347 uint32_t byte_count)
1349 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_CONST_FILL);
1350 ib->ptr[ib->length_dw++] = lower_32_bits(dst_offset);
1351 ib->ptr[ib->length_dw++] = upper_32_bits(dst_offset);
1352 ib->ptr[ib->length_dw++] = src_data;
1353 ib->ptr[ib->length_dw++] = byte_count;
1356 static const struct amdgpu_buffer_funcs sdma_v2_4_buffer_funcs = {
1357 .copy_max_bytes = 0x1fffff,
1359 .emit_copy_buffer = sdma_v2_4_emit_copy_buffer,
1361 .fill_max_bytes = 0x1fffff,
1363 .emit_fill_buffer = sdma_v2_4_emit_fill_buffer,
1366 static void sdma_v2_4_set_buffer_funcs(struct amdgpu_device *adev)
1368 if (adev->mman.buffer_funcs == NULL) {
1369 adev->mman.buffer_funcs = &sdma_v2_4_buffer_funcs;
1370 adev->mman.buffer_funcs_ring = &adev->sdma.instance[0].ring;
1374 static const struct amdgpu_vm_pte_funcs sdma_v2_4_vm_pte_funcs = {
1375 .copy_pte = sdma_v2_4_vm_copy_pte,
1376 .write_pte = sdma_v2_4_vm_write_pte,
1377 .set_pte_pde = sdma_v2_4_vm_set_pte_pde,
1380 static void sdma_v2_4_set_vm_pte_funcs(struct amdgpu_device *adev)
1384 if (adev->vm_manager.vm_pte_funcs == NULL) {
1385 adev->vm_manager.vm_pte_funcs = &sdma_v2_4_vm_pte_funcs;
1386 for (i = 0; i < adev->sdma.num_instances; i++)
1387 adev->vm_manager.vm_pte_rings[i] =
1388 &adev->sdma.instance[i].ring;
1390 adev->vm_manager.vm_pte_num_rings = adev->sdma.num_instances;