drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c

   1 /*
   2  * Copyright 2019 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23
  24 #include <linux/firmware.h>
  25 #include <drm/drmP.h>
  26 #include "amdgpu.h"
  27 #include "amdgpu_ucode.h"
  28 #include "amdgpu_trace.h"
  29
  30 #include "gc/gc_10_1_0_offset.h"
  31 #include "gc/gc_10_1_0_sh_mask.h"
  32 #include "hdp/hdp_5_0_0_offset.h"
  33 #include "ivsrcid/sdma0/irqsrcs_sdma0_5_0.h"
  34 #include "ivsrcid/sdma1/irqsrcs_sdma1_5_0.h"
  35
  36 #include "soc15_common.h"
  37 #include "soc15.h"
  38 #include "navi10_sdma_pkt_open.h"
  39 #include "nbio_v2_3.h"
  40 #include "sdma_v5_0.h"
  41
  42 MODULE_FIRMWARE("amdgpu/navi10_sdma.bin");
  43 MODULE_FIRMWARE("amdgpu/navi10_sdma1.bin");
  44
  45 MODULE_FIRMWARE("amdgpu/navi14_sdma.bin");
  46 MODULE_FIRMWARE("amdgpu/navi14_sdma1.bin");
  47
  48 #define SDMA1_REG_OFFSET 0x600
  49 #define SDMA0_HYP_DEC_REG_START 0x5880
  50 #define SDMA0_HYP_DEC_REG_END 0x5893
  51 #define SDMA1_HYP_DEC_REG_OFFSET 0x20
  52
  53 static void sdma_v5_0_set_ring_funcs(struct amdgpu_device *adev);
  54 static void sdma_v5_0_set_buffer_funcs(struct amdgpu_device *adev);
  55 static void sdma_v5_0_set_vm_pte_funcs(struct amdgpu_device *adev);
  56 static void sdma_v5_0_set_irq_funcs(struct amdgpu_device *adev);
  57
  58 static const struct soc15_reg_golden golden_settings_sdma_5[] = {
  59         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_CHICKEN_BITS, 0xffbf1f0f, 0x03ab0107),
  60         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_GFX_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
  61         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_PAGE_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
  62         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC0_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
  63         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC1_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
  64         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC2_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
  65         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC3_RB_WPTR_POLL_CNTL, 0x0000fff0, 0x00403000),
  66         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC4_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
  67         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC5_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
  68         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC6_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
  69         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC7_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
  70         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_UTCL1_PAGE, 0x00ffffff, 0x000c5c00),
  71         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_CHICKEN_BITS, 0xffbf1f0f, 0x03ab0107),
  72         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_GFX_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
  73         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_PAGE_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
  74         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC0_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
  75         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC1_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
  76         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC2_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
  77         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC3_RB_WPTR_POLL_CNTL, 0x0000fff0, 0x00403000),
  78         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC4_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
  79         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC5_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
  80         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC6_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
  81         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC7_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
  82         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_UTCL1_PAGE, 0x00ffffff, 0x000c5c00)
  83 };
  84
  85 static const struct soc15_reg_golden golden_settings_sdma_nv10[] = {
  86 };
  87
  88 static const struct soc15_reg_golden golden_settings_sdma_nv14[] = {
  89 };
  90
  91 static u32 sdma_v5_0_get_reg_offset(struct amdgpu_device *adev, u32 instance, u32 internal_offset)
  92 {
  93         u32 base;
  94
  95         if (internal_offset >= SDMA0_HYP_DEC_REG_START &&
  96             internal_offset <= SDMA0_HYP_DEC_REG_END) {
  97                 base = adev->reg_offset[GC_HWIP][0][1];
  98                 if (instance == 1)
  99                         internal_offset += SDMA1_HYP_DEC_REG_OFFSET;
 100         } else {
 101                 base = adev->reg_offset[GC_HWIP][0][0];
 102                 if (instance == 1)
 103                         internal_offset += SDMA1_REG_OFFSET;
 104         }
 105
 106         return base + internal_offset;
 107 }
 108
 109 static void sdma_v5_0_init_golden_registers(struct amdgpu_device *adev)
 110 {
 111         switch (adev->asic_type) {
 112         case CHIP_NAVI10:
 113                 soc15_program_register_sequence(adev,
 114                                                 golden_settings_sdma_5,
 115                                                 (const u32)ARRAY_SIZE(golden_settings_sdma_5));
 116                 soc15_program_register_sequence(adev,
 117                                                 golden_settings_sdma_nv10,
 118                                                 (const u32)ARRAY_SIZE(golden_settings_sdma_nv10));
 119                 break;
 120         case CHIP_NAVI14:
 121                 soc15_program_register_sequence(adev,
 122                                                 golden_settings_sdma_5,
 123                                                 (const u32)ARRAY_SIZE(golden_settings_sdma_5));
 124                 soc15_program_register_sequence(adev,
 125                                                 golden_settings_sdma_nv14,
 126                                                 (const u32)ARRAY_SIZE(golden_settings_sdma_nv14));
 127                 break;
 128         default:
 129                 break;
 130         }
 131 }
 132
 133 /**
 134  * sdma_v5_0_init_microcode - load ucode images from disk
 135  *
 136  * @adev: amdgpu_device pointer
 137  *
 138  * Use the firmware interface to load the ucode images into
 139  * the driver (not loaded into hw).
 140  * Returns 0 on success, error on failure.
 141  */
 142
 143 // emulation only, won't work on real chip
 144 // navi10 real chip need to use PSP to load firmware
 145 static int sdma_v5_0_init_microcode(struct amdgpu_device *adev)
 146 {
 147         const char *chip_name;
 148         char fw_name[30];
 149         int err = 0, i;
 150         struct amdgpu_firmware_info *info = NULL;
 151         const struct common_firmware_header *header = NULL;
 152         const struct sdma_firmware_header_v1_0 *hdr;
 153
 154         DRM_DEBUG("\n");
 155
 156         switch (adev->asic_type) {
 157         case CHIP_NAVI10:
 158                 chip_name = "navi10";
 159                 break;
 160         case CHIP_NAVI14:
 161                 chip_name = "navi14";
 162                 break;
 163         default:
 164                 BUG();
 165         }
 166
 167         for (i = 0; i < adev->sdma.num_instances; i++) {
 168                 if (i == 0)
 169                         snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_sdma.bin", chip_name);
 170                 else
 171                         snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_sdma1.bin", chip_name);
 172                 err = request_firmware(&adev->sdma.instance[i].fw, fw_name, adev->dev);
 173                 if (err)
 174                         goto out;
 175                 err = amdgpu_ucode_validate(adev->sdma.instance[i].fw);
 176                 if (err)
 177                         goto out;
 178                 hdr = (const struct sdma_firmware_header_v1_0 *)adev->sdma.instance[i].fw->data;
 179                 adev->sdma.instance[i].fw_version = le32_to_cpu(hdr->header.ucode_version);
 180                 adev->sdma.instance[i].feature_version = le32_to_cpu(hdr->ucode_feature_version);
 181                 if (adev->sdma.instance[i].feature_version >= 20)
 182                         adev->sdma.instance[i].burst_nop = true;
 183                 DRM_DEBUG("psp_load == '%s'\n",
 184                                 adev->firmware.load_type == AMDGPU_FW_LOAD_PSP ? "true" : "false");
 185
 186                 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
 187                         info = &adev->firmware.ucode[AMDGPU_UCODE_ID_SDMA0 + i];
 188                         info->ucode_id = AMDGPU_UCODE_ID_SDMA0 + i;
 189                         info->fw = adev->sdma.instance[i].fw;
 190                         header = (const struct common_firmware_header *)info->fw->data;
 191                         adev->firmware.fw_size +=
 192                                 ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
 193                 }
 194         }
 195 out:
 196         if (err) {
 197                 DRM_ERROR("sdma_v5_0: Failed to load firmware \"%s\"\n", fw_name);
 198                 for (i = 0; i < adev->sdma.num_instances; i++) {
 199                         release_firmware(adev->sdma.instance[i].fw);
 200                         adev->sdma.instance[i].fw = NULL;
 201                 }
 202         }
 203         return err;
 204 }
 205
 206 static unsigned sdma_v5_0_ring_init_cond_exec(struct amdgpu_ring *ring)
 207 {
 208         unsigned ret;
 209
 210         amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_COND_EXE));
 211         amdgpu_ring_write(ring, lower_32_bits(ring->cond_exe_gpu_addr));
 212         amdgpu_ring_write(ring, upper_32_bits(ring->cond_exe_gpu_addr));
 213         amdgpu_ring_write(ring, 1);
 214         ret = ring->wptr & ring->buf_mask;/* this is the offset we need patch later */
 215         amdgpu_ring_write(ring, 0x55aa55aa);/* insert dummy here and patch it later */
 216
 217         return ret;
 218 }
 219
 220 static void sdma_v5_0_ring_patch_cond_exec(struct amdgpu_ring *ring,
 221                                            unsigned offset)
 222 {
 223         unsigned cur;
 224
 225         BUG_ON(offset > ring->buf_mask);
 226         BUG_ON(ring->ring[offset] != 0x55aa55aa);
 227
 228         cur = (ring->wptr - 1) & ring->buf_mask;
 229         if (cur > offset)
 230                 ring->ring[offset] = cur - offset;
 231         else
 232                 ring->ring[offset] = (ring->buf_mask + 1) - offset + cur;
 233 }
 234
 235 /**
 236  * sdma_v5_0_ring_get_rptr - get the current read pointer
 237  *
 238  * @ring: amdgpu ring pointer
 239  *
 240  * Get the current rptr from the hardware (NAVI10+).
 241  */
 242 static uint64_t sdma_v5_0_ring_get_rptr(struct amdgpu_ring *ring)
 243 {
 244         u64 *rptr;
 245
 246         /* XXX check if swapping is necessary on BE */
 247         rptr = ((u64 *)&ring->adev->wb.wb[ring->rptr_offs]);
 248
 249         DRM_DEBUG("rptr before shift == 0x%016llx\n", *rptr);
 250         return ((*rptr) >> 2);
 251 }
 252
 253 /**
 254  * sdma_v5_0_ring_get_wptr - get the current write pointer
 255  *
 256  * @ring: amdgpu ring pointer
 257  *
 258  * Get the current wptr from the hardware (NAVI10+).
 259  */
 260 static uint64_t sdma_v5_0_ring_get_wptr(struct amdgpu_ring *ring)
 261 {
 262         struct amdgpu_device *adev = ring->adev;
 263         u64 *wptr = NULL;
 264         uint64_t local_wptr = 0;
 265
 266         if (ring->use_doorbell) {
 267                 /* XXX check if swapping is necessary on BE */
 268                 wptr = ((u64 *)&adev->wb.wb[ring->wptr_offs]);
 269                 DRM_DEBUG("wptr/doorbell before shift == 0x%016llx\n", *wptr);
 270                 *wptr = (*wptr) >> 2;
 271                 DRM_DEBUG("wptr/doorbell after shift == 0x%016llx\n", *wptr);
 272         } else {
 273                 u32 lowbit, highbit;
 274
 275                 wptr = &local_wptr;
 276                 lowbit = RREG32(sdma_v5_0_get_reg_offset(adev, ring->me, mmSDMA0_GFX_RB_WPTR)) >> 2;
 277                 highbit = RREG32(sdma_v5_0_get_reg_offset(adev, ring->me, mmSDMA0_GFX_RB_WPTR_HI)) >> 2;
 278
 279                 DRM_DEBUG("wptr [%i]high== 0x%08x low==0x%08x\n",
 280                                 ring->me, highbit, lowbit);
 281                 *wptr = highbit;
 282                 *wptr = (*wptr) << 32;
 283                 *wptr |= lowbit;
 284         }
 285
 286         return *wptr;
 287 }
 288
 289 /**
 290  * sdma_v5_0_ring_set_wptr - commit the write pointer
 291  *
 292  * @ring: amdgpu ring pointer
 293  *
 294  * Write the wptr back to the hardware (NAVI10+).
 295  */
 296 static void sdma_v5_0_ring_set_wptr(struct amdgpu_ring *ring)
 297 {
 298         struct amdgpu_device *adev = ring->adev;
 299
 300         DRM_DEBUG("Setting write pointer\n");
 301         if (ring->use_doorbell) {
 302                 DRM_DEBUG("Using doorbell -- "
 303                                 "wptr_offs == 0x%08x "
 304                                 "lower_32_bits(ring->wptr) << 2 == 0x%08x "
 305                                 "upper_32_bits(ring->wptr) << 2 == 0x%08x\n",
 306                                 ring->wptr_offs,
 307                                 lower_32_bits(ring->wptr << 2),
 308                                 upper_32_bits(ring->wptr << 2));
 309                 /* XXX check if swapping is necessary on BE */
 310                 adev->wb.wb[ring->wptr_offs] = lower_32_bits(ring->wptr << 2);
 311                 adev->wb.wb[ring->wptr_offs + 1] = upper_32_bits(ring->wptr << 2);
 312                 DRM_DEBUG("calling WDOORBELL64(0x%08x, 0x%016llx)\n",
 313                                 ring->doorbell_index, ring->wptr << 2);
 314                 WDOORBELL64(ring->doorbell_index, ring->wptr << 2);
 315         } else {
 316                 DRM_DEBUG("Not using doorbell -- "
 317                                 "mmSDMA%i_GFX_RB_WPTR == 0x%08x "
 318                                 "mmSDMA%i_GFX_RB_WPTR_HI == 0x%08x\n",
 319                                 ring->me,
 320                                 lower_32_bits(ring->wptr << 2),
 321                                 ring->me,
 322                                 upper_32_bits(ring->wptr << 2));
 323                 WREG32(sdma_v5_0_get_reg_offset(adev, ring->me, mmSDMA0_GFX_RB_WPTR),
 324                         lower_32_bits(ring->wptr << 2));
 325                 WREG32(sdma_v5_0_get_reg_offset(adev, ring->me, mmSDMA0_GFX_RB_WPTR_HI),
 326                         upper_32_bits(ring->wptr << 2));
 327         }
 328 }
 329
 330 static void sdma_v5_0_ring_insert_nop(struct amdgpu_ring *ring, uint32_t count)
 331 {
 332         struct amdgpu_sdma_instance *sdma = amdgpu_sdma_get_instance_from_ring(ring);
 333         int i;
 334
 335         for (i = 0; i < count; i++)
 336                 if (sdma && sdma->burst_nop && (i == 0))
 337                         amdgpu_ring_write(ring, ring->funcs->nop |
 338                                 SDMA_PKT_NOP_HEADER_COUNT(count - 1));
 339                 else
 340                         amdgpu_ring_write(ring, ring->funcs->nop);
 341 }
 342
 343 /**
 344  * sdma_v5_0_ring_emit_ib - Schedule an IB on the DMA engine
 345  *
 346  * @ring: amdgpu ring pointer
 347  * @ib: IB object to schedule
 348  *
 349  * Schedule an IB in the DMA ring (NAVI10).
 350  */
 351 static void sdma_v5_0_ring_emit_ib(struct amdgpu_ring *ring,
 352                                    struct amdgpu_job *job,
 353                                    struct amdgpu_ib *ib,
 354                                    uint32_t flags)
 355 {
 356         unsigned vmid = AMDGPU_JOB_GET_VMID(job);
 357         uint64_t csa_mc_addr = amdgpu_sdma_get_csa_mc_addr(ring, vmid);
 358
 359         /* IB packet must end on a 8 DW boundary */
 360         sdma_v5_0_ring_insert_nop(ring, (10 - (lower_32_bits(ring->wptr) & 7)) % 8);
 361
 362         amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_INDIRECT) |
 363                           SDMA_PKT_INDIRECT_HEADER_VMID(vmid & 0xf));
 364         /* base must be 32 byte aligned */
 365         amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr) & 0xffffffe0);
 366         amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr));
 367         amdgpu_ring_write(ring, ib->length_dw);
 368         amdgpu_ring_write(ring, lower_32_bits(csa_mc_addr));
 369         amdgpu_ring_write(ring, upper_32_bits(csa_mc_addr));
 370 }
 371
 372 /**
 373  * sdma_v5_0_ring_emit_hdp_flush - emit an hdp flush on the DMA ring
 374  *
 375  * @ring: amdgpu ring pointer
 376  *
 377  * Emit an hdp flush packet on the requested DMA ring.
 378  */
 379 static void sdma_v5_0_ring_emit_hdp_flush(struct amdgpu_ring *ring)
 380 {
 381         struct amdgpu_device *adev = ring->adev;
 382         u32 ref_and_mask = 0;
 383         const struct nbio_hdp_flush_reg *nbio_hf_reg = adev->nbio_funcs->hdp_flush_reg;
 384
 385         if (ring->me == 0)
 386                 ref_and_mask = nbio_hf_reg->ref_and_mask_sdma0;
 387         else
 388                 ref_and_mask = nbio_hf_reg->ref_and_mask_sdma1;
 389
 390         amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_POLL_REGMEM) |
 391                           SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(1) |
 392                           SDMA_PKT_POLL_REGMEM_HEADER_FUNC(3)); /* == */
 393         amdgpu_ring_write(ring, (adev->nbio_funcs->get_hdp_flush_done_offset(adev)) << 2);
 394         amdgpu_ring_write(ring, (adev->nbio_funcs->get_hdp_flush_req_offset(adev)) << 2);
 395         amdgpu_ring_write(ring, ref_and_mask); /* reference */
 396         amdgpu_ring_write(ring, ref_and_mask); /* mask */
 397         amdgpu_ring_write(ring, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) |
 398                           SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(10)); /* retry count, poll interval */
 399 }
 400
 401 /**
 402  * sdma_v5_0_ring_emit_fence - emit a fence on the DMA ring
 403  *
 404  * @ring: amdgpu ring pointer
 405  * @fence: amdgpu fence object
 406  *
 407  * Add a DMA fence packet to the ring to write
 408  * the fence seq number and DMA trap packet to generate
 409  * an interrupt if needed (NAVI10).
 410  */
 411 static void sdma_v5_0_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 seq,
 412                                       unsigned flags)
 413 {
 414         struct amdgpu_device *adev = ring->adev;
 415         bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT;
 416         /* write the fence */
 417         amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_FENCE) |
 418                           SDMA_PKT_FENCE_HEADER_MTYPE(0x3)); /* Ucached(UC) */
 419         /* zero in first two bits */
 420         BUG_ON(addr & 0x3);
 421         amdgpu_ring_write(ring, lower_32_bits(addr));
 422         amdgpu_ring_write(ring, upper_32_bits(addr));
 423         amdgpu_ring_write(ring, lower_32_bits(seq));
 424
 425         /* optionally write high bits as well */
 426         if (write64bit) {
 427                 addr += 4;
 428                 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_FENCE) |
 429                                   SDMA_PKT_FENCE_HEADER_MTYPE(0x3));
 430                 /* zero in first two bits */
 431                 BUG_ON(addr & 0x3);
 432                 amdgpu_ring_write(ring, lower_32_bits(addr));
 433                 amdgpu_ring_write(ring, upper_32_bits(addr));
 434                 amdgpu_ring_write(ring, upper_32_bits(seq));
 435         }
 436
 437         /* Interrupt not work fine on GFX10.1 model yet. Use fallback instead */
 438         if ((flags & AMDGPU_FENCE_FLAG_INT) && adev->pdev->device != 0x50) {
 439                 /* generate an interrupt */
 440                 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_TRAP));
 441                 amdgpu_ring_write(ring, SDMA_PKT_TRAP_INT_CONTEXT_INT_CONTEXT(0));
 442         }
 443 }
 444
 445
 446 /**
 447  * sdma_v5_0_gfx_stop - stop the gfx async dma engines
 448  *
 449  * @adev: amdgpu_device pointer
 450  *
 451  * Stop the gfx async dma ring buffers (NAVI10).
 452  */
 453 static void sdma_v5_0_gfx_stop(struct amdgpu_device *adev)
 454 {
 455         struct amdgpu_ring *sdma0 = &adev->sdma.instance[0].ring;
 456         struct amdgpu_ring *sdma1 = &adev->sdma.instance[1].ring;
 457         u32 rb_cntl, ib_cntl;
 458         int i;
 459
 460         if ((adev->mman.buffer_funcs_ring == sdma0) ||
 461             (adev->mman.buffer_funcs_ring == sdma1))
 462                 amdgpu_ttm_set_buffer_funcs_status(adev, false);
 463
 464         for (i = 0; i < adev->sdma.num_instances; i++) {
 465                 rb_cntl = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_CNTL));
 466                 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_ENABLE, 0);
 467                 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_CNTL), rb_cntl);
 468                 ib_cntl = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_IB_CNTL));
 469                 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_ENABLE, 0);
 470                 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_IB_CNTL), ib_cntl);
 471         }
 472
 473         sdma0->sched.ready = false;
 474         sdma1->sched.ready = false;
 475 }
 476
 477 /**
 478  * sdma_v5_0_rlc_stop - stop the compute async dma engines
 479  *
 480  * @adev: amdgpu_device pointer
 481  *
 482  * Stop the compute async dma queues (NAVI10).
 483  */
 484 static void sdma_v5_0_rlc_stop(struct amdgpu_device *adev)
 485 {
 486         /* XXX todo */
 487 }
 488
 489 /**
 490  * sdma_v_0_ctx_switch_enable - stop the async dma engines context switch
 491  *
 492  * @adev: amdgpu_device pointer
 493  * @enable: enable/disable the DMA MEs context switch.
 494  *
 495  * Halt or unhalt the async dma engines context switch (NAVI10).
 496  */
 497 static void sdma_v5_0_ctx_switch_enable(struct amdgpu_device *adev, bool enable)
 498 {
 499         u32 f32_cntl, phase_quantum = 0;
 500         int i;
 501
 502         if (amdgpu_sdma_phase_quantum) {
 503                 unsigned value = amdgpu_sdma_phase_quantum;
 504                 unsigned unit = 0;
 505
 506                 while (value > (SDMA0_PHASE0_QUANTUM__VALUE_MASK >>
 507                                 SDMA0_PHASE0_QUANTUM__VALUE__SHIFT)) {
 508                         value = (value + 1) >> 1;
 509                         unit++;
 510                 }
 511                 if (unit > (SDMA0_PHASE0_QUANTUM__UNIT_MASK >>
 512                             SDMA0_PHASE0_QUANTUM__UNIT__SHIFT)) {
 513                         value = (SDMA0_PHASE0_QUANTUM__VALUE_MASK >>
 514                                  SDMA0_PHASE0_QUANTUM__VALUE__SHIFT);
 515                         unit = (SDMA0_PHASE0_QUANTUM__UNIT_MASK >>
 516                                 SDMA0_PHASE0_QUANTUM__UNIT__SHIFT);
 517                         WARN_ONCE(1,
 518                         "clamping sdma_phase_quantum to %uK clock cycles\n",
 519                                   value << unit);
 520                 }
 521                 phase_quantum =
 522                         value << SDMA0_PHASE0_QUANTUM__VALUE__SHIFT |
 523                         unit  << SDMA0_PHASE0_QUANTUM__UNIT__SHIFT;
 524         }
 525
 526         for (i = 0; i < adev->sdma.num_instances; i++) {
 527                 f32_cntl = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_CNTL));
 528                 f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_CNTL,
 529                                 AUTO_CTXSW_ENABLE, enable ? 1 : 0);
 530                 if (enable && amdgpu_sdma_phase_quantum) {
 531                         WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_PHASE0_QUANTUM),
 532                                phase_quantum);
 533                         WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_PHASE1_QUANTUM),
 534                                phase_quantum);
 535                         WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_PHASE2_QUANTUM),
 536                                phase_quantum);
 537                 }
 538                 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_CNTL), f32_cntl);
 539         }
 540
 541 }
 542
 543 /**
 544  * sdma_v5_0_enable - stop the async dma engines
 545  *
 546  * @adev: amdgpu_device pointer
 547  * @enable: enable/disable the DMA MEs.
 548  *
 549  * Halt or unhalt the async dma engines (NAVI10).
 550  */
 551 static void sdma_v5_0_enable(struct amdgpu_device *adev, bool enable)
 552 {
 553         u32 f32_cntl;
 554         int i;
 555
 556         if (enable == false) {
 557                 sdma_v5_0_gfx_stop(adev);
 558                 sdma_v5_0_rlc_stop(adev);
 559         }
 560
 561         for (i = 0; i < adev->sdma.num_instances; i++) {
 562                 f32_cntl = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_F32_CNTL));
 563                 f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_F32_CNTL, HALT, enable ? 0 : 1);
 564                 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_F32_CNTL), f32_cntl);
 565         }
 566 }
 567
 568 /**
 569  * sdma_v5_0_gfx_resume - setup and start the async dma engines
 570  *
 571  * @adev: amdgpu_device pointer
 572  *
 573  * Set up the gfx DMA ring buffers and enable them (NAVI10).
 574  * Returns 0 for success, error for failure.
 575  */
 576 static int sdma_v5_0_gfx_resume(struct amdgpu_device *adev)
 577 {
 578         struct amdgpu_ring *ring;
 579         u32 rb_cntl, ib_cntl;
 580         u32 rb_bufsz;
 581         u32 wb_offset;
 582         u32 doorbell;
 583         u32 doorbell_offset;
 584         u32 temp;
 585         u32 wptr_poll_cntl;
 586         u64 wptr_gpu_addr;
 587         int i, r;
 588
 589         for (i = 0; i < adev->sdma.num_instances; i++) {
 590                 ring = &adev->sdma.instance[i].ring;
 591                 wb_offset = (ring->rptr_offs * 4);
 592
 593                 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_SEM_WAIT_FAIL_TIMER_CNTL), 0);
 594
 595                 /* Set ring buffer size in dwords */
 596                 rb_bufsz = order_base_2(ring->ring_size / 4);
 597                 rb_cntl = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_CNTL));
 598                 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_SIZE, rb_bufsz);
 599 #ifdef __BIG_ENDIAN
 600                 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_SWAP_ENABLE, 1);
 601                 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL,
 602                                         RPTR_WRITEBACK_SWAP_ENABLE, 1);
 603 #endif
 604                 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_CNTL), rb_cntl);
 605
 606                 /* Initialize the ring buffer's read and write pointers */
 607                 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_RPTR), 0);
 608                 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_RPTR_HI), 0);
 609                 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR), 0);
 610                 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR_HI), 0);
 611
 612                 /* setup the wptr shadow polling */
 613                 wptr_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4);
 614                 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR_POLL_ADDR_LO),
 615                        lower_32_bits(wptr_gpu_addr));
 616                 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR_POLL_ADDR_HI),
 617                        upper_32_bits(wptr_gpu_addr));
 618                 wptr_poll_cntl = RREG32(sdma_v5_0_get_reg_offset(adev, i,
 619                                                          mmSDMA0_GFX_RB_WPTR_POLL_CNTL));
 620                 wptr_poll_cntl = REG_SET_FIELD(wptr_poll_cntl,
 621                                                SDMA0_GFX_RB_WPTR_POLL_CNTL,
 622                                                F32_POLL_ENABLE, 1);
 623                 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR_POLL_CNTL),
 624                        wptr_poll_cntl);
 625
 626                 /* set the wb address whether it's enabled or not */
 627                 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_RPTR_ADDR_HI),
 628                        upper_32_bits(adev->wb.gpu_addr + wb_offset) & 0xFFFFFFFF);
 629                 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_RPTR_ADDR_LO),
 630                        lower_32_bits(adev->wb.gpu_addr + wb_offset) & 0xFFFFFFFC);
 631
 632                 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RPTR_WRITEBACK_ENABLE, 1);
 633
 634                 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_BASE), ring->gpu_addr >> 8);
 635                 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_BASE_HI), ring->gpu_addr >> 40);
 636
 637                 ring->wptr = 0;
 638
 639                 /* before programing wptr to a less value, need set minor_ptr_update first */
 640                 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_MINOR_PTR_UPDATE), 1);
 641
 642                 if (!amdgpu_sriov_vf(adev)) { /* only bare-metal use register write for wptr */
 643                         WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR), lower_32_bits(ring->wptr) << 2);
 644                         WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR_HI), upper_32_bits(ring->wptr) << 2);
 645                 }
 646
 647                 doorbell = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_DOORBELL));
 648                 doorbell_offset = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_DOORBELL_OFFSET));
 649
 650                 if (ring->use_doorbell) {
 651                         doorbell = REG_SET_FIELD(doorbell, SDMA0_GFX_DOORBELL, ENABLE, 1);
 652                         doorbell_offset = REG_SET_FIELD(doorbell_offset, SDMA0_GFX_DOORBELL_OFFSET,
 653                                         OFFSET, ring->doorbell_index);
 654                 } else {
 655                         doorbell = REG_SET_FIELD(doorbell, SDMA0_GFX_DOORBELL, ENABLE, 0);
 656                 }
 657                 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_DOORBELL), doorbell);
 658                 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_DOORBELL_OFFSET), doorbell_offset);
 659
 660                 adev->nbio_funcs->sdma_doorbell_range(adev, i, ring->use_doorbell,
 661                                                       ring->doorbell_index, 20);
 662
 663                 if (amdgpu_sriov_vf(adev))
 664                         sdma_v5_0_ring_set_wptr(ring);
 665
 666                 /* set minor_ptr_update to 0 after wptr programed */
 667                 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_MINOR_PTR_UPDATE), 0);
 668
 669                 /* set utc l1 enable flag always to 1 */
 670                 temp = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_CNTL));
 671                 temp = REG_SET_FIELD(temp, SDMA0_CNTL, UTC_L1_ENABLE, 1);
 672
 673                 /* enable MCBP */
 674                 temp = REG_SET_FIELD(temp, SDMA0_CNTL, MIDCMD_PREEMPT_ENABLE, 1);
 675                 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_CNTL), temp);
 676
 677                 /* Set up RESP_MODE to non-copy addresses */
 678                 temp = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_UTCL1_CNTL));
 679                 temp = REG_SET_FIELD(temp, SDMA0_UTCL1_CNTL, RESP_MODE, 3);
 680                 temp = REG_SET_FIELD(temp, SDMA0_UTCL1_CNTL, REDO_DELAY, 9);
 681                 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_UTCL1_CNTL), temp);
 682
 683                 /* program default cache read and write policy */
 684                 temp = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_UTCL1_PAGE));
 685                 /* clean read policy and write policy bits */
 686                 temp &= 0xFF0FFF;
 687                 temp |= ((CACHE_READ_POLICY_L2__DEFAULT << 12) | (CACHE_WRITE_POLICY_L2__DEFAULT << 14));
 688                 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_UTCL1_PAGE), temp);
 689
 690                 if (!amdgpu_sriov_vf(adev)) {
 691                         /* unhalt engine */
 692                         temp = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_F32_CNTL));
 693                         temp = REG_SET_FIELD(temp, SDMA0_F32_CNTL, HALT, 0);
 694                         WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_F32_CNTL), temp);
 695                 }
 696
 697                 /* enable DMA RB */
 698                 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_ENABLE, 1);
 699                 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_CNTL), rb_cntl);
 700
 701                 ib_cntl = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_IB_CNTL));
 702                 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_ENABLE, 1);
 703 #ifdef __BIG_ENDIAN
 704                 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_SWAP_ENABLE, 1);
 705 #endif
 706                 /* enable DMA IBs */
 707                 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_IB_CNTL), ib_cntl);
 708
 709                 ring->sched.ready = true;
 710
 711                 if (amdgpu_sriov_vf(adev)) { /* bare-metal sequence doesn't need below to lines */
 712                         sdma_v5_0_ctx_switch_enable(adev, true);
 713                         sdma_v5_0_enable(adev, true);
 714                 }
 715
 716                 r = amdgpu_ring_test_ring(ring);
 717                 if (r) {
 718                         ring->sched.ready = false;
 719                         return r;
 720                 }
 721
 722                 if (adev->mman.buffer_funcs_ring == ring)
 723                         amdgpu_ttm_set_buffer_funcs_status(adev, true);
 724         }
 725
 726         return 0;
 727 }
 728
 729 /**
 730  * sdma_v5_0_rlc_resume - setup and start the async dma engines
 731  *
 732  * @adev: amdgpu_device pointer
 733  *
 734  * Set up the compute DMA queues and enable them (NAVI10).
 735  * Returns 0 for success, error for failure.
 736  */
 737 static int sdma_v5_0_rlc_resume(struct amdgpu_device *adev)
 738 {
 739         return 0;
 740 }
 741
 742 /**
 743  * sdma_v5_0_load_microcode - load the sDMA ME ucode
 744  *
 745  * @adev: amdgpu_device pointer
 746  *
 747  * Loads the sDMA0/1 ucode.
 748  * Returns 0 for success, -EINVAL if the ucode is not available.
 749  */
 750 static int sdma_v5_0_load_microcode(struct amdgpu_device *adev)
 751 {
 752         const struct sdma_firmware_header_v1_0 *hdr;
 753         const __le32 *fw_data;
 754         u32 fw_size;
 755         int i, j;
 756
 757         /* halt the MEs */
 758         sdma_v5_0_enable(adev, false);
 759
 760         for (i = 0; i < adev->sdma.num_instances; i++) {
 761                 if (!adev->sdma.instance[i].fw)
 762                         return -EINVAL;
 763
 764                 hdr = (const struct sdma_firmware_header_v1_0 *)adev->sdma.instance[i].fw->data;
 765                 amdgpu_ucode_print_sdma_hdr(&hdr->header);
 766                 fw_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4;
 767
 768                 fw_data = (const __le32 *)
 769                         (adev->sdma.instance[i].fw->data +
 770                                 le32_to_cpu(hdr->header.ucode_array_offset_bytes));
 771
 772                 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_UCODE_ADDR), 0);
 773
 774                 for (j = 0; j < fw_size; j++) {
 775                         if (amdgpu_emu_mode == 1 && j % 500 == 0)
 776                                 msleep(1);
 777                         WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_UCODE_DATA), le32_to_cpup(fw_data++));
 778                 }
 779
 780                 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_UCODE_ADDR), adev->sdma.instance[i].fw_version);
 781         }
 782
 783         return 0;
 784 }
 785
 786 /**
 787  * sdma_v5_0_start - setup and start the async dma engines
 788  *
 789  * @adev: amdgpu_device pointer
 790  *
 791  * Set up the DMA engines and enable them (NAVI10).
 792  * Returns 0 for success, error for failure.
 793  */
 794 static int sdma_v5_0_start(struct amdgpu_device *adev)
 795 {
 796         int r = 0;
 797
 798         if (amdgpu_sriov_vf(adev)) {
 799                 sdma_v5_0_ctx_switch_enable(adev, false);
 800                 sdma_v5_0_enable(adev, false);
 801
 802                 /* set RB registers */
 803                 r = sdma_v5_0_gfx_resume(adev);
 804                 return r;
 805         }
 806
 807         if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) {
 808                 r = sdma_v5_0_load_microcode(adev);
 809                 if (r)
 810                         return r;
 811
 812                 /* The value of mmSDMA_F32_CNTL is invalid the moment after loading fw */
 813                 if (amdgpu_emu_mode == 1 && adev->pdev->device == 0x4d)
 814                         msleep(1000);
 815         }
 816
 817         /* unhalt the MEs */
 818         sdma_v5_0_enable(adev, true);
 819         /* enable sdma ring preemption */
 820         sdma_v5_0_ctx_switch_enable(adev, true);
 821
 822         /* start the gfx rings and rlc compute queues */
 823         r = sdma_v5_0_gfx_resume(adev);
 824         if (r)
 825                 return r;
 826         r = sdma_v5_0_rlc_resume(adev);
 827
 828         return r;
 829 }
 830
 831 /**
 832  * sdma_v5_0_ring_test_ring - simple async dma engine test
 833  *
 834  * @ring: amdgpu_ring structure holding ring information
 835  *
 836  * Test the DMA engine by writing using it to write an
 837  * value to memory. (NAVI10).
 838  * Returns 0 for success, error for failure.
 839  */
 840 static int sdma_v5_0_ring_test_ring(struct amdgpu_ring *ring)
 841 {
 842         struct amdgpu_device *adev = ring->adev;
 843         unsigned i;
 844         unsigned index;
 845         int r;
 846         u32 tmp;
 847         u64 gpu_addr;
 848
 849         r = amdgpu_device_wb_get(adev, &index);
 850         if (r) {
 851                 dev_err(adev->dev, "(%d) failed to allocate wb slot\n", r);
 852                 return r;
 853         }
 854
 855         gpu_addr = adev->wb.gpu_addr + (index * 4);
 856         tmp = 0xCAFEDEAD;
 857         adev->wb.wb[index] = cpu_to_le32(tmp);
 858
 859         r = amdgpu_ring_alloc(ring, 5);
 860         if (r) {
 861                 DRM_ERROR("amdgpu: dma failed to lock ring %d (%d).\n", ring->idx, r);
 862                 amdgpu_device_wb_free(adev, index);
 863                 return r;
 864         }
 865
 866         amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) |
 867                           SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR));
 868         amdgpu_ring_write(ring, lower_32_bits(gpu_addr));
 869         amdgpu_ring_write(ring, upper_32_bits(gpu_addr));
 870         amdgpu_ring_write(ring, SDMA_PKT_WRITE_UNTILED_DW_3_COUNT(0));
 871         amdgpu_ring_write(ring, 0xDEADBEEF);
 872         amdgpu_ring_commit(ring);
 873
 874         for (i = 0; i < adev->usec_timeout; i++) {
 875                 tmp = le32_to_cpu(adev->wb.wb[index]);
 876                 if (tmp == 0xDEADBEEF)
 877                         break;
 878                 if (amdgpu_emu_mode == 1)
 879                         msleep(1);
 880                 else
 881                         DRM_UDELAY(1);
 882         }
 883
 884         if (i < adev->usec_timeout) {
 885                 if (amdgpu_emu_mode == 1)
 886                         DRM_INFO("ring test on %d succeeded in %d msecs\n", ring->idx, i);
 887                 else
 888                         DRM_INFO("ring test on %d succeeded in %d usecs\n", ring->idx, i);
 889         } else {
 890                 DRM_ERROR("amdgpu: ring %d test failed (0x%08X)\n",
 891                           ring->idx, tmp);
 892                 r = -EINVAL;
 893         }
 894         amdgpu_device_wb_free(adev, index);
 895
 896         return r;
 897 }
 898
 899 /**
 900  * sdma_v5_0_ring_test_ib - test an IB on the DMA engine
 901  *
 902  * @ring: amdgpu_ring structure holding ring information
 903  *
 904  * Test a simple IB in the DMA ring (NAVI10).
 905  * Returns 0 on success, error on failure.
 906  */
 907 static int sdma_v5_0_ring_test_ib(struct amdgpu_ring *ring, long timeout)
 908 {
 909         struct amdgpu_device *adev = ring->adev;
 910         struct amdgpu_ib ib;
 911         struct dma_fence *f = NULL;
 912         unsigned index;
 913         long r;
 914         u32 tmp = 0;
 915         u64 gpu_addr;
 916
 917         r = amdgpu_device_wb_get(adev, &index);
 918         if (r) {
 919                 dev_err(adev->dev, "(%ld) failed to allocate wb slot\n", r);
 920                 return r;
 921         }
 922
 923         gpu_addr = adev->wb.gpu_addr + (index * 4);
 924         tmp = 0xCAFEDEAD;
 925         adev->wb.wb[index] = cpu_to_le32(tmp);
 926         memset(&ib, 0, sizeof(ib));
 927         r = amdgpu_ib_get(adev, NULL, 256, &ib);
 928         if (r) {
 929                 DRM_ERROR("amdgpu: failed to get ib (%ld).\n", r);
 930                 goto err0;
 931         }
 932
 933         ib.ptr[0] = SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) |
 934                 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR);
 935         ib.ptr[1] = lower_32_bits(gpu_addr);
 936         ib.ptr[2] = upper_32_bits(gpu_addr);
 937         ib.ptr[3] = SDMA_PKT_WRITE_UNTILED_DW_3_COUNT(0);
 938         ib.ptr[4] = 0xDEADBEEF;
 939         ib.ptr[5] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP);
 940         ib.ptr[6] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP);
 941         ib.ptr[7] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP);
 942         ib.length_dw = 8;
 943
 944         r = amdgpu_ib_schedule(ring, 1, &ib, NULL, &f);
 945         if (r)
 946                 goto err1;
 947
 948         r = dma_fence_wait_timeout(f, false, timeout);
 949         if (r == 0) {
 950                 DRM_ERROR("amdgpu: IB test timed out\n");
 951                 r = -ETIMEDOUT;
 952                 goto err1;
 953         } else if (r < 0) {
 954                 DRM_ERROR("amdgpu: fence wait failed (%ld).\n", r);
 955                 goto err1;
 956         }
 957         tmp = le32_to_cpu(adev->wb.wb[index]);
 958         if (tmp == 0xDEADBEEF) {
 959                 DRM_INFO("ib test on ring %d succeeded\n", ring->idx);
 960                 r = 0;
 961         } else {
 962                 DRM_ERROR("amdgpu: ib test failed (0x%08X)\n", tmp);
 963                 r = -EINVAL;
 964         }
 965
 966 err1:
 967         amdgpu_ib_free(adev, &ib, NULL);
 968         dma_fence_put(f);
 969 err0:
 970         amdgpu_device_wb_free(adev, index);
 971         return r;
 972 }
 973
 974
 975 /**
 976  * sdma_v5_0_vm_copy_pte - update PTEs by copying them from the GART
 977  *
 978  * @ib: indirect buffer to fill with commands
 979  * @pe: addr of the page entry
 980  * @src: src addr to copy from
 981  * @count: number of page entries to update
 982  *
 983  * Update PTEs by copying them from the GART using sDMA (NAVI10).
 984  */
 985 static void sdma_v5_0_vm_copy_pte(struct amdgpu_ib *ib,
 986                                   uint64_t pe, uint64_t src,
 987                                   unsigned count)
 988 {
 989         unsigned bytes = count * 8;
 990
 991         ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_COPY) |
 992                 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_COPY_LINEAR);
 993         ib->ptr[ib->length_dw++] = bytes - 1;
 994         ib->ptr[ib->length_dw++] = 0; /* src/dst endian swap */
 995         ib->ptr[ib->length_dw++] = lower_32_bits(src);
 996         ib->ptr[ib->length_dw++] = upper_32_bits(src);
 997         ib->ptr[ib->length_dw++] = lower_32_bits(pe);
 998         ib->ptr[ib->length_dw++] = upper_32_bits(pe);
 999
1000 }
1001
1002 /**
1003  * sdma_v5_0_vm_write_pte - update PTEs by writing them manually
1004  *
1005  * @ib: indirect buffer to fill with commands
1006  * @pe: addr of the page entry
1007  * @addr: dst addr to write into pe
1008  * @count: number of page entries to update
1009  * @incr: increase next addr by incr bytes
1010  * @flags: access flags
1011  *
1012  * Update PTEs by writing them manually using sDMA (NAVI10).
1013  */
1014 static void sdma_v5_0_vm_write_pte(struct amdgpu_ib *ib, uint64_t pe,
1015                                    uint64_t value, unsigned count,
1016                                    uint32_t incr)
1017 {
1018         unsigned ndw = count * 2;
1019
1020         ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) |
1021                 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR);
1022         ib->ptr[ib->length_dw++] = lower_32_bits(pe);
1023         ib->ptr[ib->length_dw++] = upper_32_bits(pe);
1024         ib->ptr[ib->length_dw++] = ndw - 1;
1025         for (; ndw > 0; ndw -= 2) {
1026                 ib->ptr[ib->length_dw++] = lower_32_bits(value);
1027                 ib->ptr[ib->length_dw++] = upper_32_bits(value);
1028                 value += incr;
1029         }
1030 }
1031
1032 /**
1033  * sdma_v5_0_vm_set_pte_pde - update the page tables using sDMA
1034  *
1035  * @ib: indirect buffer to fill with commands
1036  * @pe: addr of the page entry
1037  * @addr: dst addr to write into pe
1038  * @count: number of page entries to update
1039  * @incr: increase next addr by incr bytes
1040  * @flags: access flags
1041  *
1042  * Update the page tables using sDMA (NAVI10).
1043  */
1044 static void sdma_v5_0_vm_set_pte_pde(struct amdgpu_ib *ib,
1045                                      uint64_t pe,
1046                                      uint64_t addr, unsigned count,
1047                                      uint32_t incr, uint64_t flags)
1048 {
1049         /* for physically contiguous pages (vram) */
1050         ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_PTEPDE);
1051         ib->ptr[ib->length_dw++] = lower_32_bits(pe); /* dst addr */
1052         ib->ptr[ib->length_dw++] = upper_32_bits(pe);
1053         ib->ptr[ib->length_dw++] = lower_32_bits(flags); /* mask */
1054         ib->ptr[ib->length_dw++] = upper_32_bits(flags);
1055         ib->ptr[ib->length_dw++] = lower_32_bits(addr); /* value */
1056         ib->ptr[ib->length_dw++] = upper_32_bits(addr);
1057         ib->ptr[ib->length_dw++] = incr; /* increment size */
1058         ib->ptr[ib->length_dw++] = 0;
1059         ib->ptr[ib->length_dw++] = count - 1; /* number of entries */
1060 }
1061
1062 /**
1063  * sdma_v5_0_ring_pad_ib - pad the IB to the required number of dw
1064  *
1065  * @ib: indirect buffer to fill with padding
1066  *
1067  */
1068 static void sdma_v5_0_ring_pad_ib(struct amdgpu_ring *ring, struct amdgpu_ib *ib)
1069 {
1070         struct amdgpu_sdma_instance *sdma = amdgpu_sdma_get_instance_from_ring(ring);
1071         u32 pad_count;
1072         int i;
1073
1074         pad_count = (8 - (ib->length_dw & 0x7)) % 8;
1075         for (i = 0; i < pad_count; i++)
1076                 if (sdma && sdma->burst_nop && (i == 0))
1077                         ib->ptr[ib->length_dw++] =
1078                                 SDMA_PKT_HEADER_OP(SDMA_OP_NOP) |
1079                                 SDMA_PKT_NOP_HEADER_COUNT(pad_count - 1);
1080                 else
1081                         ib->ptr[ib->length_dw++] =
1082                                 SDMA_PKT_HEADER_OP(SDMA_OP_NOP);
1083 }
1084
1085
1086 /**
1087  * sdma_v5_0_ring_emit_pipeline_sync - sync the pipeline
1088  *
1089  * @ring: amdgpu_ring pointer
1090  *
1091  * Make sure all previous operations are completed (CIK).
1092  */
1093 static void sdma_v5_0_ring_emit_pipeline_sync(struct amdgpu_ring *ring)
1094 {
1095         uint32_t seq = ring->fence_drv.sync_seq;
1096         uint64_t addr = ring->fence_drv.gpu_addr;
1097
1098         /* wait for idle */
1099         amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_POLL_REGMEM) |
1100                           SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(0) |
1101                           SDMA_PKT_POLL_REGMEM_HEADER_FUNC(3) | /* equal */
1102                           SDMA_PKT_POLL_REGMEM_HEADER_MEM_POLL(1));
1103         amdgpu_ring_write(ring, addr & 0xfffffffc);
1104         amdgpu_ring_write(ring, upper_32_bits(addr) & 0xffffffff);
1105         amdgpu_ring_write(ring, seq); /* reference */
1106         amdgpu_ring_write(ring, 0xfffffff); /* mask */
1107         amdgpu_ring_write(ring, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) |
1108                           SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(4)); /* retry count, poll interval */
1109 }
1110
1111
1112 /**
1113  * sdma_v5_0_ring_emit_vm_flush - vm flush using sDMA
1114  *
1115  * @ring: amdgpu_ring pointer
1116  * @vm: amdgpu_vm pointer
1117  *
1118  * Update the page table base and flush the VM TLB
1119  * using sDMA (NAVI10).
1120  */
1121 static void sdma_v5_0_ring_emit_vm_flush(struct amdgpu_ring *ring,
1122                                          unsigned vmid, uint64_t pd_addr)
1123 {
1124         amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr);
1125 }
1126
1127 static void sdma_v5_0_ring_emit_wreg(struct amdgpu_ring *ring,
1128                                      uint32_t reg, uint32_t val)
1129 {
1130         amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_SRBM_WRITE) |
1131                           SDMA_PKT_SRBM_WRITE_HEADER_BYTE_EN(0xf));
1132         amdgpu_ring_write(ring, reg);
1133         amdgpu_ring_write(ring, val);
1134 }
1135
1136 static void sdma_v5_0_ring_emit_reg_wait(struct amdgpu_ring *ring, uint32_t reg,
1137                                          uint32_t val, uint32_t mask)
1138 {
1139         amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_POLL_REGMEM) |
1140                           SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(0) |
1141                           SDMA_PKT_POLL_REGMEM_HEADER_FUNC(3)); /* equal */
1142         amdgpu_ring_write(ring, reg << 2);
1143         amdgpu_ring_write(ring, 0);
1144         amdgpu_ring_write(ring, val); /* reference */
1145         amdgpu_ring_write(ring, mask); /* mask */
1146         amdgpu_ring_write(ring, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) |
1147                           SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(10));
1148 }
1149
1150 static int sdma_v5_0_early_init(void *handle)
1151 {
1152         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1153
1154         adev->sdma.num_instances = 2;
1155
1156         sdma_v5_0_set_ring_funcs(adev);
1157         sdma_v5_0_set_buffer_funcs(adev);
1158         sdma_v5_0_set_vm_pte_funcs(adev);
1159         sdma_v5_0_set_irq_funcs(adev);
1160
1161         return 0;
1162 }
1163
1164
1165 static int sdma_v5_0_sw_init(void *handle)
1166 {
1167         struct amdgpu_ring *ring;
1168         int r, i;
1169         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1170
1171         /* SDMA trap event */
1172         r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_SDMA0,
1173                               SDMA0_5_0__SRCID__SDMA_TRAP,
1174                               &adev->sdma.trap_irq);
1175         if (r)
1176                 return r;
1177
1178         /* SDMA trap event */
1179         r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_SDMA1,
1180                               SDMA1_5_0__SRCID__SDMA_TRAP,
1181                               &adev->sdma.trap_irq);
1182         if (r)
1183                 return r;
1184
1185         r = sdma_v5_0_init_microcode(adev);
1186         if (r) {
1187                 DRM_ERROR("Failed to load sdma firmware!\n");
1188                 return r;
1189         }
1190
1191         for (i = 0; i < adev->sdma.num_instances; i++) {
1192                 ring = &adev->sdma.instance[i].ring;
1193                 ring->ring_obj = NULL;
1194                 ring->use_doorbell = true;
1195
1196                 DRM_INFO("use_doorbell being set to: [%s]\n",
1197                                 ring->use_doorbell?"true":"false");
1198
1199                 ring->doorbell_index = (i == 0) ?
1200                         (adev->doorbell_index.sdma_engine[0] << 1) //get DWORD offset
1201                         : (adev->doorbell_index.sdma_engine[1] << 1); // get DWORD offset
1202
1203                 sprintf(ring->name, "sdma%d", i);
1204                 r = amdgpu_ring_init(adev, ring, 1024,
1205                                      &adev->sdma.trap_irq,
1206                                      (i == 0) ?
1207                                      AMDGPU_SDMA_IRQ_INSTANCE0 :
1208                                      AMDGPU_SDMA_IRQ_INSTANCE1);
1209                 if (r)
1210                         return r;
1211         }
1212
1213         return r;
1214 }
1215
1216 static int sdma_v5_0_sw_fini(void *handle)
1217 {
1218         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1219         int i;
1220
1221         for (i = 0; i < adev->sdma.num_instances; i++)
1222                 amdgpu_ring_fini(&adev->sdma.instance[i].ring);
1223
1224         return 0;
1225 }
1226
1227 static int sdma_v5_0_hw_init(void *handle)
1228 {
1229         int r;
1230         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1231
1232         sdma_v5_0_init_golden_registers(adev);
1233
1234         r = sdma_v5_0_start(adev);
1235
1236         return r;
1237 }
1238
1239 static int sdma_v5_0_hw_fini(void *handle)
1240 {
1241         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1242
1243         if (amdgpu_sriov_vf(adev))
1244                 return 0;
1245
1246         sdma_v5_0_ctx_switch_enable(adev, false);
1247         sdma_v5_0_enable(adev, false);
1248
1249         return 0;
1250 }
1251
1252 static int sdma_v5_0_suspend(void *handle)
1253 {
1254         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1255
1256         return sdma_v5_0_hw_fini(adev);
1257 }
1258
1259 static int sdma_v5_0_resume(void *handle)
1260 {
1261         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1262
1263         return sdma_v5_0_hw_init(adev);
1264 }
1265
1266 static bool sdma_v5_0_is_idle(void *handle)
1267 {
1268         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1269         u32 i;
1270
1271         for (i = 0; i < adev->sdma.num_instances; i++) {
1272                 u32 tmp = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_STATUS_REG));
1273
1274                 if (!(tmp & SDMA0_STATUS_REG__IDLE_MASK))
1275                         return false;
1276         }
1277
1278         return true;
1279 }
1280
1281 static int sdma_v5_0_wait_for_idle(void *handle)
1282 {
1283         unsigned i;
1284         u32 sdma0, sdma1;
1285         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1286
1287         for (i = 0; i < adev->usec_timeout; i++) {
1288                 sdma0 = RREG32(sdma_v5_0_get_reg_offset(adev, 0, mmSDMA0_STATUS_REG));
1289                 sdma1 = RREG32(sdma_v5_0_get_reg_offset(adev, 1, mmSDMA0_STATUS_REG));
1290
1291                 if (sdma0 & sdma1 & SDMA0_STATUS_REG__IDLE_MASK)
1292                         return 0;
1293                 udelay(1);
1294         }
1295         return -ETIMEDOUT;
1296 }
1297
1298 static int sdma_v5_0_soft_reset(void *handle)
1299 {
1300         /* todo */
1301
1302         return 0;
1303 }
1304
1305 static int sdma_v5_0_ring_preempt_ib(struct amdgpu_ring *ring)
1306 {
1307         int i, r = 0;
1308         struct amdgpu_device *adev = ring->adev;
1309         u32 index = 0;
1310         u64 sdma_gfx_preempt;
1311
1312         amdgpu_sdma_get_index_from_ring(ring, &index);
1313         if (index == 0)
1314                 sdma_gfx_preempt = mmSDMA0_GFX_PREEMPT;
1315         else
1316                 sdma_gfx_preempt = mmSDMA1_GFX_PREEMPT;
1317
1318         /* assert preemption condition */
1319         amdgpu_ring_set_preempt_cond_exec(ring, false);
1320
1321         /* emit the trailing fence */
1322         ring->trail_seq += 1;
1323         amdgpu_ring_alloc(ring, 10);
1324         sdma_v5_0_ring_emit_fence(ring, ring->trail_fence_gpu_addr,
1325                                   ring->trail_seq, 0);
1326         amdgpu_ring_commit(ring);
1327
1328         /* assert IB preemption */
1329         WREG32(sdma_gfx_preempt, 1);
1330
1331         /* poll the trailing fence */
1332         for (i = 0; i < adev->usec_timeout; i++) {
1333                 if (ring->trail_seq ==
1334                     le32_to_cpu(*(ring->trail_fence_cpu_addr)))
1335                         break;
1336                 DRM_UDELAY(1);
1337         }
1338
1339         if (i >= adev->usec_timeout) {
1340                 r = -EINVAL;
1341                 DRM_ERROR("ring %d failed to be preempted\n", ring->idx);
1342         }
1343
1344         /* deassert IB preemption */
1345         WREG32(sdma_gfx_preempt, 0);
1346
1347         /* deassert the preemption condition */
1348         amdgpu_ring_set_preempt_cond_exec(ring, true);
1349         return r;
1350 }
1351
1352 static int sdma_v5_0_set_trap_irq_state(struct amdgpu_device *adev,
1353                                         struct amdgpu_irq_src *source,
1354                                         unsigned type,
1355                                         enum amdgpu_interrupt_state state)
1356 {
1357         u32 sdma_cntl;
1358
1359         u32 reg_offset = (type == AMDGPU_SDMA_IRQ_INSTANCE0) ?
1360                 sdma_v5_0_get_reg_offset(adev, 0, mmSDMA0_CNTL) :
1361                 sdma_v5_0_get_reg_offset(adev, 1, mmSDMA0_CNTL);
1362
1363         sdma_cntl = RREG32(reg_offset);
1364         sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE,
1365                        state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0);
1366         WREG32(reg_offset, sdma_cntl);
1367
1368         return 0;
1369 }
1370
1371 static int sdma_v5_0_process_trap_irq(struct amdgpu_device *adev,
1372                                       struct amdgpu_irq_src *source,
1373                                       struct amdgpu_iv_entry *entry)
1374 {
1375         DRM_DEBUG("IH: SDMA trap\n");
1376         switch (entry->client_id) {
1377         case SOC15_IH_CLIENTID_SDMA0:
1378                 switch (entry->ring_id) {
1379                 case 0:
1380                         amdgpu_fence_process(&adev->sdma.instance[0].ring);
1381                         break;
1382                 case 1:
1383                         /* XXX compute */
1384                         break;
1385                 case 2:
1386                         /* XXX compute */
1387                         break;
1388                 case 3:
1389                         /* XXX page queue*/
1390                         break;
1391                 }
1392                 break;
1393         case SOC15_IH_CLIENTID_SDMA1:
1394                 switch (entry->ring_id) {
1395                 case 0:
1396                         amdgpu_fence_process(&adev->sdma.instance[1].ring);
1397                         break;
1398                 case 1:
1399                         /* XXX compute */
1400                         break;
1401                 case 2:
1402                         /* XXX compute */
1403                         break;
1404                 case 3:
1405                         /* XXX page queue*/
1406                         break;
1407                 }
1408                 break;
1409         }
1410         return 0;
1411 }
1412
1413 static int sdma_v5_0_process_illegal_inst_irq(struct amdgpu_device *adev,
1414                                               struct amdgpu_irq_src *source,
1415                                               struct amdgpu_iv_entry *entry)
1416 {
1417         return 0;
1418 }
1419
1420 static void sdma_v5_0_update_medium_grain_clock_gating(struct amdgpu_device *adev,
1421                                                        bool enable)
1422 {
1423         uint32_t data, def;
1424         int i;
1425
1426         for (i = 0; i < adev->sdma.num_instances; i++) {
1427                 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_SDMA_MGCG)) {
1428                         /* Enable sdma clock gating */
1429                         def = data = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_CLK_CTRL));
1430                         data &= ~(SDMA0_CLK_CTRL__SOFT_OVERRIDE7_MASK |
1431                                   SDMA0_CLK_CTRL__SOFT_OVERRIDE6_MASK |
1432                                   SDMA0_CLK_CTRL__SOFT_OVERRIDE5_MASK |
1433                                   SDMA0_CLK_CTRL__SOFT_OVERRIDE4_MASK |
1434                                   SDMA0_CLK_CTRL__SOFT_OVERRIDE3_MASK |
1435                                   SDMA0_CLK_CTRL__SOFT_OVERRIDE2_MASK |
1436                                   SDMA0_CLK_CTRL__SOFT_OVERRIDE1_MASK |
1437                                   SDMA0_CLK_CTRL__SOFT_OVERRIDE0_MASK);
1438                         if (def != data)
1439                                 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_CLK_CTRL), data);
1440                 } else {
1441                         /* Disable sdma clock gating */
1442                         def = data = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_CLK_CTRL));
1443                         data |= (SDMA0_CLK_CTRL__SOFT_OVERRIDE7_MASK |
1444                                  SDMA0_CLK_CTRL__SOFT_OVERRIDE6_MASK |
1445                                  SDMA0_CLK_CTRL__SOFT_OVERRIDE5_MASK |
1446                                  SDMA0_CLK_CTRL__SOFT_OVERRIDE4_MASK |
1447                                  SDMA0_CLK_CTRL__SOFT_OVERRIDE3_MASK |
1448                                  SDMA0_CLK_CTRL__SOFT_OVERRIDE2_MASK |
1449                                  SDMA0_CLK_CTRL__SOFT_OVERRIDE1_MASK |
1450                                  SDMA0_CLK_CTRL__SOFT_OVERRIDE0_MASK);
1451                         if (def != data)
1452                                 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_CLK_CTRL), data);
1453                 }
1454         }
1455 }
1456
1457 static void sdma_v5_0_update_medium_grain_light_sleep(struct amdgpu_device *adev,
1458                                                       bool enable)
1459 {
1460         uint32_t data, def;
1461         int i;
1462
1463         for (i = 0; i < adev->sdma.num_instances; i++) {
1464                 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_SDMA_LS)) {
1465                         /* Enable sdma mem light sleep */
1466                         def = data = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_POWER_CNTL));
1467                         data |= SDMA0_POWER_CNTL__MEM_POWER_OVERRIDE_MASK;
1468                         if (def != data)
1469                                 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_POWER_CNTL), data);
1470
1471                 } else {
1472                         /* Disable sdma mem light sleep */
1473                         def = data = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_POWER_CNTL));
1474                         data &= ~SDMA0_POWER_CNTL__MEM_POWER_OVERRIDE_MASK;
1475                         if (def != data)
1476                                 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_POWER_CNTL), data);
1477
1478                 }
1479         }
1480 }
1481
1482 static int sdma_v5_0_set_clockgating_state(void *handle,
1483                                            enum amd_clockgating_state state)
1484 {
1485         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1486
1487         if (amdgpu_sriov_vf(adev))
1488                 return 0;
1489
1490         switch (adev->asic_type) {
1491         case CHIP_NAVI10:
1492                 sdma_v5_0_update_medium_grain_clock_gating(adev,
1493                                 state == AMD_CG_STATE_GATE ? true : false);
1494                 sdma_v5_0_update_medium_grain_light_sleep(adev,
1495                                 state == AMD_CG_STATE_GATE ? true : false);
1496                 break;
1497         default:
1498                 break;
1499         }
1500
1501         return 0;
1502 }
1503
1504 static int sdma_v5_0_set_powergating_state(void *handle,
1505                                           enum amd_powergating_state state)
1506 {
1507         return 0;
1508 }
1509
1510 static void sdma_v5_0_get_clockgating_state(void *handle, u32 *flags)
1511 {
1512         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1513         int data;
1514
1515         if (amdgpu_sriov_vf(adev))
1516                 *flags = 0;
1517
1518         /* AMD_CG_SUPPORT_SDMA_MGCG */
1519         data = RREG32(sdma_v5_0_get_reg_offset(adev, 0, mmSDMA0_CLK_CTRL));
1520         if (!(data & SDMA0_CLK_CTRL__SOFT_OVERRIDE7_MASK))
1521                 *flags |= AMD_CG_SUPPORT_SDMA_MGCG;
1522
1523         /* AMD_CG_SUPPORT_SDMA_LS */
1524         data = RREG32(sdma_v5_0_get_reg_offset(adev, 0, mmSDMA0_POWER_CNTL));
1525         if (data & SDMA0_POWER_CNTL__MEM_POWER_OVERRIDE_MASK)
1526                 *flags |= AMD_CG_SUPPORT_SDMA_LS;
1527 }
1528
1529 const struct amd_ip_funcs sdma_v5_0_ip_funcs = {
1530         .name = "sdma_v5_0",
1531         .early_init = sdma_v5_0_early_init,
1532         .late_init = NULL,
1533         .sw_init = sdma_v5_0_sw_init,
1534         .sw_fini = sdma_v5_0_sw_fini,
1535         .hw_init = sdma_v5_0_hw_init,
1536         .hw_fini = sdma_v5_0_hw_fini,
1537         .suspend = sdma_v5_0_suspend,
1538         .resume = sdma_v5_0_resume,
1539         .is_idle = sdma_v5_0_is_idle,
1540         .wait_for_idle = sdma_v5_0_wait_for_idle,
1541         .soft_reset = sdma_v5_0_soft_reset,
1542         .set_clockgating_state = sdma_v5_0_set_clockgating_state,
1543         .set_powergating_state = sdma_v5_0_set_powergating_state,
1544         .get_clockgating_state = sdma_v5_0_get_clockgating_state,
1545 };
1546
1547 static const struct amdgpu_ring_funcs sdma_v5_0_ring_funcs = {
1548         .type = AMDGPU_RING_TYPE_SDMA,
1549         .align_mask = 0xf,
1550         .nop = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP),
1551         .support_64bit_ptrs = true,
1552         .vmhub = AMDGPU_GFXHUB,
1553         .get_rptr = sdma_v5_0_ring_get_rptr,
1554         .get_wptr = sdma_v5_0_ring_get_wptr,
1555         .set_wptr = sdma_v5_0_ring_set_wptr,
1556         .emit_frame_size =
1557                 5 + /* sdma_v5_0_ring_init_cond_exec */
1558                 6 + /* sdma_v5_0_ring_emit_hdp_flush */
1559                 3 + /* hdp_invalidate */
1560                 6 + /* sdma_v5_0_ring_emit_pipeline_sync */
1561                 /* sdma_v5_0_ring_emit_vm_flush */
1562                 SOC15_FLUSH_GPU_TLB_NUM_WREG * 3 +
1563                 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 6 +
1564                 10 + 10 + 10, /* sdma_v5_0_ring_emit_fence x3 for user fence, vm fence */
1565         .emit_ib_size = 7 + 6, /* sdma_v5_0_ring_emit_ib */
1566         .emit_ib = sdma_v5_0_ring_emit_ib,
1567         .emit_fence = sdma_v5_0_ring_emit_fence,
1568         .emit_pipeline_sync = sdma_v5_0_ring_emit_pipeline_sync,
1569         .emit_vm_flush = sdma_v5_0_ring_emit_vm_flush,
1570         .emit_hdp_flush = sdma_v5_0_ring_emit_hdp_flush,
1571         .test_ring = sdma_v5_0_ring_test_ring,
1572         .test_ib = sdma_v5_0_ring_test_ib,
1573         .insert_nop = sdma_v5_0_ring_insert_nop,
1574         .pad_ib = sdma_v5_0_ring_pad_ib,
1575         .emit_wreg = sdma_v5_0_ring_emit_wreg,
1576         .emit_reg_wait = sdma_v5_0_ring_emit_reg_wait,
1577         .init_cond_exec = sdma_v5_0_ring_init_cond_exec,
1578         .patch_cond_exec = sdma_v5_0_ring_patch_cond_exec,
1579         .preempt_ib = sdma_v5_0_ring_preempt_ib,
1580 };
1581
1582 static void sdma_v5_0_set_ring_funcs(struct amdgpu_device *adev)
1583 {
1584         int i;
1585
1586         for (i = 0; i < adev->sdma.num_instances; i++) {
1587                 adev->sdma.instance[i].ring.funcs = &sdma_v5_0_ring_funcs;
1588                 adev->sdma.instance[i].ring.me = i;
1589         }
1590 }
1591
1592 static const struct amdgpu_irq_src_funcs sdma_v5_0_trap_irq_funcs = {
1593         .set = sdma_v5_0_set_trap_irq_state,
1594         .process = sdma_v5_0_process_trap_irq,
1595 };
1596
1597 static const struct amdgpu_irq_src_funcs sdma_v5_0_illegal_inst_irq_funcs = {
1598         .process = sdma_v5_0_process_illegal_inst_irq,
1599 };
1600
1601 static void sdma_v5_0_set_irq_funcs(struct amdgpu_device *adev)
1602 {
1603         adev->sdma.trap_irq.num_types = AMDGPU_SDMA_IRQ_LAST;
1604         adev->sdma.trap_irq.funcs = &sdma_v5_0_trap_irq_funcs;
1605         adev->sdma.illegal_inst_irq.funcs = &sdma_v5_0_illegal_inst_irq_funcs;
1606 }
1607
1608 /**
1609  * sdma_v5_0_emit_copy_buffer - copy buffer using the sDMA engine
1610  *
1611  * @ring: amdgpu_ring structure holding ring information
1612  * @src_offset: src GPU address
1613  * @dst_offset: dst GPU address
1614  * @byte_count: number of bytes to xfer
1615  *
1616  * Copy GPU buffers using the DMA engine (NAVI10).
1617  * Used by the amdgpu ttm implementation to move pages if
1618  * registered as the asic copy callback.
1619  */
1620 static void sdma_v5_0_emit_copy_buffer(struct amdgpu_ib *ib,
1621                                        uint64_t src_offset,
1622                                        uint64_t dst_offset,
1623                                        uint32_t byte_count)
1624 {
1625         ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_COPY) |
1626                 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_COPY_LINEAR);
1627         ib->ptr[ib->length_dw++] = byte_count - 1;
1628         ib->ptr[ib->length_dw++] = 0; /* src/dst endian swap */
1629         ib->ptr[ib->length_dw++] = lower_32_bits(src_offset);
1630         ib->ptr[ib->length_dw++] = upper_32_bits(src_offset);
1631         ib->ptr[ib->length_dw++] = lower_32_bits(dst_offset);
1632         ib->ptr[ib->length_dw++] = upper_32_bits(dst_offset);
1633 }
1634
1635 /**
1636  * sdma_v5_0_emit_fill_buffer - fill buffer using the sDMA engine
1637  *
1638  * @ring: amdgpu_ring structure holding ring information
1639  * @src_data: value to write to buffer
1640  * @dst_offset: dst GPU address
1641  * @byte_count: number of bytes to xfer
1642  *
1643  * Fill GPU buffers using the DMA engine (NAVI10).
1644  */
1645 static void sdma_v5_0_emit_fill_buffer(struct amdgpu_ib *ib,
1646                                        uint32_t src_data,
1647                                        uint64_t dst_offset,
1648                                        uint32_t byte_count)
1649 {
1650         ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_CONST_FILL);
1651         ib->ptr[ib->length_dw++] = lower_32_bits(dst_offset);
1652         ib->ptr[ib->length_dw++] = upper_32_bits(dst_offset);
1653         ib->ptr[ib->length_dw++] = src_data;
1654         ib->ptr[ib->length_dw++] = byte_count - 1;
1655 }
1656
1657 static const struct amdgpu_buffer_funcs sdma_v5_0_buffer_funcs = {
1658         .copy_max_bytes = 0x400000,
1659         .copy_num_dw = 7,
1660         .emit_copy_buffer = sdma_v5_0_emit_copy_buffer,
1661
1662         .fill_max_bytes = 0x400000,
1663         .fill_num_dw = 5,
1664         .emit_fill_buffer = sdma_v5_0_emit_fill_buffer,
1665 };
1666
1667 static void sdma_v5_0_set_buffer_funcs(struct amdgpu_device *adev)
1668 {
1669         if (adev->mman.buffer_funcs == NULL) {
1670                 adev->mman.buffer_funcs = &sdma_v5_0_buffer_funcs;
1671                 adev->mman.buffer_funcs_ring = &adev->sdma.instance[0].ring;
1672         }
1673 }
1674
1675 static const struct amdgpu_vm_pte_funcs sdma_v5_0_vm_pte_funcs = {
1676         .copy_pte_num_dw = 7,
1677         .copy_pte = sdma_v5_0_vm_copy_pte,
1678         .write_pte = sdma_v5_0_vm_write_pte,
1679         .set_pte_pde = sdma_v5_0_vm_set_pte_pde,
1680 };
1681
1682 static void sdma_v5_0_set_vm_pte_funcs(struct amdgpu_device *adev)
1683 {
1684         struct drm_gpu_scheduler *sched;
1685         unsigned i;
1686
1687         if (adev->vm_manager.vm_pte_funcs == NULL) {
1688                 adev->vm_manager.vm_pte_funcs = &sdma_v5_0_vm_pte_funcs;
1689                 for (i = 0; i < adev->sdma.num_instances; i++) {
1690                         sched = &adev->sdma.instance[i].ring.sched;
1691                         adev->vm_manager.vm_pte_rqs[i] =
1692                                 &sched->sched_rq[DRM_SCHED_PRIORITY_KERNEL];
1693                 }
1694                 adev->vm_manager.vm_pte_num_rqs = adev->sdma.num_instances;
1695         }
1696 }
1697
1698 const struct amdgpu_ip_block_version sdma_v5_0_ip_block = {
1699         .type = AMD_IP_BLOCK_TYPE_SDMA,
1700         .major = 5,
1701         .minor = 0,
1702         .rev = 0,
1703         .funcs = &sdma_v5_0_ip_funcs,
1704 };