drivers/gpu/drm/amd/amdgpu/si.c

   1 /*
   2  * Copyright 2015 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23
  24 #include <linux/firmware.h>
  25 #include <linux/slab.h>
  26 #include <linux/module.h>
  27 #include "drmP.h"
  28 #include "amdgpu.h"
  29 #include "amdgpu_atombios.h"
  30 #include "amdgpu_ih.h"
  31 #include "amdgpu_uvd.h"
  32 #include "amdgpu_vce.h"
  33 #include "atom.h"
  34 #include "amdgpu_powerplay.h"
  35 #include "si/sid.h"
  36 #include "si_ih.h"
  37 #include "gfx_v6_0.h"
  38 #include "gmc_v6_0.h"
  39 #include "si_dma.h"
  40 #include "dce_v6_0.h"
  41 #include "si.h"
  42 #include "dce_virtual.h"
  43
  44 static const u32 tahiti_golden_registers[] =
  45 {
  46         0x17bc, 0x00000030, 0x00000011,
  47         0x2684, 0x00010000, 0x00018208,
  48         0x260c, 0xffffffff, 0x00000000,
  49         0x260d, 0xf00fffff, 0x00000400,
  50         0x260e, 0x0002021c, 0x00020200,
  51         0x031e, 0x00000080, 0x00000000,
  52         0x340c, 0x000000c0, 0x00800040,
  53         0x360c, 0x000000c0, 0x00800040,
  54         0x16ec, 0x000000f0, 0x00000070,
  55         0x16f0, 0x00200000, 0x50100000,
  56         0x1c0c, 0x31000311, 0x00000011,
  57         0x09df, 0x00000003, 0x000007ff,
  58         0x0903, 0x000007ff, 0x00000000,
  59         0x2285, 0xf000001f, 0x00000007,
  60         0x22c9, 0xffffffff, 0x00ffffff,
  61         0x22c4, 0x0000ff0f, 0x00000000,
  62         0xa293, 0x07ffffff, 0x4e000000,
  63         0xa0d4, 0x3f3f3fff, 0x2a00126a,
  64         0x000c, 0xffffffff, 0x0040,
  65         0x000d, 0x00000040, 0x00004040,
  66         0x2440, 0x07ffffff, 0x03000000,
  67         0x23a2, 0x01ff1f3f, 0x00000000,
  68         0x23a1, 0x01ff1f3f, 0x00000000,
  69         0x2418, 0x0000007f, 0x00000020,
  70         0x2542, 0x00010000, 0x00010000,
  71         0x2b05, 0x00000200, 0x000002fb,
  72         0x2b04, 0xffffffff, 0x0000543b,
  73         0x2b03, 0xffffffff, 0xa9210876,
  74         0x2234, 0xffffffff, 0x000fff40,
  75         0x2235, 0x0000001f, 0x00000010,
  76         0x0504, 0x20000000, 0x20fffed8,
  77         0x0570, 0x000c0fc0, 0x000c0400,
  78         0x052c, 0x0fffffff, 0xffffffff,
  79         0x052d, 0x0fffffff, 0x0fffffff,
  80         0x052e, 0x0fffffff, 0x0fffffff,
  81         0x052f, 0x0fffffff, 0x0fffffff
  82 };
  83
  84 static const u32 tahiti_golden_registers2[] =
  85 {
  86         0x0319, 0x00000001, 0x00000001
  87 };
  88
  89 static const u32 tahiti_golden_rlc_registers[] =
  90 {
  91         0x263e, 0xffffffff, 0x12011003,
  92         0x3109, 0xffffffff, 0x00601005,
  93         0x311f, 0xffffffff, 0x10104040,
  94         0x3122, 0xffffffff, 0x0100000a,
  95         0x30c5, 0xffffffff, 0x00000800,
  96         0x30c3, 0xffffffff, 0x800000f4,
  97         0x3d2a, 0x00000008, 0x00000000
  98 };
  99
 100 static const u32 pitcairn_golden_registers[] =
 101 {
 102         0x17bc, 0x00000030, 0x00000011,
 103         0x2684, 0x00010000, 0x00018208,
 104         0x260c, 0xffffffff, 0x00000000,
 105         0x260d, 0xf00fffff, 0x00000400,
 106         0x260e, 0x0002021c, 0x00020200,
 107         0x031e, 0x00000080, 0x00000000,
 108         0x340c, 0x000300c0, 0x00800040,
 109         0x360c, 0x000300c0, 0x00800040,
 110         0x16ec, 0x000000f0, 0x00000070,
 111         0x16f0, 0x00200000, 0x50100000,
 112         0x1c0c, 0x31000311, 0x00000011,
 113         0x0ab9, 0x00073ffe, 0x000022a2,
 114         0x0903, 0x000007ff, 0x00000000,
 115         0x2285, 0xf000001f, 0x00000007,
 116         0x22c9, 0xffffffff, 0x00ffffff,
 117         0x22c4, 0x0000ff0f, 0x00000000,
 118         0xa293, 0x07ffffff, 0x4e000000,
 119         0xa0d4, 0x3f3f3fff, 0x2a00126a,
 120         0x000c, 0xffffffff, 0x0040,
 121         0x000d, 0x00000040, 0x00004040,
 122         0x2440, 0x07ffffff, 0x03000000,
 123         0x2418, 0x0000007f, 0x00000020,
 124         0x2542, 0x00010000, 0x00010000,
 125         0x2b05, 0x000003ff, 0x000000f7,
 126         0x2b04, 0xffffffff, 0x00000000,
 127         0x2b03, 0xffffffff, 0x32761054,
 128         0x2235, 0x0000001f, 0x00000010,
 129         0x0570, 0x000c0fc0, 0x000c0400,
 130         0x052c, 0x0fffffff, 0xffffffff,
 131         0x052d, 0x0fffffff, 0x0fffffff,
 132         0x052e, 0x0fffffff, 0x0fffffff,
 133         0x052f, 0x0fffffff, 0x0fffffff
 134 };
 135
 136 static const u32 pitcairn_golden_rlc_registers[] =
 137 {
 138         0x263e, 0xffffffff, 0x12011003,
 139         0x3109, 0xffffffff, 0x00601004,
 140         0x311f, 0xffffffff, 0x10102020,
 141         0x3122, 0xffffffff, 0x01000020,
 142         0x30c5, 0xffffffff, 0x00000800,
 143         0x30c3, 0xffffffff, 0x800000a4
 144 };
 145
 146 static const u32 verde_pg_init[] =
 147 {
 148         0xd4f, 0xffffffff, 0x40000,
 149         0xd4e, 0xffffffff, 0x200010ff,
 150         0xd4f, 0xffffffff, 0x0,
 151         0xd4f, 0xffffffff, 0x0,
 152         0xd4f, 0xffffffff, 0x0,
 153         0xd4f, 0xffffffff, 0x0,
 154         0xd4f, 0xffffffff, 0x0,
 155         0xd4f, 0xffffffff, 0x7007,
 156         0xd4e, 0xffffffff, 0x300010ff,
 157         0xd4f, 0xffffffff, 0x0,
 158         0xd4f, 0xffffffff, 0x0,
 159         0xd4f, 0xffffffff, 0x0,
 160         0xd4f, 0xffffffff, 0x0,
 161         0xd4f, 0xffffffff, 0x0,
 162         0xd4f, 0xffffffff, 0x400000,
 163         0xd4e, 0xffffffff, 0x100010ff,
 164         0xd4f, 0xffffffff, 0x0,
 165         0xd4f, 0xffffffff, 0x0,
 166         0xd4f, 0xffffffff, 0x0,
 167         0xd4f, 0xffffffff, 0x0,
 168         0xd4f, 0xffffffff, 0x0,
 169         0xd4f, 0xffffffff, 0x120200,
 170         0xd4e, 0xffffffff, 0x500010ff,
 171         0xd4f, 0xffffffff, 0x0,
 172         0xd4f, 0xffffffff, 0x0,
 173         0xd4f, 0xffffffff, 0x0,
 174         0xd4f, 0xffffffff, 0x0,
 175         0xd4f, 0xffffffff, 0x0,
 176         0xd4f, 0xffffffff, 0x1e1e16,
 177         0xd4e, 0xffffffff, 0x600010ff,
 178         0xd4f, 0xffffffff, 0x0,
 179         0xd4f, 0xffffffff, 0x0,
 180         0xd4f, 0xffffffff, 0x0,
 181         0xd4f, 0xffffffff, 0x0,
 182         0xd4f, 0xffffffff, 0x0,
 183         0xd4f, 0xffffffff, 0x171f1e,
 184         0xd4e, 0xffffffff, 0x700010ff,
 185         0xd4f, 0xffffffff, 0x0,
 186         0xd4f, 0xffffffff, 0x0,
 187         0xd4f, 0xffffffff, 0x0,
 188         0xd4f, 0xffffffff, 0x0,
 189         0xd4f, 0xffffffff, 0x0,
 190         0xd4f, 0xffffffff, 0x0,
 191         0xd4e, 0xffffffff, 0x9ff,
 192         0xd40, 0xffffffff, 0x0,
 193         0xd41, 0xffffffff, 0x10000800,
 194         0xd41, 0xffffffff, 0xf,
 195         0xd41, 0xffffffff, 0xf,
 196         0xd40, 0xffffffff, 0x4,
 197         0xd41, 0xffffffff, 0x1000051e,
 198         0xd41, 0xffffffff, 0xffff,
 199         0xd41, 0xffffffff, 0xffff,
 200         0xd40, 0xffffffff, 0x8,
 201         0xd41, 0xffffffff, 0x80500,
 202         0xd40, 0xffffffff, 0x12,
 203         0xd41, 0xffffffff, 0x9050c,
 204         0xd40, 0xffffffff, 0x1d,
 205         0xd41, 0xffffffff, 0xb052c,
 206         0xd40, 0xffffffff, 0x2a,
 207         0xd41, 0xffffffff, 0x1053e,
 208         0xd40, 0xffffffff, 0x2d,
 209         0xd41, 0xffffffff, 0x10546,
 210         0xd40, 0xffffffff, 0x30,
 211         0xd41, 0xffffffff, 0xa054e,
 212         0xd40, 0xffffffff, 0x3c,
 213         0xd41, 0xffffffff, 0x1055f,
 214         0xd40, 0xffffffff, 0x3f,
 215         0xd41, 0xffffffff, 0x10567,
 216         0xd40, 0xffffffff, 0x42,
 217         0xd41, 0xffffffff, 0x1056f,
 218         0xd40, 0xffffffff, 0x45,
 219         0xd41, 0xffffffff, 0x10572,
 220         0xd40, 0xffffffff, 0x48,
 221         0xd41, 0xffffffff, 0x20575,
 222         0xd40, 0xffffffff, 0x4c,
 223         0xd41, 0xffffffff, 0x190801,
 224         0xd40, 0xffffffff, 0x67,
 225         0xd41, 0xffffffff, 0x1082a,
 226         0xd40, 0xffffffff, 0x6a,
 227         0xd41, 0xffffffff, 0x1b082d,
 228         0xd40, 0xffffffff, 0x87,
 229         0xd41, 0xffffffff, 0x310851,
 230         0xd40, 0xffffffff, 0xba,
 231         0xd41, 0xffffffff, 0x891,
 232         0xd40, 0xffffffff, 0xbc,
 233         0xd41, 0xffffffff, 0x893,
 234         0xd40, 0xffffffff, 0xbe,
 235         0xd41, 0xffffffff, 0x20895,
 236         0xd40, 0xffffffff, 0xc2,
 237         0xd41, 0xffffffff, 0x20899,
 238         0xd40, 0xffffffff, 0xc6,
 239         0xd41, 0xffffffff, 0x2089d,
 240         0xd40, 0xffffffff, 0xca,
 241         0xd41, 0xffffffff, 0x8a1,
 242         0xd40, 0xffffffff, 0xcc,
 243         0xd41, 0xffffffff, 0x8a3,
 244         0xd40, 0xffffffff, 0xce,
 245         0xd41, 0xffffffff, 0x308a5,
 246         0xd40, 0xffffffff, 0xd3,
 247         0xd41, 0xffffffff, 0x6d08cd,
 248         0xd40, 0xffffffff, 0x142,
 249         0xd41, 0xffffffff, 0x2000095a,
 250         0xd41, 0xffffffff, 0x1,
 251         0xd40, 0xffffffff, 0x144,
 252         0xd41, 0xffffffff, 0x301f095b,
 253         0xd40, 0xffffffff, 0x165,
 254         0xd41, 0xffffffff, 0xc094d,
 255         0xd40, 0xffffffff, 0x173,
 256         0xd41, 0xffffffff, 0xf096d,
 257         0xd40, 0xffffffff, 0x184,
 258         0xd41, 0xffffffff, 0x15097f,
 259         0xd40, 0xffffffff, 0x19b,
 260         0xd41, 0xffffffff, 0xc0998,
 261         0xd40, 0xffffffff, 0x1a9,
 262         0xd41, 0xffffffff, 0x409a7,
 263         0xd40, 0xffffffff, 0x1af,
 264         0xd41, 0xffffffff, 0xcdc,
 265         0xd40, 0xffffffff, 0x1b1,
 266         0xd41, 0xffffffff, 0x800,
 267         0xd42, 0xffffffff, 0x6c9b2000,
 268         0xd44, 0xfc00, 0x2000,
 269         0xd51, 0xffffffff, 0xfc0,
 270         0xa35, 0x00000100, 0x100
 271 };
 272
 273 static const u32 verde_golden_rlc_registers[] =
 274 {
 275         0x3109, 0xffffffff, 0x033f1005,
 276         0x311f, 0xffffffff, 0x10808020,
 277         0x3122, 0xffffffff, 0x00800008,
 278         0x30c5, 0xffffffff, 0x00001000,
 279         0x30c3, 0xffffffff, 0x80010014
 280 };
 281
 282 static const u32 verde_golden_registers[] =
 283 {
 284         0x2684, 0x00010000, 0x00018208,
 285         0x260c, 0xffffffff, 0x00000000,
 286         0x260d, 0xf00fffff, 0x00000400,
 287         0x260e, 0x0002021c, 0x00020200,
 288         0x031e, 0x00000080, 0x00000000,
 289         0x340c, 0x000300c0, 0x00800040,
 290         0x340c, 0x000300c0, 0x00800040,
 291         0x360c, 0x000300c0, 0x00800040,
 292         0x360c, 0x000300c0, 0x00800040,
 293         0x16ec, 0x000000f0, 0x00000070,
 294         0x16f0, 0x00200000, 0x50100000,
 295
 296         0x1c0c, 0x31000311, 0x00000011,
 297         0x0ab9, 0x00073ffe, 0x000022a2,
 298         0x0ab9, 0x00073ffe, 0x000022a2,
 299         0x0ab9, 0x00073ffe, 0x000022a2,
 300         0x0903, 0x000007ff, 0x00000000,
 301         0x0903, 0x000007ff, 0x00000000,
 302         0x0903, 0x000007ff, 0x00000000,
 303         0x2285, 0xf000001f, 0x00000007,
 304         0x2285, 0xf000001f, 0x00000007,
 305         0x2285, 0xf000001f, 0x00000007,
 306         0x2285, 0xffffffff, 0x00ffffff,
 307         0x22c4, 0x0000ff0f, 0x00000000,
 308
 309         0xa293, 0x07ffffff, 0x4e000000,
 310         0xa0d4, 0x3f3f3fff, 0x0000124a,
 311         0xa0d4, 0x3f3f3fff, 0x0000124a,
 312         0xa0d4, 0x3f3f3fff, 0x0000124a,
 313         0x000c, 0x000000ff, 0x0040,
 314         0x000d, 0x00000040, 0x00004040,
 315         0x2440, 0x07ffffff, 0x03000000,
 316         0x2440, 0x07ffffff, 0x03000000,
 317         0x23a2, 0x01ff1f3f, 0x00000000,
 318         0x23a3, 0x01ff1f3f, 0x00000000,
 319         0x23a2, 0x01ff1f3f, 0x00000000,
 320         0x23a1, 0x01ff1f3f, 0x00000000,
 321         0x23a1, 0x01ff1f3f, 0x00000000,
 322
 323         0x23a1, 0x01ff1f3f, 0x00000000,
 324         0x2418, 0x0000007f, 0x00000020,
 325         0x2542, 0x00010000, 0x00010000,
 326         0x2b01, 0x000003ff, 0x00000003,
 327         0x2b05, 0x000003ff, 0x00000003,
 328         0x2b05, 0x000003ff, 0x00000003,
 329         0x2b04, 0xffffffff, 0x00000000,
 330         0x2b04, 0xffffffff, 0x00000000,
 331         0x2b04, 0xffffffff, 0x00000000,
 332         0x2b03, 0xffffffff, 0x00001032,
 333         0x2b03, 0xffffffff, 0x00001032,
 334         0x2b03, 0xffffffff, 0x00001032,
 335         0x2235, 0x0000001f, 0x00000010,
 336         0x2235, 0x0000001f, 0x00000010,
 337         0x2235, 0x0000001f, 0x00000010,
 338         0x0570, 0x000c0fc0, 0x000c0400
 339 };
 340
 341 static const u32 oland_golden_registers[] =
 342 {
 343         0x17bc, 0x00000030, 0x00000011,
 344         0x2684, 0x00010000, 0x00018208,
 345         0x260c, 0xffffffff, 0x00000000,
 346         0x260d, 0xf00fffff, 0x00000400,
 347         0x260e, 0x0002021c, 0x00020200,
 348         0x031e, 0x00000080, 0x00000000,
 349         0x340c, 0x000300c0, 0x00800040,
 350         0x360c, 0x000300c0, 0x00800040,
 351         0x16ec, 0x000000f0, 0x00000070,
 352         0x16f0, 0x00200000, 0x50100000,
 353         0x1c0c, 0x31000311, 0x00000011,
 354         0x0ab9, 0x00073ffe, 0x000022a2,
 355         0x0903, 0x000007ff, 0x00000000,
 356         0x2285, 0xf000001f, 0x00000007,
 357         0x22c9, 0xffffffff, 0x00ffffff,
 358         0x22c4, 0x0000ff0f, 0x00000000,
 359         0xa293, 0x07ffffff, 0x4e000000,
 360         0xa0d4, 0x3f3f3fff, 0x00000082,
 361         0x000c, 0xffffffff, 0x0040,
 362         0x000d, 0x00000040, 0x00004040,
 363         0x2440, 0x07ffffff, 0x03000000,
 364         0x2418, 0x0000007f, 0x00000020,
 365         0x2542, 0x00010000, 0x00010000,
 366         0x2b05, 0x000003ff, 0x000000f3,
 367         0x2b04, 0xffffffff, 0x00000000,
 368         0x2b03, 0xffffffff, 0x00003210,
 369         0x2235, 0x0000001f, 0x00000010,
 370         0x0570, 0x000c0fc0, 0x000c0400,
 371         0x052c, 0x0fffffff, 0xffffffff,
 372         0x052d, 0x0fffffff, 0x0fffffff,
 373         0x052e, 0x0fffffff, 0x0fffffff,
 374         0x052f, 0x0fffffff, 0x0fffffff
 375 };
 376
 377 static const u32 oland_golden_rlc_registers[] =
 378 {
 379         0x263e, 0xffffffff, 0x02010002,
 380         0x3109, 0xffffffff, 0x00601005,
 381         0x311f, 0xffffffff, 0x10104040,
 382         0x3122, 0xffffffff, 0x0100000a,
 383         0x30c5, 0xffffffff, 0x00000800,
 384         0x30c3, 0xffffffff, 0x800000f4
 385 };
 386
 387 static const u32 hainan_golden_registers[] =
 388 {
 389         0x17bc, 0x00000030, 0x00000011,
 390         0x2684, 0x00010000, 0x00018208,
 391         0x260c, 0xffffffff, 0x00000000,
 392         0x260d, 0xf00fffff, 0x00000400,
 393         0x260e, 0x0002021c, 0x00020200,
 394         0x031e, 0x00000080, 0x00000000,
 395         0x3430, 0xff000fff, 0x00000100,
 396         0x340c, 0x000300c0, 0x00800040,
 397         0x3630, 0xff000fff, 0x00000100,
 398         0x360c, 0x000300c0, 0x00800040,
 399         0x16ec, 0x000000f0, 0x00000070,
 400         0x16f0, 0x00200000, 0x50100000,
 401         0x1c0c, 0x31000311, 0x00000011,
 402         0x0ab9, 0x00073ffe, 0x000022a2,
 403         0x0903, 0x000007ff, 0x00000000,
 404         0x2285, 0xf000001f, 0x00000007,
 405         0x22c9, 0xffffffff, 0x00ffffff,
 406         0x22c4, 0x0000ff0f, 0x00000000,
 407         0xa293, 0x07ffffff, 0x4e000000,
 408         0xa0d4, 0x3f3f3fff, 0x00000000,
 409         0x000c, 0xffffffff, 0x0040,
 410         0x000d, 0x00000040, 0x00004040,
 411         0x2440, 0x03e00000, 0x03600000,
 412         0x2418, 0x0000007f, 0x00000020,
 413         0x2542, 0x00010000, 0x00010000,
 414         0x2b05, 0x000003ff, 0x000000f1,
 415         0x2b04, 0xffffffff, 0x00000000,
 416         0x2b03, 0xffffffff, 0x00003210,
 417         0x2235, 0x0000001f, 0x00000010,
 418         0x0570, 0x000c0fc0, 0x000c0400,
 419         0x052c, 0x0fffffff, 0xffffffff,
 420         0x052d, 0x0fffffff, 0x0fffffff,
 421         0x052e, 0x0fffffff, 0x0fffffff,
 422         0x052f, 0x0fffffff, 0x0fffffff
 423 };
 424
 425 static const u32 hainan_golden_registers2[] =
 426 {
 427         0x263e, 0xffffffff, 0x2011003
 428 };
 429
 430 static const u32 tahiti_mgcg_cgcg_init[] =
 431 {
 432         0x3100, 0xffffffff, 0xfffffffc,
 433         0x200b, 0xffffffff, 0xe0000000,
 434         0x2698, 0xffffffff, 0x00000100,
 435         0x24a9, 0xffffffff, 0x00000100,
 436         0x3059, 0xffffffff, 0x00000100,
 437         0x25dd, 0xffffffff, 0x00000100,
 438         0x2261, 0xffffffff, 0x06000100,
 439         0x2286, 0xffffffff, 0x00000100,
 440         0x24a8, 0xffffffff, 0x00000100,
 441         0x30e0, 0xffffffff, 0x00000100,
 442         0x22ca, 0xffffffff, 0x00000100,
 443         0x2451, 0xffffffff, 0x00000100,
 444         0x2362, 0xffffffff, 0x00000100,
 445         0x2363, 0xffffffff, 0x00000100,
 446         0x240c, 0xffffffff, 0x00000100,
 447         0x240d, 0xffffffff, 0x00000100,
 448         0x240e, 0xffffffff, 0x00000100,
 449         0x240f, 0xffffffff, 0x00000100,
 450         0x2b60, 0xffffffff, 0x00000100,
 451         0x2b15, 0xffffffff, 0x00000100,
 452         0x225f, 0xffffffff, 0x06000100,
 453         0x261a, 0xffffffff, 0x00000100,
 454         0x2544, 0xffffffff, 0x00000100,
 455         0x2bc1, 0xffffffff, 0x00000100,
 456         0x2b81, 0xffffffff, 0x00000100,
 457         0x2527, 0xffffffff, 0x00000100,
 458         0x200b, 0xffffffff, 0xe0000000,
 459         0x2458, 0xffffffff, 0x00010000,
 460         0x2459, 0xffffffff, 0x00030002,
 461         0x245a, 0xffffffff, 0x00040007,
 462         0x245b, 0xffffffff, 0x00060005,
 463         0x245c, 0xffffffff, 0x00090008,
 464         0x245d, 0xffffffff, 0x00020001,
 465         0x245e, 0xffffffff, 0x00040003,
 466         0x245f, 0xffffffff, 0x00000007,
 467         0x2460, 0xffffffff, 0x00060005,
 468         0x2461, 0xffffffff, 0x00090008,
 469         0x2462, 0xffffffff, 0x00030002,
 470         0x2463, 0xffffffff, 0x00050004,
 471         0x2464, 0xffffffff, 0x00000008,
 472         0x2465, 0xffffffff, 0x00070006,
 473         0x2466, 0xffffffff, 0x000a0009,
 474         0x2467, 0xffffffff, 0x00040003,
 475         0x2468, 0xffffffff, 0x00060005,
 476         0x2469, 0xffffffff, 0x00000009,
 477         0x246a, 0xffffffff, 0x00080007,
 478         0x246b, 0xffffffff, 0x000b000a,
 479         0x246c, 0xffffffff, 0x00050004,
 480         0x246d, 0xffffffff, 0x00070006,
 481         0x246e, 0xffffffff, 0x0008000b,
 482         0x246f, 0xffffffff, 0x000a0009,
 483         0x2470, 0xffffffff, 0x000d000c,
 484         0x2471, 0xffffffff, 0x00060005,
 485         0x2472, 0xffffffff, 0x00080007,
 486         0x2473, 0xffffffff, 0x0000000b,
 487         0x2474, 0xffffffff, 0x000a0009,
 488         0x2475, 0xffffffff, 0x000d000c,
 489         0x2476, 0xffffffff, 0x00070006,
 490         0x2477, 0xffffffff, 0x00090008,
 491         0x2478, 0xffffffff, 0x0000000c,
 492         0x2479, 0xffffffff, 0x000b000a,
 493         0x247a, 0xffffffff, 0x000e000d,
 494         0x247b, 0xffffffff, 0x00080007,
 495         0x247c, 0xffffffff, 0x000a0009,
 496         0x247d, 0xffffffff, 0x0000000d,
 497         0x247e, 0xffffffff, 0x000c000b,
 498         0x247f, 0xffffffff, 0x000f000e,
 499         0x2480, 0xffffffff, 0x00090008,
 500         0x2481, 0xffffffff, 0x000b000a,
 501         0x2482, 0xffffffff, 0x000c000f,
 502         0x2483, 0xffffffff, 0x000e000d,
 503         0x2484, 0xffffffff, 0x00110010,
 504         0x2485, 0xffffffff, 0x000a0009,
 505         0x2486, 0xffffffff, 0x000c000b,
 506         0x2487, 0xffffffff, 0x0000000f,
 507         0x2488, 0xffffffff, 0x000e000d,
 508         0x2489, 0xffffffff, 0x00110010,
 509         0x248a, 0xffffffff, 0x000b000a,
 510         0x248b, 0xffffffff, 0x000d000c,
 511         0x248c, 0xffffffff, 0x00000010,
 512         0x248d, 0xffffffff, 0x000f000e,
 513         0x248e, 0xffffffff, 0x00120011,
 514         0x248f, 0xffffffff, 0x000c000b,
 515         0x2490, 0xffffffff, 0x000e000d,
 516         0x2491, 0xffffffff, 0x00000011,
 517         0x2492, 0xffffffff, 0x0010000f,
 518         0x2493, 0xffffffff, 0x00130012,
 519         0x2494, 0xffffffff, 0x000d000c,
 520         0x2495, 0xffffffff, 0x000f000e,
 521         0x2496, 0xffffffff, 0x00100013,
 522         0x2497, 0xffffffff, 0x00120011,
 523         0x2498, 0xffffffff, 0x00150014,
 524         0x2499, 0xffffffff, 0x000e000d,
 525         0x249a, 0xffffffff, 0x0010000f,
 526         0x249b, 0xffffffff, 0x00000013,
 527         0x249c, 0xffffffff, 0x00120011,
 528         0x249d, 0xffffffff, 0x00150014,
 529         0x249e, 0xffffffff, 0x000f000e,
 530         0x249f, 0xffffffff, 0x00110010,
 531         0x24a0, 0xffffffff, 0x00000014,
 532         0x24a1, 0xffffffff, 0x00130012,
 533         0x24a2, 0xffffffff, 0x00160015,
 534         0x24a3, 0xffffffff, 0x0010000f,
 535         0x24a4, 0xffffffff, 0x00120011,
 536         0x24a5, 0xffffffff, 0x00000015,
 537         0x24a6, 0xffffffff, 0x00140013,
 538         0x24a7, 0xffffffff, 0x00170016,
 539         0x2454, 0xffffffff, 0x96940200,
 540         0x21c2, 0xffffffff, 0x00900100,
 541         0x311e, 0xffffffff, 0x00000080,
 542         0x3101, 0xffffffff, 0x0020003f,
 543         0x000c, 0xffffffff, 0x0000001c,
 544         0x000d, 0x000f0000, 0x000f0000,
 545         0x0583, 0xffffffff, 0x00000100,
 546         0x0409, 0xffffffff, 0x00000100,
 547         0x040b, 0x00000101, 0x00000000,
 548         0x082a, 0xffffffff, 0x00000104,
 549         0x0993, 0x000c0000, 0x000c0000,
 550         0x0992, 0x000c0000, 0x000c0000,
 551         0x1579, 0xff000fff, 0x00000100,
 552         0x157a, 0x00000001, 0x00000001,
 553         0x0bd4, 0x00000001, 0x00000001,
 554         0x0c33, 0xc0000fff, 0x00000104,
 555         0x3079, 0x00000001, 0x00000001,
 556         0x3430, 0xfffffff0, 0x00000100,
 557         0x3630, 0xfffffff0, 0x00000100
 558 };
 559 static const u32 pitcairn_mgcg_cgcg_init[] =
 560 {
 561         0x3100, 0xffffffff, 0xfffffffc,
 562         0x200b, 0xffffffff, 0xe0000000,
 563         0x2698, 0xffffffff, 0x00000100,
 564         0x24a9, 0xffffffff, 0x00000100,
 565         0x3059, 0xffffffff, 0x00000100,
 566         0x25dd, 0xffffffff, 0x00000100,
 567         0x2261, 0xffffffff, 0x06000100,
 568         0x2286, 0xffffffff, 0x00000100,
 569         0x24a8, 0xffffffff, 0x00000100,
 570         0x30e0, 0xffffffff, 0x00000100,
 571         0x22ca, 0xffffffff, 0x00000100,
 572         0x2451, 0xffffffff, 0x00000100,
 573         0x2362, 0xffffffff, 0x00000100,
 574         0x2363, 0xffffffff, 0x00000100,
 575         0x240c, 0xffffffff, 0x00000100,
 576         0x240d, 0xffffffff, 0x00000100,
 577         0x240e, 0xffffffff, 0x00000100,
 578         0x240f, 0xffffffff, 0x00000100,
 579         0x2b60, 0xffffffff, 0x00000100,
 580         0x2b15, 0xffffffff, 0x00000100,
 581         0x225f, 0xffffffff, 0x06000100,
 582         0x261a, 0xffffffff, 0x00000100,
 583         0x2544, 0xffffffff, 0x00000100,
 584         0x2bc1, 0xffffffff, 0x00000100,
 585         0x2b81, 0xffffffff, 0x00000100,
 586         0x2527, 0xffffffff, 0x00000100,
 587         0x200b, 0xffffffff, 0xe0000000,
 588         0x2458, 0xffffffff, 0x00010000,
 589         0x2459, 0xffffffff, 0x00030002,
 590         0x245a, 0xffffffff, 0x00040007,
 591         0x245b, 0xffffffff, 0x00060005,
 592         0x245c, 0xffffffff, 0x00090008,
 593         0x245d, 0xffffffff, 0x00020001,
 594         0x245e, 0xffffffff, 0x00040003,
 595         0x245f, 0xffffffff, 0x00000007,
 596         0x2460, 0xffffffff, 0x00060005,
 597         0x2461, 0xffffffff, 0x00090008,
 598         0x2462, 0xffffffff, 0x00030002,
 599         0x2463, 0xffffffff, 0x00050004,
 600         0x2464, 0xffffffff, 0x00000008,
 601         0x2465, 0xffffffff, 0x00070006,
 602         0x2466, 0xffffffff, 0x000a0009,
 603         0x2467, 0xffffffff, 0x00040003,
 604         0x2468, 0xffffffff, 0x00060005,
 605         0x2469, 0xffffffff, 0x00000009,
 606         0x246a, 0xffffffff, 0x00080007,
 607         0x246b, 0xffffffff, 0x000b000a,
 608         0x246c, 0xffffffff, 0x00050004,
 609         0x246d, 0xffffffff, 0x00070006,
 610         0x246e, 0xffffffff, 0x0008000b,
 611         0x246f, 0xffffffff, 0x000a0009,
 612         0x2470, 0xffffffff, 0x000d000c,
 613         0x2480, 0xffffffff, 0x00090008,
 614         0x2481, 0xffffffff, 0x000b000a,
 615         0x2482, 0xffffffff, 0x000c000f,
 616         0x2483, 0xffffffff, 0x000e000d,
 617         0x2484, 0xffffffff, 0x00110010,
 618         0x2485, 0xffffffff, 0x000a0009,
 619         0x2486, 0xffffffff, 0x000c000b,
 620         0x2487, 0xffffffff, 0x0000000f,
 621         0x2488, 0xffffffff, 0x000e000d,
 622         0x2489, 0xffffffff, 0x00110010,
 623         0x248a, 0xffffffff, 0x000b000a,
 624         0x248b, 0xffffffff, 0x000d000c,
 625         0x248c, 0xffffffff, 0x00000010,
 626         0x248d, 0xffffffff, 0x000f000e,
 627         0x248e, 0xffffffff, 0x00120011,
 628         0x248f, 0xffffffff, 0x000c000b,
 629         0x2490, 0xffffffff, 0x000e000d,
 630         0x2491, 0xffffffff, 0x00000011,
 631         0x2492, 0xffffffff, 0x0010000f,
 632         0x2493, 0xffffffff, 0x00130012,
 633         0x2494, 0xffffffff, 0x000d000c,
 634         0x2495, 0xffffffff, 0x000f000e,
 635         0x2496, 0xffffffff, 0x00100013,
 636         0x2497, 0xffffffff, 0x00120011,
 637         0x2498, 0xffffffff, 0x00150014,
 638         0x2454, 0xffffffff, 0x96940200,
 639         0x21c2, 0xffffffff, 0x00900100,
 640         0x311e, 0xffffffff, 0x00000080,
 641         0x3101, 0xffffffff, 0x0020003f,
 642         0x000c, 0xffffffff, 0x0000001c,
 643         0x000d, 0x000f0000, 0x000f0000,
 644         0x0583, 0xffffffff, 0x00000100,
 645         0x0409, 0xffffffff, 0x00000100,
 646         0x040b, 0x00000101, 0x00000000,
 647         0x082a, 0xffffffff, 0x00000104,
 648         0x1579, 0xff000fff, 0x00000100,
 649         0x157a, 0x00000001, 0x00000001,
 650         0x0bd4, 0x00000001, 0x00000001,
 651         0x0c33, 0xc0000fff, 0x00000104,
 652         0x3079, 0x00000001, 0x00000001,
 653         0x3430, 0xfffffff0, 0x00000100,
 654         0x3630, 0xfffffff0, 0x00000100
 655 };
 656 static const u32 verde_mgcg_cgcg_init[] =
 657 {
 658         0x3100, 0xffffffff, 0xfffffffc,
 659         0x200b, 0xffffffff, 0xe0000000,
 660         0x2698, 0xffffffff, 0x00000100,
 661         0x24a9, 0xffffffff, 0x00000100,
 662         0x3059, 0xffffffff, 0x00000100,
 663         0x25dd, 0xffffffff, 0x00000100,
 664         0x2261, 0xffffffff, 0x06000100,
 665         0x2286, 0xffffffff, 0x00000100,
 666         0x24a8, 0xffffffff, 0x00000100,
 667         0x30e0, 0xffffffff, 0x00000100,
 668         0x22ca, 0xffffffff, 0x00000100,
 669         0x2451, 0xffffffff, 0x00000100,
 670         0x2362, 0xffffffff, 0x00000100,
 671         0x2363, 0xffffffff, 0x00000100,
 672         0x240c, 0xffffffff, 0x00000100,
 673         0x240d, 0xffffffff, 0x00000100,
 674         0x240e, 0xffffffff, 0x00000100,
 675         0x240f, 0xffffffff, 0x00000100,
 676         0x2b60, 0xffffffff, 0x00000100,
 677         0x2b15, 0xffffffff, 0x00000100,
 678         0x225f, 0xffffffff, 0x06000100,
 679         0x261a, 0xffffffff, 0x00000100,
 680         0x2544, 0xffffffff, 0x00000100,
 681         0x2bc1, 0xffffffff, 0x00000100,
 682         0x2b81, 0xffffffff, 0x00000100,
 683         0x2527, 0xffffffff, 0x00000100,
 684         0x200b, 0xffffffff, 0xe0000000,
 685         0x2458, 0xffffffff, 0x00010000,
 686         0x2459, 0xffffffff, 0x00030002,
 687         0x245a, 0xffffffff, 0x00040007,
 688         0x245b, 0xffffffff, 0x00060005,
 689         0x245c, 0xffffffff, 0x00090008,
 690         0x245d, 0xffffffff, 0x00020001,
 691         0x245e, 0xffffffff, 0x00040003,
 692         0x245f, 0xffffffff, 0x00000007,
 693         0x2460, 0xffffffff, 0x00060005,
 694         0x2461, 0xffffffff, 0x00090008,
 695         0x2462, 0xffffffff, 0x00030002,
 696         0x2463, 0xffffffff, 0x00050004,
 697         0x2464, 0xffffffff, 0x00000008,
 698         0x2465, 0xffffffff, 0x00070006,
 699         0x2466, 0xffffffff, 0x000a0009,
 700         0x2467, 0xffffffff, 0x00040003,
 701         0x2468, 0xffffffff, 0x00060005,
 702         0x2469, 0xffffffff, 0x00000009,
 703         0x246a, 0xffffffff, 0x00080007,
 704         0x246b, 0xffffffff, 0x000b000a,
 705         0x246c, 0xffffffff, 0x00050004,
 706         0x246d, 0xffffffff, 0x00070006,
 707         0x246e, 0xffffffff, 0x0008000b,
 708         0x246f, 0xffffffff, 0x000a0009,
 709         0x2470, 0xffffffff, 0x000d000c,
 710         0x2480, 0xffffffff, 0x00090008,
 711         0x2481, 0xffffffff, 0x000b000a,
 712         0x2482, 0xffffffff, 0x000c000f,
 713         0x2483, 0xffffffff, 0x000e000d,
 714         0x2484, 0xffffffff, 0x00110010,
 715         0x2485, 0xffffffff, 0x000a0009,
 716         0x2486, 0xffffffff, 0x000c000b,
 717         0x2487, 0xffffffff, 0x0000000f,
 718         0x2488, 0xffffffff, 0x000e000d,
 719         0x2489, 0xffffffff, 0x00110010,
 720         0x248a, 0xffffffff, 0x000b000a,
 721         0x248b, 0xffffffff, 0x000d000c,
 722         0x248c, 0xffffffff, 0x00000010,
 723         0x248d, 0xffffffff, 0x000f000e,
 724         0x248e, 0xffffffff, 0x00120011,
 725         0x248f, 0xffffffff, 0x000c000b,
 726         0x2490, 0xffffffff, 0x000e000d,
 727         0x2491, 0xffffffff, 0x00000011,
 728         0x2492, 0xffffffff, 0x0010000f,
 729         0x2493, 0xffffffff, 0x00130012,
 730         0x2494, 0xffffffff, 0x000d000c,
 731         0x2495, 0xffffffff, 0x000f000e,
 732         0x2496, 0xffffffff, 0x00100013,
 733         0x2497, 0xffffffff, 0x00120011,
 734         0x2498, 0xffffffff, 0x00150014,
 735         0x2454, 0xffffffff, 0x96940200,
 736         0x21c2, 0xffffffff, 0x00900100,
 737         0x311e, 0xffffffff, 0x00000080,
 738         0x3101, 0xffffffff, 0x0020003f,
 739         0xc, 0xffffffff, 0x0000001c,
 740         0xd, 0x000f0000, 0x000f0000,
 741         0x583, 0xffffffff, 0x00000100,
 742         0x409, 0xffffffff, 0x00000100,
 743         0x40b, 0x00000101, 0x00000000,
 744         0x82a, 0xffffffff, 0x00000104,
 745         0x993, 0x000c0000, 0x000c0000,
 746         0x992, 0x000c0000, 0x000c0000,
 747         0x1579, 0xff000fff, 0x00000100,
 748         0x157a, 0x00000001, 0x00000001,
 749         0xbd4, 0x00000001, 0x00000001,
 750         0xc33, 0xc0000fff, 0x00000104,
 751         0x3079, 0x00000001, 0x00000001,
 752         0x3430, 0xfffffff0, 0x00000100,
 753         0x3630, 0xfffffff0, 0x00000100
 754 };
 755 static const u32 oland_mgcg_cgcg_init[] =
 756 {
 757         0x3100, 0xffffffff, 0xfffffffc,
 758         0x200b, 0xffffffff, 0xe0000000,
 759         0x2698, 0xffffffff, 0x00000100,
 760         0x24a9, 0xffffffff, 0x00000100,
 761         0x3059, 0xffffffff, 0x00000100,
 762         0x25dd, 0xffffffff, 0x00000100,
 763         0x2261, 0xffffffff, 0x06000100,
 764         0x2286, 0xffffffff, 0x00000100,
 765         0x24a8, 0xffffffff, 0x00000100,
 766         0x30e0, 0xffffffff, 0x00000100,
 767         0x22ca, 0xffffffff, 0x00000100,
 768         0x2451, 0xffffffff, 0x00000100,
 769         0x2362, 0xffffffff, 0x00000100,
 770         0x2363, 0xffffffff, 0x00000100,
 771         0x240c, 0xffffffff, 0x00000100,
 772         0x240d, 0xffffffff, 0x00000100,
 773         0x240e, 0xffffffff, 0x00000100,
 774         0x240f, 0xffffffff, 0x00000100,
 775         0x2b60, 0xffffffff, 0x00000100,
 776         0x2b15, 0xffffffff, 0x00000100,
 777         0x225f, 0xffffffff, 0x06000100,
 778         0x261a, 0xffffffff, 0x00000100,
 779         0x2544, 0xffffffff, 0x00000100,
 780         0x2bc1, 0xffffffff, 0x00000100,
 781         0x2b81, 0xffffffff, 0x00000100,
 782         0x2527, 0xffffffff, 0x00000100,
 783         0x200b, 0xffffffff, 0xe0000000,
 784         0x2458, 0xffffffff, 0x00010000,
 785         0x2459, 0xffffffff, 0x00030002,
 786         0x245a, 0xffffffff, 0x00040007,
 787         0x245b, 0xffffffff, 0x00060005,
 788         0x245c, 0xffffffff, 0x00090008,
 789         0x245d, 0xffffffff, 0x00020001,
 790         0x245e, 0xffffffff, 0x00040003,
 791         0x245f, 0xffffffff, 0x00000007,
 792         0x2460, 0xffffffff, 0x00060005,
 793         0x2461, 0xffffffff, 0x00090008,
 794         0x2462, 0xffffffff, 0x00030002,
 795         0x2463, 0xffffffff, 0x00050004,
 796         0x2464, 0xffffffff, 0x00000008,
 797         0x2465, 0xffffffff, 0x00070006,
 798         0x2466, 0xffffffff, 0x000a0009,
 799         0x2467, 0xffffffff, 0x00040003,
 800         0x2468, 0xffffffff, 0x00060005,
 801         0x2469, 0xffffffff, 0x00000009,
 802         0x246a, 0xffffffff, 0x00080007,
 803         0x246b, 0xffffffff, 0x000b000a,
 804         0x246c, 0xffffffff, 0x00050004,
 805         0x246d, 0xffffffff, 0x00070006,
 806         0x246e, 0xffffffff, 0x0008000b,
 807         0x246f, 0xffffffff, 0x000a0009,
 808         0x2470, 0xffffffff, 0x000d000c,
 809         0x2471, 0xffffffff, 0x00060005,
 810         0x2472, 0xffffffff, 0x00080007,
 811         0x2473, 0xffffffff, 0x0000000b,
 812         0x2474, 0xffffffff, 0x000a0009,
 813         0x2475, 0xffffffff, 0x000d000c,
 814         0x2454, 0xffffffff, 0x96940200,
 815         0x21c2, 0xffffffff, 0x00900100,
 816         0x311e, 0xffffffff, 0x00000080,
 817         0x3101, 0xffffffff, 0x0020003f,
 818         0x000c, 0xffffffff, 0x0000001c,
 819         0x000d, 0x000f0000, 0x000f0000,
 820         0x0583, 0xffffffff, 0x00000100,
 821         0x0409, 0xffffffff, 0x00000100,
 822         0x040b, 0x00000101, 0x00000000,
 823         0x082a, 0xffffffff, 0x00000104,
 824         0x0993, 0x000c0000, 0x000c0000,
 825         0x0992, 0x000c0000, 0x000c0000,
 826         0x1579, 0xff000fff, 0x00000100,
 827         0x157a, 0x00000001, 0x00000001,
 828         0x0bd4, 0x00000001, 0x00000001,
 829         0x0c33, 0xc0000fff, 0x00000104,
 830         0x3079, 0x00000001, 0x00000001,
 831         0x3430, 0xfffffff0, 0x00000100,
 832         0x3630, 0xfffffff0, 0x00000100
 833 };
 834 static const u32 hainan_mgcg_cgcg_init[] =
 835 {
 836         0x3100, 0xffffffff, 0xfffffffc,
 837         0x200b, 0xffffffff, 0xe0000000,
 838         0x2698, 0xffffffff, 0x00000100,
 839         0x24a9, 0xffffffff, 0x00000100,
 840         0x3059, 0xffffffff, 0x00000100,
 841         0x25dd, 0xffffffff, 0x00000100,
 842         0x2261, 0xffffffff, 0x06000100,
 843         0x2286, 0xffffffff, 0x00000100,
 844         0x24a8, 0xffffffff, 0x00000100,
 845         0x30e0, 0xffffffff, 0x00000100,
 846         0x22ca, 0xffffffff, 0x00000100,
 847         0x2451, 0xffffffff, 0x00000100,
 848         0x2362, 0xffffffff, 0x00000100,
 849         0x2363, 0xffffffff, 0x00000100,
 850         0x240c, 0xffffffff, 0x00000100,
 851         0x240d, 0xffffffff, 0x00000100,
 852         0x240e, 0xffffffff, 0x00000100,
 853         0x240f, 0xffffffff, 0x00000100,
 854         0x2b60, 0xffffffff, 0x00000100,
 855         0x2b15, 0xffffffff, 0x00000100,
 856         0x225f, 0xffffffff, 0x06000100,
 857         0x261a, 0xffffffff, 0x00000100,
 858         0x2544, 0xffffffff, 0x00000100,
 859         0x2bc1, 0xffffffff, 0x00000100,
 860         0x2b81, 0xffffffff, 0x00000100,
 861         0x2527, 0xffffffff, 0x00000100,
 862         0x200b, 0xffffffff, 0xe0000000,
 863         0x2458, 0xffffffff, 0x00010000,
 864         0x2459, 0xffffffff, 0x00030002,
 865         0x245a, 0xffffffff, 0x00040007,
 866         0x245b, 0xffffffff, 0x00060005,
 867         0x245c, 0xffffffff, 0x00090008,
 868         0x245d, 0xffffffff, 0x00020001,
 869         0x245e, 0xffffffff, 0x00040003,
 870         0x245f, 0xffffffff, 0x00000007,
 871         0x2460, 0xffffffff, 0x00060005,
 872         0x2461, 0xffffffff, 0x00090008,
 873         0x2462, 0xffffffff, 0x00030002,
 874         0x2463, 0xffffffff, 0x00050004,
 875         0x2464, 0xffffffff, 0x00000008,
 876         0x2465, 0xffffffff, 0x00070006,
 877         0x2466, 0xffffffff, 0x000a0009,
 878         0x2467, 0xffffffff, 0x00040003,
 879         0x2468, 0xffffffff, 0x00060005,
 880         0x2469, 0xffffffff, 0x00000009,
 881         0x246a, 0xffffffff, 0x00080007,
 882         0x246b, 0xffffffff, 0x000b000a,
 883         0x246c, 0xffffffff, 0x00050004,
 884         0x246d, 0xffffffff, 0x00070006,
 885         0x246e, 0xffffffff, 0x0008000b,
 886         0x246f, 0xffffffff, 0x000a0009,
 887         0x2470, 0xffffffff, 0x000d000c,
 888         0x2471, 0xffffffff, 0x00060005,
 889         0x2472, 0xffffffff, 0x00080007,
 890         0x2473, 0xffffffff, 0x0000000b,
 891         0x2474, 0xffffffff, 0x000a0009,
 892         0x2475, 0xffffffff, 0x000d000c,
 893         0x2454, 0xffffffff, 0x96940200,
 894         0x21c2, 0xffffffff, 0x00900100,
 895         0x311e, 0xffffffff, 0x00000080,
 896         0x3101, 0xffffffff, 0x0020003f,
 897         0x000c, 0xffffffff, 0x0000001c,
 898         0x000d, 0x000f0000, 0x000f0000,
 899         0x0583, 0xffffffff, 0x00000100,
 900         0x0409, 0xffffffff, 0x00000100,
 901         0x082a, 0xffffffff, 0x00000104,
 902         0x0993, 0x000c0000, 0x000c0000,
 903         0x0992, 0x000c0000, 0x000c0000,
 904         0x0bd4, 0x00000001, 0x00000001,
 905         0x0c33, 0xc0000fff, 0x00000104,
 906         0x3079, 0x00000001, 0x00000001,
 907         0x3430, 0xfffffff0, 0x00000100,
 908         0x3630, 0xfffffff0, 0x00000100
 909 };
 910
 911 static u32 si_pcie_rreg(struct amdgpu_device *adev, u32 reg)
 912 {
 913         unsigned long flags;
 914         u32 r;
 915
 916         spin_lock_irqsave(&adev->pcie_idx_lock, flags);
 917         WREG32(AMDGPU_PCIE_INDEX, reg);
 918         (void)RREG32(AMDGPU_PCIE_INDEX);
 919         r = RREG32(AMDGPU_PCIE_DATA);
 920         spin_unlock_irqrestore(&adev->pcie_idx_lock, flags);
 921         return r;
 922 }
 923
 924 static void si_pcie_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
 925 {
 926         unsigned long flags;
 927
 928         spin_lock_irqsave(&adev->pcie_idx_lock, flags);
 929         WREG32(AMDGPU_PCIE_INDEX, reg);
 930         (void)RREG32(AMDGPU_PCIE_INDEX);
 931         WREG32(AMDGPU_PCIE_DATA, v);
 932         (void)RREG32(AMDGPU_PCIE_DATA);
 933         spin_unlock_irqrestore(&adev->pcie_idx_lock, flags);
 934 }
 935
 936 static u32 si_pciep_rreg(struct amdgpu_device *adev, u32 reg)
 937 {
 938         unsigned long flags;
 939         u32 r;
 940
 941         spin_lock_irqsave(&adev->pcie_idx_lock, flags);
 942         WREG32(PCIE_PORT_INDEX, ((reg) & 0xff));
 943         (void)RREG32(PCIE_PORT_INDEX);
 944         r = RREG32(PCIE_PORT_DATA);
 945         spin_unlock_irqrestore(&adev->pcie_idx_lock, flags);
 946         return r;
 947 }
 948
 949 static void si_pciep_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
 950 {
 951         unsigned long flags;
 952
 953         spin_lock_irqsave(&adev->pcie_idx_lock, flags);
 954         WREG32(PCIE_PORT_INDEX, ((reg) & 0xff));
 955         (void)RREG32(PCIE_PORT_INDEX);
 956         WREG32(PCIE_PORT_DATA, (v));
 957         (void)RREG32(PCIE_PORT_DATA);
 958         spin_unlock_irqrestore(&adev->pcie_idx_lock, flags);
 959 }
 960
 961 static u32 si_smc_rreg(struct amdgpu_device *adev, u32 reg)
 962 {
 963         unsigned long flags;
 964         u32 r;
 965
 966         spin_lock_irqsave(&adev->smc_idx_lock, flags);
 967         WREG32(SMC_IND_INDEX_0, (reg));
 968         r = RREG32(SMC_IND_DATA_0);
 969         spin_unlock_irqrestore(&adev->smc_idx_lock, flags);
 970         return r;
 971 }
 972
 973 static void si_smc_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
 974 {
 975         unsigned long flags;
 976
 977         spin_lock_irqsave(&adev->smc_idx_lock, flags);
 978         WREG32(SMC_IND_INDEX_0, (reg));
 979         WREG32(SMC_IND_DATA_0, (v));
 980         spin_unlock_irqrestore(&adev->smc_idx_lock, flags);
 981 }
 982
 983 static struct amdgpu_allowed_register_entry si_allowed_read_registers[] = {
 984         {GRBM_STATUS, false},
 985         {GB_ADDR_CONFIG, false},
 986         {MC_ARB_RAMCFG, false},
 987         {GB_TILE_MODE0, false},
 988         {GB_TILE_MODE1, false},
 989         {GB_TILE_MODE2, false},
 990         {GB_TILE_MODE3, false},
 991         {GB_TILE_MODE4, false},
 992         {GB_TILE_MODE5, false},
 993         {GB_TILE_MODE6, false},
 994         {GB_TILE_MODE7, false},
 995         {GB_TILE_MODE8, false},
 996         {GB_TILE_MODE9, false},
 997         {GB_TILE_MODE10, false},
 998         {GB_TILE_MODE11, false},
 999         {GB_TILE_MODE12, false},
1000         {GB_TILE_MODE13, false},
1001         {GB_TILE_MODE14, false},
1002         {GB_TILE_MODE15, false},
1003         {GB_TILE_MODE16, false},
1004         {GB_TILE_MODE17, false},
1005         {GB_TILE_MODE18, false},
1006         {GB_TILE_MODE19, false},
1007         {GB_TILE_MODE20, false},
1008         {GB_TILE_MODE21, false},
1009         {GB_TILE_MODE22, false},
1010         {GB_TILE_MODE23, false},
1011         {GB_TILE_MODE24, false},
1012         {GB_TILE_MODE25, false},
1013         {GB_TILE_MODE26, false},
1014         {GB_TILE_MODE27, false},
1015         {GB_TILE_MODE28, false},
1016         {GB_TILE_MODE29, false},
1017         {GB_TILE_MODE30, false},
1018         {GB_TILE_MODE31, false},
1019         {CC_RB_BACKEND_DISABLE, false, true},
1020         {GC_USER_RB_BACKEND_DISABLE, false, true},
1021         {PA_SC_RASTER_CONFIG, false, true},
1022 };
1023
1024 static uint32_t si_read_indexed_register(struct amdgpu_device *adev,
1025                                           u32 se_num, u32 sh_num,
1026                                           u32 reg_offset)
1027 {
1028         uint32_t val;
1029
1030         mutex_lock(&adev->grbm_idx_mutex);
1031         if (se_num != 0xffffffff || sh_num != 0xffffffff)
1032                 amdgpu_gfx_select_se_sh(adev, se_num, sh_num, 0xffffffff);
1033
1034         val = RREG32(reg_offset);
1035
1036         if (se_num != 0xffffffff || sh_num != 0xffffffff)
1037                 amdgpu_gfx_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
1038         mutex_unlock(&adev->grbm_idx_mutex);
1039         return val;
1040 }
1041
1042 static int si_read_register(struct amdgpu_device *adev, u32 se_num,
1043                              u32 sh_num, u32 reg_offset, u32 *value)
1044 {
1045         uint32_t i;
1046
1047         *value = 0;
1048         for (i = 0; i < ARRAY_SIZE(si_allowed_read_registers); i++) {
1049                 if (reg_offset != si_allowed_read_registers[i].reg_offset)
1050                         continue;
1051
1052                 if (!si_allowed_read_registers[i].untouched)
1053                         *value = si_allowed_read_registers[i].grbm_indexed ?
1054                                  si_read_indexed_register(adev, se_num,
1055                                                            sh_num, reg_offset) :
1056                                  RREG32(reg_offset);
1057                 return 0;
1058         }
1059         return -EINVAL;
1060 }
1061
1062 static bool si_read_disabled_bios(struct amdgpu_device *adev)
1063 {
1064         u32 bus_cntl;
1065         u32 d1vga_control = 0;
1066         u32 d2vga_control = 0;
1067         u32 vga_render_control = 0;
1068         u32 rom_cntl;
1069         bool r;
1070
1071         bus_cntl = RREG32(R600_BUS_CNTL);
1072         if (adev->mode_info.num_crtc) {
1073                 d1vga_control = RREG32(AVIVO_D1VGA_CONTROL);
1074                 d2vga_control = RREG32(AVIVO_D2VGA_CONTROL);
1075                 vga_render_control = RREG32(VGA_RENDER_CONTROL);
1076         }
1077         rom_cntl = RREG32(R600_ROM_CNTL);
1078
1079         /* enable the rom */
1080         WREG32(R600_BUS_CNTL, (bus_cntl & ~R600_BIOS_ROM_DIS));
1081         if (adev->mode_info.num_crtc) {
1082                 /* Disable VGA mode */
1083                 WREG32(AVIVO_D1VGA_CONTROL,
1084                        (d1vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE |
1085                                           AVIVO_DVGA_CONTROL_TIMING_SELECT)));
1086                 WREG32(AVIVO_D2VGA_CONTROL,
1087                        (d2vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE |
1088                                           AVIVO_DVGA_CONTROL_TIMING_SELECT)));
1089                 WREG32(VGA_RENDER_CONTROL,
1090                        (vga_render_control & C_000300_VGA_VSTATUS_CNTL));
1091         }
1092         WREG32(R600_ROM_CNTL, rom_cntl | R600_SCK_OVERWRITE);
1093
1094         r = amdgpu_read_bios(adev);
1095
1096         /* restore regs */
1097         WREG32(R600_BUS_CNTL, bus_cntl);
1098         if (adev->mode_info.num_crtc) {
1099                 WREG32(AVIVO_D1VGA_CONTROL, d1vga_control);
1100                 WREG32(AVIVO_D2VGA_CONTROL, d2vga_control);
1101                 WREG32(VGA_RENDER_CONTROL, vga_render_control);
1102         }
1103         WREG32(R600_ROM_CNTL, rom_cntl);
1104         return r;
1105 }
1106
1107 //xxx: not implemented
1108 static int si_asic_reset(struct amdgpu_device *adev)
1109 {
1110         return 0;
1111 }
1112
1113 static void si_vga_set_state(struct amdgpu_device *adev, bool state)
1114 {
1115         uint32_t temp;
1116
1117         temp = RREG32(CONFIG_CNTL);
1118         if (state == false) {
1119                 temp &= ~(1<<0);
1120                 temp |= (1<<1);
1121         } else {
1122                 temp &= ~(1<<1);
1123         }
1124         WREG32(CONFIG_CNTL, temp);
1125 }
1126
1127 static u32 si_get_xclk(struct amdgpu_device *adev)
1128 {
1129         u32 reference_clock = adev->clock.spll.reference_freq;
1130         u32 tmp;
1131
1132         tmp = RREG32(CG_CLKPIN_CNTL_2);
1133         if (tmp & MUX_TCLK_TO_XCLK)
1134                 return TCLK;
1135
1136         tmp = RREG32(CG_CLKPIN_CNTL);
1137         if (tmp & XTALIN_DIVIDE)
1138                 return reference_clock / 4;
1139
1140         return reference_clock;
1141 }
1142
1143 //xxx:not implemented
1144 static int si_set_uvd_clocks(struct amdgpu_device *adev, u32 vclk, u32 dclk)
1145 {
1146         return 0;
1147 }
1148
1149 static void si_detect_hw_virtualization(struct amdgpu_device *adev)
1150 {
1151         if (is_virtual_machine()) /* passthrough mode */
1152                 adev->virtualization.virtual_caps |= AMDGPU_PASSTHROUGH_MODE;
1153 }
1154
1155 static const struct amdgpu_asic_funcs si_asic_funcs =
1156 {
1157         .read_disabled_bios = &si_read_disabled_bios,
1158         .detect_hw_virtualization = si_detect_hw_virtualization,
1159         .read_register = &si_read_register,
1160         .reset = &si_asic_reset,
1161         .set_vga_state = &si_vga_set_state,
1162         .get_xclk = &si_get_xclk,
1163         .set_uvd_clocks = &si_set_uvd_clocks,
1164         .set_vce_clocks = NULL,
1165 };
1166
1167 static uint32_t si_get_rev_id(struct amdgpu_device *adev)
1168 {
1169         return (RREG32(CC_DRM_ID_STRAPS) & CC_DRM_ID_STRAPS__ATI_REV_ID_MASK)
1170                 >> CC_DRM_ID_STRAPS__ATI_REV_ID__SHIFT;
1171 }
1172
1173 static int si_common_early_init(void *handle)
1174 {
1175         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1176
1177         adev->smc_rreg = &si_smc_rreg;
1178         adev->smc_wreg = &si_smc_wreg;
1179         adev->pcie_rreg = &si_pcie_rreg;
1180         adev->pcie_wreg = &si_pcie_wreg;
1181         adev->pciep_rreg = &si_pciep_rreg;
1182         adev->pciep_wreg = &si_pciep_wreg;
1183         adev->uvd_ctx_rreg = NULL;
1184         adev->uvd_ctx_wreg = NULL;
1185         adev->didt_rreg = NULL;
1186         adev->didt_wreg = NULL;
1187
1188         adev->asic_funcs = &si_asic_funcs;
1189
1190         adev->rev_id = si_get_rev_id(adev);
1191         adev->external_rev_id = 0xFF;
1192         switch (adev->asic_type) {
1193         case CHIP_TAHITI:
1194                 adev->cg_flags =
1195                         AMD_CG_SUPPORT_GFX_MGCG |
1196                         AMD_CG_SUPPORT_GFX_MGLS |
1197                         /*AMD_CG_SUPPORT_GFX_CGCG |*/
1198                         AMD_CG_SUPPORT_GFX_CGLS |
1199                         AMD_CG_SUPPORT_GFX_CGTS |
1200                         AMD_CG_SUPPORT_GFX_CP_LS |
1201                         AMD_CG_SUPPORT_MC_MGCG |
1202                         AMD_CG_SUPPORT_SDMA_MGCG |
1203                         AMD_CG_SUPPORT_BIF_LS |
1204                         AMD_CG_SUPPORT_VCE_MGCG |
1205                         AMD_CG_SUPPORT_UVD_MGCG |
1206                         AMD_CG_SUPPORT_HDP_LS |
1207                         AMD_CG_SUPPORT_HDP_MGCG;
1208                         adev->pg_flags = 0;
1209                 adev->external_rev_id = (adev->rev_id == 0) ? 1 :
1210                                         (adev->rev_id == 1) ? 5 : 6;
1211                 break;
1212         case CHIP_PITCAIRN:
1213                 adev->cg_flags =
1214                         AMD_CG_SUPPORT_GFX_MGCG |
1215                         AMD_CG_SUPPORT_GFX_MGLS |
1216                         /*AMD_CG_SUPPORT_GFX_CGCG |*/
1217                         AMD_CG_SUPPORT_GFX_CGLS |
1218                         AMD_CG_SUPPORT_GFX_CGTS |
1219                         AMD_CG_SUPPORT_GFX_CP_LS |
1220                         AMD_CG_SUPPORT_GFX_RLC_LS |
1221                         AMD_CG_SUPPORT_MC_LS |
1222                         AMD_CG_SUPPORT_MC_MGCG |
1223                         AMD_CG_SUPPORT_SDMA_MGCG |
1224                         AMD_CG_SUPPORT_BIF_LS |
1225                         AMD_CG_SUPPORT_VCE_MGCG |
1226                         AMD_CG_SUPPORT_UVD_MGCG |
1227                         AMD_CG_SUPPORT_HDP_LS |
1228                         AMD_CG_SUPPORT_HDP_MGCG;
1229                 adev->pg_flags = 0;
1230                 adev->external_rev_id = adev->rev_id + 20;
1231                 break;
1232
1233         case CHIP_VERDE:
1234                 adev->cg_flags =
1235                         AMD_CG_SUPPORT_GFX_MGCG |
1236                         AMD_CG_SUPPORT_GFX_MGLS |
1237                         AMD_CG_SUPPORT_GFX_CGLS |
1238                         AMD_CG_SUPPORT_GFX_CGTS |
1239                         AMD_CG_SUPPORT_GFX_CGTS_LS |
1240                         AMD_CG_SUPPORT_GFX_CP_LS |
1241                         AMD_CG_SUPPORT_MC_LS |
1242                         AMD_CG_SUPPORT_MC_MGCG |
1243                         AMD_CG_SUPPORT_SDMA_MGCG |
1244                         AMD_CG_SUPPORT_SDMA_LS |
1245                         AMD_CG_SUPPORT_BIF_LS |
1246                         AMD_CG_SUPPORT_VCE_MGCG |
1247                         AMD_CG_SUPPORT_UVD_MGCG |
1248                         AMD_CG_SUPPORT_HDP_LS |
1249                         AMD_CG_SUPPORT_HDP_MGCG;
1250                 adev->pg_flags = 0;
1251                 //???
1252                 adev->external_rev_id = adev->rev_id + 0x14;
1253                 break;
1254         case CHIP_OLAND:
1255                 adev->cg_flags =
1256                         AMD_CG_SUPPORT_GFX_MGCG |
1257                         AMD_CG_SUPPORT_GFX_MGLS |
1258                         /*AMD_CG_SUPPORT_GFX_CGCG |*/
1259                         AMD_CG_SUPPORT_GFX_CGLS |
1260                         AMD_CG_SUPPORT_GFX_CGTS |
1261                         AMD_CG_SUPPORT_GFX_CP_LS |
1262                         AMD_CG_SUPPORT_GFX_RLC_LS |
1263                         AMD_CG_SUPPORT_MC_LS |
1264                         AMD_CG_SUPPORT_MC_MGCG |
1265                         AMD_CG_SUPPORT_SDMA_MGCG |
1266                         AMD_CG_SUPPORT_BIF_LS |
1267                         AMD_CG_SUPPORT_UVD_MGCG |
1268                         AMD_CG_SUPPORT_HDP_LS |
1269                         AMD_CG_SUPPORT_HDP_MGCG;
1270                 adev->pg_flags = 0;
1271                 break;
1272         case CHIP_HAINAN:
1273                 adev->cg_flags =
1274                         AMD_CG_SUPPORT_GFX_MGCG |
1275                         AMD_CG_SUPPORT_GFX_MGLS |
1276                         /*AMD_CG_SUPPORT_GFX_CGCG |*/
1277                         AMD_CG_SUPPORT_GFX_CGLS |
1278                         AMD_CG_SUPPORT_GFX_CGTS |
1279                         AMD_CG_SUPPORT_GFX_CP_LS |
1280                         AMD_CG_SUPPORT_GFX_RLC_LS |
1281                         AMD_CG_SUPPORT_MC_LS |
1282                         AMD_CG_SUPPORT_MC_MGCG |
1283                         AMD_CG_SUPPORT_SDMA_MGCG |
1284                         AMD_CG_SUPPORT_BIF_LS |
1285                         AMD_CG_SUPPORT_HDP_LS |
1286                         AMD_CG_SUPPORT_HDP_MGCG;
1287                 adev->pg_flags = 0;
1288                 adev->external_rev_id = 70;
1289                 break;
1290
1291         default:
1292                 return -EINVAL;
1293         }
1294
1295         return 0;
1296 }
1297
1298 static int si_common_sw_init(void *handle)
1299 {
1300         return 0;
1301 }
1302
1303 static int si_common_sw_fini(void *handle)
1304 {
1305         return 0;
1306 }
1307
1308
1309 static void si_init_golden_registers(struct amdgpu_device *adev)
1310 {
1311         switch (adev->asic_type) {
1312         case CHIP_TAHITI:
1313                 amdgpu_program_register_sequence(adev,
1314                                                  tahiti_golden_registers,
1315                                                  (const u32)ARRAY_SIZE(tahiti_golden_registers));
1316                 amdgpu_program_register_sequence(adev,
1317                                                  tahiti_golden_rlc_registers,
1318                                                  (const u32)ARRAY_SIZE(tahiti_golden_rlc_registers));
1319                 amdgpu_program_register_sequence(adev,
1320                                                  tahiti_mgcg_cgcg_init,
1321                                                  (const u32)ARRAY_SIZE(tahiti_mgcg_cgcg_init));
1322                 amdgpu_program_register_sequence(adev,
1323                                                  tahiti_golden_registers2,
1324                                                  (const u32)ARRAY_SIZE(tahiti_golden_registers2));
1325                 break;
1326         case CHIP_PITCAIRN:
1327                 amdgpu_program_register_sequence(adev,
1328                                                  pitcairn_golden_registers,
1329                                                  (const u32)ARRAY_SIZE(pitcairn_golden_registers));
1330                 amdgpu_program_register_sequence(adev,
1331                                                  pitcairn_golden_rlc_registers,
1332                                                  (const u32)ARRAY_SIZE(pitcairn_golden_rlc_registers));
1333                 amdgpu_program_register_sequence(adev,
1334                                                  pitcairn_mgcg_cgcg_init,
1335                                                  (const u32)ARRAY_SIZE(pitcairn_mgcg_cgcg_init));
1336         case CHIP_VERDE:
1337                 amdgpu_program_register_sequence(adev,
1338                                                  verde_golden_registers,
1339                                                  (const u32)ARRAY_SIZE(verde_golden_registers));
1340                 amdgpu_program_register_sequence(adev,
1341                                                  verde_golden_rlc_registers,
1342                                                  (const u32)ARRAY_SIZE(verde_golden_rlc_registers));
1343                 amdgpu_program_register_sequence(adev,
1344                                                  verde_mgcg_cgcg_init,
1345                                                  (const u32)ARRAY_SIZE(verde_mgcg_cgcg_init));
1346                 amdgpu_program_register_sequence(adev,
1347                                                  verde_pg_init,
1348                                                  (const u32)ARRAY_SIZE(verde_pg_init));
1349                 break;
1350         case CHIP_OLAND:
1351                 amdgpu_program_register_sequence(adev,
1352                                                  oland_golden_registers,
1353                                                  (const u32)ARRAY_SIZE(oland_golden_registers));
1354                 amdgpu_program_register_sequence(adev,
1355                                                  oland_golden_rlc_registers,
1356                                                  (const u32)ARRAY_SIZE(oland_golden_rlc_registers));
1357                 amdgpu_program_register_sequence(adev,
1358                                                  oland_mgcg_cgcg_init,
1359                                                  (const u32)ARRAY_SIZE(oland_mgcg_cgcg_init));
1360         case CHIP_HAINAN:
1361                 amdgpu_program_register_sequence(adev,
1362                                                  hainan_golden_registers,
1363                                                  (const u32)ARRAY_SIZE(hainan_golden_registers));
1364                 amdgpu_program_register_sequence(adev,
1365                                                  hainan_golden_registers2,
1366                                                  (const u32)ARRAY_SIZE(hainan_golden_registers2));
1367                 amdgpu_program_register_sequence(adev,
1368                                                  hainan_mgcg_cgcg_init,
1369                                                  (const u32)ARRAY_SIZE(hainan_mgcg_cgcg_init));
1370                 break;
1371
1372
1373         default:
1374                 BUG();
1375         }
1376 }
1377
1378 static void si_pcie_gen3_enable(struct amdgpu_device *adev)
1379 {
1380         struct pci_dev *root = adev->pdev->bus->self;
1381         int bridge_pos, gpu_pos;
1382         u32 speed_cntl, mask, current_data_rate;
1383         int ret, i;
1384         u16 tmp16;
1385
1386         if (pci_is_root_bus(adev->pdev->bus))
1387                 return;
1388
1389         if (amdgpu_pcie_gen2 == 0)
1390                 return;
1391
1392         if (adev->flags & AMD_IS_APU)
1393                 return;
1394
1395         ret = drm_pcie_get_speed_cap_mask(adev->ddev, &mask);
1396         if (ret != 0)
1397                 return;
1398
1399         if (!(mask & (DRM_PCIE_SPEED_50 | DRM_PCIE_SPEED_80)))
1400                 return;
1401
1402         speed_cntl = RREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL);
1403         current_data_rate = (speed_cntl & LC_CURRENT_DATA_RATE_MASK) >>
1404                 LC_CURRENT_DATA_RATE_SHIFT;
1405         if (mask & DRM_PCIE_SPEED_80) {
1406                 if (current_data_rate == 2) {
1407                         DRM_INFO("PCIE gen 3 link speeds already enabled\n");
1408                         return;
1409                 }
1410                 DRM_INFO("enabling PCIE gen 3 link speeds, disable with amdgpu.pcie_gen2=0\n");
1411         } else if (mask & DRM_PCIE_SPEED_50) {
1412                 if (current_data_rate == 1) {
1413                         DRM_INFO("PCIE gen 2 link speeds already enabled\n");
1414                         return;
1415                 }
1416                 DRM_INFO("enabling PCIE gen 2 link speeds, disable with amdgpu.pcie_gen2=0\n");
1417         }
1418
1419         bridge_pos = pci_pcie_cap(root);
1420         if (!bridge_pos)
1421                 return;
1422
1423         gpu_pos = pci_pcie_cap(adev->pdev);
1424         if (!gpu_pos)
1425                 return;
1426
1427         if (mask & DRM_PCIE_SPEED_80) {
1428                 if (current_data_rate != 2) {
1429                         u16 bridge_cfg, gpu_cfg;
1430                         u16 bridge_cfg2, gpu_cfg2;
1431                         u32 max_lw, current_lw, tmp;
1432
1433                         pci_read_config_word(root, bridge_pos + PCI_EXP_LNKCTL, &bridge_cfg);
1434                         pci_read_config_word(adev->pdev, gpu_pos + PCI_EXP_LNKCTL, &gpu_cfg);
1435
1436                         tmp16 = bridge_cfg | PCI_EXP_LNKCTL_HAWD;
1437                         pci_write_config_word(root, bridge_pos + PCI_EXP_LNKCTL, tmp16);
1438
1439                         tmp16 = gpu_cfg | PCI_EXP_LNKCTL_HAWD;
1440                         pci_write_config_word(adev->pdev, gpu_pos + PCI_EXP_LNKCTL, tmp16);
1441
1442                         tmp = RREG32_PCIE(PCIE_LC_STATUS1);
1443                         max_lw = (tmp & LC_DETECTED_LINK_WIDTH_MASK) >> LC_DETECTED_LINK_WIDTH_SHIFT;
1444                         current_lw = (tmp & LC_OPERATING_LINK_WIDTH_MASK) >> LC_OPERATING_LINK_WIDTH_SHIFT;
1445
1446                         if (current_lw < max_lw) {
1447                                 tmp = RREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL);
1448                                 if (tmp & LC_RENEGOTIATION_SUPPORT) {
1449                                         tmp &= ~(LC_LINK_WIDTH_MASK | LC_UPCONFIGURE_DIS);
1450                                         tmp |= (max_lw << LC_LINK_WIDTH_SHIFT);
1451                                         tmp |= LC_UPCONFIGURE_SUPPORT | LC_RENEGOTIATE_EN | LC_RECONFIG_NOW;
1452                                         WREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL, tmp);
1453                                 }
1454                         }
1455
1456                         for (i = 0; i < 10; i++) {
1457                                 pci_read_config_word(adev->pdev, gpu_pos + PCI_EXP_DEVSTA, &tmp16);
1458                                 if (tmp16 & PCI_EXP_DEVSTA_TRPND)
1459                                         break;
1460
1461                                 pci_read_config_word(root, bridge_pos + PCI_EXP_LNKCTL, &bridge_cfg);
1462                                 pci_read_config_word(adev->pdev, gpu_pos + PCI_EXP_LNKCTL, &gpu_cfg);
1463
1464                                 pci_read_config_word(root, bridge_pos + PCI_EXP_LNKCTL2, &bridge_cfg2);
1465                                 pci_read_config_word(adev->pdev, gpu_pos + PCI_EXP_LNKCTL2, &gpu_cfg2);
1466
1467                                 tmp = RREG32_PCIE_PORT(PCIE_LC_CNTL4);
1468                                 tmp |= LC_SET_QUIESCE;
1469                                 WREG32_PCIE_PORT(PCIE_LC_CNTL4, tmp);
1470
1471                                 tmp = RREG32_PCIE_PORT(PCIE_LC_CNTL4);
1472                                 tmp |= LC_REDO_EQ;
1473                                 WREG32_PCIE_PORT(PCIE_LC_CNTL4, tmp);
1474
1475                                 mdelay(100);
1476
1477                                 pci_read_config_word(root, bridge_pos + PCI_EXP_LNKCTL, &tmp16);
1478                                 tmp16 &= ~PCI_EXP_LNKCTL_HAWD;
1479                                 tmp16 |= (bridge_cfg & PCI_EXP_LNKCTL_HAWD);
1480                                 pci_write_config_word(root, bridge_pos + PCI_EXP_LNKCTL, tmp16);
1481
1482                                 pci_read_config_word(adev->pdev, gpu_pos + PCI_EXP_LNKCTL, &tmp16);
1483                                 tmp16 &= ~PCI_EXP_LNKCTL_HAWD;
1484                                 tmp16 |= (gpu_cfg & PCI_EXP_LNKCTL_HAWD);
1485                                 pci_write_config_word(adev->pdev, gpu_pos + PCI_EXP_LNKCTL, tmp16);
1486
1487                                 pci_read_config_word(root, bridge_pos + PCI_EXP_LNKCTL2, &tmp16);
1488                                 tmp16 &= ~((1 << 4) | (7 << 9));
1489                                 tmp16 |= (bridge_cfg2 & ((1 << 4) | (7 << 9)));
1490                                 pci_write_config_word(root, bridge_pos + PCI_EXP_LNKCTL2, tmp16);
1491
1492                                 pci_read_config_word(adev->pdev, gpu_pos + PCI_EXP_LNKCTL2, &tmp16);
1493                                 tmp16 &= ~((1 << 4) | (7 << 9));
1494                                 tmp16 |= (gpu_cfg2 & ((1 << 4) | (7 << 9)));
1495                                 pci_write_config_word(adev->pdev, gpu_pos + PCI_EXP_LNKCTL2, tmp16);
1496
1497                                 tmp = RREG32_PCIE_PORT(PCIE_LC_CNTL4);
1498                                 tmp &= ~LC_SET_QUIESCE;
1499                                 WREG32_PCIE_PORT(PCIE_LC_CNTL4, tmp);
1500                         }
1501                 }
1502         }
1503
1504         speed_cntl |= LC_FORCE_EN_SW_SPEED_CHANGE | LC_FORCE_DIS_HW_SPEED_CHANGE;
1505         speed_cntl &= ~LC_FORCE_DIS_SW_SPEED_CHANGE;
1506         WREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL, speed_cntl);
1507
1508         pci_read_config_word(adev->pdev, gpu_pos + PCI_EXP_LNKCTL2, &tmp16);
1509         tmp16 &= ~0xf;
1510         if (mask & DRM_PCIE_SPEED_80)
1511                 tmp16 |= 3;
1512         else if (mask & DRM_PCIE_SPEED_50)
1513                 tmp16 |= 2;
1514         else
1515                 tmp16 |= 1;
1516         pci_write_config_word(adev->pdev, gpu_pos + PCI_EXP_LNKCTL2, tmp16);
1517
1518         speed_cntl = RREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL);
1519         speed_cntl |= LC_INITIATE_LINK_SPEED_CHANGE;
1520         WREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL, speed_cntl);
1521
1522         for (i = 0; i < adev->usec_timeout; i++) {
1523                 speed_cntl = RREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL);
1524                 if ((speed_cntl & LC_INITIATE_LINK_SPEED_CHANGE) == 0)
1525                         break;
1526                 udelay(1);
1527         }
1528 }
1529
1530 static inline u32 si_pif_phy0_rreg(struct amdgpu_device *adev, u32 reg)
1531 {
1532         unsigned long flags;
1533         u32 r;
1534
1535         spin_lock_irqsave(&adev->pcie_idx_lock, flags);
1536         WREG32(EVERGREEN_PIF_PHY0_INDEX, ((reg) & 0xffff));
1537         r = RREG32(EVERGREEN_PIF_PHY0_DATA);
1538         spin_unlock_irqrestore(&adev->pcie_idx_lock, flags);
1539         return r;
1540 }
1541
1542 static inline void si_pif_phy0_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
1543 {
1544         unsigned long flags;
1545
1546         spin_lock_irqsave(&adev->pcie_idx_lock, flags);
1547         WREG32(EVERGREEN_PIF_PHY0_INDEX, ((reg) & 0xffff));
1548         WREG32(EVERGREEN_PIF_PHY0_DATA, (v));
1549         spin_unlock_irqrestore(&adev->pcie_idx_lock, flags);
1550 }
1551
1552 static inline u32 si_pif_phy1_rreg(struct amdgpu_device *adev, u32 reg)
1553 {
1554         unsigned long flags;
1555         u32 r;
1556
1557         spin_lock_irqsave(&adev->pcie_idx_lock, flags);
1558         WREG32(EVERGREEN_PIF_PHY1_INDEX, ((reg) & 0xffff));
1559         r = RREG32(EVERGREEN_PIF_PHY1_DATA);
1560         spin_unlock_irqrestore(&adev->pcie_idx_lock, flags);
1561         return r;
1562 }
1563
1564 static inline void si_pif_phy1_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
1565 {
1566         unsigned long flags;
1567
1568         spin_lock_irqsave(&adev->pcie_idx_lock, flags);
1569         WREG32(EVERGREEN_PIF_PHY1_INDEX, ((reg) & 0xffff));
1570         WREG32(EVERGREEN_PIF_PHY1_DATA, (v));
1571         spin_unlock_irqrestore(&adev->pcie_idx_lock, flags);
1572 }
1573 static void si_program_aspm(struct amdgpu_device *adev)
1574 {
1575         u32 data, orig;
1576         bool disable_l0s = false, disable_l1 = false, disable_plloff_in_l1 = false;
1577         bool disable_clkreq = false;
1578
1579         if (amdgpu_aspm == 0)
1580                 return;
1581
1582         if (adev->flags & AMD_IS_APU)
1583                 return;
1584         orig = data = RREG32_PCIE_PORT(PCIE_LC_N_FTS_CNTL);
1585         data &= ~LC_XMIT_N_FTS_MASK;
1586         data |= LC_XMIT_N_FTS(0x24) | LC_XMIT_N_FTS_OVERRIDE_EN;
1587         if (orig != data)
1588                 WREG32_PCIE_PORT(PCIE_LC_N_FTS_CNTL, data);
1589
1590         orig = data = RREG32_PCIE_PORT(PCIE_LC_CNTL3);
1591         data |= LC_GO_TO_RECOVERY;
1592         if (orig != data)
1593                 WREG32_PCIE_PORT(PCIE_LC_CNTL3, data);
1594
1595         orig = data = RREG32_PCIE(PCIE_P_CNTL);
1596         data |= P_IGNORE_EDB_ERR;
1597         if (orig != data)
1598                 WREG32_PCIE(PCIE_P_CNTL, data);
1599
1600         orig = data = RREG32_PCIE_PORT(PCIE_LC_CNTL);
1601         data &= ~(LC_L0S_INACTIVITY_MASK | LC_L1_INACTIVITY_MASK);
1602         data |= LC_PMI_TO_L1_DIS;
1603         if (!disable_l0s)
1604                 data |= LC_L0S_INACTIVITY(7);
1605
1606         if (!disable_l1) {
1607                 data |= LC_L1_INACTIVITY(7);
1608                 data &= ~LC_PMI_TO_L1_DIS;
1609                 if (orig != data)
1610                         WREG32_PCIE_PORT(PCIE_LC_CNTL, data);
1611
1612                 if (!disable_plloff_in_l1) {
1613                         bool clk_req_support;
1614
1615                         orig = data = si_pif_phy0_rreg(adev,PB0_PIF_PWRDOWN_0);
1616                         data &= ~(PLL_POWER_STATE_IN_OFF_0_MASK | PLL_POWER_STATE_IN_TXS2_0_MASK);
1617                         data |= PLL_POWER_STATE_IN_OFF_0(7) | PLL_POWER_STATE_IN_TXS2_0(7);
1618                         if (orig != data)
1619                                 si_pif_phy0_wreg(adev,PB0_PIF_PWRDOWN_0, data);
1620
1621                         orig = data = si_pif_phy0_rreg(adev,PB0_PIF_PWRDOWN_1);
1622                         data &= ~(PLL_POWER_STATE_IN_OFF_1_MASK | PLL_POWER_STATE_IN_TXS2_1_MASK);
1623                         data |= PLL_POWER_STATE_IN_OFF_1(7) | PLL_POWER_STATE_IN_TXS2_1(7);
1624                         if (orig != data)
1625                                 si_pif_phy0_wreg(adev,PB0_PIF_PWRDOWN_1, data);
1626
1627                         orig = data = si_pif_phy1_rreg(adev,PB1_PIF_PWRDOWN_0);
1628                         data &= ~(PLL_POWER_STATE_IN_OFF_0_MASK | PLL_POWER_STATE_IN_TXS2_0_MASK);
1629                         data |= PLL_POWER_STATE_IN_OFF_0(7) | PLL_POWER_STATE_IN_TXS2_0(7);
1630                         if (orig != data)
1631                                 si_pif_phy1_wreg(adev,PB1_PIF_PWRDOWN_0, data);
1632
1633                         orig = data = si_pif_phy1_rreg(adev,PB1_PIF_PWRDOWN_1);
1634                         data &= ~(PLL_POWER_STATE_IN_OFF_1_MASK | PLL_POWER_STATE_IN_TXS2_1_MASK);
1635                         data |= PLL_POWER_STATE_IN_OFF_1(7) | PLL_POWER_STATE_IN_TXS2_1(7);
1636                         if (orig != data)
1637                                 si_pif_phy1_wreg(adev,PB1_PIF_PWRDOWN_1, data);
1638
1639                         if ((adev->family != CHIP_OLAND) && (adev->family != CHIP_HAINAN)) {
1640                                 orig = data = si_pif_phy0_rreg(adev,PB0_PIF_PWRDOWN_0);
1641                                 data &= ~PLL_RAMP_UP_TIME_0_MASK;
1642                                 if (orig != data)
1643                                         si_pif_phy0_wreg(adev,PB0_PIF_PWRDOWN_0, data);
1644
1645                                 orig = data = si_pif_phy0_rreg(adev,PB0_PIF_PWRDOWN_1);
1646                                 data &= ~PLL_RAMP_UP_TIME_1_MASK;
1647                                 if (orig != data)
1648                                         si_pif_phy0_wreg(adev,PB0_PIF_PWRDOWN_1, data);
1649
1650                                 orig = data = si_pif_phy0_rreg(adev,PB0_PIF_PWRDOWN_2);
1651                                 data &= ~PLL_RAMP_UP_TIME_2_MASK;
1652                                 if (orig != data)
1653                                         si_pif_phy0_wreg(adev,PB0_PIF_PWRDOWN_2, data);
1654
1655                                 orig = data = si_pif_phy0_rreg(adev,PB0_PIF_PWRDOWN_3);
1656                                 data &= ~PLL_RAMP_UP_TIME_3_MASK;
1657                                 if (orig != data)
1658                                         si_pif_phy0_wreg(adev,PB0_PIF_PWRDOWN_3, data);
1659
1660                                 orig = data = si_pif_phy1_rreg(adev,PB1_PIF_PWRDOWN_0);
1661                                 data &= ~PLL_RAMP_UP_TIME_0_MASK;
1662                                 if (orig != data)
1663                                         si_pif_phy1_wreg(adev,PB1_PIF_PWRDOWN_0, data);
1664
1665                                 orig = data = si_pif_phy1_rreg(adev,PB1_PIF_PWRDOWN_1);
1666                                 data &= ~PLL_RAMP_UP_TIME_1_MASK;
1667                                 if (orig != data)
1668                                         si_pif_phy1_wreg(adev,PB1_PIF_PWRDOWN_1, data);
1669
1670                                 orig = data = si_pif_phy1_rreg(adev,PB1_PIF_PWRDOWN_2);
1671                                 data &= ~PLL_RAMP_UP_TIME_2_MASK;
1672                                 if (orig != data)
1673                                         si_pif_phy1_wreg(adev,PB1_PIF_PWRDOWN_2, data);
1674
1675                                 orig = data = si_pif_phy1_rreg(adev,PB1_PIF_PWRDOWN_3);
1676                                 data &= ~PLL_RAMP_UP_TIME_3_MASK;
1677                                 if (orig != data)
1678                                         si_pif_phy1_wreg(adev,PB1_PIF_PWRDOWN_3, data);
1679                         }
1680                         orig = data = RREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL);
1681                         data &= ~LC_DYN_LANES_PWR_STATE_MASK;
1682                         data |= LC_DYN_LANES_PWR_STATE(3);
1683                         if (orig != data)
1684                                 WREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL, data);
1685
1686                         orig = data = si_pif_phy0_rreg(adev,PB0_PIF_CNTL);
1687                         data &= ~LS2_EXIT_TIME_MASK;
1688                         if ((adev->family == CHIP_OLAND) || (adev->family == CHIP_HAINAN))
1689                                 data |= LS2_EXIT_TIME(5);
1690                         if (orig != data)
1691                                 si_pif_phy0_wreg(adev,PB0_PIF_CNTL, data);
1692
1693                         orig = data = si_pif_phy1_rreg(adev,PB1_PIF_CNTL);
1694                         data &= ~LS2_EXIT_TIME_MASK;
1695                         if ((adev->family == CHIP_OLAND) || (adev->family == CHIP_HAINAN))
1696                                 data |= LS2_EXIT_TIME(5);
1697                         if (orig != data)
1698                                 si_pif_phy1_wreg(adev,PB1_PIF_CNTL, data);
1699
1700                         if (!disable_clkreq &&
1701                             !pci_is_root_bus(adev->pdev->bus)) {
1702                                 struct pci_dev *root = adev->pdev->bus->self;
1703                                 u32 lnkcap;
1704
1705                                 clk_req_support = false;
1706                                 pcie_capability_read_dword(root, PCI_EXP_LNKCAP, &lnkcap);
1707                                 if (lnkcap & PCI_EXP_LNKCAP_CLKPM)
1708                                         clk_req_support = true;
1709                         } else {
1710                                 clk_req_support = false;
1711                         }
1712
1713                         if (clk_req_support) {
1714                                 orig = data = RREG32_PCIE_PORT(PCIE_LC_CNTL2);
1715                                 data |= LC_ALLOW_PDWN_IN_L1 | LC_ALLOW_PDWN_IN_L23;
1716                                 if (orig != data)
1717                                         WREG32_PCIE_PORT(PCIE_LC_CNTL2, data);
1718
1719                                 orig = data = RREG32(THM_CLK_CNTL);
1720                                 data &= ~(CMON_CLK_SEL_MASK | TMON_CLK_SEL_MASK);
1721                                 data |= CMON_CLK_SEL(1) | TMON_CLK_SEL(1);
1722                                 if (orig != data)
1723                                         WREG32(THM_CLK_CNTL, data);
1724
1725                                 orig = data = RREG32(MISC_CLK_CNTL);
1726                                 data &= ~(DEEP_SLEEP_CLK_SEL_MASK | ZCLK_SEL_MASK);
1727                                 data |= DEEP_SLEEP_CLK_SEL(1) | ZCLK_SEL(1);
1728                                 if (orig != data)
1729                                         WREG32(MISC_CLK_CNTL, data);
1730
1731                                 orig = data = RREG32(CG_CLKPIN_CNTL);
1732                                 data &= ~BCLK_AS_XCLK;
1733                                 if (orig != data)
1734                                         WREG32(CG_CLKPIN_CNTL, data);
1735
1736                                 orig = data = RREG32(CG_CLKPIN_CNTL_2);
1737                                 data &= ~FORCE_BIF_REFCLK_EN;
1738                                 if (orig != data)
1739                                         WREG32(CG_CLKPIN_CNTL_2, data);
1740
1741                                 orig = data = RREG32(MPLL_BYPASSCLK_SEL);
1742                                 data &= ~MPLL_CLKOUT_SEL_MASK;
1743                                 data |= MPLL_CLKOUT_SEL(4);
1744                                 if (orig != data)
1745                                         WREG32(MPLL_BYPASSCLK_SEL, data);
1746
1747                                 orig = data = RREG32(SPLL_CNTL_MODE);
1748                                 data &= ~SPLL_REFCLK_SEL_MASK;
1749                                 if (orig != data)
1750                                         WREG32(SPLL_CNTL_MODE, data);
1751                         }
1752                 }
1753         } else {
1754                 if (orig != data)
1755                         WREG32_PCIE_PORT(PCIE_LC_CNTL, data);
1756         }
1757
1758         orig = data = RREG32_PCIE(PCIE_CNTL2);
1759         data |= SLV_MEM_LS_EN | MST_MEM_LS_EN | REPLAY_MEM_LS_EN;
1760         if (orig != data)
1761                 WREG32_PCIE(PCIE_CNTL2, data);
1762
1763         if (!disable_l0s) {
1764                 data = RREG32_PCIE_PORT(PCIE_LC_N_FTS_CNTL);
1765                 if((data & LC_N_FTS_MASK) == LC_N_FTS_MASK) {
1766                         data = RREG32_PCIE(PCIE_LC_STATUS1);
1767                         if ((data & LC_REVERSE_XMIT) && (data & LC_REVERSE_RCVR)) {
1768                                 orig = data = RREG32_PCIE_PORT(PCIE_LC_CNTL);
1769                                 data &= ~LC_L0S_INACTIVITY_MASK;
1770                                 if (orig != data)
1771                                         WREG32_PCIE_PORT(PCIE_LC_CNTL, data);
1772                         }
1773                 }
1774         }
1775 }
1776
1777 static void si_fix_pci_max_read_req_size(struct amdgpu_device *adev)
1778 {
1779         int readrq;
1780         u16 v;
1781
1782         readrq = pcie_get_readrq(adev->pdev);
1783         v = ffs(readrq) - 8;
1784         if ((v == 0) || (v == 6) || (v == 7))
1785                 pcie_set_readrq(adev->pdev, 512);
1786 }
1787
1788 static int si_common_hw_init(void *handle)
1789 {
1790         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1791
1792         si_fix_pci_max_read_req_size(adev);
1793         si_init_golden_registers(adev);
1794         si_pcie_gen3_enable(adev);
1795         si_program_aspm(adev);
1796
1797         return 0;
1798 }
1799
1800 static int si_common_hw_fini(void *handle)
1801 {
1802         return 0;
1803 }
1804
1805 static int si_common_suspend(void *handle)
1806 {
1807         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1808
1809         return si_common_hw_fini(adev);
1810 }
1811
1812 static int si_common_resume(void *handle)
1813 {
1814         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1815
1816         return si_common_hw_init(adev);
1817 }
1818
1819 static bool si_common_is_idle(void *handle)
1820 {
1821         return true;
1822 }
1823
1824 static int si_common_wait_for_idle(void *handle)
1825 {
1826         return 0;
1827 }
1828
1829 static int si_common_soft_reset(void *handle)
1830 {
1831         return 0;
1832 }
1833
1834 static int si_common_set_clockgating_state(void *handle,
1835                                             enum amd_clockgating_state state)
1836 {
1837         return 0;
1838 }
1839
1840 static int si_common_set_powergating_state(void *handle,
1841                                             enum amd_powergating_state state)
1842 {
1843         return 0;
1844 }
1845
1846 static const struct amd_ip_funcs si_common_ip_funcs = {
1847         .name = "si_common",
1848         .early_init = si_common_early_init,
1849         .late_init = NULL,
1850         .sw_init = si_common_sw_init,
1851         .sw_fini = si_common_sw_fini,
1852         .hw_init = si_common_hw_init,
1853         .hw_fini = si_common_hw_fini,
1854         .suspend = si_common_suspend,
1855         .resume = si_common_resume,
1856         .is_idle = si_common_is_idle,
1857         .wait_for_idle = si_common_wait_for_idle,
1858         .soft_reset = si_common_soft_reset,
1859         .set_clockgating_state = si_common_set_clockgating_state,
1860         .set_powergating_state = si_common_set_powergating_state,
1861 };
1862
1863 static const struct amdgpu_ip_block_version si_common_ip_block =
1864 {
1865         .type = AMD_IP_BLOCK_TYPE_COMMON,
1866         .major = 1,
1867         .minor = 0,
1868         .rev = 0,
1869         .funcs = &si_common_ip_funcs,
1870 };
1871
1872 int si_set_ip_blocks(struct amdgpu_device *adev)
1873 {
1874         switch (adev->asic_type) {
1875         case CHIP_VERDE:
1876         case CHIP_TAHITI:
1877         case CHIP_PITCAIRN:
1878                 amdgpu_ip_block_add(adev, &si_common_ip_block);
1879                 amdgpu_ip_block_add(adev, &gmc_v6_0_ip_block);
1880                 amdgpu_ip_block_add(adev, &si_ih_ip_block);
1881                 amdgpu_ip_block_add(adev, &amdgpu_pp_ip_block);
1882                 if (adev->enable_virtual_display)
1883                         amdgpu_ip_block_add(adev, &dce_virtual_ip_block);
1884                 else
1885                         amdgpu_ip_block_add(adev, &dce_v6_0_ip_block);
1886                 amdgpu_ip_block_add(adev, &gfx_v6_0_ip_block);
1887                 amdgpu_ip_block_add(adev, &si_dma_ip_block);
1888                 /* amdgpu_ip_block_add(adev, &uvd_v3_1_ip_block); */
1889                 /* amdgpu_ip_block_add(adev, &vce_v1_0_ip_block); */
1890                 break;
1891         case CHIP_OLAND:
1892                 amdgpu_ip_block_add(adev, &si_common_ip_block);
1893                 amdgpu_ip_block_add(adev, &gmc_v6_0_ip_block);
1894                 amdgpu_ip_block_add(adev, &si_ih_ip_block);
1895                 amdgpu_ip_block_add(adev, &amdgpu_pp_ip_block);
1896                 if (adev->enable_virtual_display)
1897                         amdgpu_ip_block_add(adev, &dce_virtual_ip_block);
1898                 else
1899                         amdgpu_ip_block_add(adev, &dce_v6_4_ip_block);
1900                 amdgpu_ip_block_add(adev, &gfx_v6_0_ip_block);
1901                 amdgpu_ip_block_add(adev, &si_dma_ip_block);
1902                 /* amdgpu_ip_block_add(adev, &uvd_v3_1_ip_block); */
1903                 /* amdgpu_ip_block_add(adev, &vce_v1_0_ip_block); */
1904                 break;
1905         case CHIP_HAINAN:
1906                 amdgpu_ip_block_add(adev, &si_common_ip_block);
1907                 amdgpu_ip_block_add(adev, &gmc_v6_0_ip_block);
1908                 amdgpu_ip_block_add(adev, &si_ih_ip_block);
1909                 amdgpu_ip_block_add(adev, &amdgpu_pp_ip_block);
1910                 if (adev->enable_virtual_display)
1911                         amdgpu_ip_block_add(adev, &dce_virtual_ip_block);
1912                 amdgpu_ip_block_add(adev, &gfx_v6_0_ip_block);
1913                 amdgpu_ip_block_add(adev, &si_dma_ip_block);
1914                 break;
1915         default:
1916                 BUG();
1917         }
1918         return 0;
1919 }
1920