drivers/gpu/drm/amd/amdgpu/si.c

   1 /*
   2  * Copyright 2015 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23
  24 #include <linux/firmware.h>
  25 #include <linux/slab.h>
  26 #include <linux/module.h>
  27 #include <drm/drmP.h>
  28 #include "amdgpu.h"
  29 #include "amdgpu_atombios.h"
  30 #include "amdgpu_ih.h"
  31 #include "amdgpu_uvd.h"
  32 #include "amdgpu_vce.h"
  33 #include "atom.h"
  34 #include "amd_pcie.h"
  35 #include "si_dpm.h"
  36 #include "sid.h"
  37 #include "si_ih.h"
  38 #include "gfx_v6_0.h"
  39 #include "gmc_v6_0.h"
  40 #include "si_dma.h"
  41 #include "dce_v6_0.h"
  42 #include "si.h"
  43 #include "dce_virtual.h"
  44 #include "gca/gfx_6_0_d.h"
  45 #include "oss/oss_1_0_d.h"
  46 #include "gmc/gmc_6_0_d.h"
  47 #include "dce/dce_6_0_d.h"
  48 #include "uvd/uvd_4_0_d.h"
  49 #include "bif/bif_3_0_d.h"
  50 #include "bif/bif_3_0_sh_mask.h"
  51
  52 static const u32 tahiti_golden_registers[] =
  53 {
  54         mmAZALIA_SCLK_CONTROL, 0x00000030, 0x00000011,
  55         mmCB_HW_CONTROL, 0x00010000, 0x00018208,
  56         mmDB_DEBUG, 0xffffffff, 0x00000000,
  57         mmDB_DEBUG2, 0xf00fffff, 0x00000400,
  58         mmDB_DEBUG3, 0x0002021c, 0x00020200,
  59         mmDCI_CLK_CNTL, 0x00000080, 0x00000000,
  60         0x340c, 0x000000c0, 0x00800040,
  61         0x360c, 0x000000c0, 0x00800040,
  62         mmFBC_DEBUG_COMP, 0x000000f0, 0x00000070,
  63         mmFBC_MISC, 0x00200000, 0x50100000,
  64         mmDIG0_HDMI_CONTROL, 0x31000311, 0x00000011,
  65         mmMC_ARB_WTM_CNTL_RD, 0x00000003, 0x000007ff,
  66         mmMC_XPB_P2P_BAR_CFG, 0x000007ff, 0x00000000,
  67         mmPA_CL_ENHANCE, 0xf000001f, 0x00000007,
  68         mmPA_SC_FORCE_EOV_MAX_CNTS, 0xffffffff, 0x00ffffff,
  69         mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000,
  70         mmPA_SC_MODE_CNTL_1, 0x07ffffff, 0x4e000000,
  71         mmPA_SC_RASTER_CONFIG, 0x3f3f3fff, 0x2a00126a,
  72         0x000c, 0xffffffff, 0x0040,
  73         0x000d, 0x00000040, 0x00004040,
  74         mmSPI_CONFIG_CNTL, 0x07ffffff, 0x03000000,
  75         mmSQ_DED_CNT, 0x01ff1f3f, 0x00000000,
  76         mmSQ_SEC_CNT, 0x01ff1f3f, 0x00000000,
  77         mmSX_DEBUG_1, 0x0000007f, 0x00000020,
  78         mmTA_CNTL_AUX, 0x00010000, 0x00010000,
  79         mmTCP_ADDR_CONFIG, 0x00000200, 0x000002fb,
  80         mmTCP_CHAN_STEER_HI, 0xffffffff, 0x0000543b,
  81         mmTCP_CHAN_STEER_LO, 0xffffffff, 0xa9210876,
  82         mmVGT_FIFO_DEPTHS, 0xffffffff, 0x000fff40,
  83         mmVGT_GS_VERTEX_REUSE, 0x0000001f, 0x00000010,
  84         mmVM_CONTEXT0_CNTL, 0x20000000, 0x20fffed8,
  85         mmVM_L2_CG, 0x000c0fc0, 0x000c0400,
  86         mmVM_PRT_APERTURE0_LOW_ADDR, 0x0fffffff, 0xffffffff,
  87         mmVM_PRT_APERTURE1_LOW_ADDR, 0x0fffffff, 0x0fffffff,
  88         mmVM_PRT_APERTURE2_LOW_ADDR, 0x0fffffff, 0x0fffffff,
  89         mmVM_PRT_APERTURE3_LOW_ADDR, 0x0fffffff, 0x0fffffff,
  90 };
  91
  92 static const u32 tahiti_golden_registers2[] =
  93 {
  94         mmMCIF_MEM_CONTROL, 0x00000001, 0x00000001,
  95 };
  96
  97 static const u32 tahiti_golden_rlc_registers[] =
  98 {
  99         mmGB_ADDR_CONFIG, 0xffffffff, 0x12011003,
 100         mmRLC_LB_PARAMS, 0xffffffff, 0x00601005,
 101         0x311f, 0xffffffff, 0x10104040,
 102         0x3122, 0xffffffff, 0x0100000a,
 103         mmRLC_LB_CNTR_MAX, 0xffffffff, 0x00000800,
 104         mmRLC_LB_CNTL, 0xffffffff, 0x800000f4,
 105         mmUVD_CGC_GATE, 0x00000008, 0x00000000,
 106 };
 107
 108 static const u32 pitcairn_golden_registers[] =
 109 {
 110         mmAZALIA_SCLK_CONTROL, 0x00000030, 0x00000011,
 111         mmCB_HW_CONTROL, 0x00010000, 0x00018208,
 112         mmDB_DEBUG, 0xffffffff, 0x00000000,
 113         mmDB_DEBUG2, 0xf00fffff, 0x00000400,
 114         mmDB_DEBUG3, 0x0002021c, 0x00020200,
 115         mmDCI_CLK_CNTL, 0x00000080, 0x00000000,
 116         0x340c, 0x000300c0, 0x00800040,
 117         0x360c, 0x000300c0, 0x00800040,
 118         mmFBC_DEBUG_COMP, 0x000000f0, 0x00000070,
 119         mmFBC_MISC, 0x00200000, 0x50100000,
 120         mmDIG0_HDMI_CONTROL, 0x31000311, 0x00000011,
 121         mmMC_SEQ_PMG_PG_HWCNTL, 0x00073ffe, 0x000022a2,
 122         mmMC_XPB_P2P_BAR_CFG, 0x000007ff, 0x00000000,
 123         mmPA_CL_ENHANCE, 0xf000001f, 0x00000007,
 124         mmPA_SC_FORCE_EOV_MAX_CNTS, 0xffffffff, 0x00ffffff,
 125         mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000,
 126         mmPA_SC_MODE_CNTL_1, 0x07ffffff, 0x4e000000,
 127         mmPA_SC_RASTER_CONFIG, 0x3f3f3fff, 0x2a00126a,
 128         0x000c, 0xffffffff, 0x0040,
 129         0x000d, 0x00000040, 0x00004040,
 130         mmSPI_CONFIG_CNTL, 0x07ffffff, 0x03000000,
 131         mmSX_DEBUG_1, 0x0000007f, 0x00000020,
 132         mmTA_CNTL_AUX, 0x00010000, 0x00010000,
 133         mmTCP_ADDR_CONFIG, 0x000003ff, 0x000000f7,
 134         mmTCP_CHAN_STEER_HI, 0xffffffff, 0x00000000,
 135         mmTCP_CHAN_STEER_LO, 0xffffffff, 0x32761054,
 136         mmVGT_GS_VERTEX_REUSE, 0x0000001f, 0x00000010,
 137         mmVM_L2_CG, 0x000c0fc0, 0x000c0400,
 138         mmVM_PRT_APERTURE0_LOW_ADDR, 0x0fffffff, 0xffffffff,
 139         mmVM_PRT_APERTURE1_LOW_ADDR, 0x0fffffff, 0x0fffffff,
 140         mmVM_PRT_APERTURE2_LOW_ADDR, 0x0fffffff, 0x0fffffff,
 141         mmVM_PRT_APERTURE3_LOW_ADDR, 0x0fffffff, 0x0fffffff,
 142 };
 143
 144 static const u32 pitcairn_golden_rlc_registers[] =
 145 {
 146         mmGB_ADDR_CONFIG, 0xffffffff, 0x12011003,
 147         mmRLC_LB_PARAMS, 0xffffffff, 0x00601004,
 148         0x311f, 0xffffffff, 0x10102020,
 149         0x3122, 0xffffffff, 0x01000020,
 150         mmRLC_LB_CNTR_MAX, 0xffffffff, 0x00000800,
 151         mmRLC_LB_CNTL, 0xffffffff, 0x800000a4,
 152 };
 153
 154 static const u32 verde_pg_init[] =
 155 {
 156         mmGMCON_PGFSM_WRITE, 0xffffffff, 0x40000,
 157         mmGMCON_PGFSM_CONFIG, 0xffffffff, 0x200010ff,
 158         mmGMCON_PGFSM_WRITE, 0xffffffff, 0x0,
 159         mmGMCON_PGFSM_WRITE, 0xffffffff, 0x0,
 160         mmGMCON_PGFSM_WRITE, 0xffffffff, 0x0,
 161         mmGMCON_PGFSM_WRITE, 0xffffffff, 0x0,
 162         mmGMCON_PGFSM_WRITE, 0xffffffff, 0x0,
 163         mmGMCON_PGFSM_WRITE, 0xffffffff, 0x7007,
 164         mmGMCON_PGFSM_CONFIG, 0xffffffff, 0x300010ff,
 165         mmGMCON_PGFSM_WRITE, 0xffffffff, 0x0,
 166         mmGMCON_PGFSM_WRITE, 0xffffffff, 0x0,
 167         mmGMCON_PGFSM_WRITE, 0xffffffff, 0x0,
 168         mmGMCON_PGFSM_WRITE, 0xffffffff, 0x0,
 169         mmGMCON_PGFSM_WRITE, 0xffffffff, 0x0,
 170         mmGMCON_PGFSM_WRITE, 0xffffffff, 0x400000,
 171         mmGMCON_PGFSM_CONFIG, 0xffffffff, 0x100010ff,
 172         mmGMCON_PGFSM_WRITE, 0xffffffff, 0x0,
 173         mmGMCON_PGFSM_WRITE, 0xffffffff, 0x0,
 174         mmGMCON_PGFSM_WRITE, 0xffffffff, 0x0,
 175         mmGMCON_PGFSM_WRITE, 0xffffffff, 0x0,
 176         mmGMCON_PGFSM_WRITE, 0xffffffff, 0x0,
 177         mmGMCON_PGFSM_WRITE, 0xffffffff, 0x120200,
 178         mmGMCON_PGFSM_CONFIG, 0xffffffff, 0x500010ff,
 179         mmGMCON_PGFSM_WRITE, 0xffffffff, 0x0,
 180         mmGMCON_PGFSM_WRITE, 0xffffffff, 0x0,
 181         mmGMCON_PGFSM_WRITE, 0xffffffff, 0x0,
 182         mmGMCON_PGFSM_WRITE, 0xffffffff, 0x0,
 183         mmGMCON_PGFSM_WRITE, 0xffffffff, 0x0,
 184         mmGMCON_PGFSM_WRITE, 0xffffffff, 0x1e1e16,
 185         mmGMCON_PGFSM_CONFIG, 0xffffffff, 0x600010ff,
 186         mmGMCON_PGFSM_WRITE, 0xffffffff, 0x0,
 187         mmGMCON_PGFSM_WRITE, 0xffffffff, 0x0,
 188         mmGMCON_PGFSM_WRITE, 0xffffffff, 0x0,
 189         mmGMCON_PGFSM_WRITE, 0xffffffff, 0x0,
 190         mmGMCON_PGFSM_WRITE, 0xffffffff, 0x0,
 191         mmGMCON_PGFSM_WRITE, 0xffffffff, 0x171f1e,
 192         mmGMCON_PGFSM_CONFIG, 0xffffffff, 0x700010ff,
 193         mmGMCON_PGFSM_WRITE, 0xffffffff, 0x0,
 194         mmGMCON_PGFSM_WRITE, 0xffffffff, 0x0,
 195         mmGMCON_PGFSM_WRITE, 0xffffffff, 0x0,
 196         mmGMCON_PGFSM_WRITE, 0xffffffff, 0x0,
 197         mmGMCON_PGFSM_WRITE, 0xffffffff, 0x0,
 198         mmGMCON_PGFSM_WRITE, 0xffffffff, 0x0,
 199         mmGMCON_PGFSM_CONFIG, 0xffffffff, 0x9ff,
 200         mmGMCON_RENG_RAM_INDEX, 0xffffffff, 0x0,
 201         mmGMCON_RENG_RAM_DATA, 0xffffffff, 0x10000800,
 202         mmGMCON_RENG_RAM_DATA, 0xffffffff, 0xf,
 203         mmGMCON_RENG_RAM_DATA, 0xffffffff, 0xf,
 204         mmGMCON_RENG_RAM_INDEX, 0xffffffff, 0x4,
 205         mmGMCON_RENG_RAM_DATA, 0xffffffff, 0x1000051e,
 206         mmGMCON_RENG_RAM_DATA, 0xffffffff, 0xffff,
 207         mmGMCON_RENG_RAM_DATA, 0xffffffff, 0xffff,
 208         mmGMCON_RENG_RAM_INDEX, 0xffffffff, 0x8,
 209         mmGMCON_RENG_RAM_DATA, 0xffffffff, 0x80500,
 210         mmGMCON_RENG_RAM_INDEX, 0xffffffff, 0x12,
 211         mmGMCON_RENG_RAM_DATA, 0xffffffff, 0x9050c,
 212         mmGMCON_RENG_RAM_INDEX, 0xffffffff, 0x1d,
 213         mmGMCON_RENG_RAM_DATA, 0xffffffff, 0xb052c,
 214         mmGMCON_RENG_RAM_INDEX, 0xffffffff, 0x2a,
 215         mmGMCON_RENG_RAM_DATA, 0xffffffff, 0x1053e,
 216         mmGMCON_RENG_RAM_INDEX, 0xffffffff, 0x2d,
 217         mmGMCON_RENG_RAM_DATA, 0xffffffff, 0x10546,
 218         mmGMCON_RENG_RAM_INDEX, 0xffffffff, 0x30,
 219         mmGMCON_RENG_RAM_DATA, 0xffffffff, 0xa054e,
 220         mmGMCON_RENG_RAM_INDEX, 0xffffffff, 0x3c,
 221         mmGMCON_RENG_RAM_DATA, 0xffffffff, 0x1055f,
 222         mmGMCON_RENG_RAM_INDEX, 0xffffffff, 0x3f,
 223         mmGMCON_RENG_RAM_DATA, 0xffffffff, 0x10567,
 224         mmGMCON_RENG_RAM_INDEX, 0xffffffff, 0x42,
 225         mmGMCON_RENG_RAM_DATA, 0xffffffff, 0x1056f,
 226         mmGMCON_RENG_RAM_INDEX, 0xffffffff, 0x45,
 227         mmGMCON_RENG_RAM_DATA, 0xffffffff, 0x10572,
 228         mmGMCON_RENG_RAM_INDEX, 0xffffffff, 0x48,
 229         mmGMCON_RENG_RAM_DATA, 0xffffffff, 0x20575,
 230         mmGMCON_RENG_RAM_INDEX, 0xffffffff, 0x4c,
 231         mmGMCON_RENG_RAM_DATA, 0xffffffff, 0x190801,
 232         mmGMCON_RENG_RAM_INDEX, 0xffffffff, 0x67,
 233         mmGMCON_RENG_RAM_DATA, 0xffffffff, 0x1082a,
 234         mmGMCON_RENG_RAM_INDEX, 0xffffffff, 0x6a,
 235         mmGMCON_RENG_RAM_DATA, 0xffffffff, 0x1b082d,
 236         mmGMCON_RENG_RAM_INDEX, 0xffffffff, 0x87,
 237         mmGMCON_RENG_RAM_DATA, 0xffffffff, 0x310851,
 238         mmGMCON_RENG_RAM_INDEX, 0xffffffff, 0xba,
 239         mmGMCON_RENG_RAM_DATA, 0xffffffff, 0x891,
 240         mmGMCON_RENG_RAM_INDEX, 0xffffffff, 0xbc,
 241         mmGMCON_RENG_RAM_DATA, 0xffffffff, 0x893,
 242         mmGMCON_RENG_RAM_INDEX, 0xffffffff, 0xbe,
 243         mmGMCON_RENG_RAM_DATA, 0xffffffff, 0x20895,
 244         mmGMCON_RENG_RAM_INDEX, 0xffffffff, 0xc2,
 245         mmGMCON_RENG_RAM_DATA, 0xffffffff, 0x20899,
 246         mmGMCON_RENG_RAM_INDEX, 0xffffffff, 0xc6,
 247         mmGMCON_RENG_RAM_DATA, 0xffffffff, 0x2089d,
 248         mmGMCON_RENG_RAM_INDEX, 0xffffffff, 0xca,
 249         mmGMCON_RENG_RAM_DATA, 0xffffffff, 0x8a1,
 250         mmGMCON_RENG_RAM_INDEX, 0xffffffff, 0xcc,
 251         mmGMCON_RENG_RAM_DATA, 0xffffffff, 0x8a3,
 252         mmGMCON_RENG_RAM_INDEX, 0xffffffff, 0xce,
 253         mmGMCON_RENG_RAM_DATA, 0xffffffff, 0x308a5,
 254         mmGMCON_RENG_RAM_INDEX, 0xffffffff, 0xd3,
 255         mmGMCON_RENG_RAM_DATA, 0xffffffff, 0x6d08cd,
 256         mmGMCON_RENG_RAM_INDEX, 0xffffffff, 0x142,
 257         mmGMCON_RENG_RAM_DATA, 0xffffffff, 0x2000095a,
 258         mmGMCON_RENG_RAM_DATA, 0xffffffff, 0x1,
 259         mmGMCON_RENG_RAM_INDEX, 0xffffffff, 0x144,
 260         mmGMCON_RENG_RAM_DATA, 0xffffffff, 0x301f095b,
 261         mmGMCON_RENG_RAM_INDEX, 0xffffffff, 0x165,
 262         mmGMCON_RENG_RAM_DATA, 0xffffffff, 0xc094d,
 263         mmGMCON_RENG_RAM_INDEX, 0xffffffff, 0x173,
 264         mmGMCON_RENG_RAM_DATA, 0xffffffff, 0xf096d,
 265         mmGMCON_RENG_RAM_INDEX, 0xffffffff, 0x184,
 266         mmGMCON_RENG_RAM_DATA, 0xffffffff, 0x15097f,
 267         mmGMCON_RENG_RAM_INDEX, 0xffffffff, 0x19b,
 268         mmGMCON_RENG_RAM_DATA, 0xffffffff, 0xc0998,
 269         mmGMCON_RENG_RAM_INDEX, 0xffffffff, 0x1a9,
 270         mmGMCON_RENG_RAM_DATA, 0xffffffff, 0x409a7,
 271         mmGMCON_RENG_RAM_INDEX, 0xffffffff, 0x1af,
 272         mmGMCON_RENG_RAM_DATA, 0xffffffff, 0xcdc,
 273         mmGMCON_RENG_RAM_INDEX, 0xffffffff, 0x1b1,
 274         mmGMCON_RENG_RAM_DATA, 0xffffffff, 0x800,
 275         mmGMCON_RENG_EXECUTE, 0xffffffff, 0x6c9b2000,
 276         mmGMCON_MISC2, 0xfc00, 0x2000,
 277         mmGMCON_MISC3, 0xffffffff, 0xfc0,
 278         mmMC_PMG_AUTO_CFG, 0x00000100, 0x100,
 279 };
 280
 281 static const u32 verde_golden_rlc_registers[] =
 282 {
 283         mmGB_ADDR_CONFIG, 0xffffffff, 0x02010002,
 284         mmRLC_LB_PARAMS, 0xffffffff, 0x033f1005,
 285         0x311f, 0xffffffff, 0x10808020,
 286         0x3122, 0xffffffff, 0x00800008,
 287         mmRLC_LB_CNTR_MAX, 0xffffffff, 0x00001000,
 288         mmRLC_LB_CNTL, 0xffffffff, 0x80010014,
 289 };
 290
 291 static const u32 verde_golden_registers[] =
 292 {
 293         mmAZALIA_SCLK_CONTROL, 0x00000030, 0x00000011,
 294         mmCB_HW_CONTROL, 0x00010000, 0x00018208,
 295         mmDB_DEBUG, 0xffffffff, 0x00000000,
 296         mmDB_DEBUG2, 0xf00fffff, 0x00000400,
 297         mmDB_DEBUG3, 0x0002021c, 0x00020200,
 298         mmDCI_CLK_CNTL, 0x00000080, 0x00000000,
 299         0x340c, 0x000300c0, 0x00800040,
 300         0x360c, 0x000300c0, 0x00800040,
 301         mmFBC_DEBUG_COMP, 0x000000f0, 0x00000070,
 302         mmFBC_MISC, 0x00200000, 0x50100000,
 303         mmDIG0_HDMI_CONTROL, 0x31000311, 0x00000011,
 304         mmMC_SEQ_PMG_PG_HWCNTL, 0x00073ffe, 0x000022a2,
 305         mmMC_XPB_P2P_BAR_CFG, 0x000007ff, 0x00000000,
 306         mmPA_CL_ENHANCE, 0xf000001f, 0x00000007,
 307         mmPA_SC_FORCE_EOV_MAX_CNTS, 0xffffffff, 0x00ffffff,
 308         mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000,
 309         mmPA_SC_MODE_CNTL_1, 0x07ffffff, 0x4e000000,
 310         mmPA_SC_RASTER_CONFIG, 0x3f3f3fff, 0x0000124a,
 311         0x000c, 0xffffffff, 0x0040,
 312         0x000d, 0x00000040, 0x00004040,
 313         mmSPI_CONFIG_CNTL, 0x07ffffff, 0x03000000,
 314         mmSQ_DED_CNT, 0x01ff1f3f, 0x00000000,
 315         mmSQ_SEC_CNT, 0x01ff1f3f, 0x00000000,
 316         mmSX_DEBUG_1, 0x0000007f, 0x00000020,
 317         mmTA_CNTL_AUX, 0x00010000, 0x00010000,
 318         mmTCP_ADDR_CONFIG, 0x000003ff, 0x00000003,
 319         mmTCP_CHAN_STEER_HI, 0xffffffff, 0x00000000,
 320         mmTCP_CHAN_STEER_LO, 0xffffffff, 0x00001032,
 321         mmVGT_GS_VERTEX_REUSE, 0x0000001f, 0x00000010,
 322         mmVM_L2_CG, 0x000c0fc0, 0x000c0400,
 323         mmVM_PRT_APERTURE0_LOW_ADDR, 0x0fffffff, 0xffffffff,
 324         mmVM_PRT_APERTURE1_LOW_ADDR, 0x0fffffff, 0x0fffffff,
 325         mmVM_PRT_APERTURE2_LOW_ADDR, 0x0fffffff, 0x0fffffff,
 326         mmVM_PRT_APERTURE3_LOW_ADDR, 0x0fffffff, 0x0fffffff,
 327 };
 328
 329 static const u32 oland_golden_registers[] =
 330 {
 331         mmAZALIA_SCLK_CONTROL, 0x00000030, 0x00000011,
 332         mmCB_HW_CONTROL, 0x00010000, 0x00018208,
 333         mmDB_DEBUG, 0xffffffff, 0x00000000,
 334         mmDB_DEBUG2, 0xf00fffff, 0x00000400,
 335         mmDB_DEBUG3, 0x0002021c, 0x00020200,
 336         mmDCI_CLK_CNTL, 0x00000080, 0x00000000,
 337         0x340c, 0x000300c0, 0x00800040,
 338         0x360c, 0x000300c0, 0x00800040,
 339         mmFBC_DEBUG_COMP, 0x000000f0, 0x00000070,
 340         mmFBC_MISC, 0x00200000, 0x50100000,
 341         mmDIG0_HDMI_CONTROL, 0x31000311, 0x00000011,
 342         mmMC_SEQ_PMG_PG_HWCNTL, 0x00073ffe, 0x000022a2,
 343         mmMC_XPB_P2P_BAR_CFG, 0x000007ff, 0x00000000,
 344         mmPA_CL_ENHANCE, 0xf000001f, 0x00000007,
 345         mmPA_SC_FORCE_EOV_MAX_CNTS, 0xffffffff, 0x00ffffff,
 346         mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000,
 347         mmPA_SC_MODE_CNTL_1, 0x07ffffff, 0x4e000000,
 348         mmPA_SC_RASTER_CONFIG, 0x3f3f3fff, 0x00000082,
 349         0x000c, 0xffffffff, 0x0040,
 350         0x000d, 0x00000040, 0x00004040,
 351         mmSPI_CONFIG_CNTL, 0x07ffffff, 0x03000000,
 352         mmSX_DEBUG_1, 0x0000007f, 0x00000020,
 353         mmTA_CNTL_AUX, 0x00010000, 0x00010000,
 354         mmTCP_ADDR_CONFIG, 0x000003ff, 0x000000f3,
 355         mmTCP_CHAN_STEER_HI, 0xffffffff, 0x00000000,
 356         mmTCP_CHAN_STEER_LO, 0xffffffff, 0x00003210,
 357         mmVGT_GS_VERTEX_REUSE, 0x0000001f, 0x00000010,
 358         mmVM_L2_CG, 0x000c0fc0, 0x000c0400,
 359         mmVM_PRT_APERTURE0_LOW_ADDR, 0x0fffffff, 0xffffffff,
 360         mmVM_PRT_APERTURE1_LOW_ADDR, 0x0fffffff, 0x0fffffff,
 361         mmVM_PRT_APERTURE2_LOW_ADDR, 0x0fffffff, 0x0fffffff,
 362         mmVM_PRT_APERTURE3_LOW_ADDR, 0x0fffffff, 0x0fffffff,
 363
 364 };
 365
 366 static const u32 oland_golden_rlc_registers[] =
 367 {
 368         mmGB_ADDR_CONFIG, 0xffffffff, 0x02010002,
 369         mmRLC_LB_PARAMS, 0xffffffff, 0x00601005,
 370         0x311f, 0xffffffff, 0x10104040,
 371         0x3122, 0xffffffff, 0x0100000a,
 372         mmRLC_LB_CNTR_MAX, 0xffffffff, 0x00000800,
 373         mmRLC_LB_CNTL, 0xffffffff, 0x800000f4,
 374 };
 375
 376 static const u32 hainan_golden_registers[] =
 377 {
 378         0x17bc, 0x00000030, 0x00000011,
 379         mmCB_HW_CONTROL, 0x00010000, 0x00018208,
 380         mmDB_DEBUG, 0xffffffff, 0x00000000,
 381         mmDB_DEBUG2, 0xf00fffff, 0x00000400,
 382         mmDB_DEBUG3, 0x0002021c, 0x00020200,
 383         0x031e, 0x00000080, 0x00000000,
 384         0x3430, 0xff000fff, 0x00000100,
 385         0x340c, 0x000300c0, 0x00800040,
 386         0x3630, 0xff000fff, 0x00000100,
 387         0x360c, 0x000300c0, 0x00800040,
 388         0x16ec, 0x000000f0, 0x00000070,
 389         0x16f0, 0x00200000, 0x50100000,
 390         0x1c0c, 0x31000311, 0x00000011,
 391         mmMC_SEQ_PMG_PG_HWCNTL, 0x00073ffe, 0x000022a2,
 392         mmMC_XPB_P2P_BAR_CFG, 0x000007ff, 0x00000000,
 393         mmPA_CL_ENHANCE, 0xf000001f, 0x00000007,
 394         mmPA_SC_FORCE_EOV_MAX_CNTS, 0xffffffff, 0x00ffffff,
 395         mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000,
 396         mmPA_SC_MODE_CNTL_1, 0x07ffffff, 0x4e000000,
 397         mmPA_SC_RASTER_CONFIG, 0x3f3f3fff, 0x00000000,
 398         0x000c, 0xffffffff, 0x0040,
 399         0x000d, 0x00000040, 0x00004040,
 400         mmSPI_CONFIG_CNTL, 0x03e00000, 0x03600000,
 401         mmSX_DEBUG_1, 0x0000007f, 0x00000020,
 402         mmTA_CNTL_AUX, 0x00010000, 0x00010000,
 403         mmTCP_ADDR_CONFIG, 0x000003ff, 0x000000f1,
 404         mmTCP_CHAN_STEER_HI, 0xffffffff, 0x00000000,
 405         mmTCP_CHAN_STEER_LO, 0xffffffff, 0x00003210,
 406         mmVGT_GS_VERTEX_REUSE, 0x0000001f, 0x00000010,
 407         mmVM_L2_CG, 0x000c0fc0, 0x000c0400,
 408         mmVM_PRT_APERTURE0_LOW_ADDR, 0x0fffffff, 0xffffffff,
 409         mmVM_PRT_APERTURE1_LOW_ADDR, 0x0fffffff, 0x0fffffff,
 410         mmVM_PRT_APERTURE2_LOW_ADDR, 0x0fffffff, 0x0fffffff,
 411         mmVM_PRT_APERTURE3_LOW_ADDR, 0x0fffffff, 0x0fffffff,
 412 };
 413
 414 static const u32 hainan_golden_registers2[] =
 415 {
 416         mmGB_ADDR_CONFIG, 0xffffffff, 0x2011003,
 417 };
 418
 419 static const u32 tahiti_mgcg_cgcg_init[] =
 420 {
 421         mmRLC_CGTT_MGCG_OVERRIDE, 0xffffffff, 0xfffffffc,
 422         mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000,
 423         mmCB_CGTT_SCLK_CTRL, 0xffffffff, 0x00000100,
 424         mmCGTT_BCI_CLK_CTRL, 0xffffffff, 0x00000100,
 425         mmCGTT_CP_CLK_CTRL, 0xffffffff, 0x00000100,
 426         mmCGTT_GDS_CLK_CTRL, 0xffffffff, 0x00000100,
 427         mmCGTT_IA_CLK_CTRL, 0xffffffff, 0x06000100,
 428         mmCGTT_PA_CLK_CTRL, 0xffffffff, 0x00000100,
 429         mmCGTT_PC_CLK_CTRL, 0xffffffff, 0x00000100,
 430         mmCGTT_RLC_CLK_CTRL, 0xffffffff, 0x00000100,
 431         mmCGTT_SC_CLK_CTRL, 0xffffffff, 0x00000100,
 432         mmCGTT_SPI_CLK_CTRL, 0xffffffff, 0x00000100,
 433         mmCGTT_SQ_CLK_CTRL, 0xffffffff, 0x00000100,
 434         mmCGTT_SQG_CLK_CTRL, 0xffffffff, 0x00000100,
 435         mmCGTT_SX_CLK_CTRL0, 0xffffffff, 0x00000100,
 436         mmCGTT_SX_CLK_CTRL1, 0xffffffff, 0x00000100,
 437         mmCGTT_SX_CLK_CTRL2, 0xffffffff, 0x00000100,
 438         mmCGTT_SX_CLK_CTRL3, 0xffffffff, 0x00000100,
 439         mmCGTT_TCI_CLK_CTRL, 0xffffffff, 0x00000100,
 440         mmCGTT_TCP_CLK_CTRL, 0xffffffff, 0x00000100,
 441         mmCGTT_VGT_CLK_CTRL, 0xffffffff, 0x06000100,
 442         mmDB_CGTT_CLK_CTRL_0, 0xffffffff, 0x00000100,
 443         mmTA_CGTT_CTRL, 0xffffffff, 0x00000100,
 444         mmTCA_CGTT_SCLK_CTRL, 0xffffffff, 0x00000100,
 445         mmTCC_CGTT_SCLK_CTRL, 0xffffffff, 0x00000100,
 446         mmTD_CGTT_CTRL, 0xffffffff, 0x00000100,
 447         mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000,
 448         0x2458, 0xffffffff, 0x00010000,
 449         0x2459, 0xffffffff, 0x00030002,
 450         0x245a, 0xffffffff, 0x00040007,
 451         0x245b, 0xffffffff, 0x00060005,
 452         0x245c, 0xffffffff, 0x00090008,
 453         0x245d, 0xffffffff, 0x00020001,
 454         0x245e, 0xffffffff, 0x00040003,
 455         0x245f, 0xffffffff, 0x00000007,
 456         0x2460, 0xffffffff, 0x00060005,
 457         0x2461, 0xffffffff, 0x00090008,
 458         0x2462, 0xffffffff, 0x00030002,
 459         0x2463, 0xffffffff, 0x00050004,
 460         0x2464, 0xffffffff, 0x00000008,
 461         0x2465, 0xffffffff, 0x00070006,
 462         0x2466, 0xffffffff, 0x000a0009,
 463         0x2467, 0xffffffff, 0x00040003,
 464         0x2468, 0xffffffff, 0x00060005,
 465         0x2469, 0xffffffff, 0x00000009,
 466         0x246a, 0xffffffff, 0x00080007,
 467         0x246b, 0xffffffff, 0x000b000a,
 468         0x246c, 0xffffffff, 0x00050004,
 469         0x246d, 0xffffffff, 0x00070006,
 470         0x246e, 0xffffffff, 0x0008000b,
 471         0x246f, 0xffffffff, 0x000a0009,
 472         0x2470, 0xffffffff, 0x000d000c,
 473         0x2471, 0xffffffff, 0x00060005,
 474         0x2472, 0xffffffff, 0x00080007,
 475         0x2473, 0xffffffff, 0x0000000b,
 476         0x2474, 0xffffffff, 0x000a0009,
 477         0x2475, 0xffffffff, 0x000d000c,
 478         0x2476, 0xffffffff, 0x00070006,
 479         0x2477, 0xffffffff, 0x00090008,
 480         0x2478, 0xffffffff, 0x0000000c,
 481         0x2479, 0xffffffff, 0x000b000a,
 482         0x247a, 0xffffffff, 0x000e000d,
 483         0x247b, 0xffffffff, 0x00080007,
 484         0x247c, 0xffffffff, 0x000a0009,
 485         0x247d, 0xffffffff, 0x0000000d,
 486         0x247e, 0xffffffff, 0x000c000b,
 487         0x247f, 0xffffffff, 0x000f000e,
 488         0x2480, 0xffffffff, 0x00090008,
 489         0x2481, 0xffffffff, 0x000b000a,
 490         0x2482, 0xffffffff, 0x000c000f,
 491         0x2483, 0xffffffff, 0x000e000d,
 492         0x2484, 0xffffffff, 0x00110010,
 493         0x2485, 0xffffffff, 0x000a0009,
 494         0x2486, 0xffffffff, 0x000c000b,
 495         0x2487, 0xffffffff, 0x0000000f,
 496         0x2488, 0xffffffff, 0x000e000d,
 497         0x2489, 0xffffffff, 0x00110010,
 498         0x248a, 0xffffffff, 0x000b000a,
 499         0x248b, 0xffffffff, 0x000d000c,
 500         0x248c, 0xffffffff, 0x00000010,
 501         0x248d, 0xffffffff, 0x000f000e,
 502         0x248e, 0xffffffff, 0x00120011,
 503         0x248f, 0xffffffff, 0x000c000b,
 504         0x2490, 0xffffffff, 0x000e000d,
 505         0x2491, 0xffffffff, 0x00000011,
 506         0x2492, 0xffffffff, 0x0010000f,
 507         0x2493, 0xffffffff, 0x00130012,
 508         0x2494, 0xffffffff, 0x000d000c,
 509         0x2495, 0xffffffff, 0x000f000e,
 510         0x2496, 0xffffffff, 0x00100013,
 511         0x2497, 0xffffffff, 0x00120011,
 512         0x2498, 0xffffffff, 0x00150014,
 513         0x2499, 0xffffffff, 0x000e000d,
 514         0x249a, 0xffffffff, 0x0010000f,
 515         0x249b, 0xffffffff, 0x00000013,
 516         0x249c, 0xffffffff, 0x00120011,
 517         0x249d, 0xffffffff, 0x00150014,
 518         0x249e, 0xffffffff, 0x000f000e,
 519         0x249f, 0xffffffff, 0x00110010,
 520         0x24a0, 0xffffffff, 0x00000014,
 521         0x24a1, 0xffffffff, 0x00130012,
 522         0x24a2, 0xffffffff, 0x00160015,
 523         0x24a3, 0xffffffff, 0x0010000f,
 524         0x24a4, 0xffffffff, 0x00120011,
 525         0x24a5, 0xffffffff, 0x00000015,
 526         0x24a6, 0xffffffff, 0x00140013,
 527         0x24a7, 0xffffffff, 0x00170016,
 528         mmCGTS_SM_CTRL_REG, 0xffffffff, 0x96940200,
 529         mmCP_RB_WPTR_POLL_CNTL, 0xffffffff, 0x00900100,
 530         mmRLC_GCPM_GENERAL_3, 0xffffffff, 0x00000080,
 531         mmRLC_CGCG_CGLS_CTRL, 0xffffffff, 0x0020003f,
 532         0x000c, 0xffffffff, 0x0000001c,
 533         0x000d, 0x000f0000, 0x000f0000,
 534         0x0583, 0xffffffff, 0x00000100,
 535         mmXDMA_CLOCK_GATING_CNTL, 0xffffffff, 0x00000100,
 536         mmXDMA_MEM_POWER_CNTL, 0x00000101, 0x00000000,
 537         mmMC_MEM_POWER_LS, 0xffffffff, 0x00000104,
 538         mmMC_CITF_MISC_WR_CG, 0x000c0000, 0x000c0000,
 539         mmMC_CITF_MISC_RD_CG, 0x000c0000, 0x000c0000,
 540         mmCGTT_DRM_CLK_CTRL0, 0xff000fff, 0x00000100,
 541         0x157a, 0x00000001, 0x00000001,
 542         mmHDP_MEM_POWER_LS, 0x00000001, 0x00000001,
 543         mmHDP_XDP_CGTT_BLK_CTRL, 0xc0000fff, 0x00000104,
 544         mmCP_MEM_SLP_CNTL, 0x00000001, 0x00000001,
 545         0x3430, 0xfffffff0, 0x00000100,
 546         0x3630, 0xfffffff0, 0x00000100,
 547 };
 548 static const u32 pitcairn_mgcg_cgcg_init[] =
 549 {
 550         mmRLC_CGTT_MGCG_OVERRIDE, 0xffffffff, 0xfffffffc,
 551         mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000,
 552         mmCB_CGTT_SCLK_CTRL, 0xffffffff, 0x00000100,
 553         mmCGTT_BCI_CLK_CTRL, 0xffffffff, 0x00000100,
 554         mmCGTT_CP_CLK_CTRL, 0xffffffff, 0x00000100,
 555         mmCGTT_GDS_CLK_CTRL, 0xffffffff, 0x00000100,
 556         mmCGTT_IA_CLK_CTRL, 0xffffffff, 0x06000100,
 557         mmCGTT_PA_CLK_CTRL, 0xffffffff, 0x00000100,
 558         mmCGTT_PC_CLK_CTRL, 0xffffffff, 0x00000100,
 559         mmCGTT_RLC_CLK_CTRL, 0xffffffff, 0x00000100,
 560         mmCGTT_SC_CLK_CTRL, 0xffffffff, 0x00000100,
 561         mmCGTT_SPI_CLK_CTRL, 0xffffffff, 0x00000100,
 562         mmCGTT_SQ_CLK_CTRL, 0xffffffff, 0x00000100,
 563         mmCGTT_SQG_CLK_CTRL, 0xffffffff, 0x00000100,
 564         mmCGTT_SX_CLK_CTRL0, 0xffffffff, 0x00000100,
 565         mmCGTT_SX_CLK_CTRL1, 0xffffffff, 0x00000100,
 566         mmCGTT_SX_CLK_CTRL2, 0xffffffff, 0x00000100,
 567         mmCGTT_SX_CLK_CTRL3, 0xffffffff, 0x00000100,
 568         mmCGTT_TCI_CLK_CTRL, 0xffffffff, 0x00000100,
 569         mmCGTT_TCP_CLK_CTRL, 0xffffffff, 0x00000100,
 570         mmCGTT_VGT_CLK_CTRL, 0xffffffff, 0x06000100,
 571         mmDB_CGTT_CLK_CTRL_0, 0xffffffff, 0x00000100,
 572         mmTA_CGTT_CTRL, 0xffffffff, 0x00000100,
 573         mmTCA_CGTT_SCLK_CTRL, 0xffffffff, 0x00000100,
 574         mmTCC_CGTT_SCLK_CTRL, 0xffffffff, 0x00000100,
 575         mmTD_CGTT_CTRL, 0xffffffff, 0x00000100,
 576         mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000,
 577         0x2458, 0xffffffff, 0x00010000,
 578         0x2459, 0xffffffff, 0x00030002,
 579         0x245a, 0xffffffff, 0x00040007,
 580         0x245b, 0xffffffff, 0x00060005,
 581         0x245c, 0xffffffff, 0x00090008,
 582         0x245d, 0xffffffff, 0x00020001,
 583         0x245e, 0xffffffff, 0x00040003,
 584         0x245f, 0xffffffff, 0x00000007,
 585         0x2460, 0xffffffff, 0x00060005,
 586         0x2461, 0xffffffff, 0x00090008,
 587         0x2462, 0xffffffff, 0x00030002,
 588         0x2463, 0xffffffff, 0x00050004,
 589         0x2464, 0xffffffff, 0x00000008,
 590         0x2465, 0xffffffff, 0x00070006,
 591         0x2466, 0xffffffff, 0x000a0009,
 592         0x2467, 0xffffffff, 0x00040003,
 593         0x2468, 0xffffffff, 0x00060005,
 594         0x2469, 0xffffffff, 0x00000009,
 595         0x246a, 0xffffffff, 0x00080007,
 596         0x246b, 0xffffffff, 0x000b000a,
 597         0x246c, 0xffffffff, 0x00050004,
 598         0x246d, 0xffffffff, 0x00070006,
 599         0x246e, 0xffffffff, 0x0008000b,
 600         0x246f, 0xffffffff, 0x000a0009,
 601         0x2470, 0xffffffff, 0x000d000c,
 602         0x2480, 0xffffffff, 0x00090008,
 603         0x2481, 0xffffffff, 0x000b000a,
 604         0x2482, 0xffffffff, 0x000c000f,
 605         0x2483, 0xffffffff, 0x000e000d,
 606         0x2484, 0xffffffff, 0x00110010,
 607         0x2485, 0xffffffff, 0x000a0009,
 608         0x2486, 0xffffffff, 0x000c000b,
 609         0x2487, 0xffffffff, 0x0000000f,
 610         0x2488, 0xffffffff, 0x000e000d,
 611         0x2489, 0xffffffff, 0x00110010,
 612         0x248a, 0xffffffff, 0x000b000a,
 613         0x248b, 0xffffffff, 0x000d000c,
 614         0x248c, 0xffffffff, 0x00000010,
 615         0x248d, 0xffffffff, 0x000f000e,
 616         0x248e, 0xffffffff, 0x00120011,
 617         0x248f, 0xffffffff, 0x000c000b,
 618         0x2490, 0xffffffff, 0x000e000d,
 619         0x2491, 0xffffffff, 0x00000011,
 620         0x2492, 0xffffffff, 0x0010000f,
 621         0x2493, 0xffffffff, 0x00130012,
 622         0x2494, 0xffffffff, 0x000d000c,
 623         0x2495, 0xffffffff, 0x000f000e,
 624         0x2496, 0xffffffff, 0x00100013,
 625         0x2497, 0xffffffff, 0x00120011,
 626         0x2498, 0xffffffff, 0x00150014,
 627         mmCGTS_SM_CTRL_REG, 0xffffffff, 0x96940200,
 628         mmCP_RB_WPTR_POLL_CNTL, 0xffffffff, 0x00900100,
 629         mmRLC_GCPM_GENERAL_3, 0xffffffff, 0x00000080,
 630         mmRLC_CGCG_CGLS_CTRL, 0xffffffff, 0x0020003f,
 631         0x000c, 0xffffffff, 0x0000001c,
 632         0x000d, 0x000f0000, 0x000f0000,
 633         0x0583, 0xffffffff, 0x00000100,
 634         mmXDMA_CLOCK_GATING_CNTL, 0xffffffff, 0x00000100,
 635         mmXDMA_MEM_POWER_CNTL, 0x00000101, 0x00000000,
 636         mmMC_MEM_POWER_LS, 0xffffffff, 0x00000104,
 637         mmCGTT_DRM_CLK_CTRL0, 0xff000fff, 0x00000100,
 638         0x157a, 0x00000001, 0x00000001,
 639         mmHDP_MEM_POWER_LS, 0x00000001, 0x00000001,
 640         mmHDP_XDP_CGTT_BLK_CTRL, 0xc0000fff, 0x00000104,
 641         mmCP_MEM_SLP_CNTL, 0x00000001, 0x00000001,
 642         0x3430, 0xfffffff0, 0x00000100,
 643         0x3630, 0xfffffff0, 0x00000100,
 644 };
 645
 646 static const u32 verde_mgcg_cgcg_init[] =
 647 {
 648         mmRLC_CGTT_MGCG_OVERRIDE, 0xffffffff, 0xfffffffc,
 649         mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000,
 650         mmCB_CGTT_SCLK_CTRL, 0xffffffff, 0x00000100,
 651         mmCGTT_BCI_CLK_CTRL, 0xffffffff, 0x00000100,
 652         mmCGTT_CP_CLK_CTRL, 0xffffffff, 0x00000100,
 653         mmCGTT_GDS_CLK_CTRL, 0xffffffff, 0x00000100,
 654         mmCGTT_IA_CLK_CTRL, 0xffffffff, 0x06000100,
 655         mmCGTT_PA_CLK_CTRL, 0xffffffff, 0x00000100,
 656         mmCGTT_PC_CLK_CTRL, 0xffffffff, 0x00000100,
 657         mmCGTT_RLC_CLK_CTRL, 0xffffffff, 0x00000100,
 658         mmCGTT_SC_CLK_CTRL, 0xffffffff, 0x00000100,
 659         mmCGTT_SPI_CLK_CTRL, 0xffffffff, 0x00000100,
 660         mmCGTT_SQ_CLK_CTRL, 0xffffffff, 0x00000100,
 661         mmCGTT_SQG_CLK_CTRL, 0xffffffff, 0x00000100,
 662         mmCGTT_SX_CLK_CTRL0, 0xffffffff, 0x00000100,
 663         mmCGTT_SX_CLK_CTRL1, 0xffffffff, 0x00000100,
 664         mmCGTT_SX_CLK_CTRL2, 0xffffffff, 0x00000100,
 665         mmCGTT_SX_CLK_CTRL3, 0xffffffff, 0x00000100,
 666         mmCGTT_TCI_CLK_CTRL, 0xffffffff, 0x00000100,
 667         mmCGTT_TCP_CLK_CTRL, 0xffffffff, 0x00000100,
 668         mmCGTT_VGT_CLK_CTRL, 0xffffffff, 0x06000100,
 669         mmDB_CGTT_CLK_CTRL_0, 0xffffffff, 0x00000100,
 670         mmTA_CGTT_CTRL, 0xffffffff, 0x00000100,
 671         mmTCA_CGTT_SCLK_CTRL, 0xffffffff, 0x00000100,
 672         mmTCC_CGTT_SCLK_CTRL, 0xffffffff, 0x00000100,
 673         mmTD_CGTT_CTRL, 0xffffffff, 0x00000100,
 674         mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000,
 675         0x2458, 0xffffffff, 0x00010000,
 676         0x2459, 0xffffffff, 0x00030002,
 677         0x245a, 0xffffffff, 0x00040007,
 678         0x245b, 0xffffffff, 0x00060005,
 679         0x245c, 0xffffffff, 0x00090008,
 680         0x245d, 0xffffffff, 0x00020001,
 681         0x245e, 0xffffffff, 0x00040003,
 682         0x245f, 0xffffffff, 0x00000007,
 683         0x2460, 0xffffffff, 0x00060005,
 684         0x2461, 0xffffffff, 0x00090008,
 685         0x2462, 0xffffffff, 0x00030002,
 686         0x2463, 0xffffffff, 0x00050004,
 687         0x2464, 0xffffffff, 0x00000008,
 688         0x2465, 0xffffffff, 0x00070006,
 689         0x2466, 0xffffffff, 0x000a0009,
 690         0x2467, 0xffffffff, 0x00040003,
 691         0x2468, 0xffffffff, 0x00060005,
 692         0x2469, 0xffffffff, 0x00000009,
 693         0x246a, 0xffffffff, 0x00080007,
 694         0x246b, 0xffffffff, 0x000b000a,
 695         0x246c, 0xffffffff, 0x00050004,
 696         0x246d, 0xffffffff, 0x00070006,
 697         0x246e, 0xffffffff, 0x0008000b,
 698         0x246f, 0xffffffff, 0x000a0009,
 699         0x2470, 0xffffffff, 0x000d000c,
 700         0x2480, 0xffffffff, 0x00090008,
 701         0x2481, 0xffffffff, 0x000b000a,
 702         0x2482, 0xffffffff, 0x000c000f,
 703         0x2483, 0xffffffff, 0x000e000d,
 704         0x2484, 0xffffffff, 0x00110010,
 705         0x2485, 0xffffffff, 0x000a0009,
 706         0x2486, 0xffffffff, 0x000c000b,
 707         0x2487, 0xffffffff, 0x0000000f,
 708         0x2488, 0xffffffff, 0x000e000d,
 709         0x2489, 0xffffffff, 0x00110010,
 710         0x248a, 0xffffffff, 0x000b000a,
 711         0x248b, 0xffffffff, 0x000d000c,
 712         0x248c, 0xffffffff, 0x00000010,
 713         0x248d, 0xffffffff, 0x000f000e,
 714         0x248e, 0xffffffff, 0x00120011,
 715         0x248f, 0xffffffff, 0x000c000b,
 716         0x2490, 0xffffffff, 0x000e000d,
 717         0x2491, 0xffffffff, 0x00000011,
 718         0x2492, 0xffffffff, 0x0010000f,
 719         0x2493, 0xffffffff, 0x00130012,
 720         0x2494, 0xffffffff, 0x000d000c,
 721         0x2495, 0xffffffff, 0x000f000e,
 722         0x2496, 0xffffffff, 0x00100013,
 723         0x2497, 0xffffffff, 0x00120011,
 724         0x2498, 0xffffffff, 0x00150014,
 725         mmCGTS_SM_CTRL_REG, 0xffffffff, 0x96940200,
 726         mmCP_RB_WPTR_POLL_CNTL, 0xffffffff, 0x00900100,
 727         mmRLC_GCPM_GENERAL_3, 0xffffffff, 0x00000080,
 728         mmRLC_CGCG_CGLS_CTRL, 0xffffffff, 0x0020003f,
 729         0x000c, 0xffffffff, 0x0000001c,
 730         0x000d, 0x000f0000, 0x000f0000,
 731         0x0583, 0xffffffff, 0x00000100,
 732         mmXDMA_CLOCK_GATING_CNTL, 0xffffffff, 0x00000100,
 733         mmXDMA_MEM_POWER_CNTL, 0x00000101, 0x00000000,
 734         mmMC_MEM_POWER_LS, 0xffffffff, 0x00000104,
 735         mmMC_CITF_MISC_WR_CG, 0x000c0000, 0x000c0000,
 736         mmMC_CITF_MISC_RD_CG, 0x000c0000, 0x000c0000,
 737         mmCGTT_DRM_CLK_CTRL0, 0xff000fff, 0x00000100,
 738         0x157a, 0x00000001, 0x00000001,
 739         mmHDP_MEM_POWER_LS, 0x00000001, 0x00000001,
 740         mmHDP_XDP_CGTT_BLK_CTRL, 0xc0000fff, 0x00000104,
 741         mmCP_MEM_SLP_CNTL, 0x00000001, 0x00000001,
 742         0x3430, 0xfffffff0, 0x00000100,
 743         0x3630, 0xfffffff0, 0x00000100,
 744 };
 745
 746 static const u32 oland_mgcg_cgcg_init[] =
 747 {
 748         mmRLC_CGTT_MGCG_OVERRIDE, 0xffffffff, 0xfffffffc,
 749         mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000,
 750         mmCB_CGTT_SCLK_CTRL, 0xffffffff, 0x00000100,
 751         mmCGTT_BCI_CLK_CTRL, 0xffffffff, 0x00000100,
 752         mmCGTT_CP_CLK_CTRL, 0xffffffff, 0x00000100,
 753         mmCGTT_GDS_CLK_CTRL, 0xffffffff, 0x00000100,
 754         mmCGTT_IA_CLK_CTRL, 0xffffffff, 0x06000100,
 755         mmCGTT_PA_CLK_CTRL, 0xffffffff, 0x00000100,
 756         mmCGTT_PC_CLK_CTRL, 0xffffffff, 0x00000100,
 757         mmCGTT_RLC_CLK_CTRL, 0xffffffff, 0x00000100,
 758         mmCGTT_SC_CLK_CTRL, 0xffffffff, 0x00000100,
 759         mmCGTT_SPI_CLK_CTRL, 0xffffffff, 0x00000100,
 760         mmCGTT_SQ_CLK_CTRL, 0xffffffff, 0x00000100,
 761         mmCGTT_SQG_CLK_CTRL, 0xffffffff, 0x00000100,
 762         mmCGTT_SX_CLK_CTRL0, 0xffffffff, 0x00000100,
 763         mmCGTT_SX_CLK_CTRL1, 0xffffffff, 0x00000100,
 764         mmCGTT_SX_CLK_CTRL2, 0xffffffff, 0x00000100,
 765         mmCGTT_SX_CLK_CTRL3, 0xffffffff, 0x00000100,
 766         mmCGTT_TCI_CLK_CTRL, 0xffffffff, 0x00000100,
 767         mmCGTT_TCP_CLK_CTRL, 0xffffffff, 0x00000100,
 768         mmCGTT_VGT_CLK_CTRL, 0xffffffff, 0x06000100,
 769         mmDB_CGTT_CLK_CTRL_0, 0xffffffff, 0x00000100,
 770         mmTA_CGTT_CTRL, 0xffffffff, 0x00000100,
 771         mmTCA_CGTT_SCLK_CTRL, 0xffffffff, 0x00000100,
 772         mmTCC_CGTT_SCLK_CTRL, 0xffffffff, 0x00000100,
 773         mmTD_CGTT_CTRL, 0xffffffff, 0x00000100,
 774         mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000,
 775         0x2458, 0xffffffff, 0x00010000,
 776         0x2459, 0xffffffff, 0x00030002,
 777         0x245a, 0xffffffff, 0x00040007,
 778         0x245b, 0xffffffff, 0x00060005,
 779         0x245c, 0xffffffff, 0x00090008,
 780         0x245d, 0xffffffff, 0x00020001,
 781         0x245e, 0xffffffff, 0x00040003,
 782         0x245f, 0xffffffff, 0x00000007,
 783         0x2460, 0xffffffff, 0x00060005,
 784         0x2461, 0xffffffff, 0x00090008,
 785         0x2462, 0xffffffff, 0x00030002,
 786         0x2463, 0xffffffff, 0x00050004,
 787         0x2464, 0xffffffff, 0x00000008,
 788         0x2465, 0xffffffff, 0x00070006,
 789         0x2466, 0xffffffff, 0x000a0009,
 790         0x2467, 0xffffffff, 0x00040003,
 791         0x2468, 0xffffffff, 0x00060005,
 792         0x2469, 0xffffffff, 0x00000009,
 793         0x246a, 0xffffffff, 0x00080007,
 794         0x246b, 0xffffffff, 0x000b000a,
 795         0x246c, 0xffffffff, 0x00050004,
 796         0x246d, 0xffffffff, 0x00070006,
 797         0x246e, 0xffffffff, 0x0008000b,
 798         0x246f, 0xffffffff, 0x000a0009,
 799         0x2470, 0xffffffff, 0x000d000c,
 800         0x2471, 0xffffffff, 0x00060005,
 801         0x2472, 0xffffffff, 0x00080007,
 802         0x2473, 0xffffffff, 0x0000000b,
 803         0x2474, 0xffffffff, 0x000a0009,
 804         0x2475, 0xffffffff, 0x000d000c,
 805         mmCGTS_SM_CTRL_REG, 0xffffffff, 0x96940200,
 806         mmCP_RB_WPTR_POLL_CNTL, 0xffffffff, 0x00900100,
 807         mmRLC_GCPM_GENERAL_3, 0xffffffff, 0x00000080,
 808         mmRLC_CGCG_CGLS_CTRL, 0xffffffff, 0x0020003f,
 809         0x000c, 0xffffffff, 0x0000001c,
 810         0x000d, 0x000f0000, 0x000f0000,
 811         0x0583, 0xffffffff, 0x00000100,
 812         mmXDMA_CLOCK_GATING_CNTL, 0xffffffff, 0x00000100,
 813         mmXDMA_MEM_POWER_CNTL, 0x00000101, 0x00000000,
 814         mmMC_MEM_POWER_LS, 0xffffffff, 0x00000104,
 815         mmMC_CITF_MISC_WR_CG, 0x000c0000, 0x000c0000,
 816         mmMC_CITF_MISC_RD_CG, 0x000c0000, 0x000c0000,
 817         mmCGTT_DRM_CLK_CTRL0, 0xff000fff, 0x00000100,
 818         0x157a, 0x00000001, 0x00000001,
 819         mmHDP_MEM_POWER_LS, 0x00000001, 0x00000001,
 820         mmHDP_XDP_CGTT_BLK_CTRL, 0xc0000fff, 0x00000104,
 821         mmCP_MEM_SLP_CNTL, 0x00000001, 0x00000001,
 822         0x3430, 0xfffffff0, 0x00000100,
 823         0x3630, 0xfffffff0, 0x00000100,
 824 };
 825
 826 static const u32 hainan_mgcg_cgcg_init[] =
 827 {
 828         mmRLC_CGTT_MGCG_OVERRIDE, 0xffffffff, 0xfffffffc,
 829         mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000,
 830         mmCB_CGTT_SCLK_CTRL, 0xffffffff, 0x00000100,
 831         mmCGTT_BCI_CLK_CTRL, 0xffffffff, 0x00000100,
 832         mmCGTT_CP_CLK_CTRL, 0xffffffff, 0x00000100,
 833         mmCGTT_GDS_CLK_CTRL, 0xffffffff, 0x00000100,
 834         mmCGTT_IA_CLK_CTRL, 0xffffffff, 0x06000100,
 835         mmCGTT_PA_CLK_CTRL, 0xffffffff, 0x00000100,
 836         mmCGTT_PC_CLK_CTRL, 0xffffffff, 0x00000100,
 837         mmCGTT_RLC_CLK_CTRL, 0xffffffff, 0x00000100,
 838         mmCGTT_SC_CLK_CTRL, 0xffffffff, 0x00000100,
 839         mmCGTT_SPI_CLK_CTRL, 0xffffffff, 0x00000100,
 840         mmCGTT_SQ_CLK_CTRL, 0xffffffff, 0x00000100,
 841         mmCGTT_SQG_CLK_CTRL, 0xffffffff, 0x00000100,
 842         mmCGTT_SX_CLK_CTRL0, 0xffffffff, 0x00000100,
 843         mmCGTT_SX_CLK_CTRL1, 0xffffffff, 0x00000100,
 844         mmCGTT_SX_CLK_CTRL2, 0xffffffff, 0x00000100,
 845         mmCGTT_SX_CLK_CTRL3, 0xffffffff, 0x00000100,
 846         mmCGTT_TCI_CLK_CTRL, 0xffffffff, 0x00000100,
 847         mmCGTT_TCP_CLK_CTRL, 0xffffffff, 0x00000100,
 848         mmCGTT_VGT_CLK_CTRL, 0xffffffff, 0x06000100,
 849         mmDB_CGTT_CLK_CTRL_0, 0xffffffff, 0x00000100,
 850         mmTA_CGTT_CTRL, 0xffffffff, 0x00000100,
 851         mmTCA_CGTT_SCLK_CTRL, 0xffffffff, 0x00000100,
 852         mmTCC_CGTT_SCLK_CTRL, 0xffffffff, 0x00000100,
 853         mmTD_CGTT_CTRL, 0xffffffff, 0x00000100,
 854         mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000,
 855         0x2458, 0xffffffff, 0x00010000,
 856         0x2459, 0xffffffff, 0x00030002,
 857         0x245a, 0xffffffff, 0x00040007,
 858         0x245b, 0xffffffff, 0x00060005,
 859         0x245c, 0xffffffff, 0x00090008,
 860         0x245d, 0xffffffff, 0x00020001,
 861         0x245e, 0xffffffff, 0x00040003,
 862         0x245f, 0xffffffff, 0x00000007,
 863         0x2460, 0xffffffff, 0x00060005,
 864         0x2461, 0xffffffff, 0x00090008,
 865         0x2462, 0xffffffff, 0x00030002,
 866         0x2463, 0xffffffff, 0x00050004,
 867         0x2464, 0xffffffff, 0x00000008,
 868         0x2465, 0xffffffff, 0x00070006,
 869         0x2466, 0xffffffff, 0x000a0009,
 870         0x2467, 0xffffffff, 0x00040003,
 871         0x2468, 0xffffffff, 0x00060005,
 872         0x2469, 0xffffffff, 0x00000009,
 873         0x246a, 0xffffffff, 0x00080007,
 874         0x246b, 0xffffffff, 0x000b000a,
 875         0x246c, 0xffffffff, 0x00050004,
 876         0x246d, 0xffffffff, 0x00070006,
 877         0x246e, 0xffffffff, 0x0008000b,
 878         0x246f, 0xffffffff, 0x000a0009,
 879         0x2470, 0xffffffff, 0x000d000c,
 880         0x2471, 0xffffffff, 0x00060005,
 881         0x2472, 0xffffffff, 0x00080007,
 882         0x2473, 0xffffffff, 0x0000000b,
 883         0x2474, 0xffffffff, 0x000a0009,
 884         0x2475, 0xffffffff, 0x000d000c,
 885         mmCGTS_SM_CTRL_REG, 0xffffffff, 0x96940200,
 886         mmCP_RB_WPTR_POLL_CNTL, 0xffffffff, 0x00900100,
 887         mmRLC_GCPM_GENERAL_3, 0xffffffff, 0x00000080,
 888         mmRLC_CGCG_CGLS_CTRL, 0xffffffff, 0x0020003f,
 889         0x000c, 0xffffffff, 0x0000001c,
 890         0x000d, 0x000f0000, 0x000f0000,
 891         0x0583, 0xffffffff, 0x00000100,
 892         0x0409, 0xffffffff, 0x00000100,
 893         mmMC_MEM_POWER_LS, 0xffffffff, 0x00000104,
 894         mmMC_CITF_MISC_WR_CG, 0x000c0000, 0x000c0000,
 895         mmMC_CITF_MISC_RD_CG, 0x000c0000, 0x000c0000,
 896         mmHDP_MEM_POWER_LS, 0x00000001, 0x00000001,
 897         mmHDP_XDP_CGTT_BLK_CTRL, 0xc0000fff, 0x00000104,
 898         mmCP_MEM_SLP_CNTL, 0x00000001, 0x00000001,
 899         0x3430, 0xfffffff0, 0x00000100,
 900         0x3630, 0xfffffff0, 0x00000100,
 901 };
 902
 903 static u32 si_pcie_rreg(struct amdgpu_device *adev, u32 reg)
 904 {
 905         unsigned long flags;
 906         u32 r;
 907
 908         spin_lock_irqsave(&adev->pcie_idx_lock, flags);
 909         WREG32(AMDGPU_PCIE_INDEX, reg);
 910         (void)RREG32(AMDGPU_PCIE_INDEX);
 911         r = RREG32(AMDGPU_PCIE_DATA);
 912         spin_unlock_irqrestore(&adev->pcie_idx_lock, flags);
 913         return r;
 914 }
 915
 916 static void si_pcie_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
 917 {
 918         unsigned long flags;
 919
 920         spin_lock_irqsave(&adev->pcie_idx_lock, flags);
 921         WREG32(AMDGPU_PCIE_INDEX, reg);
 922         (void)RREG32(AMDGPU_PCIE_INDEX);
 923         WREG32(AMDGPU_PCIE_DATA, v);
 924         (void)RREG32(AMDGPU_PCIE_DATA);
 925         spin_unlock_irqrestore(&adev->pcie_idx_lock, flags);
 926 }
 927
 928 static u32 si_pciep_rreg(struct amdgpu_device *adev, u32 reg)
 929 {
 930         unsigned long flags;
 931         u32 r;
 932
 933         spin_lock_irqsave(&adev->pcie_idx_lock, flags);
 934         WREG32(PCIE_PORT_INDEX, ((reg) & 0xff));
 935         (void)RREG32(PCIE_PORT_INDEX);
 936         r = RREG32(PCIE_PORT_DATA);
 937         spin_unlock_irqrestore(&adev->pcie_idx_lock, flags);
 938         return r;
 939 }
 940
 941 static void si_pciep_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
 942 {
 943         unsigned long flags;
 944
 945         spin_lock_irqsave(&adev->pcie_idx_lock, flags);
 946         WREG32(PCIE_PORT_INDEX, ((reg) & 0xff));
 947         (void)RREG32(PCIE_PORT_INDEX);
 948         WREG32(PCIE_PORT_DATA, (v));
 949         (void)RREG32(PCIE_PORT_DATA);
 950         spin_unlock_irqrestore(&adev->pcie_idx_lock, flags);
 951 }
 952
 953 static u32 si_smc_rreg(struct amdgpu_device *adev, u32 reg)
 954 {
 955         unsigned long flags;
 956         u32 r;
 957
 958         spin_lock_irqsave(&adev->smc_idx_lock, flags);
 959         WREG32(SMC_IND_INDEX_0, (reg));
 960         r = RREG32(SMC_IND_DATA_0);
 961         spin_unlock_irqrestore(&adev->smc_idx_lock, flags);
 962         return r;
 963 }
 964
 965 static void si_smc_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
 966 {
 967         unsigned long flags;
 968
 969         spin_lock_irqsave(&adev->smc_idx_lock, flags);
 970         WREG32(SMC_IND_INDEX_0, (reg));
 971         WREG32(SMC_IND_DATA_0, (v));
 972         spin_unlock_irqrestore(&adev->smc_idx_lock, flags);
 973 }
 974
 975 static struct amdgpu_allowed_register_entry si_allowed_read_registers[] = {
 976         {GRBM_STATUS},
 977         {GB_ADDR_CONFIG},
 978         {MC_ARB_RAMCFG},
 979         {GB_TILE_MODE0},
 980         {GB_TILE_MODE1},
 981         {GB_TILE_MODE2},
 982         {GB_TILE_MODE3},
 983         {GB_TILE_MODE4},
 984         {GB_TILE_MODE5},
 985         {GB_TILE_MODE6},
 986         {GB_TILE_MODE7},
 987         {GB_TILE_MODE8},
 988         {GB_TILE_MODE9},
 989         {GB_TILE_MODE10},
 990         {GB_TILE_MODE11},
 991         {GB_TILE_MODE12},
 992         {GB_TILE_MODE13},
 993         {GB_TILE_MODE14},
 994         {GB_TILE_MODE15},
 995         {GB_TILE_MODE16},
 996         {GB_TILE_MODE17},
 997         {GB_TILE_MODE18},
 998         {GB_TILE_MODE19},
 999         {GB_TILE_MODE20},
1000         {GB_TILE_MODE21},
1001         {GB_TILE_MODE22},
1002         {GB_TILE_MODE23},
1003         {GB_TILE_MODE24},
1004         {GB_TILE_MODE25},
1005         {GB_TILE_MODE26},
1006         {GB_TILE_MODE27},
1007         {GB_TILE_MODE28},
1008         {GB_TILE_MODE29},
1009         {GB_TILE_MODE30},
1010         {GB_TILE_MODE31},
1011         {CC_RB_BACKEND_DISABLE, true},
1012         {GC_USER_RB_BACKEND_DISABLE, true},
1013         {PA_SC_RASTER_CONFIG, true},
1014 };
1015
1016 static uint32_t si_get_register_value(struct amdgpu_device *adev,
1017                                       bool indexed, u32 se_num,
1018                                       u32 sh_num, u32 reg_offset)
1019 {
1020         if (indexed) {
1021                 uint32_t val;
1022                 unsigned se_idx = (se_num == 0xffffffff) ? 0 : se_num;
1023                 unsigned sh_idx = (sh_num == 0xffffffff) ? 0 : sh_num;
1024
1025                 switch (reg_offset) {
1026                 case mmCC_RB_BACKEND_DISABLE:
1027                         return adev->gfx.config.rb_config[se_idx][sh_idx].rb_backend_disable;
1028                 case mmGC_USER_RB_BACKEND_DISABLE:
1029                         return adev->gfx.config.rb_config[se_idx][sh_idx].user_rb_backend_disable;
1030                 case mmPA_SC_RASTER_CONFIG:
1031                         return adev->gfx.config.rb_config[se_idx][sh_idx].raster_config;
1032                 }
1033
1034                 mutex_lock(&adev->grbm_idx_mutex);
1035                 if (se_num != 0xffffffff || sh_num != 0xffffffff)
1036                         amdgpu_gfx_select_se_sh(adev, se_num, sh_num, 0xffffffff);
1037
1038                 val = RREG32(reg_offset);
1039
1040                 if (se_num != 0xffffffff || sh_num != 0xffffffff)
1041                         amdgpu_gfx_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
1042                 mutex_unlock(&adev->grbm_idx_mutex);
1043                 return val;
1044         } else {
1045                 unsigned idx;
1046
1047                 switch (reg_offset) {
1048                 case mmGB_ADDR_CONFIG:
1049                         return adev->gfx.config.gb_addr_config;
1050                 case mmMC_ARB_RAMCFG:
1051                         return adev->gfx.config.mc_arb_ramcfg;
1052                 case mmGB_TILE_MODE0:
1053                 case mmGB_TILE_MODE1:
1054                 case mmGB_TILE_MODE2:
1055                 case mmGB_TILE_MODE3:
1056                 case mmGB_TILE_MODE4:
1057                 case mmGB_TILE_MODE5:
1058                 case mmGB_TILE_MODE6:
1059                 case mmGB_TILE_MODE7:
1060                 case mmGB_TILE_MODE8:
1061                 case mmGB_TILE_MODE9:
1062                 case mmGB_TILE_MODE10:
1063                 case mmGB_TILE_MODE11:
1064                 case mmGB_TILE_MODE12:
1065                 case mmGB_TILE_MODE13:
1066                 case mmGB_TILE_MODE14:
1067                 case mmGB_TILE_MODE15:
1068                 case mmGB_TILE_MODE16:
1069                 case mmGB_TILE_MODE17:
1070                 case mmGB_TILE_MODE18:
1071                 case mmGB_TILE_MODE19:
1072                 case mmGB_TILE_MODE20:
1073                 case mmGB_TILE_MODE21:
1074                 case mmGB_TILE_MODE22:
1075                 case mmGB_TILE_MODE23:
1076                 case mmGB_TILE_MODE24:
1077                 case mmGB_TILE_MODE25:
1078                 case mmGB_TILE_MODE26:
1079                 case mmGB_TILE_MODE27:
1080                 case mmGB_TILE_MODE28:
1081                 case mmGB_TILE_MODE29:
1082                 case mmGB_TILE_MODE30:
1083                 case mmGB_TILE_MODE31:
1084                         idx = (reg_offset - mmGB_TILE_MODE0);
1085                         return adev->gfx.config.tile_mode_array[idx];
1086                 default:
1087                         return RREG32(reg_offset);
1088                 }
1089         }
1090 }
1091 static int si_read_register(struct amdgpu_device *adev, u32 se_num,
1092                              u32 sh_num, u32 reg_offset, u32 *value)
1093 {
1094         uint32_t i;
1095
1096         *value = 0;
1097         for (i = 0; i < ARRAY_SIZE(si_allowed_read_registers); i++) {
1098                 bool indexed = si_allowed_read_registers[i].grbm_indexed;
1099
1100                 if (reg_offset != si_allowed_read_registers[i].reg_offset)
1101                         continue;
1102
1103                 *value = si_get_register_value(adev, indexed, se_num, sh_num,
1104                                                reg_offset);
1105                 return 0;
1106         }
1107         return -EINVAL;
1108 }
1109
1110 static bool si_read_disabled_bios(struct amdgpu_device *adev)
1111 {
1112         u32 bus_cntl;
1113         u32 d1vga_control = 0;
1114         u32 d2vga_control = 0;
1115         u32 vga_render_control = 0;
1116         u32 rom_cntl;
1117         bool r;
1118
1119         bus_cntl = RREG32(R600_BUS_CNTL);
1120         if (adev->mode_info.num_crtc) {
1121                 d1vga_control = RREG32(AVIVO_D1VGA_CONTROL);
1122                 d2vga_control = RREG32(AVIVO_D2VGA_CONTROL);
1123                 vga_render_control = RREG32(VGA_RENDER_CONTROL);
1124         }
1125         rom_cntl = RREG32(R600_ROM_CNTL);
1126
1127         /* enable the rom */
1128         WREG32(R600_BUS_CNTL, (bus_cntl & ~R600_BIOS_ROM_DIS));
1129         if (adev->mode_info.num_crtc) {
1130                 /* Disable VGA mode */
1131                 WREG32(AVIVO_D1VGA_CONTROL,
1132                        (d1vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE |
1133                                           AVIVO_DVGA_CONTROL_TIMING_SELECT)));
1134                 WREG32(AVIVO_D2VGA_CONTROL,
1135                        (d2vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE |
1136                                           AVIVO_DVGA_CONTROL_TIMING_SELECT)));
1137                 WREG32(VGA_RENDER_CONTROL,
1138                        (vga_render_control & C_000300_VGA_VSTATUS_CNTL));
1139         }
1140         WREG32(R600_ROM_CNTL, rom_cntl | R600_SCK_OVERWRITE);
1141
1142         r = amdgpu_read_bios(adev);
1143
1144         /* restore regs */
1145         WREG32(R600_BUS_CNTL, bus_cntl);
1146         if (adev->mode_info.num_crtc) {
1147                 WREG32(AVIVO_D1VGA_CONTROL, d1vga_control);
1148                 WREG32(AVIVO_D2VGA_CONTROL, d2vga_control);
1149                 WREG32(VGA_RENDER_CONTROL, vga_render_control);
1150         }
1151         WREG32(R600_ROM_CNTL, rom_cntl);
1152         return r;
1153 }
1154
1155 #define mmROM_INDEX 0x2A
1156 #define mmROM_DATA  0x2B
1157
1158 static bool si_read_bios_from_rom(struct amdgpu_device *adev,
1159                                   u8 *bios, u32 length_bytes)
1160 {
1161         u32 *dw_ptr;
1162         u32 i, length_dw;
1163
1164         if (bios == NULL)
1165                 return false;
1166         if (length_bytes == 0)
1167                 return false;
1168         /* APU vbios image is part of sbios image */
1169         if (adev->flags & AMD_IS_APU)
1170                 return false;
1171
1172         dw_ptr = (u32 *)bios;
1173         length_dw = ALIGN(length_bytes, 4) / 4;
1174         /* set rom index to 0 */
1175         WREG32(mmROM_INDEX, 0);
1176         for (i = 0; i < length_dw; i++)
1177                 dw_ptr[i] = RREG32(mmROM_DATA);
1178
1179         return true;
1180 }
1181
1182 //xxx: not implemented
1183 static int si_asic_reset(struct amdgpu_device *adev)
1184 {
1185         return 0;
1186 }
1187
1188 static u32 si_get_config_memsize(struct amdgpu_device *adev)
1189 {
1190         return RREG32(mmCONFIG_MEMSIZE);
1191 }
1192
1193 static void si_vga_set_state(struct amdgpu_device *adev, bool state)
1194 {
1195         uint32_t temp;
1196
1197         temp = RREG32(CONFIG_CNTL);
1198         if (state == false) {
1199                 temp &= ~(1<<0);
1200                 temp |= (1<<1);
1201         } else {
1202                 temp &= ~(1<<1);
1203         }
1204         WREG32(CONFIG_CNTL, temp);
1205 }
1206
1207 static u32 si_get_xclk(struct amdgpu_device *adev)
1208 {
1209         u32 reference_clock = adev->clock.spll.reference_freq;
1210         u32 tmp;
1211
1212         tmp = RREG32(CG_CLKPIN_CNTL_2);
1213         if (tmp & MUX_TCLK_TO_XCLK)
1214                 return TCLK;
1215
1216         tmp = RREG32(CG_CLKPIN_CNTL);
1217         if (tmp & XTALIN_DIVIDE)
1218                 return reference_clock / 4;
1219
1220         return reference_clock;
1221 }
1222
1223 //xxx:not implemented
1224 static int si_set_uvd_clocks(struct amdgpu_device *adev, u32 vclk, u32 dclk)
1225 {
1226         return 0;
1227 }
1228
1229 static void si_detect_hw_virtualization(struct amdgpu_device *adev)
1230 {
1231         if (is_virtual_machine()) /* passthrough mode */
1232                 adev->virt.caps |= AMDGPU_PASSTHROUGH_MODE;
1233 }
1234
1235 static void si_flush_hdp(struct amdgpu_device *adev, struct amdgpu_ring *ring)
1236 {
1237         if (!ring || !ring->funcs->emit_wreg) {
1238                 WREG32(mmHDP_MEM_COHERENCY_FLUSH_CNTL, 1);
1239                 RREG32(mmHDP_MEM_COHERENCY_FLUSH_CNTL);
1240         } else {
1241                 amdgpu_ring_emit_wreg(ring, mmHDP_MEM_COHERENCY_FLUSH_CNTL, 1);
1242         }
1243 }
1244
1245 static void si_invalidate_hdp(struct amdgpu_device *adev,
1246                               struct amdgpu_ring *ring)
1247 {
1248         if (!ring || !ring->funcs->emit_wreg) {
1249                 WREG32(mmHDP_DEBUG0, 1);
1250                 RREG32(mmHDP_DEBUG0);
1251         } else {
1252                 amdgpu_ring_emit_wreg(ring, mmHDP_DEBUG0, 1);
1253         }
1254 }
1255
1256 static bool si_need_full_reset(struct amdgpu_device *adev)
1257 {
1258         /* change this when we support soft reset */
1259         return true;
1260 }
1261
1262 static bool si_need_reset_on_init(struct amdgpu_device *adev)
1263 {
1264         return false;
1265 }
1266
1267 static int si_get_pcie_lanes(struct amdgpu_device *adev)
1268 {
1269         u32 link_width_cntl;
1270
1271         if (adev->flags & AMD_IS_APU)
1272                 return 0;
1273
1274         link_width_cntl = RREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL);
1275
1276         switch ((link_width_cntl & LC_LINK_WIDTH_RD_MASK) >> LC_LINK_WIDTH_RD_SHIFT) {
1277         case LC_LINK_WIDTH_X1:
1278                 return 1;
1279         case LC_LINK_WIDTH_X2:
1280                 return 2;
1281         case LC_LINK_WIDTH_X4:
1282                 return 4;
1283         case LC_LINK_WIDTH_X8:
1284                 return 8;
1285         case LC_LINK_WIDTH_X0:
1286         case LC_LINK_WIDTH_X16:
1287         default:
1288                 return 16;
1289         }
1290 }
1291
1292 static void si_set_pcie_lanes(struct amdgpu_device *adev, int lanes)
1293 {
1294         u32 link_width_cntl, mask;
1295
1296         if (adev->flags & AMD_IS_APU)
1297                 return;
1298
1299         switch (lanes) {
1300         case 0:
1301                 mask = LC_LINK_WIDTH_X0;
1302                 break;
1303         case 1:
1304                 mask = LC_LINK_WIDTH_X1;
1305                 break;
1306         case 2:
1307                 mask = LC_LINK_WIDTH_X2;
1308                 break;
1309         case 4:
1310                 mask = LC_LINK_WIDTH_X4;
1311                 break;
1312         case 8:
1313                 mask = LC_LINK_WIDTH_X8;
1314                 break;
1315         case 16:
1316                 mask = LC_LINK_WIDTH_X16;
1317                 break;
1318         default:
1319                 DRM_ERROR("invalid pcie lane request: %d\n", lanes);
1320                 return;
1321         }
1322
1323         link_width_cntl = RREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL);
1324         link_width_cntl &= ~LC_LINK_WIDTH_MASK;
1325         link_width_cntl |= mask << LC_LINK_WIDTH_SHIFT;
1326         link_width_cntl |= (LC_RECONFIG_NOW |
1327                             LC_RECONFIG_ARC_MISSING_ESCAPE);
1328
1329         WREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl);
1330 }
1331
1332 static void si_get_pcie_usage(struct amdgpu_device *adev, uint64_t *count0,
1333                               uint64_t *count1)
1334 {
1335         uint32_t perfctr = 0;
1336         uint64_t cnt0_of, cnt1_of;
1337         int tmp;
1338
1339         /* This reports 0 on APUs, so return to avoid writing/reading registers
1340          * that may or may not be different from their GPU counterparts
1341          */
1342         if (adev->flags & AMD_IS_APU)
1343                 return;
1344
1345         /* Set the 2 events that we wish to watch, defined above */
1346         /* Reg 40 is # received msgs, Reg 104 is # of posted requests sent */
1347         perfctr = REG_SET_FIELD(perfctr, PCIE_PERF_CNTL_TXCLK, EVENT0_SEL, 40);
1348         perfctr = REG_SET_FIELD(perfctr, PCIE_PERF_CNTL_TXCLK, EVENT1_SEL, 104);
1349
1350         /* Write to enable desired perf counters */
1351         WREG32_PCIE(ixPCIE_PERF_CNTL_TXCLK, perfctr);
1352         /* Zero out and enable the perf counters
1353          * Write 0x5:
1354          * Bit 0 = Start all counters(1)
1355          * Bit 2 = Global counter reset enable(1)
1356          */
1357         WREG32_PCIE(ixPCIE_PERF_COUNT_CNTL, 0x00000005);
1358
1359         msleep(1000);
1360
1361         /* Load the shadow and disable the perf counters
1362          * Write 0x2:
1363          * Bit 0 = Stop counters(0)
1364          * Bit 1 = Load the shadow counters(1)
1365          */
1366         WREG32_PCIE(ixPCIE_PERF_COUNT_CNTL, 0x00000002);
1367
1368         /* Read register values to get any >32bit overflow */
1369         tmp = RREG32_PCIE(ixPCIE_PERF_CNTL_TXCLK);
1370         cnt0_of = REG_GET_FIELD(tmp, PCIE_PERF_CNTL_TXCLK, COUNTER0_UPPER);
1371         cnt1_of = REG_GET_FIELD(tmp, PCIE_PERF_CNTL_TXCLK, COUNTER1_UPPER);
1372
1373         /* Get the values and add the overflow */
1374         *count0 = RREG32_PCIE(ixPCIE_PERF_COUNT0_TXCLK) | (cnt0_of << 32);
1375         *count1 = RREG32_PCIE(ixPCIE_PERF_COUNT1_TXCLK) | (cnt1_of << 32);
1376 }
1377
1378 static const struct amdgpu_asic_funcs si_asic_funcs =
1379 {
1380         .read_disabled_bios = &si_read_disabled_bios,
1381         .read_bios_from_rom = &si_read_bios_from_rom,
1382         .read_register = &si_read_register,
1383         .reset = &si_asic_reset,
1384         .set_vga_state = &si_vga_set_state,
1385         .get_xclk = &si_get_xclk,
1386         .set_uvd_clocks = &si_set_uvd_clocks,
1387         .set_vce_clocks = NULL,
1388         .get_pcie_lanes = &si_get_pcie_lanes,
1389         .set_pcie_lanes = &si_set_pcie_lanes,
1390         .get_config_memsize = &si_get_config_memsize,
1391         .flush_hdp = &si_flush_hdp,
1392         .invalidate_hdp = &si_invalidate_hdp,
1393         .need_full_reset = &si_need_full_reset,
1394         .get_pcie_usage = &si_get_pcie_usage,
1395         .need_reset_on_init = &si_need_reset_on_init,
1396 };
1397
1398 static uint32_t si_get_rev_id(struct amdgpu_device *adev)
1399 {
1400         return (RREG32(CC_DRM_ID_STRAPS) & CC_DRM_ID_STRAPS__ATI_REV_ID_MASK)
1401                 >> CC_DRM_ID_STRAPS__ATI_REV_ID__SHIFT;
1402 }
1403
1404 static int si_common_early_init(void *handle)
1405 {
1406         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1407
1408         adev->smc_rreg = &si_smc_rreg;
1409         adev->smc_wreg = &si_smc_wreg;
1410         adev->pcie_rreg = &si_pcie_rreg;
1411         adev->pcie_wreg = &si_pcie_wreg;
1412         adev->pciep_rreg = &si_pciep_rreg;
1413         adev->pciep_wreg = &si_pciep_wreg;
1414         adev->uvd_ctx_rreg = NULL;
1415         adev->uvd_ctx_wreg = NULL;
1416         adev->didt_rreg = NULL;
1417         adev->didt_wreg = NULL;
1418
1419         adev->asic_funcs = &si_asic_funcs;
1420
1421         adev->rev_id = si_get_rev_id(adev);
1422         adev->external_rev_id = 0xFF;
1423         switch (adev->asic_type) {
1424         case CHIP_TAHITI:
1425                 adev->cg_flags =
1426                         AMD_CG_SUPPORT_GFX_MGCG |
1427                         AMD_CG_SUPPORT_GFX_MGLS |
1428                         /*AMD_CG_SUPPORT_GFX_CGCG |*/
1429                         AMD_CG_SUPPORT_GFX_CGLS |
1430                         AMD_CG_SUPPORT_GFX_CGTS |
1431                         AMD_CG_SUPPORT_GFX_CP_LS |
1432                         AMD_CG_SUPPORT_MC_MGCG |
1433                         AMD_CG_SUPPORT_SDMA_MGCG |
1434                         AMD_CG_SUPPORT_BIF_LS |
1435                         AMD_CG_SUPPORT_VCE_MGCG |
1436                         AMD_CG_SUPPORT_UVD_MGCG |
1437                         AMD_CG_SUPPORT_HDP_LS |
1438                         AMD_CG_SUPPORT_HDP_MGCG;
1439                 adev->pg_flags = 0;
1440                 adev->external_rev_id = (adev->rev_id == 0) ? 1 :
1441                                         (adev->rev_id == 1) ? 5 : 6;
1442                 break;
1443         case CHIP_PITCAIRN:
1444                 adev->cg_flags =
1445                         AMD_CG_SUPPORT_GFX_MGCG |
1446                         AMD_CG_SUPPORT_GFX_MGLS |
1447                         /*AMD_CG_SUPPORT_GFX_CGCG |*/
1448                         AMD_CG_SUPPORT_GFX_CGLS |
1449                         AMD_CG_SUPPORT_GFX_CGTS |
1450                         AMD_CG_SUPPORT_GFX_CP_LS |
1451                         AMD_CG_SUPPORT_GFX_RLC_LS |
1452                         AMD_CG_SUPPORT_MC_LS |
1453                         AMD_CG_SUPPORT_MC_MGCG |
1454                         AMD_CG_SUPPORT_SDMA_MGCG |
1455                         AMD_CG_SUPPORT_BIF_LS |
1456                         AMD_CG_SUPPORT_VCE_MGCG |
1457                         AMD_CG_SUPPORT_UVD_MGCG |
1458                         AMD_CG_SUPPORT_HDP_LS |
1459                         AMD_CG_SUPPORT_HDP_MGCG;
1460                 adev->pg_flags = 0;
1461                 adev->external_rev_id = adev->rev_id + 20;
1462                 break;
1463
1464         case CHIP_VERDE:
1465                 adev->cg_flags =
1466                         AMD_CG_SUPPORT_GFX_MGCG |
1467                         AMD_CG_SUPPORT_GFX_MGLS |
1468                         AMD_CG_SUPPORT_GFX_CGLS |
1469                         AMD_CG_SUPPORT_GFX_CGTS |
1470                         AMD_CG_SUPPORT_GFX_CGTS_LS |
1471                         AMD_CG_SUPPORT_GFX_CP_LS |
1472                         AMD_CG_SUPPORT_MC_LS |
1473                         AMD_CG_SUPPORT_MC_MGCG |
1474                         AMD_CG_SUPPORT_SDMA_MGCG |
1475                         AMD_CG_SUPPORT_SDMA_LS |
1476                         AMD_CG_SUPPORT_BIF_LS |
1477                         AMD_CG_SUPPORT_VCE_MGCG |
1478                         AMD_CG_SUPPORT_UVD_MGCG |
1479                         AMD_CG_SUPPORT_HDP_LS |
1480                         AMD_CG_SUPPORT_HDP_MGCG;
1481                 adev->pg_flags = 0;
1482                 //???
1483                 adev->external_rev_id = adev->rev_id + 40;
1484                 break;
1485         case CHIP_OLAND:
1486                 adev->cg_flags =
1487                         AMD_CG_SUPPORT_GFX_MGCG |
1488                         AMD_CG_SUPPORT_GFX_MGLS |
1489                         /*AMD_CG_SUPPORT_GFX_CGCG |*/
1490                         AMD_CG_SUPPORT_GFX_CGLS |
1491                         AMD_CG_SUPPORT_GFX_CGTS |
1492                         AMD_CG_SUPPORT_GFX_CP_LS |
1493                         AMD_CG_SUPPORT_GFX_RLC_LS |
1494                         AMD_CG_SUPPORT_MC_LS |
1495                         AMD_CG_SUPPORT_MC_MGCG |
1496                         AMD_CG_SUPPORT_SDMA_MGCG |
1497                         AMD_CG_SUPPORT_BIF_LS |
1498                         AMD_CG_SUPPORT_UVD_MGCG |
1499                         AMD_CG_SUPPORT_HDP_LS |
1500                         AMD_CG_SUPPORT_HDP_MGCG;
1501                 adev->pg_flags = 0;
1502                 adev->external_rev_id = 60;
1503                 break;
1504         case CHIP_HAINAN:
1505                 adev->cg_flags =
1506                         AMD_CG_SUPPORT_GFX_MGCG |
1507                         AMD_CG_SUPPORT_GFX_MGLS |
1508                         /*AMD_CG_SUPPORT_GFX_CGCG |*/
1509                         AMD_CG_SUPPORT_GFX_CGLS |
1510                         AMD_CG_SUPPORT_GFX_CGTS |
1511                         AMD_CG_SUPPORT_GFX_CP_LS |
1512                         AMD_CG_SUPPORT_GFX_RLC_LS |
1513                         AMD_CG_SUPPORT_MC_LS |
1514                         AMD_CG_SUPPORT_MC_MGCG |
1515                         AMD_CG_SUPPORT_SDMA_MGCG |
1516                         AMD_CG_SUPPORT_BIF_LS |
1517                         AMD_CG_SUPPORT_HDP_LS |
1518                         AMD_CG_SUPPORT_HDP_MGCG;
1519                 adev->pg_flags = 0;
1520                 adev->external_rev_id = 70;
1521                 break;
1522
1523         default:
1524                 return -EINVAL;
1525         }
1526
1527         return 0;
1528 }
1529
1530 static int si_common_sw_init(void *handle)
1531 {
1532         return 0;
1533 }
1534
1535 static int si_common_sw_fini(void *handle)
1536 {
1537         return 0;
1538 }
1539
1540
1541 static void si_init_golden_registers(struct amdgpu_device *adev)
1542 {
1543         switch (adev->asic_type) {
1544         case CHIP_TAHITI:
1545                 amdgpu_device_program_register_sequence(adev,
1546                                                         tahiti_golden_registers,
1547                                                         ARRAY_SIZE(tahiti_golden_registers));
1548                 amdgpu_device_program_register_sequence(adev,
1549                                                         tahiti_golden_rlc_registers,
1550                                                         ARRAY_SIZE(tahiti_golden_rlc_registers));
1551                 amdgpu_device_program_register_sequence(adev,
1552                                                         tahiti_mgcg_cgcg_init,
1553                                                         ARRAY_SIZE(tahiti_mgcg_cgcg_init));
1554                 amdgpu_device_program_register_sequence(adev,
1555                                                         tahiti_golden_registers2,
1556                                                         ARRAY_SIZE(tahiti_golden_registers2));
1557                 break;
1558         case CHIP_PITCAIRN:
1559                 amdgpu_device_program_register_sequence(adev,
1560                                                         pitcairn_golden_registers,
1561                                                         ARRAY_SIZE(pitcairn_golden_registers));
1562                 amdgpu_device_program_register_sequence(adev,
1563                                                         pitcairn_golden_rlc_registers,
1564                                                         ARRAY_SIZE(pitcairn_golden_rlc_registers));
1565                 amdgpu_device_program_register_sequence(adev,
1566                                                         pitcairn_mgcg_cgcg_init,
1567                                                         ARRAY_SIZE(pitcairn_mgcg_cgcg_init));
1568                 break;
1569         case CHIP_VERDE:
1570                 amdgpu_device_program_register_sequence(adev,
1571                                                         verde_golden_registers,
1572                                                         ARRAY_SIZE(verde_golden_registers));
1573                 amdgpu_device_program_register_sequence(adev,
1574                                                         verde_golden_rlc_registers,
1575                                                         ARRAY_SIZE(verde_golden_rlc_registers));
1576                 amdgpu_device_program_register_sequence(adev,
1577                                                         verde_mgcg_cgcg_init,
1578                                                         ARRAY_SIZE(verde_mgcg_cgcg_init));
1579                 amdgpu_device_program_register_sequence(adev,
1580                                                         verde_pg_init,
1581                                                         ARRAY_SIZE(verde_pg_init));
1582                 break;
1583         case CHIP_OLAND:
1584                 amdgpu_device_program_register_sequence(adev,
1585                                                         oland_golden_registers,
1586                                                         ARRAY_SIZE(oland_golden_registers));
1587                 amdgpu_device_program_register_sequence(adev,
1588                                                         oland_golden_rlc_registers,
1589                                                         ARRAY_SIZE(oland_golden_rlc_registers));
1590                 amdgpu_device_program_register_sequence(adev,
1591                                                         oland_mgcg_cgcg_init,
1592                                                         ARRAY_SIZE(oland_mgcg_cgcg_init));
1593                 break;
1594         case CHIP_HAINAN:
1595                 amdgpu_device_program_register_sequence(adev,
1596                                                         hainan_golden_registers,
1597                                                         ARRAY_SIZE(hainan_golden_registers));
1598                 amdgpu_device_program_register_sequence(adev,
1599                                                         hainan_golden_registers2,
1600                                                         ARRAY_SIZE(hainan_golden_registers2));
1601                 amdgpu_device_program_register_sequence(adev,
1602                                                         hainan_mgcg_cgcg_init,
1603                                                         ARRAY_SIZE(hainan_mgcg_cgcg_init));
1604                 break;
1605
1606
1607         default:
1608                 BUG();
1609         }
1610 }
1611
1612 static void si_pcie_gen3_enable(struct amdgpu_device *adev)
1613 {
1614         struct pci_dev *root = adev->pdev->bus->self;
1615         int bridge_pos, gpu_pos;
1616         u32 speed_cntl, current_data_rate;
1617         int i;
1618         u16 tmp16;
1619
1620         if (pci_is_root_bus(adev->pdev->bus))
1621                 return;
1622
1623         if (amdgpu_pcie_gen2 == 0)
1624                 return;
1625
1626         if (adev->flags & AMD_IS_APU)
1627                 return;
1628
1629         if (!(adev->pm.pcie_gen_mask & (CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2 |
1630                                         CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3)))
1631                 return;
1632
1633         speed_cntl = RREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL);
1634         current_data_rate = (speed_cntl & LC_CURRENT_DATA_RATE_MASK) >>
1635                 LC_CURRENT_DATA_RATE_SHIFT;
1636         if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3) {
1637                 if (current_data_rate == 2) {
1638                         DRM_INFO("PCIE gen 3 link speeds already enabled\n");
1639                         return;
1640                 }
1641                 DRM_INFO("enabling PCIE gen 3 link speeds, disable with amdgpu.pcie_gen2=0\n");
1642         } else if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2) {
1643                 if (current_data_rate == 1) {
1644                         DRM_INFO("PCIE gen 2 link speeds already enabled\n");
1645                         return;
1646                 }
1647                 DRM_INFO("enabling PCIE gen 2 link speeds, disable with amdgpu.pcie_gen2=0\n");
1648         }
1649
1650         bridge_pos = pci_pcie_cap(root);
1651         if (!bridge_pos)
1652                 return;
1653
1654         gpu_pos = pci_pcie_cap(adev->pdev);
1655         if (!gpu_pos)
1656                 return;
1657
1658         if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3) {
1659                 if (current_data_rate != 2) {
1660                         u16 bridge_cfg, gpu_cfg;
1661                         u16 bridge_cfg2, gpu_cfg2;
1662                         u32 max_lw, current_lw, tmp;
1663
1664                         pci_read_config_word(root, bridge_pos + PCI_EXP_LNKCTL, &bridge_cfg);
1665                         pci_read_config_word(adev->pdev, gpu_pos + PCI_EXP_LNKCTL, &gpu_cfg);
1666
1667                         tmp16 = bridge_cfg | PCI_EXP_LNKCTL_HAWD;
1668                         pci_write_config_word(root, bridge_pos + PCI_EXP_LNKCTL, tmp16);
1669
1670                         tmp16 = gpu_cfg | PCI_EXP_LNKCTL_HAWD;
1671                         pci_write_config_word(adev->pdev, gpu_pos + PCI_EXP_LNKCTL, tmp16);
1672
1673                         tmp = RREG32_PCIE(PCIE_LC_STATUS1);
1674                         max_lw = (tmp & LC_DETECTED_LINK_WIDTH_MASK) >> LC_DETECTED_LINK_WIDTH_SHIFT;
1675                         current_lw = (tmp & LC_OPERATING_LINK_WIDTH_MASK) >> LC_OPERATING_LINK_WIDTH_SHIFT;
1676
1677                         if (current_lw < max_lw) {
1678                                 tmp = RREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL);
1679                                 if (tmp & LC_RENEGOTIATION_SUPPORT) {
1680                                         tmp &= ~(LC_LINK_WIDTH_MASK | LC_UPCONFIGURE_DIS);
1681                                         tmp |= (max_lw << LC_LINK_WIDTH_SHIFT);
1682                                         tmp |= LC_UPCONFIGURE_SUPPORT | LC_RENEGOTIATE_EN | LC_RECONFIG_NOW;
1683                                         WREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL, tmp);
1684                                 }
1685                         }
1686
1687                         for (i = 0; i < 10; i++) {
1688                                 pci_read_config_word(adev->pdev, gpu_pos + PCI_EXP_DEVSTA, &tmp16);
1689                                 if (tmp16 & PCI_EXP_DEVSTA_TRPND)
1690                                         break;
1691
1692                                 pci_read_config_word(root, bridge_pos + PCI_EXP_LNKCTL, &bridge_cfg);
1693                                 pci_read_config_word(adev->pdev, gpu_pos + PCI_EXP_LNKCTL, &gpu_cfg);
1694
1695                                 pci_read_config_word(root, bridge_pos + PCI_EXP_LNKCTL2, &bridge_cfg2);
1696                                 pci_read_config_word(adev->pdev, gpu_pos + PCI_EXP_LNKCTL2, &gpu_cfg2);
1697
1698                                 tmp = RREG32_PCIE_PORT(PCIE_LC_CNTL4);
1699                                 tmp |= LC_SET_QUIESCE;
1700                                 WREG32_PCIE_PORT(PCIE_LC_CNTL4, tmp);
1701
1702                                 tmp = RREG32_PCIE_PORT(PCIE_LC_CNTL4);
1703                                 tmp |= LC_REDO_EQ;
1704                                 WREG32_PCIE_PORT(PCIE_LC_CNTL4, tmp);
1705
1706                                 mdelay(100);
1707
1708                                 pci_read_config_word(root, bridge_pos + PCI_EXP_LNKCTL, &tmp16);
1709                                 tmp16 &= ~PCI_EXP_LNKCTL_HAWD;
1710                                 tmp16 |= (bridge_cfg & PCI_EXP_LNKCTL_HAWD);
1711                                 pci_write_config_word(root, bridge_pos + PCI_EXP_LNKCTL, tmp16);
1712
1713                                 pci_read_config_word(adev->pdev, gpu_pos + PCI_EXP_LNKCTL, &tmp16);
1714                                 tmp16 &= ~PCI_EXP_LNKCTL_HAWD;
1715                                 tmp16 |= (gpu_cfg & PCI_EXP_LNKCTL_HAWD);
1716                                 pci_write_config_word(adev->pdev, gpu_pos + PCI_EXP_LNKCTL, tmp16);
1717
1718                                 pci_read_config_word(root, bridge_pos + PCI_EXP_LNKCTL2, &tmp16);
1719                                 tmp16 &= ~((1 << 4) | (7 << 9));
1720                                 tmp16 |= (bridge_cfg2 & ((1 << 4) | (7 << 9)));
1721                                 pci_write_config_word(root, bridge_pos + PCI_EXP_LNKCTL2, tmp16);
1722
1723                                 pci_read_config_word(adev->pdev, gpu_pos + PCI_EXP_LNKCTL2, &tmp16);
1724                                 tmp16 &= ~((1 << 4) | (7 << 9));
1725                                 tmp16 |= (gpu_cfg2 & ((1 << 4) | (7 << 9)));
1726                                 pci_write_config_word(adev->pdev, gpu_pos + PCI_EXP_LNKCTL2, tmp16);
1727
1728                                 tmp = RREG32_PCIE_PORT(PCIE_LC_CNTL4);
1729                                 tmp &= ~LC_SET_QUIESCE;
1730                                 WREG32_PCIE_PORT(PCIE_LC_CNTL4, tmp);
1731                         }
1732                 }
1733         }
1734
1735         speed_cntl |= LC_FORCE_EN_SW_SPEED_CHANGE | LC_FORCE_DIS_HW_SPEED_CHANGE;
1736         speed_cntl &= ~LC_FORCE_DIS_SW_SPEED_CHANGE;
1737         WREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL, speed_cntl);
1738
1739         pci_read_config_word(adev->pdev, gpu_pos + PCI_EXP_LNKCTL2, &tmp16);
1740         tmp16 &= ~0xf;
1741         if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3)
1742                 tmp16 |= 3;
1743         else if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2)
1744                 tmp16 |= 2;
1745         else
1746                 tmp16 |= 1;
1747         pci_write_config_word(adev->pdev, gpu_pos + PCI_EXP_LNKCTL2, tmp16);
1748
1749         speed_cntl = RREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL);
1750         speed_cntl |= LC_INITIATE_LINK_SPEED_CHANGE;
1751         WREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL, speed_cntl);
1752
1753         for (i = 0; i < adev->usec_timeout; i++) {
1754                 speed_cntl = RREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL);
1755                 if ((speed_cntl & LC_INITIATE_LINK_SPEED_CHANGE) == 0)
1756                         break;
1757                 udelay(1);
1758         }
1759 }
1760
1761 static inline u32 si_pif_phy0_rreg(struct amdgpu_device *adev, u32 reg)
1762 {
1763         unsigned long flags;
1764         u32 r;
1765
1766         spin_lock_irqsave(&adev->pcie_idx_lock, flags);
1767         WREG32(EVERGREEN_PIF_PHY0_INDEX, ((reg) & 0xffff));
1768         r = RREG32(EVERGREEN_PIF_PHY0_DATA);
1769         spin_unlock_irqrestore(&adev->pcie_idx_lock, flags);
1770         return r;
1771 }
1772
1773 static inline void si_pif_phy0_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
1774 {
1775         unsigned long flags;
1776
1777         spin_lock_irqsave(&adev->pcie_idx_lock, flags);
1778         WREG32(EVERGREEN_PIF_PHY0_INDEX, ((reg) & 0xffff));
1779         WREG32(EVERGREEN_PIF_PHY0_DATA, (v));
1780         spin_unlock_irqrestore(&adev->pcie_idx_lock, flags);
1781 }
1782
1783 static inline u32 si_pif_phy1_rreg(struct amdgpu_device *adev, u32 reg)
1784 {
1785         unsigned long flags;
1786         u32 r;
1787
1788         spin_lock_irqsave(&adev->pcie_idx_lock, flags);
1789         WREG32(EVERGREEN_PIF_PHY1_INDEX, ((reg) & 0xffff));
1790         r = RREG32(EVERGREEN_PIF_PHY1_DATA);
1791         spin_unlock_irqrestore(&adev->pcie_idx_lock, flags);
1792         return r;
1793 }
1794
1795 static inline void si_pif_phy1_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
1796 {
1797         unsigned long flags;
1798
1799         spin_lock_irqsave(&adev->pcie_idx_lock, flags);
1800         WREG32(EVERGREEN_PIF_PHY1_INDEX, ((reg) & 0xffff));
1801         WREG32(EVERGREEN_PIF_PHY1_DATA, (v));
1802         spin_unlock_irqrestore(&adev->pcie_idx_lock, flags);
1803 }
1804 static void si_program_aspm(struct amdgpu_device *adev)
1805 {
1806         u32 data, orig;
1807         bool disable_l0s = false, disable_l1 = false, disable_plloff_in_l1 = false;
1808         bool disable_clkreq = false;
1809
1810         if (amdgpu_aspm == 0)
1811                 return;
1812
1813         if (adev->flags & AMD_IS_APU)
1814                 return;
1815         orig = data = RREG32_PCIE_PORT(PCIE_LC_N_FTS_CNTL);
1816         data &= ~LC_XMIT_N_FTS_MASK;
1817         data |= LC_XMIT_N_FTS(0x24) | LC_XMIT_N_FTS_OVERRIDE_EN;
1818         if (orig != data)
1819                 WREG32_PCIE_PORT(PCIE_LC_N_FTS_CNTL, data);
1820
1821         orig = data = RREG32_PCIE_PORT(PCIE_LC_CNTL3);
1822         data |= LC_GO_TO_RECOVERY;
1823         if (orig != data)
1824                 WREG32_PCIE_PORT(PCIE_LC_CNTL3, data);
1825
1826         orig = data = RREG32_PCIE(PCIE_P_CNTL);
1827         data |= P_IGNORE_EDB_ERR;
1828         if (orig != data)
1829                 WREG32_PCIE(PCIE_P_CNTL, data);
1830
1831         orig = data = RREG32_PCIE_PORT(PCIE_LC_CNTL);
1832         data &= ~(LC_L0S_INACTIVITY_MASK | LC_L1_INACTIVITY_MASK);
1833         data |= LC_PMI_TO_L1_DIS;
1834         if (!disable_l0s)
1835                 data |= LC_L0S_INACTIVITY(7);
1836
1837         if (!disable_l1) {
1838                 data |= LC_L1_INACTIVITY(7);
1839                 data &= ~LC_PMI_TO_L1_DIS;
1840                 if (orig != data)
1841                         WREG32_PCIE_PORT(PCIE_LC_CNTL, data);
1842
1843                 if (!disable_plloff_in_l1) {
1844                         bool clk_req_support;
1845
1846                         orig = data = si_pif_phy0_rreg(adev,PB0_PIF_PWRDOWN_0);
1847                         data &= ~(PLL_POWER_STATE_IN_OFF_0_MASK | PLL_POWER_STATE_IN_TXS2_0_MASK);
1848                         data |= PLL_POWER_STATE_IN_OFF_0(7) | PLL_POWER_STATE_IN_TXS2_0(7);
1849                         if (orig != data)
1850                                 si_pif_phy0_wreg(adev,PB0_PIF_PWRDOWN_0, data);
1851
1852                         orig = data = si_pif_phy0_rreg(adev,PB0_PIF_PWRDOWN_1);
1853                         data &= ~(PLL_POWER_STATE_IN_OFF_1_MASK | PLL_POWER_STATE_IN_TXS2_1_MASK);
1854                         data |= PLL_POWER_STATE_IN_OFF_1(7) | PLL_POWER_STATE_IN_TXS2_1(7);
1855                         if (orig != data)
1856                                 si_pif_phy0_wreg(adev,PB0_PIF_PWRDOWN_1, data);
1857
1858                         orig = data = si_pif_phy1_rreg(adev,PB1_PIF_PWRDOWN_0);
1859                         data &= ~(PLL_POWER_STATE_IN_OFF_0_MASK | PLL_POWER_STATE_IN_TXS2_0_MASK);
1860                         data |= PLL_POWER_STATE_IN_OFF_0(7) | PLL_POWER_STATE_IN_TXS2_0(7);
1861                         if (orig != data)
1862                                 si_pif_phy1_wreg(adev,PB1_PIF_PWRDOWN_0, data);
1863
1864                         orig = data = si_pif_phy1_rreg(adev,PB1_PIF_PWRDOWN_1);
1865                         data &= ~(PLL_POWER_STATE_IN_OFF_1_MASK | PLL_POWER_STATE_IN_TXS2_1_MASK);
1866                         data |= PLL_POWER_STATE_IN_OFF_1(7) | PLL_POWER_STATE_IN_TXS2_1(7);
1867                         if (orig != data)
1868                                 si_pif_phy1_wreg(adev,PB1_PIF_PWRDOWN_1, data);
1869
1870                         if ((adev->family != CHIP_OLAND) && (adev->family != CHIP_HAINAN)) {
1871                                 orig = data = si_pif_phy0_rreg(adev,PB0_PIF_PWRDOWN_0);
1872                                 data &= ~PLL_RAMP_UP_TIME_0_MASK;
1873                                 if (orig != data)
1874                                         si_pif_phy0_wreg(adev,PB0_PIF_PWRDOWN_0, data);
1875
1876                                 orig = data = si_pif_phy0_rreg(adev,PB0_PIF_PWRDOWN_1);
1877                                 data &= ~PLL_RAMP_UP_TIME_1_MASK;
1878                                 if (orig != data)
1879                                         si_pif_phy0_wreg(adev,PB0_PIF_PWRDOWN_1, data);
1880
1881                                 orig = data = si_pif_phy0_rreg(adev,PB0_PIF_PWRDOWN_2);
1882                                 data &= ~PLL_RAMP_UP_TIME_2_MASK;
1883                                 if (orig != data)
1884                                         si_pif_phy0_wreg(adev,PB0_PIF_PWRDOWN_2, data);
1885
1886                                 orig = data = si_pif_phy0_rreg(adev,PB0_PIF_PWRDOWN_3);
1887                                 data &= ~PLL_RAMP_UP_TIME_3_MASK;
1888                                 if (orig != data)
1889                                         si_pif_phy0_wreg(adev,PB0_PIF_PWRDOWN_3, data);
1890
1891                                 orig = data = si_pif_phy1_rreg(adev,PB1_PIF_PWRDOWN_0);
1892                                 data &= ~PLL_RAMP_UP_TIME_0_MASK;
1893                                 if (orig != data)
1894                                         si_pif_phy1_wreg(adev,PB1_PIF_PWRDOWN_0, data);
1895
1896                                 orig = data = si_pif_phy1_rreg(adev,PB1_PIF_PWRDOWN_1);
1897                                 data &= ~PLL_RAMP_UP_TIME_1_MASK;
1898                                 if (orig != data)
1899                                         si_pif_phy1_wreg(adev,PB1_PIF_PWRDOWN_1, data);
1900
1901                                 orig = data = si_pif_phy1_rreg(adev,PB1_PIF_PWRDOWN_2);
1902                                 data &= ~PLL_RAMP_UP_TIME_2_MASK;
1903                                 if (orig != data)
1904                                         si_pif_phy1_wreg(adev,PB1_PIF_PWRDOWN_2, data);
1905
1906                                 orig = data = si_pif_phy1_rreg(adev,PB1_PIF_PWRDOWN_3);
1907                                 data &= ~PLL_RAMP_UP_TIME_3_MASK;
1908                                 if (orig != data)
1909                                         si_pif_phy1_wreg(adev,PB1_PIF_PWRDOWN_3, data);
1910                         }
1911                         orig = data = RREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL);
1912                         data &= ~LC_DYN_LANES_PWR_STATE_MASK;
1913                         data |= LC_DYN_LANES_PWR_STATE(3);
1914                         if (orig != data)
1915                                 WREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL, data);
1916
1917                         orig = data = si_pif_phy0_rreg(adev,PB0_PIF_CNTL);
1918                         data &= ~LS2_EXIT_TIME_MASK;
1919                         if ((adev->family == CHIP_OLAND) || (adev->family == CHIP_HAINAN))
1920                                 data |= LS2_EXIT_TIME(5);
1921                         if (orig != data)
1922                                 si_pif_phy0_wreg(adev,PB0_PIF_CNTL, data);
1923
1924                         orig = data = si_pif_phy1_rreg(adev,PB1_PIF_CNTL);
1925                         data &= ~LS2_EXIT_TIME_MASK;
1926                         if ((adev->family == CHIP_OLAND) || (adev->family == CHIP_HAINAN))
1927                                 data |= LS2_EXIT_TIME(5);
1928                         if (orig != data)
1929                                 si_pif_phy1_wreg(adev,PB1_PIF_CNTL, data);
1930
1931                         if (!disable_clkreq &&
1932                             !pci_is_root_bus(adev->pdev->bus)) {
1933                                 struct pci_dev *root = adev->pdev->bus->self;
1934                                 u32 lnkcap;
1935
1936                                 clk_req_support = false;
1937                                 pcie_capability_read_dword(root, PCI_EXP_LNKCAP, &lnkcap);
1938                                 if (lnkcap & PCI_EXP_LNKCAP_CLKPM)
1939                                         clk_req_support = true;
1940                         } else {
1941                                 clk_req_support = false;
1942                         }
1943
1944                         if (clk_req_support) {
1945                                 orig = data = RREG32_PCIE_PORT(PCIE_LC_CNTL2);
1946                                 data |= LC_ALLOW_PDWN_IN_L1 | LC_ALLOW_PDWN_IN_L23;
1947                                 if (orig != data)
1948                                         WREG32_PCIE_PORT(PCIE_LC_CNTL2, data);
1949
1950                                 orig = data = RREG32(THM_CLK_CNTL);
1951                                 data &= ~(CMON_CLK_SEL_MASK | TMON_CLK_SEL_MASK);
1952                                 data |= CMON_CLK_SEL(1) | TMON_CLK_SEL(1);
1953                                 if (orig != data)
1954                                         WREG32(THM_CLK_CNTL, data);
1955
1956                                 orig = data = RREG32(MISC_CLK_CNTL);
1957                                 data &= ~(DEEP_SLEEP_CLK_SEL_MASK | ZCLK_SEL_MASK);
1958                                 data |= DEEP_SLEEP_CLK_SEL(1) | ZCLK_SEL(1);
1959                                 if (orig != data)
1960                                         WREG32(MISC_CLK_CNTL, data);
1961
1962                                 orig = data = RREG32(CG_CLKPIN_CNTL);
1963                                 data &= ~BCLK_AS_XCLK;
1964                                 if (orig != data)
1965                                         WREG32(CG_CLKPIN_CNTL, data);
1966
1967                                 orig = data = RREG32(CG_CLKPIN_CNTL_2);
1968                                 data &= ~FORCE_BIF_REFCLK_EN;
1969                                 if (orig != data)
1970                                         WREG32(CG_CLKPIN_CNTL_2, data);
1971
1972                                 orig = data = RREG32(MPLL_BYPASSCLK_SEL);
1973                                 data &= ~MPLL_CLKOUT_SEL_MASK;
1974                                 data |= MPLL_CLKOUT_SEL(4);
1975                                 if (orig != data)
1976                                         WREG32(MPLL_BYPASSCLK_SEL, data);
1977
1978                                 orig = data = RREG32(SPLL_CNTL_MODE);
1979                                 data &= ~SPLL_REFCLK_SEL_MASK;
1980                                 if (orig != data)
1981                                         WREG32(SPLL_CNTL_MODE, data);
1982                         }
1983                 }
1984         } else {
1985                 if (orig != data)
1986                         WREG32_PCIE_PORT(PCIE_LC_CNTL, data);
1987         }
1988
1989         orig = data = RREG32_PCIE(PCIE_CNTL2);
1990         data |= SLV_MEM_LS_EN | MST_MEM_LS_EN | REPLAY_MEM_LS_EN;
1991         if (orig != data)
1992                 WREG32_PCIE(PCIE_CNTL2, data);
1993
1994         if (!disable_l0s) {
1995                 data = RREG32_PCIE_PORT(PCIE_LC_N_FTS_CNTL);
1996                 if((data & LC_N_FTS_MASK) == LC_N_FTS_MASK) {
1997                         data = RREG32_PCIE(PCIE_LC_STATUS1);
1998                         if ((data & LC_REVERSE_XMIT) && (data & LC_REVERSE_RCVR)) {
1999                                 orig = data = RREG32_PCIE_PORT(PCIE_LC_CNTL);
2000                                 data &= ~LC_L0S_INACTIVITY_MASK;
2001                                 if (orig != data)
2002                                         WREG32_PCIE_PORT(PCIE_LC_CNTL, data);
2003                         }
2004                 }
2005         }
2006 }
2007
2008 static void si_fix_pci_max_read_req_size(struct amdgpu_device *adev)
2009 {
2010         int readrq;
2011         u16 v;
2012
2013         readrq = pcie_get_readrq(adev->pdev);
2014         v = ffs(readrq) - 8;
2015         if ((v == 0) || (v == 6) || (v == 7))
2016                 pcie_set_readrq(adev->pdev, 512);
2017 }
2018
2019 static int si_common_hw_init(void *handle)
2020 {
2021         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2022
2023         si_fix_pci_max_read_req_size(adev);
2024         si_init_golden_registers(adev);
2025         si_pcie_gen3_enable(adev);
2026         si_program_aspm(adev);
2027
2028         return 0;
2029 }
2030
2031 static int si_common_hw_fini(void *handle)
2032 {
2033         return 0;
2034 }
2035
2036 static int si_common_suspend(void *handle)
2037 {
2038         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2039
2040         return si_common_hw_fini(adev);
2041 }
2042
2043 static int si_common_resume(void *handle)
2044 {
2045         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2046
2047         return si_common_hw_init(adev);
2048 }
2049
2050 static bool si_common_is_idle(void *handle)
2051 {
2052         return true;
2053 }
2054
2055 static int si_common_wait_for_idle(void *handle)
2056 {
2057         return 0;
2058 }
2059
2060 static int si_common_soft_reset(void *handle)
2061 {
2062         return 0;
2063 }
2064
2065 static int si_common_set_clockgating_state(void *handle,
2066                                             enum amd_clockgating_state state)
2067 {
2068         return 0;
2069 }
2070
2071 static int si_common_set_powergating_state(void *handle,
2072                                             enum amd_powergating_state state)
2073 {
2074         return 0;
2075 }
2076
2077 static const struct amd_ip_funcs si_common_ip_funcs = {
2078         .name = "si_common",
2079         .early_init = si_common_early_init,
2080         .late_init = NULL,
2081         .sw_init = si_common_sw_init,
2082         .sw_fini = si_common_sw_fini,
2083         .hw_init = si_common_hw_init,
2084         .hw_fini = si_common_hw_fini,
2085         .suspend = si_common_suspend,
2086         .resume = si_common_resume,
2087         .is_idle = si_common_is_idle,
2088         .wait_for_idle = si_common_wait_for_idle,
2089         .soft_reset = si_common_soft_reset,
2090         .set_clockgating_state = si_common_set_clockgating_state,
2091         .set_powergating_state = si_common_set_powergating_state,
2092 };
2093
2094 static const struct amdgpu_ip_block_version si_common_ip_block =
2095 {
2096         .type = AMD_IP_BLOCK_TYPE_COMMON,
2097         .major = 1,
2098         .minor = 0,
2099         .rev = 0,
2100         .funcs = &si_common_ip_funcs,
2101 };
2102
2103 int si_set_ip_blocks(struct amdgpu_device *adev)
2104 {
2105         si_detect_hw_virtualization(adev);
2106
2107         switch (adev->asic_type) {
2108         case CHIP_VERDE:
2109         case CHIP_TAHITI:
2110         case CHIP_PITCAIRN:
2111                 amdgpu_device_ip_block_add(adev, &si_common_ip_block);
2112                 amdgpu_device_ip_block_add(adev, &gmc_v6_0_ip_block);
2113                 amdgpu_device_ip_block_add(adev, &si_ih_ip_block);
2114                 amdgpu_device_ip_block_add(adev, &gfx_v6_0_ip_block);
2115                 amdgpu_device_ip_block_add(adev, &si_dma_ip_block);
2116                 amdgpu_device_ip_block_add(adev, &si_smu_ip_block);
2117                 if (adev->enable_virtual_display)
2118                         amdgpu_device_ip_block_add(adev, &dce_virtual_ip_block);
2119                 else
2120                         amdgpu_device_ip_block_add(adev, &dce_v6_0_ip_block);
2121                 /* amdgpu_device_ip_block_add(adev, &uvd_v3_1_ip_block); */
2122                 /* amdgpu_device_ip_block_add(adev, &vce_v1_0_ip_block); */
2123                 break;
2124         case CHIP_OLAND:
2125                 amdgpu_device_ip_block_add(adev, &si_common_ip_block);
2126                 amdgpu_device_ip_block_add(adev, &gmc_v6_0_ip_block);
2127                 amdgpu_device_ip_block_add(adev, &si_ih_ip_block);
2128                 amdgpu_device_ip_block_add(adev, &gfx_v6_0_ip_block);
2129                 amdgpu_device_ip_block_add(adev, &si_dma_ip_block);
2130                 amdgpu_device_ip_block_add(adev, &si_smu_ip_block);
2131                 if (adev->enable_virtual_display)
2132                         amdgpu_device_ip_block_add(adev, &dce_virtual_ip_block);
2133                 else
2134                         amdgpu_device_ip_block_add(adev, &dce_v6_4_ip_block);
2135
2136                 /* amdgpu_device_ip_block_add(adev, &uvd_v3_1_ip_block); */
2137                 /* amdgpu_device_ip_block_add(adev, &vce_v1_0_ip_block); */
2138                 break;
2139         case CHIP_HAINAN:
2140                 amdgpu_device_ip_block_add(adev, &si_common_ip_block);
2141                 amdgpu_device_ip_block_add(adev, &gmc_v6_0_ip_block);
2142                 amdgpu_device_ip_block_add(adev, &si_ih_ip_block);
2143                 amdgpu_device_ip_block_add(adev, &gfx_v6_0_ip_block);
2144                 amdgpu_device_ip_block_add(adev, &si_dma_ip_block);
2145                 amdgpu_device_ip_block_add(adev, &si_smu_ip_block);
2146                 if (adev->enable_virtual_display)
2147                         amdgpu_device_ip_block_add(adev, &dce_virtual_ip_block);
2148                 break;
2149         default:
2150                 BUG();
2151         }
2152         return 0;
2153 }
2154