drivers/gpu/drm/amd/amdgpu/si.c

   1 /*
   2  * Copyright 2015 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23
  24 #include <linux/firmware.h>
  25 #include <linux/slab.h>
  26 #include <linux/module.h>
  27 #include "drmP.h"
  28 #include "amdgpu.h"
  29 #include "amdgpu_atombios.h"
  30 #include "amdgpu_ih.h"
  31 #include "amdgpu_uvd.h"
  32 #include "amdgpu_vce.h"
  33 #include "atom.h"
  34 #include "amdgpu_powerplay.h"
  35 #include "si/sid.h"
  36 #include "si_ih.h"
  37 #include "gfx_v6_0.h"
  38 #include "gmc_v6_0.h"
  39 #include "si_dma.h"
  40 #include "dce_v6_0.h"
  41 #include "si.h"
  42 #include "dce_virtual.h"
  43
  44 static const u32 tahiti_golden_registers[] =
  45 {
  46         0x17bc, 0x00000030, 0x00000011,
  47         0x2684, 0x00010000, 0x00018208,
  48         0x260c, 0xffffffff, 0x00000000,
  49         0x260d, 0xf00fffff, 0x00000400,
  50         0x260e, 0x0002021c, 0x00020200,
  51         0x031e, 0x00000080, 0x00000000,
  52         0x340c, 0x000000c0, 0x00800040,
  53         0x360c, 0x000000c0, 0x00800040,
  54         0x16ec, 0x000000f0, 0x00000070,
  55         0x16f0, 0x00200000, 0x50100000,
  56         0x1c0c, 0x31000311, 0x00000011,
  57         0x09df, 0x00000003, 0x000007ff,
  58         0x0903, 0x000007ff, 0x00000000,
  59         0x2285, 0xf000001f, 0x00000007,
  60         0x22c9, 0xffffffff, 0x00ffffff,
  61         0x22c4, 0x0000ff0f, 0x00000000,
  62         0xa293, 0x07ffffff, 0x4e000000,
  63         0xa0d4, 0x3f3f3fff, 0x2a00126a,
  64         0x000c, 0xffffffff, 0x0040,
  65         0x000d, 0x00000040, 0x00004040,
  66         0x2440, 0x07ffffff, 0x03000000,
  67         0x23a2, 0x01ff1f3f, 0x00000000,
  68         0x23a1, 0x01ff1f3f, 0x00000000,
  69         0x2418, 0x0000007f, 0x00000020,
  70         0x2542, 0x00010000, 0x00010000,
  71         0x2b05, 0x00000200, 0x000002fb,
  72         0x2b04, 0xffffffff, 0x0000543b,
  73         0x2b03, 0xffffffff, 0xa9210876,
  74         0x2234, 0xffffffff, 0x000fff40,
  75         0x2235, 0x0000001f, 0x00000010,
  76         0x0504, 0x20000000, 0x20fffed8,
  77         0x0570, 0x000c0fc0, 0x000c0400,
  78         0x052c, 0x0fffffff, 0xffffffff,
  79         0x052d, 0x0fffffff, 0x0fffffff,
  80         0x052e, 0x0fffffff, 0x0fffffff,
  81         0x052f, 0x0fffffff, 0x0fffffff
  82 };
  83
  84 static const u32 tahiti_golden_registers2[] =
  85 {
  86         0x0319, 0x00000001, 0x00000001
  87 };
  88
  89 static const u32 tahiti_golden_rlc_registers[] =
  90 {
  91         0x263e, 0xffffffff, 0x12011003,
  92         0x3109, 0xffffffff, 0x00601005,
  93         0x311f, 0xffffffff, 0x10104040,
  94         0x3122, 0xffffffff, 0x0100000a,
  95         0x30c5, 0xffffffff, 0x00000800,
  96         0x30c3, 0xffffffff, 0x800000f4,
  97         0x3d2a, 0x00000008, 0x00000000
  98 };
  99
 100 static const u32 pitcairn_golden_registers[] =
 101 {
 102         0x2684, 0x00010000, 0x00018208,
 103         0x260c, 0xffffffff, 0x00000000,
 104         0x260d, 0xf00fffff, 0x00000400,
 105         0x260e, 0x0002021c, 0x00020200,
 106         0x031e, 0x00000080, 0x00000000,
 107         0x340c, 0x000300c0, 0x00800040,
 108         0x360c, 0x000300c0, 0x00800040,
 109         0x16ec, 0x000000f0, 0x00000070,
 110         0x16f0, 0x00200000, 0x50100000,
 111         0x1c0c, 0x31000311, 0x00000011,
 112         0x0ab9, 0x00073ffe, 0x000022a2,
 113         0x0903, 0x000007ff, 0x00000000,
 114         0x2285, 0xf000001f, 0x00000007,
 115         0x22c9, 0xffffffff, 0x00ffffff,
 116         0x22c4, 0x0000ff0f, 0x00000000,
 117         0xa293, 0x07ffffff, 0x4e000000,
 118         0xa0d4, 0x3f3f3fff, 0x2a00126a,
 119         0x000c, 0x000000ff, 0x0040,
 120         0x000d, 0x00000040, 0x00004040,
 121         0x2440, 0x07ffffff, 0x03000000,
 122         0x2418, 0x0000007f, 0x00000020,
 123         0x2542, 0x00010000, 0x00010000,
 124         0x2b05, 0x000003ff, 0x000000f7,
 125         0x2b04, 0xffffffff, 0x00000000,
 126         0x2b03, 0xffffffff, 0x32761054,
 127         0x2235, 0x0000001f, 0x00000010,
 128         0x0570, 0x000c0fc0, 0x000c0400
 129 };
 130
 131 static const u32 pitcairn_golden_rlc_registers[] =
 132 {
 133         0x3109, 0xffffffff, 0x00601004,
 134         0x311f, 0xffffffff, 0x10102020,
 135         0x3122, 0xffffffff, 0x01000020,
 136         0x30c5, 0xffffffff, 0x00000800,
 137         0x30c3, 0xffffffff, 0x800000a4
 138 };
 139
 140 static const u32 verde_pg_init[] =
 141 {
 142         0xd4f, 0xffffffff, 0x40000,
 143         0xd4e, 0xffffffff, 0x200010ff,
 144         0xd4f, 0xffffffff, 0x0,
 145         0xd4f, 0xffffffff, 0x0,
 146         0xd4f, 0xffffffff, 0x0,
 147         0xd4f, 0xffffffff, 0x0,
 148         0xd4f, 0xffffffff, 0x0,
 149         0xd4f, 0xffffffff, 0x7007,
 150         0xd4e, 0xffffffff, 0x300010ff,
 151         0xd4f, 0xffffffff, 0x0,
 152         0xd4f, 0xffffffff, 0x0,
 153         0xd4f, 0xffffffff, 0x0,
 154         0xd4f, 0xffffffff, 0x0,
 155         0xd4f, 0xffffffff, 0x0,
 156         0xd4f, 0xffffffff, 0x400000,
 157         0xd4e, 0xffffffff, 0x100010ff,
 158         0xd4f, 0xffffffff, 0x0,
 159         0xd4f, 0xffffffff, 0x0,
 160         0xd4f, 0xffffffff, 0x0,
 161         0xd4f, 0xffffffff, 0x0,
 162         0xd4f, 0xffffffff, 0x0,
 163         0xd4f, 0xffffffff, 0x120200,
 164         0xd4e, 0xffffffff, 0x500010ff,
 165         0xd4f, 0xffffffff, 0x0,
 166         0xd4f, 0xffffffff, 0x0,
 167         0xd4f, 0xffffffff, 0x0,
 168         0xd4f, 0xffffffff, 0x0,
 169         0xd4f, 0xffffffff, 0x0,
 170         0xd4f, 0xffffffff, 0x1e1e16,
 171         0xd4e, 0xffffffff, 0x600010ff,
 172         0xd4f, 0xffffffff, 0x0,
 173         0xd4f, 0xffffffff, 0x0,
 174         0xd4f, 0xffffffff, 0x0,
 175         0xd4f, 0xffffffff, 0x0,
 176         0xd4f, 0xffffffff, 0x0,
 177         0xd4f, 0xffffffff, 0x171f1e,
 178         0xd4e, 0xffffffff, 0x700010ff,
 179         0xd4f, 0xffffffff, 0x0,
 180         0xd4f, 0xffffffff, 0x0,
 181         0xd4f, 0xffffffff, 0x0,
 182         0xd4f, 0xffffffff, 0x0,
 183         0xd4f, 0xffffffff, 0x0,
 184         0xd4f, 0xffffffff, 0x0,
 185         0xd4e, 0xffffffff, 0x9ff,
 186         0xd40, 0xffffffff, 0x0,
 187         0xd41, 0xffffffff, 0x10000800,
 188         0xd41, 0xffffffff, 0xf,
 189         0xd41, 0xffffffff, 0xf,
 190         0xd40, 0xffffffff, 0x4,
 191         0xd41, 0xffffffff, 0x1000051e,
 192         0xd41, 0xffffffff, 0xffff,
 193         0xd41, 0xffffffff, 0xffff,
 194         0xd40, 0xffffffff, 0x8,
 195         0xd41, 0xffffffff, 0x80500,
 196         0xd40, 0xffffffff, 0x12,
 197         0xd41, 0xffffffff, 0x9050c,
 198         0xd40, 0xffffffff, 0x1d,
 199         0xd41, 0xffffffff, 0xb052c,
 200         0xd40, 0xffffffff, 0x2a,
 201         0xd41, 0xffffffff, 0x1053e,
 202         0xd40, 0xffffffff, 0x2d,
 203         0xd41, 0xffffffff, 0x10546,
 204         0xd40, 0xffffffff, 0x30,
 205         0xd41, 0xffffffff, 0xa054e,
 206         0xd40, 0xffffffff, 0x3c,
 207         0xd41, 0xffffffff, 0x1055f,
 208         0xd40, 0xffffffff, 0x3f,
 209         0xd41, 0xffffffff, 0x10567,
 210         0xd40, 0xffffffff, 0x42,
 211         0xd41, 0xffffffff, 0x1056f,
 212         0xd40, 0xffffffff, 0x45,
 213         0xd41, 0xffffffff, 0x10572,
 214         0xd40, 0xffffffff, 0x48,
 215         0xd41, 0xffffffff, 0x20575,
 216         0xd40, 0xffffffff, 0x4c,
 217         0xd41, 0xffffffff, 0x190801,
 218         0xd40, 0xffffffff, 0x67,
 219         0xd41, 0xffffffff, 0x1082a,
 220         0xd40, 0xffffffff, 0x6a,
 221         0xd41, 0xffffffff, 0x1b082d,
 222         0xd40, 0xffffffff, 0x87,
 223         0xd41, 0xffffffff, 0x310851,
 224         0xd40, 0xffffffff, 0xba,
 225         0xd41, 0xffffffff, 0x891,
 226         0xd40, 0xffffffff, 0xbc,
 227         0xd41, 0xffffffff, 0x893,
 228         0xd40, 0xffffffff, 0xbe,
 229         0xd41, 0xffffffff, 0x20895,
 230         0xd40, 0xffffffff, 0xc2,
 231         0xd41, 0xffffffff, 0x20899,
 232         0xd40, 0xffffffff, 0xc6,
 233         0xd41, 0xffffffff, 0x2089d,
 234         0xd40, 0xffffffff, 0xca,
 235         0xd41, 0xffffffff, 0x8a1,
 236         0xd40, 0xffffffff, 0xcc,
 237         0xd41, 0xffffffff, 0x8a3,
 238         0xd40, 0xffffffff, 0xce,
 239         0xd41, 0xffffffff, 0x308a5,
 240         0xd40, 0xffffffff, 0xd3,
 241         0xd41, 0xffffffff, 0x6d08cd,
 242         0xd40, 0xffffffff, 0x142,
 243         0xd41, 0xffffffff, 0x2000095a,
 244         0xd41, 0xffffffff, 0x1,
 245         0xd40, 0xffffffff, 0x144,
 246         0xd41, 0xffffffff, 0x301f095b,
 247         0xd40, 0xffffffff, 0x165,
 248         0xd41, 0xffffffff, 0xc094d,
 249         0xd40, 0xffffffff, 0x173,
 250         0xd41, 0xffffffff, 0xf096d,
 251         0xd40, 0xffffffff, 0x184,
 252         0xd41, 0xffffffff, 0x15097f,
 253         0xd40, 0xffffffff, 0x19b,
 254         0xd41, 0xffffffff, 0xc0998,
 255         0xd40, 0xffffffff, 0x1a9,
 256         0xd41, 0xffffffff, 0x409a7,
 257         0xd40, 0xffffffff, 0x1af,
 258         0xd41, 0xffffffff, 0xcdc,
 259         0xd40, 0xffffffff, 0x1b1,
 260         0xd41, 0xffffffff, 0x800,
 261         0xd42, 0xffffffff, 0x6c9b2000,
 262         0xd44, 0xfc00, 0x2000,
 263         0xd51, 0xffffffff, 0xfc0,
 264         0xa35, 0x00000100, 0x100
 265 };
 266
 267 static const u32 verde_golden_rlc_registers[] =
 268 {
 269         0x3109, 0xffffffff, 0x033f1005,
 270         0x311f, 0xffffffff, 0x10808020,
 271         0x3122, 0xffffffff, 0x00800008,
 272         0x30c5, 0xffffffff, 0x00001000,
 273         0x30c3, 0xffffffff, 0x80010014
 274 };
 275
 276 static const u32 verde_golden_registers[] =
 277 {
 278         0x2684, 0x00010000, 0x00018208,
 279         0x260c, 0xffffffff, 0x00000000,
 280         0x260d, 0xf00fffff, 0x00000400,
 281         0x260e, 0x0002021c, 0x00020200,
 282         0x031e, 0x00000080, 0x00000000,
 283         0x340c, 0x000300c0, 0x00800040,
 284         0x340c, 0x000300c0, 0x00800040,
 285         0x360c, 0x000300c0, 0x00800040,
 286         0x360c, 0x000300c0, 0x00800040,
 287         0x16ec, 0x000000f0, 0x00000070,
 288         0x16f0, 0x00200000, 0x50100000,
 289
 290         0x1c0c, 0x31000311, 0x00000011,
 291         0x0ab9, 0x00073ffe, 0x000022a2,
 292         0x0ab9, 0x00073ffe, 0x000022a2,
 293         0x0ab9, 0x00073ffe, 0x000022a2,
 294         0x0903, 0x000007ff, 0x00000000,
 295         0x0903, 0x000007ff, 0x00000000,
 296         0x0903, 0x000007ff, 0x00000000,
 297         0x2285, 0xf000001f, 0x00000007,
 298         0x2285, 0xf000001f, 0x00000007,
 299         0x2285, 0xf000001f, 0x00000007,
 300         0x2285, 0xffffffff, 0x00ffffff,
 301         0x22c4, 0x0000ff0f, 0x00000000,
 302
 303         0xa293, 0x07ffffff, 0x4e000000,
 304         0xa0d4, 0x3f3f3fff, 0x0000124a,
 305         0xa0d4, 0x3f3f3fff, 0x0000124a,
 306         0xa0d4, 0x3f3f3fff, 0x0000124a,
 307         0x000c, 0x000000ff, 0x0040,
 308         0x000d, 0x00000040, 0x00004040,
 309         0x2440, 0x07ffffff, 0x03000000,
 310         0x2440, 0x07ffffff, 0x03000000,
 311         0x23a2, 0x01ff1f3f, 0x00000000,
 312         0x23a3, 0x01ff1f3f, 0x00000000,
 313         0x23a2, 0x01ff1f3f, 0x00000000,
 314         0x23a1, 0x01ff1f3f, 0x00000000,
 315         0x23a1, 0x01ff1f3f, 0x00000000,
 316
 317         0x23a1, 0x01ff1f3f, 0x00000000,
 318         0x2418, 0x0000007f, 0x00000020,
 319         0x2542, 0x00010000, 0x00010000,
 320         0x2b01, 0x000003ff, 0x00000003,
 321         0x2b05, 0x000003ff, 0x00000003,
 322         0x2b05, 0x000003ff, 0x00000003,
 323         0x2b04, 0xffffffff, 0x00000000,
 324         0x2b04, 0xffffffff, 0x00000000,
 325         0x2b04, 0xffffffff, 0x00000000,
 326         0x2b03, 0xffffffff, 0x00001032,
 327         0x2b03, 0xffffffff, 0x00001032,
 328         0x2b03, 0xffffffff, 0x00001032,
 329         0x2235, 0x0000001f, 0x00000010,
 330         0x2235, 0x0000001f, 0x00000010,
 331         0x2235, 0x0000001f, 0x00000010,
 332         0x0570, 0x000c0fc0, 0x000c0400
 333 };
 334
 335 static const u32 oland_golden_registers[] =
 336 {
 337         0x2684, 0x00010000, 0x00018208,
 338         0x260c, 0xffffffff, 0x00000000,
 339         0x260d, 0xf00fffff, 0x00000400,
 340         0x260e, 0x0002021c, 0x00020200,
 341         0x031e, 0x00000080, 0x00000000,
 342         0x340c, 0x000300c0, 0x00800040,
 343         0x360c, 0x000300c0, 0x00800040,
 344         0x16ec, 0x000000f0, 0x00000070,
 345         0x16f9, 0x00200000, 0x50100000,
 346         0x1c0c, 0x31000311, 0x00000011,
 347         0x0ab9, 0x00073ffe, 0x000022a2,
 348         0x0903, 0x000007ff, 0x00000000,
 349         0x2285, 0xf000001f, 0x00000007,
 350         0x22c9, 0xffffffff, 0x00ffffff,
 351         0x22c4, 0x0000ff0f, 0x00000000,
 352         0xa293, 0x07ffffff, 0x4e000000,
 353         0xa0d4, 0x3f3f3fff, 0x00000082,
 354         0x000c, 0x000000ff, 0x0040,
 355         0x000d, 0x00000040, 0x00004040,
 356         0x2440, 0x07ffffff, 0x03000000,
 357         0x2418, 0x0000007f, 0x00000020,
 358         0x2542, 0x00010000, 0x00010000,
 359         0x2b05, 0x000003ff, 0x000000f3,
 360         0x2b04, 0xffffffff, 0x00000000,
 361         0x2b03, 0xffffffff, 0x00003210,
 362         0x2235, 0x0000001f, 0x00000010,
 363         0x0570, 0x000c0fc0, 0x000c0400
 364 };
 365
 366 static const u32 oland_golden_rlc_registers[] =
 367 {
 368         0x3109, 0xffffffff, 0x00601005,
 369         0x311f, 0xffffffff, 0x10104040,
 370         0x3122, 0xffffffff, 0x0100000a,
 371         0x30c5, 0xffffffff, 0x00000800,
 372         0x30c3, 0xffffffff, 0x800000f4
 373 };
 374
 375 static const u32 hainan_golden_registers[] =
 376 {
 377         0x2684, 0x00010000, 0x00018208,
 378         0x260c, 0xffffffff, 0x00000000,
 379         0x260d, 0xf00fffff, 0x00000400,
 380         0x260e, 0x0002021c, 0x00020200,
 381         0x4595, 0xff000fff, 0x00000100,
 382         0x340c, 0x000300c0, 0x00800040,
 383         0x3630, 0xff000fff, 0x00000100,
 384         0x360c, 0x000300c0, 0x00800040,
 385         0x0ab9, 0x00073ffe, 0x000022a2,
 386         0x0903, 0x000007ff, 0x00000000,
 387         0x2285, 0xf000001f, 0x00000007,
 388         0x22c9, 0xffffffff, 0x00ffffff,
 389         0x22c4, 0x0000ff0f, 0x00000000,
 390         0xa393, 0x07ffffff, 0x4e000000,
 391         0xa0d4, 0x3f3f3fff, 0x00000000,
 392         0x000c, 0x000000ff, 0x0040,
 393         0x000d, 0x00000040, 0x00004040,
 394         0x2440, 0x03e00000, 0x03600000,
 395         0x2418, 0x0000007f, 0x00000020,
 396         0x2542, 0x00010000, 0x00010000,
 397         0x2b05, 0x000003ff, 0x000000f1,
 398         0x2b04, 0xffffffff, 0x00000000,
 399         0x2b03, 0xffffffff, 0x00003210,
 400         0x2235, 0x0000001f, 0x00000010,
 401         0x0570, 0x000c0fc0, 0x000c0400
 402 };
 403
 404 static const u32 hainan_golden_registers2[] =
 405 {
 406         0x263e, 0xffffffff, 0x02010001
 407 };
 408
 409 static const u32 tahiti_mgcg_cgcg_init[] =
 410 {
 411         0x3100, 0xffffffff, 0xfffffffc,
 412         0x200b, 0xffffffff, 0xe0000000,
 413         0x2698, 0xffffffff, 0x00000100,
 414         0x24a9, 0xffffffff, 0x00000100,
 415         0x3059, 0xffffffff, 0x00000100,
 416         0x25dd, 0xffffffff, 0x00000100,
 417         0x2261, 0xffffffff, 0x06000100,
 418         0x2286, 0xffffffff, 0x00000100,
 419         0x24a8, 0xffffffff, 0x00000100,
 420         0x30e0, 0xffffffff, 0x00000100,
 421         0x22ca, 0xffffffff, 0x00000100,
 422         0x2451, 0xffffffff, 0x00000100,
 423         0x2362, 0xffffffff, 0x00000100,
 424         0x2363, 0xffffffff, 0x00000100,
 425         0x240c, 0xffffffff, 0x00000100,
 426         0x240d, 0xffffffff, 0x00000100,
 427         0x240e, 0xffffffff, 0x00000100,
 428         0x240f, 0xffffffff, 0x00000100,
 429         0x2b60, 0xffffffff, 0x00000100,
 430         0x2b15, 0xffffffff, 0x00000100,
 431         0x225f, 0xffffffff, 0x06000100,
 432         0x261a, 0xffffffff, 0x00000100,
 433         0x2544, 0xffffffff, 0x00000100,
 434         0x2bc1, 0xffffffff, 0x00000100,
 435         0x2b81, 0xffffffff, 0x00000100,
 436         0x2527, 0xffffffff, 0x00000100,
 437         0x200b, 0xffffffff, 0xe0000000,
 438         0x2458, 0xffffffff, 0x00010000,
 439         0x2459, 0xffffffff, 0x00030002,
 440         0x245a, 0xffffffff, 0x00040007,
 441         0x245b, 0xffffffff, 0x00060005,
 442         0x245c, 0xffffffff, 0x00090008,
 443         0x245d, 0xffffffff, 0x00020001,
 444         0x245e, 0xffffffff, 0x00040003,
 445         0x245f, 0xffffffff, 0x00000007,
 446         0x2460, 0xffffffff, 0x00060005,
 447         0x2461, 0xffffffff, 0x00090008,
 448         0x2462, 0xffffffff, 0x00030002,
 449         0x2463, 0xffffffff, 0x00050004,
 450         0x2464, 0xffffffff, 0x00000008,
 451         0x2465, 0xffffffff, 0x00070006,
 452         0x2466, 0xffffffff, 0x000a0009,
 453         0x2467, 0xffffffff, 0x00040003,
 454         0x2468, 0xffffffff, 0x00060005,
 455         0x2469, 0xffffffff, 0x00000009,
 456         0x246a, 0xffffffff, 0x00080007,
 457         0x246b, 0xffffffff, 0x000b000a,
 458         0x246c, 0xffffffff, 0x00050004,
 459         0x246d, 0xffffffff, 0x00070006,
 460         0x246e, 0xffffffff, 0x0008000b,
 461         0x246f, 0xffffffff, 0x000a0009,
 462         0x2470, 0xffffffff, 0x000d000c,
 463         0x2471, 0xffffffff, 0x00060005,
 464         0x2472, 0xffffffff, 0x00080007,
 465         0x2473, 0xffffffff, 0x0000000b,
 466         0x2474, 0xffffffff, 0x000a0009,
 467         0x2475, 0xffffffff, 0x000d000c,
 468         0x2476, 0xffffffff, 0x00070006,
 469         0x2477, 0xffffffff, 0x00090008,
 470         0x2478, 0xffffffff, 0x0000000c,
 471         0x2479, 0xffffffff, 0x000b000a,
 472         0x247a, 0xffffffff, 0x000e000d,
 473         0x247b, 0xffffffff, 0x00080007,
 474         0x247c, 0xffffffff, 0x000a0009,
 475         0x247d, 0xffffffff, 0x0000000d,
 476         0x247e, 0xffffffff, 0x000c000b,
 477         0x247f, 0xffffffff, 0x000f000e,
 478         0x2480, 0xffffffff, 0x00090008,
 479         0x2481, 0xffffffff, 0x000b000a,
 480         0x2482, 0xffffffff, 0x000c000f,
 481         0x2483, 0xffffffff, 0x000e000d,
 482         0x2484, 0xffffffff, 0x00110010,
 483         0x2485, 0xffffffff, 0x000a0009,
 484         0x2486, 0xffffffff, 0x000c000b,
 485         0x2487, 0xffffffff, 0x0000000f,
 486         0x2488, 0xffffffff, 0x000e000d,
 487         0x2489, 0xffffffff, 0x00110010,
 488         0x248a, 0xffffffff, 0x000b000a,
 489         0x248b, 0xffffffff, 0x000d000c,
 490         0x248c, 0xffffffff, 0x00000010,
 491         0x248d, 0xffffffff, 0x000f000e,
 492         0x248e, 0xffffffff, 0x00120011,
 493         0x248f, 0xffffffff, 0x000c000b,
 494         0x2490, 0xffffffff, 0x000e000d,
 495         0x2491, 0xffffffff, 0x00000011,
 496         0x2492, 0xffffffff, 0x0010000f,
 497         0x2493, 0xffffffff, 0x00130012,
 498         0x2494, 0xffffffff, 0x000d000c,
 499         0x2495, 0xffffffff, 0x000f000e,
 500         0x2496, 0xffffffff, 0x00100013,
 501         0x2497, 0xffffffff, 0x00120011,
 502         0x2498, 0xffffffff, 0x00150014,
 503         0x2499, 0xffffffff, 0x000e000d,
 504         0x249a, 0xffffffff, 0x0010000f,
 505         0x249b, 0xffffffff, 0x00000013,
 506         0x249c, 0xffffffff, 0x00120011,
 507         0x249d, 0xffffffff, 0x00150014,
 508         0x249e, 0xffffffff, 0x000f000e,
 509         0x249f, 0xffffffff, 0x00110010,
 510         0x24a0, 0xffffffff, 0x00000014,
 511         0x24a1, 0xffffffff, 0x00130012,
 512         0x24a2, 0xffffffff, 0x00160015,
 513         0x24a3, 0xffffffff, 0x0010000f,
 514         0x24a4, 0xffffffff, 0x00120011,
 515         0x24a5, 0xffffffff, 0x00000015,
 516         0x24a6, 0xffffffff, 0x00140013,
 517         0x24a7, 0xffffffff, 0x00170016,
 518         0x2454, 0xffffffff, 0x96940200,
 519         0x21c2, 0xffffffff, 0x00900100,
 520         0x311e, 0xffffffff, 0x00000080,
 521         0x3101, 0xffffffff, 0x0020003f,
 522         0x000c, 0xffffffff, 0x0000001c,
 523         0x000d, 0x000f0000, 0x000f0000,
 524         0x0583, 0xffffffff, 0x00000100,
 525         0x0409, 0xffffffff, 0x00000100,
 526         0x040b, 0x00000101, 0x00000000,
 527         0x082a, 0xffffffff, 0x00000104,
 528         0x0993, 0x000c0000, 0x000c0000,
 529         0x0992, 0x000c0000, 0x000c0000,
 530         0x1579, 0xff000fff, 0x00000100,
 531         0x157a, 0x00000001, 0x00000001,
 532         0x0bd4, 0x00000001, 0x00000001,
 533         0x0c33, 0xc0000fff, 0x00000104,
 534         0x3079, 0x00000001, 0x00000001,
 535         0x3430, 0xfffffff0, 0x00000100,
 536         0x3630, 0xfffffff0, 0x00000100
 537 };
 538 static const u32 pitcairn_mgcg_cgcg_init[] =
 539 {
 540         0x3100, 0xffffffff, 0xfffffffc,
 541         0x200b, 0xffffffff, 0xe0000000,
 542         0x2698, 0xffffffff, 0x00000100,
 543         0x24a9, 0xffffffff, 0x00000100,
 544         0x3059, 0xffffffff, 0x00000100,
 545         0x25dd, 0xffffffff, 0x00000100,
 546         0x2261, 0xffffffff, 0x06000100,
 547         0x2286, 0xffffffff, 0x00000100,
 548         0x24a8, 0xffffffff, 0x00000100,
 549         0x30e0, 0xffffffff, 0x00000100,
 550         0x22ca, 0xffffffff, 0x00000100,
 551         0x2451, 0xffffffff, 0x00000100,
 552         0x2362, 0xffffffff, 0x00000100,
 553         0x2363, 0xffffffff, 0x00000100,
 554         0x240c, 0xffffffff, 0x00000100,
 555         0x240d, 0xffffffff, 0x00000100,
 556         0x240e, 0xffffffff, 0x00000100,
 557         0x240f, 0xffffffff, 0x00000100,
 558         0x2b60, 0xffffffff, 0x00000100,
 559         0x2b15, 0xffffffff, 0x00000100,
 560         0x225f, 0xffffffff, 0x06000100,
 561         0x261a, 0xffffffff, 0x00000100,
 562         0x2544, 0xffffffff, 0x00000100,
 563         0x2bc1, 0xffffffff, 0x00000100,
 564         0x2b81, 0xffffffff, 0x00000100,
 565         0x2527, 0xffffffff, 0x00000100,
 566         0x200b, 0xffffffff, 0xe0000000,
 567         0x2458, 0xffffffff, 0x00010000,
 568         0x2459, 0xffffffff, 0x00030002,
 569         0x245a, 0xffffffff, 0x00040007,
 570         0x245b, 0xffffffff, 0x00060005,
 571         0x245c, 0xffffffff, 0x00090008,
 572         0x245d, 0xffffffff, 0x00020001,
 573         0x245e, 0xffffffff, 0x00040003,
 574         0x245f, 0xffffffff, 0x00000007,
 575         0x2460, 0xffffffff, 0x00060005,
 576         0x2461, 0xffffffff, 0x00090008,
 577         0x2462, 0xffffffff, 0x00030002,
 578         0x2463, 0xffffffff, 0x00050004,
 579         0x2464, 0xffffffff, 0x00000008,
 580         0x2465, 0xffffffff, 0x00070006,
 581         0x2466, 0xffffffff, 0x000a0009,
 582         0x2467, 0xffffffff, 0x00040003,
 583         0x2468, 0xffffffff, 0x00060005,
 584         0x2469, 0xffffffff, 0x00000009,
 585         0x246a, 0xffffffff, 0x00080007,
 586         0x246b, 0xffffffff, 0x000b000a,
 587         0x246c, 0xffffffff, 0x00050004,
 588         0x246d, 0xffffffff, 0x00070006,
 589         0x246e, 0xffffffff, 0x0008000b,
 590         0x246f, 0xffffffff, 0x000a0009,
 591         0x2470, 0xffffffff, 0x000d000c,
 592         0x2480, 0xffffffff, 0x00090008,
 593         0x2481, 0xffffffff, 0x000b000a,
 594         0x2482, 0xffffffff, 0x000c000f,
 595         0x2483, 0xffffffff, 0x000e000d,
 596         0x2484, 0xffffffff, 0x00110010,
 597         0x2485, 0xffffffff, 0x000a0009,
 598         0x2486, 0xffffffff, 0x000c000b,
 599         0x2487, 0xffffffff, 0x0000000f,
 600         0x2488, 0xffffffff, 0x000e000d,
 601         0x2489, 0xffffffff, 0x00110010,
 602         0x248a, 0xffffffff, 0x000b000a,
 603         0x248b, 0xffffffff, 0x000d000c,
 604         0x248c, 0xffffffff, 0x00000010,
 605         0x248d, 0xffffffff, 0x000f000e,
 606         0x248e, 0xffffffff, 0x00120011,
 607         0x248f, 0xffffffff, 0x000c000b,
 608         0x2490, 0xffffffff, 0x000e000d,
 609         0x2491, 0xffffffff, 0x00000011,
 610         0x2492, 0xffffffff, 0x0010000f,
 611         0x2493, 0xffffffff, 0x00130012,
 612         0x2494, 0xffffffff, 0x000d000c,
 613         0x2495, 0xffffffff, 0x000f000e,
 614         0x2496, 0xffffffff, 0x00100013,
 615         0x2497, 0xffffffff, 0x00120011,
 616         0x2498, 0xffffffff, 0x00150014,
 617         0x2454, 0xffffffff, 0x96940200,
 618         0x21c2, 0xffffffff, 0x00900100,
 619         0x311e, 0xffffffff, 0x00000080,
 620         0x3101, 0xffffffff, 0x0020003f,
 621         0xc, 0xffffffff, 0x0000001c,
 622         0xd, 0x000f0000, 0x000f0000,
 623         0x583, 0xffffffff, 0x00000100,
 624         0x409, 0xffffffff, 0x00000100,
 625         0x40b, 0x00000101, 0x00000000,
 626         0x82a, 0xffffffff, 0x00000104,
 627         0x1579, 0xff000fff, 0x00000100,
 628         0x157a, 0x00000001, 0x00000001,
 629         0xbd4, 0x00000001, 0x00000001,
 630         0xc33, 0xc0000fff, 0x00000104,
 631         0x3079, 0x00000001, 0x00000001,
 632         0x3430, 0xfffffff0, 0x00000100,
 633         0x3630, 0xfffffff0, 0x00000100
 634 };
 635 static const u32 verde_mgcg_cgcg_init[] =
 636 {
 637         0x3100, 0xffffffff, 0xfffffffc,
 638         0x200b, 0xffffffff, 0xe0000000,
 639         0x2698, 0xffffffff, 0x00000100,
 640         0x24a9, 0xffffffff, 0x00000100,
 641         0x3059, 0xffffffff, 0x00000100,
 642         0x25dd, 0xffffffff, 0x00000100,
 643         0x2261, 0xffffffff, 0x06000100,
 644         0x2286, 0xffffffff, 0x00000100,
 645         0x24a8, 0xffffffff, 0x00000100,
 646         0x30e0, 0xffffffff, 0x00000100,
 647         0x22ca, 0xffffffff, 0x00000100,
 648         0x2451, 0xffffffff, 0x00000100,
 649         0x2362, 0xffffffff, 0x00000100,
 650         0x2363, 0xffffffff, 0x00000100,
 651         0x240c, 0xffffffff, 0x00000100,
 652         0x240d, 0xffffffff, 0x00000100,
 653         0x240e, 0xffffffff, 0x00000100,
 654         0x240f, 0xffffffff, 0x00000100,
 655         0x2b60, 0xffffffff, 0x00000100,
 656         0x2b15, 0xffffffff, 0x00000100,
 657         0x225f, 0xffffffff, 0x06000100,
 658         0x261a, 0xffffffff, 0x00000100,
 659         0x2544, 0xffffffff, 0x00000100,
 660         0x2bc1, 0xffffffff, 0x00000100,
 661         0x2b81, 0xffffffff, 0x00000100,
 662         0x2527, 0xffffffff, 0x00000100,
 663         0x200b, 0xffffffff, 0xe0000000,
 664         0x2458, 0xffffffff, 0x00010000,
 665         0x2459, 0xffffffff, 0x00030002,
 666         0x245a, 0xffffffff, 0x00040007,
 667         0x245b, 0xffffffff, 0x00060005,
 668         0x245c, 0xffffffff, 0x00090008,
 669         0x245d, 0xffffffff, 0x00020001,
 670         0x245e, 0xffffffff, 0x00040003,
 671         0x245f, 0xffffffff, 0x00000007,
 672         0x2460, 0xffffffff, 0x00060005,
 673         0x2461, 0xffffffff, 0x00090008,
 674         0x2462, 0xffffffff, 0x00030002,
 675         0x2463, 0xffffffff, 0x00050004,
 676         0x2464, 0xffffffff, 0x00000008,
 677         0x2465, 0xffffffff, 0x00070006,
 678         0x2466, 0xffffffff, 0x000a0009,
 679         0x2467, 0xffffffff, 0x00040003,
 680         0x2468, 0xffffffff, 0x00060005,
 681         0x2469, 0xffffffff, 0x00000009,
 682         0x246a, 0xffffffff, 0x00080007,
 683         0x246b, 0xffffffff, 0x000b000a,
 684         0x246c, 0xffffffff, 0x00050004,
 685         0x246d, 0xffffffff, 0x00070006,
 686         0x246e, 0xffffffff, 0x0008000b,
 687         0x246f, 0xffffffff, 0x000a0009,
 688         0x2470, 0xffffffff, 0x000d000c,
 689         0x2480, 0xffffffff, 0x00090008,
 690         0x2481, 0xffffffff, 0x000b000a,
 691         0x2482, 0xffffffff, 0x000c000f,
 692         0x2483, 0xffffffff, 0x000e000d,
 693         0x2484, 0xffffffff, 0x00110010,
 694         0x2485, 0xffffffff, 0x000a0009,
 695         0x2486, 0xffffffff, 0x000c000b,
 696         0x2487, 0xffffffff, 0x0000000f,
 697         0x2488, 0xffffffff, 0x000e000d,
 698         0x2489, 0xffffffff, 0x00110010,
 699         0x248a, 0xffffffff, 0x000b000a,
 700         0x248b, 0xffffffff, 0x000d000c,
 701         0x248c, 0xffffffff, 0x00000010,
 702         0x248d, 0xffffffff, 0x000f000e,
 703         0x248e, 0xffffffff, 0x00120011,
 704         0x248f, 0xffffffff, 0x000c000b,
 705         0x2490, 0xffffffff, 0x000e000d,
 706         0x2491, 0xffffffff, 0x00000011,
 707         0x2492, 0xffffffff, 0x0010000f,
 708         0x2493, 0xffffffff, 0x00130012,
 709         0x2494, 0xffffffff, 0x000d000c,
 710         0x2495, 0xffffffff, 0x000f000e,
 711         0x2496, 0xffffffff, 0x00100013,
 712         0x2497, 0xffffffff, 0x00120011,
 713         0x2498, 0xffffffff, 0x00150014,
 714         0x2454, 0xffffffff, 0x96940200,
 715         0x21c2, 0xffffffff, 0x00900100,
 716         0x311e, 0xffffffff, 0x00000080,
 717         0x3101, 0xffffffff, 0x0020003f,
 718         0xc, 0xffffffff, 0x0000001c,
 719         0xd, 0x000f0000, 0x000f0000,
 720         0x583, 0xffffffff, 0x00000100,
 721         0x409, 0xffffffff, 0x00000100,
 722         0x40b, 0x00000101, 0x00000000,
 723         0x82a, 0xffffffff, 0x00000104,
 724         0x993, 0x000c0000, 0x000c0000,
 725         0x992, 0x000c0000, 0x000c0000,
 726         0x1579, 0xff000fff, 0x00000100,
 727         0x157a, 0x00000001, 0x00000001,
 728         0xbd4, 0x00000001, 0x00000001,
 729         0xc33, 0xc0000fff, 0x00000104,
 730         0x3079, 0x00000001, 0x00000001,
 731         0x3430, 0xfffffff0, 0x00000100,
 732         0x3630, 0xfffffff0, 0x00000100
 733 };
 734 static const u32 oland_mgcg_cgcg_init[] =
 735 {
 736         0x3100, 0xffffffff, 0xfffffffc,
 737         0x200b, 0xffffffff, 0xe0000000,
 738         0x2698, 0xffffffff, 0x00000100,
 739         0x24a9, 0xffffffff, 0x00000100,
 740         0x3059, 0xffffffff, 0x00000100,
 741         0x25dd, 0xffffffff, 0x00000100,
 742         0x2261, 0xffffffff, 0x06000100,
 743         0x2286, 0xffffffff, 0x00000100,
 744         0x24a8, 0xffffffff, 0x00000100,
 745         0x30e0, 0xffffffff, 0x00000100,
 746         0x22ca, 0xffffffff, 0x00000100,
 747         0x2451, 0xffffffff, 0x00000100,
 748         0x2362, 0xffffffff, 0x00000100,
 749         0x2363, 0xffffffff, 0x00000100,
 750         0x240c, 0xffffffff, 0x00000100,
 751         0x240d, 0xffffffff, 0x00000100,
 752         0x240e, 0xffffffff, 0x00000100,
 753         0x240f, 0xffffffff, 0x00000100,
 754         0x2b60, 0xffffffff, 0x00000100,
 755         0x2b15, 0xffffffff, 0x00000100,
 756         0x225f, 0xffffffff, 0x06000100,
 757         0x261a, 0xffffffff, 0x00000100,
 758         0x2544, 0xffffffff, 0x00000100,
 759         0x2bc1, 0xffffffff, 0x00000100,
 760         0x2b81, 0xffffffff, 0x00000100,
 761         0x2527, 0xffffffff, 0x00000100,
 762         0x200b, 0xffffffff, 0xe0000000,
 763         0x2458, 0xffffffff, 0x00010000,
 764         0x2459, 0xffffffff, 0x00030002,
 765         0x245a, 0xffffffff, 0x00040007,
 766         0x245b, 0xffffffff, 0x00060005,
 767         0x245c, 0xffffffff, 0x00090008,
 768         0x245d, 0xffffffff, 0x00020001,
 769         0x245e, 0xffffffff, 0x00040003,
 770         0x245f, 0xffffffff, 0x00000007,
 771         0x2460, 0xffffffff, 0x00060005,
 772         0x2461, 0xffffffff, 0x00090008,
 773         0x2462, 0xffffffff, 0x00030002,
 774         0x2463, 0xffffffff, 0x00050004,
 775         0x2464, 0xffffffff, 0x00000008,
 776         0x2465, 0xffffffff, 0x00070006,
 777         0x2466, 0xffffffff, 0x000a0009,
 778         0x2467, 0xffffffff, 0x00040003,
 779         0x2468, 0xffffffff, 0x00060005,
 780         0x2469, 0xffffffff, 0x00000009,
 781         0x246a, 0xffffffff, 0x00080007,
 782         0x246b, 0xffffffff, 0x000b000a,
 783         0x246c, 0xffffffff, 0x00050004,
 784         0x246d, 0xffffffff, 0x00070006,
 785         0x246e, 0xffffffff, 0x0008000b,
 786         0x246f, 0xffffffff, 0x000a0009,
 787         0x2470, 0xffffffff, 0x000d000c,
 788         0x2471, 0xffffffff, 0x00060005,
 789         0x2472, 0xffffffff, 0x00080007,
 790         0x2473, 0xffffffff, 0x0000000b,
 791         0x2474, 0xffffffff, 0x000a0009,
 792         0x2475, 0xffffffff, 0x000d000c,
 793         0x2454, 0xffffffff, 0x96940200,
 794         0x21c2, 0xffffffff, 0x00900100,
 795         0x311e, 0xffffffff, 0x00000080,
 796         0x3101, 0xffffffff, 0x0020003f,
 797         0xc, 0xffffffff, 0x0000001c,
 798         0xd, 0x000f0000, 0x000f0000,
 799         0x583, 0xffffffff, 0x00000100,
 800         0x409, 0xffffffff, 0x00000100,
 801         0x40b, 0x00000101, 0x00000000,
 802         0x82a, 0xffffffff, 0x00000104,
 803         0x993, 0x000c0000, 0x000c0000,
 804         0x992, 0x000c0000, 0x000c0000,
 805         0x1579, 0xff000fff, 0x00000100,
 806         0x157a, 0x00000001, 0x00000001,
 807         0xbd4, 0x00000001, 0x00000001,
 808         0xc33, 0xc0000fff, 0x00000104,
 809         0x3079, 0x00000001, 0x00000001,
 810         0x3430, 0xfffffff0, 0x00000100,
 811         0x3630, 0xfffffff0, 0x00000100
 812 };
 813 static const u32 hainan_mgcg_cgcg_init[] =
 814 {
 815         0x3100, 0xffffffff, 0xfffffffc,
 816         0x200b, 0xffffffff, 0xe0000000,
 817         0x2698, 0xffffffff, 0x00000100,
 818         0x24a9, 0xffffffff, 0x00000100,
 819         0x3059, 0xffffffff, 0x00000100,
 820         0x25dd, 0xffffffff, 0x00000100,
 821         0x2261, 0xffffffff, 0x06000100,
 822         0x2286, 0xffffffff, 0x00000100,
 823         0x24a8, 0xffffffff, 0x00000100,
 824         0x30e0, 0xffffffff, 0x00000100,
 825         0x22ca, 0xffffffff, 0x00000100,
 826         0x2451, 0xffffffff, 0x00000100,
 827         0x2362, 0xffffffff, 0x00000100,
 828         0x2363, 0xffffffff, 0x00000100,
 829         0x240c, 0xffffffff, 0x00000100,
 830         0x240d, 0xffffffff, 0x00000100,
 831         0x240e, 0xffffffff, 0x00000100,
 832         0x240f, 0xffffffff, 0x00000100,
 833         0x2b60, 0xffffffff, 0x00000100,
 834         0x2b15, 0xffffffff, 0x00000100,
 835         0x225f, 0xffffffff, 0x06000100,
 836         0x261a, 0xffffffff, 0x00000100,
 837         0x2544, 0xffffffff, 0x00000100,
 838         0x2bc1, 0xffffffff, 0x00000100,
 839         0x2b81, 0xffffffff, 0x00000100,
 840         0x2527, 0xffffffff, 0x00000100,
 841         0x200b, 0xffffffff, 0xe0000000,
 842         0x2458, 0xffffffff, 0x00010000,
 843         0x2459, 0xffffffff, 0x00030002,
 844         0x245a, 0xffffffff, 0x00040007,
 845         0x245b, 0xffffffff, 0x00060005,
 846         0x245c, 0xffffffff, 0x00090008,
 847         0x245d, 0xffffffff, 0x00020001,
 848         0x245e, 0xffffffff, 0x00040003,
 849         0x245f, 0xffffffff, 0x00000007,
 850         0x2460, 0xffffffff, 0x00060005,
 851         0x2461, 0xffffffff, 0x00090008,
 852         0x2462, 0xffffffff, 0x00030002,
 853         0x2463, 0xffffffff, 0x00050004,
 854         0x2464, 0xffffffff, 0x00000008,
 855         0x2465, 0xffffffff, 0x00070006,
 856         0x2466, 0xffffffff, 0x000a0009,
 857         0x2467, 0xffffffff, 0x00040003,
 858         0x2468, 0xffffffff, 0x00060005,
 859         0x2469, 0xffffffff, 0x00000009,
 860         0x246a, 0xffffffff, 0x00080007,
 861         0x246b, 0xffffffff, 0x000b000a,
 862         0x246c, 0xffffffff, 0x00050004,
 863         0x246d, 0xffffffff, 0x00070006,
 864         0x246e, 0xffffffff, 0x0008000b,
 865         0x246f, 0xffffffff, 0x000a0009,
 866         0x2470, 0xffffffff, 0x000d000c,
 867         0x2471, 0xffffffff, 0x00060005,
 868         0x2472, 0xffffffff, 0x00080007,
 869         0x2473, 0xffffffff, 0x0000000b,
 870         0x2474, 0xffffffff, 0x000a0009,
 871         0x2475, 0xffffffff, 0x000d000c,
 872         0x2454, 0xffffffff, 0x96940200,
 873         0x21c2, 0xffffffff, 0x00900100,
 874         0x311e, 0xffffffff, 0x00000080,
 875         0x3101, 0xffffffff, 0x0020003f,
 876         0xc, 0xffffffff, 0x0000001c,
 877         0xd, 0x000f0000, 0x000f0000,
 878         0x583, 0xffffffff, 0x00000100,
 879         0x409, 0xffffffff, 0x00000100,
 880         0x82a, 0xffffffff, 0x00000104,
 881         0x993, 0x000c0000, 0x000c0000,
 882         0x992, 0x000c0000, 0x000c0000,
 883         0xbd4, 0x00000001, 0x00000001,
 884         0xc33, 0xc0000fff, 0x00000104,
 885         0x3079, 0x00000001, 0x00000001,
 886         0x3430, 0xfffffff0, 0x00000100,
 887         0x3630, 0xfffffff0, 0x00000100
 888 };
 889
 890 static u32 si_pcie_rreg(struct amdgpu_device *adev, u32 reg)
 891 {
 892         unsigned long flags;
 893         u32 r;
 894
 895         spin_lock_irqsave(&adev->pcie_idx_lock, flags);
 896         WREG32(AMDGPU_PCIE_INDEX, reg);
 897         (void)RREG32(AMDGPU_PCIE_INDEX);
 898         r = RREG32(AMDGPU_PCIE_DATA);
 899         spin_unlock_irqrestore(&adev->pcie_idx_lock, flags);
 900         return r;
 901 }
 902
 903 static void si_pcie_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
 904 {
 905         unsigned long flags;
 906
 907         spin_lock_irqsave(&adev->pcie_idx_lock, flags);
 908         WREG32(AMDGPU_PCIE_INDEX, reg);
 909         (void)RREG32(AMDGPU_PCIE_INDEX);
 910         WREG32(AMDGPU_PCIE_DATA, v);
 911         (void)RREG32(AMDGPU_PCIE_DATA);
 912         spin_unlock_irqrestore(&adev->pcie_idx_lock, flags);
 913 }
 914
 915 static u32 si_pciep_rreg(struct amdgpu_device *adev, u32 reg)
 916 {
 917         unsigned long flags;
 918         u32 r;
 919
 920         spin_lock_irqsave(&adev->pcie_idx_lock, flags);
 921         WREG32(PCIE_PORT_INDEX, ((reg) & 0xff));
 922         (void)RREG32(PCIE_PORT_INDEX);
 923         r = RREG32(PCIE_PORT_DATA);
 924         spin_unlock_irqrestore(&adev->pcie_idx_lock, flags);
 925         return r;
 926 }
 927
 928 static void si_pciep_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
 929 {
 930         unsigned long flags;
 931
 932         spin_lock_irqsave(&adev->pcie_idx_lock, flags);
 933         WREG32(PCIE_PORT_INDEX, ((reg) & 0xff));
 934         (void)RREG32(PCIE_PORT_INDEX);
 935         WREG32(PCIE_PORT_DATA, (v));
 936         (void)RREG32(PCIE_PORT_DATA);
 937         spin_unlock_irqrestore(&adev->pcie_idx_lock, flags);
 938 }
 939
 940 static u32 si_smc_rreg(struct amdgpu_device *adev, u32 reg)
 941 {
 942         unsigned long flags;
 943         u32 r;
 944
 945         spin_lock_irqsave(&adev->smc_idx_lock, flags);
 946         WREG32(SMC_IND_INDEX_0, (reg));
 947         r = RREG32(SMC_IND_DATA_0);
 948         spin_unlock_irqrestore(&adev->smc_idx_lock, flags);
 949         return r;
 950 }
 951
 952 static void si_smc_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
 953 {
 954         unsigned long flags;
 955
 956         spin_lock_irqsave(&adev->smc_idx_lock, flags);
 957         WREG32(SMC_IND_INDEX_0, (reg));
 958         WREG32(SMC_IND_DATA_0, (v));
 959         spin_unlock_irqrestore(&adev->smc_idx_lock, flags);
 960 }
 961
 962 static struct amdgpu_allowed_register_entry si_allowed_read_registers[] = {
 963         {GRBM_STATUS, false},
 964         {GB_ADDR_CONFIG, false},
 965         {MC_ARB_RAMCFG, false},
 966         {GB_TILE_MODE0, false},
 967         {GB_TILE_MODE1, false},
 968         {GB_TILE_MODE2, false},
 969         {GB_TILE_MODE3, false},
 970         {GB_TILE_MODE4, false},
 971         {GB_TILE_MODE5, false},
 972         {GB_TILE_MODE6, false},
 973         {GB_TILE_MODE7, false},
 974         {GB_TILE_MODE8, false},
 975         {GB_TILE_MODE9, false},
 976         {GB_TILE_MODE10, false},
 977         {GB_TILE_MODE11, false},
 978         {GB_TILE_MODE12, false},
 979         {GB_TILE_MODE13, false},
 980         {GB_TILE_MODE14, false},
 981         {GB_TILE_MODE15, false},
 982         {GB_TILE_MODE16, false},
 983         {GB_TILE_MODE17, false},
 984         {GB_TILE_MODE18, false},
 985         {GB_TILE_MODE19, false},
 986         {GB_TILE_MODE20, false},
 987         {GB_TILE_MODE21, false},
 988         {GB_TILE_MODE22, false},
 989         {GB_TILE_MODE23, false},
 990         {GB_TILE_MODE24, false},
 991         {GB_TILE_MODE25, false},
 992         {GB_TILE_MODE26, false},
 993         {GB_TILE_MODE27, false},
 994         {GB_TILE_MODE28, false},
 995         {GB_TILE_MODE29, false},
 996         {GB_TILE_MODE30, false},
 997         {GB_TILE_MODE31, false},
 998         {CC_RB_BACKEND_DISABLE, false, true},
 999         {GC_USER_RB_BACKEND_DISABLE, false, true},
1000         {PA_SC_RASTER_CONFIG, false, true},
1001 };
1002
1003 static uint32_t si_read_indexed_register(struct amdgpu_device *adev,
1004                                           u32 se_num, u32 sh_num,
1005                                           u32 reg_offset)
1006 {
1007         uint32_t val;
1008
1009         mutex_lock(&adev->grbm_idx_mutex);
1010         if (se_num != 0xffffffff || sh_num != 0xffffffff)
1011                 amdgpu_gfx_select_se_sh(adev, se_num, sh_num, 0xffffffff);
1012
1013         val = RREG32(reg_offset);
1014
1015         if (se_num != 0xffffffff || sh_num != 0xffffffff)
1016                 amdgpu_gfx_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
1017         mutex_unlock(&adev->grbm_idx_mutex);
1018         return val;
1019 }
1020
1021 static int si_read_register(struct amdgpu_device *adev, u32 se_num,
1022                              u32 sh_num, u32 reg_offset, u32 *value)
1023 {
1024         uint32_t i;
1025
1026         *value = 0;
1027         for (i = 0; i < ARRAY_SIZE(si_allowed_read_registers); i++) {
1028                 if (reg_offset != si_allowed_read_registers[i].reg_offset)
1029                         continue;
1030
1031                 if (!si_allowed_read_registers[i].untouched)
1032                         *value = si_allowed_read_registers[i].grbm_indexed ?
1033                                  si_read_indexed_register(adev, se_num,
1034                                                            sh_num, reg_offset) :
1035                                  RREG32(reg_offset);
1036                 return 0;
1037         }
1038         return -EINVAL;
1039 }
1040
1041 static bool si_read_disabled_bios(struct amdgpu_device *adev)
1042 {
1043         u32 bus_cntl;
1044         u32 d1vga_control = 0;
1045         u32 d2vga_control = 0;
1046         u32 vga_render_control = 0;
1047         u32 rom_cntl;
1048         bool r;
1049
1050         bus_cntl = RREG32(R600_BUS_CNTL);
1051         if (adev->mode_info.num_crtc) {
1052                 d1vga_control = RREG32(AVIVO_D1VGA_CONTROL);
1053                 d2vga_control = RREG32(AVIVO_D2VGA_CONTROL);
1054                 vga_render_control = RREG32(VGA_RENDER_CONTROL);
1055         }
1056         rom_cntl = RREG32(R600_ROM_CNTL);
1057
1058         /* enable the rom */
1059         WREG32(R600_BUS_CNTL, (bus_cntl & ~R600_BIOS_ROM_DIS));
1060         if (adev->mode_info.num_crtc) {
1061                 /* Disable VGA mode */
1062                 WREG32(AVIVO_D1VGA_CONTROL,
1063                        (d1vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE |
1064                                           AVIVO_DVGA_CONTROL_TIMING_SELECT)));
1065                 WREG32(AVIVO_D2VGA_CONTROL,
1066                        (d2vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE |
1067                                           AVIVO_DVGA_CONTROL_TIMING_SELECT)));
1068                 WREG32(VGA_RENDER_CONTROL,
1069                        (vga_render_control & C_000300_VGA_VSTATUS_CNTL));
1070         }
1071         WREG32(R600_ROM_CNTL, rom_cntl | R600_SCK_OVERWRITE);
1072
1073         r = amdgpu_read_bios(adev);
1074
1075         /* restore regs */
1076         WREG32(R600_BUS_CNTL, bus_cntl);
1077         if (adev->mode_info.num_crtc) {
1078                 WREG32(AVIVO_D1VGA_CONTROL, d1vga_control);
1079                 WREG32(AVIVO_D2VGA_CONTROL, d2vga_control);
1080                 WREG32(VGA_RENDER_CONTROL, vga_render_control);
1081         }
1082         WREG32(R600_ROM_CNTL, rom_cntl);
1083         return r;
1084 }
1085
1086 //xxx: not implemented
1087 static int si_asic_reset(struct amdgpu_device *adev)
1088 {
1089         return 0;
1090 }
1091
1092 static void si_vga_set_state(struct amdgpu_device *adev, bool state)
1093 {
1094         uint32_t temp;
1095
1096         temp = RREG32(CONFIG_CNTL);
1097         if (state == false) {
1098                 temp &= ~(1<<0);
1099                 temp |= (1<<1);
1100         } else {
1101                 temp &= ~(1<<1);
1102         }
1103         WREG32(CONFIG_CNTL, temp);
1104 }
1105
1106 static u32 si_get_xclk(struct amdgpu_device *adev)
1107 {
1108         u32 reference_clock = adev->clock.spll.reference_freq;
1109         u32 tmp;
1110
1111         tmp = RREG32(CG_CLKPIN_CNTL_2);
1112         if (tmp & MUX_TCLK_TO_XCLK)
1113                 return TCLK;
1114
1115         tmp = RREG32(CG_CLKPIN_CNTL);
1116         if (tmp & XTALIN_DIVIDE)
1117                 return reference_clock / 4;
1118
1119         return reference_clock;
1120 }
1121
1122 //xxx:not implemented
1123 static int si_set_uvd_clocks(struct amdgpu_device *adev, u32 vclk, u32 dclk)
1124 {
1125         return 0;
1126 }
1127
1128 static void si_detect_hw_virtualization(struct amdgpu_device *adev)
1129 {
1130         if (is_virtual_machine()) /* passthrough mode */
1131                 adev->virtualization.virtual_caps |= AMDGPU_PASSTHROUGH_MODE;
1132 }
1133
1134 static const struct amdgpu_asic_funcs si_asic_funcs =
1135 {
1136         .read_disabled_bios = &si_read_disabled_bios,
1137         .detect_hw_virtualization = si_detect_hw_virtualization,
1138         .read_register = &si_read_register,
1139         .reset = &si_asic_reset,
1140         .set_vga_state = &si_vga_set_state,
1141         .get_xclk = &si_get_xclk,
1142         .set_uvd_clocks = &si_set_uvd_clocks,
1143         .set_vce_clocks = NULL,
1144 };
1145
1146 static uint32_t si_get_rev_id(struct amdgpu_device *adev)
1147 {
1148         return (RREG32(CC_DRM_ID_STRAPS) & CC_DRM_ID_STRAPS__ATI_REV_ID_MASK)
1149                 >> CC_DRM_ID_STRAPS__ATI_REV_ID__SHIFT;
1150 }
1151
1152 static int si_common_early_init(void *handle)
1153 {
1154         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1155
1156         adev->smc_rreg = &si_smc_rreg;
1157         adev->smc_wreg = &si_smc_wreg;
1158         adev->pcie_rreg = &si_pcie_rreg;
1159         adev->pcie_wreg = &si_pcie_wreg;
1160         adev->pciep_rreg = &si_pciep_rreg;
1161         adev->pciep_wreg = &si_pciep_wreg;
1162         adev->uvd_ctx_rreg = NULL;
1163         adev->uvd_ctx_wreg = NULL;
1164         adev->didt_rreg = NULL;
1165         adev->didt_wreg = NULL;
1166
1167         adev->asic_funcs = &si_asic_funcs;
1168
1169         adev->rev_id = si_get_rev_id(adev);
1170         adev->external_rev_id = 0xFF;
1171         switch (adev->asic_type) {
1172         case CHIP_TAHITI:
1173                 adev->cg_flags =
1174                         AMD_CG_SUPPORT_GFX_MGCG |
1175                         AMD_CG_SUPPORT_GFX_MGLS |
1176                         /*AMD_CG_SUPPORT_GFX_CGCG |*/
1177                         AMD_CG_SUPPORT_GFX_CGLS |
1178                         AMD_CG_SUPPORT_GFX_CGTS |
1179                         AMD_CG_SUPPORT_GFX_CP_LS |
1180                         AMD_CG_SUPPORT_MC_MGCG |
1181                         AMD_CG_SUPPORT_SDMA_MGCG |
1182                         AMD_CG_SUPPORT_BIF_LS |
1183                         AMD_CG_SUPPORT_VCE_MGCG |
1184                         AMD_CG_SUPPORT_UVD_MGCG |
1185                         AMD_CG_SUPPORT_HDP_LS |
1186                         AMD_CG_SUPPORT_HDP_MGCG;
1187                         adev->pg_flags = 0;
1188                 adev->external_rev_id = (adev->rev_id == 0) ? 1 :
1189                                         (adev->rev_id == 1) ? 5 : 6;
1190                 break;
1191         case CHIP_PITCAIRN:
1192                 adev->cg_flags =
1193                         AMD_CG_SUPPORT_GFX_MGCG |
1194                         AMD_CG_SUPPORT_GFX_MGLS |
1195                         /*AMD_CG_SUPPORT_GFX_CGCG |*/
1196                         AMD_CG_SUPPORT_GFX_CGLS |
1197                         AMD_CG_SUPPORT_GFX_CGTS |
1198                         AMD_CG_SUPPORT_GFX_CP_LS |
1199                         AMD_CG_SUPPORT_GFX_RLC_LS |
1200                         AMD_CG_SUPPORT_MC_LS |
1201                         AMD_CG_SUPPORT_MC_MGCG |
1202                         AMD_CG_SUPPORT_SDMA_MGCG |
1203                         AMD_CG_SUPPORT_BIF_LS |
1204                         AMD_CG_SUPPORT_VCE_MGCG |
1205                         AMD_CG_SUPPORT_UVD_MGCG |
1206                         AMD_CG_SUPPORT_HDP_LS |
1207                         AMD_CG_SUPPORT_HDP_MGCG;
1208                 adev->pg_flags = 0;
1209                 break;
1210
1211         case CHIP_VERDE:
1212                 adev->cg_flags =
1213                         AMD_CG_SUPPORT_GFX_MGCG |
1214                         AMD_CG_SUPPORT_GFX_MGLS |
1215                         AMD_CG_SUPPORT_GFX_CGLS |
1216                         AMD_CG_SUPPORT_GFX_CGTS |
1217                         AMD_CG_SUPPORT_GFX_CGTS_LS |
1218                         AMD_CG_SUPPORT_GFX_CP_LS |
1219                         AMD_CG_SUPPORT_MC_LS |
1220                         AMD_CG_SUPPORT_MC_MGCG |
1221                         AMD_CG_SUPPORT_SDMA_MGCG |
1222                         AMD_CG_SUPPORT_SDMA_LS |
1223                         AMD_CG_SUPPORT_BIF_LS |
1224                         AMD_CG_SUPPORT_VCE_MGCG |
1225                         AMD_CG_SUPPORT_UVD_MGCG |
1226                         AMD_CG_SUPPORT_HDP_LS |
1227                         AMD_CG_SUPPORT_HDP_MGCG;
1228                 adev->pg_flags = 0;
1229                 //???
1230                 adev->external_rev_id = adev->rev_id + 0x14;
1231                 break;
1232         case CHIP_OLAND:
1233                 adev->cg_flags =
1234                         AMD_CG_SUPPORT_GFX_MGCG |
1235                         AMD_CG_SUPPORT_GFX_MGLS |
1236                         /*AMD_CG_SUPPORT_GFX_CGCG |*/
1237                         AMD_CG_SUPPORT_GFX_CGLS |
1238                         AMD_CG_SUPPORT_GFX_CGTS |
1239                         AMD_CG_SUPPORT_GFX_CP_LS |
1240                         AMD_CG_SUPPORT_GFX_RLC_LS |
1241                         AMD_CG_SUPPORT_MC_LS |
1242                         AMD_CG_SUPPORT_MC_MGCG |
1243                         AMD_CG_SUPPORT_SDMA_MGCG |
1244                         AMD_CG_SUPPORT_BIF_LS |
1245                         AMD_CG_SUPPORT_UVD_MGCG |
1246                         AMD_CG_SUPPORT_HDP_LS |
1247                         AMD_CG_SUPPORT_HDP_MGCG;
1248                 adev->pg_flags = 0;
1249                 break;
1250         case CHIP_HAINAN:
1251                 adev->cg_flags =
1252                         AMD_CG_SUPPORT_GFX_MGCG |
1253                         AMD_CG_SUPPORT_GFX_MGLS |
1254                         /*AMD_CG_SUPPORT_GFX_CGCG |*/
1255                         AMD_CG_SUPPORT_GFX_CGLS |
1256                         AMD_CG_SUPPORT_GFX_CGTS |
1257                         AMD_CG_SUPPORT_GFX_CP_LS |
1258                         AMD_CG_SUPPORT_GFX_RLC_LS |
1259                         AMD_CG_SUPPORT_MC_LS |
1260                         AMD_CG_SUPPORT_MC_MGCG |
1261                         AMD_CG_SUPPORT_SDMA_MGCG |
1262                         AMD_CG_SUPPORT_BIF_LS |
1263                         AMD_CG_SUPPORT_HDP_LS |
1264                         AMD_CG_SUPPORT_HDP_MGCG;
1265                 adev->pg_flags = 0;
1266                 break;
1267
1268         default:
1269                 return -EINVAL;
1270         }
1271
1272         return 0;
1273 }
1274
1275 static int si_common_sw_init(void *handle)
1276 {
1277         return 0;
1278 }
1279
1280 static int si_common_sw_fini(void *handle)
1281 {
1282         return 0;
1283 }
1284
1285
1286 static void si_init_golden_registers(struct amdgpu_device *adev)
1287 {
1288         switch (adev->asic_type) {
1289         case CHIP_TAHITI:
1290                 amdgpu_program_register_sequence(adev,
1291                                                  tahiti_golden_registers,
1292                                                  (const u32)ARRAY_SIZE(tahiti_golden_registers));
1293                 amdgpu_program_register_sequence(adev,
1294                                                  tahiti_golden_rlc_registers,
1295                                                  (const u32)ARRAY_SIZE(tahiti_golden_rlc_registers));
1296                 amdgpu_program_register_sequence(adev,
1297                                                  tahiti_mgcg_cgcg_init,
1298                                                  (const u32)ARRAY_SIZE(tahiti_mgcg_cgcg_init));
1299                 amdgpu_program_register_sequence(adev,
1300                                                  tahiti_golden_registers2,
1301                                                  (const u32)ARRAY_SIZE(tahiti_golden_registers2));
1302                 break;
1303         case CHIP_PITCAIRN:
1304                 amdgpu_program_register_sequence(adev,
1305                                                  pitcairn_golden_registers,
1306                                                  (const u32)ARRAY_SIZE(pitcairn_golden_registers));
1307                 amdgpu_program_register_sequence(adev,
1308                                                  pitcairn_golden_rlc_registers,
1309                                                  (const u32)ARRAY_SIZE(pitcairn_golden_rlc_registers));
1310                 amdgpu_program_register_sequence(adev,
1311                                                  pitcairn_mgcg_cgcg_init,
1312                                                  (const u32)ARRAY_SIZE(pitcairn_mgcg_cgcg_init));
1313         case CHIP_VERDE:
1314                 amdgpu_program_register_sequence(adev,
1315                                                  verde_golden_registers,
1316                                                  (const u32)ARRAY_SIZE(verde_golden_registers));
1317                 amdgpu_program_register_sequence(adev,
1318                                                  verde_golden_rlc_registers,
1319                                                  (const u32)ARRAY_SIZE(verde_golden_rlc_registers));
1320                 amdgpu_program_register_sequence(adev,
1321                                                  verde_mgcg_cgcg_init,
1322                                                  (const u32)ARRAY_SIZE(verde_mgcg_cgcg_init));
1323                 amdgpu_program_register_sequence(adev,
1324                                                  verde_pg_init,
1325                                                  (const u32)ARRAY_SIZE(verde_pg_init));
1326                 break;
1327         case CHIP_OLAND:
1328                 amdgpu_program_register_sequence(adev,
1329                                                  oland_golden_registers,
1330                                                  (const u32)ARRAY_SIZE(oland_golden_registers));
1331                 amdgpu_program_register_sequence(adev,
1332                                                  oland_golden_rlc_registers,
1333                                                  (const u32)ARRAY_SIZE(oland_golden_rlc_registers));
1334                 amdgpu_program_register_sequence(adev,
1335                                                  oland_mgcg_cgcg_init,
1336                                                  (const u32)ARRAY_SIZE(oland_mgcg_cgcg_init));
1337         case CHIP_HAINAN:
1338                 amdgpu_program_register_sequence(adev,
1339                                                  hainan_golden_registers,
1340                                                  (const u32)ARRAY_SIZE(hainan_golden_registers));
1341                 amdgpu_program_register_sequence(adev,
1342                                                  hainan_golden_registers2,
1343                                                  (const u32)ARRAY_SIZE(hainan_golden_registers2));
1344                 amdgpu_program_register_sequence(adev,
1345                                                  hainan_mgcg_cgcg_init,
1346                                                  (const u32)ARRAY_SIZE(hainan_mgcg_cgcg_init));
1347                 break;
1348
1349
1350         default:
1351                 BUG();
1352         }
1353 }
1354
1355 static void si_pcie_gen3_enable(struct amdgpu_device *adev)
1356 {
1357         struct pci_dev *root = adev->pdev->bus->self;
1358         int bridge_pos, gpu_pos;
1359         u32 speed_cntl, mask, current_data_rate;
1360         int ret, i;
1361         u16 tmp16;
1362
1363         if (pci_is_root_bus(adev->pdev->bus))
1364                 return;
1365
1366         if (amdgpu_pcie_gen2 == 0)
1367                 return;
1368
1369         if (adev->flags & AMD_IS_APU)
1370                 return;
1371
1372         ret = drm_pcie_get_speed_cap_mask(adev->ddev, &mask);
1373         if (ret != 0)
1374                 return;
1375
1376         if (!(mask & (DRM_PCIE_SPEED_50 | DRM_PCIE_SPEED_80)))
1377                 return;
1378
1379         speed_cntl = RREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL);
1380         current_data_rate = (speed_cntl & LC_CURRENT_DATA_RATE_MASK) >>
1381                 LC_CURRENT_DATA_RATE_SHIFT;
1382         if (mask & DRM_PCIE_SPEED_80) {
1383                 if (current_data_rate == 2) {
1384                         DRM_INFO("PCIE gen 3 link speeds already enabled\n");
1385                         return;
1386                 }
1387                 DRM_INFO("enabling PCIE gen 3 link speeds, disable with amdgpu.pcie_gen2=0\n");
1388         } else if (mask & DRM_PCIE_SPEED_50) {
1389                 if (current_data_rate == 1) {
1390                         DRM_INFO("PCIE gen 2 link speeds already enabled\n");
1391                         return;
1392                 }
1393                 DRM_INFO("enabling PCIE gen 2 link speeds, disable with amdgpu.pcie_gen2=0\n");
1394         }
1395
1396         bridge_pos = pci_pcie_cap(root);
1397         if (!bridge_pos)
1398                 return;
1399
1400         gpu_pos = pci_pcie_cap(adev->pdev);
1401         if (!gpu_pos)
1402                 return;
1403
1404         if (mask & DRM_PCIE_SPEED_80) {
1405                 if (current_data_rate != 2) {
1406                         u16 bridge_cfg, gpu_cfg;
1407                         u16 bridge_cfg2, gpu_cfg2;
1408                         u32 max_lw, current_lw, tmp;
1409
1410                         pci_read_config_word(root, bridge_pos + PCI_EXP_LNKCTL, &bridge_cfg);
1411                         pci_read_config_word(adev->pdev, gpu_pos + PCI_EXP_LNKCTL, &gpu_cfg);
1412
1413                         tmp16 = bridge_cfg | PCI_EXP_LNKCTL_HAWD;
1414                         pci_write_config_word(root, bridge_pos + PCI_EXP_LNKCTL, tmp16);
1415
1416                         tmp16 = gpu_cfg | PCI_EXP_LNKCTL_HAWD;
1417                         pci_write_config_word(adev->pdev, gpu_pos + PCI_EXP_LNKCTL, tmp16);
1418
1419                         tmp = RREG32_PCIE(PCIE_LC_STATUS1);
1420                         max_lw = (tmp & LC_DETECTED_LINK_WIDTH_MASK) >> LC_DETECTED_LINK_WIDTH_SHIFT;
1421                         current_lw = (tmp & LC_OPERATING_LINK_WIDTH_MASK) >> LC_OPERATING_LINK_WIDTH_SHIFT;
1422
1423                         if (current_lw < max_lw) {
1424                                 tmp = RREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL);
1425                                 if (tmp & LC_RENEGOTIATION_SUPPORT) {
1426                                         tmp &= ~(LC_LINK_WIDTH_MASK | LC_UPCONFIGURE_DIS);
1427                                         tmp |= (max_lw << LC_LINK_WIDTH_SHIFT);
1428                                         tmp |= LC_UPCONFIGURE_SUPPORT | LC_RENEGOTIATE_EN | LC_RECONFIG_NOW;
1429                                         WREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL, tmp);
1430                                 }
1431                         }
1432
1433                         for (i = 0; i < 10; i++) {
1434                                 pci_read_config_word(adev->pdev, gpu_pos + PCI_EXP_DEVSTA, &tmp16);
1435                                 if (tmp16 & PCI_EXP_DEVSTA_TRPND)
1436                                         break;
1437
1438                                 pci_read_config_word(root, bridge_pos + PCI_EXP_LNKCTL, &bridge_cfg);
1439                                 pci_read_config_word(adev->pdev, gpu_pos + PCI_EXP_LNKCTL, &gpu_cfg);
1440
1441                                 pci_read_config_word(root, bridge_pos + PCI_EXP_LNKCTL2, &bridge_cfg2);
1442                                 pci_read_config_word(adev->pdev, gpu_pos + PCI_EXP_LNKCTL2, &gpu_cfg2);
1443
1444                                 tmp = RREG32_PCIE_PORT(PCIE_LC_CNTL4);
1445                                 tmp |= LC_SET_QUIESCE;
1446                                 WREG32_PCIE_PORT(PCIE_LC_CNTL4, tmp);
1447
1448                                 tmp = RREG32_PCIE_PORT(PCIE_LC_CNTL4);
1449                                 tmp |= LC_REDO_EQ;
1450                                 WREG32_PCIE_PORT(PCIE_LC_CNTL4, tmp);
1451
1452                                 mdelay(100);
1453
1454                                 pci_read_config_word(root, bridge_pos + PCI_EXP_LNKCTL, &tmp16);
1455                                 tmp16 &= ~PCI_EXP_LNKCTL_HAWD;
1456                                 tmp16 |= (bridge_cfg & PCI_EXP_LNKCTL_HAWD);
1457                                 pci_write_config_word(root, bridge_pos + PCI_EXP_LNKCTL, tmp16);
1458
1459                                 pci_read_config_word(adev->pdev, gpu_pos + PCI_EXP_LNKCTL, &tmp16);
1460                                 tmp16 &= ~PCI_EXP_LNKCTL_HAWD;
1461                                 tmp16 |= (gpu_cfg & PCI_EXP_LNKCTL_HAWD);
1462                                 pci_write_config_word(adev->pdev, gpu_pos + PCI_EXP_LNKCTL, tmp16);
1463
1464                                 pci_read_config_word(root, bridge_pos + PCI_EXP_LNKCTL2, &tmp16);
1465                                 tmp16 &= ~((1 << 4) | (7 << 9));
1466                                 tmp16 |= (bridge_cfg2 & ((1 << 4) | (7 << 9)));
1467                                 pci_write_config_word(root, bridge_pos + PCI_EXP_LNKCTL2, tmp16);
1468
1469                                 pci_read_config_word(adev->pdev, gpu_pos + PCI_EXP_LNKCTL2, &tmp16);
1470                                 tmp16 &= ~((1 << 4) | (7 << 9));
1471                                 tmp16 |= (gpu_cfg2 & ((1 << 4) | (7 << 9)));
1472                                 pci_write_config_word(adev->pdev, gpu_pos + PCI_EXP_LNKCTL2, tmp16);
1473
1474                                 tmp = RREG32_PCIE_PORT(PCIE_LC_CNTL4);
1475                                 tmp &= ~LC_SET_QUIESCE;
1476                                 WREG32_PCIE_PORT(PCIE_LC_CNTL4, tmp);
1477                         }
1478                 }
1479         }
1480
1481         speed_cntl |= LC_FORCE_EN_SW_SPEED_CHANGE | LC_FORCE_DIS_HW_SPEED_CHANGE;
1482         speed_cntl &= ~LC_FORCE_DIS_SW_SPEED_CHANGE;
1483         WREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL, speed_cntl);
1484
1485         pci_read_config_word(adev->pdev, gpu_pos + PCI_EXP_LNKCTL2, &tmp16);
1486         tmp16 &= ~0xf;
1487         if (mask & DRM_PCIE_SPEED_80)
1488                 tmp16 |= 3;
1489         else if (mask & DRM_PCIE_SPEED_50)
1490                 tmp16 |= 2;
1491         else
1492                 tmp16 |= 1;
1493         pci_write_config_word(adev->pdev, gpu_pos + PCI_EXP_LNKCTL2, tmp16);
1494
1495         speed_cntl = RREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL);
1496         speed_cntl |= LC_INITIATE_LINK_SPEED_CHANGE;
1497         WREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL, speed_cntl);
1498
1499         for (i = 0; i < adev->usec_timeout; i++) {
1500                 speed_cntl = RREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL);
1501                 if ((speed_cntl & LC_INITIATE_LINK_SPEED_CHANGE) == 0)
1502                         break;
1503                 udelay(1);
1504         }
1505 }
1506
1507 static inline u32 si_pif_phy0_rreg(struct amdgpu_device *adev, u32 reg)
1508 {
1509         unsigned long flags;
1510         u32 r;
1511
1512         spin_lock_irqsave(&adev->pcie_idx_lock, flags);
1513         WREG32(EVERGREEN_PIF_PHY0_INDEX, ((reg) & 0xffff));
1514         r = RREG32(EVERGREEN_PIF_PHY0_DATA);
1515         spin_unlock_irqrestore(&adev->pcie_idx_lock, flags);
1516         return r;
1517 }
1518
1519 static inline void si_pif_phy0_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
1520 {
1521         unsigned long flags;
1522
1523         spin_lock_irqsave(&adev->pcie_idx_lock, flags);
1524         WREG32(EVERGREEN_PIF_PHY0_INDEX, ((reg) & 0xffff));
1525         WREG32(EVERGREEN_PIF_PHY0_DATA, (v));
1526         spin_unlock_irqrestore(&adev->pcie_idx_lock, flags);
1527 }
1528
1529 static inline u32 si_pif_phy1_rreg(struct amdgpu_device *adev, u32 reg)
1530 {
1531         unsigned long flags;
1532         u32 r;
1533
1534         spin_lock_irqsave(&adev->pcie_idx_lock, flags);
1535         WREG32(EVERGREEN_PIF_PHY1_INDEX, ((reg) & 0xffff));
1536         r = RREG32(EVERGREEN_PIF_PHY1_DATA);
1537         spin_unlock_irqrestore(&adev->pcie_idx_lock, flags);
1538         return r;
1539 }
1540
1541 static inline void si_pif_phy1_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
1542 {
1543         unsigned long flags;
1544
1545         spin_lock_irqsave(&adev->pcie_idx_lock, flags);
1546         WREG32(EVERGREEN_PIF_PHY1_INDEX, ((reg) & 0xffff));
1547         WREG32(EVERGREEN_PIF_PHY1_DATA, (v));
1548         spin_unlock_irqrestore(&adev->pcie_idx_lock, flags);
1549 }
1550 static void si_program_aspm(struct amdgpu_device *adev)
1551 {
1552         u32 data, orig;
1553         bool disable_l0s = false, disable_l1 = false, disable_plloff_in_l1 = false;
1554         bool disable_clkreq = false;
1555
1556         if (amdgpu_aspm == 0)
1557                 return;
1558
1559         if (adev->flags & AMD_IS_APU)
1560                 return;
1561         orig = data = RREG32_PCIE_PORT(PCIE_LC_N_FTS_CNTL);
1562         data &= ~LC_XMIT_N_FTS_MASK;
1563         data |= LC_XMIT_N_FTS(0x24) | LC_XMIT_N_FTS_OVERRIDE_EN;
1564         if (orig != data)
1565                 WREG32_PCIE_PORT(PCIE_LC_N_FTS_CNTL, data);
1566
1567         orig = data = RREG32_PCIE_PORT(PCIE_LC_CNTL3);
1568         data |= LC_GO_TO_RECOVERY;
1569         if (orig != data)
1570                 WREG32_PCIE_PORT(PCIE_LC_CNTL3, data);
1571
1572         orig = data = RREG32_PCIE(PCIE_P_CNTL);
1573         data |= P_IGNORE_EDB_ERR;
1574         if (orig != data)
1575                 WREG32_PCIE(PCIE_P_CNTL, data);
1576
1577         orig = data = RREG32_PCIE_PORT(PCIE_LC_CNTL);
1578         data &= ~(LC_L0S_INACTIVITY_MASK | LC_L1_INACTIVITY_MASK);
1579         data |= LC_PMI_TO_L1_DIS;
1580         if (!disable_l0s)
1581                 data |= LC_L0S_INACTIVITY(7);
1582
1583         if (!disable_l1) {
1584                 data |= LC_L1_INACTIVITY(7);
1585                 data &= ~LC_PMI_TO_L1_DIS;
1586                 if (orig != data)
1587                         WREG32_PCIE_PORT(PCIE_LC_CNTL, data);
1588
1589                 if (!disable_plloff_in_l1) {
1590                         bool clk_req_support;
1591
1592                         orig = data = si_pif_phy0_rreg(adev,PB0_PIF_PWRDOWN_0);
1593                         data &= ~(PLL_POWER_STATE_IN_OFF_0_MASK | PLL_POWER_STATE_IN_TXS2_0_MASK);
1594                         data |= PLL_POWER_STATE_IN_OFF_0(7) | PLL_POWER_STATE_IN_TXS2_0(7);
1595                         if (orig != data)
1596                                 si_pif_phy0_wreg(adev,PB0_PIF_PWRDOWN_0, data);
1597
1598                         orig = data = si_pif_phy0_rreg(adev,PB0_PIF_PWRDOWN_1);
1599                         data &= ~(PLL_POWER_STATE_IN_OFF_1_MASK | PLL_POWER_STATE_IN_TXS2_1_MASK);
1600                         data |= PLL_POWER_STATE_IN_OFF_1(7) | PLL_POWER_STATE_IN_TXS2_1(7);
1601                         if (orig != data)
1602                                 si_pif_phy0_wreg(adev,PB0_PIF_PWRDOWN_1, data);
1603
1604                         orig = data = si_pif_phy1_rreg(adev,PB1_PIF_PWRDOWN_0);
1605                         data &= ~(PLL_POWER_STATE_IN_OFF_0_MASK | PLL_POWER_STATE_IN_TXS2_0_MASK);
1606                         data |= PLL_POWER_STATE_IN_OFF_0(7) | PLL_POWER_STATE_IN_TXS2_0(7);
1607                         if (orig != data)
1608                                 si_pif_phy1_wreg(adev,PB1_PIF_PWRDOWN_0, data);
1609
1610                         orig = data = si_pif_phy1_rreg(adev,PB1_PIF_PWRDOWN_1);
1611                         data &= ~(PLL_POWER_STATE_IN_OFF_1_MASK | PLL_POWER_STATE_IN_TXS2_1_MASK);
1612                         data |= PLL_POWER_STATE_IN_OFF_1(7) | PLL_POWER_STATE_IN_TXS2_1(7);
1613                         if (orig != data)
1614                                 si_pif_phy1_wreg(adev,PB1_PIF_PWRDOWN_1, data);
1615
1616                         if ((adev->family != CHIP_OLAND) && (adev->family != CHIP_HAINAN)) {
1617                                 orig = data = si_pif_phy0_rreg(adev,PB0_PIF_PWRDOWN_0);
1618                                 data &= ~PLL_RAMP_UP_TIME_0_MASK;
1619                                 if (orig != data)
1620                                         si_pif_phy0_wreg(adev,PB0_PIF_PWRDOWN_0, data);
1621
1622                                 orig = data = si_pif_phy0_rreg(adev,PB0_PIF_PWRDOWN_1);
1623                                 data &= ~PLL_RAMP_UP_TIME_1_MASK;
1624                                 if (orig != data)
1625                                         si_pif_phy0_wreg(adev,PB0_PIF_PWRDOWN_1, data);
1626
1627                                 orig = data = si_pif_phy0_rreg(adev,PB0_PIF_PWRDOWN_2);
1628                                 data &= ~PLL_RAMP_UP_TIME_2_MASK;
1629                                 if (orig != data)
1630                                         si_pif_phy0_wreg(adev,PB0_PIF_PWRDOWN_2, data);
1631
1632                                 orig = data = si_pif_phy0_rreg(adev,PB0_PIF_PWRDOWN_3);
1633                                 data &= ~PLL_RAMP_UP_TIME_3_MASK;
1634                                 if (orig != data)
1635                                         si_pif_phy0_wreg(adev,PB0_PIF_PWRDOWN_3, data);
1636
1637                                 orig = data = si_pif_phy1_rreg(adev,PB1_PIF_PWRDOWN_0);
1638                                 data &= ~PLL_RAMP_UP_TIME_0_MASK;
1639                                 if (orig != data)
1640                                         si_pif_phy1_wreg(adev,PB1_PIF_PWRDOWN_0, data);
1641
1642                                 orig = data = si_pif_phy1_rreg(adev,PB1_PIF_PWRDOWN_1);
1643                                 data &= ~PLL_RAMP_UP_TIME_1_MASK;
1644                                 if (orig != data)
1645                                         si_pif_phy1_wreg(adev,PB1_PIF_PWRDOWN_1, data);
1646
1647                                 orig = data = si_pif_phy1_rreg(adev,PB1_PIF_PWRDOWN_2);
1648                                 data &= ~PLL_RAMP_UP_TIME_2_MASK;
1649                                 if (orig != data)
1650                                         si_pif_phy1_wreg(adev,PB1_PIF_PWRDOWN_2, data);
1651
1652                                 orig = data = si_pif_phy1_rreg(adev,PB1_PIF_PWRDOWN_3);
1653                                 data &= ~PLL_RAMP_UP_TIME_3_MASK;
1654                                 if (orig != data)
1655                                         si_pif_phy1_wreg(adev,PB1_PIF_PWRDOWN_3, data);
1656                         }
1657                         orig = data = RREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL);
1658                         data &= ~LC_DYN_LANES_PWR_STATE_MASK;
1659                         data |= LC_DYN_LANES_PWR_STATE(3);
1660                         if (orig != data)
1661                                 WREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL, data);
1662
1663                         orig = data = si_pif_phy0_rreg(adev,PB0_PIF_CNTL);
1664                         data &= ~LS2_EXIT_TIME_MASK;
1665                         if ((adev->family == CHIP_OLAND) || (adev->family == CHIP_HAINAN))
1666                                 data |= LS2_EXIT_TIME(5);
1667                         if (orig != data)
1668                                 si_pif_phy0_wreg(adev,PB0_PIF_CNTL, data);
1669
1670                         orig = data = si_pif_phy1_rreg(adev,PB1_PIF_CNTL);
1671                         data &= ~LS2_EXIT_TIME_MASK;
1672                         if ((adev->family == CHIP_OLAND) || (adev->family == CHIP_HAINAN))
1673                                 data |= LS2_EXIT_TIME(5);
1674                         if (orig != data)
1675                                 si_pif_phy1_wreg(adev,PB1_PIF_CNTL, data);
1676
1677                         if (!disable_clkreq &&
1678                             !pci_is_root_bus(adev->pdev->bus)) {
1679                                 struct pci_dev *root = adev->pdev->bus->self;
1680                                 u32 lnkcap;
1681
1682                                 clk_req_support = false;
1683                                 pcie_capability_read_dword(root, PCI_EXP_LNKCAP, &lnkcap);
1684                                 if (lnkcap & PCI_EXP_LNKCAP_CLKPM)
1685                                         clk_req_support = true;
1686                         } else {
1687                                 clk_req_support = false;
1688                         }
1689
1690                         if (clk_req_support) {
1691                                 orig = data = RREG32_PCIE_PORT(PCIE_LC_CNTL2);
1692                                 data |= LC_ALLOW_PDWN_IN_L1 | LC_ALLOW_PDWN_IN_L23;
1693                                 if (orig != data)
1694                                         WREG32_PCIE_PORT(PCIE_LC_CNTL2, data);
1695
1696                                 orig = data = RREG32(THM_CLK_CNTL);
1697                                 data &= ~(CMON_CLK_SEL_MASK | TMON_CLK_SEL_MASK);
1698                                 data |= CMON_CLK_SEL(1) | TMON_CLK_SEL(1);
1699                                 if (orig != data)
1700                                         WREG32(THM_CLK_CNTL, data);
1701
1702                                 orig = data = RREG32(MISC_CLK_CNTL);
1703                                 data &= ~(DEEP_SLEEP_CLK_SEL_MASK | ZCLK_SEL_MASK);
1704                                 data |= DEEP_SLEEP_CLK_SEL(1) | ZCLK_SEL(1);
1705                                 if (orig != data)
1706                                         WREG32(MISC_CLK_CNTL, data);
1707
1708                                 orig = data = RREG32(CG_CLKPIN_CNTL);
1709                                 data &= ~BCLK_AS_XCLK;
1710                                 if (orig != data)
1711                                         WREG32(CG_CLKPIN_CNTL, data);
1712
1713                                 orig = data = RREG32(CG_CLKPIN_CNTL_2);
1714                                 data &= ~FORCE_BIF_REFCLK_EN;
1715                                 if (orig != data)
1716                                         WREG32(CG_CLKPIN_CNTL_2, data);
1717
1718                                 orig = data = RREG32(MPLL_BYPASSCLK_SEL);
1719                                 data &= ~MPLL_CLKOUT_SEL_MASK;
1720                                 data |= MPLL_CLKOUT_SEL(4);
1721                                 if (orig != data)
1722                                         WREG32(MPLL_BYPASSCLK_SEL, data);
1723
1724                                 orig = data = RREG32(SPLL_CNTL_MODE);
1725                                 data &= ~SPLL_REFCLK_SEL_MASK;
1726                                 if (orig != data)
1727                                         WREG32(SPLL_CNTL_MODE, data);
1728                         }
1729                 }
1730         } else {
1731                 if (orig != data)
1732                         WREG32_PCIE_PORT(PCIE_LC_CNTL, data);
1733         }
1734
1735         orig = data = RREG32_PCIE(PCIE_CNTL2);
1736         data |= SLV_MEM_LS_EN | MST_MEM_LS_EN | REPLAY_MEM_LS_EN;
1737         if (orig != data)
1738                 WREG32_PCIE(PCIE_CNTL2, data);
1739
1740         if (!disable_l0s) {
1741                 data = RREG32_PCIE_PORT(PCIE_LC_N_FTS_CNTL);
1742                 if((data & LC_N_FTS_MASK) == LC_N_FTS_MASK) {
1743                         data = RREG32_PCIE(PCIE_LC_STATUS1);
1744                         if ((data & LC_REVERSE_XMIT) && (data & LC_REVERSE_RCVR)) {
1745                                 orig = data = RREG32_PCIE_PORT(PCIE_LC_CNTL);
1746                                 data &= ~LC_L0S_INACTIVITY_MASK;
1747                                 if (orig != data)
1748                                         WREG32_PCIE_PORT(PCIE_LC_CNTL, data);
1749                         }
1750                 }
1751         }
1752 }
1753
1754 static void si_fix_pci_max_read_req_size(struct amdgpu_device *adev)
1755 {
1756         int readrq;
1757         u16 v;
1758
1759         readrq = pcie_get_readrq(adev->pdev);
1760         v = ffs(readrq) - 8;
1761         if ((v == 0) || (v == 6) || (v == 7))
1762                 pcie_set_readrq(adev->pdev, 512);
1763 }
1764
1765 static int si_common_hw_init(void *handle)
1766 {
1767         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1768
1769         si_fix_pci_max_read_req_size(adev);
1770         si_init_golden_registers(adev);
1771         si_pcie_gen3_enable(adev);
1772         si_program_aspm(adev);
1773
1774         return 0;
1775 }
1776
1777 static int si_common_hw_fini(void *handle)
1778 {
1779         return 0;
1780 }
1781
1782 static int si_common_suspend(void *handle)
1783 {
1784         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1785
1786         return si_common_hw_fini(adev);
1787 }
1788
1789 static int si_common_resume(void *handle)
1790 {
1791         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1792
1793         return si_common_hw_init(adev);
1794 }
1795
1796 static bool si_common_is_idle(void *handle)
1797 {
1798         return true;
1799 }
1800
1801 static int si_common_wait_for_idle(void *handle)
1802 {
1803         return 0;
1804 }
1805
1806 static int si_common_soft_reset(void *handle)
1807 {
1808         return 0;
1809 }
1810
1811 static int si_common_set_clockgating_state(void *handle,
1812                                             enum amd_clockgating_state state)
1813 {
1814         return 0;
1815 }
1816
1817 static int si_common_set_powergating_state(void *handle,
1818                                             enum amd_powergating_state state)
1819 {
1820         return 0;
1821 }
1822
1823 static const struct amd_ip_funcs si_common_ip_funcs = {
1824         .name = "si_common",
1825         .early_init = si_common_early_init,
1826         .late_init = NULL,
1827         .sw_init = si_common_sw_init,
1828         .sw_fini = si_common_sw_fini,
1829         .hw_init = si_common_hw_init,
1830         .hw_fini = si_common_hw_fini,
1831         .suspend = si_common_suspend,
1832         .resume = si_common_resume,
1833         .is_idle = si_common_is_idle,
1834         .wait_for_idle = si_common_wait_for_idle,
1835         .soft_reset = si_common_soft_reset,
1836         .set_clockgating_state = si_common_set_clockgating_state,
1837         .set_powergating_state = si_common_set_powergating_state,
1838 };
1839
1840 static const struct amdgpu_ip_block_version si_common_ip_block =
1841 {
1842         .type = AMD_IP_BLOCK_TYPE_COMMON,
1843         .major = 1,
1844         .minor = 0,
1845         .rev = 0,
1846         .funcs = &si_common_ip_funcs,
1847 };
1848
1849 int si_set_ip_blocks(struct amdgpu_device *adev)
1850 {
1851         switch (adev->asic_type) {
1852         case CHIP_VERDE:
1853         case CHIP_TAHITI:
1854         case CHIP_PITCAIRN:
1855                 amdgpu_ip_block_add(adev, &si_common_ip_block);
1856                 amdgpu_ip_block_add(adev, &gmc_v6_0_ip_block);
1857                 amdgpu_ip_block_add(adev, &si_ih_ip_block);
1858                 amdgpu_ip_block_add(adev, &amdgpu_pp_ip_block);
1859                 if (adev->enable_virtual_display)
1860                         amdgpu_ip_block_add(adev, &dce_virtual_ip_block);
1861                 else
1862                         amdgpu_ip_block_add(adev, &dce_v6_0_ip_block);
1863                 amdgpu_ip_block_add(adev, &gfx_v6_0_ip_block);
1864                 amdgpu_ip_block_add(adev, &si_dma_ip_block);
1865                 /* amdgpu_ip_block_add(adev, &uvd_v3_1_ip_block); */
1866                 /* amdgpu_ip_block_add(adev, &vce_v1_0_ip_block); */
1867                 break;
1868         case CHIP_OLAND:
1869                 amdgpu_ip_block_add(adev, &si_common_ip_block);
1870                 amdgpu_ip_block_add(adev, &gmc_v6_0_ip_block);
1871                 amdgpu_ip_block_add(adev, &si_ih_ip_block);
1872                 amdgpu_ip_block_add(adev, &amdgpu_pp_ip_block);
1873                 if (adev->enable_virtual_display)
1874                         amdgpu_ip_block_add(adev, &dce_virtual_ip_block);
1875                 else
1876                         amdgpu_ip_block_add(adev, &dce_v6_4_ip_block);
1877                 amdgpu_ip_block_add(adev, &gfx_v6_0_ip_block);
1878                 amdgpu_ip_block_add(adev, &si_dma_ip_block);
1879                 /* amdgpu_ip_block_add(adev, &uvd_v3_1_ip_block); */
1880                 /* amdgpu_ip_block_add(adev, &vce_v1_0_ip_block); */
1881                 break;
1882         case CHIP_HAINAN:
1883                 amdgpu_ip_block_add(adev, &si_common_ip_block);
1884                 amdgpu_ip_block_add(adev, &gmc_v6_0_ip_block);
1885                 amdgpu_ip_block_add(adev, &si_ih_ip_block);
1886                 amdgpu_ip_block_add(adev, &amdgpu_pp_ip_block);
1887                 if (adev->enable_virtual_display)
1888                         amdgpu_ip_block_add(adev, &dce_virtual_ip_block);
1889                 amdgpu_ip_block_add(adev, &gfx_v6_0_ip_block);
1890                 amdgpu_ip_block_add(adev, &si_dma_ip_block);
1891                 break;
1892         default:
1893                 BUG();
1894         }
1895         return 0;
1896 }
1897