drivers/gpu/drm/amd/amdgpu/si.c

   1 /*
   2  * Copyright 2015 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23
  24 #include <linux/firmware.h>
  25 #include <linux/slab.h>
  26 #include <linux/module.h>
  27 #include "drmP.h"
  28 #include "amdgpu.h"
  29 #include "amdgpu_atombios.h"
  30 #include "amdgpu_ih.h"
  31 #include "amdgpu_uvd.h"
  32 #include "amdgpu_vce.h"
  33 #include "atom.h"
  34 #include "amdgpu_powerplay.h"
  35 #include "si/sid.h"
  36 #include "si_ih.h"
  37 #include "gfx_v6_0.h"
  38 #include "gmc_v6_0.h"
  39 #include "si_dma.h"
  40 #include "dce_v6_0.h"
  41 #include "si.h"
  42 #include "dce_virtual.h"
  43
  44 static const u32 tahiti_golden_registers[] =
  45 {
  46         0x17bc, 0x00000030, 0x00000011,
  47         0x2684, 0x00010000, 0x00018208,
  48         0x260c, 0xffffffff, 0x00000000,
  49         0x260d, 0xf00fffff, 0x00000400,
  50         0x260e, 0x0002021c, 0x00020200,
  51         0x031e, 0x00000080, 0x00000000,
  52         0x340c, 0x000000c0, 0x00800040,
  53         0x360c, 0x000000c0, 0x00800040,
  54         0x16ec, 0x000000f0, 0x00000070,
  55         0x16f0, 0x00200000, 0x50100000,
  56         0x1c0c, 0x31000311, 0x00000011,
  57         0x09df, 0x00000003, 0x000007ff,
  58         0x0903, 0x000007ff, 0x00000000,
  59         0x2285, 0xf000001f, 0x00000007,
  60         0x22c9, 0xffffffff, 0x00ffffff,
  61         0x22c4, 0x0000ff0f, 0x00000000,
  62         0xa293, 0x07ffffff, 0x4e000000,
  63         0xa0d4, 0x3f3f3fff, 0x2a00126a,
  64         0x000c, 0xffffffff, 0x0040,
  65         0x000d, 0x00000040, 0x00004040,
  66         0x2440, 0x07ffffff, 0x03000000,
  67         0x23a2, 0x01ff1f3f, 0x00000000,
  68         0x23a1, 0x01ff1f3f, 0x00000000,
  69         0x2418, 0x0000007f, 0x00000020,
  70         0x2542, 0x00010000, 0x00010000,
  71         0x2b05, 0x00000200, 0x000002fb,
  72         0x2b04, 0xffffffff, 0x0000543b,
  73         0x2b03, 0xffffffff, 0xa9210876,
  74         0x2234, 0xffffffff, 0x000fff40,
  75         0x2235, 0x0000001f, 0x00000010,
  76         0x0504, 0x20000000, 0x20fffed8,
  77         0x0570, 0x000c0fc0, 0x000c0400,
  78         0x052c, 0x0fffffff, 0xffffffff,
  79         0x052d, 0x0fffffff, 0x0fffffff,
  80         0x052e, 0x0fffffff, 0x0fffffff,
  81         0x052f, 0x0fffffff, 0x0fffffff
  82 };
  83
  84 static const u32 tahiti_golden_registers2[] =
  85 {
  86         0x0319, 0x00000001, 0x00000001
  87 };
  88
  89 static const u32 tahiti_golden_rlc_registers[] =
  90 {
  91         0x263e, 0xffffffff, 0x12011003,
  92         0x3109, 0xffffffff, 0x00601005,
  93         0x311f, 0xffffffff, 0x10104040,
  94         0x3122, 0xffffffff, 0x0100000a,
  95         0x30c5, 0xffffffff, 0x00000800,
  96         0x30c3, 0xffffffff, 0x800000f4,
  97         0x3d2a, 0x00000008, 0x00000000
  98 };
  99
 100 static const u32 pitcairn_golden_registers[] =
 101 {
 102         0x17bc, 0x00000030, 0x00000011,
 103         0x2684, 0x00010000, 0x00018208,
 104         0x260c, 0xffffffff, 0x00000000,
 105         0x260d, 0xf00fffff, 0x00000400,
 106         0x260e, 0x0002021c, 0x00020200,
 107         0x031e, 0x00000080, 0x00000000,
 108         0x340c, 0x000300c0, 0x00800040,
 109         0x360c, 0x000300c0, 0x00800040,
 110         0x16ec, 0x000000f0, 0x00000070,
 111         0x16f0, 0x00200000, 0x50100000,
 112         0x1c0c, 0x31000311, 0x00000011,
 113         0x0ab9, 0x00073ffe, 0x000022a2,
 114         0x0903, 0x000007ff, 0x00000000,
 115         0x2285, 0xf000001f, 0x00000007,
 116         0x22c9, 0xffffffff, 0x00ffffff,
 117         0x22c4, 0x0000ff0f, 0x00000000,
 118         0xa293, 0x07ffffff, 0x4e000000,
 119         0xa0d4, 0x3f3f3fff, 0x2a00126a,
 120         0x000c, 0xffffffff, 0x0040,
 121         0x000d, 0x00000040, 0x00004040,
 122         0x2440, 0x07ffffff, 0x03000000,
 123         0x2418, 0x0000007f, 0x00000020,
 124         0x2542, 0x00010000, 0x00010000,
 125         0x2b05, 0x000003ff, 0x000000f7,
 126         0x2b04, 0xffffffff, 0x00000000,
 127         0x2b03, 0xffffffff, 0x32761054,
 128         0x2235, 0x0000001f, 0x00000010,
 129         0x0570, 0x000c0fc0, 0x000c0400,
 130         0x052c, 0x0fffffff, 0xffffffff,
 131         0x052d, 0x0fffffff, 0x0fffffff,
 132         0x052e, 0x0fffffff, 0x0fffffff,
 133         0x052f, 0x0fffffff, 0x0fffffff
 134 };
 135
 136 static const u32 pitcairn_golden_rlc_registers[] =
 137 {
 138         0x263e, 0xffffffff, 0x12011003,
 139         0x3109, 0xffffffff, 0x00601004,
 140         0x311f, 0xffffffff, 0x10102020,
 141         0x3122, 0xffffffff, 0x01000020,
 142         0x30c5, 0xffffffff, 0x00000800,
 143         0x30c3, 0xffffffff, 0x800000a4
 144 };
 145
 146 static const u32 verde_pg_init[] =
 147 {
 148         0xd4f, 0xffffffff, 0x40000,
 149         0xd4e, 0xffffffff, 0x200010ff,
 150         0xd4f, 0xffffffff, 0x0,
 151         0xd4f, 0xffffffff, 0x0,
 152         0xd4f, 0xffffffff, 0x0,
 153         0xd4f, 0xffffffff, 0x0,
 154         0xd4f, 0xffffffff, 0x0,
 155         0xd4f, 0xffffffff, 0x7007,
 156         0xd4e, 0xffffffff, 0x300010ff,
 157         0xd4f, 0xffffffff, 0x0,
 158         0xd4f, 0xffffffff, 0x0,
 159         0xd4f, 0xffffffff, 0x0,
 160         0xd4f, 0xffffffff, 0x0,
 161         0xd4f, 0xffffffff, 0x0,
 162         0xd4f, 0xffffffff, 0x400000,
 163         0xd4e, 0xffffffff, 0x100010ff,
 164         0xd4f, 0xffffffff, 0x0,
 165         0xd4f, 0xffffffff, 0x0,
 166         0xd4f, 0xffffffff, 0x0,
 167         0xd4f, 0xffffffff, 0x0,
 168         0xd4f, 0xffffffff, 0x0,
 169         0xd4f, 0xffffffff, 0x120200,
 170         0xd4e, 0xffffffff, 0x500010ff,
 171         0xd4f, 0xffffffff, 0x0,
 172         0xd4f, 0xffffffff, 0x0,
 173         0xd4f, 0xffffffff, 0x0,
 174         0xd4f, 0xffffffff, 0x0,
 175         0xd4f, 0xffffffff, 0x0,
 176         0xd4f, 0xffffffff, 0x1e1e16,
 177         0xd4e, 0xffffffff, 0x600010ff,
 178         0xd4f, 0xffffffff, 0x0,
 179         0xd4f, 0xffffffff, 0x0,
 180         0xd4f, 0xffffffff, 0x0,
 181         0xd4f, 0xffffffff, 0x0,
 182         0xd4f, 0xffffffff, 0x0,
 183         0xd4f, 0xffffffff, 0x171f1e,
 184         0xd4e, 0xffffffff, 0x700010ff,
 185         0xd4f, 0xffffffff, 0x0,
 186         0xd4f, 0xffffffff, 0x0,
 187         0xd4f, 0xffffffff, 0x0,
 188         0xd4f, 0xffffffff, 0x0,
 189         0xd4f, 0xffffffff, 0x0,
 190         0xd4f, 0xffffffff, 0x0,
 191         0xd4e, 0xffffffff, 0x9ff,
 192         0xd40, 0xffffffff, 0x0,
 193         0xd41, 0xffffffff, 0x10000800,
 194         0xd41, 0xffffffff, 0xf,
 195         0xd41, 0xffffffff, 0xf,
 196         0xd40, 0xffffffff, 0x4,
 197         0xd41, 0xffffffff, 0x1000051e,
 198         0xd41, 0xffffffff, 0xffff,
 199         0xd41, 0xffffffff, 0xffff,
 200         0xd40, 0xffffffff, 0x8,
 201         0xd41, 0xffffffff, 0x80500,
 202         0xd40, 0xffffffff, 0x12,
 203         0xd41, 0xffffffff, 0x9050c,
 204         0xd40, 0xffffffff, 0x1d,
 205         0xd41, 0xffffffff, 0xb052c,
 206         0xd40, 0xffffffff, 0x2a,
 207         0xd41, 0xffffffff, 0x1053e,
 208         0xd40, 0xffffffff, 0x2d,
 209         0xd41, 0xffffffff, 0x10546,
 210         0xd40, 0xffffffff, 0x30,
 211         0xd41, 0xffffffff, 0xa054e,
 212         0xd40, 0xffffffff, 0x3c,
 213         0xd41, 0xffffffff, 0x1055f,
 214         0xd40, 0xffffffff, 0x3f,
 215         0xd41, 0xffffffff, 0x10567,
 216         0xd40, 0xffffffff, 0x42,
 217         0xd41, 0xffffffff, 0x1056f,
 218         0xd40, 0xffffffff, 0x45,
 219         0xd41, 0xffffffff, 0x10572,
 220         0xd40, 0xffffffff, 0x48,
 221         0xd41, 0xffffffff, 0x20575,
 222         0xd40, 0xffffffff, 0x4c,
 223         0xd41, 0xffffffff, 0x190801,
 224         0xd40, 0xffffffff, 0x67,
 225         0xd41, 0xffffffff, 0x1082a,
 226         0xd40, 0xffffffff, 0x6a,
 227         0xd41, 0xffffffff, 0x1b082d,
 228         0xd40, 0xffffffff, 0x87,
 229         0xd41, 0xffffffff, 0x310851,
 230         0xd40, 0xffffffff, 0xba,
 231         0xd41, 0xffffffff, 0x891,
 232         0xd40, 0xffffffff, 0xbc,
 233         0xd41, 0xffffffff, 0x893,
 234         0xd40, 0xffffffff, 0xbe,
 235         0xd41, 0xffffffff, 0x20895,
 236         0xd40, 0xffffffff, 0xc2,
 237         0xd41, 0xffffffff, 0x20899,
 238         0xd40, 0xffffffff, 0xc6,
 239         0xd41, 0xffffffff, 0x2089d,
 240         0xd40, 0xffffffff, 0xca,
 241         0xd41, 0xffffffff, 0x8a1,
 242         0xd40, 0xffffffff, 0xcc,
 243         0xd41, 0xffffffff, 0x8a3,
 244         0xd40, 0xffffffff, 0xce,
 245         0xd41, 0xffffffff, 0x308a5,
 246         0xd40, 0xffffffff, 0xd3,
 247         0xd41, 0xffffffff, 0x6d08cd,
 248         0xd40, 0xffffffff, 0x142,
 249         0xd41, 0xffffffff, 0x2000095a,
 250         0xd41, 0xffffffff, 0x1,
 251         0xd40, 0xffffffff, 0x144,
 252         0xd41, 0xffffffff, 0x301f095b,
 253         0xd40, 0xffffffff, 0x165,
 254         0xd41, 0xffffffff, 0xc094d,
 255         0xd40, 0xffffffff, 0x173,
 256         0xd41, 0xffffffff, 0xf096d,
 257         0xd40, 0xffffffff, 0x184,
 258         0xd41, 0xffffffff, 0x15097f,
 259         0xd40, 0xffffffff, 0x19b,
 260         0xd41, 0xffffffff, 0xc0998,
 261         0xd40, 0xffffffff, 0x1a9,
 262         0xd41, 0xffffffff, 0x409a7,
 263         0xd40, 0xffffffff, 0x1af,
 264         0xd41, 0xffffffff, 0xcdc,
 265         0xd40, 0xffffffff, 0x1b1,
 266         0xd41, 0xffffffff, 0x800,
 267         0xd42, 0xffffffff, 0x6c9b2000,
 268         0xd44, 0xfc00, 0x2000,
 269         0xd51, 0xffffffff, 0xfc0,
 270         0xa35, 0x00000100, 0x100
 271 };
 272
 273 static const u32 verde_golden_rlc_registers[] =
 274 {
 275         0x3109, 0xffffffff, 0x033f1005,
 276         0x311f, 0xffffffff, 0x10808020,
 277         0x3122, 0xffffffff, 0x00800008,
 278         0x30c5, 0xffffffff, 0x00001000,
 279         0x30c3, 0xffffffff, 0x80010014
 280 };
 281
 282 static const u32 verde_golden_registers[] =
 283 {
 284         0x2684, 0x00010000, 0x00018208,
 285         0x260c, 0xffffffff, 0x00000000,
 286         0x260d, 0xf00fffff, 0x00000400,
 287         0x260e, 0x0002021c, 0x00020200,
 288         0x031e, 0x00000080, 0x00000000,
 289         0x340c, 0x000300c0, 0x00800040,
 290         0x340c, 0x000300c0, 0x00800040,
 291         0x360c, 0x000300c0, 0x00800040,
 292         0x360c, 0x000300c0, 0x00800040,
 293         0x16ec, 0x000000f0, 0x00000070,
 294         0x16f0, 0x00200000, 0x50100000,
 295
 296         0x1c0c, 0x31000311, 0x00000011,
 297         0x0ab9, 0x00073ffe, 0x000022a2,
 298         0x0ab9, 0x00073ffe, 0x000022a2,
 299         0x0ab9, 0x00073ffe, 0x000022a2,
 300         0x0903, 0x000007ff, 0x00000000,
 301         0x0903, 0x000007ff, 0x00000000,
 302         0x0903, 0x000007ff, 0x00000000,
 303         0x2285, 0xf000001f, 0x00000007,
 304         0x2285, 0xf000001f, 0x00000007,
 305         0x2285, 0xf000001f, 0x00000007,
 306         0x2285, 0xffffffff, 0x00ffffff,
 307         0x22c4, 0x0000ff0f, 0x00000000,
 308
 309         0xa293, 0x07ffffff, 0x4e000000,
 310         0xa0d4, 0x3f3f3fff, 0x0000124a,
 311         0xa0d4, 0x3f3f3fff, 0x0000124a,
 312         0xa0d4, 0x3f3f3fff, 0x0000124a,
 313         0x000c, 0x000000ff, 0x0040,
 314         0x000d, 0x00000040, 0x00004040,
 315         0x2440, 0x07ffffff, 0x03000000,
 316         0x2440, 0x07ffffff, 0x03000000,
 317         0x23a2, 0x01ff1f3f, 0x00000000,
 318         0x23a3, 0x01ff1f3f, 0x00000000,
 319         0x23a2, 0x01ff1f3f, 0x00000000,
 320         0x23a1, 0x01ff1f3f, 0x00000000,
 321         0x23a1, 0x01ff1f3f, 0x00000000,
 322
 323         0x23a1, 0x01ff1f3f, 0x00000000,
 324         0x2418, 0x0000007f, 0x00000020,
 325         0x2542, 0x00010000, 0x00010000,
 326         0x2b01, 0x000003ff, 0x00000003,
 327         0x2b05, 0x000003ff, 0x00000003,
 328         0x2b05, 0x000003ff, 0x00000003,
 329         0x2b04, 0xffffffff, 0x00000000,
 330         0x2b04, 0xffffffff, 0x00000000,
 331         0x2b04, 0xffffffff, 0x00000000,
 332         0x2b03, 0xffffffff, 0x00001032,
 333         0x2b03, 0xffffffff, 0x00001032,
 334         0x2b03, 0xffffffff, 0x00001032,
 335         0x2235, 0x0000001f, 0x00000010,
 336         0x2235, 0x0000001f, 0x00000010,
 337         0x2235, 0x0000001f, 0x00000010,
 338         0x0570, 0x000c0fc0, 0x000c0400
 339 };
 340
 341 static const u32 oland_golden_registers[] =
 342 {
 343         0x2684, 0x00010000, 0x00018208,
 344         0x260c, 0xffffffff, 0x00000000,
 345         0x260d, 0xf00fffff, 0x00000400,
 346         0x260e, 0x0002021c, 0x00020200,
 347         0x031e, 0x00000080, 0x00000000,
 348         0x340c, 0x000300c0, 0x00800040,
 349         0x360c, 0x000300c0, 0x00800040,
 350         0x16ec, 0x000000f0, 0x00000070,
 351         0x16f9, 0x00200000, 0x50100000,
 352         0x1c0c, 0x31000311, 0x00000011,
 353         0x0ab9, 0x00073ffe, 0x000022a2,
 354         0x0903, 0x000007ff, 0x00000000,
 355         0x2285, 0xf000001f, 0x00000007,
 356         0x22c9, 0xffffffff, 0x00ffffff,
 357         0x22c4, 0x0000ff0f, 0x00000000,
 358         0xa293, 0x07ffffff, 0x4e000000,
 359         0xa0d4, 0x3f3f3fff, 0x00000082,
 360         0x000c, 0x000000ff, 0x0040,
 361         0x000d, 0x00000040, 0x00004040,
 362         0x2440, 0x07ffffff, 0x03000000,
 363         0x2418, 0x0000007f, 0x00000020,
 364         0x2542, 0x00010000, 0x00010000,
 365         0x2b05, 0x000003ff, 0x000000f3,
 366         0x2b04, 0xffffffff, 0x00000000,
 367         0x2b03, 0xffffffff, 0x00003210,
 368         0x2235, 0x0000001f, 0x00000010,
 369         0x0570, 0x000c0fc0, 0x000c0400
 370 };
 371
 372 static const u32 oland_golden_rlc_registers[] =
 373 {
 374         0x3109, 0xffffffff, 0x00601005,
 375         0x311f, 0xffffffff, 0x10104040,
 376         0x3122, 0xffffffff, 0x0100000a,
 377         0x30c5, 0xffffffff, 0x00000800,
 378         0x30c3, 0xffffffff, 0x800000f4
 379 };
 380
 381 static const u32 hainan_golden_registers[] =
 382 {
 383         0x17bc, 0x00000030, 0x00000011,
 384         0x2684, 0x00010000, 0x00018208,
 385         0x260c, 0xffffffff, 0x00000000,
 386         0x260d, 0xf00fffff, 0x00000400,
 387         0x260e, 0x0002021c, 0x00020200,
 388         0x031e, 0x00000080, 0x00000000,
 389         0x3430, 0xff000fff, 0x00000100,
 390         0x340c, 0x000300c0, 0x00800040,
 391         0x3630, 0xff000fff, 0x00000100,
 392         0x360c, 0x000300c0, 0x00800040,
 393         0x16ec, 0x000000f0, 0x00000070,
 394         0x16f0, 0x00200000, 0x50100000,
 395         0x1c0c, 0x31000311, 0x00000011,
 396         0x0ab9, 0x00073ffe, 0x000022a2,
 397         0x0903, 0x000007ff, 0x00000000,
 398         0x2285, 0xf000001f, 0x00000007,
 399         0x22c9, 0xffffffff, 0x00ffffff,
 400         0x22c4, 0x0000ff0f, 0x00000000,
 401         0xa293, 0x07ffffff, 0x4e000000,
 402         0xa0d4, 0x3f3f3fff, 0x00000000,
 403         0x000c, 0xffffffff, 0x0040,
 404         0x000d, 0x00000040, 0x00004040,
 405         0x2440, 0x03e00000, 0x03600000,
 406         0x2418, 0x0000007f, 0x00000020,
 407         0x2542, 0x00010000, 0x00010000,
 408         0x2b05, 0x000003ff, 0x000000f1,
 409         0x2b04, 0xffffffff, 0x00000000,
 410         0x2b03, 0xffffffff, 0x00003210,
 411         0x2235, 0x0000001f, 0x00000010,
 412         0x0570, 0x000c0fc0, 0x000c0400,
 413         0x052c, 0x0fffffff, 0xffffffff,
 414         0x052d, 0x0fffffff, 0x0fffffff,
 415         0x052e, 0x0fffffff, 0x0fffffff,
 416         0x052f, 0x0fffffff, 0x0fffffff
 417 };
 418
 419 static const u32 hainan_golden_registers2[] =
 420 {
 421         0x263e, 0xffffffff, 0x2011003
 422 };
 423
 424 static const u32 tahiti_mgcg_cgcg_init[] =
 425 {
 426         0x3100, 0xffffffff, 0xfffffffc,
 427         0x200b, 0xffffffff, 0xe0000000,
 428         0x2698, 0xffffffff, 0x00000100,
 429         0x24a9, 0xffffffff, 0x00000100,
 430         0x3059, 0xffffffff, 0x00000100,
 431         0x25dd, 0xffffffff, 0x00000100,
 432         0x2261, 0xffffffff, 0x06000100,
 433         0x2286, 0xffffffff, 0x00000100,
 434         0x24a8, 0xffffffff, 0x00000100,
 435         0x30e0, 0xffffffff, 0x00000100,
 436         0x22ca, 0xffffffff, 0x00000100,
 437         0x2451, 0xffffffff, 0x00000100,
 438         0x2362, 0xffffffff, 0x00000100,
 439         0x2363, 0xffffffff, 0x00000100,
 440         0x240c, 0xffffffff, 0x00000100,
 441         0x240d, 0xffffffff, 0x00000100,
 442         0x240e, 0xffffffff, 0x00000100,
 443         0x240f, 0xffffffff, 0x00000100,
 444         0x2b60, 0xffffffff, 0x00000100,
 445         0x2b15, 0xffffffff, 0x00000100,
 446         0x225f, 0xffffffff, 0x06000100,
 447         0x261a, 0xffffffff, 0x00000100,
 448         0x2544, 0xffffffff, 0x00000100,
 449         0x2bc1, 0xffffffff, 0x00000100,
 450         0x2b81, 0xffffffff, 0x00000100,
 451         0x2527, 0xffffffff, 0x00000100,
 452         0x200b, 0xffffffff, 0xe0000000,
 453         0x2458, 0xffffffff, 0x00010000,
 454         0x2459, 0xffffffff, 0x00030002,
 455         0x245a, 0xffffffff, 0x00040007,
 456         0x245b, 0xffffffff, 0x00060005,
 457         0x245c, 0xffffffff, 0x00090008,
 458         0x245d, 0xffffffff, 0x00020001,
 459         0x245e, 0xffffffff, 0x00040003,
 460         0x245f, 0xffffffff, 0x00000007,
 461         0x2460, 0xffffffff, 0x00060005,
 462         0x2461, 0xffffffff, 0x00090008,
 463         0x2462, 0xffffffff, 0x00030002,
 464         0x2463, 0xffffffff, 0x00050004,
 465         0x2464, 0xffffffff, 0x00000008,
 466         0x2465, 0xffffffff, 0x00070006,
 467         0x2466, 0xffffffff, 0x000a0009,
 468         0x2467, 0xffffffff, 0x00040003,
 469         0x2468, 0xffffffff, 0x00060005,
 470         0x2469, 0xffffffff, 0x00000009,
 471         0x246a, 0xffffffff, 0x00080007,
 472         0x246b, 0xffffffff, 0x000b000a,
 473         0x246c, 0xffffffff, 0x00050004,
 474         0x246d, 0xffffffff, 0x00070006,
 475         0x246e, 0xffffffff, 0x0008000b,
 476         0x246f, 0xffffffff, 0x000a0009,
 477         0x2470, 0xffffffff, 0x000d000c,
 478         0x2471, 0xffffffff, 0x00060005,
 479         0x2472, 0xffffffff, 0x00080007,
 480         0x2473, 0xffffffff, 0x0000000b,
 481         0x2474, 0xffffffff, 0x000a0009,
 482         0x2475, 0xffffffff, 0x000d000c,
 483         0x2476, 0xffffffff, 0x00070006,
 484         0x2477, 0xffffffff, 0x00090008,
 485         0x2478, 0xffffffff, 0x0000000c,
 486         0x2479, 0xffffffff, 0x000b000a,
 487         0x247a, 0xffffffff, 0x000e000d,
 488         0x247b, 0xffffffff, 0x00080007,
 489         0x247c, 0xffffffff, 0x000a0009,
 490         0x247d, 0xffffffff, 0x0000000d,
 491         0x247e, 0xffffffff, 0x000c000b,
 492         0x247f, 0xffffffff, 0x000f000e,
 493         0x2480, 0xffffffff, 0x00090008,
 494         0x2481, 0xffffffff, 0x000b000a,
 495         0x2482, 0xffffffff, 0x000c000f,
 496         0x2483, 0xffffffff, 0x000e000d,
 497         0x2484, 0xffffffff, 0x00110010,
 498         0x2485, 0xffffffff, 0x000a0009,
 499         0x2486, 0xffffffff, 0x000c000b,
 500         0x2487, 0xffffffff, 0x0000000f,
 501         0x2488, 0xffffffff, 0x000e000d,
 502         0x2489, 0xffffffff, 0x00110010,
 503         0x248a, 0xffffffff, 0x000b000a,
 504         0x248b, 0xffffffff, 0x000d000c,
 505         0x248c, 0xffffffff, 0x00000010,
 506         0x248d, 0xffffffff, 0x000f000e,
 507         0x248e, 0xffffffff, 0x00120011,
 508         0x248f, 0xffffffff, 0x000c000b,
 509         0x2490, 0xffffffff, 0x000e000d,
 510         0x2491, 0xffffffff, 0x00000011,
 511         0x2492, 0xffffffff, 0x0010000f,
 512         0x2493, 0xffffffff, 0x00130012,
 513         0x2494, 0xffffffff, 0x000d000c,
 514         0x2495, 0xffffffff, 0x000f000e,
 515         0x2496, 0xffffffff, 0x00100013,
 516         0x2497, 0xffffffff, 0x00120011,
 517         0x2498, 0xffffffff, 0x00150014,
 518         0x2499, 0xffffffff, 0x000e000d,
 519         0x249a, 0xffffffff, 0x0010000f,
 520         0x249b, 0xffffffff, 0x00000013,
 521         0x249c, 0xffffffff, 0x00120011,
 522         0x249d, 0xffffffff, 0x00150014,
 523         0x249e, 0xffffffff, 0x000f000e,
 524         0x249f, 0xffffffff, 0x00110010,
 525         0x24a0, 0xffffffff, 0x00000014,
 526         0x24a1, 0xffffffff, 0x00130012,
 527         0x24a2, 0xffffffff, 0x00160015,
 528         0x24a3, 0xffffffff, 0x0010000f,
 529         0x24a4, 0xffffffff, 0x00120011,
 530         0x24a5, 0xffffffff, 0x00000015,
 531         0x24a6, 0xffffffff, 0x00140013,
 532         0x24a7, 0xffffffff, 0x00170016,
 533         0x2454, 0xffffffff, 0x96940200,
 534         0x21c2, 0xffffffff, 0x00900100,
 535         0x311e, 0xffffffff, 0x00000080,
 536         0x3101, 0xffffffff, 0x0020003f,
 537         0x000c, 0xffffffff, 0x0000001c,
 538         0x000d, 0x000f0000, 0x000f0000,
 539         0x0583, 0xffffffff, 0x00000100,
 540         0x0409, 0xffffffff, 0x00000100,
 541         0x040b, 0x00000101, 0x00000000,
 542         0x082a, 0xffffffff, 0x00000104,
 543         0x0993, 0x000c0000, 0x000c0000,
 544         0x0992, 0x000c0000, 0x000c0000,
 545         0x1579, 0xff000fff, 0x00000100,
 546         0x157a, 0x00000001, 0x00000001,
 547         0x0bd4, 0x00000001, 0x00000001,
 548         0x0c33, 0xc0000fff, 0x00000104,
 549         0x3079, 0x00000001, 0x00000001,
 550         0x3430, 0xfffffff0, 0x00000100,
 551         0x3630, 0xfffffff0, 0x00000100
 552 };
 553 static const u32 pitcairn_mgcg_cgcg_init[] =
 554 {
 555         0x3100, 0xffffffff, 0xfffffffc,
 556         0x200b, 0xffffffff, 0xe0000000,
 557         0x2698, 0xffffffff, 0x00000100,
 558         0x24a9, 0xffffffff, 0x00000100,
 559         0x3059, 0xffffffff, 0x00000100,
 560         0x25dd, 0xffffffff, 0x00000100,
 561         0x2261, 0xffffffff, 0x06000100,
 562         0x2286, 0xffffffff, 0x00000100,
 563         0x24a8, 0xffffffff, 0x00000100,
 564         0x30e0, 0xffffffff, 0x00000100,
 565         0x22ca, 0xffffffff, 0x00000100,
 566         0x2451, 0xffffffff, 0x00000100,
 567         0x2362, 0xffffffff, 0x00000100,
 568         0x2363, 0xffffffff, 0x00000100,
 569         0x240c, 0xffffffff, 0x00000100,
 570         0x240d, 0xffffffff, 0x00000100,
 571         0x240e, 0xffffffff, 0x00000100,
 572         0x240f, 0xffffffff, 0x00000100,
 573         0x2b60, 0xffffffff, 0x00000100,
 574         0x2b15, 0xffffffff, 0x00000100,
 575         0x225f, 0xffffffff, 0x06000100,
 576         0x261a, 0xffffffff, 0x00000100,
 577         0x2544, 0xffffffff, 0x00000100,
 578         0x2bc1, 0xffffffff, 0x00000100,
 579         0x2b81, 0xffffffff, 0x00000100,
 580         0x2527, 0xffffffff, 0x00000100,
 581         0x200b, 0xffffffff, 0xe0000000,
 582         0x2458, 0xffffffff, 0x00010000,
 583         0x2459, 0xffffffff, 0x00030002,
 584         0x245a, 0xffffffff, 0x00040007,
 585         0x245b, 0xffffffff, 0x00060005,
 586         0x245c, 0xffffffff, 0x00090008,
 587         0x245d, 0xffffffff, 0x00020001,
 588         0x245e, 0xffffffff, 0x00040003,
 589         0x245f, 0xffffffff, 0x00000007,
 590         0x2460, 0xffffffff, 0x00060005,
 591         0x2461, 0xffffffff, 0x00090008,
 592         0x2462, 0xffffffff, 0x00030002,
 593         0x2463, 0xffffffff, 0x00050004,
 594         0x2464, 0xffffffff, 0x00000008,
 595         0x2465, 0xffffffff, 0x00070006,
 596         0x2466, 0xffffffff, 0x000a0009,
 597         0x2467, 0xffffffff, 0x00040003,
 598         0x2468, 0xffffffff, 0x00060005,
 599         0x2469, 0xffffffff, 0x00000009,
 600         0x246a, 0xffffffff, 0x00080007,
 601         0x246b, 0xffffffff, 0x000b000a,
 602         0x246c, 0xffffffff, 0x00050004,
 603         0x246d, 0xffffffff, 0x00070006,
 604         0x246e, 0xffffffff, 0x0008000b,
 605         0x246f, 0xffffffff, 0x000a0009,
 606         0x2470, 0xffffffff, 0x000d000c,
 607         0x2480, 0xffffffff, 0x00090008,
 608         0x2481, 0xffffffff, 0x000b000a,
 609         0x2482, 0xffffffff, 0x000c000f,
 610         0x2483, 0xffffffff, 0x000e000d,
 611         0x2484, 0xffffffff, 0x00110010,
 612         0x2485, 0xffffffff, 0x000a0009,
 613         0x2486, 0xffffffff, 0x000c000b,
 614         0x2487, 0xffffffff, 0x0000000f,
 615         0x2488, 0xffffffff, 0x000e000d,
 616         0x2489, 0xffffffff, 0x00110010,
 617         0x248a, 0xffffffff, 0x000b000a,
 618         0x248b, 0xffffffff, 0x000d000c,
 619         0x248c, 0xffffffff, 0x00000010,
 620         0x248d, 0xffffffff, 0x000f000e,
 621         0x248e, 0xffffffff, 0x00120011,
 622         0x248f, 0xffffffff, 0x000c000b,
 623         0x2490, 0xffffffff, 0x000e000d,
 624         0x2491, 0xffffffff, 0x00000011,
 625         0x2492, 0xffffffff, 0x0010000f,
 626         0x2493, 0xffffffff, 0x00130012,
 627         0x2494, 0xffffffff, 0x000d000c,
 628         0x2495, 0xffffffff, 0x000f000e,
 629         0x2496, 0xffffffff, 0x00100013,
 630         0x2497, 0xffffffff, 0x00120011,
 631         0x2498, 0xffffffff, 0x00150014,
 632         0x2454, 0xffffffff, 0x96940200,
 633         0x21c2, 0xffffffff, 0x00900100,
 634         0x311e, 0xffffffff, 0x00000080,
 635         0x3101, 0xffffffff, 0x0020003f,
 636         0x000c, 0xffffffff, 0x0000001c,
 637         0x000d, 0x000f0000, 0x000f0000,
 638         0x0583, 0xffffffff, 0x00000100,
 639         0x0409, 0xffffffff, 0x00000100,
 640         0x040b, 0x00000101, 0x00000000,
 641         0x082a, 0xffffffff, 0x00000104,
 642         0x1579, 0xff000fff, 0x00000100,
 643         0x157a, 0x00000001, 0x00000001,
 644         0x0bd4, 0x00000001, 0x00000001,
 645         0x0c33, 0xc0000fff, 0x00000104,
 646         0x3079, 0x00000001, 0x00000001,
 647         0x3430, 0xfffffff0, 0x00000100,
 648         0x3630, 0xfffffff0, 0x00000100
 649 };
 650 static const u32 verde_mgcg_cgcg_init[] =
 651 {
 652         0x3100, 0xffffffff, 0xfffffffc,
 653         0x200b, 0xffffffff, 0xe0000000,
 654         0x2698, 0xffffffff, 0x00000100,
 655         0x24a9, 0xffffffff, 0x00000100,
 656         0x3059, 0xffffffff, 0x00000100,
 657         0x25dd, 0xffffffff, 0x00000100,
 658         0x2261, 0xffffffff, 0x06000100,
 659         0x2286, 0xffffffff, 0x00000100,
 660         0x24a8, 0xffffffff, 0x00000100,
 661         0x30e0, 0xffffffff, 0x00000100,
 662         0x22ca, 0xffffffff, 0x00000100,
 663         0x2451, 0xffffffff, 0x00000100,
 664         0x2362, 0xffffffff, 0x00000100,
 665         0x2363, 0xffffffff, 0x00000100,
 666         0x240c, 0xffffffff, 0x00000100,
 667         0x240d, 0xffffffff, 0x00000100,
 668         0x240e, 0xffffffff, 0x00000100,
 669         0x240f, 0xffffffff, 0x00000100,
 670         0x2b60, 0xffffffff, 0x00000100,
 671         0x2b15, 0xffffffff, 0x00000100,
 672         0x225f, 0xffffffff, 0x06000100,
 673         0x261a, 0xffffffff, 0x00000100,
 674         0x2544, 0xffffffff, 0x00000100,
 675         0x2bc1, 0xffffffff, 0x00000100,
 676         0x2b81, 0xffffffff, 0x00000100,
 677         0x2527, 0xffffffff, 0x00000100,
 678         0x200b, 0xffffffff, 0xe0000000,
 679         0x2458, 0xffffffff, 0x00010000,
 680         0x2459, 0xffffffff, 0x00030002,
 681         0x245a, 0xffffffff, 0x00040007,
 682         0x245b, 0xffffffff, 0x00060005,
 683         0x245c, 0xffffffff, 0x00090008,
 684         0x245d, 0xffffffff, 0x00020001,
 685         0x245e, 0xffffffff, 0x00040003,
 686         0x245f, 0xffffffff, 0x00000007,
 687         0x2460, 0xffffffff, 0x00060005,
 688         0x2461, 0xffffffff, 0x00090008,
 689         0x2462, 0xffffffff, 0x00030002,
 690         0x2463, 0xffffffff, 0x00050004,
 691         0x2464, 0xffffffff, 0x00000008,
 692         0x2465, 0xffffffff, 0x00070006,
 693         0x2466, 0xffffffff, 0x000a0009,
 694         0x2467, 0xffffffff, 0x00040003,
 695         0x2468, 0xffffffff, 0x00060005,
 696         0x2469, 0xffffffff, 0x00000009,
 697         0x246a, 0xffffffff, 0x00080007,
 698         0x246b, 0xffffffff, 0x000b000a,
 699         0x246c, 0xffffffff, 0x00050004,
 700         0x246d, 0xffffffff, 0x00070006,
 701         0x246e, 0xffffffff, 0x0008000b,
 702         0x246f, 0xffffffff, 0x000a0009,
 703         0x2470, 0xffffffff, 0x000d000c,
 704         0x2480, 0xffffffff, 0x00090008,
 705         0x2481, 0xffffffff, 0x000b000a,
 706         0x2482, 0xffffffff, 0x000c000f,
 707         0x2483, 0xffffffff, 0x000e000d,
 708         0x2484, 0xffffffff, 0x00110010,
 709         0x2485, 0xffffffff, 0x000a0009,
 710         0x2486, 0xffffffff, 0x000c000b,
 711         0x2487, 0xffffffff, 0x0000000f,
 712         0x2488, 0xffffffff, 0x000e000d,
 713         0x2489, 0xffffffff, 0x00110010,
 714         0x248a, 0xffffffff, 0x000b000a,
 715         0x248b, 0xffffffff, 0x000d000c,
 716         0x248c, 0xffffffff, 0x00000010,
 717         0x248d, 0xffffffff, 0x000f000e,
 718         0x248e, 0xffffffff, 0x00120011,
 719         0x248f, 0xffffffff, 0x000c000b,
 720         0x2490, 0xffffffff, 0x000e000d,
 721         0x2491, 0xffffffff, 0x00000011,
 722         0x2492, 0xffffffff, 0x0010000f,
 723         0x2493, 0xffffffff, 0x00130012,
 724         0x2494, 0xffffffff, 0x000d000c,
 725         0x2495, 0xffffffff, 0x000f000e,
 726         0x2496, 0xffffffff, 0x00100013,
 727         0x2497, 0xffffffff, 0x00120011,
 728         0x2498, 0xffffffff, 0x00150014,
 729         0x2454, 0xffffffff, 0x96940200,
 730         0x21c2, 0xffffffff, 0x00900100,
 731         0x311e, 0xffffffff, 0x00000080,
 732         0x3101, 0xffffffff, 0x0020003f,
 733         0xc, 0xffffffff, 0x0000001c,
 734         0xd, 0x000f0000, 0x000f0000,
 735         0x583, 0xffffffff, 0x00000100,
 736         0x409, 0xffffffff, 0x00000100,
 737         0x40b, 0x00000101, 0x00000000,
 738         0x82a, 0xffffffff, 0x00000104,
 739         0x993, 0x000c0000, 0x000c0000,
 740         0x992, 0x000c0000, 0x000c0000,
 741         0x1579, 0xff000fff, 0x00000100,
 742         0x157a, 0x00000001, 0x00000001,
 743         0xbd4, 0x00000001, 0x00000001,
 744         0xc33, 0xc0000fff, 0x00000104,
 745         0x3079, 0x00000001, 0x00000001,
 746         0x3430, 0xfffffff0, 0x00000100,
 747         0x3630, 0xfffffff0, 0x00000100
 748 };
 749 static const u32 oland_mgcg_cgcg_init[] =
 750 {
 751         0x3100, 0xffffffff, 0xfffffffc,
 752         0x200b, 0xffffffff, 0xe0000000,
 753         0x2698, 0xffffffff, 0x00000100,
 754         0x24a9, 0xffffffff, 0x00000100,
 755         0x3059, 0xffffffff, 0x00000100,
 756         0x25dd, 0xffffffff, 0x00000100,
 757         0x2261, 0xffffffff, 0x06000100,
 758         0x2286, 0xffffffff, 0x00000100,
 759         0x24a8, 0xffffffff, 0x00000100,
 760         0x30e0, 0xffffffff, 0x00000100,
 761         0x22ca, 0xffffffff, 0x00000100,
 762         0x2451, 0xffffffff, 0x00000100,
 763         0x2362, 0xffffffff, 0x00000100,
 764         0x2363, 0xffffffff, 0x00000100,
 765         0x240c, 0xffffffff, 0x00000100,
 766         0x240d, 0xffffffff, 0x00000100,
 767         0x240e, 0xffffffff, 0x00000100,
 768         0x240f, 0xffffffff, 0x00000100,
 769         0x2b60, 0xffffffff, 0x00000100,
 770         0x2b15, 0xffffffff, 0x00000100,
 771         0x225f, 0xffffffff, 0x06000100,
 772         0x261a, 0xffffffff, 0x00000100,
 773         0x2544, 0xffffffff, 0x00000100,
 774         0x2bc1, 0xffffffff, 0x00000100,
 775         0x2b81, 0xffffffff, 0x00000100,
 776         0x2527, 0xffffffff, 0x00000100,
 777         0x200b, 0xffffffff, 0xe0000000,
 778         0x2458, 0xffffffff, 0x00010000,
 779         0x2459, 0xffffffff, 0x00030002,
 780         0x245a, 0xffffffff, 0x00040007,
 781         0x245b, 0xffffffff, 0x00060005,
 782         0x245c, 0xffffffff, 0x00090008,
 783         0x245d, 0xffffffff, 0x00020001,
 784         0x245e, 0xffffffff, 0x00040003,
 785         0x245f, 0xffffffff, 0x00000007,
 786         0x2460, 0xffffffff, 0x00060005,
 787         0x2461, 0xffffffff, 0x00090008,
 788         0x2462, 0xffffffff, 0x00030002,
 789         0x2463, 0xffffffff, 0x00050004,
 790         0x2464, 0xffffffff, 0x00000008,
 791         0x2465, 0xffffffff, 0x00070006,
 792         0x2466, 0xffffffff, 0x000a0009,
 793         0x2467, 0xffffffff, 0x00040003,
 794         0x2468, 0xffffffff, 0x00060005,
 795         0x2469, 0xffffffff, 0x00000009,
 796         0x246a, 0xffffffff, 0x00080007,
 797         0x246b, 0xffffffff, 0x000b000a,
 798         0x246c, 0xffffffff, 0x00050004,
 799         0x246d, 0xffffffff, 0x00070006,
 800         0x246e, 0xffffffff, 0x0008000b,
 801         0x246f, 0xffffffff, 0x000a0009,
 802         0x2470, 0xffffffff, 0x000d000c,
 803         0x2471, 0xffffffff, 0x00060005,
 804         0x2472, 0xffffffff, 0x00080007,
 805         0x2473, 0xffffffff, 0x0000000b,
 806         0x2474, 0xffffffff, 0x000a0009,
 807         0x2475, 0xffffffff, 0x000d000c,
 808         0x2454, 0xffffffff, 0x96940200,
 809         0x21c2, 0xffffffff, 0x00900100,
 810         0x311e, 0xffffffff, 0x00000080,
 811         0x3101, 0xffffffff, 0x0020003f,
 812         0xc, 0xffffffff, 0x0000001c,
 813         0xd, 0x000f0000, 0x000f0000,
 814         0x583, 0xffffffff, 0x00000100,
 815         0x409, 0xffffffff, 0x00000100,
 816         0x40b, 0x00000101, 0x00000000,
 817         0x82a, 0xffffffff, 0x00000104,
 818         0x993, 0x000c0000, 0x000c0000,
 819         0x992, 0x000c0000, 0x000c0000,
 820         0x1579, 0xff000fff, 0x00000100,
 821         0x157a, 0x00000001, 0x00000001,
 822         0xbd4, 0x00000001, 0x00000001,
 823         0xc33, 0xc0000fff, 0x00000104,
 824         0x3079, 0x00000001, 0x00000001,
 825         0x3430, 0xfffffff0, 0x00000100,
 826         0x3630, 0xfffffff0, 0x00000100
 827 };
 828 static const u32 hainan_mgcg_cgcg_init[] =
 829 {
 830         0x3100, 0xffffffff, 0xfffffffc,
 831         0x200b, 0xffffffff, 0xe0000000,
 832         0x2698, 0xffffffff, 0x00000100,
 833         0x24a9, 0xffffffff, 0x00000100,
 834         0x3059, 0xffffffff, 0x00000100,
 835         0x25dd, 0xffffffff, 0x00000100,
 836         0x2261, 0xffffffff, 0x06000100,
 837         0x2286, 0xffffffff, 0x00000100,
 838         0x24a8, 0xffffffff, 0x00000100,
 839         0x30e0, 0xffffffff, 0x00000100,
 840         0x22ca, 0xffffffff, 0x00000100,
 841         0x2451, 0xffffffff, 0x00000100,
 842         0x2362, 0xffffffff, 0x00000100,
 843         0x2363, 0xffffffff, 0x00000100,
 844         0x240c, 0xffffffff, 0x00000100,
 845         0x240d, 0xffffffff, 0x00000100,
 846         0x240e, 0xffffffff, 0x00000100,
 847         0x240f, 0xffffffff, 0x00000100,
 848         0x2b60, 0xffffffff, 0x00000100,
 849         0x2b15, 0xffffffff, 0x00000100,
 850         0x225f, 0xffffffff, 0x06000100,
 851         0x261a, 0xffffffff, 0x00000100,
 852         0x2544, 0xffffffff, 0x00000100,
 853         0x2bc1, 0xffffffff, 0x00000100,
 854         0x2b81, 0xffffffff, 0x00000100,
 855         0x2527, 0xffffffff, 0x00000100,
 856         0x200b, 0xffffffff, 0xe0000000,
 857         0x2458, 0xffffffff, 0x00010000,
 858         0x2459, 0xffffffff, 0x00030002,
 859         0x245a, 0xffffffff, 0x00040007,
 860         0x245b, 0xffffffff, 0x00060005,
 861         0x245c, 0xffffffff, 0x00090008,
 862         0x245d, 0xffffffff, 0x00020001,
 863         0x245e, 0xffffffff, 0x00040003,
 864         0x245f, 0xffffffff, 0x00000007,
 865         0x2460, 0xffffffff, 0x00060005,
 866         0x2461, 0xffffffff, 0x00090008,
 867         0x2462, 0xffffffff, 0x00030002,
 868         0x2463, 0xffffffff, 0x00050004,
 869         0x2464, 0xffffffff, 0x00000008,
 870         0x2465, 0xffffffff, 0x00070006,
 871         0x2466, 0xffffffff, 0x000a0009,
 872         0x2467, 0xffffffff, 0x00040003,
 873         0x2468, 0xffffffff, 0x00060005,
 874         0x2469, 0xffffffff, 0x00000009,
 875         0x246a, 0xffffffff, 0x00080007,
 876         0x246b, 0xffffffff, 0x000b000a,
 877         0x246c, 0xffffffff, 0x00050004,
 878         0x246d, 0xffffffff, 0x00070006,
 879         0x246e, 0xffffffff, 0x0008000b,
 880         0x246f, 0xffffffff, 0x000a0009,
 881         0x2470, 0xffffffff, 0x000d000c,
 882         0x2471, 0xffffffff, 0x00060005,
 883         0x2472, 0xffffffff, 0x00080007,
 884         0x2473, 0xffffffff, 0x0000000b,
 885         0x2474, 0xffffffff, 0x000a0009,
 886         0x2475, 0xffffffff, 0x000d000c,
 887         0x2454, 0xffffffff, 0x96940200,
 888         0x21c2, 0xffffffff, 0x00900100,
 889         0x311e, 0xffffffff, 0x00000080,
 890         0x3101, 0xffffffff, 0x0020003f,
 891         0x000c, 0xffffffff, 0x0000001c,
 892         0x000d, 0x000f0000, 0x000f0000,
 893         0x0583, 0xffffffff, 0x00000100,
 894         0x0409, 0xffffffff, 0x00000100,
 895         0x082a, 0xffffffff, 0x00000104,
 896         0x0993, 0x000c0000, 0x000c0000,
 897         0x0992, 0x000c0000, 0x000c0000,
 898         0x0bd4, 0x00000001, 0x00000001,
 899         0x0c33, 0xc0000fff, 0x00000104,
 900         0x3079, 0x00000001, 0x00000001,
 901         0x3430, 0xfffffff0, 0x00000100,
 902         0x3630, 0xfffffff0, 0x00000100
 903 };
 904
 905 static u32 si_pcie_rreg(struct amdgpu_device *adev, u32 reg)
 906 {
 907         unsigned long flags;
 908         u32 r;
 909
 910         spin_lock_irqsave(&adev->pcie_idx_lock, flags);
 911         WREG32(AMDGPU_PCIE_INDEX, reg);
 912         (void)RREG32(AMDGPU_PCIE_INDEX);
 913         r = RREG32(AMDGPU_PCIE_DATA);
 914         spin_unlock_irqrestore(&adev->pcie_idx_lock, flags);
 915         return r;
 916 }
 917
 918 static void si_pcie_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
 919 {
 920         unsigned long flags;
 921
 922         spin_lock_irqsave(&adev->pcie_idx_lock, flags);
 923         WREG32(AMDGPU_PCIE_INDEX, reg);
 924         (void)RREG32(AMDGPU_PCIE_INDEX);
 925         WREG32(AMDGPU_PCIE_DATA, v);
 926         (void)RREG32(AMDGPU_PCIE_DATA);
 927         spin_unlock_irqrestore(&adev->pcie_idx_lock, flags);
 928 }
 929
 930 static u32 si_pciep_rreg(struct amdgpu_device *adev, u32 reg)
 931 {
 932         unsigned long flags;
 933         u32 r;
 934
 935         spin_lock_irqsave(&adev->pcie_idx_lock, flags);
 936         WREG32(PCIE_PORT_INDEX, ((reg) & 0xff));
 937         (void)RREG32(PCIE_PORT_INDEX);
 938         r = RREG32(PCIE_PORT_DATA);
 939         spin_unlock_irqrestore(&adev->pcie_idx_lock, flags);
 940         return r;
 941 }
 942
 943 static void si_pciep_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
 944 {
 945         unsigned long flags;
 946
 947         spin_lock_irqsave(&adev->pcie_idx_lock, flags);
 948         WREG32(PCIE_PORT_INDEX, ((reg) & 0xff));
 949         (void)RREG32(PCIE_PORT_INDEX);
 950         WREG32(PCIE_PORT_DATA, (v));
 951         (void)RREG32(PCIE_PORT_DATA);
 952         spin_unlock_irqrestore(&adev->pcie_idx_lock, flags);
 953 }
 954
 955 static u32 si_smc_rreg(struct amdgpu_device *adev, u32 reg)
 956 {
 957         unsigned long flags;
 958         u32 r;
 959
 960         spin_lock_irqsave(&adev->smc_idx_lock, flags);
 961         WREG32(SMC_IND_INDEX_0, (reg));
 962         r = RREG32(SMC_IND_DATA_0);
 963         spin_unlock_irqrestore(&adev->smc_idx_lock, flags);
 964         return r;
 965 }
 966
 967 static void si_smc_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
 968 {
 969         unsigned long flags;
 970
 971         spin_lock_irqsave(&adev->smc_idx_lock, flags);
 972         WREG32(SMC_IND_INDEX_0, (reg));
 973         WREG32(SMC_IND_DATA_0, (v));
 974         spin_unlock_irqrestore(&adev->smc_idx_lock, flags);
 975 }
 976
 977 static struct amdgpu_allowed_register_entry si_allowed_read_registers[] = {
 978         {GRBM_STATUS, false},
 979         {GB_ADDR_CONFIG, false},
 980         {MC_ARB_RAMCFG, false},
 981         {GB_TILE_MODE0, false},
 982         {GB_TILE_MODE1, false},
 983         {GB_TILE_MODE2, false},
 984         {GB_TILE_MODE3, false},
 985         {GB_TILE_MODE4, false},
 986         {GB_TILE_MODE5, false},
 987         {GB_TILE_MODE6, false},
 988         {GB_TILE_MODE7, false},
 989         {GB_TILE_MODE8, false},
 990         {GB_TILE_MODE9, false},
 991         {GB_TILE_MODE10, false},
 992         {GB_TILE_MODE11, false},
 993         {GB_TILE_MODE12, false},
 994         {GB_TILE_MODE13, false},
 995         {GB_TILE_MODE14, false},
 996         {GB_TILE_MODE15, false},
 997         {GB_TILE_MODE16, false},
 998         {GB_TILE_MODE17, false},
 999         {GB_TILE_MODE18, false},
1000         {GB_TILE_MODE19, false},
1001         {GB_TILE_MODE20, false},
1002         {GB_TILE_MODE21, false},
1003         {GB_TILE_MODE22, false},
1004         {GB_TILE_MODE23, false},
1005         {GB_TILE_MODE24, false},
1006         {GB_TILE_MODE25, false},
1007         {GB_TILE_MODE26, false},
1008         {GB_TILE_MODE27, false},
1009         {GB_TILE_MODE28, false},
1010         {GB_TILE_MODE29, false},
1011         {GB_TILE_MODE30, false},
1012         {GB_TILE_MODE31, false},
1013         {CC_RB_BACKEND_DISABLE, false, true},
1014         {GC_USER_RB_BACKEND_DISABLE, false, true},
1015         {PA_SC_RASTER_CONFIG, false, true},
1016 };
1017
1018 static uint32_t si_read_indexed_register(struct amdgpu_device *adev,
1019                                           u32 se_num, u32 sh_num,
1020                                           u32 reg_offset)
1021 {
1022         uint32_t val;
1023
1024         mutex_lock(&adev->grbm_idx_mutex);
1025         if (se_num != 0xffffffff || sh_num != 0xffffffff)
1026                 amdgpu_gfx_select_se_sh(adev, se_num, sh_num, 0xffffffff);
1027
1028         val = RREG32(reg_offset);
1029
1030         if (se_num != 0xffffffff || sh_num != 0xffffffff)
1031                 amdgpu_gfx_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
1032         mutex_unlock(&adev->grbm_idx_mutex);
1033         return val;
1034 }
1035
1036 static int si_read_register(struct amdgpu_device *adev, u32 se_num,
1037                              u32 sh_num, u32 reg_offset, u32 *value)
1038 {
1039         uint32_t i;
1040
1041         *value = 0;
1042         for (i = 0; i < ARRAY_SIZE(si_allowed_read_registers); i++) {
1043                 if (reg_offset != si_allowed_read_registers[i].reg_offset)
1044                         continue;
1045
1046                 if (!si_allowed_read_registers[i].untouched)
1047                         *value = si_allowed_read_registers[i].grbm_indexed ?
1048                                  si_read_indexed_register(adev, se_num,
1049                                                            sh_num, reg_offset) :
1050                                  RREG32(reg_offset);
1051                 return 0;
1052         }
1053         return -EINVAL;
1054 }
1055
1056 static bool si_read_disabled_bios(struct amdgpu_device *adev)
1057 {
1058         u32 bus_cntl;
1059         u32 d1vga_control = 0;
1060         u32 d2vga_control = 0;
1061         u32 vga_render_control = 0;
1062         u32 rom_cntl;
1063         bool r;
1064
1065         bus_cntl = RREG32(R600_BUS_CNTL);
1066         if (adev->mode_info.num_crtc) {
1067                 d1vga_control = RREG32(AVIVO_D1VGA_CONTROL);
1068                 d2vga_control = RREG32(AVIVO_D2VGA_CONTROL);
1069                 vga_render_control = RREG32(VGA_RENDER_CONTROL);
1070         }
1071         rom_cntl = RREG32(R600_ROM_CNTL);
1072
1073         /* enable the rom */
1074         WREG32(R600_BUS_CNTL, (bus_cntl & ~R600_BIOS_ROM_DIS));
1075         if (adev->mode_info.num_crtc) {
1076                 /* Disable VGA mode */
1077                 WREG32(AVIVO_D1VGA_CONTROL,
1078                        (d1vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE |
1079                                           AVIVO_DVGA_CONTROL_TIMING_SELECT)));
1080                 WREG32(AVIVO_D2VGA_CONTROL,
1081                        (d2vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE |
1082                                           AVIVO_DVGA_CONTROL_TIMING_SELECT)));
1083                 WREG32(VGA_RENDER_CONTROL,
1084                        (vga_render_control & C_000300_VGA_VSTATUS_CNTL));
1085         }
1086         WREG32(R600_ROM_CNTL, rom_cntl | R600_SCK_OVERWRITE);
1087
1088         r = amdgpu_read_bios(adev);
1089
1090         /* restore regs */
1091         WREG32(R600_BUS_CNTL, bus_cntl);
1092         if (adev->mode_info.num_crtc) {
1093                 WREG32(AVIVO_D1VGA_CONTROL, d1vga_control);
1094                 WREG32(AVIVO_D2VGA_CONTROL, d2vga_control);
1095                 WREG32(VGA_RENDER_CONTROL, vga_render_control);
1096         }
1097         WREG32(R600_ROM_CNTL, rom_cntl);
1098         return r;
1099 }
1100
1101 //xxx: not implemented
1102 static int si_asic_reset(struct amdgpu_device *adev)
1103 {
1104         return 0;
1105 }
1106
1107 static void si_vga_set_state(struct amdgpu_device *adev, bool state)
1108 {
1109         uint32_t temp;
1110
1111         temp = RREG32(CONFIG_CNTL);
1112         if (state == false) {
1113                 temp &= ~(1<<0);
1114                 temp |= (1<<1);
1115         } else {
1116                 temp &= ~(1<<1);
1117         }
1118         WREG32(CONFIG_CNTL, temp);
1119 }
1120
1121 static u32 si_get_xclk(struct amdgpu_device *adev)
1122 {
1123         u32 reference_clock = adev->clock.spll.reference_freq;
1124         u32 tmp;
1125
1126         tmp = RREG32(CG_CLKPIN_CNTL_2);
1127         if (tmp & MUX_TCLK_TO_XCLK)
1128                 return TCLK;
1129
1130         tmp = RREG32(CG_CLKPIN_CNTL);
1131         if (tmp & XTALIN_DIVIDE)
1132                 return reference_clock / 4;
1133
1134         return reference_clock;
1135 }
1136
1137 //xxx:not implemented
1138 static int si_set_uvd_clocks(struct amdgpu_device *adev, u32 vclk, u32 dclk)
1139 {
1140         return 0;
1141 }
1142
1143 static void si_detect_hw_virtualization(struct amdgpu_device *adev)
1144 {
1145         if (is_virtual_machine()) /* passthrough mode */
1146                 adev->virtualization.virtual_caps |= AMDGPU_PASSTHROUGH_MODE;
1147 }
1148
1149 static const struct amdgpu_asic_funcs si_asic_funcs =
1150 {
1151         .read_disabled_bios = &si_read_disabled_bios,
1152         .detect_hw_virtualization = si_detect_hw_virtualization,
1153         .read_register = &si_read_register,
1154         .reset = &si_asic_reset,
1155         .set_vga_state = &si_vga_set_state,
1156         .get_xclk = &si_get_xclk,
1157         .set_uvd_clocks = &si_set_uvd_clocks,
1158         .set_vce_clocks = NULL,
1159 };
1160
1161 static uint32_t si_get_rev_id(struct amdgpu_device *adev)
1162 {
1163         return (RREG32(CC_DRM_ID_STRAPS) & CC_DRM_ID_STRAPS__ATI_REV_ID_MASK)
1164                 >> CC_DRM_ID_STRAPS__ATI_REV_ID__SHIFT;
1165 }
1166
1167 static int si_common_early_init(void *handle)
1168 {
1169         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1170
1171         adev->smc_rreg = &si_smc_rreg;
1172         adev->smc_wreg = &si_smc_wreg;
1173         adev->pcie_rreg = &si_pcie_rreg;
1174         adev->pcie_wreg = &si_pcie_wreg;
1175         adev->pciep_rreg = &si_pciep_rreg;
1176         adev->pciep_wreg = &si_pciep_wreg;
1177         adev->uvd_ctx_rreg = NULL;
1178         adev->uvd_ctx_wreg = NULL;
1179         adev->didt_rreg = NULL;
1180         adev->didt_wreg = NULL;
1181
1182         adev->asic_funcs = &si_asic_funcs;
1183
1184         adev->rev_id = si_get_rev_id(adev);
1185         adev->external_rev_id = 0xFF;
1186         switch (adev->asic_type) {
1187         case CHIP_TAHITI:
1188                 adev->cg_flags =
1189                         AMD_CG_SUPPORT_GFX_MGCG |
1190                         AMD_CG_SUPPORT_GFX_MGLS |
1191                         /*AMD_CG_SUPPORT_GFX_CGCG |*/
1192                         AMD_CG_SUPPORT_GFX_CGLS |
1193                         AMD_CG_SUPPORT_GFX_CGTS |
1194                         AMD_CG_SUPPORT_GFX_CP_LS |
1195                         AMD_CG_SUPPORT_MC_MGCG |
1196                         AMD_CG_SUPPORT_SDMA_MGCG |
1197                         AMD_CG_SUPPORT_BIF_LS |
1198                         AMD_CG_SUPPORT_VCE_MGCG |
1199                         AMD_CG_SUPPORT_UVD_MGCG |
1200                         AMD_CG_SUPPORT_HDP_LS |
1201                         AMD_CG_SUPPORT_HDP_MGCG;
1202                         adev->pg_flags = 0;
1203                 adev->external_rev_id = (adev->rev_id == 0) ? 1 :
1204                                         (adev->rev_id == 1) ? 5 : 6;
1205                 break;
1206         case CHIP_PITCAIRN:
1207                 adev->cg_flags =
1208                         AMD_CG_SUPPORT_GFX_MGCG |
1209                         AMD_CG_SUPPORT_GFX_MGLS |
1210                         /*AMD_CG_SUPPORT_GFX_CGCG |*/
1211                         AMD_CG_SUPPORT_GFX_CGLS |
1212                         AMD_CG_SUPPORT_GFX_CGTS |
1213                         AMD_CG_SUPPORT_GFX_CP_LS |
1214                         AMD_CG_SUPPORT_GFX_RLC_LS |
1215                         AMD_CG_SUPPORT_MC_LS |
1216                         AMD_CG_SUPPORT_MC_MGCG |
1217                         AMD_CG_SUPPORT_SDMA_MGCG |
1218                         AMD_CG_SUPPORT_BIF_LS |
1219                         AMD_CG_SUPPORT_VCE_MGCG |
1220                         AMD_CG_SUPPORT_UVD_MGCG |
1221                         AMD_CG_SUPPORT_HDP_LS |
1222                         AMD_CG_SUPPORT_HDP_MGCG;
1223                 adev->pg_flags = 0;
1224                 adev->external_rev_id = adev->rev_id + 20;
1225                 break;
1226
1227         case CHIP_VERDE:
1228                 adev->cg_flags =
1229                         AMD_CG_SUPPORT_GFX_MGCG |
1230                         AMD_CG_SUPPORT_GFX_MGLS |
1231                         AMD_CG_SUPPORT_GFX_CGLS |
1232                         AMD_CG_SUPPORT_GFX_CGTS |
1233                         AMD_CG_SUPPORT_GFX_CGTS_LS |
1234                         AMD_CG_SUPPORT_GFX_CP_LS |
1235                         AMD_CG_SUPPORT_MC_LS |
1236                         AMD_CG_SUPPORT_MC_MGCG |
1237                         AMD_CG_SUPPORT_SDMA_MGCG |
1238                         AMD_CG_SUPPORT_SDMA_LS |
1239                         AMD_CG_SUPPORT_BIF_LS |
1240                         AMD_CG_SUPPORT_VCE_MGCG |
1241                         AMD_CG_SUPPORT_UVD_MGCG |
1242                         AMD_CG_SUPPORT_HDP_LS |
1243                         AMD_CG_SUPPORT_HDP_MGCG;
1244                 adev->pg_flags = 0;
1245                 //???
1246                 adev->external_rev_id = adev->rev_id + 0x14;
1247                 break;
1248         case CHIP_OLAND:
1249                 adev->cg_flags =
1250                         AMD_CG_SUPPORT_GFX_MGCG |
1251                         AMD_CG_SUPPORT_GFX_MGLS |
1252                         /*AMD_CG_SUPPORT_GFX_CGCG |*/
1253                         AMD_CG_SUPPORT_GFX_CGLS |
1254                         AMD_CG_SUPPORT_GFX_CGTS |
1255                         AMD_CG_SUPPORT_GFX_CP_LS |
1256                         AMD_CG_SUPPORT_GFX_RLC_LS |
1257                         AMD_CG_SUPPORT_MC_LS |
1258                         AMD_CG_SUPPORT_MC_MGCG |
1259                         AMD_CG_SUPPORT_SDMA_MGCG |
1260                         AMD_CG_SUPPORT_BIF_LS |
1261                         AMD_CG_SUPPORT_UVD_MGCG |
1262                         AMD_CG_SUPPORT_HDP_LS |
1263                         AMD_CG_SUPPORT_HDP_MGCG;
1264                 adev->pg_flags = 0;
1265                 break;
1266         case CHIP_HAINAN:
1267                 adev->cg_flags =
1268                         AMD_CG_SUPPORT_GFX_MGCG |
1269                         AMD_CG_SUPPORT_GFX_MGLS |
1270                         /*AMD_CG_SUPPORT_GFX_CGCG |*/
1271                         AMD_CG_SUPPORT_GFX_CGLS |
1272                         AMD_CG_SUPPORT_GFX_CGTS |
1273                         AMD_CG_SUPPORT_GFX_CP_LS |
1274                         AMD_CG_SUPPORT_GFX_RLC_LS |
1275                         AMD_CG_SUPPORT_MC_LS |
1276                         AMD_CG_SUPPORT_MC_MGCG |
1277                         AMD_CG_SUPPORT_SDMA_MGCG |
1278                         AMD_CG_SUPPORT_BIF_LS |
1279                         AMD_CG_SUPPORT_HDP_LS |
1280                         AMD_CG_SUPPORT_HDP_MGCG;
1281                 adev->pg_flags = 0;
1282                 break;
1283
1284         default:
1285                 return -EINVAL;
1286         }
1287
1288         return 0;
1289 }
1290
1291 static int si_common_sw_init(void *handle)
1292 {
1293         return 0;
1294 }
1295
1296 static int si_common_sw_fini(void *handle)
1297 {
1298         return 0;
1299 }
1300
1301
1302 static void si_init_golden_registers(struct amdgpu_device *adev)
1303 {
1304         switch (adev->asic_type) {
1305         case CHIP_TAHITI:
1306                 amdgpu_program_register_sequence(adev,
1307                                                  tahiti_golden_registers,
1308                                                  (const u32)ARRAY_SIZE(tahiti_golden_registers));
1309                 amdgpu_program_register_sequence(adev,
1310                                                  tahiti_golden_rlc_registers,
1311                                                  (const u32)ARRAY_SIZE(tahiti_golden_rlc_registers));
1312                 amdgpu_program_register_sequence(adev,
1313                                                  tahiti_mgcg_cgcg_init,
1314                                                  (const u32)ARRAY_SIZE(tahiti_mgcg_cgcg_init));
1315                 amdgpu_program_register_sequence(adev,
1316                                                  tahiti_golden_registers2,
1317                                                  (const u32)ARRAY_SIZE(tahiti_golden_registers2));
1318                 break;
1319         case CHIP_PITCAIRN:
1320                 amdgpu_program_register_sequence(adev,
1321                                                  pitcairn_golden_registers,
1322                                                  (const u32)ARRAY_SIZE(pitcairn_golden_registers));
1323                 amdgpu_program_register_sequence(adev,
1324                                                  pitcairn_golden_rlc_registers,
1325                                                  (const u32)ARRAY_SIZE(pitcairn_golden_rlc_registers));
1326                 amdgpu_program_register_sequence(adev,
1327                                                  pitcairn_mgcg_cgcg_init,
1328                                                  (const u32)ARRAY_SIZE(pitcairn_mgcg_cgcg_init));
1329         case CHIP_VERDE:
1330                 amdgpu_program_register_sequence(adev,
1331                                                  verde_golden_registers,
1332                                                  (const u32)ARRAY_SIZE(verde_golden_registers));
1333                 amdgpu_program_register_sequence(adev,
1334                                                  verde_golden_rlc_registers,
1335                                                  (const u32)ARRAY_SIZE(verde_golden_rlc_registers));
1336                 amdgpu_program_register_sequence(adev,
1337                                                  verde_mgcg_cgcg_init,
1338                                                  (const u32)ARRAY_SIZE(verde_mgcg_cgcg_init));
1339                 amdgpu_program_register_sequence(adev,
1340                                                  verde_pg_init,
1341                                                  (const u32)ARRAY_SIZE(verde_pg_init));
1342                 break;
1343         case CHIP_OLAND:
1344                 amdgpu_program_register_sequence(adev,
1345                                                  oland_golden_registers,
1346                                                  (const u32)ARRAY_SIZE(oland_golden_registers));
1347                 amdgpu_program_register_sequence(adev,
1348                                                  oland_golden_rlc_registers,
1349                                                  (const u32)ARRAY_SIZE(oland_golden_rlc_registers));
1350                 amdgpu_program_register_sequence(adev,
1351                                                  oland_mgcg_cgcg_init,
1352                                                  (const u32)ARRAY_SIZE(oland_mgcg_cgcg_init));
1353         case CHIP_HAINAN:
1354                 amdgpu_program_register_sequence(adev,
1355                                                  hainan_golden_registers,
1356                                                  (const u32)ARRAY_SIZE(hainan_golden_registers));
1357                 amdgpu_program_register_sequence(adev,
1358                                                  hainan_golden_registers2,
1359                                                  (const u32)ARRAY_SIZE(hainan_golden_registers2));
1360                 amdgpu_program_register_sequence(adev,
1361                                                  hainan_mgcg_cgcg_init,
1362                                                  (const u32)ARRAY_SIZE(hainan_mgcg_cgcg_init));
1363                 break;
1364
1365
1366         default:
1367                 BUG();
1368         }
1369 }
1370
1371 static void si_pcie_gen3_enable(struct amdgpu_device *adev)
1372 {
1373         struct pci_dev *root = adev->pdev->bus->self;
1374         int bridge_pos, gpu_pos;
1375         u32 speed_cntl, mask, current_data_rate;
1376         int ret, i;
1377         u16 tmp16;
1378
1379         if (pci_is_root_bus(adev->pdev->bus))
1380                 return;
1381
1382         if (amdgpu_pcie_gen2 == 0)
1383                 return;
1384
1385         if (adev->flags & AMD_IS_APU)
1386                 return;
1387
1388         ret = drm_pcie_get_speed_cap_mask(adev->ddev, &mask);
1389         if (ret != 0)
1390                 return;
1391
1392         if (!(mask & (DRM_PCIE_SPEED_50 | DRM_PCIE_SPEED_80)))
1393                 return;
1394
1395         speed_cntl = RREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL);
1396         current_data_rate = (speed_cntl & LC_CURRENT_DATA_RATE_MASK) >>
1397                 LC_CURRENT_DATA_RATE_SHIFT;
1398         if (mask & DRM_PCIE_SPEED_80) {
1399                 if (current_data_rate == 2) {
1400                         DRM_INFO("PCIE gen 3 link speeds already enabled\n");
1401                         return;
1402                 }
1403                 DRM_INFO("enabling PCIE gen 3 link speeds, disable with amdgpu.pcie_gen2=0\n");
1404         } else if (mask & DRM_PCIE_SPEED_50) {
1405                 if (current_data_rate == 1) {
1406                         DRM_INFO("PCIE gen 2 link speeds already enabled\n");
1407                         return;
1408                 }
1409                 DRM_INFO("enabling PCIE gen 2 link speeds, disable with amdgpu.pcie_gen2=0\n");
1410         }
1411
1412         bridge_pos = pci_pcie_cap(root);
1413         if (!bridge_pos)
1414                 return;
1415
1416         gpu_pos = pci_pcie_cap(adev->pdev);
1417         if (!gpu_pos)
1418                 return;
1419
1420         if (mask & DRM_PCIE_SPEED_80) {
1421                 if (current_data_rate != 2) {
1422                         u16 bridge_cfg, gpu_cfg;
1423                         u16 bridge_cfg2, gpu_cfg2;
1424                         u32 max_lw, current_lw, tmp;
1425
1426                         pci_read_config_word(root, bridge_pos + PCI_EXP_LNKCTL, &bridge_cfg);
1427                         pci_read_config_word(adev->pdev, gpu_pos + PCI_EXP_LNKCTL, &gpu_cfg);
1428
1429                         tmp16 = bridge_cfg | PCI_EXP_LNKCTL_HAWD;
1430                         pci_write_config_word(root, bridge_pos + PCI_EXP_LNKCTL, tmp16);
1431
1432                         tmp16 = gpu_cfg | PCI_EXP_LNKCTL_HAWD;
1433                         pci_write_config_word(adev->pdev, gpu_pos + PCI_EXP_LNKCTL, tmp16);
1434
1435                         tmp = RREG32_PCIE(PCIE_LC_STATUS1);
1436                         max_lw = (tmp & LC_DETECTED_LINK_WIDTH_MASK) >> LC_DETECTED_LINK_WIDTH_SHIFT;
1437                         current_lw = (tmp & LC_OPERATING_LINK_WIDTH_MASK) >> LC_OPERATING_LINK_WIDTH_SHIFT;
1438
1439                         if (current_lw < max_lw) {
1440                                 tmp = RREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL);
1441                                 if (tmp & LC_RENEGOTIATION_SUPPORT) {
1442                                         tmp &= ~(LC_LINK_WIDTH_MASK | LC_UPCONFIGURE_DIS);
1443                                         tmp |= (max_lw << LC_LINK_WIDTH_SHIFT);
1444                                         tmp |= LC_UPCONFIGURE_SUPPORT | LC_RENEGOTIATE_EN | LC_RECONFIG_NOW;
1445                                         WREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL, tmp);
1446                                 }
1447                         }
1448
1449                         for (i = 0; i < 10; i++) {
1450                                 pci_read_config_word(adev->pdev, gpu_pos + PCI_EXP_DEVSTA, &tmp16);
1451                                 if (tmp16 & PCI_EXP_DEVSTA_TRPND)
1452                                         break;
1453
1454                                 pci_read_config_word(root, bridge_pos + PCI_EXP_LNKCTL, &bridge_cfg);
1455                                 pci_read_config_word(adev->pdev, gpu_pos + PCI_EXP_LNKCTL, &gpu_cfg);
1456
1457                                 pci_read_config_word(root, bridge_pos + PCI_EXP_LNKCTL2, &bridge_cfg2);
1458                                 pci_read_config_word(adev->pdev, gpu_pos + PCI_EXP_LNKCTL2, &gpu_cfg2);
1459
1460                                 tmp = RREG32_PCIE_PORT(PCIE_LC_CNTL4);
1461                                 tmp |= LC_SET_QUIESCE;
1462                                 WREG32_PCIE_PORT(PCIE_LC_CNTL4, tmp);
1463
1464                                 tmp = RREG32_PCIE_PORT(PCIE_LC_CNTL4);
1465                                 tmp |= LC_REDO_EQ;
1466                                 WREG32_PCIE_PORT(PCIE_LC_CNTL4, tmp);
1467
1468                                 mdelay(100);
1469
1470                                 pci_read_config_word(root, bridge_pos + PCI_EXP_LNKCTL, &tmp16);
1471                                 tmp16 &= ~PCI_EXP_LNKCTL_HAWD;
1472                                 tmp16 |= (bridge_cfg & PCI_EXP_LNKCTL_HAWD);
1473                                 pci_write_config_word(root, bridge_pos + PCI_EXP_LNKCTL, tmp16);
1474
1475                                 pci_read_config_word(adev->pdev, gpu_pos + PCI_EXP_LNKCTL, &tmp16);
1476                                 tmp16 &= ~PCI_EXP_LNKCTL_HAWD;
1477                                 tmp16 |= (gpu_cfg & PCI_EXP_LNKCTL_HAWD);
1478                                 pci_write_config_word(adev->pdev, gpu_pos + PCI_EXP_LNKCTL, tmp16);
1479
1480                                 pci_read_config_word(root, bridge_pos + PCI_EXP_LNKCTL2, &tmp16);
1481                                 tmp16 &= ~((1 << 4) | (7 << 9));
1482                                 tmp16 |= (bridge_cfg2 & ((1 << 4) | (7 << 9)));
1483                                 pci_write_config_word(root, bridge_pos + PCI_EXP_LNKCTL2, tmp16);
1484
1485                                 pci_read_config_word(adev->pdev, gpu_pos + PCI_EXP_LNKCTL2, &tmp16);
1486                                 tmp16 &= ~((1 << 4) | (7 << 9));
1487                                 tmp16 |= (gpu_cfg2 & ((1 << 4) | (7 << 9)));
1488                                 pci_write_config_word(adev->pdev, gpu_pos + PCI_EXP_LNKCTL2, tmp16);
1489
1490                                 tmp = RREG32_PCIE_PORT(PCIE_LC_CNTL4);
1491                                 tmp &= ~LC_SET_QUIESCE;
1492                                 WREG32_PCIE_PORT(PCIE_LC_CNTL4, tmp);
1493                         }
1494                 }
1495         }
1496
1497         speed_cntl |= LC_FORCE_EN_SW_SPEED_CHANGE | LC_FORCE_DIS_HW_SPEED_CHANGE;
1498         speed_cntl &= ~LC_FORCE_DIS_SW_SPEED_CHANGE;
1499         WREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL, speed_cntl);
1500
1501         pci_read_config_word(adev->pdev, gpu_pos + PCI_EXP_LNKCTL2, &tmp16);
1502         tmp16 &= ~0xf;
1503         if (mask & DRM_PCIE_SPEED_80)
1504                 tmp16 |= 3;
1505         else if (mask & DRM_PCIE_SPEED_50)
1506                 tmp16 |= 2;
1507         else
1508                 tmp16 |= 1;
1509         pci_write_config_word(adev->pdev, gpu_pos + PCI_EXP_LNKCTL2, tmp16);
1510
1511         speed_cntl = RREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL);
1512         speed_cntl |= LC_INITIATE_LINK_SPEED_CHANGE;
1513         WREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL, speed_cntl);
1514
1515         for (i = 0; i < adev->usec_timeout; i++) {
1516                 speed_cntl = RREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL);
1517                 if ((speed_cntl & LC_INITIATE_LINK_SPEED_CHANGE) == 0)
1518                         break;
1519                 udelay(1);
1520         }
1521 }
1522
1523 static inline u32 si_pif_phy0_rreg(struct amdgpu_device *adev, u32 reg)
1524 {
1525         unsigned long flags;
1526         u32 r;
1527
1528         spin_lock_irqsave(&adev->pcie_idx_lock, flags);
1529         WREG32(EVERGREEN_PIF_PHY0_INDEX, ((reg) & 0xffff));
1530         r = RREG32(EVERGREEN_PIF_PHY0_DATA);
1531         spin_unlock_irqrestore(&adev->pcie_idx_lock, flags);
1532         return r;
1533 }
1534
1535 static inline void si_pif_phy0_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
1536 {
1537         unsigned long flags;
1538
1539         spin_lock_irqsave(&adev->pcie_idx_lock, flags);
1540         WREG32(EVERGREEN_PIF_PHY0_INDEX, ((reg) & 0xffff));
1541         WREG32(EVERGREEN_PIF_PHY0_DATA, (v));
1542         spin_unlock_irqrestore(&adev->pcie_idx_lock, flags);
1543 }
1544
1545 static inline u32 si_pif_phy1_rreg(struct amdgpu_device *adev, u32 reg)
1546 {
1547         unsigned long flags;
1548         u32 r;
1549
1550         spin_lock_irqsave(&adev->pcie_idx_lock, flags);
1551         WREG32(EVERGREEN_PIF_PHY1_INDEX, ((reg) & 0xffff));
1552         r = RREG32(EVERGREEN_PIF_PHY1_DATA);
1553         spin_unlock_irqrestore(&adev->pcie_idx_lock, flags);
1554         return r;
1555 }
1556
1557 static inline void si_pif_phy1_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
1558 {
1559         unsigned long flags;
1560
1561         spin_lock_irqsave(&adev->pcie_idx_lock, flags);
1562         WREG32(EVERGREEN_PIF_PHY1_INDEX, ((reg) & 0xffff));
1563         WREG32(EVERGREEN_PIF_PHY1_DATA, (v));
1564         spin_unlock_irqrestore(&adev->pcie_idx_lock, flags);
1565 }
1566 static void si_program_aspm(struct amdgpu_device *adev)
1567 {
1568         u32 data, orig;
1569         bool disable_l0s = false, disable_l1 = false, disable_plloff_in_l1 = false;
1570         bool disable_clkreq = false;
1571
1572         if (amdgpu_aspm == 0)
1573                 return;
1574
1575         if (adev->flags & AMD_IS_APU)
1576                 return;
1577         orig = data = RREG32_PCIE_PORT(PCIE_LC_N_FTS_CNTL);
1578         data &= ~LC_XMIT_N_FTS_MASK;
1579         data |= LC_XMIT_N_FTS(0x24) | LC_XMIT_N_FTS_OVERRIDE_EN;
1580         if (orig != data)
1581                 WREG32_PCIE_PORT(PCIE_LC_N_FTS_CNTL, data);
1582
1583         orig = data = RREG32_PCIE_PORT(PCIE_LC_CNTL3);
1584         data |= LC_GO_TO_RECOVERY;
1585         if (orig != data)
1586                 WREG32_PCIE_PORT(PCIE_LC_CNTL3, data);
1587
1588         orig = data = RREG32_PCIE(PCIE_P_CNTL);
1589         data |= P_IGNORE_EDB_ERR;
1590         if (orig != data)
1591                 WREG32_PCIE(PCIE_P_CNTL, data);
1592
1593         orig = data = RREG32_PCIE_PORT(PCIE_LC_CNTL);
1594         data &= ~(LC_L0S_INACTIVITY_MASK | LC_L1_INACTIVITY_MASK);
1595         data |= LC_PMI_TO_L1_DIS;
1596         if (!disable_l0s)
1597                 data |= LC_L0S_INACTIVITY(7);
1598
1599         if (!disable_l1) {
1600                 data |= LC_L1_INACTIVITY(7);
1601                 data &= ~LC_PMI_TO_L1_DIS;
1602                 if (orig != data)
1603                         WREG32_PCIE_PORT(PCIE_LC_CNTL, data);
1604
1605                 if (!disable_plloff_in_l1) {
1606                         bool clk_req_support;
1607
1608                         orig = data = si_pif_phy0_rreg(adev,PB0_PIF_PWRDOWN_0);
1609                         data &= ~(PLL_POWER_STATE_IN_OFF_0_MASK | PLL_POWER_STATE_IN_TXS2_0_MASK);
1610                         data |= PLL_POWER_STATE_IN_OFF_0(7) | PLL_POWER_STATE_IN_TXS2_0(7);
1611                         if (orig != data)
1612                                 si_pif_phy0_wreg(adev,PB0_PIF_PWRDOWN_0, data);
1613
1614                         orig = data = si_pif_phy0_rreg(adev,PB0_PIF_PWRDOWN_1);
1615                         data &= ~(PLL_POWER_STATE_IN_OFF_1_MASK | PLL_POWER_STATE_IN_TXS2_1_MASK);
1616                         data |= PLL_POWER_STATE_IN_OFF_1(7) | PLL_POWER_STATE_IN_TXS2_1(7);
1617                         if (orig != data)
1618                                 si_pif_phy0_wreg(adev,PB0_PIF_PWRDOWN_1, data);
1619
1620                         orig = data = si_pif_phy1_rreg(adev,PB1_PIF_PWRDOWN_0);
1621                         data &= ~(PLL_POWER_STATE_IN_OFF_0_MASK | PLL_POWER_STATE_IN_TXS2_0_MASK);
1622                         data |= PLL_POWER_STATE_IN_OFF_0(7) | PLL_POWER_STATE_IN_TXS2_0(7);
1623                         if (orig != data)
1624                                 si_pif_phy1_wreg(adev,PB1_PIF_PWRDOWN_0, data);
1625
1626                         orig = data = si_pif_phy1_rreg(adev,PB1_PIF_PWRDOWN_1);
1627                         data &= ~(PLL_POWER_STATE_IN_OFF_1_MASK | PLL_POWER_STATE_IN_TXS2_1_MASK);
1628                         data |= PLL_POWER_STATE_IN_OFF_1(7) | PLL_POWER_STATE_IN_TXS2_1(7);
1629                         if (orig != data)
1630                                 si_pif_phy1_wreg(adev,PB1_PIF_PWRDOWN_1, data);
1631
1632                         if ((adev->family != CHIP_OLAND) && (adev->family != CHIP_HAINAN)) {
1633                                 orig = data = si_pif_phy0_rreg(adev,PB0_PIF_PWRDOWN_0);
1634                                 data &= ~PLL_RAMP_UP_TIME_0_MASK;
1635                                 if (orig != data)
1636                                         si_pif_phy0_wreg(adev,PB0_PIF_PWRDOWN_0, data);
1637
1638                                 orig = data = si_pif_phy0_rreg(adev,PB0_PIF_PWRDOWN_1);
1639                                 data &= ~PLL_RAMP_UP_TIME_1_MASK;
1640                                 if (orig != data)
1641                                         si_pif_phy0_wreg(adev,PB0_PIF_PWRDOWN_1, data);
1642
1643                                 orig = data = si_pif_phy0_rreg(adev,PB0_PIF_PWRDOWN_2);
1644                                 data &= ~PLL_RAMP_UP_TIME_2_MASK;
1645                                 if (orig != data)
1646                                         si_pif_phy0_wreg(adev,PB0_PIF_PWRDOWN_2, data);
1647
1648                                 orig = data = si_pif_phy0_rreg(adev,PB0_PIF_PWRDOWN_3);
1649                                 data &= ~PLL_RAMP_UP_TIME_3_MASK;
1650                                 if (orig != data)
1651                                         si_pif_phy0_wreg(adev,PB0_PIF_PWRDOWN_3, data);
1652
1653                                 orig = data = si_pif_phy1_rreg(adev,PB1_PIF_PWRDOWN_0);
1654                                 data &= ~PLL_RAMP_UP_TIME_0_MASK;
1655                                 if (orig != data)
1656                                         si_pif_phy1_wreg(adev,PB1_PIF_PWRDOWN_0, data);
1657
1658                                 orig = data = si_pif_phy1_rreg(adev,PB1_PIF_PWRDOWN_1);
1659                                 data &= ~PLL_RAMP_UP_TIME_1_MASK;
1660                                 if (orig != data)
1661                                         si_pif_phy1_wreg(adev,PB1_PIF_PWRDOWN_1, data);
1662
1663                                 orig = data = si_pif_phy1_rreg(adev,PB1_PIF_PWRDOWN_2);
1664                                 data &= ~PLL_RAMP_UP_TIME_2_MASK;
1665                                 if (orig != data)
1666                                         si_pif_phy1_wreg(adev,PB1_PIF_PWRDOWN_2, data);
1667
1668                                 orig = data = si_pif_phy1_rreg(adev,PB1_PIF_PWRDOWN_3);
1669                                 data &= ~PLL_RAMP_UP_TIME_3_MASK;
1670                                 if (orig != data)
1671                                         si_pif_phy1_wreg(adev,PB1_PIF_PWRDOWN_3, data);
1672                         }
1673                         orig = data = RREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL);
1674                         data &= ~LC_DYN_LANES_PWR_STATE_MASK;
1675                         data |= LC_DYN_LANES_PWR_STATE(3);
1676                         if (orig != data)
1677                                 WREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL, data);
1678
1679                         orig = data = si_pif_phy0_rreg(adev,PB0_PIF_CNTL);
1680                         data &= ~LS2_EXIT_TIME_MASK;
1681                         if ((adev->family == CHIP_OLAND) || (adev->family == CHIP_HAINAN))
1682                                 data |= LS2_EXIT_TIME(5);
1683                         if (orig != data)
1684                                 si_pif_phy0_wreg(adev,PB0_PIF_CNTL, data);
1685
1686                         orig = data = si_pif_phy1_rreg(adev,PB1_PIF_CNTL);
1687                         data &= ~LS2_EXIT_TIME_MASK;
1688                         if ((adev->family == CHIP_OLAND) || (adev->family == CHIP_HAINAN))
1689                                 data |= LS2_EXIT_TIME(5);
1690                         if (orig != data)
1691                                 si_pif_phy1_wreg(adev,PB1_PIF_CNTL, data);
1692
1693                         if (!disable_clkreq &&
1694                             !pci_is_root_bus(adev->pdev->bus)) {
1695                                 struct pci_dev *root = adev->pdev->bus->self;
1696                                 u32 lnkcap;
1697
1698                                 clk_req_support = false;
1699                                 pcie_capability_read_dword(root, PCI_EXP_LNKCAP, &lnkcap);
1700                                 if (lnkcap & PCI_EXP_LNKCAP_CLKPM)
1701                                         clk_req_support = true;
1702                         } else {
1703                                 clk_req_support = false;
1704                         }
1705
1706                         if (clk_req_support) {
1707                                 orig = data = RREG32_PCIE_PORT(PCIE_LC_CNTL2);
1708                                 data |= LC_ALLOW_PDWN_IN_L1 | LC_ALLOW_PDWN_IN_L23;
1709                                 if (orig != data)
1710                                         WREG32_PCIE_PORT(PCIE_LC_CNTL2, data);
1711
1712                                 orig = data = RREG32(THM_CLK_CNTL);
1713                                 data &= ~(CMON_CLK_SEL_MASK | TMON_CLK_SEL_MASK);
1714                                 data |= CMON_CLK_SEL(1) | TMON_CLK_SEL(1);
1715                                 if (orig != data)
1716                                         WREG32(THM_CLK_CNTL, data);
1717
1718                                 orig = data = RREG32(MISC_CLK_CNTL);
1719                                 data &= ~(DEEP_SLEEP_CLK_SEL_MASK | ZCLK_SEL_MASK);
1720                                 data |= DEEP_SLEEP_CLK_SEL(1) | ZCLK_SEL(1);
1721                                 if (orig != data)
1722                                         WREG32(MISC_CLK_CNTL, data);
1723
1724                                 orig = data = RREG32(CG_CLKPIN_CNTL);
1725                                 data &= ~BCLK_AS_XCLK;
1726                                 if (orig != data)
1727                                         WREG32(CG_CLKPIN_CNTL, data);
1728
1729                                 orig = data = RREG32(CG_CLKPIN_CNTL_2);
1730                                 data &= ~FORCE_BIF_REFCLK_EN;
1731                                 if (orig != data)
1732                                         WREG32(CG_CLKPIN_CNTL_2, data);
1733
1734                                 orig = data = RREG32(MPLL_BYPASSCLK_SEL);
1735                                 data &= ~MPLL_CLKOUT_SEL_MASK;
1736                                 data |= MPLL_CLKOUT_SEL(4);
1737                                 if (orig != data)
1738                                         WREG32(MPLL_BYPASSCLK_SEL, data);
1739
1740                                 orig = data = RREG32(SPLL_CNTL_MODE);
1741                                 data &= ~SPLL_REFCLK_SEL_MASK;
1742                                 if (orig != data)
1743                                         WREG32(SPLL_CNTL_MODE, data);
1744                         }
1745                 }
1746         } else {
1747                 if (orig != data)
1748                         WREG32_PCIE_PORT(PCIE_LC_CNTL, data);
1749         }
1750
1751         orig = data = RREG32_PCIE(PCIE_CNTL2);
1752         data |= SLV_MEM_LS_EN | MST_MEM_LS_EN | REPLAY_MEM_LS_EN;
1753         if (orig != data)
1754                 WREG32_PCIE(PCIE_CNTL2, data);
1755
1756         if (!disable_l0s) {
1757                 data = RREG32_PCIE_PORT(PCIE_LC_N_FTS_CNTL);
1758                 if((data & LC_N_FTS_MASK) == LC_N_FTS_MASK) {
1759                         data = RREG32_PCIE(PCIE_LC_STATUS1);
1760                         if ((data & LC_REVERSE_XMIT) && (data & LC_REVERSE_RCVR)) {
1761                                 orig = data = RREG32_PCIE_PORT(PCIE_LC_CNTL);
1762                                 data &= ~LC_L0S_INACTIVITY_MASK;
1763                                 if (orig != data)
1764                                         WREG32_PCIE_PORT(PCIE_LC_CNTL, data);
1765                         }
1766                 }
1767         }
1768 }
1769
1770 static void si_fix_pci_max_read_req_size(struct amdgpu_device *adev)
1771 {
1772         int readrq;
1773         u16 v;
1774
1775         readrq = pcie_get_readrq(adev->pdev);
1776         v = ffs(readrq) - 8;
1777         if ((v == 0) || (v == 6) || (v == 7))
1778                 pcie_set_readrq(adev->pdev, 512);
1779 }
1780
1781 static int si_common_hw_init(void *handle)
1782 {
1783         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1784
1785         si_fix_pci_max_read_req_size(adev);
1786         si_init_golden_registers(adev);
1787         si_pcie_gen3_enable(adev);
1788         si_program_aspm(adev);
1789
1790         return 0;
1791 }
1792
1793 static int si_common_hw_fini(void *handle)
1794 {
1795         return 0;
1796 }
1797
1798 static int si_common_suspend(void *handle)
1799 {
1800         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1801
1802         return si_common_hw_fini(adev);
1803 }
1804
1805 static int si_common_resume(void *handle)
1806 {
1807         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1808
1809         return si_common_hw_init(adev);
1810 }
1811
1812 static bool si_common_is_idle(void *handle)
1813 {
1814         return true;
1815 }
1816
1817 static int si_common_wait_for_idle(void *handle)
1818 {
1819         return 0;
1820 }
1821
1822 static int si_common_soft_reset(void *handle)
1823 {
1824         return 0;
1825 }
1826
1827 static int si_common_set_clockgating_state(void *handle,
1828                                             enum amd_clockgating_state state)
1829 {
1830         return 0;
1831 }
1832
1833 static int si_common_set_powergating_state(void *handle,
1834                                             enum amd_powergating_state state)
1835 {
1836         return 0;
1837 }
1838
1839 static const struct amd_ip_funcs si_common_ip_funcs = {
1840         .name = "si_common",
1841         .early_init = si_common_early_init,
1842         .late_init = NULL,
1843         .sw_init = si_common_sw_init,
1844         .sw_fini = si_common_sw_fini,
1845         .hw_init = si_common_hw_init,
1846         .hw_fini = si_common_hw_fini,
1847         .suspend = si_common_suspend,
1848         .resume = si_common_resume,
1849         .is_idle = si_common_is_idle,
1850         .wait_for_idle = si_common_wait_for_idle,
1851         .soft_reset = si_common_soft_reset,
1852         .set_clockgating_state = si_common_set_clockgating_state,
1853         .set_powergating_state = si_common_set_powergating_state,
1854 };
1855
1856 static const struct amdgpu_ip_block_version si_common_ip_block =
1857 {
1858         .type = AMD_IP_BLOCK_TYPE_COMMON,
1859         .major = 1,
1860         .minor = 0,
1861         .rev = 0,
1862         .funcs = &si_common_ip_funcs,
1863 };
1864
1865 int si_set_ip_blocks(struct amdgpu_device *adev)
1866 {
1867         switch (adev->asic_type) {
1868         case CHIP_VERDE:
1869         case CHIP_TAHITI:
1870         case CHIP_PITCAIRN:
1871                 amdgpu_ip_block_add(adev, &si_common_ip_block);
1872                 amdgpu_ip_block_add(adev, &gmc_v6_0_ip_block);
1873                 amdgpu_ip_block_add(adev, &si_ih_ip_block);
1874                 amdgpu_ip_block_add(adev, &amdgpu_pp_ip_block);
1875                 if (adev->enable_virtual_display)
1876                         amdgpu_ip_block_add(adev, &dce_virtual_ip_block);
1877                 else
1878                         amdgpu_ip_block_add(adev, &dce_v6_0_ip_block);
1879                 amdgpu_ip_block_add(adev, &gfx_v6_0_ip_block);
1880                 amdgpu_ip_block_add(adev, &si_dma_ip_block);
1881                 /* amdgpu_ip_block_add(adev, &uvd_v3_1_ip_block); */
1882                 /* amdgpu_ip_block_add(adev, &vce_v1_0_ip_block); */
1883                 break;
1884         case CHIP_OLAND:
1885                 amdgpu_ip_block_add(adev, &si_common_ip_block);
1886                 amdgpu_ip_block_add(adev, &gmc_v6_0_ip_block);
1887                 amdgpu_ip_block_add(adev, &si_ih_ip_block);
1888                 amdgpu_ip_block_add(adev, &amdgpu_pp_ip_block);
1889                 if (adev->enable_virtual_display)
1890                         amdgpu_ip_block_add(adev, &dce_virtual_ip_block);
1891                 else
1892                         amdgpu_ip_block_add(adev, &dce_v6_4_ip_block);
1893                 amdgpu_ip_block_add(adev, &gfx_v6_0_ip_block);
1894                 amdgpu_ip_block_add(adev, &si_dma_ip_block);
1895                 /* amdgpu_ip_block_add(adev, &uvd_v3_1_ip_block); */
1896                 /* amdgpu_ip_block_add(adev, &vce_v1_0_ip_block); */
1897                 break;
1898         case CHIP_HAINAN:
1899                 amdgpu_ip_block_add(adev, &si_common_ip_block);
1900                 amdgpu_ip_block_add(adev, &gmc_v6_0_ip_block);
1901                 amdgpu_ip_block_add(adev, &si_ih_ip_block);
1902                 amdgpu_ip_block_add(adev, &amdgpu_pp_ip_block);
1903                 if (adev->enable_virtual_display)
1904                         amdgpu_ip_block_add(adev, &dce_virtual_ip_block);
1905                 amdgpu_ip_block_add(adev, &gfx_v6_0_ip_block);
1906                 amdgpu_ip_block_add(adev, &si_dma_ip_block);
1907                 break;
1908         default:
1909                 BUG();
1910         }
1911         return 0;
1912 }
1913