drivers/gpu/drm/amd/amdgpu/si.c

   1 /*
   2  * Copyright 2015 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23
  24 #include <linux/firmware.h>
  25 #include <linux/slab.h>
  26 #include <linux/module.h>
  27 #include "drmP.h"
  28 #include "amdgpu.h"
  29 #include "amdgpu_atombios.h"
  30 #include "amdgpu_ih.h"
  31 #include "amdgpu_uvd.h"
  32 #include "amdgpu_vce.h"
  33 #include "atom.h"
  34 #include "amdgpu_powerplay.h"
  35 #include "si/sid.h"
  36 #include "si_ih.h"
  37 #include "gfx_v6_0.h"
  38 #include "gmc_v6_0.h"
  39 #include "si_dma.h"
  40 #include "dce_v6_0.h"
  41 #include "si.h"
  42 #include "dce_virtual.h"
  43
  44 static const u32 tahiti_golden_registers[] =
  45 {
  46         0x17bc, 0x00000030, 0x00000011,
  47         0x2684, 0x00010000, 0x00018208,
  48         0x260c, 0xffffffff, 0x00000000,
  49         0x260d, 0xf00fffff, 0x00000400,
  50         0x260e, 0x0002021c, 0x00020200,
  51         0x031e, 0x00000080, 0x00000000,
  52         0x340c, 0x000000c0, 0x00800040,
  53         0x360c, 0x000000c0, 0x00800040,
  54         0x16ec, 0x000000f0, 0x00000070,
  55         0x16f0, 0x00200000, 0x50100000,
  56         0x1c0c, 0x31000311, 0x00000011,
  57         0x09df, 0x00000003, 0x000007ff,
  58         0x0903, 0x000007ff, 0x00000000,
  59         0x2285, 0xf000001f, 0x00000007,
  60         0x22c9, 0xffffffff, 0x00ffffff,
  61         0x22c4, 0x0000ff0f, 0x00000000,
  62         0xa293, 0x07ffffff, 0x4e000000,
  63         0xa0d4, 0x3f3f3fff, 0x2a00126a,
  64         0x000c, 0xffffffff, 0x0040,
  65         0x000d, 0x00000040, 0x00004040,
  66         0x2440, 0x07ffffff, 0x03000000,
  67         0x23a2, 0x01ff1f3f, 0x00000000,
  68         0x23a1, 0x01ff1f3f, 0x00000000,
  69         0x2418, 0x0000007f, 0x00000020,
  70         0x2542, 0x00010000, 0x00010000,
  71         0x2b05, 0x00000200, 0x000002fb,
  72         0x2b04, 0xffffffff, 0x0000543b,
  73         0x2b03, 0xffffffff, 0xa9210876,
  74         0x2234, 0xffffffff, 0x000fff40,
  75         0x2235, 0x0000001f, 0x00000010,
  76         0x0504, 0x20000000, 0x20fffed8,
  77         0x0570, 0x000c0fc0, 0x000c0400,
  78         0x052c, 0x0fffffff, 0xffffffff,
  79         0x052d, 0x0fffffff, 0x0fffffff,
  80         0x052e, 0x0fffffff, 0x0fffffff,
  81         0x052f, 0x0fffffff, 0x0fffffff
  82 };
  83
  84 static const u32 tahiti_golden_registers2[] =
  85 {
  86         0x0319, 0x00000001, 0x00000001
  87 };
  88
  89 static const u32 tahiti_golden_rlc_registers[] =
  90 {
  91         0x263e, 0xffffffff, 0x12011003,
  92         0x3109, 0xffffffff, 0x00601005,
  93         0x311f, 0xffffffff, 0x10104040,
  94         0x3122, 0xffffffff, 0x0100000a,
  95         0x30c5, 0xffffffff, 0x00000800,
  96         0x30c3, 0xffffffff, 0x800000f4,
  97         0x3d2a, 0x00000008, 0x00000000
  98 };
  99
 100 static const u32 pitcairn_golden_registers[] =
 101 {
 102         0x17bc, 0x00000030, 0x00000011,
 103         0x2684, 0x00010000, 0x00018208,
 104         0x260c, 0xffffffff, 0x00000000,
 105         0x260d, 0xf00fffff, 0x00000400,
 106         0x260e, 0x0002021c, 0x00020200,
 107         0x031e, 0x00000080, 0x00000000,
 108         0x340c, 0x000300c0, 0x00800040,
 109         0x360c, 0x000300c0, 0x00800040,
 110         0x16ec, 0x000000f0, 0x00000070,
 111         0x16f0, 0x00200000, 0x50100000,
 112         0x1c0c, 0x31000311, 0x00000011,
 113         0x0ab9, 0x00073ffe, 0x000022a2,
 114         0x0903, 0x000007ff, 0x00000000,
 115         0x2285, 0xf000001f, 0x00000007,
 116         0x22c9, 0xffffffff, 0x00ffffff,
 117         0x22c4, 0x0000ff0f, 0x00000000,
 118         0xa293, 0x07ffffff, 0x4e000000,
 119         0xa0d4, 0x3f3f3fff, 0x2a00126a,
 120         0x000c, 0xffffffff, 0x0040,
 121         0x000d, 0x00000040, 0x00004040,
 122         0x2440, 0x07ffffff, 0x03000000,
 123         0x2418, 0x0000007f, 0x00000020,
 124         0x2542, 0x00010000, 0x00010000,
 125         0x2b05, 0x000003ff, 0x000000f7,
 126         0x2b04, 0xffffffff, 0x00000000,
 127         0x2b03, 0xffffffff, 0x32761054,
 128         0x2235, 0x0000001f, 0x00000010,
 129         0x0570, 0x000c0fc0, 0x000c0400,
 130         0x052c, 0x0fffffff, 0xffffffff,
 131         0x052d, 0x0fffffff, 0x0fffffff,
 132         0x052e, 0x0fffffff, 0x0fffffff,
 133         0x052f, 0x0fffffff, 0x0fffffff
 134 };
 135
 136 static const u32 pitcairn_golden_rlc_registers[] =
 137 {
 138         0x263e, 0xffffffff, 0x12011003,
 139         0x3109, 0xffffffff, 0x00601004,
 140         0x311f, 0xffffffff, 0x10102020,
 141         0x3122, 0xffffffff, 0x01000020,
 142         0x30c5, 0xffffffff, 0x00000800,
 143         0x30c3, 0xffffffff, 0x800000a4
 144 };
 145
 146 static const u32 verde_pg_init[] =
 147 {
 148         0xd4f, 0xffffffff, 0x40000,
 149         0xd4e, 0xffffffff, 0x200010ff,
 150         0xd4f, 0xffffffff, 0x0,
 151         0xd4f, 0xffffffff, 0x0,
 152         0xd4f, 0xffffffff, 0x0,
 153         0xd4f, 0xffffffff, 0x0,
 154         0xd4f, 0xffffffff, 0x0,
 155         0xd4f, 0xffffffff, 0x7007,
 156         0xd4e, 0xffffffff, 0x300010ff,
 157         0xd4f, 0xffffffff, 0x0,
 158         0xd4f, 0xffffffff, 0x0,
 159         0xd4f, 0xffffffff, 0x0,
 160         0xd4f, 0xffffffff, 0x0,
 161         0xd4f, 0xffffffff, 0x0,
 162         0xd4f, 0xffffffff, 0x400000,
 163         0xd4e, 0xffffffff, 0x100010ff,
 164         0xd4f, 0xffffffff, 0x0,
 165         0xd4f, 0xffffffff, 0x0,
 166         0xd4f, 0xffffffff, 0x0,
 167         0xd4f, 0xffffffff, 0x0,
 168         0xd4f, 0xffffffff, 0x0,
 169         0xd4f, 0xffffffff, 0x120200,
 170         0xd4e, 0xffffffff, 0x500010ff,
 171         0xd4f, 0xffffffff, 0x0,
 172         0xd4f, 0xffffffff, 0x0,
 173         0xd4f, 0xffffffff, 0x0,
 174         0xd4f, 0xffffffff, 0x0,
 175         0xd4f, 0xffffffff, 0x0,
 176         0xd4f, 0xffffffff, 0x1e1e16,
 177         0xd4e, 0xffffffff, 0x600010ff,
 178         0xd4f, 0xffffffff, 0x0,
 179         0xd4f, 0xffffffff, 0x0,
 180         0xd4f, 0xffffffff, 0x0,
 181         0xd4f, 0xffffffff, 0x0,
 182         0xd4f, 0xffffffff, 0x0,
 183         0xd4f, 0xffffffff, 0x171f1e,
 184         0xd4e, 0xffffffff, 0x700010ff,
 185         0xd4f, 0xffffffff, 0x0,
 186         0xd4f, 0xffffffff, 0x0,
 187         0xd4f, 0xffffffff, 0x0,
 188         0xd4f, 0xffffffff, 0x0,
 189         0xd4f, 0xffffffff, 0x0,
 190         0xd4f, 0xffffffff, 0x0,
 191         0xd4e, 0xffffffff, 0x9ff,
 192         0xd40, 0xffffffff, 0x0,
 193         0xd41, 0xffffffff, 0x10000800,
 194         0xd41, 0xffffffff, 0xf,
 195         0xd41, 0xffffffff, 0xf,
 196         0xd40, 0xffffffff, 0x4,
 197         0xd41, 0xffffffff, 0x1000051e,
 198         0xd41, 0xffffffff, 0xffff,
 199         0xd41, 0xffffffff, 0xffff,
 200         0xd40, 0xffffffff, 0x8,
 201         0xd41, 0xffffffff, 0x80500,
 202         0xd40, 0xffffffff, 0x12,
 203         0xd41, 0xffffffff, 0x9050c,
 204         0xd40, 0xffffffff, 0x1d,
 205         0xd41, 0xffffffff, 0xb052c,
 206         0xd40, 0xffffffff, 0x2a,
 207         0xd41, 0xffffffff, 0x1053e,
 208         0xd40, 0xffffffff, 0x2d,
 209         0xd41, 0xffffffff, 0x10546,
 210         0xd40, 0xffffffff, 0x30,
 211         0xd41, 0xffffffff, 0xa054e,
 212         0xd40, 0xffffffff, 0x3c,
 213         0xd41, 0xffffffff, 0x1055f,
 214         0xd40, 0xffffffff, 0x3f,
 215         0xd41, 0xffffffff, 0x10567,
 216         0xd40, 0xffffffff, 0x42,
 217         0xd41, 0xffffffff, 0x1056f,
 218         0xd40, 0xffffffff, 0x45,
 219         0xd41, 0xffffffff, 0x10572,
 220         0xd40, 0xffffffff, 0x48,
 221         0xd41, 0xffffffff, 0x20575,
 222         0xd40, 0xffffffff, 0x4c,
 223         0xd41, 0xffffffff, 0x190801,
 224         0xd40, 0xffffffff, 0x67,
 225         0xd41, 0xffffffff, 0x1082a,
 226         0xd40, 0xffffffff, 0x6a,
 227         0xd41, 0xffffffff, 0x1b082d,
 228         0xd40, 0xffffffff, 0x87,
 229         0xd41, 0xffffffff, 0x310851,
 230         0xd40, 0xffffffff, 0xba,
 231         0xd41, 0xffffffff, 0x891,
 232         0xd40, 0xffffffff, 0xbc,
 233         0xd41, 0xffffffff, 0x893,
 234         0xd40, 0xffffffff, 0xbe,
 235         0xd41, 0xffffffff, 0x20895,
 236         0xd40, 0xffffffff, 0xc2,
 237         0xd41, 0xffffffff, 0x20899,
 238         0xd40, 0xffffffff, 0xc6,
 239         0xd41, 0xffffffff, 0x2089d,
 240         0xd40, 0xffffffff, 0xca,
 241         0xd41, 0xffffffff, 0x8a1,
 242         0xd40, 0xffffffff, 0xcc,
 243         0xd41, 0xffffffff, 0x8a3,
 244         0xd40, 0xffffffff, 0xce,
 245         0xd41, 0xffffffff, 0x308a5,
 246         0xd40, 0xffffffff, 0xd3,
 247         0xd41, 0xffffffff, 0x6d08cd,
 248         0xd40, 0xffffffff, 0x142,
 249         0xd41, 0xffffffff, 0x2000095a,
 250         0xd41, 0xffffffff, 0x1,
 251         0xd40, 0xffffffff, 0x144,
 252         0xd41, 0xffffffff, 0x301f095b,
 253         0xd40, 0xffffffff, 0x165,
 254         0xd41, 0xffffffff, 0xc094d,
 255         0xd40, 0xffffffff, 0x173,
 256         0xd41, 0xffffffff, 0xf096d,
 257         0xd40, 0xffffffff, 0x184,
 258         0xd41, 0xffffffff, 0x15097f,
 259         0xd40, 0xffffffff, 0x19b,
 260         0xd41, 0xffffffff, 0xc0998,
 261         0xd40, 0xffffffff, 0x1a9,
 262         0xd41, 0xffffffff, 0x409a7,
 263         0xd40, 0xffffffff, 0x1af,
 264         0xd41, 0xffffffff, 0xcdc,
 265         0xd40, 0xffffffff, 0x1b1,
 266         0xd41, 0xffffffff, 0x800,
 267         0xd42, 0xffffffff, 0x6c9b2000,
 268         0xd44, 0xfc00, 0x2000,
 269         0xd51, 0xffffffff, 0xfc0,
 270         0xa35, 0x00000100, 0x100
 271 };
 272
 273 static const u32 verde_golden_rlc_registers[] =
 274 {
 275         0x3109, 0xffffffff, 0x033f1005,
 276         0x311f, 0xffffffff, 0x10808020,
 277         0x3122, 0xffffffff, 0x00800008,
 278         0x30c5, 0xffffffff, 0x00001000,
 279         0x30c3, 0xffffffff, 0x80010014
 280 };
 281
 282 static const u32 verde_golden_registers[] =
 283 {
 284         0x2684, 0x00010000, 0x00018208,
 285         0x260c, 0xffffffff, 0x00000000,
 286         0x260d, 0xf00fffff, 0x00000400,
 287         0x260e, 0x0002021c, 0x00020200,
 288         0x031e, 0x00000080, 0x00000000,
 289         0x340c, 0x000300c0, 0x00800040,
 290         0x340c, 0x000300c0, 0x00800040,
 291         0x360c, 0x000300c0, 0x00800040,
 292         0x360c, 0x000300c0, 0x00800040,
 293         0x16ec, 0x000000f0, 0x00000070,
 294         0x16f0, 0x00200000, 0x50100000,
 295
 296         0x1c0c, 0x31000311, 0x00000011,
 297         0x0ab9, 0x00073ffe, 0x000022a2,
 298         0x0ab9, 0x00073ffe, 0x000022a2,
 299         0x0ab9, 0x00073ffe, 0x000022a2,
 300         0x0903, 0x000007ff, 0x00000000,
 301         0x0903, 0x000007ff, 0x00000000,
 302         0x0903, 0x000007ff, 0x00000000,
 303         0x2285, 0xf000001f, 0x00000007,
 304         0x2285, 0xf000001f, 0x00000007,
 305         0x2285, 0xf000001f, 0x00000007,
 306         0x2285, 0xffffffff, 0x00ffffff,
 307         0x22c4, 0x0000ff0f, 0x00000000,
 308
 309         0xa293, 0x07ffffff, 0x4e000000,
 310         0xa0d4, 0x3f3f3fff, 0x0000124a,
 311         0xa0d4, 0x3f3f3fff, 0x0000124a,
 312         0xa0d4, 0x3f3f3fff, 0x0000124a,
 313         0x000c, 0x000000ff, 0x0040,
 314         0x000d, 0x00000040, 0x00004040,
 315         0x2440, 0x07ffffff, 0x03000000,
 316         0x2440, 0x07ffffff, 0x03000000,
 317         0x23a2, 0x01ff1f3f, 0x00000000,
 318         0x23a3, 0x01ff1f3f, 0x00000000,
 319         0x23a2, 0x01ff1f3f, 0x00000000,
 320         0x23a1, 0x01ff1f3f, 0x00000000,
 321         0x23a1, 0x01ff1f3f, 0x00000000,
 322
 323         0x23a1, 0x01ff1f3f, 0x00000000,
 324         0x2418, 0x0000007f, 0x00000020,
 325         0x2542, 0x00010000, 0x00010000,
 326         0x2b01, 0x000003ff, 0x00000003,
 327         0x2b05, 0x000003ff, 0x00000003,
 328         0x2b05, 0x000003ff, 0x00000003,
 329         0x2b04, 0xffffffff, 0x00000000,
 330         0x2b04, 0xffffffff, 0x00000000,
 331         0x2b04, 0xffffffff, 0x00000000,
 332         0x2b03, 0xffffffff, 0x00001032,
 333         0x2b03, 0xffffffff, 0x00001032,
 334         0x2b03, 0xffffffff, 0x00001032,
 335         0x2235, 0x0000001f, 0x00000010,
 336         0x2235, 0x0000001f, 0x00000010,
 337         0x2235, 0x0000001f, 0x00000010,
 338         0x0570, 0x000c0fc0, 0x000c0400
 339 };
 340
 341 static const u32 oland_golden_registers[] =
 342 {
 343         0x2684, 0x00010000, 0x00018208,
 344         0x260c, 0xffffffff, 0x00000000,
 345         0x260d, 0xf00fffff, 0x00000400,
 346         0x260e, 0x0002021c, 0x00020200,
 347         0x031e, 0x00000080, 0x00000000,
 348         0x340c, 0x000300c0, 0x00800040,
 349         0x360c, 0x000300c0, 0x00800040,
 350         0x16ec, 0x000000f0, 0x00000070,
 351         0x16f9, 0x00200000, 0x50100000,
 352         0x1c0c, 0x31000311, 0x00000011,
 353         0x0ab9, 0x00073ffe, 0x000022a2,
 354         0x0903, 0x000007ff, 0x00000000,
 355         0x2285, 0xf000001f, 0x00000007,
 356         0x22c9, 0xffffffff, 0x00ffffff,
 357         0x22c4, 0x0000ff0f, 0x00000000,
 358         0xa293, 0x07ffffff, 0x4e000000,
 359         0xa0d4, 0x3f3f3fff, 0x00000082,
 360         0x000c, 0x000000ff, 0x0040,
 361         0x000d, 0x00000040, 0x00004040,
 362         0x2440, 0x07ffffff, 0x03000000,
 363         0x2418, 0x0000007f, 0x00000020,
 364         0x2542, 0x00010000, 0x00010000,
 365         0x2b05, 0x000003ff, 0x000000f3,
 366         0x2b04, 0xffffffff, 0x00000000,
 367         0x2b03, 0xffffffff, 0x00003210,
 368         0x2235, 0x0000001f, 0x00000010,
 369         0x0570, 0x000c0fc0, 0x000c0400
 370 };
 371
 372 static const u32 oland_golden_rlc_registers[] =
 373 {
 374         0x3109, 0xffffffff, 0x00601005,
 375         0x311f, 0xffffffff, 0x10104040,
 376         0x3122, 0xffffffff, 0x0100000a,
 377         0x30c5, 0xffffffff, 0x00000800,
 378         0x30c3, 0xffffffff, 0x800000f4
 379 };
 380
 381 static const u32 hainan_golden_registers[] =
 382 {
 383         0x2684, 0x00010000, 0x00018208,
 384         0x260c, 0xffffffff, 0x00000000,
 385         0x260d, 0xf00fffff, 0x00000400,
 386         0x260e, 0x0002021c, 0x00020200,
 387         0x4595, 0xff000fff, 0x00000100,
 388         0x340c, 0x000300c0, 0x00800040,
 389         0x3630, 0xff000fff, 0x00000100,
 390         0x360c, 0x000300c0, 0x00800040,
 391         0x0ab9, 0x00073ffe, 0x000022a2,
 392         0x0903, 0x000007ff, 0x00000000,
 393         0x2285, 0xf000001f, 0x00000007,
 394         0x22c9, 0xffffffff, 0x00ffffff,
 395         0x22c4, 0x0000ff0f, 0x00000000,
 396         0xa393, 0x07ffffff, 0x4e000000,
 397         0xa0d4, 0x3f3f3fff, 0x00000000,
 398         0x000c, 0x000000ff, 0x0040,
 399         0x000d, 0x00000040, 0x00004040,
 400         0x2440, 0x03e00000, 0x03600000,
 401         0x2418, 0x0000007f, 0x00000020,
 402         0x2542, 0x00010000, 0x00010000,
 403         0x2b05, 0x000003ff, 0x000000f1,
 404         0x2b04, 0xffffffff, 0x00000000,
 405         0x2b03, 0xffffffff, 0x00003210,
 406         0x2235, 0x0000001f, 0x00000010,
 407         0x0570, 0x000c0fc0, 0x000c0400
 408 };
 409
 410 static const u32 hainan_golden_registers2[] =
 411 {
 412         0x263e, 0xffffffff, 0x02010001
 413 };
 414
 415 static const u32 tahiti_mgcg_cgcg_init[] =
 416 {
 417         0x3100, 0xffffffff, 0xfffffffc,
 418         0x200b, 0xffffffff, 0xe0000000,
 419         0x2698, 0xffffffff, 0x00000100,
 420         0x24a9, 0xffffffff, 0x00000100,
 421         0x3059, 0xffffffff, 0x00000100,
 422         0x25dd, 0xffffffff, 0x00000100,
 423         0x2261, 0xffffffff, 0x06000100,
 424         0x2286, 0xffffffff, 0x00000100,
 425         0x24a8, 0xffffffff, 0x00000100,
 426         0x30e0, 0xffffffff, 0x00000100,
 427         0x22ca, 0xffffffff, 0x00000100,
 428         0x2451, 0xffffffff, 0x00000100,
 429         0x2362, 0xffffffff, 0x00000100,
 430         0x2363, 0xffffffff, 0x00000100,
 431         0x240c, 0xffffffff, 0x00000100,
 432         0x240d, 0xffffffff, 0x00000100,
 433         0x240e, 0xffffffff, 0x00000100,
 434         0x240f, 0xffffffff, 0x00000100,
 435         0x2b60, 0xffffffff, 0x00000100,
 436         0x2b15, 0xffffffff, 0x00000100,
 437         0x225f, 0xffffffff, 0x06000100,
 438         0x261a, 0xffffffff, 0x00000100,
 439         0x2544, 0xffffffff, 0x00000100,
 440         0x2bc1, 0xffffffff, 0x00000100,
 441         0x2b81, 0xffffffff, 0x00000100,
 442         0x2527, 0xffffffff, 0x00000100,
 443         0x200b, 0xffffffff, 0xe0000000,
 444         0x2458, 0xffffffff, 0x00010000,
 445         0x2459, 0xffffffff, 0x00030002,
 446         0x245a, 0xffffffff, 0x00040007,
 447         0x245b, 0xffffffff, 0x00060005,
 448         0x245c, 0xffffffff, 0x00090008,
 449         0x245d, 0xffffffff, 0x00020001,
 450         0x245e, 0xffffffff, 0x00040003,
 451         0x245f, 0xffffffff, 0x00000007,
 452         0x2460, 0xffffffff, 0x00060005,
 453         0x2461, 0xffffffff, 0x00090008,
 454         0x2462, 0xffffffff, 0x00030002,
 455         0x2463, 0xffffffff, 0x00050004,
 456         0x2464, 0xffffffff, 0x00000008,
 457         0x2465, 0xffffffff, 0x00070006,
 458         0x2466, 0xffffffff, 0x000a0009,
 459         0x2467, 0xffffffff, 0x00040003,
 460         0x2468, 0xffffffff, 0x00060005,
 461         0x2469, 0xffffffff, 0x00000009,
 462         0x246a, 0xffffffff, 0x00080007,
 463         0x246b, 0xffffffff, 0x000b000a,
 464         0x246c, 0xffffffff, 0x00050004,
 465         0x246d, 0xffffffff, 0x00070006,
 466         0x246e, 0xffffffff, 0x0008000b,
 467         0x246f, 0xffffffff, 0x000a0009,
 468         0x2470, 0xffffffff, 0x000d000c,
 469         0x2471, 0xffffffff, 0x00060005,
 470         0x2472, 0xffffffff, 0x00080007,
 471         0x2473, 0xffffffff, 0x0000000b,
 472         0x2474, 0xffffffff, 0x000a0009,
 473         0x2475, 0xffffffff, 0x000d000c,
 474         0x2476, 0xffffffff, 0x00070006,
 475         0x2477, 0xffffffff, 0x00090008,
 476         0x2478, 0xffffffff, 0x0000000c,
 477         0x2479, 0xffffffff, 0x000b000a,
 478         0x247a, 0xffffffff, 0x000e000d,
 479         0x247b, 0xffffffff, 0x00080007,
 480         0x247c, 0xffffffff, 0x000a0009,
 481         0x247d, 0xffffffff, 0x0000000d,
 482         0x247e, 0xffffffff, 0x000c000b,
 483         0x247f, 0xffffffff, 0x000f000e,
 484         0x2480, 0xffffffff, 0x00090008,
 485         0x2481, 0xffffffff, 0x000b000a,
 486         0x2482, 0xffffffff, 0x000c000f,
 487         0x2483, 0xffffffff, 0x000e000d,
 488         0x2484, 0xffffffff, 0x00110010,
 489         0x2485, 0xffffffff, 0x000a0009,
 490         0x2486, 0xffffffff, 0x000c000b,
 491         0x2487, 0xffffffff, 0x0000000f,
 492         0x2488, 0xffffffff, 0x000e000d,
 493         0x2489, 0xffffffff, 0x00110010,
 494         0x248a, 0xffffffff, 0x000b000a,
 495         0x248b, 0xffffffff, 0x000d000c,
 496         0x248c, 0xffffffff, 0x00000010,
 497         0x248d, 0xffffffff, 0x000f000e,
 498         0x248e, 0xffffffff, 0x00120011,
 499         0x248f, 0xffffffff, 0x000c000b,
 500         0x2490, 0xffffffff, 0x000e000d,
 501         0x2491, 0xffffffff, 0x00000011,
 502         0x2492, 0xffffffff, 0x0010000f,
 503         0x2493, 0xffffffff, 0x00130012,
 504         0x2494, 0xffffffff, 0x000d000c,
 505         0x2495, 0xffffffff, 0x000f000e,
 506         0x2496, 0xffffffff, 0x00100013,
 507         0x2497, 0xffffffff, 0x00120011,
 508         0x2498, 0xffffffff, 0x00150014,
 509         0x2499, 0xffffffff, 0x000e000d,
 510         0x249a, 0xffffffff, 0x0010000f,
 511         0x249b, 0xffffffff, 0x00000013,
 512         0x249c, 0xffffffff, 0x00120011,
 513         0x249d, 0xffffffff, 0x00150014,
 514         0x249e, 0xffffffff, 0x000f000e,
 515         0x249f, 0xffffffff, 0x00110010,
 516         0x24a0, 0xffffffff, 0x00000014,
 517         0x24a1, 0xffffffff, 0x00130012,
 518         0x24a2, 0xffffffff, 0x00160015,
 519         0x24a3, 0xffffffff, 0x0010000f,
 520         0x24a4, 0xffffffff, 0x00120011,
 521         0x24a5, 0xffffffff, 0x00000015,
 522         0x24a6, 0xffffffff, 0x00140013,
 523         0x24a7, 0xffffffff, 0x00170016,
 524         0x2454, 0xffffffff, 0x96940200,
 525         0x21c2, 0xffffffff, 0x00900100,
 526         0x311e, 0xffffffff, 0x00000080,
 527         0x3101, 0xffffffff, 0x0020003f,
 528         0x000c, 0xffffffff, 0x0000001c,
 529         0x000d, 0x000f0000, 0x000f0000,
 530         0x0583, 0xffffffff, 0x00000100,
 531         0x0409, 0xffffffff, 0x00000100,
 532         0x040b, 0x00000101, 0x00000000,
 533         0x082a, 0xffffffff, 0x00000104,
 534         0x0993, 0x000c0000, 0x000c0000,
 535         0x0992, 0x000c0000, 0x000c0000,
 536         0x1579, 0xff000fff, 0x00000100,
 537         0x157a, 0x00000001, 0x00000001,
 538         0x0bd4, 0x00000001, 0x00000001,
 539         0x0c33, 0xc0000fff, 0x00000104,
 540         0x3079, 0x00000001, 0x00000001,
 541         0x3430, 0xfffffff0, 0x00000100,
 542         0x3630, 0xfffffff0, 0x00000100
 543 };
 544 static const u32 pitcairn_mgcg_cgcg_init[] =
 545 {
 546         0x3100, 0xffffffff, 0xfffffffc,
 547         0x200b, 0xffffffff, 0xe0000000,
 548         0x2698, 0xffffffff, 0x00000100,
 549         0x24a9, 0xffffffff, 0x00000100,
 550         0x3059, 0xffffffff, 0x00000100,
 551         0x25dd, 0xffffffff, 0x00000100,
 552         0x2261, 0xffffffff, 0x06000100,
 553         0x2286, 0xffffffff, 0x00000100,
 554         0x24a8, 0xffffffff, 0x00000100,
 555         0x30e0, 0xffffffff, 0x00000100,
 556         0x22ca, 0xffffffff, 0x00000100,
 557         0x2451, 0xffffffff, 0x00000100,
 558         0x2362, 0xffffffff, 0x00000100,
 559         0x2363, 0xffffffff, 0x00000100,
 560         0x240c, 0xffffffff, 0x00000100,
 561         0x240d, 0xffffffff, 0x00000100,
 562         0x240e, 0xffffffff, 0x00000100,
 563         0x240f, 0xffffffff, 0x00000100,
 564         0x2b60, 0xffffffff, 0x00000100,
 565         0x2b15, 0xffffffff, 0x00000100,
 566         0x225f, 0xffffffff, 0x06000100,
 567         0x261a, 0xffffffff, 0x00000100,
 568         0x2544, 0xffffffff, 0x00000100,
 569         0x2bc1, 0xffffffff, 0x00000100,
 570         0x2b81, 0xffffffff, 0x00000100,
 571         0x2527, 0xffffffff, 0x00000100,
 572         0x200b, 0xffffffff, 0xe0000000,
 573         0x2458, 0xffffffff, 0x00010000,
 574         0x2459, 0xffffffff, 0x00030002,
 575         0x245a, 0xffffffff, 0x00040007,
 576         0x245b, 0xffffffff, 0x00060005,
 577         0x245c, 0xffffffff, 0x00090008,
 578         0x245d, 0xffffffff, 0x00020001,
 579         0x245e, 0xffffffff, 0x00040003,
 580         0x245f, 0xffffffff, 0x00000007,
 581         0x2460, 0xffffffff, 0x00060005,
 582         0x2461, 0xffffffff, 0x00090008,
 583         0x2462, 0xffffffff, 0x00030002,
 584         0x2463, 0xffffffff, 0x00050004,
 585         0x2464, 0xffffffff, 0x00000008,
 586         0x2465, 0xffffffff, 0x00070006,
 587         0x2466, 0xffffffff, 0x000a0009,
 588         0x2467, 0xffffffff, 0x00040003,
 589         0x2468, 0xffffffff, 0x00060005,
 590         0x2469, 0xffffffff, 0x00000009,
 591         0x246a, 0xffffffff, 0x00080007,
 592         0x246b, 0xffffffff, 0x000b000a,
 593         0x246c, 0xffffffff, 0x00050004,
 594         0x246d, 0xffffffff, 0x00070006,
 595         0x246e, 0xffffffff, 0x0008000b,
 596         0x246f, 0xffffffff, 0x000a0009,
 597         0x2470, 0xffffffff, 0x000d000c,
 598         0x2480, 0xffffffff, 0x00090008,
 599         0x2481, 0xffffffff, 0x000b000a,
 600         0x2482, 0xffffffff, 0x000c000f,
 601         0x2483, 0xffffffff, 0x000e000d,
 602         0x2484, 0xffffffff, 0x00110010,
 603         0x2485, 0xffffffff, 0x000a0009,
 604         0x2486, 0xffffffff, 0x000c000b,
 605         0x2487, 0xffffffff, 0x0000000f,
 606         0x2488, 0xffffffff, 0x000e000d,
 607         0x2489, 0xffffffff, 0x00110010,
 608         0x248a, 0xffffffff, 0x000b000a,
 609         0x248b, 0xffffffff, 0x000d000c,
 610         0x248c, 0xffffffff, 0x00000010,
 611         0x248d, 0xffffffff, 0x000f000e,
 612         0x248e, 0xffffffff, 0x00120011,
 613         0x248f, 0xffffffff, 0x000c000b,
 614         0x2490, 0xffffffff, 0x000e000d,
 615         0x2491, 0xffffffff, 0x00000011,
 616         0x2492, 0xffffffff, 0x0010000f,
 617         0x2493, 0xffffffff, 0x00130012,
 618         0x2494, 0xffffffff, 0x000d000c,
 619         0x2495, 0xffffffff, 0x000f000e,
 620         0x2496, 0xffffffff, 0x00100013,
 621         0x2497, 0xffffffff, 0x00120011,
 622         0x2498, 0xffffffff, 0x00150014,
 623         0x2454, 0xffffffff, 0x96940200,
 624         0x21c2, 0xffffffff, 0x00900100,
 625         0x311e, 0xffffffff, 0x00000080,
 626         0x3101, 0xffffffff, 0x0020003f,
 627         0x000c, 0xffffffff, 0x0000001c,
 628         0x000d, 0x000f0000, 0x000f0000,
 629         0x0583, 0xffffffff, 0x00000100,
 630         0x0409, 0xffffffff, 0x00000100,
 631         0x040b, 0x00000101, 0x00000000,
 632         0x082a, 0xffffffff, 0x00000104,
 633         0x1579, 0xff000fff, 0x00000100,
 634         0x157a, 0x00000001, 0x00000001,
 635         0x0bd4, 0x00000001, 0x00000001,
 636         0x0c33, 0xc0000fff, 0x00000104,
 637         0x3079, 0x00000001, 0x00000001,
 638         0x3430, 0xfffffff0, 0x00000100,
 639         0x3630, 0xfffffff0, 0x00000100
 640 };
 641 static const u32 verde_mgcg_cgcg_init[] =
 642 {
 643         0x3100, 0xffffffff, 0xfffffffc,
 644         0x200b, 0xffffffff, 0xe0000000,
 645         0x2698, 0xffffffff, 0x00000100,
 646         0x24a9, 0xffffffff, 0x00000100,
 647         0x3059, 0xffffffff, 0x00000100,
 648         0x25dd, 0xffffffff, 0x00000100,
 649         0x2261, 0xffffffff, 0x06000100,
 650         0x2286, 0xffffffff, 0x00000100,
 651         0x24a8, 0xffffffff, 0x00000100,
 652         0x30e0, 0xffffffff, 0x00000100,
 653         0x22ca, 0xffffffff, 0x00000100,
 654         0x2451, 0xffffffff, 0x00000100,
 655         0x2362, 0xffffffff, 0x00000100,
 656         0x2363, 0xffffffff, 0x00000100,
 657         0x240c, 0xffffffff, 0x00000100,
 658         0x240d, 0xffffffff, 0x00000100,
 659         0x240e, 0xffffffff, 0x00000100,
 660         0x240f, 0xffffffff, 0x00000100,
 661         0x2b60, 0xffffffff, 0x00000100,
 662         0x2b15, 0xffffffff, 0x00000100,
 663         0x225f, 0xffffffff, 0x06000100,
 664         0x261a, 0xffffffff, 0x00000100,
 665         0x2544, 0xffffffff, 0x00000100,
 666         0x2bc1, 0xffffffff, 0x00000100,
 667         0x2b81, 0xffffffff, 0x00000100,
 668         0x2527, 0xffffffff, 0x00000100,
 669         0x200b, 0xffffffff, 0xe0000000,
 670         0x2458, 0xffffffff, 0x00010000,
 671         0x2459, 0xffffffff, 0x00030002,
 672         0x245a, 0xffffffff, 0x00040007,
 673         0x245b, 0xffffffff, 0x00060005,
 674         0x245c, 0xffffffff, 0x00090008,
 675         0x245d, 0xffffffff, 0x00020001,
 676         0x245e, 0xffffffff, 0x00040003,
 677         0x245f, 0xffffffff, 0x00000007,
 678         0x2460, 0xffffffff, 0x00060005,
 679         0x2461, 0xffffffff, 0x00090008,
 680         0x2462, 0xffffffff, 0x00030002,
 681         0x2463, 0xffffffff, 0x00050004,
 682         0x2464, 0xffffffff, 0x00000008,
 683         0x2465, 0xffffffff, 0x00070006,
 684         0x2466, 0xffffffff, 0x000a0009,
 685         0x2467, 0xffffffff, 0x00040003,
 686         0x2468, 0xffffffff, 0x00060005,
 687         0x2469, 0xffffffff, 0x00000009,
 688         0x246a, 0xffffffff, 0x00080007,
 689         0x246b, 0xffffffff, 0x000b000a,
 690         0x246c, 0xffffffff, 0x00050004,
 691         0x246d, 0xffffffff, 0x00070006,
 692         0x246e, 0xffffffff, 0x0008000b,
 693         0x246f, 0xffffffff, 0x000a0009,
 694         0x2470, 0xffffffff, 0x000d000c,
 695         0x2480, 0xffffffff, 0x00090008,
 696         0x2481, 0xffffffff, 0x000b000a,
 697         0x2482, 0xffffffff, 0x000c000f,
 698         0x2483, 0xffffffff, 0x000e000d,
 699         0x2484, 0xffffffff, 0x00110010,
 700         0x2485, 0xffffffff, 0x000a0009,
 701         0x2486, 0xffffffff, 0x000c000b,
 702         0x2487, 0xffffffff, 0x0000000f,
 703         0x2488, 0xffffffff, 0x000e000d,
 704         0x2489, 0xffffffff, 0x00110010,
 705         0x248a, 0xffffffff, 0x000b000a,
 706         0x248b, 0xffffffff, 0x000d000c,
 707         0x248c, 0xffffffff, 0x00000010,
 708         0x248d, 0xffffffff, 0x000f000e,
 709         0x248e, 0xffffffff, 0x00120011,
 710         0x248f, 0xffffffff, 0x000c000b,
 711         0x2490, 0xffffffff, 0x000e000d,
 712         0x2491, 0xffffffff, 0x00000011,
 713         0x2492, 0xffffffff, 0x0010000f,
 714         0x2493, 0xffffffff, 0x00130012,
 715         0x2494, 0xffffffff, 0x000d000c,
 716         0x2495, 0xffffffff, 0x000f000e,
 717         0x2496, 0xffffffff, 0x00100013,
 718         0x2497, 0xffffffff, 0x00120011,
 719         0x2498, 0xffffffff, 0x00150014,
 720         0x2454, 0xffffffff, 0x96940200,
 721         0x21c2, 0xffffffff, 0x00900100,
 722         0x311e, 0xffffffff, 0x00000080,
 723         0x3101, 0xffffffff, 0x0020003f,
 724         0xc, 0xffffffff, 0x0000001c,
 725         0xd, 0x000f0000, 0x000f0000,
 726         0x583, 0xffffffff, 0x00000100,
 727         0x409, 0xffffffff, 0x00000100,
 728         0x40b, 0x00000101, 0x00000000,
 729         0x82a, 0xffffffff, 0x00000104,
 730         0x993, 0x000c0000, 0x000c0000,
 731         0x992, 0x000c0000, 0x000c0000,
 732         0x1579, 0xff000fff, 0x00000100,
 733         0x157a, 0x00000001, 0x00000001,
 734         0xbd4, 0x00000001, 0x00000001,
 735         0xc33, 0xc0000fff, 0x00000104,
 736         0x3079, 0x00000001, 0x00000001,
 737         0x3430, 0xfffffff0, 0x00000100,
 738         0x3630, 0xfffffff0, 0x00000100
 739 };
 740 static const u32 oland_mgcg_cgcg_init[] =
 741 {
 742         0x3100, 0xffffffff, 0xfffffffc,
 743         0x200b, 0xffffffff, 0xe0000000,
 744         0x2698, 0xffffffff, 0x00000100,
 745         0x24a9, 0xffffffff, 0x00000100,
 746         0x3059, 0xffffffff, 0x00000100,
 747         0x25dd, 0xffffffff, 0x00000100,
 748         0x2261, 0xffffffff, 0x06000100,
 749         0x2286, 0xffffffff, 0x00000100,
 750         0x24a8, 0xffffffff, 0x00000100,
 751         0x30e0, 0xffffffff, 0x00000100,
 752         0x22ca, 0xffffffff, 0x00000100,
 753         0x2451, 0xffffffff, 0x00000100,
 754         0x2362, 0xffffffff, 0x00000100,
 755         0x2363, 0xffffffff, 0x00000100,
 756         0x240c, 0xffffffff, 0x00000100,
 757         0x240d, 0xffffffff, 0x00000100,
 758         0x240e, 0xffffffff, 0x00000100,
 759         0x240f, 0xffffffff, 0x00000100,
 760         0x2b60, 0xffffffff, 0x00000100,
 761         0x2b15, 0xffffffff, 0x00000100,
 762         0x225f, 0xffffffff, 0x06000100,
 763         0x261a, 0xffffffff, 0x00000100,
 764         0x2544, 0xffffffff, 0x00000100,
 765         0x2bc1, 0xffffffff, 0x00000100,
 766         0x2b81, 0xffffffff, 0x00000100,
 767         0x2527, 0xffffffff, 0x00000100,
 768         0x200b, 0xffffffff, 0xe0000000,
 769         0x2458, 0xffffffff, 0x00010000,
 770         0x2459, 0xffffffff, 0x00030002,
 771         0x245a, 0xffffffff, 0x00040007,
 772         0x245b, 0xffffffff, 0x00060005,
 773         0x245c, 0xffffffff, 0x00090008,
 774         0x245d, 0xffffffff, 0x00020001,
 775         0x245e, 0xffffffff, 0x00040003,
 776         0x245f, 0xffffffff, 0x00000007,
 777         0x2460, 0xffffffff, 0x00060005,
 778         0x2461, 0xffffffff, 0x00090008,
 779         0x2462, 0xffffffff, 0x00030002,
 780         0x2463, 0xffffffff, 0x00050004,
 781         0x2464, 0xffffffff, 0x00000008,
 782         0x2465, 0xffffffff, 0x00070006,
 783         0x2466, 0xffffffff, 0x000a0009,
 784         0x2467, 0xffffffff, 0x00040003,
 785         0x2468, 0xffffffff, 0x00060005,
 786         0x2469, 0xffffffff, 0x00000009,
 787         0x246a, 0xffffffff, 0x00080007,
 788         0x246b, 0xffffffff, 0x000b000a,
 789         0x246c, 0xffffffff, 0x00050004,
 790         0x246d, 0xffffffff, 0x00070006,
 791         0x246e, 0xffffffff, 0x0008000b,
 792         0x246f, 0xffffffff, 0x000a0009,
 793         0x2470, 0xffffffff, 0x000d000c,
 794         0x2471, 0xffffffff, 0x00060005,
 795         0x2472, 0xffffffff, 0x00080007,
 796         0x2473, 0xffffffff, 0x0000000b,
 797         0x2474, 0xffffffff, 0x000a0009,
 798         0x2475, 0xffffffff, 0x000d000c,
 799         0x2454, 0xffffffff, 0x96940200,
 800         0x21c2, 0xffffffff, 0x00900100,
 801         0x311e, 0xffffffff, 0x00000080,
 802         0x3101, 0xffffffff, 0x0020003f,
 803         0xc, 0xffffffff, 0x0000001c,
 804         0xd, 0x000f0000, 0x000f0000,
 805         0x583, 0xffffffff, 0x00000100,
 806         0x409, 0xffffffff, 0x00000100,
 807         0x40b, 0x00000101, 0x00000000,
 808         0x82a, 0xffffffff, 0x00000104,
 809         0x993, 0x000c0000, 0x000c0000,
 810         0x992, 0x000c0000, 0x000c0000,
 811         0x1579, 0xff000fff, 0x00000100,
 812         0x157a, 0x00000001, 0x00000001,
 813         0xbd4, 0x00000001, 0x00000001,
 814         0xc33, 0xc0000fff, 0x00000104,
 815         0x3079, 0x00000001, 0x00000001,
 816         0x3430, 0xfffffff0, 0x00000100,
 817         0x3630, 0xfffffff0, 0x00000100
 818 };
 819 static const u32 hainan_mgcg_cgcg_init[] =
 820 {
 821         0x3100, 0xffffffff, 0xfffffffc,
 822         0x200b, 0xffffffff, 0xe0000000,
 823         0x2698, 0xffffffff, 0x00000100,
 824         0x24a9, 0xffffffff, 0x00000100,
 825         0x3059, 0xffffffff, 0x00000100,
 826         0x25dd, 0xffffffff, 0x00000100,
 827         0x2261, 0xffffffff, 0x06000100,
 828         0x2286, 0xffffffff, 0x00000100,
 829         0x24a8, 0xffffffff, 0x00000100,
 830         0x30e0, 0xffffffff, 0x00000100,
 831         0x22ca, 0xffffffff, 0x00000100,
 832         0x2451, 0xffffffff, 0x00000100,
 833         0x2362, 0xffffffff, 0x00000100,
 834         0x2363, 0xffffffff, 0x00000100,
 835         0x240c, 0xffffffff, 0x00000100,
 836         0x240d, 0xffffffff, 0x00000100,
 837         0x240e, 0xffffffff, 0x00000100,
 838         0x240f, 0xffffffff, 0x00000100,
 839         0x2b60, 0xffffffff, 0x00000100,
 840         0x2b15, 0xffffffff, 0x00000100,
 841         0x225f, 0xffffffff, 0x06000100,
 842         0x261a, 0xffffffff, 0x00000100,
 843         0x2544, 0xffffffff, 0x00000100,
 844         0x2bc1, 0xffffffff, 0x00000100,
 845         0x2b81, 0xffffffff, 0x00000100,
 846         0x2527, 0xffffffff, 0x00000100,
 847         0x200b, 0xffffffff, 0xe0000000,
 848         0x2458, 0xffffffff, 0x00010000,
 849         0x2459, 0xffffffff, 0x00030002,
 850         0x245a, 0xffffffff, 0x00040007,
 851         0x245b, 0xffffffff, 0x00060005,
 852         0x245c, 0xffffffff, 0x00090008,
 853         0x245d, 0xffffffff, 0x00020001,
 854         0x245e, 0xffffffff, 0x00040003,
 855         0x245f, 0xffffffff, 0x00000007,
 856         0x2460, 0xffffffff, 0x00060005,
 857         0x2461, 0xffffffff, 0x00090008,
 858         0x2462, 0xffffffff, 0x00030002,
 859         0x2463, 0xffffffff, 0x00050004,
 860         0x2464, 0xffffffff, 0x00000008,
 861         0x2465, 0xffffffff, 0x00070006,
 862         0x2466, 0xffffffff, 0x000a0009,
 863         0x2467, 0xffffffff, 0x00040003,
 864         0x2468, 0xffffffff, 0x00060005,
 865         0x2469, 0xffffffff, 0x00000009,
 866         0x246a, 0xffffffff, 0x00080007,
 867         0x246b, 0xffffffff, 0x000b000a,
 868         0x246c, 0xffffffff, 0x00050004,
 869         0x246d, 0xffffffff, 0x00070006,
 870         0x246e, 0xffffffff, 0x0008000b,
 871         0x246f, 0xffffffff, 0x000a0009,
 872         0x2470, 0xffffffff, 0x000d000c,
 873         0x2471, 0xffffffff, 0x00060005,
 874         0x2472, 0xffffffff, 0x00080007,
 875         0x2473, 0xffffffff, 0x0000000b,
 876         0x2474, 0xffffffff, 0x000a0009,
 877         0x2475, 0xffffffff, 0x000d000c,
 878         0x2454, 0xffffffff, 0x96940200,
 879         0x21c2, 0xffffffff, 0x00900100,
 880         0x311e, 0xffffffff, 0x00000080,
 881         0x3101, 0xffffffff, 0x0020003f,
 882         0xc, 0xffffffff, 0x0000001c,
 883         0xd, 0x000f0000, 0x000f0000,
 884         0x583, 0xffffffff, 0x00000100,
 885         0x409, 0xffffffff, 0x00000100,
 886         0x82a, 0xffffffff, 0x00000104,
 887         0x993, 0x000c0000, 0x000c0000,
 888         0x992, 0x000c0000, 0x000c0000,
 889         0xbd4, 0x00000001, 0x00000001,
 890         0xc33, 0xc0000fff, 0x00000104,
 891         0x3079, 0x00000001, 0x00000001,
 892         0x3430, 0xfffffff0, 0x00000100,
 893         0x3630, 0xfffffff0, 0x00000100
 894 };
 895
 896 static u32 si_pcie_rreg(struct amdgpu_device *adev, u32 reg)
 897 {
 898         unsigned long flags;
 899         u32 r;
 900
 901         spin_lock_irqsave(&adev->pcie_idx_lock, flags);
 902         WREG32(AMDGPU_PCIE_INDEX, reg);
 903         (void)RREG32(AMDGPU_PCIE_INDEX);
 904         r = RREG32(AMDGPU_PCIE_DATA);
 905         spin_unlock_irqrestore(&adev->pcie_idx_lock, flags);
 906         return r;
 907 }
 908
 909 static void si_pcie_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
 910 {
 911         unsigned long flags;
 912
 913         spin_lock_irqsave(&adev->pcie_idx_lock, flags);
 914         WREG32(AMDGPU_PCIE_INDEX, reg);
 915         (void)RREG32(AMDGPU_PCIE_INDEX);
 916         WREG32(AMDGPU_PCIE_DATA, v);
 917         (void)RREG32(AMDGPU_PCIE_DATA);
 918         spin_unlock_irqrestore(&adev->pcie_idx_lock, flags);
 919 }
 920
 921 static u32 si_pciep_rreg(struct amdgpu_device *adev, u32 reg)
 922 {
 923         unsigned long flags;
 924         u32 r;
 925
 926         spin_lock_irqsave(&adev->pcie_idx_lock, flags);
 927         WREG32(PCIE_PORT_INDEX, ((reg) & 0xff));
 928         (void)RREG32(PCIE_PORT_INDEX);
 929         r = RREG32(PCIE_PORT_DATA);
 930         spin_unlock_irqrestore(&adev->pcie_idx_lock, flags);
 931         return r;
 932 }
 933
 934 static void si_pciep_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
 935 {
 936         unsigned long flags;
 937
 938         spin_lock_irqsave(&adev->pcie_idx_lock, flags);
 939         WREG32(PCIE_PORT_INDEX, ((reg) & 0xff));
 940         (void)RREG32(PCIE_PORT_INDEX);
 941         WREG32(PCIE_PORT_DATA, (v));
 942         (void)RREG32(PCIE_PORT_DATA);
 943         spin_unlock_irqrestore(&adev->pcie_idx_lock, flags);
 944 }
 945
 946 static u32 si_smc_rreg(struct amdgpu_device *adev, u32 reg)
 947 {
 948         unsigned long flags;
 949         u32 r;
 950
 951         spin_lock_irqsave(&adev->smc_idx_lock, flags);
 952         WREG32(SMC_IND_INDEX_0, (reg));
 953         r = RREG32(SMC_IND_DATA_0);
 954         spin_unlock_irqrestore(&adev->smc_idx_lock, flags);
 955         return r;
 956 }
 957
 958 static void si_smc_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
 959 {
 960         unsigned long flags;
 961
 962         spin_lock_irqsave(&adev->smc_idx_lock, flags);
 963         WREG32(SMC_IND_INDEX_0, (reg));
 964         WREG32(SMC_IND_DATA_0, (v));
 965         spin_unlock_irqrestore(&adev->smc_idx_lock, flags);
 966 }
 967
 968 static struct amdgpu_allowed_register_entry si_allowed_read_registers[] = {
 969         {GRBM_STATUS, false},
 970         {GB_ADDR_CONFIG, false},
 971         {MC_ARB_RAMCFG, false},
 972         {GB_TILE_MODE0, false},
 973         {GB_TILE_MODE1, false},
 974         {GB_TILE_MODE2, false},
 975         {GB_TILE_MODE3, false},
 976         {GB_TILE_MODE4, false},
 977         {GB_TILE_MODE5, false},
 978         {GB_TILE_MODE6, false},
 979         {GB_TILE_MODE7, false},
 980         {GB_TILE_MODE8, false},
 981         {GB_TILE_MODE9, false},
 982         {GB_TILE_MODE10, false},
 983         {GB_TILE_MODE11, false},
 984         {GB_TILE_MODE12, false},
 985         {GB_TILE_MODE13, false},
 986         {GB_TILE_MODE14, false},
 987         {GB_TILE_MODE15, false},
 988         {GB_TILE_MODE16, false},
 989         {GB_TILE_MODE17, false},
 990         {GB_TILE_MODE18, false},
 991         {GB_TILE_MODE19, false},
 992         {GB_TILE_MODE20, false},
 993         {GB_TILE_MODE21, false},
 994         {GB_TILE_MODE22, false},
 995         {GB_TILE_MODE23, false},
 996         {GB_TILE_MODE24, false},
 997         {GB_TILE_MODE25, false},
 998         {GB_TILE_MODE26, false},
 999         {GB_TILE_MODE27, false},
1000         {GB_TILE_MODE28, false},
1001         {GB_TILE_MODE29, false},
1002         {GB_TILE_MODE30, false},
1003         {GB_TILE_MODE31, false},
1004         {CC_RB_BACKEND_DISABLE, false, true},
1005         {GC_USER_RB_BACKEND_DISABLE, false, true},
1006         {PA_SC_RASTER_CONFIG, false, true},
1007 };
1008
1009 static uint32_t si_read_indexed_register(struct amdgpu_device *adev,
1010                                           u32 se_num, u32 sh_num,
1011                                           u32 reg_offset)
1012 {
1013         uint32_t val;
1014
1015         mutex_lock(&adev->grbm_idx_mutex);
1016         if (se_num != 0xffffffff || sh_num != 0xffffffff)
1017                 amdgpu_gfx_select_se_sh(adev, se_num, sh_num, 0xffffffff);
1018
1019         val = RREG32(reg_offset);
1020
1021         if (se_num != 0xffffffff || sh_num != 0xffffffff)
1022                 amdgpu_gfx_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
1023         mutex_unlock(&adev->grbm_idx_mutex);
1024         return val;
1025 }
1026
1027 static int si_read_register(struct amdgpu_device *adev, u32 se_num,
1028                              u32 sh_num, u32 reg_offset, u32 *value)
1029 {
1030         uint32_t i;
1031
1032         *value = 0;
1033         for (i = 0; i < ARRAY_SIZE(si_allowed_read_registers); i++) {
1034                 if (reg_offset != si_allowed_read_registers[i].reg_offset)
1035                         continue;
1036
1037                 if (!si_allowed_read_registers[i].untouched)
1038                         *value = si_allowed_read_registers[i].grbm_indexed ?
1039                                  si_read_indexed_register(adev, se_num,
1040                                                            sh_num, reg_offset) :
1041                                  RREG32(reg_offset);
1042                 return 0;
1043         }
1044         return -EINVAL;
1045 }
1046
1047 static bool si_read_disabled_bios(struct amdgpu_device *adev)
1048 {
1049         u32 bus_cntl;
1050         u32 d1vga_control = 0;
1051         u32 d2vga_control = 0;
1052         u32 vga_render_control = 0;
1053         u32 rom_cntl;
1054         bool r;
1055
1056         bus_cntl = RREG32(R600_BUS_CNTL);
1057         if (adev->mode_info.num_crtc) {
1058                 d1vga_control = RREG32(AVIVO_D1VGA_CONTROL);
1059                 d2vga_control = RREG32(AVIVO_D2VGA_CONTROL);
1060                 vga_render_control = RREG32(VGA_RENDER_CONTROL);
1061         }
1062         rom_cntl = RREG32(R600_ROM_CNTL);
1063
1064         /* enable the rom */
1065         WREG32(R600_BUS_CNTL, (bus_cntl & ~R600_BIOS_ROM_DIS));
1066         if (adev->mode_info.num_crtc) {
1067                 /* Disable VGA mode */
1068                 WREG32(AVIVO_D1VGA_CONTROL,
1069                        (d1vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE |
1070                                           AVIVO_DVGA_CONTROL_TIMING_SELECT)));
1071                 WREG32(AVIVO_D2VGA_CONTROL,
1072                        (d2vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE |
1073                                           AVIVO_DVGA_CONTROL_TIMING_SELECT)));
1074                 WREG32(VGA_RENDER_CONTROL,
1075                        (vga_render_control & C_000300_VGA_VSTATUS_CNTL));
1076         }
1077         WREG32(R600_ROM_CNTL, rom_cntl | R600_SCK_OVERWRITE);
1078
1079         r = amdgpu_read_bios(adev);
1080
1081         /* restore regs */
1082         WREG32(R600_BUS_CNTL, bus_cntl);
1083         if (adev->mode_info.num_crtc) {
1084                 WREG32(AVIVO_D1VGA_CONTROL, d1vga_control);
1085                 WREG32(AVIVO_D2VGA_CONTROL, d2vga_control);
1086                 WREG32(VGA_RENDER_CONTROL, vga_render_control);
1087         }
1088         WREG32(R600_ROM_CNTL, rom_cntl);
1089         return r;
1090 }
1091
1092 //xxx: not implemented
1093 static int si_asic_reset(struct amdgpu_device *adev)
1094 {
1095         return 0;
1096 }
1097
1098 static void si_vga_set_state(struct amdgpu_device *adev, bool state)
1099 {
1100         uint32_t temp;
1101
1102         temp = RREG32(CONFIG_CNTL);
1103         if (state == false) {
1104                 temp &= ~(1<<0);
1105                 temp |= (1<<1);
1106         } else {
1107                 temp &= ~(1<<1);
1108         }
1109         WREG32(CONFIG_CNTL, temp);
1110 }
1111
1112 static u32 si_get_xclk(struct amdgpu_device *adev)
1113 {
1114         u32 reference_clock = adev->clock.spll.reference_freq;
1115         u32 tmp;
1116
1117         tmp = RREG32(CG_CLKPIN_CNTL_2);
1118         if (tmp & MUX_TCLK_TO_XCLK)
1119                 return TCLK;
1120
1121         tmp = RREG32(CG_CLKPIN_CNTL);
1122         if (tmp & XTALIN_DIVIDE)
1123                 return reference_clock / 4;
1124
1125         return reference_clock;
1126 }
1127
1128 //xxx:not implemented
1129 static int si_set_uvd_clocks(struct amdgpu_device *adev, u32 vclk, u32 dclk)
1130 {
1131         return 0;
1132 }
1133
1134 static void si_detect_hw_virtualization(struct amdgpu_device *adev)
1135 {
1136         if (is_virtual_machine()) /* passthrough mode */
1137                 adev->virtualization.virtual_caps |= AMDGPU_PASSTHROUGH_MODE;
1138 }
1139
1140 static const struct amdgpu_asic_funcs si_asic_funcs =
1141 {
1142         .read_disabled_bios = &si_read_disabled_bios,
1143         .detect_hw_virtualization = si_detect_hw_virtualization,
1144         .read_register = &si_read_register,
1145         .reset = &si_asic_reset,
1146         .set_vga_state = &si_vga_set_state,
1147         .get_xclk = &si_get_xclk,
1148         .set_uvd_clocks = &si_set_uvd_clocks,
1149         .set_vce_clocks = NULL,
1150 };
1151
1152 static uint32_t si_get_rev_id(struct amdgpu_device *adev)
1153 {
1154         return (RREG32(CC_DRM_ID_STRAPS) & CC_DRM_ID_STRAPS__ATI_REV_ID_MASK)
1155                 >> CC_DRM_ID_STRAPS__ATI_REV_ID__SHIFT;
1156 }
1157
1158 static int si_common_early_init(void *handle)
1159 {
1160         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1161
1162         adev->smc_rreg = &si_smc_rreg;
1163         adev->smc_wreg = &si_smc_wreg;
1164         adev->pcie_rreg = &si_pcie_rreg;
1165         adev->pcie_wreg = &si_pcie_wreg;
1166         adev->pciep_rreg = &si_pciep_rreg;
1167         adev->pciep_wreg = &si_pciep_wreg;
1168         adev->uvd_ctx_rreg = NULL;
1169         adev->uvd_ctx_wreg = NULL;
1170         adev->didt_rreg = NULL;
1171         adev->didt_wreg = NULL;
1172
1173         adev->asic_funcs = &si_asic_funcs;
1174
1175         adev->rev_id = si_get_rev_id(adev);
1176         adev->external_rev_id = 0xFF;
1177         switch (adev->asic_type) {
1178         case CHIP_TAHITI:
1179                 adev->cg_flags =
1180                         AMD_CG_SUPPORT_GFX_MGCG |
1181                         AMD_CG_SUPPORT_GFX_MGLS |
1182                         /*AMD_CG_SUPPORT_GFX_CGCG |*/
1183                         AMD_CG_SUPPORT_GFX_CGLS |
1184                         AMD_CG_SUPPORT_GFX_CGTS |
1185                         AMD_CG_SUPPORT_GFX_CP_LS |
1186                         AMD_CG_SUPPORT_MC_MGCG |
1187                         AMD_CG_SUPPORT_SDMA_MGCG |
1188                         AMD_CG_SUPPORT_BIF_LS |
1189                         AMD_CG_SUPPORT_VCE_MGCG |
1190                         AMD_CG_SUPPORT_UVD_MGCG |
1191                         AMD_CG_SUPPORT_HDP_LS |
1192                         AMD_CG_SUPPORT_HDP_MGCG;
1193                         adev->pg_flags = 0;
1194                 adev->external_rev_id = (adev->rev_id == 0) ? 1 :
1195                                         (adev->rev_id == 1) ? 5 : 6;
1196                 break;
1197         case CHIP_PITCAIRN:
1198                 adev->cg_flags =
1199                         AMD_CG_SUPPORT_GFX_MGCG |
1200                         AMD_CG_SUPPORT_GFX_MGLS |
1201                         /*AMD_CG_SUPPORT_GFX_CGCG |*/
1202                         AMD_CG_SUPPORT_GFX_CGLS |
1203                         AMD_CG_SUPPORT_GFX_CGTS |
1204                         AMD_CG_SUPPORT_GFX_CP_LS |
1205                         AMD_CG_SUPPORT_GFX_RLC_LS |
1206                         AMD_CG_SUPPORT_MC_LS |
1207                         AMD_CG_SUPPORT_MC_MGCG |
1208                         AMD_CG_SUPPORT_SDMA_MGCG |
1209                         AMD_CG_SUPPORT_BIF_LS |
1210                         AMD_CG_SUPPORT_VCE_MGCG |
1211                         AMD_CG_SUPPORT_UVD_MGCG |
1212                         AMD_CG_SUPPORT_HDP_LS |
1213                         AMD_CG_SUPPORT_HDP_MGCG;
1214                 adev->pg_flags = 0;
1215                 adev->external_rev_id = adev->rev_id + 20;
1216                 break;
1217
1218         case CHIP_VERDE:
1219                 adev->cg_flags =
1220                         AMD_CG_SUPPORT_GFX_MGCG |
1221                         AMD_CG_SUPPORT_GFX_MGLS |
1222                         AMD_CG_SUPPORT_GFX_CGLS |
1223                         AMD_CG_SUPPORT_GFX_CGTS |
1224                         AMD_CG_SUPPORT_GFX_CGTS_LS |
1225                         AMD_CG_SUPPORT_GFX_CP_LS |
1226                         AMD_CG_SUPPORT_MC_LS |
1227                         AMD_CG_SUPPORT_MC_MGCG |
1228                         AMD_CG_SUPPORT_SDMA_MGCG |
1229                         AMD_CG_SUPPORT_SDMA_LS |
1230                         AMD_CG_SUPPORT_BIF_LS |
1231                         AMD_CG_SUPPORT_VCE_MGCG |
1232                         AMD_CG_SUPPORT_UVD_MGCG |
1233                         AMD_CG_SUPPORT_HDP_LS |
1234                         AMD_CG_SUPPORT_HDP_MGCG;
1235                 adev->pg_flags = 0;
1236                 //???
1237                 adev->external_rev_id = adev->rev_id + 0x14;
1238                 break;
1239         case CHIP_OLAND:
1240                 adev->cg_flags =
1241                         AMD_CG_SUPPORT_GFX_MGCG |
1242                         AMD_CG_SUPPORT_GFX_MGLS |
1243                         /*AMD_CG_SUPPORT_GFX_CGCG |*/
1244                         AMD_CG_SUPPORT_GFX_CGLS |
1245                         AMD_CG_SUPPORT_GFX_CGTS |
1246                         AMD_CG_SUPPORT_GFX_CP_LS |
1247                         AMD_CG_SUPPORT_GFX_RLC_LS |
1248                         AMD_CG_SUPPORT_MC_LS |
1249                         AMD_CG_SUPPORT_MC_MGCG |
1250                         AMD_CG_SUPPORT_SDMA_MGCG |
1251                         AMD_CG_SUPPORT_BIF_LS |
1252                         AMD_CG_SUPPORT_UVD_MGCG |
1253                         AMD_CG_SUPPORT_HDP_LS |
1254                         AMD_CG_SUPPORT_HDP_MGCG;
1255                 adev->pg_flags = 0;
1256                 break;
1257         case CHIP_HAINAN:
1258                 adev->cg_flags =
1259                         AMD_CG_SUPPORT_GFX_MGCG |
1260                         AMD_CG_SUPPORT_GFX_MGLS |
1261                         /*AMD_CG_SUPPORT_GFX_CGCG |*/
1262                         AMD_CG_SUPPORT_GFX_CGLS |
1263                         AMD_CG_SUPPORT_GFX_CGTS |
1264                         AMD_CG_SUPPORT_GFX_CP_LS |
1265                         AMD_CG_SUPPORT_GFX_RLC_LS |
1266                         AMD_CG_SUPPORT_MC_LS |
1267                         AMD_CG_SUPPORT_MC_MGCG |
1268                         AMD_CG_SUPPORT_SDMA_MGCG |
1269                         AMD_CG_SUPPORT_BIF_LS |
1270                         AMD_CG_SUPPORT_HDP_LS |
1271                         AMD_CG_SUPPORT_HDP_MGCG;
1272                 adev->pg_flags = 0;
1273                 break;
1274
1275         default:
1276                 return -EINVAL;
1277         }
1278
1279         return 0;
1280 }
1281
1282 static int si_common_sw_init(void *handle)
1283 {
1284         return 0;
1285 }
1286
1287 static int si_common_sw_fini(void *handle)
1288 {
1289         return 0;
1290 }
1291
1292
1293 static void si_init_golden_registers(struct amdgpu_device *adev)
1294 {
1295         switch (adev->asic_type) {
1296         case CHIP_TAHITI:
1297                 amdgpu_program_register_sequence(adev,
1298                                                  tahiti_golden_registers,
1299                                                  (const u32)ARRAY_SIZE(tahiti_golden_registers));
1300                 amdgpu_program_register_sequence(adev,
1301                                                  tahiti_golden_rlc_registers,
1302                                                  (const u32)ARRAY_SIZE(tahiti_golden_rlc_registers));
1303                 amdgpu_program_register_sequence(adev,
1304                                                  tahiti_mgcg_cgcg_init,
1305                                                  (const u32)ARRAY_SIZE(tahiti_mgcg_cgcg_init));
1306                 amdgpu_program_register_sequence(adev,
1307                                                  tahiti_golden_registers2,
1308                                                  (const u32)ARRAY_SIZE(tahiti_golden_registers2));
1309                 break;
1310         case CHIP_PITCAIRN:
1311                 amdgpu_program_register_sequence(adev,
1312                                                  pitcairn_golden_registers,
1313                                                  (const u32)ARRAY_SIZE(pitcairn_golden_registers));
1314                 amdgpu_program_register_sequence(adev,
1315                                                  pitcairn_golden_rlc_registers,
1316                                                  (const u32)ARRAY_SIZE(pitcairn_golden_rlc_registers));
1317                 amdgpu_program_register_sequence(adev,
1318                                                  pitcairn_mgcg_cgcg_init,
1319                                                  (const u32)ARRAY_SIZE(pitcairn_mgcg_cgcg_init));
1320         case CHIP_VERDE:
1321                 amdgpu_program_register_sequence(adev,
1322                                                  verde_golden_registers,
1323                                                  (const u32)ARRAY_SIZE(verde_golden_registers));
1324                 amdgpu_program_register_sequence(adev,
1325                                                  verde_golden_rlc_registers,
1326                                                  (const u32)ARRAY_SIZE(verde_golden_rlc_registers));
1327                 amdgpu_program_register_sequence(adev,
1328                                                  verde_mgcg_cgcg_init,
1329                                                  (const u32)ARRAY_SIZE(verde_mgcg_cgcg_init));
1330                 amdgpu_program_register_sequence(adev,
1331                                                  verde_pg_init,
1332                                                  (const u32)ARRAY_SIZE(verde_pg_init));
1333                 break;
1334         case CHIP_OLAND:
1335                 amdgpu_program_register_sequence(adev,
1336                                                  oland_golden_registers,
1337                                                  (const u32)ARRAY_SIZE(oland_golden_registers));
1338                 amdgpu_program_register_sequence(adev,
1339                                                  oland_golden_rlc_registers,
1340                                                  (const u32)ARRAY_SIZE(oland_golden_rlc_registers));
1341                 amdgpu_program_register_sequence(adev,
1342                                                  oland_mgcg_cgcg_init,
1343                                                  (const u32)ARRAY_SIZE(oland_mgcg_cgcg_init));
1344         case CHIP_HAINAN:
1345                 amdgpu_program_register_sequence(adev,
1346                                                  hainan_golden_registers,
1347                                                  (const u32)ARRAY_SIZE(hainan_golden_registers));
1348                 amdgpu_program_register_sequence(adev,
1349                                                  hainan_golden_registers2,
1350                                                  (const u32)ARRAY_SIZE(hainan_golden_registers2));
1351                 amdgpu_program_register_sequence(adev,
1352                                                  hainan_mgcg_cgcg_init,
1353                                                  (const u32)ARRAY_SIZE(hainan_mgcg_cgcg_init));
1354                 break;
1355
1356
1357         default:
1358                 BUG();
1359         }
1360 }
1361
1362 static void si_pcie_gen3_enable(struct amdgpu_device *adev)
1363 {
1364         struct pci_dev *root = adev->pdev->bus->self;
1365         int bridge_pos, gpu_pos;
1366         u32 speed_cntl, mask, current_data_rate;
1367         int ret, i;
1368         u16 tmp16;
1369
1370         if (pci_is_root_bus(adev->pdev->bus))
1371                 return;
1372
1373         if (amdgpu_pcie_gen2 == 0)
1374                 return;
1375
1376         if (adev->flags & AMD_IS_APU)
1377                 return;
1378
1379         ret = drm_pcie_get_speed_cap_mask(adev->ddev, &mask);
1380         if (ret != 0)
1381                 return;
1382
1383         if (!(mask & (DRM_PCIE_SPEED_50 | DRM_PCIE_SPEED_80)))
1384                 return;
1385
1386         speed_cntl = RREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL);
1387         current_data_rate = (speed_cntl & LC_CURRENT_DATA_RATE_MASK) >>
1388                 LC_CURRENT_DATA_RATE_SHIFT;
1389         if (mask & DRM_PCIE_SPEED_80) {
1390                 if (current_data_rate == 2) {
1391                         DRM_INFO("PCIE gen 3 link speeds already enabled\n");
1392                         return;
1393                 }
1394                 DRM_INFO("enabling PCIE gen 3 link speeds, disable with amdgpu.pcie_gen2=0\n");
1395         } else if (mask & DRM_PCIE_SPEED_50) {
1396                 if (current_data_rate == 1) {
1397                         DRM_INFO("PCIE gen 2 link speeds already enabled\n");
1398                         return;
1399                 }
1400                 DRM_INFO("enabling PCIE gen 2 link speeds, disable with amdgpu.pcie_gen2=0\n");
1401         }
1402
1403         bridge_pos = pci_pcie_cap(root);
1404         if (!bridge_pos)
1405                 return;
1406
1407         gpu_pos = pci_pcie_cap(adev->pdev);
1408         if (!gpu_pos)
1409                 return;
1410
1411         if (mask & DRM_PCIE_SPEED_80) {
1412                 if (current_data_rate != 2) {
1413                         u16 bridge_cfg, gpu_cfg;
1414                         u16 bridge_cfg2, gpu_cfg2;
1415                         u32 max_lw, current_lw, tmp;
1416
1417                         pci_read_config_word(root, bridge_pos + PCI_EXP_LNKCTL, &bridge_cfg);
1418                         pci_read_config_word(adev->pdev, gpu_pos + PCI_EXP_LNKCTL, &gpu_cfg);
1419
1420                         tmp16 = bridge_cfg | PCI_EXP_LNKCTL_HAWD;
1421                         pci_write_config_word(root, bridge_pos + PCI_EXP_LNKCTL, tmp16);
1422
1423                         tmp16 = gpu_cfg | PCI_EXP_LNKCTL_HAWD;
1424                         pci_write_config_word(adev->pdev, gpu_pos + PCI_EXP_LNKCTL, tmp16);
1425
1426                         tmp = RREG32_PCIE(PCIE_LC_STATUS1);
1427                         max_lw = (tmp & LC_DETECTED_LINK_WIDTH_MASK) >> LC_DETECTED_LINK_WIDTH_SHIFT;
1428                         current_lw = (tmp & LC_OPERATING_LINK_WIDTH_MASK) >> LC_OPERATING_LINK_WIDTH_SHIFT;
1429
1430                         if (current_lw < max_lw) {
1431                                 tmp = RREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL);
1432                                 if (tmp & LC_RENEGOTIATION_SUPPORT) {
1433                                         tmp &= ~(LC_LINK_WIDTH_MASK | LC_UPCONFIGURE_DIS);
1434                                         tmp |= (max_lw << LC_LINK_WIDTH_SHIFT);
1435                                         tmp |= LC_UPCONFIGURE_SUPPORT | LC_RENEGOTIATE_EN | LC_RECONFIG_NOW;
1436                                         WREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL, tmp);
1437                                 }
1438                         }
1439
1440                         for (i = 0; i < 10; i++) {
1441                                 pci_read_config_word(adev->pdev, gpu_pos + PCI_EXP_DEVSTA, &tmp16);
1442                                 if (tmp16 & PCI_EXP_DEVSTA_TRPND)
1443                                         break;
1444
1445                                 pci_read_config_word(root, bridge_pos + PCI_EXP_LNKCTL, &bridge_cfg);
1446                                 pci_read_config_word(adev->pdev, gpu_pos + PCI_EXP_LNKCTL, &gpu_cfg);
1447
1448                                 pci_read_config_word(root, bridge_pos + PCI_EXP_LNKCTL2, &bridge_cfg2);
1449                                 pci_read_config_word(adev->pdev, gpu_pos + PCI_EXP_LNKCTL2, &gpu_cfg2);
1450
1451                                 tmp = RREG32_PCIE_PORT(PCIE_LC_CNTL4);
1452                                 tmp |= LC_SET_QUIESCE;
1453                                 WREG32_PCIE_PORT(PCIE_LC_CNTL4, tmp);
1454
1455                                 tmp = RREG32_PCIE_PORT(PCIE_LC_CNTL4);
1456                                 tmp |= LC_REDO_EQ;
1457                                 WREG32_PCIE_PORT(PCIE_LC_CNTL4, tmp);
1458
1459                                 mdelay(100);
1460
1461                                 pci_read_config_word(root, bridge_pos + PCI_EXP_LNKCTL, &tmp16);
1462                                 tmp16 &= ~PCI_EXP_LNKCTL_HAWD;
1463                                 tmp16 |= (bridge_cfg & PCI_EXP_LNKCTL_HAWD);
1464                                 pci_write_config_word(root, bridge_pos + PCI_EXP_LNKCTL, tmp16);
1465
1466                                 pci_read_config_word(adev->pdev, gpu_pos + PCI_EXP_LNKCTL, &tmp16);
1467                                 tmp16 &= ~PCI_EXP_LNKCTL_HAWD;
1468                                 tmp16 |= (gpu_cfg & PCI_EXP_LNKCTL_HAWD);
1469                                 pci_write_config_word(adev->pdev, gpu_pos + PCI_EXP_LNKCTL, tmp16);
1470
1471                                 pci_read_config_word(root, bridge_pos + PCI_EXP_LNKCTL2, &tmp16);
1472                                 tmp16 &= ~((1 << 4) | (7 << 9));
1473                                 tmp16 |= (bridge_cfg2 & ((1 << 4) | (7 << 9)));
1474                                 pci_write_config_word(root, bridge_pos + PCI_EXP_LNKCTL2, tmp16);
1475
1476                                 pci_read_config_word(adev->pdev, gpu_pos + PCI_EXP_LNKCTL2, &tmp16);
1477                                 tmp16 &= ~((1 << 4) | (7 << 9));
1478                                 tmp16 |= (gpu_cfg2 & ((1 << 4) | (7 << 9)));
1479                                 pci_write_config_word(adev->pdev, gpu_pos + PCI_EXP_LNKCTL2, tmp16);
1480
1481                                 tmp = RREG32_PCIE_PORT(PCIE_LC_CNTL4);
1482                                 tmp &= ~LC_SET_QUIESCE;
1483                                 WREG32_PCIE_PORT(PCIE_LC_CNTL4, tmp);
1484                         }
1485                 }
1486         }
1487
1488         speed_cntl |= LC_FORCE_EN_SW_SPEED_CHANGE | LC_FORCE_DIS_HW_SPEED_CHANGE;
1489         speed_cntl &= ~LC_FORCE_DIS_SW_SPEED_CHANGE;
1490         WREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL, speed_cntl);
1491
1492         pci_read_config_word(adev->pdev, gpu_pos + PCI_EXP_LNKCTL2, &tmp16);
1493         tmp16 &= ~0xf;
1494         if (mask & DRM_PCIE_SPEED_80)
1495                 tmp16 |= 3;
1496         else if (mask & DRM_PCIE_SPEED_50)
1497                 tmp16 |= 2;
1498         else
1499                 tmp16 |= 1;
1500         pci_write_config_word(adev->pdev, gpu_pos + PCI_EXP_LNKCTL2, tmp16);
1501
1502         speed_cntl = RREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL);
1503         speed_cntl |= LC_INITIATE_LINK_SPEED_CHANGE;
1504         WREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL, speed_cntl);
1505
1506         for (i = 0; i < adev->usec_timeout; i++) {
1507                 speed_cntl = RREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL);
1508                 if ((speed_cntl & LC_INITIATE_LINK_SPEED_CHANGE) == 0)
1509                         break;
1510                 udelay(1);
1511         }
1512 }
1513
1514 static inline u32 si_pif_phy0_rreg(struct amdgpu_device *adev, u32 reg)
1515 {
1516         unsigned long flags;
1517         u32 r;
1518
1519         spin_lock_irqsave(&adev->pcie_idx_lock, flags);
1520         WREG32(EVERGREEN_PIF_PHY0_INDEX, ((reg) & 0xffff));
1521         r = RREG32(EVERGREEN_PIF_PHY0_DATA);
1522         spin_unlock_irqrestore(&adev->pcie_idx_lock, flags);
1523         return r;
1524 }
1525
1526 static inline void si_pif_phy0_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
1527 {
1528         unsigned long flags;
1529
1530         spin_lock_irqsave(&adev->pcie_idx_lock, flags);
1531         WREG32(EVERGREEN_PIF_PHY0_INDEX, ((reg) & 0xffff));
1532         WREG32(EVERGREEN_PIF_PHY0_DATA, (v));
1533         spin_unlock_irqrestore(&adev->pcie_idx_lock, flags);
1534 }
1535
1536 static inline u32 si_pif_phy1_rreg(struct amdgpu_device *adev, u32 reg)
1537 {
1538         unsigned long flags;
1539         u32 r;
1540
1541         spin_lock_irqsave(&adev->pcie_idx_lock, flags);
1542         WREG32(EVERGREEN_PIF_PHY1_INDEX, ((reg) & 0xffff));
1543         r = RREG32(EVERGREEN_PIF_PHY1_DATA);
1544         spin_unlock_irqrestore(&adev->pcie_idx_lock, flags);
1545         return r;
1546 }
1547
1548 static inline void si_pif_phy1_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
1549 {
1550         unsigned long flags;
1551
1552         spin_lock_irqsave(&adev->pcie_idx_lock, flags);
1553         WREG32(EVERGREEN_PIF_PHY1_INDEX, ((reg) & 0xffff));
1554         WREG32(EVERGREEN_PIF_PHY1_DATA, (v));
1555         spin_unlock_irqrestore(&adev->pcie_idx_lock, flags);
1556 }
1557 static void si_program_aspm(struct amdgpu_device *adev)
1558 {
1559         u32 data, orig;
1560         bool disable_l0s = false, disable_l1 = false, disable_plloff_in_l1 = false;
1561         bool disable_clkreq = false;
1562
1563         if (amdgpu_aspm == 0)
1564                 return;
1565
1566         if (adev->flags & AMD_IS_APU)
1567                 return;
1568         orig = data = RREG32_PCIE_PORT(PCIE_LC_N_FTS_CNTL);
1569         data &= ~LC_XMIT_N_FTS_MASK;
1570         data |= LC_XMIT_N_FTS(0x24) | LC_XMIT_N_FTS_OVERRIDE_EN;
1571         if (orig != data)
1572                 WREG32_PCIE_PORT(PCIE_LC_N_FTS_CNTL, data);
1573
1574         orig = data = RREG32_PCIE_PORT(PCIE_LC_CNTL3);
1575         data |= LC_GO_TO_RECOVERY;
1576         if (orig != data)
1577                 WREG32_PCIE_PORT(PCIE_LC_CNTL3, data);
1578
1579         orig = data = RREG32_PCIE(PCIE_P_CNTL);
1580         data |= P_IGNORE_EDB_ERR;
1581         if (orig != data)
1582                 WREG32_PCIE(PCIE_P_CNTL, data);
1583
1584         orig = data = RREG32_PCIE_PORT(PCIE_LC_CNTL);
1585         data &= ~(LC_L0S_INACTIVITY_MASK | LC_L1_INACTIVITY_MASK);
1586         data |= LC_PMI_TO_L1_DIS;
1587         if (!disable_l0s)
1588                 data |= LC_L0S_INACTIVITY(7);
1589
1590         if (!disable_l1) {
1591                 data |= LC_L1_INACTIVITY(7);
1592                 data &= ~LC_PMI_TO_L1_DIS;
1593                 if (orig != data)
1594                         WREG32_PCIE_PORT(PCIE_LC_CNTL, data);
1595
1596                 if (!disable_plloff_in_l1) {
1597                         bool clk_req_support;
1598
1599                         orig = data = si_pif_phy0_rreg(adev,PB0_PIF_PWRDOWN_0);
1600                         data &= ~(PLL_POWER_STATE_IN_OFF_0_MASK | PLL_POWER_STATE_IN_TXS2_0_MASK);
1601                         data |= PLL_POWER_STATE_IN_OFF_0(7) | PLL_POWER_STATE_IN_TXS2_0(7);
1602                         if (orig != data)
1603                                 si_pif_phy0_wreg(adev,PB0_PIF_PWRDOWN_0, data);
1604
1605                         orig = data = si_pif_phy0_rreg(adev,PB0_PIF_PWRDOWN_1);
1606                         data &= ~(PLL_POWER_STATE_IN_OFF_1_MASK | PLL_POWER_STATE_IN_TXS2_1_MASK);
1607                         data |= PLL_POWER_STATE_IN_OFF_1(7) | PLL_POWER_STATE_IN_TXS2_1(7);
1608                         if (orig != data)
1609                                 si_pif_phy0_wreg(adev,PB0_PIF_PWRDOWN_1, data);
1610
1611                         orig = data = si_pif_phy1_rreg(adev,PB1_PIF_PWRDOWN_0);
1612                         data &= ~(PLL_POWER_STATE_IN_OFF_0_MASK | PLL_POWER_STATE_IN_TXS2_0_MASK);
1613                         data |= PLL_POWER_STATE_IN_OFF_0(7) | PLL_POWER_STATE_IN_TXS2_0(7);
1614                         if (orig != data)
1615                                 si_pif_phy1_wreg(adev,PB1_PIF_PWRDOWN_0, data);
1616
1617                         orig = data = si_pif_phy1_rreg(adev,PB1_PIF_PWRDOWN_1);
1618                         data &= ~(PLL_POWER_STATE_IN_OFF_1_MASK | PLL_POWER_STATE_IN_TXS2_1_MASK);
1619                         data |= PLL_POWER_STATE_IN_OFF_1(7) | PLL_POWER_STATE_IN_TXS2_1(7);
1620                         if (orig != data)
1621                                 si_pif_phy1_wreg(adev,PB1_PIF_PWRDOWN_1, data);
1622
1623                         if ((adev->family != CHIP_OLAND) && (adev->family != CHIP_HAINAN)) {
1624                                 orig = data = si_pif_phy0_rreg(adev,PB0_PIF_PWRDOWN_0);
1625                                 data &= ~PLL_RAMP_UP_TIME_0_MASK;
1626                                 if (orig != data)
1627                                         si_pif_phy0_wreg(adev,PB0_PIF_PWRDOWN_0, data);
1628
1629                                 orig = data = si_pif_phy0_rreg(adev,PB0_PIF_PWRDOWN_1);
1630                                 data &= ~PLL_RAMP_UP_TIME_1_MASK;
1631                                 if (orig != data)
1632                                         si_pif_phy0_wreg(adev,PB0_PIF_PWRDOWN_1, data);
1633
1634                                 orig = data = si_pif_phy0_rreg(adev,PB0_PIF_PWRDOWN_2);
1635                                 data &= ~PLL_RAMP_UP_TIME_2_MASK;
1636                                 if (orig != data)
1637                                         si_pif_phy0_wreg(adev,PB0_PIF_PWRDOWN_2, data);
1638
1639                                 orig = data = si_pif_phy0_rreg(adev,PB0_PIF_PWRDOWN_3);
1640                                 data &= ~PLL_RAMP_UP_TIME_3_MASK;
1641                                 if (orig != data)
1642                                         si_pif_phy0_wreg(adev,PB0_PIF_PWRDOWN_3, data);
1643
1644                                 orig = data = si_pif_phy1_rreg(adev,PB1_PIF_PWRDOWN_0);
1645                                 data &= ~PLL_RAMP_UP_TIME_0_MASK;
1646                                 if (orig != data)
1647                                         si_pif_phy1_wreg(adev,PB1_PIF_PWRDOWN_0, data);
1648
1649                                 orig = data = si_pif_phy1_rreg(adev,PB1_PIF_PWRDOWN_1);
1650                                 data &= ~PLL_RAMP_UP_TIME_1_MASK;
1651                                 if (orig != data)
1652                                         si_pif_phy1_wreg(adev,PB1_PIF_PWRDOWN_1, data);
1653
1654                                 orig = data = si_pif_phy1_rreg(adev,PB1_PIF_PWRDOWN_2);
1655                                 data &= ~PLL_RAMP_UP_TIME_2_MASK;
1656                                 if (orig != data)
1657                                         si_pif_phy1_wreg(adev,PB1_PIF_PWRDOWN_2, data);
1658
1659                                 orig = data = si_pif_phy1_rreg(adev,PB1_PIF_PWRDOWN_3);
1660                                 data &= ~PLL_RAMP_UP_TIME_3_MASK;
1661                                 if (orig != data)
1662                                         si_pif_phy1_wreg(adev,PB1_PIF_PWRDOWN_3, data);
1663                         }
1664                         orig = data = RREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL);
1665                         data &= ~LC_DYN_LANES_PWR_STATE_MASK;
1666                         data |= LC_DYN_LANES_PWR_STATE(3);
1667                         if (orig != data)
1668                                 WREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL, data);
1669
1670                         orig = data = si_pif_phy0_rreg(adev,PB0_PIF_CNTL);
1671                         data &= ~LS2_EXIT_TIME_MASK;
1672                         if ((adev->family == CHIP_OLAND) || (adev->family == CHIP_HAINAN))
1673                                 data |= LS2_EXIT_TIME(5);
1674                         if (orig != data)
1675                                 si_pif_phy0_wreg(adev,PB0_PIF_CNTL, data);
1676
1677                         orig = data = si_pif_phy1_rreg(adev,PB1_PIF_CNTL);
1678                         data &= ~LS2_EXIT_TIME_MASK;
1679                         if ((adev->family == CHIP_OLAND) || (adev->family == CHIP_HAINAN))
1680                                 data |= LS2_EXIT_TIME(5);
1681                         if (orig != data)
1682                                 si_pif_phy1_wreg(adev,PB1_PIF_CNTL, data);
1683
1684                         if (!disable_clkreq &&
1685                             !pci_is_root_bus(adev->pdev->bus)) {
1686                                 struct pci_dev *root = adev->pdev->bus->self;
1687                                 u32 lnkcap;
1688
1689                                 clk_req_support = false;
1690                                 pcie_capability_read_dword(root, PCI_EXP_LNKCAP, &lnkcap);
1691                                 if (lnkcap & PCI_EXP_LNKCAP_CLKPM)
1692                                         clk_req_support = true;
1693                         } else {
1694                                 clk_req_support = false;
1695                         }
1696
1697                         if (clk_req_support) {
1698                                 orig = data = RREG32_PCIE_PORT(PCIE_LC_CNTL2);
1699                                 data |= LC_ALLOW_PDWN_IN_L1 | LC_ALLOW_PDWN_IN_L23;
1700                                 if (orig != data)
1701                                         WREG32_PCIE_PORT(PCIE_LC_CNTL2, data);
1702
1703                                 orig = data = RREG32(THM_CLK_CNTL);
1704                                 data &= ~(CMON_CLK_SEL_MASK | TMON_CLK_SEL_MASK);
1705                                 data |= CMON_CLK_SEL(1) | TMON_CLK_SEL(1);
1706                                 if (orig != data)
1707                                         WREG32(THM_CLK_CNTL, data);
1708
1709                                 orig = data = RREG32(MISC_CLK_CNTL);
1710                                 data &= ~(DEEP_SLEEP_CLK_SEL_MASK | ZCLK_SEL_MASK);
1711                                 data |= DEEP_SLEEP_CLK_SEL(1) | ZCLK_SEL(1);
1712                                 if (orig != data)
1713                                         WREG32(MISC_CLK_CNTL, data);
1714
1715                                 orig = data = RREG32(CG_CLKPIN_CNTL);
1716                                 data &= ~BCLK_AS_XCLK;
1717                                 if (orig != data)
1718                                         WREG32(CG_CLKPIN_CNTL, data);
1719
1720                                 orig = data = RREG32(CG_CLKPIN_CNTL_2);
1721                                 data &= ~FORCE_BIF_REFCLK_EN;
1722                                 if (orig != data)
1723                                         WREG32(CG_CLKPIN_CNTL_2, data);
1724
1725                                 orig = data = RREG32(MPLL_BYPASSCLK_SEL);
1726                                 data &= ~MPLL_CLKOUT_SEL_MASK;
1727                                 data |= MPLL_CLKOUT_SEL(4);
1728                                 if (orig != data)
1729                                         WREG32(MPLL_BYPASSCLK_SEL, data);
1730
1731                                 orig = data = RREG32(SPLL_CNTL_MODE);
1732                                 data &= ~SPLL_REFCLK_SEL_MASK;
1733                                 if (orig != data)
1734                                         WREG32(SPLL_CNTL_MODE, data);
1735                         }
1736                 }
1737         } else {
1738                 if (orig != data)
1739                         WREG32_PCIE_PORT(PCIE_LC_CNTL, data);
1740         }
1741
1742         orig = data = RREG32_PCIE(PCIE_CNTL2);
1743         data |= SLV_MEM_LS_EN | MST_MEM_LS_EN | REPLAY_MEM_LS_EN;
1744         if (orig != data)
1745                 WREG32_PCIE(PCIE_CNTL2, data);
1746
1747         if (!disable_l0s) {
1748                 data = RREG32_PCIE_PORT(PCIE_LC_N_FTS_CNTL);
1749                 if((data & LC_N_FTS_MASK) == LC_N_FTS_MASK) {
1750                         data = RREG32_PCIE(PCIE_LC_STATUS1);
1751                         if ((data & LC_REVERSE_XMIT) && (data & LC_REVERSE_RCVR)) {
1752                                 orig = data = RREG32_PCIE_PORT(PCIE_LC_CNTL);
1753                                 data &= ~LC_L0S_INACTIVITY_MASK;
1754                                 if (orig != data)
1755                                         WREG32_PCIE_PORT(PCIE_LC_CNTL, data);
1756                         }
1757                 }
1758         }
1759 }
1760
1761 static void si_fix_pci_max_read_req_size(struct amdgpu_device *adev)
1762 {
1763         int readrq;
1764         u16 v;
1765
1766         readrq = pcie_get_readrq(adev->pdev);
1767         v = ffs(readrq) - 8;
1768         if ((v == 0) || (v == 6) || (v == 7))
1769                 pcie_set_readrq(adev->pdev, 512);
1770 }
1771
1772 static int si_common_hw_init(void *handle)
1773 {
1774         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1775
1776         si_fix_pci_max_read_req_size(adev);
1777         si_init_golden_registers(adev);
1778         si_pcie_gen3_enable(adev);
1779         si_program_aspm(adev);
1780
1781         return 0;
1782 }
1783
1784 static int si_common_hw_fini(void *handle)
1785 {
1786         return 0;
1787 }
1788
1789 static int si_common_suspend(void *handle)
1790 {
1791         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1792
1793         return si_common_hw_fini(adev);
1794 }
1795
1796 static int si_common_resume(void *handle)
1797 {
1798         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1799
1800         return si_common_hw_init(adev);
1801 }
1802
1803 static bool si_common_is_idle(void *handle)
1804 {
1805         return true;
1806 }
1807
1808 static int si_common_wait_for_idle(void *handle)
1809 {
1810         return 0;
1811 }
1812
1813 static int si_common_soft_reset(void *handle)
1814 {
1815         return 0;
1816 }
1817
1818 static int si_common_set_clockgating_state(void *handle,
1819                                             enum amd_clockgating_state state)
1820 {
1821         return 0;
1822 }
1823
1824 static int si_common_set_powergating_state(void *handle,
1825                                             enum amd_powergating_state state)
1826 {
1827         return 0;
1828 }
1829
1830 static const struct amd_ip_funcs si_common_ip_funcs = {
1831         .name = "si_common",
1832         .early_init = si_common_early_init,
1833         .late_init = NULL,
1834         .sw_init = si_common_sw_init,
1835         .sw_fini = si_common_sw_fini,
1836         .hw_init = si_common_hw_init,
1837         .hw_fini = si_common_hw_fini,
1838         .suspend = si_common_suspend,
1839         .resume = si_common_resume,
1840         .is_idle = si_common_is_idle,
1841         .wait_for_idle = si_common_wait_for_idle,
1842         .soft_reset = si_common_soft_reset,
1843         .set_clockgating_state = si_common_set_clockgating_state,
1844         .set_powergating_state = si_common_set_powergating_state,
1845 };
1846
1847 static const struct amdgpu_ip_block_version si_common_ip_block =
1848 {
1849         .type = AMD_IP_BLOCK_TYPE_COMMON,
1850         .major = 1,
1851         .minor = 0,
1852         .rev = 0,
1853         .funcs = &si_common_ip_funcs,
1854 };
1855
1856 int si_set_ip_blocks(struct amdgpu_device *adev)
1857 {
1858         switch (adev->asic_type) {
1859         case CHIP_VERDE:
1860         case CHIP_TAHITI:
1861         case CHIP_PITCAIRN:
1862                 amdgpu_ip_block_add(adev, &si_common_ip_block);
1863                 amdgpu_ip_block_add(adev, &gmc_v6_0_ip_block);
1864                 amdgpu_ip_block_add(adev, &si_ih_ip_block);
1865                 amdgpu_ip_block_add(adev, &amdgpu_pp_ip_block);
1866                 if (adev->enable_virtual_display)
1867                         amdgpu_ip_block_add(adev, &dce_virtual_ip_block);
1868                 else
1869                         amdgpu_ip_block_add(adev, &dce_v6_0_ip_block);
1870                 amdgpu_ip_block_add(adev, &gfx_v6_0_ip_block);
1871                 amdgpu_ip_block_add(adev, &si_dma_ip_block);
1872                 /* amdgpu_ip_block_add(adev, &uvd_v3_1_ip_block); */
1873                 /* amdgpu_ip_block_add(adev, &vce_v1_0_ip_block); */
1874                 break;
1875         case CHIP_OLAND:
1876                 amdgpu_ip_block_add(adev, &si_common_ip_block);
1877                 amdgpu_ip_block_add(adev, &gmc_v6_0_ip_block);
1878                 amdgpu_ip_block_add(adev, &si_ih_ip_block);
1879                 amdgpu_ip_block_add(adev, &amdgpu_pp_ip_block);
1880                 if (adev->enable_virtual_display)
1881                         amdgpu_ip_block_add(adev, &dce_virtual_ip_block);
1882                 else
1883                         amdgpu_ip_block_add(adev, &dce_v6_4_ip_block);
1884                 amdgpu_ip_block_add(adev, &gfx_v6_0_ip_block);
1885                 amdgpu_ip_block_add(adev, &si_dma_ip_block);
1886                 /* amdgpu_ip_block_add(adev, &uvd_v3_1_ip_block); */
1887                 /* amdgpu_ip_block_add(adev, &vce_v1_0_ip_block); */
1888                 break;
1889         case CHIP_HAINAN:
1890                 amdgpu_ip_block_add(adev, &si_common_ip_block);
1891                 amdgpu_ip_block_add(adev, &gmc_v6_0_ip_block);
1892                 amdgpu_ip_block_add(adev, &si_ih_ip_block);
1893                 amdgpu_ip_block_add(adev, &amdgpu_pp_ip_block);
1894                 if (adev->enable_virtual_display)
1895                         amdgpu_ip_block_add(adev, &dce_virtual_ip_block);
1896                 amdgpu_ip_block_add(adev, &gfx_v6_0_ip_block);
1897                 amdgpu_ip_block_add(adev, &si_dma_ip_block);
1898                 break;
1899         default:
1900                 BUG();
1901         }
1902         return 0;
1903 }
1904