drivers/gpu/drm/amd/amdgpu/si_dpm.c

   1 /*
   2  * Copyright 2013 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23
  24 #include "drmP.h"
  25 #include "amdgpu.h"
  26 #include "amdgpu_pm.h"
  27 #include "amdgpu_dpm.h"
  28 #include "amdgpu_atombios.h"
  29 #include "si/sid.h"
  30 #include "r600_dpm.h"
  31 #include "si_dpm.h"
  32 #include "atom.h"
  33 #include "../include/pptable.h"
  34 #include <linux/math64.h>
  35 #include <linux/seq_file.h>
  36 #include <linux/firmware.h>
  37
  38 #define MC_CG_ARB_FREQ_F0           0x0a
  39 #define MC_CG_ARB_FREQ_F1           0x0b
  40 #define MC_CG_ARB_FREQ_F2           0x0c
  41 #define MC_CG_ARB_FREQ_F3           0x0d
  42
  43 #define SMC_RAM_END                 0x20000
  44
  45 #define SCLK_MIN_DEEPSLEEP_FREQ     1350
  46
  47
  48 /* sizeof(ATOM_PPLIB_EXTENDEDHEADER) */
  49 #define SIZE_OF_ATOM_PPLIB_EXTENDEDHEADER_V2 12
  50 #define SIZE_OF_ATOM_PPLIB_EXTENDEDHEADER_V3 14
  51 #define SIZE_OF_ATOM_PPLIB_EXTENDEDHEADER_V4 16
  52 #define SIZE_OF_ATOM_PPLIB_EXTENDEDHEADER_V5 18
  53 #define SIZE_OF_ATOM_PPLIB_EXTENDEDHEADER_V6 20
  54 #define SIZE_OF_ATOM_PPLIB_EXTENDEDHEADER_V7 22
  55
  56 #define BIOS_SCRATCH_4                                    0x5cd
  57
  58 MODULE_FIRMWARE("radeon/tahiti_smc.bin");
  59 MODULE_FIRMWARE("radeon/pitcairn_smc.bin");
  60 MODULE_FIRMWARE("radeon/pitcairn_k_smc.bin");
  61 MODULE_FIRMWARE("radeon/verde_smc.bin");
  62 MODULE_FIRMWARE("radeon/verde_k_smc.bin");
  63 MODULE_FIRMWARE("radeon/oland_smc.bin");
  64 MODULE_FIRMWARE("radeon/oland_k_smc.bin");
  65 MODULE_FIRMWARE("radeon/hainan_smc.bin");
  66 MODULE_FIRMWARE("radeon/hainan_k_smc.bin");
  67
  68 union power_info {
  69         struct _ATOM_POWERPLAY_INFO info;
  70         struct _ATOM_POWERPLAY_INFO_V2 info_2;
  71         struct _ATOM_POWERPLAY_INFO_V3 info_3;
  72         struct _ATOM_PPLIB_POWERPLAYTABLE pplib;
  73         struct _ATOM_PPLIB_POWERPLAYTABLE2 pplib2;
  74         struct _ATOM_PPLIB_POWERPLAYTABLE3 pplib3;
  75         struct _ATOM_PPLIB_POWERPLAYTABLE4 pplib4;
  76         struct _ATOM_PPLIB_POWERPLAYTABLE5 pplib5;
  77 };
  78
  79 union fan_info {
  80         struct _ATOM_PPLIB_FANTABLE fan;
  81         struct _ATOM_PPLIB_FANTABLE2 fan2;
  82         struct _ATOM_PPLIB_FANTABLE3 fan3;
  83 };
  84
  85 union pplib_clock_info {
  86         struct _ATOM_PPLIB_R600_CLOCK_INFO r600;
  87         struct _ATOM_PPLIB_RS780_CLOCK_INFO rs780;
  88         struct _ATOM_PPLIB_EVERGREEN_CLOCK_INFO evergreen;
  89         struct _ATOM_PPLIB_SUMO_CLOCK_INFO sumo;
  90         struct _ATOM_PPLIB_SI_CLOCK_INFO si;
  91 };
  92
  93 static const u32 r600_utc[R600_PM_NUMBER_OF_TC] =
  94 {
  95         R600_UTC_DFLT_00,
  96         R600_UTC_DFLT_01,
  97         R600_UTC_DFLT_02,
  98         R600_UTC_DFLT_03,
  99         R600_UTC_DFLT_04,
 100         R600_UTC_DFLT_05,
 101         R600_UTC_DFLT_06,
 102         R600_UTC_DFLT_07,
 103         R600_UTC_DFLT_08,
 104         R600_UTC_DFLT_09,
 105         R600_UTC_DFLT_10,
 106         R600_UTC_DFLT_11,
 107         R600_UTC_DFLT_12,
 108         R600_UTC_DFLT_13,
 109         R600_UTC_DFLT_14,
 110 };
 111
 112 static const u32 r600_dtc[R600_PM_NUMBER_OF_TC] =
 113 {
 114         R600_DTC_DFLT_00,
 115         R600_DTC_DFLT_01,
 116         R600_DTC_DFLT_02,
 117         R600_DTC_DFLT_03,
 118         R600_DTC_DFLT_04,
 119         R600_DTC_DFLT_05,
 120         R600_DTC_DFLT_06,
 121         R600_DTC_DFLT_07,
 122         R600_DTC_DFLT_08,
 123         R600_DTC_DFLT_09,
 124         R600_DTC_DFLT_10,
 125         R600_DTC_DFLT_11,
 126         R600_DTC_DFLT_12,
 127         R600_DTC_DFLT_13,
 128         R600_DTC_DFLT_14,
 129 };
 130
 131 static const struct si_cac_config_reg cac_weights_tahiti[] =
 132 {
 133         { 0x0, 0x0000ffff, 0, 0xc, SISLANDS_CACCONFIG_CGIND },
 134         { 0x0, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 135         { 0x1, 0x0000ffff, 0, 0x101, SISLANDS_CACCONFIG_CGIND },
 136         { 0x1, 0xffff0000, 16, 0xc, SISLANDS_CACCONFIG_CGIND },
 137         { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 138         { 0x3, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 139         { 0x3, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 140         { 0x4, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 141         { 0x4, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 142         { 0x5, 0x0000ffff, 0, 0x8fc, SISLANDS_CACCONFIG_CGIND },
 143         { 0x5, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 144         { 0x6, 0x0000ffff, 0, 0x95, SISLANDS_CACCONFIG_CGIND },
 145         { 0x6, 0xffff0000, 16, 0x34e, SISLANDS_CACCONFIG_CGIND },
 146         { 0x18f, 0x0000ffff, 0, 0x1a1, SISLANDS_CACCONFIG_CGIND },
 147         { 0x7, 0x0000ffff, 0, 0xda, SISLANDS_CACCONFIG_CGIND },
 148         { 0x7, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 149         { 0x8, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 150         { 0x8, 0xffff0000, 16, 0x46, SISLANDS_CACCONFIG_CGIND },
 151         { 0x9, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 152         { 0xa, 0x0000ffff, 0, 0x208, SISLANDS_CACCONFIG_CGIND },
 153         { 0xb, 0x0000ffff, 0, 0xe7, SISLANDS_CACCONFIG_CGIND },
 154         { 0xb, 0xffff0000, 16, 0x948, SISLANDS_CACCONFIG_CGIND },
 155         { 0xc, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 156         { 0xd, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 157         { 0xd, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 158         { 0xe, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 159         { 0xf, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 160         { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 161         { 0x10, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 162         { 0x10, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 163         { 0x11, 0x0000ffff, 0, 0x167, SISLANDS_CACCONFIG_CGIND },
 164         { 0x11, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 165         { 0x12, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 166         { 0x13, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 167         { 0x13, 0xffff0000, 16, 0x35, SISLANDS_CACCONFIG_CGIND },
 168         { 0x14, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 169         { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 170         { 0x15, 0xffff0000, 16, 0x2, SISLANDS_CACCONFIG_CGIND },
 171         { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 172         { 0x16, 0x0000ffff, 0, 0x31, SISLANDS_CACCONFIG_CGIND },
 173         { 0x16, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 174         { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 175         { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 176         { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 177         { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 178         { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 179         { 0x1a, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 180         { 0x1a, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 181         { 0x1b, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 182         { 0x1b, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 183         { 0x1c, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 184         { 0x1c, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 185         { 0x1d, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 186         { 0x1d, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 187         { 0x1e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 188         { 0x1e, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 189         { 0x1f, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 190         { 0x1f, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 191         { 0x20, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 192         { 0x6d, 0x0000ffff, 0, 0x18e, SISLANDS_CACCONFIG_CGIND },
 193         { 0xFFFFFFFF }
 194 };
 195
 196 static const struct si_cac_config_reg lcac_tahiti[] =
 197 {
 198         { 0x143, 0x0001fffe, 1, 0x3, SISLANDS_CACCONFIG_CGIND },
 199         { 0x143, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 200         { 0x146, 0x0001fffe, 1, 0x3, SISLANDS_CACCONFIG_CGIND },
 201         { 0x146, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 202         { 0x149, 0x0001fffe, 1, 0x3, SISLANDS_CACCONFIG_CGIND },
 203         { 0x149, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 204         { 0x14c, 0x0001fffe, 1, 0x3, SISLANDS_CACCONFIG_CGIND },
 205         { 0x14c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 206         { 0x98, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 207         { 0x98, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 208         { 0x9b, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 209         { 0x9b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 210         { 0x9e, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 211         { 0x9e, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 212         { 0x101, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 213         { 0x101, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 214         { 0x104, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 215         { 0x104, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 216         { 0x107, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 217         { 0x107, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 218         { 0x10a, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 219         { 0x10a, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 220         { 0x10d, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 221         { 0x10d, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 222         { 0x8c, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND },
 223         { 0x8c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 224         { 0x8f, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND },
 225         { 0x8f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 226         { 0x92, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND },
 227         { 0x92, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 228         { 0x95, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND },
 229         { 0x95, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 230         { 0x14f, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND },
 231         { 0x14f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 232         { 0x152, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND },
 233         { 0x152, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 234         { 0x155, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND },
 235         { 0x155, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 236         { 0x158, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND },
 237         { 0x158, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 238         { 0x110, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND },
 239         { 0x110, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 240         { 0x113, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND },
 241         { 0x113, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 242         { 0x116, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND },
 243         { 0x116, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 244         { 0x119, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND },
 245         { 0x119, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 246         { 0x11c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 247         { 0x11c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 248         { 0x11f, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 249         { 0x11f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 250         { 0x122, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 251         { 0x122, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 252         { 0x125, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 253         { 0x125, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 254         { 0x128, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 255         { 0x128, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 256         { 0x12b, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 257         { 0x12b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 258         { 0x15b, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
 259         { 0x15b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 260         { 0x15e, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
 261         { 0x15e, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 262         { 0x161, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
 263         { 0x161, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 264         { 0x164, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
 265         { 0x164, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 266         { 0x167, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
 267         { 0x167, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 268         { 0x16a, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
 269         { 0x16a, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 270         { 0x16d, 0x0001fffe, 1, 0x6, SISLANDS_CACCONFIG_CGIND },
 271         { 0x16d, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 272         { 0x170, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 273         { 0x170, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 274         { 0x173, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 275         { 0x173, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 276         { 0x176, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 277         { 0x176, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 278         { 0x179, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 279         { 0x179, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 280         { 0x17c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 281         { 0x17c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 282         { 0x17f, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 283         { 0x17f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 284         { 0xFFFFFFFF }
 285
 286 };
 287
 288 static const struct si_cac_config_reg cac_override_tahiti[] =
 289 {
 290         { 0xFFFFFFFF }
 291 };
 292
 293 static const struct si_powertune_data powertune_data_tahiti =
 294 {
 295         ((1 << 16) | 27027),
 296         6,
 297         0,
 298         4,
 299         95,
 300         {
 301                 0UL,
 302                 0UL,
 303                 4521550UL,
 304                 309631529UL,
 305                 -1270850L,
 306                 4513710L,
 307                 40
 308         },
 309         595000000UL,
 310         12,
 311         {
 312                 0,
 313                 0,
 314                 0,
 315                 0,
 316                 0,
 317                 0,
 318                 0,
 319                 0
 320         },
 321         true
 322 };
 323
 324 static const struct si_dte_data dte_data_tahiti =
 325 {
 326         { 1159409, 0, 0, 0, 0 },
 327         { 777, 0, 0, 0, 0 },
 328         2,
 329         54000,
 330         127000,
 331         25,
 332         2,
 333         10,
 334         13,
 335         { 27, 31, 35, 39, 43, 47, 54, 61, 67, 74, 81, 88, 95, 0, 0, 0 },
 336         { 240888759, 221057860, 235370597, 162287531, 158510299, 131423027, 116673180, 103067515, 87941937, 76209048, 68209175, 64090048, 58301890, 0, 0, 0 },
 337         { 12024, 11189, 11451, 8411, 7939, 6666, 5681, 4905, 4241, 3720, 3354, 3122, 2890, 0, 0, 0 },
 338         85,
 339         false
 340 };
 341
 342 #if 0
 343 static const struct si_dte_data dte_data_tahiti_le =
 344 {
 345         { 0x1E8480, 0x7A1200, 0x2160EC0, 0x3938700, 0 },
 346         { 0x7D, 0x7D, 0x4E4, 0xB00, 0 },
 347         0x5,
 348         0xAFC8,
 349         0x64,
 350         0x32,
 351         1,
 352         0,
 353         0x10,
 354         { 0x78, 0x7C, 0x82, 0x88, 0x8E, 0x94, 0x9A, 0xA0, 0xA6, 0xAC, 0xB0, 0xB4, 0xB8, 0xBC, 0xC0, 0xC4 },
 355         { 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700 },
 356         { 0x2AF8, 0x2AF8, 0x29BB, 0x27F9, 0x2637, 0x2475, 0x22B3, 0x20F1, 0x1F2F, 0x1D6D, 0x1734, 0x1414, 0x10F4, 0xDD4, 0xAB4, 0x794 },
 357         85,
 358         true
 359 };
 360 #endif
 361
 362 static const struct si_dte_data dte_data_tahiti_pro =
 363 {
 364         { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 },
 365         { 0x0, 0x0, 0x0, 0x0, 0x0 },
 366         5,
 367         45000,
 368         100,
 369         0xA,
 370         1,
 371         0,
 372         0x10,
 373         { 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF },
 374         { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 },
 375         { 0x7D0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
 376         90,
 377         true
 378 };
 379
 380 static const struct si_dte_data dte_data_new_zealand =
 381 {
 382         { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0 },
 383         { 0x29B, 0x3E9, 0x537, 0x7D2, 0 },
 384         0x5,
 385         0xAFC8,
 386         0x69,
 387         0x32,
 388         1,
 389         0,
 390         0x10,
 391         { 0x82, 0xA0, 0xB4, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE },
 392         { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 },
 393         { 0xDAC, 0x1388, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685 },
 394         85,
 395         true
 396 };
 397
 398 static const struct si_dte_data dte_data_aruba_pro =
 399 {
 400         { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 },
 401         { 0x0, 0x0, 0x0, 0x0, 0x0 },
 402         5,
 403         45000,
 404         100,
 405         0xA,
 406         1,
 407         0,
 408         0x10,
 409         { 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF },
 410         { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 },
 411         { 0x1000, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
 412         90,
 413         true
 414 };
 415
 416 static const struct si_dte_data dte_data_malta =
 417 {
 418         { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 },
 419         { 0x0, 0x0, 0x0, 0x0, 0x0 },
 420         5,
 421         45000,
 422         100,
 423         0xA,
 424         1,
 425         0,
 426         0x10,
 427         { 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF },
 428         { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 },
 429         { 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
 430         90,
 431         true
 432 };
 433
 434 static const struct si_cac_config_reg cac_weights_pitcairn[] =
 435 {
 436         { 0x0, 0x0000ffff, 0, 0x8a, SISLANDS_CACCONFIG_CGIND },
 437         { 0x0, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 438         { 0x1, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 439         { 0x1, 0xffff0000, 16, 0x24d, SISLANDS_CACCONFIG_CGIND },
 440         { 0x2, 0x0000ffff, 0, 0x19, SISLANDS_CACCONFIG_CGIND },
 441         { 0x3, 0x0000ffff, 0, 0x118, SISLANDS_CACCONFIG_CGIND },
 442         { 0x3, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 443         { 0x4, 0x0000ffff, 0, 0x76, SISLANDS_CACCONFIG_CGIND },
 444         { 0x4, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 445         { 0x5, 0x0000ffff, 0, 0xc11, SISLANDS_CACCONFIG_CGIND },
 446         { 0x5, 0xffff0000, 16, 0x7f3, SISLANDS_CACCONFIG_CGIND },
 447         { 0x6, 0x0000ffff, 0, 0x403, SISLANDS_CACCONFIG_CGIND },
 448         { 0x6, 0xffff0000, 16, 0x367, SISLANDS_CACCONFIG_CGIND },
 449         { 0x18f, 0x0000ffff, 0, 0x4c9, SISLANDS_CACCONFIG_CGIND },
 450         { 0x7, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 451         { 0x7, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 452         { 0x8, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 453         { 0x8, 0xffff0000, 16, 0x45d, SISLANDS_CACCONFIG_CGIND },
 454         { 0x9, 0x0000ffff, 0, 0x36d, SISLANDS_CACCONFIG_CGIND },
 455         { 0xa, 0x0000ffff, 0, 0x534, SISLANDS_CACCONFIG_CGIND },
 456         { 0xb, 0x0000ffff, 0, 0x5da, SISLANDS_CACCONFIG_CGIND },
 457         { 0xb, 0xffff0000, 16, 0x880, SISLANDS_CACCONFIG_CGIND },
 458         { 0xc, 0x0000ffff, 0, 0x201, SISLANDS_CACCONFIG_CGIND },
 459         { 0xd, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 460         { 0xd, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 461         { 0xe, 0x0000ffff, 0, 0x9f, SISLANDS_CACCONFIG_CGIND },
 462         { 0xf, 0x0000ffff, 0, 0x1f, SISLANDS_CACCONFIG_CGIND },
 463         { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 464         { 0x10, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 465         { 0x10, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 466         { 0x11, 0x0000ffff, 0, 0x5de, SISLANDS_CACCONFIG_CGIND },
 467         { 0x11, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 468         { 0x12, 0x0000ffff, 0, 0x7b, SISLANDS_CACCONFIG_CGIND },
 469         { 0x13, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 470         { 0x13, 0xffff0000, 16, 0x13, SISLANDS_CACCONFIG_CGIND },
 471         { 0x14, 0x0000ffff, 0, 0xf9, SISLANDS_CACCONFIG_CGIND },
 472         { 0x15, 0x0000ffff, 0, 0x66, SISLANDS_CACCONFIG_CGIND },
 473         { 0x15, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 474         { 0x4e, 0x0000ffff, 0, 0x13, SISLANDS_CACCONFIG_CGIND },
 475         { 0x16, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 476         { 0x16, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 477         { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 478         { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 479         { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 480         { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 481         { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 482         { 0x1a, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 483         { 0x1a, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 484         { 0x1b, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 485         { 0x1b, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 486         { 0x1c, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 487         { 0x1c, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 488         { 0x1d, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 489         { 0x1d, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 490         { 0x1e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 491         { 0x1e, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 492         { 0x1f, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 493         { 0x1f, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 494         { 0x20, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 495         { 0x6d, 0x0000ffff, 0, 0x186, SISLANDS_CACCONFIG_CGIND },
 496         { 0xFFFFFFFF }
 497 };
 498
 499 static const struct si_cac_config_reg lcac_pitcairn[] =
 500 {
 501         { 0x98, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 502         { 0x98, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 503         { 0x104, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 504         { 0x104, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 505         { 0x110, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
 506         { 0x110, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 507         { 0x14f, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
 508         { 0x14f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 509         { 0x8c, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
 510         { 0x8c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 511         { 0x143, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 512         { 0x143, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 513         { 0x9b, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 514         { 0x9b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 515         { 0x107, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 516         { 0x107, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 517         { 0x113, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
 518         { 0x113, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 519         { 0x152, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
 520         { 0x152, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 521         { 0x8f, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
 522         { 0x8f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 523         { 0x146, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 524         { 0x146, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 525         { 0x9e, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 526         { 0x9e, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 527         { 0x10a, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 528         { 0x10a, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 529         { 0x116, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
 530         { 0x116, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 531         { 0x155, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
 532         { 0x155, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 533         { 0x92, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
 534         { 0x92, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 535         { 0x149, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 536         { 0x149, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 537         { 0x101, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 538         { 0x101, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 539         { 0x10d, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 540         { 0x10d, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 541         { 0x119, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
 542         { 0x119, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 543         { 0x158, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
 544         { 0x158, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 545         { 0x95, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
 546         { 0x95, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 547         { 0x14c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 548         { 0x14c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 549         { 0x11c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 550         { 0x11c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 551         { 0x11f, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 552         { 0x11f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 553         { 0x122, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 554         { 0x122, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 555         { 0x125, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 556         { 0x125, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 557         { 0x128, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 558         { 0x128, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 559         { 0x12b, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 560         { 0x12b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 561         { 0x164, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
 562         { 0x164, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 563         { 0x167, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
 564         { 0x167, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 565         { 0x16a, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
 566         { 0x16a, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 567         { 0x15e, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
 568         { 0x15e, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 569         { 0x161, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
 570         { 0x161, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 571         { 0x15b, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
 572         { 0x15b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 573         { 0x16d, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
 574         { 0x16d, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 575         { 0x170, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 576         { 0x170, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 577         { 0x173, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 578         { 0x173, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 579         { 0x176, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 580         { 0x176, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 581         { 0x179, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 582         { 0x179, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 583         { 0x17c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 584         { 0x17c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 585         { 0x17f, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 586         { 0x17f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 587         { 0xFFFFFFFF }
 588 };
 589
 590 static const struct si_cac_config_reg cac_override_pitcairn[] =
 591 {
 592     { 0xFFFFFFFF }
 593 };
 594
 595 static const struct si_powertune_data powertune_data_pitcairn =
 596 {
 597         ((1 << 16) | 27027),
 598         5,
 599         0,
 600         6,
 601         100,
 602         {
 603                 51600000UL,
 604                 1800000UL,
 605                 7194395UL,
 606                 309631529UL,
 607                 -1270850L,
 608                 4513710L,
 609                 100
 610         },
 611         117830498UL,
 612         12,
 613         {
 614                 0,
 615                 0,
 616                 0,
 617                 0,
 618                 0,
 619                 0,
 620                 0,
 621                 0
 622         },
 623         true
 624 };
 625
 626 static const struct si_dte_data dte_data_pitcairn =
 627 {
 628         { 0, 0, 0, 0, 0 },
 629         { 0, 0, 0, 0, 0 },
 630         0,
 631         0,
 632         0,
 633         0,
 634         0,
 635         0,
 636         0,
 637         { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
 638         { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
 639         { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
 640         0,
 641         false
 642 };
 643
 644 static const struct si_dte_data dte_data_curacao_xt =
 645 {
 646         { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 },
 647         { 0x0, 0x0, 0x0, 0x0, 0x0 },
 648         5,
 649         45000,
 650         100,
 651         0xA,
 652         1,
 653         0,
 654         0x10,
 655         { 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF },
 656         { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 },
 657         { 0x1D17, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
 658         90,
 659         true
 660 };
 661
 662 static const struct si_dte_data dte_data_curacao_pro =
 663 {
 664         { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 },
 665         { 0x0, 0x0, 0x0, 0x0, 0x0 },
 666         5,
 667         45000,
 668         100,
 669         0xA,
 670         1,
 671         0,
 672         0x10,
 673         { 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF },
 674         { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 },
 675         { 0x1D17, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
 676         90,
 677         true
 678 };
 679
 680 static const struct si_dte_data dte_data_neptune_xt =
 681 {
 682         { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 },
 683         { 0x0, 0x0, 0x0, 0x0, 0x0 },
 684         5,
 685         45000,
 686         100,
 687         0xA,
 688         1,
 689         0,
 690         0x10,
 691         { 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF },
 692         { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 },
 693         { 0x3A2F, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
 694         90,
 695         true
 696 };
 697
 698 static const struct si_cac_config_reg cac_weights_chelsea_pro[] =
 699 {
 700         { 0x0, 0x0000ffff, 0, 0x82, SISLANDS_CACCONFIG_CGIND },
 701         { 0x0, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND },
 702         { 0x1, 0x0000ffff, 0, 0x153, SISLANDS_CACCONFIG_CGIND },
 703         { 0x1, 0xffff0000, 16, 0x52, SISLANDS_CACCONFIG_CGIND },
 704         { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 705         { 0x3, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND },
 706         { 0x3, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND },
 707         { 0x4, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND },
 708         { 0x4, 0xffff0000, 16, 0xAC, SISLANDS_CACCONFIG_CGIND },
 709         { 0x5, 0x0000ffff, 0, 0x118, SISLANDS_CACCONFIG_CGIND },
 710         { 0x5, 0xffff0000, 16, 0xBE, SISLANDS_CACCONFIG_CGIND },
 711         { 0x6, 0x0000ffff, 0, 0x110, SISLANDS_CACCONFIG_CGIND },
 712         { 0x6, 0xffff0000, 16, 0x4CD, SISLANDS_CACCONFIG_CGIND },
 713         { 0x18f, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND },
 714         { 0x7, 0x0000ffff, 0, 0x37, SISLANDS_CACCONFIG_CGIND },
 715         { 0x7, 0xffff0000, 16, 0x27, SISLANDS_CACCONFIG_CGIND },
 716         { 0x8, 0x0000ffff, 0, 0xC3, SISLANDS_CACCONFIG_CGIND },
 717         { 0x8, 0xffff0000, 16, 0x35, SISLANDS_CACCONFIG_CGIND },
 718         { 0x9, 0x0000ffff, 0, 0x28, SISLANDS_CACCONFIG_CGIND },
 719         { 0xa, 0x0000ffff, 0, 0x26C, SISLANDS_CACCONFIG_CGIND },
 720         { 0xb, 0x0000ffff, 0, 0x3B2, SISLANDS_CACCONFIG_CGIND },
 721         { 0xb, 0xffff0000, 16, 0x99D, SISLANDS_CACCONFIG_CGIND },
 722         { 0xc, 0x0000ffff, 0, 0xA3F, SISLANDS_CACCONFIG_CGIND },
 723         { 0xd, 0x0000ffff, 0, 0xA, SISLANDS_CACCONFIG_CGIND },
 724         { 0xd, 0xffff0000, 16, 0xA, SISLANDS_CACCONFIG_CGIND },
 725         { 0xe, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
 726         { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND },
 727         { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 728         { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 729         { 0x10, 0xffff0000, 16, 0x1, SISLANDS_CACCONFIG_CGIND },
 730         { 0x11, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
 731         { 0x11, 0xffff0000, 16, 0x15, SISLANDS_CACCONFIG_CGIND },
 732         { 0x12, 0x0000ffff, 0, 0x34, SISLANDS_CACCONFIG_CGIND },
 733         { 0x13, 0x0000ffff, 0, 0x4, SISLANDS_CACCONFIG_CGIND },
 734         { 0x13, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND },
 735         { 0x14, 0x0000ffff, 0, 0x2BD, SISLANDS_CACCONFIG_CGIND },
 736         { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 737         { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND },
 738         { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 739         { 0x16, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND },
 740         { 0x16, 0xffff0000, 16, 0x7A, SISLANDS_CACCONFIG_CGIND },
 741         { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 742         { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 743         { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 744         { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 745         { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 746         { 0x1a, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
 747         { 0x1a, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
 748         { 0x1b, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
 749         { 0x1b, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
 750         { 0x1c, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
 751         { 0x1c, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
 752         { 0x1d, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
 753         { 0x1d, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
 754         { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
 755         { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
 756         { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
 757         { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
 758         { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
 759         { 0x6d, 0x0000ffff, 0, 0x100, SISLANDS_CACCONFIG_CGIND },
 760         { 0xFFFFFFFF }
 761 };
 762
 763 static const struct si_cac_config_reg cac_weights_chelsea_xt[] =
 764 {
 765         { 0x0, 0x0000ffff, 0, 0x82, SISLANDS_CACCONFIG_CGIND },
 766         { 0x0, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND },
 767         { 0x1, 0x0000ffff, 0, 0x153, SISLANDS_CACCONFIG_CGIND },
 768         { 0x1, 0xffff0000, 16, 0x52, SISLANDS_CACCONFIG_CGIND },
 769         { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 770         { 0x3, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND },
 771         { 0x3, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND },
 772         { 0x4, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND },
 773         { 0x4, 0xffff0000, 16, 0xAC, SISLANDS_CACCONFIG_CGIND },
 774         { 0x5, 0x0000ffff, 0, 0x118, SISLANDS_CACCONFIG_CGIND },
 775         { 0x5, 0xffff0000, 16, 0xBE, SISLANDS_CACCONFIG_CGIND },
 776         { 0x6, 0x0000ffff, 0, 0x110, SISLANDS_CACCONFIG_CGIND },
 777         { 0x6, 0xffff0000, 16, 0x4CD, SISLANDS_CACCONFIG_CGIND },
 778         { 0x18f, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND },
 779         { 0x7, 0x0000ffff, 0, 0x37, SISLANDS_CACCONFIG_CGIND },
 780         { 0x7, 0xffff0000, 16, 0x27, SISLANDS_CACCONFIG_CGIND },
 781         { 0x8, 0x0000ffff, 0, 0xC3, SISLANDS_CACCONFIG_CGIND },
 782         { 0x8, 0xffff0000, 16, 0x35, SISLANDS_CACCONFIG_CGIND },
 783         { 0x9, 0x0000ffff, 0, 0x28, SISLANDS_CACCONFIG_CGIND },
 784         { 0xa, 0x0000ffff, 0, 0x26C, SISLANDS_CACCONFIG_CGIND },
 785         { 0xb, 0x0000ffff, 0, 0x3B2, SISLANDS_CACCONFIG_CGIND },
 786         { 0xb, 0xffff0000, 16, 0x99D, SISLANDS_CACCONFIG_CGIND },
 787         { 0xc, 0x0000ffff, 0, 0xA3F, SISLANDS_CACCONFIG_CGIND },
 788         { 0xd, 0x0000ffff, 0, 0xA, SISLANDS_CACCONFIG_CGIND },
 789         { 0xd, 0xffff0000, 16, 0xA, SISLANDS_CACCONFIG_CGIND },
 790         { 0xe, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
 791         { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND },
 792         { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 793         { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 794         { 0x10, 0xffff0000, 16, 0x1, SISLANDS_CACCONFIG_CGIND },
 795         { 0x11, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
 796         { 0x11, 0xffff0000, 16, 0x15, SISLANDS_CACCONFIG_CGIND },
 797         { 0x12, 0x0000ffff, 0, 0x34, SISLANDS_CACCONFIG_CGIND },
 798         { 0x13, 0x0000ffff, 0, 0x4, SISLANDS_CACCONFIG_CGIND },
 799         { 0x13, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND },
 800         { 0x14, 0x0000ffff, 0, 0x30A, SISLANDS_CACCONFIG_CGIND },
 801         { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 802         { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND },
 803         { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 804         { 0x16, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND },
 805         { 0x16, 0xffff0000, 16, 0x7A, SISLANDS_CACCONFIG_CGIND },
 806         { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 807         { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 808         { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 809         { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 810         { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 811         { 0x1a, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
 812         { 0x1a, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
 813         { 0x1b, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
 814         { 0x1b, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
 815         { 0x1c, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
 816         { 0x1c, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
 817         { 0x1d, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
 818         { 0x1d, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
 819         { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
 820         { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
 821         { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
 822         { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
 823         { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
 824         { 0x6d, 0x0000ffff, 0, 0x100, SISLANDS_CACCONFIG_CGIND },
 825         { 0xFFFFFFFF }
 826 };
 827
 828 static const struct si_cac_config_reg cac_weights_heathrow[] =
 829 {
 830         { 0x0, 0x0000ffff, 0, 0x82, SISLANDS_CACCONFIG_CGIND },
 831         { 0x0, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND },
 832         { 0x1, 0x0000ffff, 0, 0x153, SISLANDS_CACCONFIG_CGIND },
 833         { 0x1, 0xffff0000, 16, 0x52, SISLANDS_CACCONFIG_CGIND },
 834         { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 835         { 0x3, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND },
 836         { 0x3, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND },
 837         { 0x4, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND },
 838         { 0x4, 0xffff0000, 16, 0xAC, SISLANDS_CACCONFIG_CGIND },
 839         { 0x5, 0x0000ffff, 0, 0x118, SISLANDS_CACCONFIG_CGIND },
 840         { 0x5, 0xffff0000, 16, 0xBE, SISLANDS_CACCONFIG_CGIND },
 841         { 0x6, 0x0000ffff, 0, 0x110, SISLANDS_CACCONFIG_CGIND },
 842         { 0x6, 0xffff0000, 16, 0x4CD, SISLANDS_CACCONFIG_CGIND },
 843         { 0x18f, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND },
 844         { 0x7, 0x0000ffff, 0, 0x37, SISLANDS_CACCONFIG_CGIND },
 845         { 0x7, 0xffff0000, 16, 0x27, SISLANDS_CACCONFIG_CGIND },
 846         { 0x8, 0x0000ffff, 0, 0xC3, SISLANDS_CACCONFIG_CGIND },
 847         { 0x8, 0xffff0000, 16, 0x35, SISLANDS_CACCONFIG_CGIND },
 848         { 0x9, 0x0000ffff, 0, 0x28, SISLANDS_CACCONFIG_CGIND },
 849         { 0xa, 0x0000ffff, 0, 0x26C, SISLANDS_CACCONFIG_CGIND },
 850         { 0xb, 0x0000ffff, 0, 0x3B2, SISLANDS_CACCONFIG_CGIND },
 851         { 0xb, 0xffff0000, 16, 0x99D, SISLANDS_CACCONFIG_CGIND },
 852         { 0xc, 0x0000ffff, 0, 0xA3F, SISLANDS_CACCONFIG_CGIND },
 853         { 0xd, 0x0000ffff, 0, 0xA, SISLANDS_CACCONFIG_CGIND },
 854         { 0xd, 0xffff0000, 16, 0xA, SISLANDS_CACCONFIG_CGIND },
 855         { 0xe, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
 856         { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND },
 857         { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 858         { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 859         { 0x10, 0xffff0000, 16, 0x1, SISLANDS_CACCONFIG_CGIND },
 860         { 0x11, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
 861         { 0x11, 0xffff0000, 16, 0x15, SISLANDS_CACCONFIG_CGIND },
 862         { 0x12, 0x0000ffff, 0, 0x34, SISLANDS_CACCONFIG_CGIND },
 863         { 0x13, 0x0000ffff, 0, 0x4, SISLANDS_CACCONFIG_CGIND },
 864         { 0x13, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND },
 865         { 0x14, 0x0000ffff, 0, 0x362, SISLANDS_CACCONFIG_CGIND },
 866         { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 867         { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND },
 868         { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 869         { 0x16, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND },
 870         { 0x16, 0xffff0000, 16, 0x7A, SISLANDS_CACCONFIG_CGIND },
 871         { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 872         { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 873         { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 874         { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 875         { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 876         { 0x1a, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
 877         { 0x1a, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
 878         { 0x1b, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
 879         { 0x1b, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
 880         { 0x1c, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
 881         { 0x1c, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
 882         { 0x1d, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
 883         { 0x1d, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
 884         { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
 885         { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
 886         { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
 887         { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
 888         { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
 889         { 0x6d, 0x0000ffff, 0, 0x100, SISLANDS_CACCONFIG_CGIND },
 890         { 0xFFFFFFFF }
 891 };
 892
 893 static const struct si_cac_config_reg cac_weights_cape_verde_pro[] =
 894 {
 895         { 0x0, 0x0000ffff, 0, 0x82, SISLANDS_CACCONFIG_CGIND },
 896         { 0x0, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND },
 897         { 0x1, 0x0000ffff, 0, 0x153, SISLANDS_CACCONFIG_CGIND },
 898         { 0x1, 0xffff0000, 16, 0x52, SISLANDS_CACCONFIG_CGIND },
 899         { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 900         { 0x3, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND },
 901         { 0x3, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND },
 902         { 0x4, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND },
 903         { 0x4, 0xffff0000, 16, 0xAC, SISLANDS_CACCONFIG_CGIND },
 904         { 0x5, 0x0000ffff, 0, 0x118, SISLANDS_CACCONFIG_CGIND },
 905         { 0x5, 0xffff0000, 16, 0xBE, SISLANDS_CACCONFIG_CGIND },
 906         { 0x6, 0x0000ffff, 0, 0x110, SISLANDS_CACCONFIG_CGIND },
 907         { 0x6, 0xffff0000, 16, 0x4CD, SISLANDS_CACCONFIG_CGIND },
 908         { 0x18f, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND },
 909         { 0x7, 0x0000ffff, 0, 0x37, SISLANDS_CACCONFIG_CGIND },
 910         { 0x7, 0xffff0000, 16, 0x27, SISLANDS_CACCONFIG_CGIND },
 911         { 0x8, 0x0000ffff, 0, 0xC3, SISLANDS_CACCONFIG_CGIND },
 912         { 0x8, 0xffff0000, 16, 0x35, SISLANDS_CACCONFIG_CGIND },
 913         { 0x9, 0x0000ffff, 0, 0x28, SISLANDS_CACCONFIG_CGIND },
 914         { 0xa, 0x0000ffff, 0, 0x26C, SISLANDS_CACCONFIG_CGIND },
 915         { 0xb, 0x0000ffff, 0, 0x3B2, SISLANDS_CACCONFIG_CGIND },
 916         { 0xb, 0xffff0000, 16, 0x99D, SISLANDS_CACCONFIG_CGIND },
 917         { 0xc, 0x0000ffff, 0, 0xA3F, SISLANDS_CACCONFIG_CGIND },
 918         { 0xd, 0x0000ffff, 0, 0xA, SISLANDS_CACCONFIG_CGIND },
 919         { 0xd, 0xffff0000, 16, 0xA, SISLANDS_CACCONFIG_CGIND },
 920         { 0xe, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
 921         { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND },
 922         { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 923         { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 924         { 0x10, 0xffff0000, 16, 0x1, SISLANDS_CACCONFIG_CGIND },
 925         { 0x11, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
 926         { 0x11, 0xffff0000, 16, 0x15, SISLANDS_CACCONFIG_CGIND },
 927         { 0x12, 0x0000ffff, 0, 0x34, SISLANDS_CACCONFIG_CGIND },
 928         { 0x13, 0x0000ffff, 0, 0x4, SISLANDS_CACCONFIG_CGIND },
 929         { 0x13, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND },
 930         { 0x14, 0x0000ffff, 0, 0x315, SISLANDS_CACCONFIG_CGIND },
 931         { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 932         { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND },
 933         { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 934         { 0x16, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND },
 935         { 0x16, 0xffff0000, 16, 0x7A, SISLANDS_CACCONFIG_CGIND },
 936         { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 937         { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 938         { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 939         { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 940         { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 941         { 0x1a, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
 942         { 0x1a, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
 943         { 0x1b, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
 944         { 0x1b, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
 945         { 0x1c, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
 946         { 0x1c, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
 947         { 0x1d, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
 948         { 0x1d, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
 949         { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
 950         { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
 951         { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
 952         { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
 953         { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
 954         { 0x6d, 0x0000ffff, 0, 0x100, SISLANDS_CACCONFIG_CGIND },
 955         { 0xFFFFFFFF }
 956 };
 957
 958 static const struct si_cac_config_reg cac_weights_cape_verde[] =
 959 {
 960         { 0x0, 0x0000ffff, 0, 0x82, SISLANDS_CACCONFIG_CGIND },
 961         { 0x0, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND },
 962         { 0x1, 0x0000ffff, 0, 0x153, SISLANDS_CACCONFIG_CGIND },
 963         { 0x1, 0xffff0000, 16, 0x52, SISLANDS_CACCONFIG_CGIND },
 964         { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 965         { 0x3, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND },
 966         { 0x3, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND },
 967         { 0x4, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND },
 968         { 0x4, 0xffff0000, 16, 0xAC, SISLANDS_CACCONFIG_CGIND },
 969         { 0x5, 0x0000ffff, 0, 0x118, SISLANDS_CACCONFIG_CGIND },
 970         { 0x5, 0xffff0000, 16, 0xBE, SISLANDS_CACCONFIG_CGIND },
 971         { 0x6, 0x0000ffff, 0, 0x110, SISLANDS_CACCONFIG_CGIND },
 972         { 0x6, 0xffff0000, 16, 0x4CD, SISLANDS_CACCONFIG_CGIND },
 973         { 0x18f, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND },
 974         { 0x7, 0x0000ffff, 0, 0x37, SISLANDS_CACCONFIG_CGIND },
 975         { 0x7, 0xffff0000, 16, 0x27, SISLANDS_CACCONFIG_CGIND },
 976         { 0x8, 0x0000ffff, 0, 0xC3, SISLANDS_CACCONFIG_CGIND },
 977         { 0x8, 0xffff0000, 16, 0x35, SISLANDS_CACCONFIG_CGIND },
 978         { 0x9, 0x0000ffff, 0, 0x28, SISLANDS_CACCONFIG_CGIND },
 979         { 0xa, 0x0000ffff, 0, 0x26C, SISLANDS_CACCONFIG_CGIND },
 980         { 0xb, 0x0000ffff, 0, 0x3B2, SISLANDS_CACCONFIG_CGIND },
 981         { 0xb, 0xffff0000, 16, 0x99D, SISLANDS_CACCONFIG_CGIND },
 982         { 0xc, 0x0000ffff, 0, 0xA3F, SISLANDS_CACCONFIG_CGIND },
 983         { 0xd, 0x0000ffff, 0, 0xA, SISLANDS_CACCONFIG_CGIND },
 984         { 0xd, 0xffff0000, 16, 0xA, SISLANDS_CACCONFIG_CGIND },
 985         { 0xe, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
 986         { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND },
 987         { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 988         { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 989         { 0x10, 0xffff0000, 16, 0x1, SISLANDS_CACCONFIG_CGIND },
 990         { 0x11, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
 991         { 0x11, 0xffff0000, 16, 0x15, SISLANDS_CACCONFIG_CGIND },
 992         { 0x12, 0x0000ffff, 0, 0x34, SISLANDS_CACCONFIG_CGIND },
 993         { 0x13, 0x0000ffff, 0, 0x4, SISLANDS_CACCONFIG_CGIND },
 994         { 0x13, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND },
 995         { 0x14, 0x0000ffff, 0, 0x3BA, SISLANDS_CACCONFIG_CGIND },
 996         { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 997         { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND },
 998         { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 999         { 0x16, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND },
1000         { 0x16, 0xffff0000, 16, 0x7A, SISLANDS_CACCONFIG_CGIND },
1001         { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1002         { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1003         { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1004         { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1005         { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1006         { 0x1a, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1007         { 0x1a, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1008         { 0x1b, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1009         { 0x1b, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1010         { 0x1c, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1011         { 0x1c, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1012         { 0x1d, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1013         { 0x1d, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1014         { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1015         { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1016         { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1017         { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1018         { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1019         { 0x6d, 0x0000ffff, 0, 0x100, SISLANDS_CACCONFIG_CGIND },
1020         { 0xFFFFFFFF }
1021 };
1022
1023 static const struct si_cac_config_reg lcac_cape_verde[] =
1024 {
1025         { 0x98, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1026         { 0x98, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1027         { 0x104, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1028         { 0x104, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1029         { 0x110, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
1030         { 0x110, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1031         { 0x14f, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
1032         { 0x14f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1033         { 0x8c, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
1034         { 0x8c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1035         { 0x143, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1036         { 0x143, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1037         { 0x9b, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1038         { 0x9b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1039         { 0x107, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1040         { 0x107, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1041         { 0x113, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
1042         { 0x113, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1043         { 0x152, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
1044         { 0x152, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1045         { 0x8f, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1046         { 0x8f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1047         { 0x146, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1048         { 0x146, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1049         { 0x11c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1050         { 0x11c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1051         { 0x11f, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1052         { 0x11f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1053         { 0x164, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1054         { 0x164, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1055         { 0x167, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1056         { 0x167, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1057         { 0x16a, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1058         { 0x16a, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1059         { 0x15e, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1060         { 0x15e, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1061         { 0x161, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1062         { 0x161, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1063         { 0x15b, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1064         { 0x15b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1065         { 0x16d, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1066         { 0x16d, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1067         { 0x170, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1068         { 0x170, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1069         { 0x173, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1070         { 0x173, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1071         { 0x176, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1072         { 0x176, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1073         { 0x179, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1074         { 0x179, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1075         { 0x17c, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1076         { 0x17c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1077         { 0x17f, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1078         { 0x17f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1079         { 0xFFFFFFFF }
1080 };
1081
1082 static const struct si_cac_config_reg cac_override_cape_verde[] =
1083 {
1084     { 0xFFFFFFFF }
1085 };
1086
1087 static const struct si_powertune_data powertune_data_cape_verde =
1088 {
1089         ((1 << 16) | 0x6993),
1090         5,
1091         0,
1092         7,
1093         105,
1094         {
1095                 0UL,
1096                 0UL,
1097                 7194395UL,
1098                 309631529UL,
1099                 -1270850L,
1100                 4513710L,
1101                 100
1102         },
1103         117830498UL,
1104         12,
1105         {
1106                 0,
1107                 0,
1108                 0,
1109                 0,
1110                 0,
1111                 0,
1112                 0,
1113                 0
1114         },
1115         true
1116 };
1117
1118 static const struct si_dte_data dte_data_cape_verde =
1119 {
1120         { 0, 0, 0, 0, 0 },
1121         { 0, 0, 0, 0, 0 },
1122         0,
1123         0,
1124         0,
1125         0,
1126         0,
1127         0,
1128         0,
1129         { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
1130         { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
1131         { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
1132         0,
1133         false
1134 };
1135
1136 static const struct si_dte_data dte_data_venus_xtx =
1137 {
1138         { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 },
1139         { 0x71C, 0xAAB, 0xE39, 0x11C7, 0x0 },
1140         5,
1141         55000,
1142         0x69,
1143         0xA,
1144         1,
1145         0,
1146         0x3,
1147         { 0x96, 0xB4, 0xFF, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
1148         { 0x895440, 0x3D0900, 0x989680, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
1149         { 0xD6D8, 0x88B8, 0x1555, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
1150         90,
1151         true
1152 };
1153
1154 static const struct si_dte_data dte_data_venus_xt =
1155 {
1156         { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 },
1157         { 0xBDA, 0x11C7, 0x17B4, 0x1DA1, 0x0 },
1158         5,
1159         55000,
1160         0x69,
1161         0xA,
1162         1,
1163         0,
1164         0x3,
1165         { 0x96, 0xB4, 0xFF, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
1166         { 0x895440, 0x3D0900, 0x989680, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
1167         { 0xAFC8, 0x88B8, 0x238E, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
1168         90,
1169         true
1170 };
1171
1172 static const struct si_dte_data dte_data_venus_pro =
1173 {
1174         {  0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 },
1175         { 0x11C7, 0x1AAB, 0x238E, 0x2C72, 0x0 },
1176         5,
1177         55000,
1178         0x69,
1179         0xA,
1180         1,
1181         0,
1182         0x3,
1183         { 0x96, 0xB4, 0xFF, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
1184         { 0x895440, 0x3D0900, 0x989680, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
1185         { 0x88B8, 0x88B8, 0x3555, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
1186         90,
1187         true
1188 };
1189
1190 static const struct si_cac_config_reg cac_weights_oland[] =
1191 {
1192         { 0x0, 0x0000ffff, 0, 0x82, SISLANDS_CACCONFIG_CGIND },
1193         { 0x0, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND },
1194         { 0x1, 0x0000ffff, 0, 0x153, SISLANDS_CACCONFIG_CGIND },
1195         { 0x1, 0xffff0000, 16, 0x52, SISLANDS_CACCONFIG_CGIND },
1196         { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1197         { 0x3, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND },
1198         { 0x3, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND },
1199         { 0x4, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND },
1200         { 0x4, 0xffff0000, 16, 0xAC, SISLANDS_CACCONFIG_CGIND },
1201         { 0x5, 0x0000ffff, 0, 0x118, SISLANDS_CACCONFIG_CGIND },
1202         { 0x5, 0xffff0000, 16, 0xBE, SISLANDS_CACCONFIG_CGIND },
1203         { 0x6, 0x0000ffff, 0, 0x110, SISLANDS_CACCONFIG_CGIND },
1204         { 0x6, 0xffff0000, 16, 0x4CD, SISLANDS_CACCONFIG_CGIND },
1205         { 0x18f, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND },
1206         { 0x7, 0x0000ffff, 0, 0x37, SISLANDS_CACCONFIG_CGIND },
1207         { 0x7, 0xffff0000, 16, 0x27, SISLANDS_CACCONFIG_CGIND },
1208         { 0x8, 0x0000ffff, 0, 0xC3, SISLANDS_CACCONFIG_CGIND },
1209         { 0x8, 0xffff0000, 16, 0x35, SISLANDS_CACCONFIG_CGIND },
1210         { 0x9, 0x0000ffff, 0, 0x28, SISLANDS_CACCONFIG_CGIND },
1211         { 0xa, 0x0000ffff, 0, 0x26C, SISLANDS_CACCONFIG_CGIND },
1212         { 0xb, 0x0000ffff, 0, 0x3B2, SISLANDS_CACCONFIG_CGIND },
1213         { 0xb, 0xffff0000, 16, 0x99D, SISLANDS_CACCONFIG_CGIND },
1214         { 0xc, 0x0000ffff, 0, 0xA3F, SISLANDS_CACCONFIG_CGIND },
1215         { 0xd, 0x0000ffff, 0, 0xA, SISLANDS_CACCONFIG_CGIND },
1216         { 0xd, 0xffff0000, 16, 0xA, SISLANDS_CACCONFIG_CGIND },
1217         { 0xe, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
1218         { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND },
1219         { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1220         { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1221         { 0x10, 0xffff0000, 16, 0x1, SISLANDS_CACCONFIG_CGIND },
1222         { 0x11, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
1223         { 0x11, 0xffff0000, 16, 0x15, SISLANDS_CACCONFIG_CGIND },
1224         { 0x12, 0x0000ffff, 0, 0x34, SISLANDS_CACCONFIG_CGIND },
1225         { 0x13, 0x0000ffff, 0, 0x4, SISLANDS_CACCONFIG_CGIND },
1226         { 0x13, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND },
1227         { 0x14, 0x0000ffff, 0, 0x3BA, SISLANDS_CACCONFIG_CGIND },
1228         { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1229         { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND },
1230         { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1231         { 0x16, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND },
1232         { 0x16, 0xffff0000, 16, 0x7A, SISLANDS_CACCONFIG_CGIND },
1233         { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1234         { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1235         { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1236         { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1237         { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1238         { 0x1a, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1239         { 0x1a, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1240         { 0x1b, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1241         { 0x1b, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1242         { 0x1c, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1243         { 0x1c, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1244         { 0x1d, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1245         { 0x1d, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1246         { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1247         { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1248         { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1249         { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1250         { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1251         { 0x6d, 0x0000ffff, 0, 0x100, SISLANDS_CACCONFIG_CGIND },
1252         { 0xFFFFFFFF }
1253 };
1254
1255 static const struct si_cac_config_reg cac_weights_mars_pro[] =
1256 {
1257         { 0x0, 0x0000ffff, 0, 0x43, SISLANDS_CACCONFIG_CGIND },
1258         { 0x0, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND },
1259         { 0x1, 0x0000ffff, 0, 0xAF, SISLANDS_CACCONFIG_CGIND },
1260         { 0x1, 0xffff0000, 16, 0x2A, SISLANDS_CACCONFIG_CGIND },
1261         { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1262         { 0x3, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND },
1263         { 0x3, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND },
1264         { 0x4, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND },
1265         { 0x4, 0xffff0000, 16, 0x59, SISLANDS_CACCONFIG_CGIND },
1266         { 0x5, 0x0000ffff, 0, 0x1A5, SISLANDS_CACCONFIG_CGIND },
1267         { 0x5, 0xffff0000, 16, 0x1D6, SISLANDS_CACCONFIG_CGIND },
1268         { 0x6, 0x0000ffff, 0, 0x2A3, SISLANDS_CACCONFIG_CGIND },
1269         { 0x6, 0xffff0000, 16, 0x8FD, SISLANDS_CACCONFIG_CGIND },
1270         { 0x18f, 0x0000ffff, 0, 0x76, SISLANDS_CACCONFIG_CGIND },
1271         { 0x7, 0x0000ffff, 0, 0x8A, SISLANDS_CACCONFIG_CGIND },
1272         { 0x7, 0xffff0000, 16, 0xA3, SISLANDS_CACCONFIG_CGIND },
1273         { 0x8, 0x0000ffff, 0, 0x71, SISLANDS_CACCONFIG_CGIND },
1274         { 0x8, 0xffff0000, 16, 0x36, SISLANDS_CACCONFIG_CGIND },
1275         { 0x9, 0x0000ffff, 0, 0xA6, SISLANDS_CACCONFIG_CGIND },
1276         { 0xa, 0x0000ffff, 0, 0x81, SISLANDS_CACCONFIG_CGIND },
1277         { 0xb, 0x0000ffff, 0, 0x3D2, SISLANDS_CACCONFIG_CGIND },
1278         { 0xb, 0xffff0000, 16, 0x27C, SISLANDS_CACCONFIG_CGIND },
1279         { 0xc, 0x0000ffff, 0, 0xA96, SISLANDS_CACCONFIG_CGIND },
1280         { 0xd, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
1281         { 0xd, 0xffff0000, 16, 0x5, SISLANDS_CACCONFIG_CGIND },
1282         { 0xe, 0x0000ffff, 0, 0xB, SISLANDS_CACCONFIG_CGIND },
1283         { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND },
1284         { 0xf, 0xffff0000, 16, 0x2, SISLANDS_CACCONFIG_CGIND },
1285         { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1286         { 0x10, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND },
1287         { 0x11, 0x0000ffff, 0, 0x15, SISLANDS_CACCONFIG_CGIND },
1288         { 0x11, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND },
1289         { 0x12, 0x0000ffff, 0, 0x36, SISLANDS_CACCONFIG_CGIND },
1290         { 0x13, 0x0000ffff, 0, 0x10, SISLANDS_CACCONFIG_CGIND },
1291         { 0x13, 0xffff0000, 16, 0x10, SISLANDS_CACCONFIG_CGIND },
1292         { 0x14, 0x0000ffff, 0, 0x2, SISLANDS_CACCONFIG_CGIND },
1293         { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1294         { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND },
1295         { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1296         { 0x16, 0x0000ffff, 0, 0x32, SISLANDS_CACCONFIG_CGIND },
1297         { 0x16, 0xffff0000, 16, 0x7E, SISLANDS_CACCONFIG_CGIND },
1298         { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1299         { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1300         { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1301         { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1302         { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1303         { 0x1a, 0x0000ffff, 0, 0x280, SISLANDS_CACCONFIG_CGIND },
1304         { 0x1a, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND },
1305         { 0x1b, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1306         { 0x1b, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1307         { 0x1c, 0x0000ffff, 0, 0x3C, SISLANDS_CACCONFIG_CGIND },
1308         { 0x1c, 0xffff0000, 16, 0x203, SISLANDS_CACCONFIG_CGIND },
1309         { 0x1d, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1310         { 0x1d, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1311         { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1312         { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1313         { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1314         { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1315         { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1316         { 0x6d, 0x0000ffff, 0, 0xB4, SISLANDS_CACCONFIG_CGIND },
1317         { 0xFFFFFFFF }
1318 };
1319
1320 static const struct si_cac_config_reg cac_weights_mars_xt[] =
1321 {
1322         { 0x0, 0x0000ffff, 0, 0x43, SISLANDS_CACCONFIG_CGIND },
1323         { 0x0, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND },
1324         { 0x1, 0x0000ffff, 0, 0xAF, SISLANDS_CACCONFIG_CGIND },
1325         { 0x1, 0xffff0000, 16, 0x2A, SISLANDS_CACCONFIG_CGIND },
1326         { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1327         { 0x3, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND },
1328         { 0x3, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND },
1329         { 0x4, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND },
1330         { 0x4, 0xffff0000, 16, 0x59, SISLANDS_CACCONFIG_CGIND },
1331         { 0x5, 0x0000ffff, 0, 0x1A5, SISLANDS_CACCONFIG_CGIND },
1332         { 0x5, 0xffff0000, 16, 0x1D6, SISLANDS_CACCONFIG_CGIND },
1333         { 0x6, 0x0000ffff, 0, 0x2A3, SISLANDS_CACCONFIG_CGIND },
1334         { 0x6, 0xffff0000, 16, 0x8FD, SISLANDS_CACCONFIG_CGIND },
1335         { 0x18f, 0x0000ffff, 0, 0x76, SISLANDS_CACCONFIG_CGIND },
1336         { 0x7, 0x0000ffff, 0, 0x8A, SISLANDS_CACCONFIG_CGIND },
1337         { 0x7, 0xffff0000, 16, 0xA3, SISLANDS_CACCONFIG_CGIND },
1338         { 0x8, 0x0000ffff, 0, 0x71, SISLANDS_CACCONFIG_CGIND },
1339         { 0x8, 0xffff0000, 16, 0x36, SISLANDS_CACCONFIG_CGIND },
1340         { 0x9, 0x0000ffff, 0, 0xA6, SISLANDS_CACCONFIG_CGIND },
1341         { 0xa, 0x0000ffff, 0, 0x81, SISLANDS_CACCONFIG_CGIND },
1342         { 0xb, 0x0000ffff, 0, 0x3D2, SISLANDS_CACCONFIG_CGIND },
1343         { 0xb, 0xffff0000, 16, 0x27C, SISLANDS_CACCONFIG_CGIND },
1344         { 0xc, 0x0000ffff, 0, 0xA96, SISLANDS_CACCONFIG_CGIND },
1345         { 0xd, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
1346         { 0xd, 0xffff0000, 16, 0x5, SISLANDS_CACCONFIG_CGIND },
1347         { 0xe, 0x0000ffff, 0, 0xB, SISLANDS_CACCONFIG_CGIND },
1348         { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND },
1349         { 0xf, 0xffff0000, 16, 0x2, SISLANDS_CACCONFIG_CGIND },
1350         { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1351         { 0x10, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND },
1352         { 0x11, 0x0000ffff, 0, 0x15, SISLANDS_CACCONFIG_CGIND },
1353         { 0x11, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND },
1354         { 0x12, 0x0000ffff, 0, 0x36, SISLANDS_CACCONFIG_CGIND },
1355         { 0x13, 0x0000ffff, 0, 0x10, SISLANDS_CACCONFIG_CGIND },
1356         { 0x13, 0xffff0000, 16, 0x10, SISLANDS_CACCONFIG_CGIND },
1357         { 0x14, 0x0000ffff, 0, 0x60, SISLANDS_CACCONFIG_CGIND },
1358         { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1359         { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND },
1360         { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1361         { 0x16, 0x0000ffff, 0, 0x32, SISLANDS_CACCONFIG_CGIND },
1362         { 0x16, 0xffff0000, 16, 0x7E, SISLANDS_CACCONFIG_CGIND },
1363         { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1364         { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1365         { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1366         { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1367         { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1368         { 0x1a, 0x0000ffff, 0, 0x280, SISLANDS_CACCONFIG_CGIND },
1369         { 0x1a, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND },
1370         { 0x1b, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1371         { 0x1b, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1372         { 0x1c, 0x0000ffff, 0, 0x3C, SISLANDS_CACCONFIG_CGIND },
1373         { 0x1c, 0xffff0000, 16, 0x203, SISLANDS_CACCONFIG_CGIND },
1374         { 0x1d, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1375         { 0x1d, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1376         { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1377         { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1378         { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1379         { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1380         { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1381         { 0x6d, 0x0000ffff, 0, 0xB4, SISLANDS_CACCONFIG_CGIND },
1382         { 0xFFFFFFFF }
1383 };
1384
1385 static const struct si_cac_config_reg cac_weights_oland_pro[] =
1386 {
1387         { 0x0, 0x0000ffff, 0, 0x43, SISLANDS_CACCONFIG_CGIND },
1388         { 0x0, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND },
1389         { 0x1, 0x0000ffff, 0, 0xAF, SISLANDS_CACCONFIG_CGIND },
1390         { 0x1, 0xffff0000, 16, 0x2A, SISLANDS_CACCONFIG_CGIND },
1391         { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1392         { 0x3, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND },
1393         { 0x3, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND },
1394         { 0x4, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND },
1395         { 0x4, 0xffff0000, 16, 0x59, SISLANDS_CACCONFIG_CGIND },
1396         { 0x5, 0x0000ffff, 0, 0x1A5, SISLANDS_CACCONFIG_CGIND },
1397         { 0x5, 0xffff0000, 16, 0x1D6, SISLANDS_CACCONFIG_CGIND },
1398         { 0x6, 0x0000ffff, 0, 0x2A3, SISLANDS_CACCONFIG_CGIND },
1399         { 0x6, 0xffff0000, 16, 0x8FD, SISLANDS_CACCONFIG_CGIND },
1400         { 0x18f, 0x0000ffff, 0, 0x76, SISLANDS_CACCONFIG_CGIND },
1401         { 0x7, 0x0000ffff, 0, 0x8A, SISLANDS_CACCONFIG_CGIND },
1402         { 0x7, 0xffff0000, 16, 0xA3, SISLANDS_CACCONFIG_CGIND },
1403         { 0x8, 0x0000ffff, 0, 0x71, SISLANDS_CACCONFIG_CGIND },
1404         { 0x8, 0xffff0000, 16, 0x36, SISLANDS_CACCONFIG_CGIND },
1405         { 0x9, 0x0000ffff, 0, 0xA6, SISLANDS_CACCONFIG_CGIND },
1406         { 0xa, 0x0000ffff, 0, 0x81, SISLANDS_CACCONFIG_CGIND },
1407         { 0xb, 0x0000ffff, 0, 0x3D2, SISLANDS_CACCONFIG_CGIND },
1408         { 0xb, 0xffff0000, 16, 0x27C, SISLANDS_CACCONFIG_CGIND },
1409         { 0xc, 0x0000ffff, 0, 0xA96, SISLANDS_CACCONFIG_CGIND },
1410         { 0xd, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
1411         { 0xd, 0xffff0000, 16, 0x5, SISLANDS_CACCONFIG_CGIND },
1412         { 0xe, 0x0000ffff, 0, 0xB, SISLANDS_CACCONFIG_CGIND },
1413         { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND },
1414         { 0xf, 0xffff0000, 16, 0x2, SISLANDS_CACCONFIG_CGIND },
1415         { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1416         { 0x10, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND },
1417         { 0x11, 0x0000ffff, 0, 0x15, SISLANDS_CACCONFIG_CGIND },
1418         { 0x11, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND },
1419         { 0x12, 0x0000ffff, 0, 0x36, SISLANDS_CACCONFIG_CGIND },
1420         { 0x13, 0x0000ffff, 0, 0x10, SISLANDS_CACCONFIG_CGIND },
1421         { 0x13, 0xffff0000, 16, 0x10, SISLANDS_CACCONFIG_CGIND },
1422         { 0x14, 0x0000ffff, 0, 0x90, SISLANDS_CACCONFIG_CGIND },
1423         { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1424         { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND },
1425         { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1426         { 0x16, 0x0000ffff, 0, 0x32, SISLANDS_CACCONFIG_CGIND },
1427         { 0x16, 0xffff0000, 16, 0x7E, SISLANDS_CACCONFIG_CGIND },
1428         { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1429         { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1430         { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1431         { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1432         { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1433         { 0x1a, 0x0000ffff, 0, 0x280, SISLANDS_CACCONFIG_CGIND },
1434         { 0x1a, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND },
1435         { 0x1b, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1436         { 0x1b, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1437         { 0x1c, 0x0000ffff, 0, 0x3C, SISLANDS_CACCONFIG_CGIND },
1438         { 0x1c, 0xffff0000, 16, 0x203, SISLANDS_CACCONFIG_CGIND },
1439         { 0x1d, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1440         { 0x1d, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1441         { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1442         { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1443         { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1444         { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1445         { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1446         { 0x6d, 0x0000ffff, 0, 0xB4, SISLANDS_CACCONFIG_CGIND },
1447         { 0xFFFFFFFF }
1448 };
1449
1450 static const struct si_cac_config_reg cac_weights_oland_xt[] =
1451 {
1452         { 0x0, 0x0000ffff, 0, 0x43, SISLANDS_CACCONFIG_CGIND },
1453         { 0x0, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND },
1454         { 0x1, 0x0000ffff, 0, 0xAF, SISLANDS_CACCONFIG_CGIND },
1455         { 0x1, 0xffff0000, 16, 0x2A, SISLANDS_CACCONFIG_CGIND },
1456         { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1457         { 0x3, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND },
1458         { 0x3, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND },
1459         { 0x4, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND },
1460         { 0x4, 0xffff0000, 16, 0x59, SISLANDS_CACCONFIG_CGIND },
1461         { 0x5, 0x0000ffff, 0, 0x1A5, SISLANDS_CACCONFIG_CGIND },
1462         { 0x5, 0xffff0000, 16, 0x1D6, SISLANDS_CACCONFIG_CGIND },
1463         { 0x6, 0x0000ffff, 0, 0x2A3, SISLANDS_CACCONFIG_CGIND },
1464         { 0x6, 0xffff0000, 16, 0x8FD, SISLANDS_CACCONFIG_CGIND },
1465         { 0x18f, 0x0000ffff, 0, 0x76, SISLANDS_CACCONFIG_CGIND },
1466         { 0x7, 0x0000ffff, 0, 0x8A, SISLANDS_CACCONFIG_CGIND },
1467         { 0x7, 0xffff0000, 16, 0xA3, SISLANDS_CACCONFIG_CGIND },
1468         { 0x8, 0x0000ffff, 0, 0x71, SISLANDS_CACCONFIG_CGIND },
1469         { 0x8, 0xffff0000, 16, 0x36, SISLANDS_CACCONFIG_CGIND },
1470         { 0x9, 0x0000ffff, 0, 0xA6, SISLANDS_CACCONFIG_CGIND },
1471         { 0xa, 0x0000ffff, 0, 0x81, SISLANDS_CACCONFIG_CGIND },
1472         { 0xb, 0x0000ffff, 0, 0x3D2, SISLANDS_CACCONFIG_CGIND },
1473         { 0xb, 0xffff0000, 16, 0x27C, SISLANDS_CACCONFIG_CGIND },
1474         { 0xc, 0x0000ffff, 0, 0xA96, SISLANDS_CACCONFIG_CGIND },
1475         { 0xd, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
1476         { 0xd, 0xffff0000, 16, 0x5, SISLANDS_CACCONFIG_CGIND },
1477         { 0xe, 0x0000ffff, 0, 0xB, SISLANDS_CACCONFIG_CGIND },
1478         { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND },
1479         { 0xf, 0xffff0000, 16, 0x2, SISLANDS_CACCONFIG_CGIND },
1480         { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1481         { 0x10, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND },
1482         { 0x11, 0x0000ffff, 0, 0x15, SISLANDS_CACCONFIG_CGIND },
1483         { 0x11, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND },
1484         { 0x12, 0x0000ffff, 0, 0x36, SISLANDS_CACCONFIG_CGIND },
1485         { 0x13, 0x0000ffff, 0, 0x10, SISLANDS_CACCONFIG_CGIND },
1486         { 0x13, 0xffff0000, 16, 0x10, SISLANDS_CACCONFIG_CGIND },
1487         { 0x14, 0x0000ffff, 0, 0x120, SISLANDS_CACCONFIG_CGIND },
1488         { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1489         { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND },
1490         { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1491         { 0x16, 0x0000ffff, 0, 0x32, SISLANDS_CACCONFIG_CGIND },
1492         { 0x16, 0xffff0000, 16, 0x7E, SISLANDS_CACCONFIG_CGIND },
1493         { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1494         { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1495         { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1496         { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1497         { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1498         { 0x1a, 0x0000ffff, 0, 0x280, SISLANDS_CACCONFIG_CGIND },
1499         { 0x1a, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND },
1500         { 0x1b, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1501         { 0x1b, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1502         { 0x1c, 0x0000ffff, 0, 0x3C, SISLANDS_CACCONFIG_CGIND },
1503         { 0x1c, 0xffff0000, 16, 0x203, SISLANDS_CACCONFIG_CGIND },
1504         { 0x1d, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1505         { 0x1d, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1506         { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1507         { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1508         { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1509         { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1510         { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1511         { 0x6d, 0x0000ffff, 0, 0xB4, SISLANDS_CACCONFIG_CGIND },
1512         { 0xFFFFFFFF }
1513 };
1514
1515 static const struct si_cac_config_reg lcac_oland[] =
1516 {
1517         { 0x98, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1518         { 0x98, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1519         { 0x104, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1520         { 0x104, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1521         { 0x110, 0x0001fffe, 1, 0x6, SISLANDS_CACCONFIG_CGIND },
1522         { 0x110, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1523         { 0x14f, 0x0001fffe, 1, 0x6, SISLANDS_CACCONFIG_CGIND },
1524         { 0x14f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1525         { 0x8c, 0x0001fffe, 1, 0x6, SISLANDS_CACCONFIG_CGIND },
1526         { 0x8c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1527         { 0x143, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
1528         { 0x143, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1529         { 0x11c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1530         { 0x11c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1531         { 0x11f, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1532         { 0x11f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1533         { 0x164, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1534         { 0x164, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1535         { 0x167, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1536         { 0x167, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1537         { 0x16a, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1538         { 0x16a, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1539         { 0x15e, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1540         { 0x15e, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1541         { 0x161, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1542         { 0x161, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1543         { 0x15b, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1544         { 0x15b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1545         { 0x16d, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1546         { 0x16d, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1547         { 0x170, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1548         { 0x170, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1549         { 0x173, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1550         { 0x173, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1551         { 0x176, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1552         { 0x176, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1553         { 0x179, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1554         { 0x179, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1555         { 0x17c, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1556         { 0x17c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1557         { 0x17f, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1558         { 0x17f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1559         { 0xFFFFFFFF }
1560 };
1561
1562 static const struct si_cac_config_reg lcac_mars_pro[] =
1563 {
1564         { 0x98, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1565         { 0x98, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1566         { 0x104, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1567         { 0x104, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1568         { 0x110, 0x0001fffe, 1, 0x6, SISLANDS_CACCONFIG_CGIND },
1569         { 0x110, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1570         { 0x14f, 0x0001fffe, 1, 0x6, SISLANDS_CACCONFIG_CGIND },
1571         { 0x14f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1572         { 0x8c, 0x0001fffe, 1, 0x6, SISLANDS_CACCONFIG_CGIND },
1573         { 0x8c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1574         { 0x143, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1575         { 0x143, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1576         { 0x11c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1577         { 0x11c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1578         { 0x11f, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1579         { 0x11f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1580         { 0x164, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1581         { 0x164, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1582         { 0x167, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1583         { 0x167, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1584         { 0x16a, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1585         { 0x16a, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1586         { 0x15e, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1587         { 0x15e, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1588         { 0x161, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1589         { 0x161, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1590         { 0x15b, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1591         { 0x15b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1592         { 0x16d, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1593         { 0x16d, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1594         { 0x170, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1595         { 0x170, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1596         { 0x173, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1597         { 0x173, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1598         { 0x176, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1599         { 0x176, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1600         { 0x179, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1601         { 0x179, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1602         { 0x17c, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1603         { 0x17c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1604         { 0x17f, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1605         { 0x17f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1606         { 0xFFFFFFFF }
1607 };
1608
1609 static const struct si_cac_config_reg cac_override_oland[] =
1610 {
1611         { 0xFFFFFFFF }
1612 };
1613
1614 static const struct si_powertune_data powertune_data_oland =
1615 {
1616         ((1 << 16) | 0x6993),
1617         5,
1618         0,
1619         7,
1620         105,
1621         {
1622                 0UL,
1623                 0UL,
1624                 7194395UL,
1625                 309631529UL,
1626                 -1270850L,
1627                 4513710L,
1628                 100
1629         },
1630         117830498UL,
1631         12,
1632         {
1633                 0,
1634                 0,
1635                 0,
1636                 0,
1637                 0,
1638                 0,
1639                 0,
1640                 0
1641         },
1642         true
1643 };
1644
1645 static const struct si_powertune_data powertune_data_mars_pro =
1646 {
1647         ((1 << 16) | 0x6993),
1648         5,
1649         0,
1650         7,
1651         105,
1652         {
1653                 0UL,
1654                 0UL,
1655                 7194395UL,
1656                 309631529UL,
1657                 -1270850L,
1658                 4513710L,
1659                 100
1660         },
1661         117830498UL,
1662         12,
1663         {
1664                 0,
1665                 0,
1666                 0,
1667                 0,
1668                 0,
1669                 0,
1670                 0,
1671                 0
1672         },
1673         true
1674 };
1675
1676 static const struct si_dte_data dte_data_oland =
1677 {
1678         { 0, 0, 0, 0, 0 },
1679         { 0, 0, 0, 0, 0 },
1680         0,
1681         0,
1682         0,
1683         0,
1684         0,
1685         0,
1686         0,
1687         { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
1688         { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
1689         { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
1690         0,
1691         false
1692 };
1693
1694 static const struct si_dte_data dte_data_mars_pro =
1695 {
1696         { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 },
1697         { 0x0, 0x0, 0x0, 0x0, 0x0 },
1698         5,
1699         55000,
1700         105,
1701         0xA,
1702         1,
1703         0,
1704         0x10,
1705         { 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF },
1706         { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 },
1707         { 0xF627, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
1708         90,
1709         true
1710 };
1711
1712 static const struct si_dte_data dte_data_sun_xt =
1713 {
1714         { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 },
1715         { 0x0, 0x0, 0x0, 0x0, 0x0 },
1716         5,
1717         55000,
1718         105,
1719         0xA,
1720         1,
1721         0,
1722         0x10,
1723         { 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF },
1724         { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 },
1725         { 0xD555, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
1726         90,
1727         true
1728 };
1729
1730
1731 static const struct si_cac_config_reg cac_weights_hainan[] =
1732 {
1733         { 0x0, 0x0000ffff, 0, 0x2d9, SISLANDS_CACCONFIG_CGIND },
1734         { 0x0, 0xffff0000, 16, 0x22b, SISLANDS_CACCONFIG_CGIND },
1735         { 0x1, 0x0000ffff, 0, 0x21c, SISLANDS_CACCONFIG_CGIND },
1736         { 0x1, 0xffff0000, 16, 0x1dc, SISLANDS_CACCONFIG_CGIND },
1737         { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1738         { 0x3, 0x0000ffff, 0, 0x24e, SISLANDS_CACCONFIG_CGIND },
1739         { 0x3, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1740         { 0x4, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1741         { 0x4, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1742         { 0x5, 0x0000ffff, 0, 0x35e, SISLANDS_CACCONFIG_CGIND },
1743         { 0x5, 0xffff0000, 16, 0x1143, SISLANDS_CACCONFIG_CGIND },
1744         { 0x6, 0x0000ffff, 0, 0xe17, SISLANDS_CACCONFIG_CGIND },
1745         { 0x6, 0xffff0000, 16, 0x441, SISLANDS_CACCONFIG_CGIND },
1746         { 0x18f, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1747         { 0x7, 0x0000ffff, 0, 0x28b, SISLANDS_CACCONFIG_CGIND },
1748         { 0x7, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1749         { 0x8, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1750         { 0x8, 0xffff0000, 16, 0xabe, SISLANDS_CACCONFIG_CGIND },
1751         { 0x9, 0x0000ffff, 0, 0xf11, SISLANDS_CACCONFIG_CGIND },
1752         { 0xa, 0x0000ffff, 0, 0x907, SISLANDS_CACCONFIG_CGIND },
1753         { 0xb, 0x0000ffff, 0, 0xb45, SISLANDS_CACCONFIG_CGIND },
1754         { 0xb, 0xffff0000, 16, 0xd1e, SISLANDS_CACCONFIG_CGIND },
1755         { 0xc, 0x0000ffff, 0, 0xa2c, SISLANDS_CACCONFIG_CGIND },
1756         { 0xd, 0x0000ffff, 0, 0x62, SISLANDS_CACCONFIG_CGIND },
1757         { 0xd, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1758         { 0xe, 0x0000ffff, 0, 0x1f3, SISLANDS_CACCONFIG_CGIND },
1759         { 0xf, 0x0000ffff, 0, 0x42, SISLANDS_CACCONFIG_CGIND },
1760         { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1761         { 0x10, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1762         { 0x10, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1763         { 0x11, 0x0000ffff, 0, 0x709, SISLANDS_CACCONFIG_CGIND },
1764         { 0x11, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1765         { 0x12, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1766         { 0x13, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1767         { 0x13, 0xffff0000, 16, 0x3a, SISLANDS_CACCONFIG_CGIND },
1768         { 0x14, 0x0000ffff, 0, 0x357, SISLANDS_CACCONFIG_CGIND },
1769         { 0x15, 0x0000ffff, 0, 0x9f, SISLANDS_CACCONFIG_CGIND },
1770         { 0x15, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1771         { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1772         { 0x16, 0x0000ffff, 0, 0x314, SISLANDS_CACCONFIG_CGIND },
1773         { 0x16, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1774         { 0x17, 0x0000ffff, 0, 0x6d, SISLANDS_CACCONFIG_CGIND },
1775         { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1776         { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1777         { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1778         { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1779         { 0x1a, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1780         { 0x1a, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1781         { 0x1b, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1782         { 0x1b, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1783         { 0x1c, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1784         { 0x1c, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1785         { 0x1d, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1786         { 0x1d, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1787         { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1788         { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1789         { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1790         { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1791         { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1792         { 0x6d, 0x0000ffff, 0, 0x1b9, SISLANDS_CACCONFIG_CGIND },
1793         { 0xFFFFFFFF }
1794 };
1795
1796 static const struct si_powertune_data powertune_data_hainan =
1797 {
1798         ((1 << 16) | 0x6993),
1799         5,
1800         0,
1801         9,
1802         105,
1803         {
1804                 0UL,
1805                 0UL,
1806                 7194395UL,
1807                 309631529UL,
1808                 -1270850L,
1809                 4513710L,
1810                 100
1811         },
1812         117830498UL,
1813         12,
1814         {
1815                 0,
1816                 0,
1817                 0,
1818                 0,
1819                 0,
1820                 0,
1821                 0,
1822                 0
1823         },
1824         true
1825 };
1826
1827 static struct rv7xx_power_info *rv770_get_pi(struct amdgpu_device *adev);
1828 static struct evergreen_power_info *evergreen_get_pi(struct amdgpu_device *adev);
1829 static struct ni_power_info *ni_get_pi(struct amdgpu_device *adev);
1830 static struct  si_ps *si_get_ps(struct amdgpu_ps *rps);
1831
1832 static int si_populate_voltage_value(struct amdgpu_device *adev,
1833                                      const struct atom_voltage_table *table,
1834                                      u16 value, SISLANDS_SMC_VOLTAGE_VALUE *voltage);
1835 static int si_get_std_voltage_value(struct amdgpu_device *adev,
1836                                     SISLANDS_SMC_VOLTAGE_VALUE *voltage,
1837                                     u16 *std_voltage);
1838 static int si_write_smc_soft_register(struct amdgpu_device *adev,
1839                                       u16 reg_offset, u32 value);
1840 static int si_convert_power_level_to_smc(struct amdgpu_device *adev,
1841                                          struct rv7xx_pl *pl,
1842                                          SISLANDS_SMC_HW_PERFORMANCE_LEVEL *level);
1843 static int si_calculate_sclk_params(struct amdgpu_device *adev,
1844                                     u32 engine_clock,
1845                                     SISLANDS_SMC_SCLK_VALUE *sclk);
1846
1847 static void si_thermal_start_smc_fan_control(struct amdgpu_device *adev);
1848 static void si_fan_ctrl_set_default_mode(struct amdgpu_device *adev);
1849 static void si_dpm_set_dpm_funcs(struct amdgpu_device *adev);
1850 static void si_dpm_set_irq_funcs(struct amdgpu_device *adev);
1851
1852 static struct si_power_info *si_get_pi(struct amdgpu_device *adev)
1853 {
1854         struct si_power_info *pi = adev->pm.dpm.priv;
1855         return pi;
1856 }
1857
1858 static void si_calculate_leakage_for_v_and_t_formula(const struct ni_leakage_coeffients *coeff,
1859                                                      u16 v, s32 t, u32 ileakage, u32 *leakage)
1860 {
1861         s64 kt, kv, leakage_w, i_leakage, vddc;
1862         s64 temperature, t_slope, t_intercept, av, bv, t_ref;
1863         s64 tmp;
1864
1865         i_leakage = div64_s64(drm_int2fixp(ileakage), 100);
1866         vddc = div64_s64(drm_int2fixp(v), 1000);
1867         temperature = div64_s64(drm_int2fixp(t), 1000);
1868
1869         t_slope = div64_s64(drm_int2fixp(coeff->t_slope), 100000000);
1870         t_intercept = div64_s64(drm_int2fixp(coeff->t_intercept), 100000000);
1871         av = div64_s64(drm_int2fixp(coeff->av), 100000000);
1872         bv = div64_s64(drm_int2fixp(coeff->bv), 100000000);
1873         t_ref = drm_int2fixp(coeff->t_ref);
1874
1875         tmp = drm_fixp_mul(t_slope, vddc) + t_intercept;
1876         kt = drm_fixp_exp(drm_fixp_mul(tmp, temperature));
1877         kt = drm_fixp_div(kt, drm_fixp_exp(drm_fixp_mul(tmp, t_ref)));
1878         kv = drm_fixp_mul(av, drm_fixp_exp(drm_fixp_mul(bv, vddc)));
1879
1880         leakage_w = drm_fixp_mul(drm_fixp_mul(drm_fixp_mul(i_leakage, kt), kv), vddc);
1881
1882         *leakage = drm_fixp2int(leakage_w * 1000);
1883 }
1884
1885 static void si_calculate_leakage_for_v_and_t(struct amdgpu_device *adev,
1886                                              const struct ni_leakage_coeffients *coeff,
1887                                              u16 v,
1888                                              s32 t,
1889                                              u32 i_leakage,
1890                                              u32 *leakage)
1891 {
1892         si_calculate_leakage_for_v_and_t_formula(coeff, v, t, i_leakage, leakage);
1893 }
1894
1895 static void si_calculate_leakage_for_v_formula(const struct ni_leakage_coeffients *coeff,
1896                                                const u32 fixed_kt, u16 v,
1897                                                u32 ileakage, u32 *leakage)
1898 {
1899         s64 kt, kv, leakage_w, i_leakage, vddc;
1900
1901         i_leakage = div64_s64(drm_int2fixp(ileakage), 100);
1902         vddc = div64_s64(drm_int2fixp(v), 1000);
1903
1904         kt = div64_s64(drm_int2fixp(fixed_kt), 100000000);
1905         kv = drm_fixp_mul(div64_s64(drm_int2fixp(coeff->av), 100000000),
1906                           drm_fixp_exp(drm_fixp_mul(div64_s64(drm_int2fixp(coeff->bv), 100000000), vddc)));
1907
1908         leakage_w = drm_fixp_mul(drm_fixp_mul(drm_fixp_mul(i_leakage, kt), kv), vddc);
1909
1910         *leakage = drm_fixp2int(leakage_w * 1000);
1911 }
1912
1913 static void si_calculate_leakage_for_v(struct amdgpu_device *adev,
1914                                        const struct ni_leakage_coeffients *coeff,
1915                                        const u32 fixed_kt,
1916                                        u16 v,
1917                                        u32 i_leakage,
1918                                        u32 *leakage)
1919 {
1920         si_calculate_leakage_for_v_formula(coeff, fixed_kt, v, i_leakage, leakage);
1921 }
1922
1923
1924 static void si_update_dte_from_pl2(struct amdgpu_device *adev,
1925                                    struct si_dte_data *dte_data)
1926 {
1927         u32 p_limit1 = adev->pm.dpm.tdp_limit;
1928         u32 p_limit2 = adev->pm.dpm.near_tdp_limit;
1929         u32 k = dte_data->k;
1930         u32 t_max = dte_data->max_t;
1931         u32 t_split[5] = { 10, 15, 20, 25, 30 };
1932         u32 t_0 = dte_data->t0;
1933         u32 i;
1934
1935         if (p_limit2 != 0 && p_limit2 <= p_limit1) {
1936                 dte_data->tdep_count = 3;
1937
1938                 for (i = 0; i < k; i++) {
1939                         dte_data->r[i] =
1940                                 (t_split[i] * (t_max - t_0/(u32)1000) * (1 << 14)) /
1941                                 (p_limit2  * (u32)100);
1942                 }
1943
1944                 dte_data->tdep_r[1] = dte_data->r[4] * 2;
1945
1946                 for (i = 2; i < SMC_SISLANDS_DTE_MAX_TEMPERATURE_DEPENDENT_ARRAY_SIZE; i++) {
1947                         dte_data->tdep_r[i] = dte_data->r[4];
1948                 }
1949         } else {
1950                 DRM_ERROR("Invalid PL2! DTE will not be updated.\n");
1951         }
1952 }
1953
1954 static struct rv7xx_power_info *rv770_get_pi(struct amdgpu_device *adev)
1955 {
1956         struct rv7xx_power_info *pi = adev->pm.dpm.priv;
1957
1958         return pi;
1959 }
1960
1961 static struct ni_power_info *ni_get_pi(struct amdgpu_device *adev)
1962 {
1963         struct ni_power_info *pi = adev->pm.dpm.priv;
1964
1965         return pi;
1966 }
1967
1968 static struct si_ps *si_get_ps(struct amdgpu_ps *aps)
1969 {
1970         struct  si_ps *ps = aps->ps_priv;
1971
1972         return ps;
1973 }
1974
1975 static void si_initialize_powertune_defaults(struct amdgpu_device *adev)
1976 {
1977         struct ni_power_info *ni_pi = ni_get_pi(adev);
1978         struct si_power_info *si_pi = si_get_pi(adev);
1979         bool update_dte_from_pl2 = false;
1980
1981         if (adev->asic_type == CHIP_TAHITI) {
1982                 si_pi->cac_weights = cac_weights_tahiti;
1983                 si_pi->lcac_config = lcac_tahiti;
1984                 si_pi->cac_override = cac_override_tahiti;
1985                 si_pi->powertune_data = &powertune_data_tahiti;
1986                 si_pi->dte_data = dte_data_tahiti;
1987
1988                 switch (adev->pdev->device) {
1989                 case 0x6798:
1990                         si_pi->dte_data.enable_dte_by_default = true;
1991                         break;
1992                 case 0x6799:
1993                         si_pi->dte_data = dte_data_new_zealand;
1994                         break;
1995                 case 0x6790:
1996                 case 0x6791:
1997                 case 0x6792:
1998                 case 0x679E:
1999                         si_pi->dte_data = dte_data_aruba_pro;
2000                         update_dte_from_pl2 = true;
2001                         break;
2002                 case 0x679B:
2003                         si_pi->dte_data = dte_data_malta;
2004                         update_dte_from_pl2 = true;
2005                         break;
2006                 case 0x679A:
2007                         si_pi->dte_data = dte_data_tahiti_pro;
2008                         update_dte_from_pl2 = true;
2009                         break;
2010                 default:
2011                         if (si_pi->dte_data.enable_dte_by_default == true)
2012                                 DRM_ERROR("DTE is not enabled!\n");
2013                         break;
2014                 }
2015         } else if (adev->asic_type == CHIP_PITCAIRN) {
2016                 si_pi->cac_weights = cac_weights_pitcairn;
2017                 si_pi->lcac_config = lcac_pitcairn;
2018                 si_pi->cac_override = cac_override_pitcairn;
2019                 si_pi->powertune_data = &powertune_data_pitcairn;
2020
2021                 switch (adev->pdev->device) {
2022                 case 0x6810:
2023                 case 0x6818:
2024                         si_pi->dte_data = dte_data_curacao_xt;
2025                         update_dte_from_pl2 = true;
2026                         break;
2027                 case 0x6819:
2028                 case 0x6811:
2029                         si_pi->dte_data = dte_data_curacao_pro;
2030                         update_dte_from_pl2 = true;
2031                         break;
2032                 case 0x6800:
2033                 case 0x6806:
2034                         si_pi->dte_data = dte_data_neptune_xt;
2035                         update_dte_from_pl2 = true;
2036                         break;
2037                 default:
2038                         si_pi->dte_data = dte_data_pitcairn;
2039                         break;
2040                 }
2041         } else if (adev->asic_type == CHIP_VERDE) {
2042                 si_pi->lcac_config = lcac_cape_verde;
2043                 si_pi->cac_override = cac_override_cape_verde;
2044                 si_pi->powertune_data = &powertune_data_cape_verde;
2045
2046                 switch (adev->pdev->device) {
2047                 case 0x683B:
2048                 case 0x683F:
2049                 case 0x6829:
2050                 case 0x6835:
2051                         si_pi->cac_weights = cac_weights_cape_verde_pro;
2052                         si_pi->dte_data = dte_data_cape_verde;
2053                         break;
2054                 case 0x682C:
2055                         si_pi->cac_weights = cac_weights_cape_verde_pro;
2056                         si_pi->dte_data = dte_data_sun_xt;
2057                         break;
2058                 case 0x6825:
2059                 case 0x6827:
2060                         si_pi->cac_weights = cac_weights_heathrow;
2061                         si_pi->dte_data = dte_data_cape_verde;
2062                         break;
2063                 case 0x6824:
2064                 case 0x682D:
2065                         si_pi->cac_weights = cac_weights_chelsea_xt;
2066                         si_pi->dte_data = dte_data_cape_verde;
2067                         break;
2068                 case 0x682F:
2069                         si_pi->cac_weights = cac_weights_chelsea_pro;
2070                         si_pi->dte_data = dte_data_cape_verde;
2071                         break;
2072                 case 0x6820:
2073                         si_pi->cac_weights = cac_weights_heathrow;
2074                         si_pi->dte_data = dte_data_venus_xtx;
2075                         break;
2076                 case 0x6821:
2077                         si_pi->cac_weights = cac_weights_heathrow;
2078                         si_pi->dte_data = dte_data_venus_xt;
2079                         break;
2080                 case 0x6823:
2081                 case 0x682B:
2082                 case 0x6822:
2083                 case 0x682A:
2084                         si_pi->cac_weights = cac_weights_chelsea_pro;
2085                         si_pi->dte_data = dte_data_venus_pro;
2086                         break;
2087                 default:
2088                         si_pi->cac_weights = cac_weights_cape_verde;
2089                         si_pi->dte_data = dte_data_cape_verde;
2090                         break;
2091                 }
2092         } else if (adev->asic_type == CHIP_OLAND) {
2093                 si_pi->lcac_config = lcac_mars_pro;
2094                 si_pi->cac_override = cac_override_oland;
2095                 si_pi->powertune_data = &powertune_data_mars_pro;
2096                 si_pi->dte_data = dte_data_mars_pro;
2097
2098                 switch (adev->pdev->device) {
2099                 case 0x6601:
2100                 case 0x6621:
2101                 case 0x6603:
2102                 case 0x6605:
2103                         si_pi->cac_weights = cac_weights_mars_pro;
2104                         update_dte_from_pl2 = true;
2105                         break;
2106                 case 0x6600:
2107                 case 0x6606:
2108                 case 0x6620:
2109                 case 0x6604:
2110                         si_pi->cac_weights = cac_weights_mars_xt;
2111                         update_dte_from_pl2 = true;
2112                         break;
2113                 case 0x6611:
2114                 case 0x6613:
2115                 case 0x6608:
2116                         si_pi->cac_weights = cac_weights_oland_pro;
2117                         update_dte_from_pl2 = true;
2118                         break;
2119                 case 0x6610:
2120                         si_pi->cac_weights = cac_weights_oland_xt;
2121                         update_dte_from_pl2 = true;
2122                         break;
2123                 default:
2124                         si_pi->cac_weights = cac_weights_oland;
2125                         si_pi->lcac_config = lcac_oland;
2126                         si_pi->cac_override = cac_override_oland;
2127                         si_pi->powertune_data = &powertune_data_oland;
2128                         si_pi->dte_data = dte_data_oland;
2129                         break;
2130                 }
2131         } else if (adev->asic_type == CHIP_HAINAN) {
2132                 si_pi->cac_weights = cac_weights_hainan;
2133                 si_pi->lcac_config = lcac_oland;
2134                 si_pi->cac_override = cac_override_oland;
2135                 si_pi->powertune_data = &powertune_data_hainan;
2136                 si_pi->dte_data = dte_data_sun_xt;
2137                 update_dte_from_pl2 = true;
2138         } else {
2139                 DRM_ERROR("Unknown SI asic revision, failed to initialize PowerTune!\n");
2140                 return;
2141         }
2142
2143         ni_pi->enable_power_containment = false;
2144         ni_pi->enable_cac = false;
2145         ni_pi->enable_sq_ramping = false;
2146         si_pi->enable_dte = false;
2147
2148         if (si_pi->powertune_data->enable_powertune_by_default) {
2149                 ni_pi->enable_power_containment = true;
2150                 ni_pi->enable_cac = true;
2151                 if (si_pi->dte_data.enable_dte_by_default) {
2152                         si_pi->enable_dte = true;
2153                         if (update_dte_from_pl2)
2154                                 si_update_dte_from_pl2(adev, &si_pi->dte_data);
2155
2156                 }
2157                 ni_pi->enable_sq_ramping = true;
2158         }
2159
2160         ni_pi->driver_calculate_cac_leakage = true;
2161         ni_pi->cac_configuration_required = true;
2162
2163         if (ni_pi->cac_configuration_required) {
2164                 ni_pi->support_cac_long_term_average = true;
2165                 si_pi->dyn_powertune_data.l2_lta_window_size =
2166                         si_pi->powertune_data->l2_lta_window_size_default;
2167                 si_pi->dyn_powertune_data.lts_truncate =
2168                         si_pi->powertune_data->lts_truncate_default;
2169         } else {
2170                 ni_pi->support_cac_long_term_average = false;
2171                 si_pi->dyn_powertune_data.l2_lta_window_size = 0;
2172                 si_pi->dyn_powertune_data.lts_truncate = 0;
2173         }
2174
2175         si_pi->dyn_powertune_data.disable_uvd_powertune = false;
2176 }
2177
2178 static u32 si_get_smc_power_scaling_factor(struct amdgpu_device *adev)
2179 {
2180         return 1;
2181 }
2182
2183 static u32 si_calculate_cac_wintime(struct amdgpu_device *adev)
2184 {
2185         u32 xclk;
2186         u32 wintime;
2187         u32 cac_window;
2188         u32 cac_window_size;
2189
2190         xclk = amdgpu_asic_get_xclk(adev);
2191
2192         if (xclk == 0)
2193                 return 0;
2194
2195         cac_window = RREG32(CG_CAC_CTRL) & CAC_WINDOW_MASK;
2196         cac_window_size = ((cac_window & 0xFFFF0000) >> 16) * (cac_window & 0x0000FFFF);
2197
2198         wintime = (cac_window_size * 100) / xclk;
2199
2200         return wintime;
2201 }
2202
2203 static u32 si_scale_power_for_smc(u32 power_in_watts, u32 scaling_factor)
2204 {
2205         return power_in_watts;
2206 }
2207
2208 static int si_calculate_adjusted_tdp_limits(struct amdgpu_device *adev,
2209                                             bool adjust_polarity,
2210                                             u32 tdp_adjustment,
2211                                             u32 *tdp_limit,
2212                                             u32 *near_tdp_limit)
2213 {
2214         u32 adjustment_delta, max_tdp_limit;
2215
2216         if (tdp_adjustment > (u32)adev->pm.dpm.tdp_od_limit)
2217                 return -EINVAL;
2218
2219         max_tdp_limit = ((100 + 100) * adev->pm.dpm.tdp_limit) / 100;
2220
2221         if (adjust_polarity) {
2222                 *tdp_limit = ((100 + tdp_adjustment) * adev->pm.dpm.tdp_limit) / 100;
2223                 *near_tdp_limit = adev->pm.dpm.near_tdp_limit_adjusted + (*tdp_limit - adev->pm.dpm.tdp_limit);
2224         } else {
2225                 *tdp_limit = ((100 - tdp_adjustment) * adev->pm.dpm.tdp_limit) / 100;
2226                 adjustment_delta  = adev->pm.dpm.tdp_limit - *tdp_limit;
2227                 if (adjustment_delta < adev->pm.dpm.near_tdp_limit_adjusted)
2228                         *near_tdp_limit = adev->pm.dpm.near_tdp_limit_adjusted - adjustment_delta;
2229                 else
2230                         *near_tdp_limit = 0;
2231         }
2232
2233         if ((*tdp_limit <= 0) || (*tdp_limit > max_tdp_limit))
2234                 return -EINVAL;
2235         if ((*near_tdp_limit <= 0) || (*near_tdp_limit > *tdp_limit))
2236                 return -EINVAL;
2237
2238         return 0;
2239 }
2240
2241 static int si_populate_smc_tdp_limits(struct amdgpu_device *adev,
2242                                       struct amdgpu_ps *amdgpu_state)
2243 {
2244         struct ni_power_info *ni_pi = ni_get_pi(adev);
2245         struct si_power_info *si_pi = si_get_pi(adev);
2246
2247         if (ni_pi->enable_power_containment) {
2248                 SISLANDS_SMC_STATETABLE *smc_table = &si_pi->smc_statetable;
2249                 PP_SIslands_PAPMParameters *papm_parm;
2250                 struct amdgpu_ppm_table *ppm = adev->pm.dpm.dyn_state.ppm_table;
2251                 u32 scaling_factor = si_get_smc_power_scaling_factor(adev);
2252                 u32 tdp_limit;
2253                 u32 near_tdp_limit;
2254                 int ret;
2255
2256                 if (scaling_factor == 0)
2257                         return -EINVAL;
2258
2259                 memset(smc_table, 0, sizeof(SISLANDS_SMC_STATETABLE));
2260
2261                 ret = si_calculate_adjusted_tdp_limits(adev,
2262                                                        false, /* ??? */
2263                                                        adev->pm.dpm.tdp_adjustment,
2264                                                        &tdp_limit,
2265                                                        &near_tdp_limit);
2266                 if (ret)
2267                         return ret;
2268
2269                 smc_table->dpm2Params.TDPLimit =
2270                         cpu_to_be32(si_scale_power_for_smc(tdp_limit, scaling_factor) * 1000);
2271                 smc_table->dpm2Params.NearTDPLimit =
2272                         cpu_to_be32(si_scale_power_for_smc(near_tdp_limit, scaling_factor) * 1000);
2273                 smc_table->dpm2Params.SafePowerLimit =
2274                         cpu_to_be32(si_scale_power_for_smc((near_tdp_limit * SISLANDS_DPM2_TDP_SAFE_LIMIT_PERCENT) / 100, scaling_factor) * 1000);
2275
2276                 ret = amdgpu_si_copy_bytes_to_smc(adev,
2277                                                   (si_pi->state_table_start + offsetof(SISLANDS_SMC_STATETABLE, dpm2Params) +
2278                                                    offsetof(PP_SIslands_DPM2Parameters, TDPLimit)),
2279                                                   (u8 *)(&(smc_table->dpm2Params.TDPLimit)),
2280                                                   sizeof(u32) * 3,
2281                                                   si_pi->sram_end);
2282                 if (ret)
2283                         return ret;
2284
2285                 if (si_pi->enable_ppm) {
2286                         papm_parm = &si_pi->papm_parm;
2287                         memset(papm_parm, 0, sizeof(PP_SIslands_PAPMParameters));
2288                         papm_parm->NearTDPLimitTherm = cpu_to_be32(ppm->dgpu_tdp);
2289                         papm_parm->dGPU_T_Limit = cpu_to_be32(ppm->tj_max);
2290                         papm_parm->dGPU_T_Warning = cpu_to_be32(95);
2291                         papm_parm->dGPU_T_Hysteresis = cpu_to_be32(5);
2292                         papm_parm->PlatformPowerLimit = 0xffffffff;
2293                         papm_parm->NearTDPLimitPAPM = 0xffffffff;
2294
2295                         ret = amdgpu_si_copy_bytes_to_smc(adev, si_pi->papm_cfg_table_start,
2296                                                           (u8 *)papm_parm,
2297                                                           sizeof(PP_SIslands_PAPMParameters),
2298                                                           si_pi->sram_end);
2299                         if (ret)
2300                                 return ret;
2301                 }
2302         }
2303         return 0;
2304 }
2305
2306 static int si_populate_smc_tdp_limits_2(struct amdgpu_device *adev,
2307                                         struct amdgpu_ps *amdgpu_state)
2308 {
2309         struct ni_power_info *ni_pi = ni_get_pi(adev);
2310         struct si_power_info *si_pi = si_get_pi(adev);
2311
2312         if (ni_pi->enable_power_containment) {
2313                 SISLANDS_SMC_STATETABLE *smc_table = &si_pi->smc_statetable;
2314                 u32 scaling_factor = si_get_smc_power_scaling_factor(adev);
2315                 int ret;
2316
2317                 memset(smc_table, 0, sizeof(SISLANDS_SMC_STATETABLE));
2318
2319                 smc_table->dpm2Params.NearTDPLimit =
2320                         cpu_to_be32(si_scale_power_for_smc(adev->pm.dpm.near_tdp_limit_adjusted, scaling_factor) * 1000);
2321                 smc_table->dpm2Params.SafePowerLimit =
2322                         cpu_to_be32(si_scale_power_for_smc((adev->pm.dpm.near_tdp_limit_adjusted * SISLANDS_DPM2_TDP_SAFE_LIMIT_PERCENT) / 100, scaling_factor) * 1000);
2323
2324                 ret = amdgpu_si_copy_bytes_to_smc(adev,
2325                                                   (si_pi->state_table_start +
2326                                                    offsetof(SISLANDS_SMC_STATETABLE, dpm2Params) +
2327                                                    offsetof(PP_SIslands_DPM2Parameters, NearTDPLimit)),
2328                                                   (u8 *)(&(smc_table->dpm2Params.NearTDPLimit)),
2329                                                   sizeof(u32) * 2,
2330                                                   si_pi->sram_end);
2331                 if (ret)
2332                         return ret;
2333         }
2334
2335         return 0;
2336 }
2337
2338 static u16 si_calculate_power_efficiency_ratio(struct amdgpu_device *adev,
2339                                                const u16 prev_std_vddc,
2340                                                const u16 curr_std_vddc)
2341 {
2342         u64 margin = (u64)SISLANDS_DPM2_PWREFFICIENCYRATIO_MARGIN;
2343         u64 prev_vddc = (u64)prev_std_vddc;
2344         u64 curr_vddc = (u64)curr_std_vddc;
2345         u64 pwr_efficiency_ratio, n, d;
2346
2347         if ((prev_vddc == 0) || (curr_vddc == 0))
2348                 return 0;
2349
2350         n = div64_u64((u64)1024 * curr_vddc * curr_vddc * ((u64)1000 + margin), (u64)1000);
2351         d = prev_vddc * prev_vddc;
2352         pwr_efficiency_ratio = div64_u64(n, d);
2353
2354         if (pwr_efficiency_ratio > (u64)0xFFFF)
2355                 return 0;
2356
2357         return (u16)pwr_efficiency_ratio;
2358 }
2359
2360 static bool si_should_disable_uvd_powertune(struct amdgpu_device *adev,
2361                                             struct amdgpu_ps *amdgpu_state)
2362 {
2363         struct si_power_info *si_pi = si_get_pi(adev);
2364
2365         if (si_pi->dyn_powertune_data.disable_uvd_powertune &&
2366             amdgpu_state->vclk && amdgpu_state->dclk)
2367                 return true;
2368
2369         return false;
2370 }
2371
2372 struct evergreen_power_info *evergreen_get_pi(struct amdgpu_device *adev)
2373 {
2374         struct evergreen_power_info *pi = adev->pm.dpm.priv;
2375
2376         return pi;
2377 }
2378
2379 static int si_populate_power_containment_values(struct amdgpu_device *adev,
2380                                                 struct amdgpu_ps *amdgpu_state,
2381                                                 SISLANDS_SMC_SWSTATE *smc_state)
2382 {
2383         struct evergreen_power_info *eg_pi = evergreen_get_pi(adev);
2384         struct ni_power_info *ni_pi = ni_get_pi(adev);
2385         struct  si_ps *state = si_get_ps(amdgpu_state);
2386         SISLANDS_SMC_VOLTAGE_VALUE vddc;
2387         u32 prev_sclk;
2388         u32 max_sclk;
2389         u32 min_sclk;
2390         u16 prev_std_vddc;
2391         u16 curr_std_vddc;
2392         int i;
2393         u16 pwr_efficiency_ratio;
2394         u8 max_ps_percent;
2395         bool disable_uvd_power_tune;
2396         int ret;
2397
2398         if (ni_pi->enable_power_containment == false)
2399                 return 0;
2400
2401         if (state->performance_level_count == 0)
2402                 return -EINVAL;
2403
2404         if (smc_state->levelCount != state->performance_level_count)
2405                 return -EINVAL;
2406
2407         disable_uvd_power_tune = si_should_disable_uvd_powertune(adev, amdgpu_state);
2408
2409         smc_state->levels[0].dpm2.MaxPS = 0;
2410         smc_state->levels[0].dpm2.NearTDPDec = 0;
2411         smc_state->levels[0].dpm2.AboveSafeInc = 0;
2412         smc_state->levels[0].dpm2.BelowSafeInc = 0;
2413         smc_state->levels[0].dpm2.PwrEfficiencyRatio = 0;
2414
2415         for (i = 1; i < state->performance_level_count; i++) {
2416                 prev_sclk = state->performance_levels[i-1].sclk;
2417                 max_sclk  = state->performance_levels[i].sclk;
2418                 if (i == 1)
2419                         max_ps_percent = SISLANDS_DPM2_MAXPS_PERCENT_M;
2420                 else
2421                         max_ps_percent = SISLANDS_DPM2_MAXPS_PERCENT_H;
2422
2423                 if (prev_sclk > max_sclk)
2424                         return -EINVAL;
2425
2426                 if ((max_ps_percent == 0) ||
2427                     (prev_sclk == max_sclk) ||
2428                     disable_uvd_power_tune)
2429                         min_sclk = max_sclk;
2430                 else if (i == 1)
2431                         min_sclk = prev_sclk;
2432                 else
2433                         min_sclk = (prev_sclk * (u32)max_ps_percent) / 100;
2434
2435                 if (min_sclk < state->performance_levels[0].sclk)
2436                         min_sclk = state->performance_levels[0].sclk;
2437
2438                 if (min_sclk == 0)
2439                         return -EINVAL;
2440
2441                 ret = si_populate_voltage_value(adev, &eg_pi->vddc_voltage_table,
2442                                                 state->performance_levels[i-1].vddc, &vddc);
2443                 if (ret)
2444                         return ret;
2445
2446                 ret = si_get_std_voltage_value(adev, &vddc, &prev_std_vddc);
2447                 if (ret)
2448                         return ret;
2449
2450                 ret = si_populate_voltage_value(adev, &eg_pi->vddc_voltage_table,
2451                                                 state->performance_levels[i].vddc, &vddc);
2452                 if (ret)
2453                         return ret;
2454
2455                 ret = si_get_std_voltage_value(adev, &vddc, &curr_std_vddc);
2456                 if (ret)
2457                         return ret;
2458
2459                 pwr_efficiency_ratio = si_calculate_power_efficiency_ratio(adev,
2460                                                                            prev_std_vddc, curr_std_vddc);
2461
2462                 smc_state->levels[i].dpm2.MaxPS = (u8)((SISLANDS_DPM2_MAX_PULSE_SKIP * (max_sclk - min_sclk)) / max_sclk);
2463                 smc_state->levels[i].dpm2.NearTDPDec = SISLANDS_DPM2_NEAR_TDP_DEC;
2464                 smc_state->levels[i].dpm2.AboveSafeInc = SISLANDS_DPM2_ABOVE_SAFE_INC;
2465                 smc_state->levels[i].dpm2.BelowSafeInc = SISLANDS_DPM2_BELOW_SAFE_INC;
2466                 smc_state->levels[i].dpm2.PwrEfficiencyRatio = cpu_to_be16(pwr_efficiency_ratio);
2467         }
2468
2469         return 0;
2470 }
2471
2472 static int si_populate_sq_ramping_values(struct amdgpu_device *adev,
2473                                          struct amdgpu_ps *amdgpu_state,
2474                                          SISLANDS_SMC_SWSTATE *smc_state)
2475 {
2476         struct ni_power_info *ni_pi = ni_get_pi(adev);
2477         struct  si_ps *state = si_get_ps(amdgpu_state);
2478         u32 sq_power_throttle, sq_power_throttle2;
2479         bool enable_sq_ramping = ni_pi->enable_sq_ramping;
2480         int i;
2481
2482         if (state->performance_level_count == 0)
2483                 return -EINVAL;
2484
2485         if (smc_state->levelCount != state->performance_level_count)
2486                 return -EINVAL;
2487
2488         if (adev->pm.dpm.sq_ramping_threshold == 0)
2489                 return -EINVAL;
2490
2491         if (SISLANDS_DPM2_SQ_RAMP_MAX_POWER > (MAX_POWER_MASK >> MAX_POWER_SHIFT))
2492                 enable_sq_ramping = false;
2493
2494         if (SISLANDS_DPM2_SQ_RAMP_MIN_POWER > (MIN_POWER_MASK >> MIN_POWER_SHIFT))
2495                 enable_sq_ramping = false;
2496
2497         if (SISLANDS_DPM2_SQ_RAMP_MAX_POWER_DELTA > (MAX_POWER_DELTA_MASK >> MAX_POWER_DELTA_SHIFT))
2498                 enable_sq_ramping = false;
2499
2500         if (SISLANDS_DPM2_SQ_RAMP_STI_SIZE > (STI_SIZE_MASK >> STI_SIZE_SHIFT))
2501                 enable_sq_ramping = false;
2502
2503         if (SISLANDS_DPM2_SQ_RAMP_LTI_RATIO > (LTI_RATIO_MASK >> LTI_RATIO_SHIFT))
2504                 enable_sq_ramping = false;
2505
2506         for (i = 0; i < state->performance_level_count; i++) {
2507                 sq_power_throttle = 0;
2508                 sq_power_throttle2 = 0;
2509
2510                 if ((state->performance_levels[i].sclk >= adev->pm.dpm.sq_ramping_threshold) &&
2511                     enable_sq_ramping) {
2512                         sq_power_throttle |= MAX_POWER(SISLANDS_DPM2_SQ_RAMP_MAX_POWER);
2513                         sq_power_throttle |= MIN_POWER(SISLANDS_DPM2_SQ_RAMP_MIN_POWER);
2514                         sq_power_throttle2 |= MAX_POWER_DELTA(SISLANDS_DPM2_SQ_RAMP_MAX_POWER_DELTA);
2515                         sq_power_throttle2 |= STI_SIZE(SISLANDS_DPM2_SQ_RAMP_STI_SIZE);
2516                         sq_power_throttle2 |= LTI_RATIO(SISLANDS_DPM2_SQ_RAMP_LTI_RATIO);
2517                 } else {
2518                         sq_power_throttle |= MAX_POWER_MASK | MIN_POWER_MASK;
2519                         sq_power_throttle2 |= MAX_POWER_DELTA_MASK | STI_SIZE_MASK | LTI_RATIO_MASK;
2520                 }
2521
2522                 smc_state->levels[i].SQPowerThrottle = cpu_to_be32(sq_power_throttle);
2523                 smc_state->levels[i].SQPowerThrottle_2 = cpu_to_be32(sq_power_throttle2);
2524         }
2525
2526         return 0;
2527 }
2528
2529 static int si_enable_power_containment(struct amdgpu_device *adev,
2530                                        struct amdgpu_ps *amdgpu_new_state,
2531                                        bool enable)
2532 {
2533         struct ni_power_info *ni_pi = ni_get_pi(adev);
2534         PPSMC_Result smc_result;
2535         int ret = 0;
2536
2537         if (ni_pi->enable_power_containment) {
2538                 if (enable) {
2539                         if (!si_should_disable_uvd_powertune(adev, amdgpu_new_state)) {
2540                                 smc_result = amdgpu_si_send_msg_to_smc(adev, PPSMC_TDPClampingActive);
2541                                 if (smc_result != PPSMC_Result_OK) {
2542                                         ret = -EINVAL;
2543                                         ni_pi->pc_enabled = false;
2544                                 } else {
2545                                         ni_pi->pc_enabled = true;
2546                                 }
2547                         }
2548                 } else {
2549                         smc_result = amdgpu_si_send_msg_to_smc(adev, PPSMC_TDPClampingInactive);
2550                         if (smc_result != PPSMC_Result_OK)
2551                                 ret = -EINVAL;
2552                         ni_pi->pc_enabled = false;
2553                 }
2554         }
2555
2556         return ret;
2557 }
2558
2559 static int si_initialize_smc_dte_tables(struct amdgpu_device *adev)
2560 {
2561         struct si_power_info *si_pi = si_get_pi(adev);
2562         int ret = 0;
2563         struct si_dte_data *dte_data = &si_pi->dte_data;
2564         Smc_SIslands_DTE_Configuration *dte_tables = NULL;
2565         u32 table_size;
2566         u8 tdep_count;
2567         u32 i;
2568
2569         if (dte_data == NULL)
2570                 si_pi->enable_dte = false;
2571
2572         if (si_pi->enable_dte == false)
2573                 return 0;
2574
2575         if (dte_data->k <= 0)
2576                 return -EINVAL;
2577
2578         dte_tables = kzalloc(sizeof(Smc_SIslands_DTE_Configuration), GFP_KERNEL);
2579         if (dte_tables == NULL) {
2580                 si_pi->enable_dte = false;
2581                 return -ENOMEM;
2582         }
2583
2584         table_size = dte_data->k;
2585
2586         if (table_size > SMC_SISLANDS_DTE_MAX_FILTER_STAGES)
2587                 table_size = SMC_SISLANDS_DTE_MAX_FILTER_STAGES;
2588
2589         tdep_count = dte_data->tdep_count;
2590         if (tdep_count > SMC_SISLANDS_DTE_MAX_TEMPERATURE_DEPENDENT_ARRAY_SIZE)
2591                 tdep_count = SMC_SISLANDS_DTE_MAX_TEMPERATURE_DEPENDENT_ARRAY_SIZE;
2592
2593         dte_tables->K = cpu_to_be32(table_size);
2594         dte_tables->T0 = cpu_to_be32(dte_data->t0);
2595         dte_tables->MaxT = cpu_to_be32(dte_data->max_t);
2596         dte_tables->WindowSize = dte_data->window_size;
2597         dte_tables->temp_select = dte_data->temp_select;
2598         dte_tables->DTE_mode = dte_data->dte_mode;
2599         dte_tables->Tthreshold = cpu_to_be32(dte_data->t_threshold);
2600
2601         if (tdep_count > 0)
2602                 table_size--;
2603
2604         for (i = 0; i < table_size; i++) {
2605                 dte_tables->tau[i] = cpu_to_be32(dte_data->tau[i]);
2606                 dte_tables->R[i]   = cpu_to_be32(dte_data->r[i]);
2607         }
2608
2609         dte_tables->Tdep_count = tdep_count;
2610
2611         for (i = 0; i < (u32)tdep_count; i++) {
2612                 dte_tables->T_limits[i] = dte_data->t_limits[i];
2613                 dte_tables->Tdep_tau[i] = cpu_to_be32(dte_data->tdep_tau[i]);
2614                 dte_tables->Tdep_R[i] = cpu_to_be32(dte_data->tdep_r[i]);
2615         }
2616
2617         ret = amdgpu_si_copy_bytes_to_smc(adev, si_pi->dte_table_start,
2618                                           (u8 *)dte_tables,
2619                                           sizeof(Smc_SIslands_DTE_Configuration),
2620                                           si_pi->sram_end);
2621         kfree(dte_tables);
2622
2623         return ret;
2624 }
2625
2626 static int si_get_cac_std_voltage_max_min(struct amdgpu_device *adev,
2627                                           u16 *max, u16 *min)
2628 {
2629         struct si_power_info *si_pi = si_get_pi(adev);
2630         struct amdgpu_cac_leakage_table *table =
2631                 &adev->pm.dpm.dyn_state.cac_leakage_table;
2632         u32 i;
2633         u32 v0_loadline;
2634
2635         if (table == NULL)
2636                 return -EINVAL;
2637
2638         *max = 0;
2639         *min = 0xFFFF;
2640
2641         for (i = 0; i < table->count; i++) {
2642                 if (table->entries[i].vddc > *max)
2643                         *max = table->entries[i].vddc;
2644                 if (table->entries[i].vddc < *min)
2645                         *min = table->entries[i].vddc;
2646         }
2647
2648         if (si_pi->powertune_data->lkge_lut_v0_percent > 100)
2649                 return -EINVAL;
2650
2651         v0_loadline = (*min) * (100 - si_pi->powertune_data->lkge_lut_v0_percent) / 100;
2652
2653         if (v0_loadline > 0xFFFFUL)
2654                 return -EINVAL;
2655
2656         *min = (u16)v0_loadline;
2657
2658         if ((*min > *max) || (*max == 0) || (*min == 0))
2659                 return -EINVAL;
2660
2661         return 0;
2662 }
2663
2664 static u16 si_get_cac_std_voltage_step(u16 max, u16 min)
2665 {
2666         return ((max - min) + (SMC_SISLANDS_LKGE_LUT_NUM_OF_VOLT_ENTRIES - 1)) /
2667                 SMC_SISLANDS_LKGE_LUT_NUM_OF_VOLT_ENTRIES;
2668 }
2669
2670 static int si_init_dte_leakage_table(struct amdgpu_device *adev,
2671                                      PP_SIslands_CacConfig *cac_tables,
2672                                      u16 vddc_max, u16 vddc_min, u16 vddc_step,
2673                                      u16 t0, u16 t_step)
2674 {
2675         struct si_power_info *si_pi = si_get_pi(adev);
2676         u32 leakage;
2677         unsigned int i, j;
2678         s32 t;
2679         u32 smc_leakage;
2680         u32 scaling_factor;
2681         u16 voltage;
2682
2683         scaling_factor = si_get_smc_power_scaling_factor(adev);
2684
2685         for (i = 0; i < SMC_SISLANDS_LKGE_LUT_NUM_OF_TEMP_ENTRIES ; i++) {
2686                 t = (1000 * (i * t_step + t0));
2687
2688                 for (j = 0; j < SMC_SISLANDS_LKGE_LUT_NUM_OF_VOLT_ENTRIES; j++) {
2689                         voltage = vddc_max - (vddc_step * j);
2690
2691                         si_calculate_leakage_for_v_and_t(adev,
2692                                                          &si_pi->powertune_data->leakage_coefficients,
2693                                                          voltage,
2694                                                          t,
2695                                                          si_pi->dyn_powertune_data.cac_leakage,
2696                                                          &leakage);
2697
2698                         smc_leakage = si_scale_power_for_smc(leakage, scaling_factor) / 4;
2699
2700                         if (smc_leakage > 0xFFFF)
2701                                 smc_leakage = 0xFFFF;
2702
2703                         cac_tables->cac_lkge_lut[i][SMC_SISLANDS_LKGE_LUT_NUM_OF_VOLT_ENTRIES-1-j] =
2704                                 cpu_to_be16((u16)smc_leakage);
2705                 }
2706         }
2707         return 0;
2708 }
2709
2710 static int si_init_simplified_leakage_table(struct amdgpu_device *adev,
2711                                             PP_SIslands_CacConfig *cac_tables,
2712                                             u16 vddc_max, u16 vddc_min, u16 vddc_step)
2713 {
2714         struct si_power_info *si_pi = si_get_pi(adev);
2715         u32 leakage;
2716         unsigned int i, j;
2717         u32 smc_leakage;
2718         u32 scaling_factor;
2719         u16 voltage;
2720
2721         scaling_factor = si_get_smc_power_scaling_factor(adev);
2722
2723         for (j = 0; j < SMC_SISLANDS_LKGE_LUT_NUM_OF_VOLT_ENTRIES; j++) {
2724                 voltage = vddc_max - (vddc_step * j);
2725
2726                 si_calculate_leakage_for_v(adev,
2727                                            &si_pi->powertune_data->leakage_coefficients,
2728                                            si_pi->powertune_data->fixed_kt,
2729                                            voltage,
2730                                            si_pi->dyn_powertune_data.cac_leakage,
2731                                            &leakage);
2732
2733                 smc_leakage = si_scale_power_for_smc(leakage, scaling_factor) / 4;
2734
2735                 if (smc_leakage > 0xFFFF)
2736                         smc_leakage = 0xFFFF;
2737
2738                 for (i = 0; i < SMC_SISLANDS_LKGE_LUT_NUM_OF_TEMP_ENTRIES ; i++)
2739                         cac_tables->cac_lkge_lut[i][SMC_SISLANDS_LKGE_LUT_NUM_OF_VOLT_ENTRIES-1-j] =
2740                                 cpu_to_be16((u16)smc_leakage);
2741         }
2742         return 0;
2743 }
2744
2745 static int si_initialize_smc_cac_tables(struct amdgpu_device *adev)
2746 {
2747         struct ni_power_info *ni_pi = ni_get_pi(adev);
2748         struct si_power_info *si_pi = si_get_pi(adev);
2749         PP_SIslands_CacConfig *cac_tables = NULL;
2750         u16 vddc_max, vddc_min, vddc_step;
2751         u16 t0, t_step;
2752         u32 load_line_slope, reg;
2753         int ret = 0;
2754         u32 ticks_per_us = amdgpu_asic_get_xclk(adev) / 100;
2755
2756         if (ni_pi->enable_cac == false)
2757                 return 0;
2758
2759         cac_tables = kzalloc(sizeof(PP_SIslands_CacConfig), GFP_KERNEL);
2760         if (!cac_tables)
2761                 return -ENOMEM;
2762
2763         reg = RREG32(CG_CAC_CTRL) & ~CAC_WINDOW_MASK;
2764         reg |= CAC_WINDOW(si_pi->powertune_data->cac_window);
2765         WREG32(CG_CAC_CTRL, reg);
2766
2767         si_pi->dyn_powertune_data.cac_leakage = adev->pm.dpm.cac_leakage;
2768         si_pi->dyn_powertune_data.dc_pwr_value =
2769                 si_pi->powertune_data->dc_cac[NISLANDS_DCCAC_LEVEL_0];
2770         si_pi->dyn_powertune_data.wintime = si_calculate_cac_wintime(adev);
2771         si_pi->dyn_powertune_data.shift_n = si_pi->powertune_data->shift_n_default;
2772
2773         si_pi->dyn_powertune_data.leakage_minimum_temperature = 80 * 1000;
2774
2775         ret = si_get_cac_std_voltage_max_min(adev, &vddc_max, &vddc_min);
2776         if (ret)
2777                 goto done_free;
2778
2779         vddc_step = si_get_cac_std_voltage_step(vddc_max, vddc_min);
2780         vddc_min = vddc_max - (vddc_step * (SMC_SISLANDS_LKGE_LUT_NUM_OF_VOLT_ENTRIES - 1));
2781         t_step = 4;
2782         t0 = 60;
2783
2784         if (si_pi->enable_dte || ni_pi->driver_calculate_cac_leakage)
2785                 ret = si_init_dte_leakage_table(adev, cac_tables,
2786                                                 vddc_max, vddc_min, vddc_step,
2787                                                 t0, t_step);
2788         else
2789                 ret = si_init_simplified_leakage_table(adev, cac_tables,
2790                                                        vddc_max, vddc_min, vddc_step);
2791         if (ret)
2792                 goto done_free;
2793
2794         load_line_slope = ((u32)adev->pm.dpm.load_line_slope << SMC_SISLANDS_SCALE_R) / 100;
2795
2796         cac_tables->l2numWin_TDP = cpu_to_be32(si_pi->dyn_powertune_data.l2_lta_window_size);
2797         cac_tables->lts_truncate_n = si_pi->dyn_powertune_data.lts_truncate;
2798         cac_tables->SHIFT_N = si_pi->dyn_powertune_data.shift_n;
2799         cac_tables->lkge_lut_V0 = cpu_to_be32((u32)vddc_min);
2800         cac_tables->lkge_lut_Vstep = cpu_to_be32((u32)vddc_step);
2801         cac_tables->R_LL = cpu_to_be32(load_line_slope);
2802         cac_tables->WinTime = cpu_to_be32(si_pi->dyn_powertune_data.wintime);
2803         cac_tables->calculation_repeats = cpu_to_be32(2);
2804         cac_tables->dc_cac = cpu_to_be32(0);
2805         cac_tables->log2_PG_LKG_SCALE = 12;
2806         cac_tables->cac_temp = si_pi->powertune_data->operating_temp;
2807         cac_tables->lkge_lut_T0 = cpu_to_be32((u32)t0);
2808         cac_tables->lkge_lut_Tstep = cpu_to_be32((u32)t_step);
2809
2810         ret = amdgpu_si_copy_bytes_to_smc(adev, si_pi->cac_table_start,
2811                                           (u8 *)cac_tables,
2812                                           sizeof(PP_SIslands_CacConfig),
2813                                           si_pi->sram_end);
2814
2815         if (ret)
2816                 goto done_free;
2817
2818         ret = si_write_smc_soft_register(adev, SI_SMC_SOFT_REGISTER_ticks_per_us, ticks_per_us);
2819
2820 done_free:
2821         if (ret) {
2822                 ni_pi->enable_cac = false;
2823                 ni_pi->enable_power_containment = false;
2824         }
2825
2826         kfree(cac_tables);
2827
2828         return ret;
2829 }
2830
2831 static int si_program_cac_config_registers(struct amdgpu_device *adev,
2832                                            const struct si_cac_config_reg *cac_config_regs)
2833 {
2834         const struct si_cac_config_reg *config_regs = cac_config_regs;
2835         u32 data = 0, offset;
2836
2837         if (!config_regs)
2838                 return -EINVAL;
2839
2840         while (config_regs->offset != 0xFFFFFFFF) {
2841                 switch (config_regs->type) {
2842                 case SISLANDS_CACCONFIG_CGIND:
2843                         offset = SMC_CG_IND_START + config_regs->offset;
2844                         if (offset < SMC_CG_IND_END)
2845                                 data = RREG32_SMC(offset);
2846                         break;
2847                 default:
2848                         data = RREG32(config_regs->offset);
2849                         break;
2850                 }
2851
2852                 data &= ~config_regs->mask;
2853                 data |= ((config_regs->value << config_regs->shift) & config_regs->mask);
2854
2855                 switch (config_regs->type) {
2856                 case SISLANDS_CACCONFIG_CGIND:
2857                         offset = SMC_CG_IND_START + config_regs->offset;
2858                         if (offset < SMC_CG_IND_END)
2859                                 WREG32_SMC(offset, data);
2860                         break;
2861                 default:
2862                         WREG32(config_regs->offset, data);
2863                         break;
2864                 }
2865                 config_regs++;
2866         }
2867         return 0;
2868 }
2869
2870 static int si_initialize_hardware_cac_manager(struct amdgpu_device *adev)
2871 {
2872         struct ni_power_info *ni_pi = ni_get_pi(adev);
2873         struct si_power_info *si_pi = si_get_pi(adev);
2874         int ret;
2875
2876         if ((ni_pi->enable_cac == false) ||
2877             (ni_pi->cac_configuration_required == false))
2878                 return 0;
2879
2880         ret = si_program_cac_config_registers(adev, si_pi->lcac_config);
2881         if (ret)
2882                 return ret;
2883         ret = si_program_cac_config_registers(adev, si_pi->cac_override);
2884         if (ret)
2885                 return ret;
2886         ret = si_program_cac_config_registers(adev, si_pi->cac_weights);
2887         if (ret)
2888                 return ret;
2889
2890         return 0;
2891 }
2892
2893 static int si_enable_smc_cac(struct amdgpu_device *adev,
2894                              struct amdgpu_ps *amdgpu_new_state,
2895                              bool enable)
2896 {
2897         struct ni_power_info *ni_pi = ni_get_pi(adev);
2898         struct si_power_info *si_pi = si_get_pi(adev);
2899         PPSMC_Result smc_result;
2900         int ret = 0;
2901
2902         if (ni_pi->enable_cac) {
2903                 if (enable) {
2904                         if (!si_should_disable_uvd_powertune(adev, amdgpu_new_state)) {
2905                                 if (ni_pi->support_cac_long_term_average) {
2906                                         smc_result = amdgpu_si_send_msg_to_smc(adev, PPSMC_CACLongTermAvgEnable);
2907                                         if (smc_result != PPSMC_Result_OK)
2908                                                 ni_pi->support_cac_long_term_average = false;
2909                                 }
2910
2911                                 smc_result = amdgpu_si_send_msg_to_smc(adev, PPSMC_MSG_EnableCac);
2912                                 if (smc_result != PPSMC_Result_OK) {
2913                                         ret = -EINVAL;
2914                                         ni_pi->cac_enabled = false;
2915                                 } else {
2916                                         ni_pi->cac_enabled = true;
2917                                 }
2918
2919                                 if (si_pi->enable_dte) {
2920                                         smc_result = amdgpu_si_send_msg_to_smc(adev, PPSMC_MSG_EnableDTE);
2921                                         if (smc_result != PPSMC_Result_OK)
2922                                                 ret = -EINVAL;
2923                                 }
2924                         }
2925                 } else if (ni_pi->cac_enabled) {
2926                         if (si_pi->enable_dte)
2927                                 smc_result = amdgpu_si_send_msg_to_smc(adev, PPSMC_MSG_DisableDTE);
2928
2929                         smc_result = amdgpu_si_send_msg_to_smc(adev, PPSMC_MSG_DisableCac);
2930
2931                         ni_pi->cac_enabled = false;
2932
2933                         if (ni_pi->support_cac_long_term_average)
2934                                 smc_result = amdgpu_si_send_msg_to_smc(adev, PPSMC_CACLongTermAvgDisable);
2935                 }
2936         }
2937         return ret;
2938 }
2939
2940 static int si_init_smc_spll_table(struct amdgpu_device *adev)
2941 {
2942         struct ni_power_info *ni_pi = ni_get_pi(adev);
2943         struct si_power_info *si_pi = si_get_pi(adev);
2944         SMC_SISLANDS_SPLL_DIV_TABLE *spll_table;
2945         SISLANDS_SMC_SCLK_VALUE sclk_params;
2946         u32 fb_div, p_div;
2947         u32 clk_s, clk_v;
2948         u32 sclk = 0;
2949         int ret = 0;
2950         u32 tmp;
2951         int i;
2952
2953         if (si_pi->spll_table_start == 0)
2954                 return -EINVAL;
2955
2956         spll_table = kzalloc(sizeof(SMC_SISLANDS_SPLL_DIV_TABLE), GFP_KERNEL);
2957         if (spll_table == NULL)
2958                 return -ENOMEM;
2959
2960         for (i = 0; i < 256; i++) {
2961                 ret = si_calculate_sclk_params(adev, sclk, &sclk_params);
2962                 if (ret)
2963                         break;
2964                 p_div = (sclk_params.vCG_SPLL_FUNC_CNTL & SPLL_PDIV_A_MASK) >> SPLL_PDIV_A_SHIFT;
2965                 fb_div = (sclk_params.vCG_SPLL_FUNC_CNTL_3 & SPLL_FB_DIV_MASK) >> SPLL_FB_DIV_SHIFT;
2966                 clk_s = (sclk_params.vCG_SPLL_SPREAD_SPECTRUM & CLK_S_MASK) >> CLK_S_SHIFT;
2967                 clk_v = (sclk_params.vCG_SPLL_SPREAD_SPECTRUM_2 & CLK_V_MASK) >> CLK_V_SHIFT;
2968
2969                 fb_div &= ~0x00001FFF;
2970                 fb_div >>= 1;
2971                 clk_v >>= 6;
2972
2973                 if (p_div & ~(SMC_SISLANDS_SPLL_DIV_TABLE_PDIV_MASK >> SMC_SISLANDS_SPLL_DIV_TABLE_PDIV_SHIFT))
2974                         ret = -EINVAL;
2975                 if (fb_div & ~(SMC_SISLANDS_SPLL_DIV_TABLE_FBDIV_MASK >> SMC_SISLANDS_SPLL_DIV_TABLE_FBDIV_SHIFT))
2976                         ret = -EINVAL;
2977                 if (clk_s & ~(SMC_SISLANDS_SPLL_DIV_TABLE_CLKS_MASK >> SMC_SISLANDS_SPLL_DIV_TABLE_CLKS_SHIFT))
2978                         ret = -EINVAL;
2979                 if (clk_v & ~(SMC_SISLANDS_SPLL_DIV_TABLE_CLKV_MASK >> SMC_SISLANDS_SPLL_DIV_TABLE_CLKV_SHIFT))
2980                         ret = -EINVAL;
2981
2982                 if (ret)
2983                         break;
2984
2985                 tmp = ((fb_div << SMC_SISLANDS_SPLL_DIV_TABLE_FBDIV_SHIFT) & SMC_SISLANDS_SPLL_DIV_TABLE_FBDIV_MASK) |
2986                         ((p_div << SMC_SISLANDS_SPLL_DIV_TABLE_PDIV_SHIFT) & SMC_SISLANDS_SPLL_DIV_TABLE_PDIV_MASK);
2987                 spll_table->freq[i] = cpu_to_be32(tmp);
2988
2989                 tmp = ((clk_v << SMC_SISLANDS_SPLL_DIV_TABLE_CLKV_SHIFT) & SMC_SISLANDS_SPLL_DIV_TABLE_CLKV_MASK) |
2990                         ((clk_s << SMC_SISLANDS_SPLL_DIV_TABLE_CLKS_SHIFT) & SMC_SISLANDS_SPLL_DIV_TABLE_CLKS_MASK);
2991                 spll_table->ss[i] = cpu_to_be32(tmp);
2992
2993                 sclk += 512;
2994         }
2995
2996
2997         if (!ret)
2998                 ret = amdgpu_si_copy_bytes_to_smc(adev, si_pi->spll_table_start,
2999                                                   (u8 *)spll_table,
3000                                                   sizeof(SMC_SISLANDS_SPLL_DIV_TABLE),
3001                                                   si_pi->sram_end);
3002
3003         if (ret)
3004                 ni_pi->enable_power_containment = false;
3005
3006         kfree(spll_table);
3007
3008         return ret;
3009 }
3010
3011 struct si_dpm_quirk {
3012         u32 chip_vendor;
3013         u32 chip_device;
3014         u32 subsys_vendor;
3015         u32 subsys_device;
3016         u32 max_sclk;
3017         u32 max_mclk;
3018 };
3019
3020 /* cards with dpm stability problems */
3021 static struct si_dpm_quirk si_dpm_quirk_list[] = {
3022         /* PITCAIRN - https://bugs.freedesktop.org/show_bug.cgi?id=76490 */
3023         { PCI_VENDOR_ID_ATI, 0x6810, 0x1462, 0x3036, 0, 120000 },
3024         { PCI_VENDOR_ID_ATI, 0x6811, 0x174b, 0xe271, 0, 120000 },
3025         { PCI_VENDOR_ID_ATI, 0x6811, 0x174b, 0x2015, 0, 120000 },
3026         { PCI_VENDOR_ID_ATI, 0x6810, 0x174b, 0xe271, 85000, 90000 },
3027         { PCI_VENDOR_ID_ATI, 0x6811, 0x1462, 0x2015, 0, 120000 },
3028         { PCI_VENDOR_ID_ATI, 0x6811, 0x1043, 0x2015, 0, 120000 },
3029         { PCI_VENDOR_ID_ATI, 0x6811, 0x148c, 0x2015, 0, 120000 },
3030         { PCI_VENDOR_ID_ATI, 0x6810, 0x1682, 0x9275, 0, 120000 },
3031         { 0, 0, 0, 0 },
3032 };
3033
3034 static u16 si_get_lower_of_leakage_and_vce_voltage(struct amdgpu_device *adev,
3035                                                    u16 vce_voltage)
3036 {
3037         u16 highest_leakage = 0;
3038         struct si_power_info *si_pi = si_get_pi(adev);
3039         int i;
3040
3041         for (i = 0; i < si_pi->leakage_voltage.count; i++){
3042                 if (highest_leakage < si_pi->leakage_voltage.entries[i].voltage)
3043                         highest_leakage = si_pi->leakage_voltage.entries[i].voltage;
3044         }
3045
3046         if (si_pi->leakage_voltage.count && (highest_leakage < vce_voltage))
3047                 return highest_leakage;
3048
3049         return vce_voltage;
3050 }
3051
3052 static int si_get_vce_clock_voltage(struct amdgpu_device *adev,
3053                                     u32 evclk, u32 ecclk, u16 *voltage)
3054 {
3055         u32 i;
3056         int ret = -EINVAL;
3057         struct amdgpu_vce_clock_voltage_dependency_table *table =
3058                 &adev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table;
3059
3060         if (((evclk == 0) && (ecclk == 0)) ||
3061             (table && (table->count == 0))) {
3062                 *voltage = 0;
3063                 return 0;
3064         }
3065
3066         for (i = 0; i < table->count; i++) {
3067                 if ((evclk <= table->entries[i].evclk) &&
3068                     (ecclk <= table->entries[i].ecclk)) {
3069                         *voltage = table->entries[i].v;
3070                         ret = 0;
3071                         break;
3072                 }
3073         }
3074
3075         /* if no match return the highest voltage */
3076         if (ret)
3077                 *voltage = table->entries[table->count - 1].v;
3078
3079         *voltage = si_get_lower_of_leakage_and_vce_voltage(adev, *voltage);
3080
3081         return ret;
3082 }
3083
3084 static bool si_dpm_vblank_too_short(struct amdgpu_device *adev)
3085 {
3086
3087         u32 vblank_time = amdgpu_dpm_get_vblank_time(adev);
3088         /* we never hit the non-gddr5 limit so disable it */
3089         u32 switch_limit = adev->mc.vram_type == AMDGPU_VRAM_TYPE_GDDR5 ? 450 : 0;
3090
3091         if (vblank_time < switch_limit)
3092                 return true;
3093         else
3094                 return false;
3095
3096 }
3097
3098 static int ni_copy_and_switch_arb_sets(struct amdgpu_device *adev,
3099                                 u32 arb_freq_src, u32 arb_freq_dest)
3100 {
3101         u32 mc_arb_dram_timing;
3102         u32 mc_arb_dram_timing2;
3103         u32 burst_time;
3104         u32 mc_cg_config;
3105
3106         switch (arb_freq_src) {
3107         case MC_CG_ARB_FREQ_F0:
3108                 mc_arb_dram_timing  = RREG32(MC_ARB_DRAM_TIMING);
3109                 mc_arb_dram_timing2 = RREG32(MC_ARB_DRAM_TIMING2);
3110                 burst_time = (RREG32(MC_ARB_BURST_TIME) & STATE0_MASK) >> STATE0_SHIFT;
3111                 break;
3112         case MC_CG_ARB_FREQ_F1:
3113                 mc_arb_dram_timing  = RREG32(MC_ARB_DRAM_TIMING_1);
3114                 mc_arb_dram_timing2 = RREG32(MC_ARB_DRAM_TIMING2_1);
3115                 burst_time = (RREG32(MC_ARB_BURST_TIME) & STATE1_MASK) >> STATE1_SHIFT;
3116                 break;
3117         case MC_CG_ARB_FREQ_F2:
3118                 mc_arb_dram_timing  = RREG32(MC_ARB_DRAM_TIMING_2);
3119                 mc_arb_dram_timing2 = RREG32(MC_ARB_DRAM_TIMING2_2);
3120                 burst_time = (RREG32(MC_ARB_BURST_TIME) & STATE2_MASK) >> STATE2_SHIFT;
3121                 break;
3122         case MC_CG_ARB_FREQ_F3:
3123                 mc_arb_dram_timing  = RREG32(MC_ARB_DRAM_TIMING_3);
3124                 mc_arb_dram_timing2 = RREG32(MC_ARB_DRAM_TIMING2_3);
3125                 burst_time = (RREG32(MC_ARB_BURST_TIME) & STATE3_MASK) >> STATE3_SHIFT;
3126                 break;
3127         default:
3128                 return -EINVAL;
3129         }
3130
3131         switch (arb_freq_dest) {
3132         case MC_CG_ARB_FREQ_F0:
3133                 WREG32(MC_ARB_DRAM_TIMING, mc_arb_dram_timing);
3134                 WREG32(MC_ARB_DRAM_TIMING2, mc_arb_dram_timing2);
3135                 WREG32_P(MC_ARB_BURST_TIME, STATE0(burst_time), ~STATE0_MASK);
3136                 break;
3137         case MC_CG_ARB_FREQ_F1:
3138                 WREG32(MC_ARB_DRAM_TIMING_1, mc_arb_dram_timing);
3139                 WREG32(MC_ARB_DRAM_TIMING2_1, mc_arb_dram_timing2);
3140                 WREG32_P(MC_ARB_BURST_TIME, STATE1(burst_time), ~STATE1_MASK);
3141                 break;
3142         case MC_CG_ARB_FREQ_F2:
3143                 WREG32(MC_ARB_DRAM_TIMING_2, mc_arb_dram_timing);
3144                 WREG32(MC_ARB_DRAM_TIMING2_2, mc_arb_dram_timing2);
3145                 WREG32_P(MC_ARB_BURST_TIME, STATE2(burst_time), ~STATE2_MASK);
3146                 break;
3147         case MC_CG_ARB_FREQ_F3:
3148                 WREG32(MC_ARB_DRAM_TIMING_3, mc_arb_dram_timing);
3149                 WREG32(MC_ARB_DRAM_TIMING2_3, mc_arb_dram_timing2);
3150                 WREG32_P(MC_ARB_BURST_TIME, STATE3(burst_time), ~STATE3_MASK);
3151                 break;
3152         default:
3153                 return -EINVAL;
3154         }
3155
3156         mc_cg_config = RREG32(MC_CG_CONFIG) | 0x0000000F;
3157         WREG32(MC_CG_CONFIG, mc_cg_config);
3158         WREG32_P(MC_ARB_CG, CG_ARB_REQ(arb_freq_dest), ~CG_ARB_REQ_MASK);
3159
3160         return 0;
3161 }
3162
3163 static void ni_update_current_ps(struct amdgpu_device *adev,
3164                           struct amdgpu_ps *rps)
3165 {
3166         struct si_ps *new_ps = si_get_ps(rps);
3167         struct evergreen_power_info *eg_pi = evergreen_get_pi(adev);
3168         struct ni_power_info *ni_pi = ni_get_pi(adev);
3169
3170         eg_pi->current_rps = *rps;
3171         ni_pi->current_ps = *new_ps;
3172         eg_pi->current_rps.ps_priv = &ni_pi->current_ps;
3173         adev->pm.dpm.current_ps = &eg_pi->current_rps;
3174 }
3175
3176 static void ni_update_requested_ps(struct amdgpu_device *adev,
3177                             struct amdgpu_ps *rps)
3178 {
3179         struct si_ps *new_ps = si_get_ps(rps);
3180         struct evergreen_power_info *eg_pi = evergreen_get_pi(adev);
3181         struct ni_power_info *ni_pi = ni_get_pi(adev);
3182
3183         eg_pi->requested_rps = *rps;
3184         ni_pi->requested_ps = *new_ps;
3185         eg_pi->requested_rps.ps_priv = &ni_pi->requested_ps;
3186         adev->pm.dpm.requested_ps = &eg_pi->requested_rps;
3187 }
3188
3189 static void ni_set_uvd_clock_before_set_eng_clock(struct amdgpu_device *adev,
3190                                            struct amdgpu_ps *new_ps,
3191                                            struct amdgpu_ps *old_ps)
3192 {
3193         struct si_ps *new_state = si_get_ps(new_ps);
3194         struct si_ps *current_state = si_get_ps(old_ps);
3195
3196         if ((new_ps->vclk == old_ps->vclk) &&
3197             (new_ps->dclk == old_ps->dclk))
3198                 return;
3199
3200         if (new_state->performance_levels[new_state->performance_level_count - 1].sclk >=
3201             current_state->performance_levels[current_state->performance_level_count - 1].sclk)
3202                 return;
3203
3204         amdgpu_asic_set_uvd_clocks(adev, new_ps->vclk, new_ps->dclk);
3205 }
3206
3207 static void ni_set_uvd_clock_after_set_eng_clock(struct amdgpu_device *adev,
3208                                           struct amdgpu_ps *new_ps,
3209                                           struct amdgpu_ps *old_ps)
3210 {
3211         struct si_ps *new_state = si_get_ps(new_ps);
3212         struct si_ps *current_state = si_get_ps(old_ps);
3213
3214         if ((new_ps->vclk == old_ps->vclk) &&
3215             (new_ps->dclk == old_ps->dclk))
3216                 return;
3217
3218         if (new_state->performance_levels[new_state->performance_level_count - 1].sclk <
3219             current_state->performance_levels[current_state->performance_level_count - 1].sclk)
3220                 return;
3221
3222         amdgpu_asic_set_uvd_clocks(adev, new_ps->vclk, new_ps->dclk);
3223 }
3224
3225 static u16 btc_find_voltage(struct atom_voltage_table *table, u16 voltage)
3226 {
3227         unsigned int i;
3228
3229         for (i = 0; i < table->count; i++)
3230                 if (voltage <= table->entries[i].value)
3231                         return table->entries[i].value;
3232
3233         return table->entries[table->count - 1].value;
3234 }
3235
3236 static u32 btc_find_valid_clock(struct amdgpu_clock_array *clocks,
3237                                 u32 max_clock, u32 requested_clock)
3238 {
3239         unsigned int i;
3240
3241         if ((clocks == NULL) || (clocks->count == 0))
3242                 return (requested_clock < max_clock) ? requested_clock : max_clock;
3243
3244         for (i = 0; i < clocks->count; i++) {
3245                 if (clocks->values[i] >= requested_clock)
3246                         return (clocks->values[i] < max_clock) ? clocks->values[i] : max_clock;
3247         }
3248
3249         return (clocks->values[clocks->count - 1] < max_clock) ?
3250                 clocks->values[clocks->count - 1] : max_clock;
3251 }
3252
3253 static u32 btc_get_valid_mclk(struct amdgpu_device *adev,
3254                               u32 max_mclk, u32 requested_mclk)
3255 {
3256         return btc_find_valid_clock(&adev->pm.dpm.dyn_state.valid_mclk_values,
3257                                     max_mclk, requested_mclk);
3258 }
3259
3260 static u32 btc_get_valid_sclk(struct amdgpu_device *adev,
3261                               u32 max_sclk, u32 requested_sclk)
3262 {
3263         return btc_find_valid_clock(&adev->pm.dpm.dyn_state.valid_sclk_values,
3264                                     max_sclk, requested_sclk);
3265 }
3266
3267 static void btc_get_max_clock_from_voltage_dependency_table(struct amdgpu_clock_voltage_dependency_table *table,
3268                                                             u32 *max_clock)
3269 {
3270         u32 i, clock = 0;
3271
3272         if ((table == NULL) || (table->count == 0)) {
3273                 *max_clock = clock;
3274                 return;
3275         }
3276
3277         for (i = 0; i < table->count; i++) {
3278                 if (clock < table->entries[i].clk)
3279                         clock = table->entries[i].clk;
3280         }
3281         *max_clock = clock;
3282 }
3283
3284 static void btc_apply_voltage_dependency_rules(struct amdgpu_clock_voltage_dependency_table *table,
3285                                                u32 clock, u16 max_voltage, u16 *voltage)
3286 {
3287         u32 i;
3288
3289         if ((table == NULL) || (table->count == 0))
3290                 return;
3291
3292         for (i= 0; i < table->count; i++) {
3293                 if (clock <= table->entries[i].clk) {
3294                         if (*voltage < table->entries[i].v)
3295                                 *voltage = (u16)((table->entries[i].v < max_voltage) ?
3296                                            table->entries[i].v : max_voltage);
3297                         return;
3298                 }
3299         }
3300
3301         *voltage = (*voltage > max_voltage) ? *voltage : max_voltage;
3302 }
3303
3304 static void btc_adjust_clock_combinations(struct amdgpu_device *adev,
3305                                           const struct amdgpu_clock_and_voltage_limits *max_limits,
3306                                           struct rv7xx_pl *pl)
3307 {
3308
3309         if ((pl->mclk == 0) || (pl->sclk == 0))
3310                 return;
3311
3312         if (pl->mclk == pl->sclk)
3313                 return;
3314
3315         if (pl->mclk > pl->sclk) {
3316                 if (((pl->mclk + (pl->sclk - 1)) / pl->sclk) > adev->pm.dpm.dyn_state.mclk_sclk_ratio)
3317                         pl->sclk = btc_get_valid_sclk(adev,
3318                                                       max_limits->sclk,
3319                                                       (pl->mclk +
3320                                                       (adev->pm.dpm.dyn_state.mclk_sclk_ratio - 1)) /
3321                                                       adev->pm.dpm.dyn_state.mclk_sclk_ratio);
3322         } else {
3323                 if ((pl->sclk - pl->mclk) > adev->pm.dpm.dyn_state.sclk_mclk_delta)
3324                         pl->mclk = btc_get_valid_mclk(adev,
3325                                                       max_limits->mclk,
3326                                                       pl->sclk -
3327                                                       adev->pm.dpm.dyn_state.sclk_mclk_delta);
3328         }
3329 }
3330
3331 static void btc_apply_voltage_delta_rules(struct amdgpu_device *adev,
3332                                           u16 max_vddc, u16 max_vddci,
3333                                           u16 *vddc, u16 *vddci)
3334 {
3335         struct evergreen_power_info *eg_pi = evergreen_get_pi(adev);
3336         u16 new_voltage;
3337
3338         if ((0 == *vddc) || (0 == *vddci))
3339                 return;
3340
3341         if (*vddc > *vddci) {
3342                 if ((*vddc - *vddci) > adev->pm.dpm.dyn_state.vddc_vddci_delta) {
3343                         new_voltage = btc_find_voltage(&eg_pi->vddci_voltage_table,
3344                                                        (*vddc - adev->pm.dpm.dyn_state.vddc_vddci_delta));
3345                         *vddci = (new_voltage < max_vddci) ? new_voltage : max_vddci;
3346                 }
3347         } else {
3348                 if ((*vddci - *vddc) > adev->pm.dpm.dyn_state.vddc_vddci_delta) {
3349                         new_voltage = btc_find_voltage(&eg_pi->vddc_voltage_table,
3350                                                        (*vddci - adev->pm.dpm.dyn_state.vddc_vddci_delta));
3351                         *vddc = (new_voltage < max_vddc) ? new_voltage : max_vddc;
3352                 }
3353         }
3354 }
3355
3356 static enum amdgpu_pcie_gen r600_get_pcie_gen_support(struct amdgpu_device *adev,
3357                                                u32 sys_mask,
3358                                                enum amdgpu_pcie_gen asic_gen,
3359                                                enum amdgpu_pcie_gen default_gen)
3360 {
3361         switch (asic_gen) {
3362         case AMDGPU_PCIE_GEN1:
3363                 return AMDGPU_PCIE_GEN1;
3364         case AMDGPU_PCIE_GEN2:
3365                 return AMDGPU_PCIE_GEN2;
3366         case AMDGPU_PCIE_GEN3:
3367                 return AMDGPU_PCIE_GEN3;
3368         default:
3369                 if ((sys_mask & DRM_PCIE_SPEED_80) && (default_gen == AMDGPU_PCIE_GEN3))
3370                         return AMDGPU_PCIE_GEN3;
3371                 else if ((sys_mask & DRM_PCIE_SPEED_50) && (default_gen == AMDGPU_PCIE_GEN2))
3372                         return AMDGPU_PCIE_GEN2;
3373                 else
3374                         return AMDGPU_PCIE_GEN1;
3375         }
3376         return AMDGPU_PCIE_GEN1;
3377 }
3378
3379 static void r600_calculate_u_and_p(u32 i, u32 r_c, u32 p_b,
3380                             u32 *p, u32 *u)
3381 {
3382         u32 b_c = 0;
3383         u32 i_c;
3384         u32 tmp;
3385
3386         i_c = (i * r_c) / 100;
3387         tmp = i_c >> p_b;
3388
3389         while (tmp) {
3390                 b_c++;
3391                 tmp >>= 1;
3392         }
3393
3394         *u = (b_c + 1) / 2;
3395         *p = i_c / (1 << (2 * (*u)));
3396 }
3397
3398 static int r600_calculate_at(u32 t, u32 h, u32 fh, u32 fl, u32 *tl, u32 *th)
3399 {
3400         u32 k, a, ah, al;
3401         u32 t1;
3402
3403         if ((fl == 0) || (fh == 0) || (fl > fh))
3404                 return -EINVAL;
3405
3406         k = (100 * fh) / fl;
3407         t1 = (t * (k - 100));
3408         a = (1000 * (100 * h + t1)) / (10000 + (t1 / 100));
3409         a = (a + 5) / 10;
3410         ah = ((a * t) + 5000) / 10000;
3411         al = a - ah;
3412
3413         *th = t - ah;
3414         *tl = t + al;
3415
3416         return 0;
3417 }
3418
3419 static bool r600_is_uvd_state(u32 class, u32 class2)
3420 {
3421         if (class & ATOM_PPLIB_CLASSIFICATION_UVDSTATE)
3422                 return true;
3423         if (class & ATOM_PPLIB_CLASSIFICATION_HD2STATE)
3424                 return true;
3425         if (class & ATOM_PPLIB_CLASSIFICATION_HDSTATE)
3426                 return true;
3427         if (class & ATOM_PPLIB_CLASSIFICATION_SDSTATE)
3428                 return true;
3429         if (class2 & ATOM_PPLIB_CLASSIFICATION2_MVC)
3430                 return true;
3431         return false;
3432 }
3433
3434 static u8 rv770_get_memory_module_index(struct amdgpu_device *adev)
3435 {
3436         return (u8) ((RREG32(BIOS_SCRATCH_4) >> 16) & 0xff);
3437 }
3438
3439 static void rv770_get_max_vddc(struct amdgpu_device *adev)
3440 {
3441         struct rv7xx_power_info *pi = rv770_get_pi(adev);
3442         u16 vddc;
3443
3444         if (amdgpu_atombios_get_max_vddc(adev, 0, 0, &vddc))
3445                 pi->max_vddc = 0;
3446         else
3447                 pi->max_vddc = vddc;
3448 }
3449
3450 static void rv770_get_engine_memory_ss(struct amdgpu_device *adev)
3451 {
3452         struct rv7xx_power_info *pi = rv770_get_pi(adev);
3453         struct amdgpu_atom_ss ss;
3454
3455         pi->sclk_ss = amdgpu_atombios_get_asic_ss_info(adev, &ss,
3456                                                        ASIC_INTERNAL_ENGINE_SS, 0);
3457         pi->mclk_ss = amdgpu_atombios_get_asic_ss_info(adev, &ss,
3458                                                        ASIC_INTERNAL_MEMORY_SS, 0);
3459
3460         if (pi->sclk_ss || pi->mclk_ss)
3461                 pi->dynamic_ss = true;
3462         else
3463                 pi->dynamic_ss = false;
3464 }
3465
3466
3467 static void si_apply_state_adjust_rules(struct amdgpu_device *adev,
3468                                         struct amdgpu_ps *rps)
3469 {
3470         struct  si_ps *ps = si_get_ps(rps);
3471         struct amdgpu_clock_and_voltage_limits *max_limits;
3472         bool disable_mclk_switching = false;
3473         bool disable_sclk_switching = false;
3474         u32 mclk, sclk;
3475         u16 vddc, vddci, min_vce_voltage = 0;
3476         u32 max_sclk_vddc, max_mclk_vddci, max_mclk_vddc;
3477         u32 max_sclk = 0, max_mclk = 0;
3478         int i;
3479         struct si_dpm_quirk *p = si_dpm_quirk_list;
3480
3481         /* limit all SI kickers */
3482         if (adev->asic_type == CHIP_PITCAIRN) {
3483                 if ((adev->pdev->revision == 0x81) ||
3484                     (adev->pdev->device == 0x6810) ||
3485                     (adev->pdev->device == 0x6811) ||
3486                     (adev->pdev->device == 0x6816) ||
3487                     (adev->pdev->device == 0x6817) ||
3488                     (adev->pdev->device == 0x6806))
3489                         max_mclk = 120000;
3490         } else if (adev->asic_type == CHIP_OLAND) {
3491                 if ((adev->pdev->revision == 0xC7) ||
3492                     (adev->pdev->revision == 0x80) ||
3493                     (adev->pdev->revision == 0x81) ||
3494                     (adev->pdev->revision == 0x83) ||
3495                     (adev->pdev->revision == 0x87) ||
3496                     (adev->pdev->device == 0x6604) ||
3497                     (adev->pdev->device == 0x6605)) {
3498                         max_sclk = 75000;
3499                         max_mclk = 80000;
3500                 }
3501         } else if (adev->asic_type == CHIP_HAINAN) {
3502                 if ((adev->pdev->revision == 0x81) ||
3503                     (adev->pdev->revision == 0x83) ||
3504                     (adev->pdev->revision == 0xC3) ||
3505                     (adev->pdev->device == 0x6664) ||
3506                     (adev->pdev->device == 0x6665) ||
3507                     (adev->pdev->device == 0x6667)) {
3508                         max_sclk = 75000;
3509                         max_mclk = 80000;
3510                 }
3511         }
3512         /* Apply dpm quirks */
3513         while (p && p->chip_device != 0) {
3514                 if (adev->pdev->vendor == p->chip_vendor &&
3515                     adev->pdev->device == p->chip_device &&
3516                     adev->pdev->subsystem_vendor == p->subsys_vendor &&
3517                     adev->pdev->subsystem_device == p->subsys_device) {
3518                         max_sclk = p->max_sclk;
3519                         max_mclk = p->max_mclk;
3520                         break;
3521                 }
3522                 ++p;
3523         }
3524
3525         if (rps->vce_active) {
3526                 rps->evclk = adev->pm.dpm.vce_states[adev->pm.dpm.vce_level].evclk;
3527                 rps->ecclk = adev->pm.dpm.vce_states[adev->pm.dpm.vce_level].ecclk;
3528                 si_get_vce_clock_voltage(adev, rps->evclk, rps->ecclk,
3529                                          &min_vce_voltage);
3530         } else {
3531                 rps->evclk = 0;
3532                 rps->ecclk = 0;
3533         }
3534
3535         if ((adev->pm.dpm.new_active_crtc_count > 1) ||
3536             si_dpm_vblank_too_short(adev))
3537                 disable_mclk_switching = true;
3538
3539         if (rps->vclk || rps->dclk) {
3540                 disable_mclk_switching = true;
3541                 disable_sclk_switching = true;
3542         }
3543
3544         if (adev->pm.dpm.ac_power)
3545                 max_limits = &adev->pm.dpm.dyn_state.max_clock_voltage_on_ac;
3546         else
3547                 max_limits = &adev->pm.dpm.dyn_state.max_clock_voltage_on_dc;
3548
3549         for (i = ps->performance_level_count - 2; i >= 0; i--) {
3550                 if (ps->performance_levels[i].vddc > ps->performance_levels[i+1].vddc)
3551                         ps->performance_levels[i].vddc = ps->performance_levels[i+1].vddc;
3552         }
3553         if (adev->pm.dpm.ac_power == false) {
3554                 for (i = 0; i < ps->performance_level_count; i++) {
3555                         if (ps->performance_levels[i].mclk > max_limits->mclk)
3556                                 ps->performance_levels[i].mclk = max_limits->mclk;
3557                         if (ps->performance_levels[i].sclk > max_limits->sclk)
3558                                 ps->performance_levels[i].sclk = max_limits->sclk;
3559                         if (ps->performance_levels[i].vddc > max_limits->vddc)
3560                                 ps->performance_levels[i].vddc = max_limits->vddc;
3561                         if (ps->performance_levels[i].vddci > max_limits->vddci)
3562                                 ps->performance_levels[i].vddci = max_limits->vddci;
3563                 }
3564         }
3565
3566         /* limit clocks to max supported clocks based on voltage dependency tables */
3567         btc_get_max_clock_from_voltage_dependency_table(&adev->pm.dpm.dyn_state.vddc_dependency_on_sclk,
3568                                                         &max_sclk_vddc);
3569         btc_get_max_clock_from_voltage_dependency_table(&adev->pm.dpm.dyn_state.vddci_dependency_on_mclk,
3570                                                         &max_mclk_vddci);
3571         btc_get_max_clock_from_voltage_dependency_table(&adev->pm.dpm.dyn_state.vddc_dependency_on_mclk,
3572                                                         &max_mclk_vddc);
3573
3574         for (i = 0; i < ps->performance_level_count; i++) {
3575                 if (max_sclk_vddc) {
3576                         if (ps->performance_levels[i].sclk > max_sclk_vddc)
3577                                 ps->performance_levels[i].sclk = max_sclk_vddc;
3578                 }
3579                 if (max_mclk_vddci) {
3580                         if (ps->performance_levels[i].mclk > max_mclk_vddci)
3581                                 ps->performance_levels[i].mclk = max_mclk_vddci;
3582                 }
3583                 if (max_mclk_vddc) {
3584                         if (ps->performance_levels[i].mclk > max_mclk_vddc)
3585                                 ps->performance_levels[i].mclk = max_mclk_vddc;
3586                 }
3587                 if (max_mclk) {
3588                         if (ps->performance_levels[i].mclk > max_mclk)
3589                                 ps->performance_levels[i].mclk = max_mclk;
3590                 }
3591                 if (max_sclk) {
3592                         if (ps->performance_levels[i].sclk > max_sclk)
3593                                 ps->performance_levels[i].sclk = max_sclk;
3594                 }
3595         }
3596
3597         /* XXX validate the min clocks required for display */
3598
3599         if (disable_mclk_switching) {
3600                 mclk  = ps->performance_levels[ps->performance_level_count - 1].mclk;
3601                 vddci = ps->performance_levels[ps->performance_level_count - 1].vddci;
3602         } else {
3603                 mclk = ps->performance_levels[0].mclk;
3604                 vddci = ps->performance_levels[0].vddci;
3605         }
3606
3607         if (disable_sclk_switching) {
3608                 sclk = ps->performance_levels[ps->performance_level_count - 1].sclk;
3609                 vddc = ps->performance_levels[ps->performance_level_count - 1].vddc;
3610         } else {
3611                 sclk = ps->performance_levels[0].sclk;
3612                 vddc = ps->performance_levels[0].vddc;
3613         }
3614
3615         if (rps->vce_active) {
3616                 if (sclk < adev->pm.dpm.vce_states[adev->pm.dpm.vce_level].sclk)
3617                         sclk = adev->pm.dpm.vce_states[adev->pm.dpm.vce_level].sclk;
3618                 if (mclk < adev->pm.dpm.vce_states[adev->pm.dpm.vce_level].mclk)
3619                         mclk = adev->pm.dpm.vce_states[adev->pm.dpm.vce_level].mclk;
3620         }
3621
3622         /* adjusted low state */
3623         ps->performance_levels[0].sclk = sclk;
3624         ps->performance_levels[0].mclk = mclk;
3625         ps->performance_levels[0].vddc = vddc;
3626         ps->performance_levels[0].vddci = vddci;
3627
3628         if (disable_sclk_switching) {
3629                 sclk = ps->performance_levels[0].sclk;
3630                 for (i = 1; i < ps->performance_level_count; i++) {
3631                         if (sclk < ps->performance_levels[i].sclk)
3632                                 sclk = ps->performance_levels[i].sclk;
3633                 }
3634                 for (i = 0; i < ps->performance_level_count; i++) {
3635                         ps->performance_levels[i].sclk = sclk;
3636                         ps->performance_levels[i].vddc = vddc;
3637                 }
3638         } else {
3639                 for (i = 1; i < ps->performance_level_count; i++) {
3640                         if (ps->performance_levels[i].sclk < ps->performance_levels[i - 1].sclk)
3641                                 ps->performance_levels[i].sclk = ps->performance_levels[i - 1].sclk;
3642                         if (ps->performance_levels[i].vddc < ps->performance_levels[i - 1].vddc)
3643                                 ps->performance_levels[i].vddc = ps->performance_levels[i - 1].vddc;
3644                 }
3645         }
3646
3647         if (disable_mclk_switching) {
3648                 mclk = ps->performance_levels[0].mclk;
3649                 for (i = 1; i < ps->performance_level_count; i++) {
3650                         if (mclk < ps->performance_levels[i].mclk)
3651                                 mclk = ps->performance_levels[i].mclk;
3652                 }
3653                 for (i = 0; i < ps->performance_level_count; i++) {
3654                         ps->performance_levels[i].mclk = mclk;
3655                         ps->performance_levels[i].vddci = vddci;
3656                 }
3657         } else {
3658                 for (i = 1; i < ps->performance_level_count; i++) {
3659                         if (ps->performance_levels[i].mclk < ps->performance_levels[i - 1].mclk)
3660                                 ps->performance_levels[i].mclk = ps->performance_levels[i - 1].mclk;
3661                         if (ps->performance_levels[i].vddci < ps->performance_levels[i - 1].vddci)
3662                                 ps->performance_levels[i].vddci = ps->performance_levels[i - 1].vddci;
3663                 }
3664         }
3665
3666         for (i = 0; i < ps->performance_level_count; i++)
3667                 btc_adjust_clock_combinations(adev, max_limits,
3668                                               &ps->performance_levels[i]);
3669
3670         for (i = 0; i < ps->performance_level_count; i++) {
3671                 if (ps->performance_levels[i].vddc < min_vce_voltage)
3672                         ps->performance_levels[i].vddc = min_vce_voltage;
3673                 btc_apply_voltage_dependency_rules(&adev->pm.dpm.dyn_state.vddc_dependency_on_sclk,
3674                                                    ps->performance_levels[i].sclk,
3675                                                    max_limits->vddc,  &ps->performance_levels[i].vddc);
3676                 btc_apply_voltage_dependency_rules(&adev->pm.dpm.dyn_state.vddci_dependency_on_mclk,
3677                                                    ps->performance_levels[i].mclk,
3678                                                    max_limits->vddci, &ps->performance_levels[i].vddci);
3679                 btc_apply_voltage_dependency_rules(&adev->pm.dpm.dyn_state.vddc_dependency_on_mclk,
3680                                                    ps->performance_levels[i].mclk,
3681                                                    max_limits->vddc,  &ps->performance_levels[i].vddc);
3682                 btc_apply_voltage_dependency_rules(&adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk,
3683                                                    adev->clock.current_dispclk,
3684                                                    max_limits->vddc,  &ps->performance_levels[i].vddc);
3685         }
3686
3687         for (i = 0; i < ps->performance_level_count; i++) {
3688                 btc_apply_voltage_delta_rules(adev,
3689                                               max_limits->vddc, max_limits->vddci,
3690                                               &ps->performance_levels[i].vddc,
3691                                               &ps->performance_levels[i].vddci);
3692         }
3693
3694         ps->dc_compatible = true;
3695         for (i = 0; i < ps->performance_level_count; i++) {
3696                 if (ps->performance_levels[i].vddc > adev->pm.dpm.dyn_state.max_clock_voltage_on_dc.vddc)
3697                         ps->dc_compatible = false;
3698         }
3699 }
3700
3701 #if 0
3702 static int si_read_smc_soft_register(struct amdgpu_device *adev,
3703                                      u16 reg_offset, u32 *value)
3704 {
3705         struct si_power_info *si_pi = si_get_pi(adev);
3706
3707         return amdgpu_si_read_smc_sram_dword(adev,
3708                                              si_pi->soft_regs_start + reg_offset, value,
3709                                              si_pi->sram_end);
3710 }
3711 #endif
3712
3713 static int si_write_smc_soft_register(struct amdgpu_device *adev,
3714                                       u16 reg_offset, u32 value)
3715 {
3716         struct si_power_info *si_pi = si_get_pi(adev);
3717
3718         return amdgpu_si_write_smc_sram_dword(adev,
3719                                               si_pi->soft_regs_start + reg_offset,
3720                                               value, si_pi->sram_end);
3721 }
3722
3723 static bool si_is_special_1gb_platform(struct amdgpu_device *adev)
3724 {
3725         bool ret = false;
3726         u32 tmp, width, row, column, bank, density;
3727         bool is_memory_gddr5, is_special;
3728
3729         tmp = RREG32(MC_SEQ_MISC0);
3730         is_memory_gddr5 = (MC_SEQ_MISC0_GDDR5_VALUE == ((tmp & MC_SEQ_MISC0_GDDR5_MASK) >> MC_SEQ_MISC0_GDDR5_SHIFT));
3731         is_special = (MC_SEQ_MISC0_REV_ID_VALUE == ((tmp & MC_SEQ_MISC0_REV_ID_MASK) >> MC_SEQ_MISC0_REV_ID_SHIFT))
3732                 & (MC_SEQ_MISC0_VEN_ID_VALUE == ((tmp & MC_SEQ_MISC0_VEN_ID_MASK) >> MC_SEQ_MISC0_VEN_ID_SHIFT));
3733
3734         WREG32(MC_SEQ_IO_DEBUG_INDEX, 0xb);
3735         width = ((RREG32(MC_SEQ_IO_DEBUG_DATA) >> 1) & 1) ? 16 : 32;
3736
3737         tmp = RREG32(MC_ARB_RAMCFG);
3738         row = ((tmp & NOOFROWS_MASK) >> NOOFROWS_SHIFT) + 10;
3739         column = ((tmp & NOOFCOLS_MASK) >> NOOFCOLS_SHIFT) + 8;
3740         bank = ((tmp & NOOFBANK_MASK) >> NOOFBANK_SHIFT) + 2;
3741
3742         density = (1 << (row + column - 20 + bank)) * width;
3743
3744         if ((adev->pdev->device == 0x6819) &&
3745             is_memory_gddr5 && is_special && (density == 0x400))
3746                 ret = true;
3747
3748         return ret;
3749 }
3750
3751 static void si_get_leakage_vddc(struct amdgpu_device *adev)
3752 {
3753         struct si_power_info *si_pi = si_get_pi(adev);
3754         u16 vddc, count = 0;
3755         int i, ret;
3756
3757         for (i = 0; i < SISLANDS_MAX_LEAKAGE_COUNT; i++) {
3758                 ret = amdgpu_atombios_get_leakage_vddc_based_on_leakage_idx(adev, &vddc, SISLANDS_LEAKAGE_INDEX0 + i);
3759
3760                 if (!ret && (vddc > 0) && (vddc != (SISLANDS_LEAKAGE_INDEX0 + i))) {
3761                         si_pi->leakage_voltage.entries[count].voltage = vddc;
3762                         si_pi->leakage_voltage.entries[count].leakage_index =
3763                                 SISLANDS_LEAKAGE_INDEX0 + i;
3764                         count++;
3765                 }
3766         }
3767         si_pi->leakage_voltage.count = count;
3768 }
3769
3770 static int si_get_leakage_voltage_from_leakage_index(struct amdgpu_device *adev,
3771                                                      u32 index, u16 *leakage_voltage)
3772 {
3773         struct si_power_info *si_pi = si_get_pi(adev);
3774         int i;
3775
3776         if (leakage_voltage == NULL)
3777                 return -EINVAL;
3778
3779         if ((index & 0xff00) != 0xff00)
3780                 return -EINVAL;
3781
3782         if ((index & 0xff) > SISLANDS_MAX_LEAKAGE_COUNT + 1)
3783                 return -EINVAL;
3784
3785         if (index < SISLANDS_LEAKAGE_INDEX0)
3786                 return -EINVAL;
3787
3788         for (i = 0; i < si_pi->leakage_voltage.count; i++) {
3789                 if (si_pi->leakage_voltage.entries[i].leakage_index == index) {
3790                         *leakage_voltage = si_pi->leakage_voltage.entries[i].voltage;
3791                         return 0;
3792                 }
3793         }
3794         return -EAGAIN;
3795 }
3796
3797 static void si_set_dpm_event_sources(struct amdgpu_device *adev, u32 sources)
3798 {
3799         struct rv7xx_power_info *pi = rv770_get_pi(adev);
3800         bool want_thermal_protection;
3801         enum amdgpu_dpm_event_src dpm_event_src;
3802
3803         switch (sources) {
3804         case 0:
3805         default:
3806                 want_thermal_protection = false;
3807                 break;
3808         case (1 << AMDGPU_DPM_AUTO_THROTTLE_SRC_THERMAL):
3809                 want_thermal_protection = true;
3810                 dpm_event_src = AMDGPU_DPM_EVENT_SRC_DIGITAL;
3811                 break;
3812         case (1 << AMDGPU_DPM_AUTO_THROTTLE_SRC_EXTERNAL):
3813                 want_thermal_protection = true;
3814                 dpm_event_src = AMDGPU_DPM_EVENT_SRC_EXTERNAL;
3815                 break;
3816         case ((1 << AMDGPU_DPM_AUTO_THROTTLE_SRC_EXTERNAL) |
3817               (1 << AMDGPU_DPM_AUTO_THROTTLE_SRC_THERMAL)):
3818                 want_thermal_protection = true;
3819                 dpm_event_src = AMDGPU_DPM_EVENT_SRC_DIGIAL_OR_EXTERNAL;
3820                 break;
3821         }
3822
3823         if (want_thermal_protection) {
3824                 WREG32_P(CG_THERMAL_CTRL, DPM_EVENT_SRC(dpm_event_src), ~DPM_EVENT_SRC_MASK);
3825                 if (pi->thermal_protection)
3826                         WREG32_P(GENERAL_PWRMGT, 0, ~THERMAL_PROTECTION_DIS);
3827         } else {
3828                 WREG32_P(GENERAL_PWRMGT, THERMAL_PROTECTION_DIS, ~THERMAL_PROTECTION_DIS);
3829         }
3830 }
3831
3832 static void si_enable_auto_throttle_source(struct amdgpu_device *adev,
3833                                            enum amdgpu_dpm_auto_throttle_src source,
3834                                            bool enable)
3835 {
3836         struct rv7xx_power_info *pi = rv770_get_pi(adev);
3837
3838         if (enable) {
3839                 if (!(pi->active_auto_throttle_sources & (1 << source))) {
3840                         pi->active_auto_throttle_sources |= 1 << source;
3841                         si_set_dpm_event_sources(adev, pi->active_auto_throttle_sources);
3842                 }
3843         } else {
3844                 if (pi->active_auto_throttle_sources & (1 << source)) {
3845                         pi->active_auto_throttle_sources &= ~(1 << source);
3846                         si_set_dpm_event_sources(adev, pi->active_auto_throttle_sources);
3847                 }
3848         }
3849 }
3850
3851 static void si_start_dpm(struct amdgpu_device *adev)
3852 {
3853         WREG32_P(GENERAL_PWRMGT, GLOBAL_PWRMGT_EN, ~GLOBAL_PWRMGT_EN);
3854 }
3855
3856 static void si_stop_dpm(struct amdgpu_device *adev)
3857 {
3858         WREG32_P(GENERAL_PWRMGT, 0, ~GLOBAL_PWRMGT_EN);
3859 }
3860
3861 static void si_enable_sclk_control(struct amdgpu_device *adev, bool enable)
3862 {
3863         if (enable)
3864                 WREG32_P(SCLK_PWRMGT_CNTL, 0, ~SCLK_PWRMGT_OFF);
3865         else
3866                 WREG32_P(SCLK_PWRMGT_CNTL, SCLK_PWRMGT_OFF, ~SCLK_PWRMGT_OFF);
3867
3868 }
3869
3870 #if 0
3871 static int si_notify_hardware_of_thermal_state(struct amdgpu_device *adev,
3872                                                u32 thermal_level)
3873 {
3874         PPSMC_Result ret;
3875
3876         if (thermal_level == 0) {
3877                 ret = amdgpu_si_send_msg_to_smc(adev, PPSMC_MSG_EnableThermalInterrupt);
3878                 if (ret == PPSMC_Result_OK)
3879                         return 0;
3880                 else
3881                         return -EINVAL;
3882         }
3883         return 0;
3884 }
3885
3886 static void si_notify_hardware_vpu_recovery_event(struct amdgpu_device *adev)
3887 {
3888         si_write_smc_soft_register(adev, SI_SMC_SOFT_REGISTER_tdr_is_about_to_happen, true);
3889 }
3890 #endif
3891
3892 #if 0
3893 static int si_notify_hw_of_powersource(struct amdgpu_device *adev, bool ac_power)
3894 {
3895         if (ac_power)
3896                 return (amdgpu_si_send_msg_to_smc(adev, PPSMC_MSG_RunningOnAC) == PPSMC_Result_OK) ?
3897                         0 : -EINVAL;
3898
3899         return 0;
3900 }
3901 #endif
3902
3903 static PPSMC_Result si_send_msg_to_smc_with_parameter(struct amdgpu_device *adev,
3904                                                       PPSMC_Msg msg, u32 parameter)
3905 {
3906         WREG32(SMC_SCRATCH0, parameter);
3907         return amdgpu_si_send_msg_to_smc(adev, msg);
3908 }
3909
3910 static int si_restrict_performance_levels_before_switch(struct amdgpu_device *adev)
3911 {
3912         if (amdgpu_si_send_msg_to_smc(adev, PPSMC_MSG_NoForcedLevel) != PPSMC_Result_OK)
3913                 return -EINVAL;
3914
3915         return (si_send_msg_to_smc_with_parameter(adev, PPSMC_MSG_SetEnabledLevels, 1) == PPSMC_Result_OK) ?
3916                 0 : -EINVAL;
3917 }
3918
3919 static int si_dpm_force_performance_level(struct amdgpu_device *adev,
3920                                    enum amdgpu_dpm_forced_level level)
3921 {
3922         struct amdgpu_ps *rps = adev->pm.dpm.current_ps;
3923         struct  si_ps *ps = si_get_ps(rps);
3924         u32 levels = ps->performance_level_count;
3925
3926         if (level == AMDGPU_DPM_FORCED_LEVEL_HIGH) {
3927                 if (si_send_msg_to_smc_with_parameter(adev, PPSMC_MSG_SetEnabledLevels, levels) != PPSMC_Result_OK)
3928                         return -EINVAL;
3929
3930                 if (si_send_msg_to_smc_with_parameter(adev, PPSMC_MSG_SetForcedLevels, 1) != PPSMC_Result_OK)
3931                         return -EINVAL;
3932         } else if (level == AMDGPU_DPM_FORCED_LEVEL_LOW) {
3933                 if (si_send_msg_to_smc_with_parameter(adev, PPSMC_MSG_SetForcedLevels, 0) != PPSMC_Result_OK)
3934                         return -EINVAL;
3935
3936                 if (si_send_msg_to_smc_with_parameter(adev, PPSMC_MSG_SetEnabledLevels, 1) != PPSMC_Result_OK)
3937                         return -EINVAL;
3938         } else if (level == AMDGPU_DPM_FORCED_LEVEL_AUTO) {
3939                 if (si_send_msg_to_smc_with_parameter(adev, PPSMC_MSG_SetForcedLevels, 0) != PPSMC_Result_OK)
3940                         return -EINVAL;
3941
3942                 if (si_send_msg_to_smc_with_parameter(adev, PPSMC_MSG_SetEnabledLevels, levels) != PPSMC_Result_OK)
3943                         return -EINVAL;
3944         }
3945
3946         adev->pm.dpm.forced_level = level;
3947
3948         return 0;
3949 }
3950
3951 #if 0
3952 static int si_set_boot_state(struct amdgpu_device *adev)
3953 {
3954         return (amdgpu_si_send_msg_to_smc(adev, PPSMC_MSG_SwitchToInitialState) == PPSMC_Result_OK) ?
3955                 0 : -EINVAL;
3956 }
3957 #endif
3958
3959 static int si_set_sw_state(struct amdgpu_device *adev)
3960 {
3961         return (amdgpu_si_send_msg_to_smc(adev, PPSMC_MSG_SwitchToSwState) == PPSMC_Result_OK) ?
3962                 0 : -EINVAL;
3963 }
3964
3965 static int si_halt_smc(struct amdgpu_device *adev)
3966 {
3967         if (amdgpu_si_send_msg_to_smc(adev, PPSMC_MSG_Halt) != PPSMC_Result_OK)
3968                 return -EINVAL;
3969
3970         return (amdgpu_si_wait_for_smc_inactive(adev) == PPSMC_Result_OK) ?
3971                 0 : -EINVAL;
3972 }
3973
3974 static int si_resume_smc(struct amdgpu_device *adev)
3975 {
3976         if (amdgpu_si_send_msg_to_smc(adev, PPSMC_FlushDataCache) != PPSMC_Result_OK)
3977                 return -EINVAL;
3978
3979         return (amdgpu_si_send_msg_to_smc(adev, PPSMC_MSG_Resume) == PPSMC_Result_OK) ?
3980                 0 : -EINVAL;
3981 }
3982
3983 static void si_dpm_start_smc(struct amdgpu_device *adev)
3984 {
3985         amdgpu_si_program_jump_on_start(adev);
3986         amdgpu_si_start_smc(adev);
3987         amdgpu_si_smc_clock(adev, true);
3988 }
3989
3990 static void si_dpm_stop_smc(struct amdgpu_device *adev)
3991 {
3992         amdgpu_si_reset_smc(adev);
3993         amdgpu_si_smc_clock(adev, false);
3994 }
3995
3996 static int si_process_firmware_header(struct amdgpu_device *adev)
3997 {
3998         struct si_power_info *si_pi = si_get_pi(adev);
3999         u32 tmp;
4000         int ret;
4001
4002         ret = amdgpu_si_read_smc_sram_dword(adev,
4003                                             SISLANDS_SMC_FIRMWARE_HEADER_LOCATION +
4004                                             SISLANDS_SMC_FIRMWARE_HEADER_stateTable,
4005                                             &tmp, si_pi->sram_end);
4006         if (ret)
4007                 return ret;
4008
4009         si_pi->state_table_start = tmp;
4010
4011         ret = amdgpu_si_read_smc_sram_dword(adev,
4012                                             SISLANDS_SMC_FIRMWARE_HEADER_LOCATION +
4013                                             SISLANDS_SMC_FIRMWARE_HEADER_softRegisters,
4014                                             &tmp, si_pi->sram_end);
4015         if (ret)
4016                 return ret;
4017
4018         si_pi->soft_regs_start = tmp;
4019
4020         ret = amdgpu_si_read_smc_sram_dword(adev,
4021                                             SISLANDS_SMC_FIRMWARE_HEADER_LOCATION +
4022                                             SISLANDS_SMC_FIRMWARE_HEADER_mcRegisterTable,
4023                                             &tmp, si_pi->sram_end);
4024         if (ret)
4025                 return ret;
4026
4027         si_pi->mc_reg_table_start = tmp;
4028
4029         ret = amdgpu_si_read_smc_sram_dword(adev,
4030                                             SISLANDS_SMC_FIRMWARE_HEADER_LOCATION +
4031                                             SISLANDS_SMC_FIRMWARE_HEADER_fanTable,
4032                                             &tmp, si_pi->sram_end);
4033         if (ret)
4034                 return ret;
4035
4036         si_pi->fan_table_start = tmp;
4037
4038         ret = amdgpu_si_read_smc_sram_dword(adev,
4039                                             SISLANDS_SMC_FIRMWARE_HEADER_LOCATION +
4040                                             SISLANDS_SMC_FIRMWARE_HEADER_mcArbDramAutoRefreshTable,
4041                                             &tmp, si_pi->sram_end);
4042         if (ret)
4043                 return ret;
4044
4045         si_pi->arb_table_start = tmp;
4046
4047         ret = amdgpu_si_read_smc_sram_dword(adev,
4048                                             SISLANDS_SMC_FIRMWARE_HEADER_LOCATION +
4049                                             SISLANDS_SMC_FIRMWARE_HEADER_CacConfigTable,
4050                                             &tmp, si_pi->sram_end);
4051         if (ret)
4052                 return ret;
4053
4054         si_pi->cac_table_start = tmp;
4055
4056         ret = amdgpu_si_read_smc_sram_dword(adev,
4057                                             SISLANDS_SMC_FIRMWARE_HEADER_LOCATION +
4058                                             SISLANDS_SMC_FIRMWARE_HEADER_DteConfiguration,
4059                                             &tmp, si_pi->sram_end);
4060         if (ret)
4061                 return ret;
4062
4063         si_pi->dte_table_start = tmp;
4064
4065         ret = amdgpu_si_read_smc_sram_dword(adev,
4066                                             SISLANDS_SMC_FIRMWARE_HEADER_LOCATION +
4067                                             SISLANDS_SMC_FIRMWARE_HEADER_spllTable,
4068                                             &tmp, si_pi->sram_end);
4069         if (ret)
4070                 return ret;
4071
4072         si_pi->spll_table_start = tmp;
4073
4074         ret = amdgpu_si_read_smc_sram_dword(adev,
4075                                             SISLANDS_SMC_FIRMWARE_HEADER_LOCATION +
4076                                             SISLANDS_SMC_FIRMWARE_HEADER_PAPMParameters,
4077                                             &tmp, si_pi->sram_end);
4078         if (ret)
4079                 return ret;
4080
4081         si_pi->papm_cfg_table_start = tmp;
4082
4083         return ret;
4084 }
4085
4086 static void si_read_clock_registers(struct amdgpu_device *adev)
4087 {
4088         struct si_power_info *si_pi = si_get_pi(adev);
4089
4090         si_pi->clock_registers.cg_spll_func_cntl = RREG32(CG_SPLL_FUNC_CNTL);
4091         si_pi->clock_registers.cg_spll_func_cntl_2 = RREG32(CG_SPLL_FUNC_CNTL_2);
4092         si_pi->clock_registers.cg_spll_func_cntl_3 = RREG32(CG_SPLL_FUNC_CNTL_3);
4093         si_pi->clock_registers.cg_spll_func_cntl_4 = RREG32(CG_SPLL_FUNC_CNTL_4);
4094         si_pi->clock_registers.cg_spll_spread_spectrum = RREG32(CG_SPLL_SPREAD_SPECTRUM);
4095         si_pi->clock_registers.cg_spll_spread_spectrum_2 = RREG32(CG_SPLL_SPREAD_SPECTRUM_2);
4096         si_pi->clock_registers.dll_cntl = RREG32(DLL_CNTL);
4097         si_pi->clock_registers.mclk_pwrmgt_cntl = RREG32(MCLK_PWRMGT_CNTL);
4098         si_pi->clock_registers.mpll_ad_func_cntl = RREG32(MPLL_AD_FUNC_CNTL);
4099         si_pi->clock_registers.mpll_dq_func_cntl = RREG32(MPLL_DQ_FUNC_CNTL);
4100         si_pi->clock_registers.mpll_func_cntl = RREG32(MPLL_FUNC_CNTL);
4101         si_pi->clock_registers.mpll_func_cntl_1 = RREG32(MPLL_FUNC_CNTL_1);
4102         si_pi->clock_registers.mpll_func_cntl_2 = RREG32(MPLL_FUNC_CNTL_2);
4103         si_pi->clock_registers.mpll_ss1 = RREG32(MPLL_SS1);
4104         si_pi->clock_registers.mpll_ss2 = RREG32(MPLL_SS2);
4105 }
4106
4107 static void si_enable_thermal_protection(struct amdgpu_device *adev,
4108                                           bool enable)
4109 {
4110         if (enable)
4111                 WREG32_P(GENERAL_PWRMGT, 0, ~THERMAL_PROTECTION_DIS);
4112         else
4113                 WREG32_P(GENERAL_PWRMGT, THERMAL_PROTECTION_DIS, ~THERMAL_PROTECTION_DIS);
4114 }
4115
4116 static void si_enable_acpi_power_management(struct amdgpu_device *adev)
4117 {
4118         WREG32_P(GENERAL_PWRMGT, STATIC_PM_EN, ~STATIC_PM_EN);
4119 }
4120
4121 #if 0
4122 static int si_enter_ulp_state(struct amdgpu_device *adev)
4123 {
4124         WREG32(SMC_MESSAGE_0, PPSMC_MSG_SwitchToMinimumPower);
4125
4126         udelay(25000);
4127
4128         return 0;
4129 }
4130
4131 static int si_exit_ulp_state(struct amdgpu_device *adev)
4132 {
4133         int i;
4134
4135         WREG32(SMC_MESSAGE_0, PPSMC_MSG_ResumeFromMinimumPower);
4136
4137         udelay(7000);
4138
4139         for (i = 0; i < adev->usec_timeout; i++) {
4140                 if (RREG32(SMC_RESP_0) == 1)
4141                         break;
4142                 udelay(1000);
4143         }
4144
4145         return 0;
4146 }
4147 #endif
4148
4149 static int si_notify_smc_display_change(struct amdgpu_device *adev,
4150                                      bool has_display)
4151 {
4152         PPSMC_Msg msg = has_display ?
4153                 PPSMC_MSG_HasDisplay : PPSMC_MSG_NoDisplay;
4154
4155         return (amdgpu_si_send_msg_to_smc(adev, msg) == PPSMC_Result_OK) ?
4156                 0 : -EINVAL;
4157 }
4158
4159 static void si_program_response_times(struct amdgpu_device *adev)
4160 {
4161         u32 voltage_response_time, backbias_response_time, acpi_delay_time, vbi_time_out;
4162         u32 vddc_dly, acpi_dly, vbi_dly;
4163         u32 reference_clock;
4164
4165         si_write_smc_soft_register(adev, SI_SMC_SOFT_REGISTER_mvdd_chg_time, 1);
4166
4167         voltage_response_time = (u32)adev->pm.dpm.voltage_response_time;
4168         backbias_response_time = (u32)adev->pm.dpm.backbias_response_time;
4169
4170         if (voltage_response_time == 0)
4171                 voltage_response_time = 1000;
4172
4173         acpi_delay_time = 15000;
4174         vbi_time_out = 100000;
4175
4176         reference_clock = amdgpu_asic_get_xclk(adev);
4177
4178         vddc_dly = (voltage_response_time  * reference_clock) / 100;
4179         acpi_dly = (acpi_delay_time * reference_clock) / 100;
4180         vbi_dly  = (vbi_time_out * reference_clock) / 100;
4181
4182         si_write_smc_soft_register(adev, SI_SMC_SOFT_REGISTER_delay_vreg,  vddc_dly);
4183         si_write_smc_soft_register(adev, SI_SMC_SOFT_REGISTER_delay_acpi,  acpi_dly);
4184         si_write_smc_soft_register(adev, SI_SMC_SOFT_REGISTER_mclk_chg_timeout, vbi_dly);
4185         si_write_smc_soft_register(adev, SI_SMC_SOFT_REGISTER_mc_block_delay, 0xAA);
4186 }
4187
4188 static void si_program_ds_registers(struct amdgpu_device *adev)
4189 {
4190         struct evergreen_power_info *eg_pi = evergreen_get_pi(adev);
4191         u32 tmp;
4192
4193         /* DEEP_SLEEP_CLK_SEL field should be 0x10 on tahiti A0 */
4194         if (adev->asic_type == CHIP_TAHITI && adev->rev_id == 0x0)
4195                 tmp = 0x10;
4196         else
4197                 tmp = 0x1;
4198
4199         if (eg_pi->sclk_deep_sleep) {
4200                 WREG32_P(MISC_CLK_CNTL, DEEP_SLEEP_CLK_SEL(tmp), ~DEEP_SLEEP_CLK_SEL_MASK);
4201                 WREG32_P(CG_SPLL_AUTOSCALE_CNTL, AUTOSCALE_ON_SS_CLEAR,
4202                          ~AUTOSCALE_ON_SS_CLEAR);
4203         }
4204 }
4205
4206 static void si_program_display_gap(struct amdgpu_device *adev)
4207 {
4208         u32 tmp, pipe;
4209         int i;
4210
4211         tmp = RREG32(CG_DISPLAY_GAP_CNTL) & ~(DISP1_GAP_MASK | DISP2_GAP_MASK);
4212         if (adev->pm.dpm.new_active_crtc_count > 0)
4213                 tmp |= DISP1_GAP(R600_PM_DISPLAY_GAP_VBLANK_OR_WM);
4214         else
4215                 tmp |= DISP1_GAP(R600_PM_DISPLAY_GAP_IGNORE);
4216
4217         if (adev->pm.dpm.new_active_crtc_count > 1)
4218                 tmp |= DISP2_GAP(R600_PM_DISPLAY_GAP_VBLANK_OR_WM);
4219         else
4220                 tmp |= DISP2_GAP(R600_PM_DISPLAY_GAP_IGNORE);
4221
4222         WREG32(CG_DISPLAY_GAP_CNTL, tmp);
4223
4224         tmp = RREG32(DCCG_DISP_SLOW_SELECT_REG);
4225         pipe = (tmp & DCCG_DISP1_SLOW_SELECT_MASK) >> DCCG_DISP1_SLOW_SELECT_SHIFT;
4226
4227         if ((adev->pm.dpm.new_active_crtc_count > 0) &&
4228             (!(adev->pm.dpm.new_active_crtcs & (1 << pipe)))) {
4229                 /* find the first active crtc */
4230                 for (i = 0; i < adev->mode_info.num_crtc; i++) {
4231                         if (adev->pm.dpm.new_active_crtcs & (1 << i))
4232                                 break;
4233                 }
4234                 if (i == adev->mode_info.num_crtc)
4235                         pipe = 0;
4236                 else
4237                         pipe = i;
4238
4239                 tmp &= ~DCCG_DISP1_SLOW_SELECT_MASK;
4240                 tmp |= DCCG_DISP1_SLOW_SELECT(pipe);
4241                 WREG32(DCCG_DISP_SLOW_SELECT_REG, tmp);
4242         }
4243
4244         /* Setting this to false forces the performance state to low if the crtcs are disabled.
4245          * This can be a problem on PowerXpress systems or if you want to use the card
4246          * for offscreen rendering or compute if there are no crtcs enabled.
4247          */
4248         si_notify_smc_display_change(adev, adev->pm.dpm.new_active_crtc_count > 0);
4249 }
4250
4251 static void si_enable_spread_spectrum(struct amdgpu_device *adev, bool enable)
4252 {
4253         struct rv7xx_power_info *pi = rv770_get_pi(adev);
4254
4255         if (enable) {
4256                 if (pi->sclk_ss)
4257                         WREG32_P(GENERAL_PWRMGT, DYN_SPREAD_SPECTRUM_EN, ~DYN_SPREAD_SPECTRUM_EN);
4258         } else {
4259                 WREG32_P(CG_SPLL_SPREAD_SPECTRUM, 0, ~SSEN);
4260                 WREG32_P(GENERAL_PWRMGT, 0, ~DYN_SPREAD_SPECTRUM_EN);
4261         }
4262 }
4263
4264 static void si_setup_bsp(struct amdgpu_device *adev)
4265 {
4266         struct rv7xx_power_info *pi = rv770_get_pi(adev);
4267         u32 xclk = amdgpu_asic_get_xclk(adev);
4268
4269         r600_calculate_u_and_p(pi->asi,
4270                                xclk,
4271                                16,
4272                                &pi->bsp,
4273                                &pi->bsu);
4274
4275         r600_calculate_u_and_p(pi->pasi,
4276                                xclk,
4277                                16,
4278                                &pi->pbsp,
4279                                &pi->pbsu);
4280
4281
4282         pi->dsp = BSP(pi->bsp) | BSU(pi->bsu);
4283         pi->psp = BSP(pi->pbsp) | BSU(pi->pbsu);
4284
4285         WREG32(CG_BSP, pi->dsp);
4286 }
4287
4288 static void si_program_git(struct amdgpu_device *adev)
4289 {
4290         WREG32_P(CG_GIT, CG_GICST(R600_GICST_DFLT), ~CG_GICST_MASK);
4291 }
4292
4293 static void si_program_tp(struct amdgpu_device *adev)
4294 {
4295         int i;
4296         enum r600_td td = R600_TD_DFLT;
4297
4298         for (i = 0; i < R600_PM_NUMBER_OF_TC; i++)
4299                 WREG32(CG_FFCT_0 + i, (UTC_0(r600_utc[i]) | DTC_0(r600_dtc[i])));
4300
4301         if (td == R600_TD_AUTO)
4302                 WREG32_P(SCLK_PWRMGT_CNTL, 0, ~FIR_FORCE_TREND_SEL);
4303         else
4304                 WREG32_P(SCLK_PWRMGT_CNTL, FIR_FORCE_TREND_SEL, ~FIR_FORCE_TREND_SEL);
4305
4306         if (td == R600_TD_UP)
4307                 WREG32_P(SCLK_PWRMGT_CNTL, 0, ~FIR_TREND_MODE);
4308
4309         if (td == R600_TD_DOWN)
4310                 WREG32_P(SCLK_PWRMGT_CNTL, FIR_TREND_MODE, ~FIR_TREND_MODE);
4311 }
4312
4313 static void si_program_tpp(struct amdgpu_device *adev)
4314 {
4315         WREG32(CG_TPC, R600_TPC_DFLT);
4316 }
4317
4318 static void si_program_sstp(struct amdgpu_device *adev)
4319 {
4320         WREG32(CG_SSP, (SSTU(R600_SSTU_DFLT) | SST(R600_SST_DFLT)));
4321 }
4322
4323 static void si_enable_display_gap(struct amdgpu_device *adev)
4324 {
4325         u32 tmp = RREG32(CG_DISPLAY_GAP_CNTL);
4326
4327         tmp &= ~(DISP1_GAP_MASK | DISP2_GAP_MASK);
4328         tmp |= (DISP1_GAP(R600_PM_DISPLAY_GAP_IGNORE) |
4329                 DISP2_GAP(R600_PM_DISPLAY_GAP_IGNORE));
4330
4331         tmp &= ~(DISP1_GAP_MCHG_MASK | DISP2_GAP_MCHG_MASK);
4332         tmp |= (DISP1_GAP_MCHG(R600_PM_DISPLAY_GAP_VBLANK) |
4333                 DISP2_GAP_MCHG(R600_PM_DISPLAY_GAP_IGNORE));
4334         WREG32(CG_DISPLAY_GAP_CNTL, tmp);
4335 }
4336
4337 static void si_program_vc(struct amdgpu_device *adev)
4338 {
4339         struct rv7xx_power_info *pi = rv770_get_pi(adev);
4340
4341         WREG32(CG_FTV, pi->vrc);
4342 }
4343
4344 static void si_clear_vc(struct amdgpu_device *adev)
4345 {
4346         WREG32(CG_FTV, 0);
4347 }
4348
4349 static u8 si_get_ddr3_mclk_frequency_ratio(u32 memory_clock)
4350 {
4351         u8 mc_para_index;
4352
4353         if (memory_clock < 10000)
4354                 mc_para_index = 0;
4355         else if (memory_clock >= 80000)
4356                 mc_para_index = 0x0f;
4357         else
4358                 mc_para_index = (u8)((memory_clock - 10000) / 5000 + 1);
4359         return mc_para_index;
4360 }
4361
4362 static u8 si_get_mclk_frequency_ratio(u32 memory_clock, bool strobe_mode)
4363 {
4364         u8 mc_para_index;
4365
4366         if (strobe_mode) {
4367                 if (memory_clock < 12500)
4368                         mc_para_index = 0x00;
4369                 else if (memory_clock > 47500)
4370                         mc_para_index = 0x0f;
4371                 else
4372                         mc_para_index = (u8)((memory_clock - 10000) / 2500);
4373         } else {
4374                 if (memory_clock < 65000)
4375                         mc_para_index = 0x00;
4376                 else if (memory_clock > 135000)
4377                         mc_para_index = 0x0f;
4378                 else
4379                         mc_para_index = (u8)((memory_clock - 60000) / 5000);
4380         }
4381         return mc_para_index;
4382 }
4383
4384 static u8 si_get_strobe_mode_settings(struct amdgpu_device *adev, u32 mclk)
4385 {
4386         struct rv7xx_power_info *pi = rv770_get_pi(adev);
4387         bool strobe_mode = false;
4388         u8 result = 0;
4389
4390         if (mclk <= pi->mclk_strobe_mode_threshold)
4391                 strobe_mode = true;
4392
4393         if (adev->mc.vram_type == AMDGPU_VRAM_TYPE_GDDR5)
4394                 result = si_get_mclk_frequency_ratio(mclk, strobe_mode);
4395         else
4396                 result = si_get_ddr3_mclk_frequency_ratio(mclk);
4397
4398         if (strobe_mode)
4399                 result |= SISLANDS_SMC_STROBE_ENABLE;
4400
4401         return result;
4402 }
4403
4404 static int si_upload_firmware(struct amdgpu_device *adev)
4405 {
4406         struct si_power_info *si_pi = si_get_pi(adev);
4407
4408         amdgpu_si_reset_smc(adev);
4409         amdgpu_si_smc_clock(adev, false);
4410
4411         return amdgpu_si_load_smc_ucode(adev, si_pi->sram_end);
4412 }
4413
4414 static bool si_validate_phase_shedding_tables(struct amdgpu_device *adev,
4415                                               const struct atom_voltage_table *table,
4416                                               const struct amdgpu_phase_shedding_limits_table *limits)
4417 {
4418         u32 data, num_bits, num_levels;
4419
4420         if ((table == NULL) || (limits == NULL))
4421                 return false;
4422
4423         data = table->mask_low;
4424
4425         num_bits = hweight32(data);
4426
4427         if (num_bits == 0)
4428                 return false;
4429
4430         num_levels = (1 << num_bits);
4431
4432         if (table->count != num_levels)
4433                 return false;
4434
4435         if (limits->count != (num_levels - 1))
4436                 return false;
4437
4438         return true;
4439 }
4440
4441 static void si_trim_voltage_table_to_fit_state_table(struct amdgpu_device *adev,
4442                                               u32 max_voltage_steps,
4443                                               struct atom_voltage_table *voltage_table)
4444 {
4445         unsigned int i, diff;
4446
4447         if (voltage_table->count <= max_voltage_steps)
4448                 return;
4449
4450         diff = voltage_table->count - max_voltage_steps;
4451
4452         for (i= 0; i < max_voltage_steps; i++)
4453                 voltage_table->entries[i] = voltage_table->entries[i + diff];
4454
4455         voltage_table->count = max_voltage_steps;
4456 }
4457
4458 static int si_get_svi2_voltage_table(struct amdgpu_device *adev,
4459                                      struct amdgpu_clock_voltage_dependency_table *voltage_dependency_table,
4460                                      struct atom_voltage_table *voltage_table)
4461 {
4462         u32 i;
4463
4464         if (voltage_dependency_table == NULL)
4465                 return -EINVAL;
4466
4467         voltage_table->mask_low = 0;
4468         voltage_table->phase_delay = 0;
4469
4470         voltage_table->count = voltage_dependency_table->count;
4471         for (i = 0; i < voltage_table->count; i++) {
4472                 voltage_table->entries[i].value = voltage_dependency_table->entries[i].v;
4473                 voltage_table->entries[i].smio_low = 0;
4474         }
4475
4476         return 0;
4477 }
4478
4479 static int si_construct_voltage_tables(struct amdgpu_device *adev)
4480 {
4481         struct rv7xx_power_info *pi = rv770_get_pi(adev);
4482         struct evergreen_power_info *eg_pi = evergreen_get_pi(adev);
4483         struct si_power_info *si_pi = si_get_pi(adev);
4484         int ret;
4485
4486         if (pi->voltage_control) {
4487                 ret = amdgpu_atombios_get_voltage_table(adev, VOLTAGE_TYPE_VDDC,
4488                                                     VOLTAGE_OBJ_GPIO_LUT, &eg_pi->vddc_voltage_table);
4489                 if (ret)
4490                         return ret;
4491
4492                 if (eg_pi->vddc_voltage_table.count > SISLANDS_MAX_NO_VREG_STEPS)
4493                         si_trim_voltage_table_to_fit_state_table(adev,
4494                                                                  SISLANDS_MAX_NO_VREG_STEPS,
4495                                                                  &eg_pi->vddc_voltage_table);
4496         } else if (si_pi->voltage_control_svi2) {
4497                 ret = si_get_svi2_voltage_table(adev,
4498                                                 &adev->pm.dpm.dyn_state.vddc_dependency_on_mclk,
4499                                                 &eg_pi->vddc_voltage_table);
4500                 if (ret)
4501                         return ret;
4502         } else {
4503                 return -EINVAL;
4504         }
4505
4506         if (eg_pi->vddci_control) {
4507                 ret = amdgpu_atombios_get_voltage_table(adev, VOLTAGE_TYPE_VDDCI,
4508                                                     VOLTAGE_OBJ_GPIO_LUT, &eg_pi->vddci_voltage_table);
4509                 if (ret)
4510                         return ret;
4511
4512                 if (eg_pi->vddci_voltage_table.count > SISLANDS_MAX_NO_VREG_STEPS)
4513                         si_trim_voltage_table_to_fit_state_table(adev,
4514                                                                  SISLANDS_MAX_NO_VREG_STEPS,
4515                                                                  &eg_pi->vddci_voltage_table);
4516         }
4517         if (si_pi->vddci_control_svi2) {
4518                 ret = si_get_svi2_voltage_table(adev,
4519                                                 &adev->pm.dpm.dyn_state.vddci_dependency_on_mclk,
4520                                                 &eg_pi->vddci_voltage_table);
4521                 if (ret)
4522                         return ret;
4523         }
4524
4525         if (pi->mvdd_control) {
4526                 ret = amdgpu_atombios_get_voltage_table(adev, VOLTAGE_TYPE_MVDDC,
4527                                                     VOLTAGE_OBJ_GPIO_LUT, &si_pi->mvdd_voltage_table);
4528
4529                 if (ret) {
4530                         pi->mvdd_control = false;
4531                         return ret;
4532                 }
4533
4534                 if (si_pi->mvdd_voltage_table.count == 0) {
4535                         pi->mvdd_control = false;
4536                         return -EINVAL;
4537                 }
4538
4539                 if (si_pi->mvdd_voltage_table.count > SISLANDS_MAX_NO_VREG_STEPS)
4540                         si_trim_voltage_table_to_fit_state_table(adev,
4541                                                                  SISLANDS_MAX_NO_VREG_STEPS,
4542                                                                  &si_pi->mvdd_voltage_table);
4543         }
4544
4545         if (si_pi->vddc_phase_shed_control) {
4546                 ret = amdgpu_atombios_get_voltage_table(adev, VOLTAGE_TYPE_VDDC,
4547                                                     VOLTAGE_OBJ_PHASE_LUT, &si_pi->vddc_phase_shed_table);
4548                 if (ret)
4549                         si_pi->vddc_phase_shed_control = false;
4550
4551                 if ((si_pi->vddc_phase_shed_table.count == 0) ||
4552                     (si_pi->vddc_phase_shed_table.count > SISLANDS_MAX_NO_VREG_STEPS))
4553                         si_pi->vddc_phase_shed_control = false;
4554         }
4555
4556         return 0;
4557 }
4558
4559 static void si_populate_smc_voltage_table(struct amdgpu_device *adev,
4560                                           const struct atom_voltage_table *voltage_table,
4561                                           SISLANDS_SMC_STATETABLE *table)
4562 {
4563         unsigned int i;
4564
4565         for (i = 0; i < voltage_table->count; i++)
4566                 table->lowSMIO[i] |= cpu_to_be32(voltage_table->entries[i].smio_low);
4567 }
4568
4569 static int si_populate_smc_voltage_tables(struct amdgpu_device *adev,
4570                                           SISLANDS_SMC_STATETABLE *table)
4571 {
4572         struct rv7xx_power_info *pi = rv770_get_pi(adev);
4573         struct evergreen_power_info *eg_pi = evergreen_get_pi(adev);
4574         struct si_power_info *si_pi = si_get_pi(adev);
4575         u8 i;
4576
4577         if (si_pi->voltage_control_svi2) {
4578                 si_write_smc_soft_register(adev, SI_SMC_SOFT_REGISTER_svi_rework_gpio_id_svc,
4579                         si_pi->svc_gpio_id);
4580                 si_write_smc_soft_register(adev, SI_SMC_SOFT_REGISTER_svi_rework_gpio_id_svd,
4581                         si_pi->svd_gpio_id);
4582                 si_write_smc_soft_register(adev, SI_SMC_SOFT_REGISTER_svi_rework_plat_type,
4583                                            2);
4584         } else {
4585                 if (eg_pi->vddc_voltage_table.count) {
4586                         si_populate_smc_voltage_table(adev, &eg_pi->vddc_voltage_table, table);
4587                         table->voltageMaskTable.lowMask[SISLANDS_SMC_VOLTAGEMASK_VDDC] =
4588                                 cpu_to_be32(eg_pi->vddc_voltage_table.mask_low);
4589
4590                         for (i = 0; i < eg_pi->vddc_voltage_table.count; i++) {
4591                                 if (pi->max_vddc_in_table <= eg_pi->vddc_voltage_table.entries[i].value) {
4592                                         table->maxVDDCIndexInPPTable = i;
4593                                         break;
4594                                 }
4595                         }
4596                 }
4597
4598                 if (eg_pi->vddci_voltage_table.count) {
4599                         si_populate_smc_voltage_table(adev, &eg_pi->vddci_voltage_table, table);
4600
4601                         table->voltageMaskTable.lowMask[SISLANDS_SMC_VOLTAGEMASK_VDDCI] =
4602                                 cpu_to_be32(eg_pi->vddci_voltage_table.mask_low);
4603                 }
4604
4605
4606                 if (si_pi->mvdd_voltage_table.count) {
4607                         si_populate_smc_voltage_table(adev, &si_pi->mvdd_voltage_table, table);
4608
4609                         table->voltageMaskTable.lowMask[SISLANDS_SMC_VOLTAGEMASK_MVDD] =
4610                                 cpu_to_be32(si_pi->mvdd_voltage_table.mask_low);
4611                 }
4612
4613                 if (si_pi->vddc_phase_shed_control) {
4614                         if (si_validate_phase_shedding_tables(adev, &si_pi->vddc_phase_shed_table,
4615                                                               &adev->pm.dpm.dyn_state.phase_shedding_limits_table)) {
4616                                 si_populate_smc_voltage_table(adev, &si_pi->vddc_phase_shed_table, table);
4617
4618                                 table->phaseMaskTable.lowMask[SISLANDS_SMC_VOLTAGEMASK_VDDC_PHASE_SHEDDING] =
4619                                         cpu_to_be32(si_pi->vddc_phase_shed_table.mask_low);
4620
4621                                 si_write_smc_soft_register(adev, SI_SMC_SOFT_REGISTER_phase_shedding_delay,
4622                                                            (u32)si_pi->vddc_phase_shed_table.phase_delay);
4623                         } else {
4624                                 si_pi->vddc_phase_shed_control = false;
4625                         }
4626                 }
4627         }
4628
4629         return 0;
4630 }
4631
4632 static int si_populate_voltage_value(struct amdgpu_device *adev,
4633                                      const struct atom_voltage_table *table,
4634                                      u16 value, SISLANDS_SMC_VOLTAGE_VALUE *voltage)
4635 {
4636         unsigned int i;
4637
4638         for (i = 0; i < table->count; i++) {
4639                 if (value <= table->entries[i].value) {
4640                         voltage->index = (u8)i;
4641                         voltage->value = cpu_to_be16(table->entries[i].value);
4642                         break;
4643                 }
4644         }
4645
4646         if (i >= table->count)
4647                 return -EINVAL;
4648
4649         return 0;
4650 }
4651
4652 static int si_populate_mvdd_value(struct amdgpu_device *adev, u32 mclk,
4653                                   SISLANDS_SMC_VOLTAGE_VALUE *voltage)
4654 {
4655         struct rv7xx_power_info *pi = rv770_get_pi(adev);
4656         struct si_power_info *si_pi = si_get_pi(adev);
4657
4658         if (pi->mvdd_control) {
4659                 if (mclk <= pi->mvdd_split_frequency)
4660                         voltage->index = 0;
4661                 else
4662                         voltage->index = (u8)(si_pi->mvdd_voltage_table.count) - 1;
4663
4664                 voltage->value = cpu_to_be16(si_pi->mvdd_voltage_table.entries[voltage->index].value);
4665         }
4666         return 0;
4667 }
4668
4669 static int si_get_std_voltage_value(struct amdgpu_device *adev,
4670                                     SISLANDS_SMC_VOLTAGE_VALUE *voltage,
4671                                     u16 *std_voltage)
4672 {
4673         u16 v_index;
4674         bool voltage_found = false;
4675         *std_voltage = be16_to_cpu(voltage->value);
4676
4677         if (adev->pm.dpm.dyn_state.cac_leakage_table.entries) {
4678                 if (adev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_NEW_CAC_VOLTAGE) {
4679                         if (adev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries == NULL)
4680                                 return -EINVAL;
4681
4682                         for (v_index = 0; (u32)v_index < adev->pm.dpm.dyn_state.vddc_dependency_on_sclk.count; v_index++) {
4683                                 if (be16_to_cpu(voltage->value) ==
4684                                     (u16)adev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[v_index].v) {
4685                                         voltage_found = true;
4686                                         if ((u32)v_index < adev->pm.dpm.dyn_state.cac_leakage_table.count)
4687                                                 *std_voltage =
4688                                                         adev->pm.dpm.dyn_state.cac_leakage_table.entries[v_index].vddc;
4689                                         else
4690                                                 *std_voltage =
4691                                                         adev->pm.dpm.dyn_state.cac_leakage_table.entries[adev->pm.dpm.dyn_state.cac_leakage_table.count-1].vddc;
4692                                         break;
4693                                 }
4694                         }
4695
4696                         if (!voltage_found) {
4697                                 for (v_index = 0; (u32)v_index < adev->pm.dpm.dyn_state.vddc_dependency_on_sclk.count; v_index++) {
4698                                         if (be16_to_cpu(voltage->value) <=
4699                                             (u16)adev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[v_index].v) {
4700                                                 voltage_found = true;
4701                                                 if ((u32)v_index < adev->pm.dpm.dyn_state.cac_leakage_table.count)
4702                                                         *std_voltage =
4703                                                                 adev->pm.dpm.dyn_state.cac_leakage_table.entries[v_index].vddc;
4704                                                 else
4705                                                         *std_voltage =
4706                                                                 adev->pm.dpm.dyn_state.cac_leakage_table.entries[adev->pm.dpm.dyn_state.cac_leakage_table.count-1].vddc;
4707                                                 break;
4708                                         }
4709                                 }
4710                         }
4711                 } else {
4712                         if ((u32)voltage->index < adev->pm.dpm.dyn_state.cac_leakage_table.count)
4713                                 *std_voltage = adev->pm.dpm.dyn_state.cac_leakage_table.entries[voltage->index].vddc;
4714                 }
4715         }
4716
4717         return 0;
4718 }
4719
4720 static int si_populate_std_voltage_value(struct amdgpu_device *adev,
4721                                          u16 value, u8 index,
4722                                          SISLANDS_SMC_VOLTAGE_VALUE *voltage)
4723 {
4724         voltage->index = index;
4725         voltage->value = cpu_to_be16(value);
4726
4727         return 0;
4728 }
4729
4730 static int si_populate_phase_shedding_value(struct amdgpu_device *adev,
4731                                             const struct amdgpu_phase_shedding_limits_table *limits,
4732                                             u16 voltage, u32 sclk, u32 mclk,
4733                                             SISLANDS_SMC_VOLTAGE_VALUE *smc_voltage)
4734 {
4735         unsigned int i;
4736
4737         for (i = 0; i < limits->count; i++) {
4738                 if ((voltage <= limits->entries[i].voltage) &&
4739                     (sclk <= limits->entries[i].sclk) &&
4740                     (mclk <= limits->entries[i].mclk))
4741                         break;
4742         }
4743
4744         smc_voltage->phase_settings = (u8)i;
4745
4746         return 0;
4747 }
4748
4749 static int si_init_arb_table_index(struct amdgpu_device *adev)
4750 {
4751         struct si_power_info *si_pi = si_get_pi(adev);
4752         u32 tmp;
4753         int ret;
4754
4755         ret = amdgpu_si_read_smc_sram_dword(adev, si_pi->arb_table_start,
4756                                             &tmp, si_pi->sram_end);
4757         if (ret)
4758                 return ret;
4759
4760         tmp &= 0x00FFFFFF;
4761         tmp |= MC_CG_ARB_FREQ_F1 << 24;
4762
4763         return amdgpu_si_write_smc_sram_dword(adev, si_pi->arb_table_start,
4764                                               tmp, si_pi->sram_end);
4765 }
4766
4767 static int si_initial_switch_from_arb_f0_to_f1(struct amdgpu_device *adev)
4768 {
4769         return ni_copy_and_switch_arb_sets(adev, MC_CG_ARB_FREQ_F0, MC_CG_ARB_FREQ_F1);
4770 }
4771
4772 static int si_reset_to_default(struct amdgpu_device *adev)
4773 {
4774         return (amdgpu_si_send_msg_to_smc(adev, PPSMC_MSG_ResetToDefaults) == PPSMC_Result_OK) ?
4775                 0 : -EINVAL;
4776 }
4777
4778 static int si_force_switch_to_arb_f0(struct amdgpu_device *adev)
4779 {
4780         struct si_power_info *si_pi = si_get_pi(adev);
4781         u32 tmp;
4782         int ret;
4783
4784         ret = amdgpu_si_read_smc_sram_dword(adev, si_pi->arb_table_start,
4785                                             &tmp, si_pi->sram_end);
4786         if (ret)
4787                 return ret;
4788
4789         tmp = (tmp >> 24) & 0xff;
4790
4791         if (tmp == MC_CG_ARB_FREQ_F0)
4792                 return 0;
4793
4794         return ni_copy_and_switch_arb_sets(adev, tmp, MC_CG_ARB_FREQ_F0);
4795 }
4796
4797 static u32 si_calculate_memory_refresh_rate(struct amdgpu_device *adev,
4798                                             u32 engine_clock)
4799 {
4800         u32 dram_rows;
4801         u32 dram_refresh_rate;
4802         u32 mc_arb_rfsh_rate;
4803         u32 tmp = (RREG32(MC_ARB_RAMCFG) & NOOFROWS_MASK) >> NOOFROWS_SHIFT;
4804
4805         if (tmp >= 4)
4806                 dram_rows = 16384;
4807         else
4808                 dram_rows = 1 << (tmp + 10);
4809
4810         dram_refresh_rate = 1 << ((RREG32(MC_SEQ_MISC0) & 0x3) + 3);
4811         mc_arb_rfsh_rate = ((engine_clock * 10) * dram_refresh_rate / dram_rows - 32) / 64;
4812
4813         return mc_arb_rfsh_rate;
4814 }
4815
4816 static int si_populate_memory_timing_parameters(struct amdgpu_device *adev,
4817                                                 struct rv7xx_pl *pl,
4818                                                 SMC_SIslands_MCArbDramTimingRegisterSet *arb_regs)
4819 {
4820         u32 dram_timing;
4821         u32 dram_timing2;
4822         u32 burst_time;
4823
4824         arb_regs->mc_arb_rfsh_rate =
4825                 (u8)si_calculate_memory_refresh_rate(adev, pl->sclk);
4826
4827         amdgpu_atombios_set_engine_dram_timings(adev,
4828                                             pl->sclk,
4829                                             pl->mclk);
4830
4831         dram_timing  = RREG32(MC_ARB_DRAM_TIMING);
4832         dram_timing2 = RREG32(MC_ARB_DRAM_TIMING2);
4833         burst_time = RREG32(MC_ARB_BURST_TIME) & STATE0_MASK;
4834
4835         arb_regs->mc_arb_dram_timing  = cpu_to_be32(dram_timing);
4836         arb_regs->mc_arb_dram_timing2 = cpu_to_be32(dram_timing2);
4837         arb_regs->mc_arb_burst_time = (u8)burst_time;
4838
4839         return 0;
4840 }
4841
4842 static int si_do_program_memory_timing_parameters(struct amdgpu_device *adev,
4843                                                   struct amdgpu_ps *amdgpu_state,
4844                                                   unsigned int first_arb_set)
4845 {
4846         struct si_power_info *si_pi = si_get_pi(adev);
4847         struct  si_ps *state = si_get_ps(amdgpu_state);
4848         SMC_SIslands_MCArbDramTimingRegisterSet arb_regs = { 0 };
4849         int i, ret = 0;
4850
4851         for (i = 0; i < state->performance_level_count; i++) {
4852                 ret = si_populate_memory_timing_parameters(adev, &state->performance_levels[i], &arb_regs);
4853                 if (ret)
4854                         break;
4855                 ret = amdgpu_si_copy_bytes_to_smc(adev,
4856                                                   si_pi->arb_table_start +
4857                                                   offsetof(SMC_SIslands_MCArbDramTimingRegisters, data) +
4858                                                   sizeof(SMC_SIslands_MCArbDramTimingRegisterSet) * (first_arb_set + i),
4859                                                   (u8 *)&arb_regs,
4860                                                   sizeof(SMC_SIslands_MCArbDramTimingRegisterSet),
4861                                                   si_pi->sram_end);
4862                 if (ret)
4863                         break;
4864         }
4865
4866         return ret;
4867 }
4868
4869 static int si_program_memory_timing_parameters(struct amdgpu_device *adev,
4870                                                struct amdgpu_ps *amdgpu_new_state)
4871 {
4872         return si_do_program_memory_timing_parameters(adev, amdgpu_new_state,
4873                                                       SISLANDS_DRIVER_STATE_ARB_INDEX);
4874 }
4875
4876 static int si_populate_initial_mvdd_value(struct amdgpu_device *adev,
4877                                           struct SISLANDS_SMC_VOLTAGE_VALUE *voltage)
4878 {
4879         struct rv7xx_power_info *pi = rv770_get_pi(adev);
4880         struct si_power_info *si_pi = si_get_pi(adev);
4881
4882         if (pi->mvdd_control)
4883                 return si_populate_voltage_value(adev, &si_pi->mvdd_voltage_table,
4884                                                  si_pi->mvdd_bootup_value, voltage);
4885
4886         return 0;
4887 }
4888
4889 static int si_populate_smc_initial_state(struct amdgpu_device *adev,
4890                                          struct amdgpu_ps *amdgpu_initial_state,
4891                                          SISLANDS_SMC_STATETABLE *table)
4892 {
4893         struct  si_ps *initial_state = si_get_ps(amdgpu_initial_state);
4894         struct rv7xx_power_info *pi = rv770_get_pi(adev);
4895         struct evergreen_power_info *eg_pi = evergreen_get_pi(adev);
4896         struct si_power_info *si_pi = si_get_pi(adev);
4897         u32 reg;
4898         int ret;
4899
4900         table->initialState.levels[0].mclk.vDLL_CNTL =
4901                 cpu_to_be32(si_pi->clock_registers.dll_cntl);
4902         table->initialState.levels[0].mclk.vMCLK_PWRMGT_CNTL =
4903                 cpu_to_be32(si_pi->clock_registers.mclk_pwrmgt_cntl);
4904         table->initialState.levels[0].mclk.vMPLL_AD_FUNC_CNTL =
4905                 cpu_to_be32(si_pi->clock_registers.mpll_ad_func_cntl);
4906         table->initialState.levels[0].mclk.vMPLL_DQ_FUNC_CNTL =
4907                 cpu_to_be32(si_pi->clock_registers.mpll_dq_func_cntl);
4908         table->initialState.levels[0].mclk.vMPLL_FUNC_CNTL =
4909                 cpu_to_be32(si_pi->clock_registers.mpll_func_cntl);
4910         table->initialState.levels[0].mclk.vMPLL_FUNC_CNTL_1 =
4911                 cpu_to_be32(si_pi->clock_registers.mpll_func_cntl_1);
4912         table->initialState.levels[0].mclk.vMPLL_FUNC_CNTL_2 =
4913                 cpu_to_be32(si_pi->clock_registers.mpll_func_cntl_2);
4914         table->initialState.levels[0].mclk.vMPLL_SS =
4915                 cpu_to_be32(si_pi->clock_registers.mpll_ss1);
4916         table->initialState.levels[0].mclk.vMPLL_SS2 =
4917                 cpu_to_be32(si_pi->clock_registers.mpll_ss2);
4918
4919         table->initialState.levels[0].mclk.mclk_value =
4920                 cpu_to_be32(initial_state->performance_levels[0].mclk);
4921
4922         table->initialState.levels[0].sclk.vCG_SPLL_FUNC_CNTL =
4923                 cpu_to_be32(si_pi->clock_registers.cg_spll_func_cntl);
4924         table->initialState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_2 =
4925                 cpu_to_be32(si_pi->clock_registers.cg_spll_func_cntl_2);
4926         table->initialState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_3 =
4927                 cpu_to_be32(si_pi->clock_registers.cg_spll_func_cntl_3);
4928         table->initialState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_4 =
4929                 cpu_to_be32(si_pi->clock_registers.cg_spll_func_cntl_4);
4930         table->initialState.levels[0].sclk.vCG_SPLL_SPREAD_SPECTRUM =
4931                 cpu_to_be32(si_pi->clock_registers.cg_spll_spread_spectrum);
4932         table->initialState.levels[0].sclk.vCG_SPLL_SPREAD_SPECTRUM_2  =
4933                 cpu_to_be32(si_pi->clock_registers.cg_spll_spread_spectrum_2);
4934
4935         table->initialState.levels[0].sclk.sclk_value =
4936                 cpu_to_be32(initial_state->performance_levels[0].sclk);
4937
4938         table->initialState.levels[0].arbRefreshState =
4939                 SISLANDS_INITIAL_STATE_ARB_INDEX;
4940
4941         table->initialState.levels[0].ACIndex = 0;
4942
4943         ret = si_populate_voltage_value(adev, &eg_pi->vddc_voltage_table,
4944                                         initial_state->performance_levels[0].vddc,
4945                                         &table->initialState.levels[0].vddc);
4946
4947         if (!ret) {
4948                 u16 std_vddc;
4949
4950                 ret = si_get_std_voltage_value(adev,
4951                                                &table->initialState.levels[0].vddc,
4952                                                &std_vddc);
4953                 if (!ret)
4954                         si_populate_std_voltage_value(adev, std_vddc,
4955                                                       table->initialState.levels[0].vddc.index,
4956                                                       &table->initialState.levels[0].std_vddc);
4957         }
4958
4959         if (eg_pi->vddci_control)
4960                 si_populate_voltage_value(adev,
4961                                           &eg_pi->vddci_voltage_table,
4962                                           initial_state->performance_levels[0].vddci,
4963                                           &table->initialState.levels[0].vddci);
4964
4965         if (si_pi->vddc_phase_shed_control)
4966                 si_populate_phase_shedding_value(adev,
4967                                                  &adev->pm.dpm.dyn_state.phase_shedding_limits_table,
4968                                                  initial_state->performance_levels[0].vddc,
4969                                                  initial_state->performance_levels[0].sclk,
4970                                                  initial_state->performance_levels[0].mclk,
4971                                                  &table->initialState.levels[0].vddc);
4972
4973         si_populate_initial_mvdd_value(adev, &table->initialState.levels[0].mvdd);
4974
4975         reg = CG_R(0xffff) | CG_L(0);
4976         table->initialState.levels[0].aT = cpu_to_be32(reg);
4977         table->initialState.levels[0].bSP = cpu_to_be32(pi->dsp);
4978         table->initialState.levels[0].gen2PCIE = (u8)si_pi->boot_pcie_gen;
4979
4980         if (adev->mc.vram_type == AMDGPU_VRAM_TYPE_GDDR5) {
4981                 table->initialState.levels[0].strobeMode =
4982                         si_get_strobe_mode_settings(adev,
4983                                                     initial_state->performance_levels[0].mclk);
4984
4985                 if (initial_state->performance_levels[0].mclk > pi->mclk_edc_enable_threshold)
4986                         table->initialState.levels[0].mcFlags = SISLANDS_SMC_MC_EDC_RD_FLAG | SISLANDS_SMC_MC_EDC_WR_FLAG;
4987                 else
4988                         table->initialState.levels[0].mcFlags =  0;
4989         }
4990
4991         table->initialState.levelCount = 1;
4992
4993         table->initialState.flags |= PPSMC_SWSTATE_FLAG_DC;
4994
4995         table->initialState.levels[0].dpm2.MaxPS = 0;
4996         table->initialState.levels[0].dpm2.NearTDPDec = 0;
4997         table->initialState.levels[0].dpm2.AboveSafeInc = 0;
4998         table->initialState.levels[0].dpm2.BelowSafeInc = 0;
4999         table->initialState.levels[0].dpm2.PwrEfficiencyRatio = 0;
5000
5001         reg = MIN_POWER_MASK | MAX_POWER_MASK;
5002         table->initialState.levels[0].SQPowerThrottle = cpu_to_be32(reg);
5003
5004         reg = MAX_POWER_DELTA_MASK | STI_SIZE_MASK | LTI_RATIO_MASK;
5005         table->initialState.levels[0].SQPowerThrottle_2 = cpu_to_be32(reg);
5006
5007         return 0;
5008 }
5009
5010 static int si_populate_smc_acpi_state(struct amdgpu_device *adev,
5011                                       SISLANDS_SMC_STATETABLE *table)
5012 {
5013         struct rv7xx_power_info *pi = rv770_get_pi(adev);
5014         struct evergreen_power_info *eg_pi = evergreen_get_pi(adev);
5015         struct si_power_info *si_pi = si_get_pi(adev);
5016         u32 spll_func_cntl = si_pi->clock_registers.cg_spll_func_cntl;
5017         u32 spll_func_cntl_2 = si_pi->clock_registers.cg_spll_func_cntl_2;
5018         u32 spll_func_cntl_3 = si_pi->clock_registers.cg_spll_func_cntl_3;
5019         u32 spll_func_cntl_4 = si_pi->clock_registers.cg_spll_func_cntl_4;
5020         u32 dll_cntl = si_pi->clock_registers.dll_cntl;
5021         u32 mclk_pwrmgt_cntl = si_pi->clock_registers.mclk_pwrmgt_cntl;
5022         u32 mpll_ad_func_cntl = si_pi->clock_registers.mpll_ad_func_cntl;
5023         u32 mpll_dq_func_cntl = si_pi->clock_registers.mpll_dq_func_cntl;
5024         u32 mpll_func_cntl = si_pi->clock_registers.mpll_func_cntl;
5025         u32 mpll_func_cntl_1 = si_pi->clock_registers.mpll_func_cntl_1;
5026         u32 mpll_func_cntl_2 = si_pi->clock_registers.mpll_func_cntl_2;
5027         u32 reg;
5028         int ret;
5029
5030         table->ACPIState = table->initialState;
5031
5032         table->ACPIState.flags &= ~PPSMC_SWSTATE_FLAG_DC;
5033
5034         if (pi->acpi_vddc) {
5035                 ret = si_populate_voltage_value(adev, &eg_pi->vddc_voltage_table,
5036                                                 pi->acpi_vddc, &table->ACPIState.levels[0].vddc);
5037                 if (!ret) {
5038                         u16 std_vddc;
5039
5040                         ret = si_get_std_voltage_value(adev,
5041                                                        &table->ACPIState.levels[0].vddc, &std_vddc);
5042                         if (!ret)
5043                                 si_populate_std_voltage_value(adev, std_vddc,
5044                                                               table->ACPIState.levels[0].vddc.index,
5045                                                               &table->ACPIState.levels[0].std_vddc);
5046                 }
5047                 table->ACPIState.levels[0].gen2PCIE = si_pi->acpi_pcie_gen;
5048
5049                 if (si_pi->vddc_phase_shed_control) {
5050                         si_populate_phase_shedding_value(adev,
5051                                                          &adev->pm.dpm.dyn_state.phase_shedding_limits_table,
5052                                                          pi->acpi_vddc,
5053                                                          0,
5054                                                          0,
5055                                                          &table->ACPIState.levels[0].vddc);
5056                 }
5057         } else {
5058                 ret = si_populate_voltage_value(adev, &eg_pi->vddc_voltage_table,
5059                                                 pi->min_vddc_in_table, &table->ACPIState.levels[0].vddc);
5060                 if (!ret) {
5061                         u16 std_vddc;
5062
5063                         ret = si_get_std_voltage_value(adev,
5064                                                        &table->ACPIState.levels[0].vddc, &std_vddc);
5065
5066                         if (!ret)
5067                                 si_populate_std_voltage_value(adev, std_vddc,
5068                                                               table->ACPIState.levels[0].vddc.index,
5069                                                               &table->ACPIState.levels[0].std_vddc);
5070                 }
5071                 table->ACPIState.levels[0].gen2PCIE = (u8)r600_get_pcie_gen_support(adev,
5072                                                                                     si_pi->sys_pcie_mask,
5073                                                                                     si_pi->boot_pcie_gen,
5074                                                                                     AMDGPU_PCIE_GEN1);
5075
5076                 if (si_pi->vddc_phase_shed_control)
5077                         si_populate_phase_shedding_value(adev,
5078                                                          &adev->pm.dpm.dyn_state.phase_shedding_limits_table,
5079                                                          pi->min_vddc_in_table,
5080                                                          0,
5081                                                          0,
5082                                                          &table->ACPIState.levels[0].vddc);
5083         }
5084
5085         if (pi->acpi_vddc) {
5086                 if (eg_pi->acpi_vddci)
5087                         si_populate_voltage_value(adev, &eg_pi->vddci_voltage_table,
5088                                                   eg_pi->acpi_vddci,
5089                                                   &table->ACPIState.levels[0].vddci);
5090         }
5091
5092         mclk_pwrmgt_cntl |= MRDCK0_RESET | MRDCK1_RESET;
5093         mclk_pwrmgt_cntl &= ~(MRDCK0_PDNB | MRDCK1_PDNB);
5094
5095         dll_cntl &= ~(MRDCK0_BYPASS | MRDCK1_BYPASS);
5096
5097         spll_func_cntl_2 &= ~SCLK_MUX_SEL_MASK;
5098         spll_func_cntl_2 |= SCLK_MUX_SEL(4);
5099
5100         table->ACPIState.levels[0].mclk.vDLL_CNTL =
5101                 cpu_to_be32(dll_cntl);
5102         table->ACPIState.levels[0].mclk.vMCLK_PWRMGT_CNTL =
5103                 cpu_to_be32(mclk_pwrmgt_cntl);
5104         table->ACPIState.levels[0].mclk.vMPLL_AD_FUNC_CNTL =
5105                 cpu_to_be32(mpll_ad_func_cntl);
5106         table->ACPIState.levels[0].mclk.vMPLL_DQ_FUNC_CNTL =
5107                 cpu_to_be32(mpll_dq_func_cntl);
5108         table->ACPIState.levels[0].mclk.vMPLL_FUNC_CNTL =
5109                 cpu_to_be32(mpll_func_cntl);
5110         table->ACPIState.levels[0].mclk.vMPLL_FUNC_CNTL_1 =
5111                 cpu_to_be32(mpll_func_cntl_1);
5112         table->ACPIState.levels[0].mclk.vMPLL_FUNC_CNTL_2 =
5113                 cpu_to_be32(mpll_func_cntl_2);
5114         table->ACPIState.levels[0].mclk.vMPLL_SS =
5115                 cpu_to_be32(si_pi->clock_registers.mpll_ss1);
5116         table->ACPIState.levels[0].mclk.vMPLL_SS2 =
5117                 cpu_to_be32(si_pi->clock_registers.mpll_ss2);
5118
5119         table->ACPIState.levels[0].sclk.vCG_SPLL_FUNC_CNTL =
5120                 cpu_to_be32(spll_func_cntl);
5121         table->ACPIState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_2 =
5122                 cpu_to_be32(spll_func_cntl_2);
5123         table->ACPIState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_3 =
5124                 cpu_to_be32(spll_func_cntl_3);
5125         table->ACPIState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_4 =
5126                 cpu_to_be32(spll_func_cntl_4);
5127
5128         table->ACPIState.levels[0].mclk.mclk_value = 0;
5129         table->ACPIState.levels[0].sclk.sclk_value = 0;
5130
5131         si_populate_mvdd_value(adev, 0, &table->ACPIState.levels[0].mvdd);
5132
5133         if (eg_pi->dynamic_ac_timing)
5134                 table->ACPIState.levels[0].ACIndex = 0;
5135
5136         table->ACPIState.levels[0].dpm2.MaxPS = 0;
5137         table->ACPIState.levels[0].dpm2.NearTDPDec = 0;
5138         table->ACPIState.levels[0].dpm2.AboveSafeInc = 0;
5139         table->ACPIState.levels[0].dpm2.BelowSafeInc = 0;
5140         table->ACPIState.levels[0].dpm2.PwrEfficiencyRatio = 0;
5141
5142         reg = MIN_POWER_MASK | MAX_POWER_MASK;
5143         table->ACPIState.levels[0].SQPowerThrottle = cpu_to_be32(reg);
5144
5145         reg = MAX_POWER_DELTA_MASK | STI_SIZE_MASK | LTI_RATIO_MASK;
5146         table->ACPIState.levels[0].SQPowerThrottle_2 = cpu_to_be32(reg);
5147
5148         return 0;
5149 }
5150
5151 static int si_populate_ulv_state(struct amdgpu_device *adev,
5152                                  SISLANDS_SMC_SWSTATE *state)
5153 {
5154         struct evergreen_power_info *eg_pi = evergreen_get_pi(adev);
5155         struct si_power_info *si_pi = si_get_pi(adev);
5156         struct si_ulv_param *ulv = &si_pi->ulv;
5157         u32 sclk_in_sr = 1350; /* ??? */
5158         int ret;
5159
5160         ret = si_convert_power_level_to_smc(adev, &ulv->pl,
5161                                             &state->levels[0]);
5162         if (!ret) {
5163                 if (eg_pi->sclk_deep_sleep) {
5164                         if (sclk_in_sr <= SCLK_MIN_DEEPSLEEP_FREQ)
5165                                 state->levels[0].stateFlags |= PPSMC_STATEFLAG_DEEPSLEEP_BYPASS;
5166                         else
5167                                 state->levels[0].stateFlags |= PPSMC_STATEFLAG_DEEPSLEEP_THROTTLE;
5168                 }
5169                 if (ulv->one_pcie_lane_in_ulv)
5170                         state->flags |= PPSMC_SWSTATE_FLAG_PCIE_X1;
5171                 state->levels[0].arbRefreshState = (u8)(SISLANDS_ULV_STATE_ARB_INDEX);
5172                 state->levels[0].ACIndex = 1;
5173                 state->levels[0].std_vddc = state->levels[0].vddc;
5174                 state->levelCount = 1;
5175
5176                 state->flags |= PPSMC_SWSTATE_FLAG_DC;
5177         }
5178
5179         return ret;
5180 }
5181
5182 static int si_program_ulv_memory_timing_parameters(struct amdgpu_device *adev)
5183 {
5184         struct si_power_info *si_pi = si_get_pi(adev);
5185         struct si_ulv_param *ulv = &si_pi->ulv;
5186         SMC_SIslands_MCArbDramTimingRegisterSet arb_regs = { 0 };
5187         int ret;
5188
5189         ret = si_populate_memory_timing_parameters(adev, &ulv->pl,
5190                                                    &arb_regs);
5191         if (ret)
5192                 return ret;
5193
5194         si_write_smc_soft_register(adev, SI_SMC_SOFT_REGISTER_ulv_volt_change_delay,
5195                                    ulv->volt_change_delay);
5196
5197         ret = amdgpu_si_copy_bytes_to_smc(adev,
5198                                           si_pi->arb_table_start +
5199                                           offsetof(SMC_SIslands_MCArbDramTimingRegisters, data) +
5200                                           sizeof(SMC_SIslands_MCArbDramTimingRegisterSet) * SISLANDS_ULV_STATE_ARB_INDEX,
5201                                           (u8 *)&arb_regs,
5202                                           sizeof(SMC_SIslands_MCArbDramTimingRegisterSet),
5203                                           si_pi->sram_end);
5204
5205         return ret;
5206 }
5207
5208 static void si_get_mvdd_configuration(struct amdgpu_device *adev)
5209 {
5210         struct rv7xx_power_info *pi = rv770_get_pi(adev);
5211
5212         pi->mvdd_split_frequency = 30000;
5213 }
5214
5215 static int si_init_smc_table(struct amdgpu_device *adev)
5216 {
5217         struct si_power_info *si_pi = si_get_pi(adev);
5218         struct amdgpu_ps *amdgpu_boot_state = adev->pm.dpm.boot_ps;
5219         const struct si_ulv_param *ulv = &si_pi->ulv;
5220         SISLANDS_SMC_STATETABLE  *table = &si_pi->smc_statetable;
5221         int ret;
5222         u32 lane_width;
5223         u32 vr_hot_gpio;
5224
5225         si_populate_smc_voltage_tables(adev, table);
5226
5227         switch (adev->pm.int_thermal_type) {
5228         case THERMAL_TYPE_SI:
5229         case THERMAL_TYPE_EMC2103_WITH_INTERNAL:
5230                 table->thermalProtectType = PPSMC_THERMAL_PROTECT_TYPE_INTERNAL;
5231                 break;
5232         case THERMAL_TYPE_NONE:
5233                 table->thermalProtectType = PPSMC_THERMAL_PROTECT_TYPE_NONE;
5234                 break;
5235         default:
5236                 table->thermalProtectType = PPSMC_THERMAL_PROTECT_TYPE_EXTERNAL;
5237                 break;
5238         }
5239
5240         if (adev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_HARDWAREDC)
5241                 table->systemFlags |= PPSMC_SYSTEMFLAG_GPIO_DC;
5242
5243         if (adev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_REGULATOR_HOT) {
5244                 if ((adev->pdev->device != 0x6818) && (adev->pdev->device != 0x6819))
5245                         table->systemFlags |= PPSMC_SYSTEMFLAG_REGULATOR_HOT;
5246         }
5247
5248         if (adev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_STEPVDDC)
5249                 table->systemFlags |= PPSMC_SYSTEMFLAG_STEPVDDC;
5250
5251         if (adev->mc.vram_type == AMDGPU_VRAM_TYPE_GDDR5)
5252                 table->systemFlags |= PPSMC_SYSTEMFLAG_GDDR5;
5253
5254         if (adev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_REVERT_GPIO5_POLARITY)
5255                 table->extraFlags |= PPSMC_EXTRAFLAGS_AC2DC_GPIO5_POLARITY_HIGH;
5256
5257         if (adev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_VRHOT_GPIO_CONFIGURABLE) {
5258                 table->systemFlags |= PPSMC_SYSTEMFLAG_REGULATOR_HOT_PROG_GPIO;
5259                 vr_hot_gpio = adev->pm.dpm.backbias_response_time;
5260                 si_write_smc_soft_register(adev, SI_SMC_SOFT_REGISTER_vr_hot_gpio,
5261                                            vr_hot_gpio);
5262         }
5263
5264         ret = si_populate_smc_initial_state(adev, amdgpu_boot_state, table);
5265         if (ret)
5266                 return ret;
5267
5268         ret = si_populate_smc_acpi_state(adev, table);
5269         if (ret)
5270                 return ret;
5271
5272         table->driverState = table->initialState;
5273
5274         ret = si_do_program_memory_timing_parameters(adev, amdgpu_boot_state,
5275                                                      SISLANDS_INITIAL_STATE_ARB_INDEX);
5276         if (ret)
5277                 return ret;
5278
5279         if (ulv->supported && ulv->pl.vddc) {
5280                 ret = si_populate_ulv_state(adev, &table->ULVState);
5281                 if (ret)
5282                         return ret;
5283
5284                 ret = si_program_ulv_memory_timing_parameters(adev);
5285                 if (ret)
5286                         return ret;
5287
5288                 WREG32(CG_ULV_CONTROL, ulv->cg_ulv_control);
5289                 WREG32(CG_ULV_PARAMETER, ulv->cg_ulv_parameter);
5290
5291                 lane_width = amdgpu_get_pcie_lanes(adev);
5292                 si_write_smc_soft_register(adev, SI_SMC_SOFT_REGISTER_non_ulv_pcie_link_width, lane_width);
5293         } else {
5294                 table->ULVState = table->initialState;
5295         }
5296
5297         return amdgpu_si_copy_bytes_to_smc(adev, si_pi->state_table_start,
5298                                            (u8 *)table, sizeof(SISLANDS_SMC_STATETABLE),
5299                                            si_pi->sram_end);
5300 }
5301
5302 static int si_calculate_sclk_params(struct amdgpu_device *adev,
5303                                     u32 engine_clock,
5304                                     SISLANDS_SMC_SCLK_VALUE *sclk)
5305 {
5306         struct rv7xx_power_info *pi = rv770_get_pi(adev);
5307         struct si_power_info *si_pi = si_get_pi(adev);
5308         struct atom_clock_dividers dividers;
5309         u32 spll_func_cntl = si_pi->clock_registers.cg_spll_func_cntl;
5310         u32 spll_func_cntl_2 = si_pi->clock_registers.cg_spll_func_cntl_2;
5311         u32 spll_func_cntl_3 = si_pi->clock_registers.cg_spll_func_cntl_3;
5312         u32 spll_func_cntl_4 = si_pi->clock_registers.cg_spll_func_cntl_4;
5313         u32 cg_spll_spread_spectrum = si_pi->clock_registers.cg_spll_spread_spectrum;
5314         u32 cg_spll_spread_spectrum_2 = si_pi->clock_registers.cg_spll_spread_spectrum_2;
5315         u64 tmp;
5316         u32 reference_clock = adev->clock.spll.reference_freq;
5317         u32 reference_divider;
5318         u32 fbdiv;
5319         int ret;
5320
5321         ret = amdgpu_atombios_get_clock_dividers(adev, COMPUTE_ENGINE_PLL_PARAM,
5322                                              engine_clock, false, &dividers);
5323         if (ret)
5324                 return ret;
5325
5326         reference_divider = 1 + dividers.ref_div;
5327
5328         tmp = (u64) engine_clock * reference_divider * dividers.post_div * 16384;
5329         do_div(tmp, reference_clock);
5330         fbdiv = (u32) tmp;
5331
5332         spll_func_cntl &= ~(SPLL_PDIV_A_MASK | SPLL_REF_DIV_MASK);
5333         spll_func_cntl |= SPLL_REF_DIV(dividers.ref_div);
5334         spll_func_cntl |= SPLL_PDIV_A(dividers.post_div);
5335
5336         spll_func_cntl_2 &= ~SCLK_MUX_SEL_MASK;
5337         spll_func_cntl_2 |= SCLK_MUX_SEL(2);
5338
5339         spll_func_cntl_3 &= ~SPLL_FB_DIV_MASK;
5340         spll_func_cntl_3 |= SPLL_FB_DIV(fbdiv);
5341         spll_func_cntl_3 |= SPLL_DITHEN;
5342
5343         if (pi->sclk_ss) {
5344                 struct amdgpu_atom_ss ss;
5345                 u32 vco_freq = engine_clock * dividers.post_div;
5346
5347                 if (amdgpu_atombios_get_asic_ss_info(adev, &ss,
5348                                                      ASIC_INTERNAL_ENGINE_SS, vco_freq)) {
5349                         u32 clk_s = reference_clock * 5 / (reference_divider * ss.rate);
5350                         u32 clk_v = 4 * ss.percentage * fbdiv / (clk_s * 10000);
5351
5352                         cg_spll_spread_spectrum &= ~CLK_S_MASK;
5353                         cg_spll_spread_spectrum |= CLK_S(clk_s);
5354                         cg_spll_spread_spectrum |= SSEN;
5355
5356                         cg_spll_spread_spectrum_2 &= ~CLK_V_MASK;
5357                         cg_spll_spread_spectrum_2 |= CLK_V(clk_v);
5358                 }
5359         }
5360
5361         sclk->sclk_value = engine_clock;
5362         sclk->vCG_SPLL_FUNC_CNTL = spll_func_cntl;
5363         sclk->vCG_SPLL_FUNC_CNTL_2 = spll_func_cntl_2;
5364         sclk->vCG_SPLL_FUNC_CNTL_3 = spll_func_cntl_3;
5365         sclk->vCG_SPLL_FUNC_CNTL_4 = spll_func_cntl_4;
5366         sclk->vCG_SPLL_SPREAD_SPECTRUM = cg_spll_spread_spectrum;
5367         sclk->vCG_SPLL_SPREAD_SPECTRUM_2 = cg_spll_spread_spectrum_2;
5368
5369         return 0;
5370 }
5371
5372 static int si_populate_sclk_value(struct amdgpu_device *adev,
5373                                   u32 engine_clock,
5374                                   SISLANDS_SMC_SCLK_VALUE *sclk)
5375 {
5376         SISLANDS_SMC_SCLK_VALUE sclk_tmp;
5377         int ret;
5378
5379         ret = si_calculate_sclk_params(adev, engine_clock, &sclk_tmp);
5380         if (!ret) {
5381                 sclk->sclk_value = cpu_to_be32(sclk_tmp.sclk_value);
5382                 sclk->vCG_SPLL_FUNC_CNTL = cpu_to_be32(sclk_tmp.vCG_SPLL_FUNC_CNTL);
5383                 sclk->vCG_SPLL_FUNC_CNTL_2 = cpu_to_be32(sclk_tmp.vCG_SPLL_FUNC_CNTL_2);
5384                 sclk->vCG_SPLL_FUNC_CNTL_3 = cpu_to_be32(sclk_tmp.vCG_SPLL_FUNC_CNTL_3);
5385                 sclk->vCG_SPLL_FUNC_CNTL_4 = cpu_to_be32(sclk_tmp.vCG_SPLL_FUNC_CNTL_4);
5386                 sclk->vCG_SPLL_SPREAD_SPECTRUM = cpu_to_be32(sclk_tmp.vCG_SPLL_SPREAD_SPECTRUM);
5387                 sclk->vCG_SPLL_SPREAD_SPECTRUM_2 = cpu_to_be32(sclk_tmp.vCG_SPLL_SPREAD_SPECTRUM_2);
5388         }
5389
5390         return ret;
5391 }
5392
5393 static int si_populate_mclk_value(struct amdgpu_device *adev,
5394                                   u32 engine_clock,
5395                                   u32 memory_clock,
5396                                   SISLANDS_SMC_MCLK_VALUE *mclk,
5397                                   bool strobe_mode,
5398                                   bool dll_state_on)
5399 {
5400         struct rv7xx_power_info *pi = rv770_get_pi(adev);
5401         struct si_power_info *si_pi = si_get_pi(adev);
5402         u32  dll_cntl = si_pi->clock_registers.dll_cntl;
5403         u32  mclk_pwrmgt_cntl = si_pi->clock_registers.mclk_pwrmgt_cntl;
5404         u32  mpll_ad_func_cntl = si_pi->clock_registers.mpll_ad_func_cntl;
5405         u32  mpll_dq_func_cntl = si_pi->clock_registers.mpll_dq_func_cntl;
5406         u32  mpll_func_cntl = si_pi->clock_registers.mpll_func_cntl;
5407         u32  mpll_func_cntl_1 = si_pi->clock_registers.mpll_func_cntl_1;
5408         u32  mpll_func_cntl_2 = si_pi->clock_registers.mpll_func_cntl_2;
5409         u32  mpll_ss1 = si_pi->clock_registers.mpll_ss1;
5410         u32  mpll_ss2 = si_pi->clock_registers.mpll_ss2;
5411         struct atom_mpll_param mpll_param;
5412         int ret;
5413
5414         ret = amdgpu_atombios_get_memory_pll_dividers(adev, memory_clock, strobe_mode, &mpll_param);
5415         if (ret)
5416                 return ret;
5417
5418         mpll_func_cntl &= ~BWCTRL_MASK;
5419         mpll_func_cntl |= BWCTRL(mpll_param.bwcntl);
5420
5421         mpll_func_cntl_1 &= ~(CLKF_MASK | CLKFRAC_MASK | VCO_MODE_MASK);
5422         mpll_func_cntl_1 |= CLKF(mpll_param.clkf) |
5423                 CLKFRAC(mpll_param.clkfrac) | VCO_MODE(mpll_param.vco_mode);
5424
5425         mpll_ad_func_cntl &= ~YCLK_POST_DIV_MASK;
5426         mpll_ad_func_cntl |= YCLK_POST_DIV(mpll_param.post_div);
5427
5428         if (adev->mc.vram_type == AMDGPU_VRAM_TYPE_GDDR5) {
5429                 mpll_dq_func_cntl &= ~(YCLK_SEL_MASK | YCLK_POST_DIV_MASK);
5430                 mpll_dq_func_cntl |= YCLK_SEL(mpll_param.yclk_sel) |
5431                         YCLK_POST_DIV(mpll_param.post_div);
5432         }
5433
5434         if (pi->mclk_ss) {
5435                 struct amdgpu_atom_ss ss;
5436                 u32 freq_nom;
5437                 u32 tmp;
5438                 u32 reference_clock = adev->clock.mpll.reference_freq;
5439
5440                 if (adev->mc.vram_type == AMDGPU_VRAM_TYPE_GDDR5)
5441                         freq_nom = memory_clock * 4;
5442                 else
5443                         freq_nom = memory_clock * 2;
5444
5445                 tmp = freq_nom / reference_clock;
5446                 tmp = tmp * tmp;
5447                 if (amdgpu_atombios_get_asic_ss_info(adev, &ss,
5448                                                      ASIC_INTERNAL_MEMORY_SS, freq_nom)) {
5449                         u32 clks = reference_clock * 5 / ss.rate;
5450                         u32 clkv = (u32)((((131 * ss.percentage * ss.rate) / 100) * tmp) / freq_nom);
5451
5452                         mpll_ss1 &= ~CLKV_MASK;
5453                         mpll_ss1 |= CLKV(clkv);
5454
5455                         mpll_ss2 &= ~CLKS_MASK;
5456                         mpll_ss2 |= CLKS(clks);
5457                 }
5458         }
5459
5460         mclk_pwrmgt_cntl &= ~DLL_SPEED_MASK;
5461         mclk_pwrmgt_cntl |= DLL_SPEED(mpll_param.dll_speed);
5462
5463         if (dll_state_on)
5464                 mclk_pwrmgt_cntl |= MRDCK0_PDNB | MRDCK1_PDNB;
5465         else
5466                 mclk_pwrmgt_cntl &= ~(MRDCK0_PDNB | MRDCK1_PDNB);
5467
5468         mclk->mclk_value = cpu_to_be32(memory_clock);
5469         mclk->vMPLL_FUNC_CNTL = cpu_to_be32(mpll_func_cntl);
5470         mclk->vMPLL_FUNC_CNTL_1 = cpu_to_be32(mpll_func_cntl_1);
5471         mclk->vMPLL_FUNC_CNTL_2 = cpu_to_be32(mpll_func_cntl_2);
5472         mclk->vMPLL_AD_FUNC_CNTL = cpu_to_be32(mpll_ad_func_cntl);
5473         mclk->vMPLL_DQ_FUNC_CNTL = cpu_to_be32(mpll_dq_func_cntl);
5474         mclk->vMCLK_PWRMGT_CNTL = cpu_to_be32(mclk_pwrmgt_cntl);
5475         mclk->vDLL_CNTL = cpu_to_be32(dll_cntl);
5476         mclk->vMPLL_SS = cpu_to_be32(mpll_ss1);
5477         mclk->vMPLL_SS2 = cpu_to_be32(mpll_ss2);
5478
5479         return 0;
5480 }
5481
5482 static void si_populate_smc_sp(struct amdgpu_device *adev,
5483                                struct amdgpu_ps *amdgpu_state,
5484                                SISLANDS_SMC_SWSTATE *smc_state)
5485 {
5486         struct  si_ps *ps = si_get_ps(amdgpu_state);
5487         struct rv7xx_power_info *pi = rv770_get_pi(adev);
5488         int i;
5489
5490         for (i = 0; i < ps->performance_level_count - 1; i++)
5491                 smc_state->levels[i].bSP = cpu_to_be32(pi->dsp);
5492
5493         smc_state->levels[ps->performance_level_count - 1].bSP =
5494                 cpu_to_be32(pi->psp);
5495 }
5496
5497 static int si_convert_power_level_to_smc(struct amdgpu_device *adev,
5498                                          struct rv7xx_pl *pl,
5499                                          SISLANDS_SMC_HW_PERFORMANCE_LEVEL *level)
5500 {
5501         struct rv7xx_power_info *pi = rv770_get_pi(adev);
5502         struct evergreen_power_info *eg_pi = evergreen_get_pi(adev);
5503         struct si_power_info *si_pi = si_get_pi(adev);
5504         int ret;
5505         bool dll_state_on;
5506         u16 std_vddc;
5507         bool gmc_pg = false;
5508
5509         if (eg_pi->pcie_performance_request &&
5510             (si_pi->force_pcie_gen != AMDGPU_PCIE_GEN_INVALID))
5511                 level->gen2PCIE = (u8)si_pi->force_pcie_gen;
5512         else
5513                 level->gen2PCIE = (u8)pl->pcie_gen;
5514
5515         ret = si_populate_sclk_value(adev, pl->sclk, &level->sclk);
5516         if (ret)
5517                 return ret;
5518
5519         level->mcFlags =  0;
5520
5521         if (pi->mclk_stutter_mode_threshold &&
5522             (pl->mclk <= pi->mclk_stutter_mode_threshold) &&
5523             !eg_pi->uvd_enabled &&
5524             (RREG32(DPG_PIPE_STUTTER_CONTROL) & STUTTER_ENABLE) &&
5525             (adev->pm.dpm.new_active_crtc_count <= 2)) {
5526                 level->mcFlags |= SISLANDS_SMC_MC_STUTTER_EN;
5527
5528                 if (gmc_pg)
5529                         level->mcFlags |= SISLANDS_SMC_MC_PG_EN;
5530         }
5531
5532         if (adev->mc.vram_type == AMDGPU_VRAM_TYPE_GDDR5) {
5533                 if (pl->mclk > pi->mclk_edc_enable_threshold)
5534                         level->mcFlags |= SISLANDS_SMC_MC_EDC_RD_FLAG;
5535
5536                 if (pl->mclk > eg_pi->mclk_edc_wr_enable_threshold)
5537                         level->mcFlags |= SISLANDS_SMC_MC_EDC_WR_FLAG;
5538
5539                 level->strobeMode = si_get_strobe_mode_settings(adev, pl->mclk);
5540
5541                 if (level->strobeMode & SISLANDS_SMC_STROBE_ENABLE) {
5542                         if (si_get_mclk_frequency_ratio(pl->mclk, true) >=
5543                             ((RREG32(MC_SEQ_MISC7) >> 16) & 0xf))
5544                                 dll_state_on = ((RREG32(MC_SEQ_MISC5) >> 1) & 0x1) ? true : false;
5545                         else
5546                                 dll_state_on = ((RREG32(MC_SEQ_MISC6) >> 1) & 0x1) ? true : false;
5547                 } else {
5548                         dll_state_on = false;
5549                 }
5550         } else {
5551                 level->strobeMode = si_get_strobe_mode_settings(adev,
5552                                                                 pl->mclk);
5553
5554                 dll_state_on = ((RREG32(MC_SEQ_MISC5) >> 1) & 0x1) ? true : false;
5555         }
5556
5557         ret = si_populate_mclk_value(adev,
5558                                      pl->sclk,
5559                                      pl->mclk,
5560                                      &level->mclk,
5561                                      (level->strobeMode & SISLANDS_SMC_STROBE_ENABLE) != 0, dll_state_on);
5562         if (ret)
5563                 return ret;
5564
5565         ret = si_populate_voltage_value(adev,
5566                                         &eg_pi->vddc_voltage_table,
5567                                         pl->vddc, &level->vddc);
5568         if (ret)
5569                 return ret;
5570
5571
5572         ret = si_get_std_voltage_value(adev, &level->vddc, &std_vddc);
5573         if (ret)
5574                 return ret;
5575
5576         ret = si_populate_std_voltage_value(adev, std_vddc,
5577                                             level->vddc.index, &level->std_vddc);
5578         if (ret)
5579                 return ret;
5580
5581         if (eg_pi->vddci_control) {
5582                 ret = si_populate_voltage_value(adev, &eg_pi->vddci_voltage_table,
5583                                                 pl->vddci, &level->vddci);
5584                 if (ret)
5585                         return ret;
5586         }
5587
5588         if (si_pi->vddc_phase_shed_control) {
5589                 ret = si_populate_phase_shedding_value(adev,
5590                                                        &adev->pm.dpm.dyn_state.phase_shedding_limits_table,
5591                                                        pl->vddc,
5592                                                        pl->sclk,
5593                                                        pl->mclk,
5594                                                        &level->vddc);
5595                 if (ret)
5596                         return ret;
5597         }
5598
5599         level->MaxPoweredUpCU = si_pi->max_cu;
5600
5601         ret = si_populate_mvdd_value(adev, pl->mclk, &level->mvdd);
5602
5603         return ret;
5604 }
5605
5606 static int si_populate_smc_t(struct amdgpu_device *adev,
5607                              struct amdgpu_ps *amdgpu_state,
5608                              SISLANDS_SMC_SWSTATE *smc_state)
5609 {
5610         struct rv7xx_power_info *pi = rv770_get_pi(adev);
5611         struct  si_ps *state = si_get_ps(amdgpu_state);
5612         u32 a_t;
5613         u32 t_l, t_h;
5614         u32 high_bsp;
5615         int i, ret;
5616
5617         if (state->performance_level_count >= 9)
5618                 return -EINVAL;
5619
5620         if (state->performance_level_count < 2) {
5621                 a_t = CG_R(0xffff) | CG_L(0);
5622                 smc_state->levels[0].aT = cpu_to_be32(a_t);
5623                 return 0;
5624         }
5625
5626         smc_state->levels[0].aT = cpu_to_be32(0);
5627
5628         for (i = 0; i <= state->performance_level_count - 2; i++) {
5629                 ret = r600_calculate_at(
5630                         (50 / SISLANDS_MAX_HARDWARE_POWERLEVELS) * 100 * (i + 1),
5631                         100 * R600_AH_DFLT,
5632                         state->performance_levels[i + 1].sclk,
5633                         state->performance_levels[i].sclk,
5634                         &t_l,
5635                         &t_h);
5636
5637                 if (ret) {
5638                         t_h = (i + 1) * 1000 - 50 * R600_AH_DFLT;
5639                         t_l = (i + 1) * 1000 + 50 * R600_AH_DFLT;
5640                 }
5641
5642                 a_t = be32_to_cpu(smc_state->levels[i].aT) & ~CG_R_MASK;
5643                 a_t |= CG_R(t_l * pi->bsp / 20000);
5644                 smc_state->levels[i].aT = cpu_to_be32(a_t);
5645
5646                 high_bsp = (i == state->performance_level_count - 2) ?
5647                         pi->pbsp : pi->bsp;
5648                 a_t = CG_R(0xffff) | CG_L(t_h * high_bsp / 20000);
5649                 smc_state->levels[i + 1].aT = cpu_to_be32(a_t);
5650         }
5651
5652         return 0;
5653 }
5654
5655 static int si_disable_ulv(struct amdgpu_device *adev)
5656 {
5657         struct si_power_info *si_pi = si_get_pi(adev);
5658         struct si_ulv_param *ulv = &si_pi->ulv;
5659
5660         if (ulv->supported)
5661                 return (amdgpu_si_send_msg_to_smc(adev, PPSMC_MSG_DisableULV) == PPSMC_Result_OK) ?
5662                         0 : -EINVAL;
5663
5664         return 0;
5665 }
5666
5667 static bool si_is_state_ulv_compatible(struct amdgpu_device *adev,
5668                                        struct amdgpu_ps *amdgpu_state)
5669 {
5670         const struct si_power_info *si_pi = si_get_pi(adev);
5671         const struct si_ulv_param *ulv = &si_pi->ulv;
5672         const struct  si_ps *state = si_get_ps(amdgpu_state);
5673         int i;
5674
5675         if (state->performance_levels[0].mclk != ulv->pl.mclk)
5676                 return false;
5677
5678         /* XXX validate against display requirements! */
5679
5680         for (i = 0; i < adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.count; i++) {
5681                 if (adev->clock.current_dispclk <=
5682                     adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[i].clk) {
5683                         if (ulv->pl.vddc <
5684                             adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[i].v)
5685                                 return false;
5686                 }
5687         }
5688
5689         if ((amdgpu_state->vclk != 0) || (amdgpu_state->dclk != 0))
5690                 return false;
5691
5692         return true;
5693 }
5694
5695 static int si_set_power_state_conditionally_enable_ulv(struct amdgpu_device *adev,
5696                                                        struct amdgpu_ps *amdgpu_new_state)
5697 {
5698         const struct si_power_info *si_pi = si_get_pi(adev);
5699         const struct si_ulv_param *ulv = &si_pi->ulv;
5700
5701         if (ulv->supported) {
5702                 if (si_is_state_ulv_compatible(adev, amdgpu_new_state))
5703                         return (amdgpu_si_send_msg_to_smc(adev, PPSMC_MSG_EnableULV) == PPSMC_Result_OK) ?
5704                                 0 : -EINVAL;
5705         }
5706         return 0;
5707 }
5708
5709 static int si_convert_power_state_to_smc(struct amdgpu_device *adev,
5710                                          struct amdgpu_ps *amdgpu_state,
5711                                          SISLANDS_SMC_SWSTATE *smc_state)
5712 {
5713         struct evergreen_power_info *eg_pi = evergreen_get_pi(adev);
5714         struct ni_power_info *ni_pi = ni_get_pi(adev);
5715         struct si_power_info *si_pi = si_get_pi(adev);
5716         struct  si_ps *state = si_get_ps(amdgpu_state);
5717         int i, ret;
5718         u32 threshold;
5719         u32 sclk_in_sr = 1350; /* ??? */
5720
5721         if (state->performance_level_count > SISLANDS_MAX_HARDWARE_POWERLEVELS)
5722                 return -EINVAL;
5723
5724         threshold = state->performance_levels[state->performance_level_count-1].sclk * 100 / 100;
5725
5726         if (amdgpu_state->vclk && amdgpu_state->dclk) {
5727                 eg_pi->uvd_enabled = true;
5728                 if (eg_pi->smu_uvd_hs)
5729                         smc_state->flags |= PPSMC_SWSTATE_FLAG_UVD;
5730         } else {
5731                 eg_pi->uvd_enabled = false;
5732         }
5733
5734         if (state->dc_compatible)
5735                 smc_state->flags |= PPSMC_SWSTATE_FLAG_DC;
5736
5737         smc_state->levelCount = 0;
5738         for (i = 0; i < state->performance_level_count; i++) {
5739                 if (eg_pi->sclk_deep_sleep) {
5740                         if ((i == 0) || si_pi->sclk_deep_sleep_above_low) {
5741                                 if (sclk_in_sr <= SCLK_MIN_DEEPSLEEP_FREQ)
5742                                         smc_state->levels[i].stateFlags |= PPSMC_STATEFLAG_DEEPSLEEP_BYPASS;
5743                                 else
5744                                         smc_state->levels[i].stateFlags |= PPSMC_STATEFLAG_DEEPSLEEP_THROTTLE;
5745                         }
5746                 }
5747
5748                 ret = si_convert_power_level_to_smc(adev, &state->performance_levels[i],
5749                                                     &smc_state->levels[i]);
5750                 smc_state->levels[i].arbRefreshState =
5751                         (u8)(SISLANDS_DRIVER_STATE_ARB_INDEX + i);
5752
5753                 if (ret)
5754                         return ret;
5755
5756                 if (ni_pi->enable_power_containment)
5757                         smc_state->levels[i].displayWatermark =
5758                                 (state->performance_levels[i].sclk < threshold) ?
5759                                 PPSMC_DISPLAY_WATERMARK_LOW : PPSMC_DISPLAY_WATERMARK_HIGH;
5760                 else
5761                         smc_state->levels[i].displayWatermark = (i < 2) ?
5762                                 PPSMC_DISPLAY_WATERMARK_LOW : PPSMC_DISPLAY_WATERMARK_HIGH;
5763
5764                 if (eg_pi->dynamic_ac_timing)
5765                         smc_state->levels[i].ACIndex = SISLANDS_MCREGISTERTABLE_FIRST_DRIVERSTATE_SLOT + i;
5766                 else
5767                         smc_state->levels[i].ACIndex = 0;
5768
5769                 smc_state->levelCount++;
5770         }
5771
5772         si_write_smc_soft_register(adev,
5773                                    SI_SMC_SOFT_REGISTER_watermark_threshold,
5774                                    threshold / 512);
5775
5776         si_populate_smc_sp(adev, amdgpu_state, smc_state);
5777
5778         ret = si_populate_power_containment_values(adev, amdgpu_state, smc_state);
5779         if (ret)
5780                 ni_pi->enable_power_containment = false;
5781
5782         ret = si_populate_sq_ramping_values(adev, amdgpu_state, smc_state);
5783         if (ret)
5784                 ni_pi->enable_sq_ramping = false;
5785
5786         return si_populate_smc_t(adev, amdgpu_state, smc_state);
5787 }
5788
5789 static int si_upload_sw_state(struct amdgpu_device *adev,
5790                               struct amdgpu_ps *amdgpu_new_state)
5791 {
5792         struct si_power_info *si_pi = si_get_pi(adev);
5793         struct  si_ps *new_state = si_get_ps(amdgpu_new_state);
5794         int ret;
5795         u32 address = si_pi->state_table_start +
5796                 offsetof(SISLANDS_SMC_STATETABLE, driverState);
5797         u32 state_size = sizeof(SISLANDS_SMC_SWSTATE) +
5798                 ((new_state->performance_level_count - 1) *
5799                  sizeof(SISLANDS_SMC_HW_PERFORMANCE_LEVEL));
5800         SISLANDS_SMC_SWSTATE *smc_state = &si_pi->smc_statetable.driverState;
5801
5802         memset(smc_state, 0, state_size);
5803
5804         ret = si_convert_power_state_to_smc(adev, amdgpu_new_state, smc_state);
5805         if (ret)
5806                 return ret;
5807
5808         return amdgpu_si_copy_bytes_to_smc(adev, address, (u8 *)smc_state,
5809                                            state_size, si_pi->sram_end);
5810 }
5811
5812 static int si_upload_ulv_state(struct amdgpu_device *adev)
5813 {
5814         struct si_power_info *si_pi = si_get_pi(adev);
5815         struct si_ulv_param *ulv = &si_pi->ulv;
5816         int ret = 0;
5817
5818         if (ulv->supported && ulv->pl.vddc) {
5819                 u32 address = si_pi->state_table_start +
5820                         offsetof(SISLANDS_SMC_STATETABLE, ULVState);
5821                 SISLANDS_SMC_SWSTATE *smc_state = &si_pi->smc_statetable.ULVState;
5822                 u32 state_size = sizeof(SISLANDS_SMC_SWSTATE);
5823
5824                 memset(smc_state, 0, state_size);
5825
5826                 ret = si_populate_ulv_state(adev, smc_state);
5827                 if (!ret)
5828                         ret = amdgpu_si_copy_bytes_to_smc(adev, address, (u8 *)smc_state,
5829                                                           state_size, si_pi->sram_end);
5830         }
5831
5832         return ret;
5833 }
5834
5835 static int si_upload_smc_data(struct amdgpu_device *adev)
5836 {
5837         struct amdgpu_crtc *amdgpu_crtc = NULL;
5838         int i;
5839
5840         if (adev->pm.dpm.new_active_crtc_count == 0)
5841                 return 0;
5842
5843         for (i = 0; i < adev->mode_info.num_crtc; i++) {
5844                 if (adev->pm.dpm.new_active_crtcs & (1 << i)) {
5845                         amdgpu_crtc = adev->mode_info.crtcs[i];
5846                         break;
5847                 }
5848         }
5849
5850         if (amdgpu_crtc == NULL)
5851                 return 0;
5852
5853         if (amdgpu_crtc->line_time <= 0)
5854                 return 0;
5855
5856         if (si_write_smc_soft_register(adev,
5857                                        SI_SMC_SOFT_REGISTER_crtc_index,
5858                                        amdgpu_crtc->crtc_id) != PPSMC_Result_OK)
5859                 return 0;
5860
5861         if (si_write_smc_soft_register(adev,
5862                                        SI_SMC_SOFT_REGISTER_mclk_change_block_cp_min,
5863                                        amdgpu_crtc->wm_high / amdgpu_crtc->line_time) != PPSMC_Result_OK)
5864                 return 0;
5865
5866         if (si_write_smc_soft_register(adev,
5867                                        SI_SMC_SOFT_REGISTER_mclk_change_block_cp_max,
5868                                        amdgpu_crtc->wm_low / amdgpu_crtc->line_time) != PPSMC_Result_OK)
5869                 return 0;
5870
5871         return 0;
5872 }
5873
5874 static int si_set_mc_special_registers(struct amdgpu_device *adev,
5875                                        struct si_mc_reg_table *table)
5876 {
5877         u8 i, j, k;
5878         u32 temp_reg;
5879
5880         for (i = 0, j = table->last; i < table->last; i++) {
5881                 if (j >= SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE)
5882                         return -EINVAL;
5883                 switch (table->mc_reg_address[i].s1) {
5884                 case MC_SEQ_MISC1:
5885                         temp_reg = RREG32(MC_PMG_CMD_EMRS);
5886                         table->mc_reg_address[j].s1 = MC_PMG_CMD_EMRS;
5887                         table->mc_reg_address[j].s0 = MC_SEQ_PMG_CMD_EMRS_LP;
5888                         for (k = 0; k < table->num_entries; k++)
5889                                 table->mc_reg_table_entry[k].mc_data[j] =
5890                                         ((temp_reg & 0xffff0000)) |
5891                                         ((table->mc_reg_table_entry[k].mc_data[i] & 0xffff0000) >> 16);
5892                         j++;
5893                         if (j >= SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE)
5894                                 return -EINVAL;
5895
5896                         temp_reg = RREG32(MC_PMG_CMD_MRS);
5897                         table->mc_reg_address[j].s1 = MC_PMG_CMD_MRS;
5898                         table->mc_reg_address[j].s0 = MC_SEQ_PMG_CMD_MRS_LP;
5899                         for (k = 0; k < table->num_entries; k++) {
5900                                 table->mc_reg_table_entry[k].mc_data[j] =
5901                                         (temp_reg & 0xffff0000) |
5902                                         (table->mc_reg_table_entry[k].mc_data[i] & 0x0000ffff);
5903                                 if (adev->mc.vram_type != AMDGPU_VRAM_TYPE_GDDR5)
5904                                         table->mc_reg_table_entry[k].mc_data[j] |= 0x100;
5905                         }
5906                         j++;
5907                         if (j >= SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE)
5908                                 return -EINVAL;
5909
5910                         if (adev->mc.vram_type != AMDGPU_VRAM_TYPE_GDDR5) {
5911                                 table->mc_reg_address[j].s1 = MC_PMG_AUTO_CMD;
5912                                 table->mc_reg_address[j].s0 = MC_PMG_AUTO_CMD;
5913                                 for (k = 0; k < table->num_entries; k++)
5914                                         table->mc_reg_table_entry[k].mc_data[j] =
5915                                                 (table->mc_reg_table_entry[k].mc_data[i] & 0xffff0000) >> 16;
5916                                 j++;
5917                                 if (j >= SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE)
5918                                         return -EINVAL;
5919                         }
5920                         break;
5921                 case MC_SEQ_RESERVE_M:
5922                         temp_reg = RREG32(MC_PMG_CMD_MRS1);
5923                         table->mc_reg_address[j].s1 = MC_PMG_CMD_MRS1;
5924                         table->mc_reg_address[j].s0 = MC_SEQ_PMG_CMD_MRS1_LP;
5925                         for(k = 0; k < table->num_entries; k++)
5926                                 table->mc_reg_table_entry[k].mc_data[j] =
5927                                         (temp_reg & 0xffff0000) |
5928                                         (table->mc_reg_table_entry[k].mc_data[i] & 0x0000ffff);
5929                         j++;
5930                         if (j >= SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE)
5931                                 return -EINVAL;
5932                         break;
5933                 default:
5934                         break;
5935                 }
5936         }
5937
5938         table->last = j;
5939
5940         return 0;
5941 }
5942
5943 static bool si_check_s0_mc_reg_index(u16 in_reg, u16 *out_reg)
5944 {
5945         bool result = true;
5946         switch (in_reg) {
5947         case  MC_SEQ_RAS_TIMING:
5948                 *out_reg = MC_SEQ_RAS_TIMING_LP;
5949                 break;
5950         case MC_SEQ_CAS_TIMING:
5951                 *out_reg = MC_SEQ_CAS_TIMING_LP;
5952                 break;
5953         case MC_SEQ_MISC_TIMING:
5954                 *out_reg = MC_SEQ_MISC_TIMING_LP;
5955                 break;
5956         case MC_SEQ_MISC_TIMING2:
5957                 *out_reg = MC_SEQ_MISC_TIMING2_LP;
5958                 break;
5959         case MC_SEQ_RD_CTL_D0:
5960                 *out_reg = MC_SEQ_RD_CTL_D0_LP;
5961                 break;
5962         case MC_SEQ_RD_CTL_D1:
5963                 *out_reg = MC_SEQ_RD_CTL_D1_LP;
5964                 break;
5965         case MC_SEQ_WR_CTL_D0:
5966                 *out_reg = MC_SEQ_WR_CTL_D0_LP;
5967                 break;
5968         case MC_SEQ_WR_CTL_D1:
5969                 *out_reg = MC_SEQ_WR_CTL_D1_LP;
5970                 break;
5971         case MC_PMG_CMD_EMRS:
5972                 *out_reg = MC_SEQ_PMG_CMD_EMRS_LP;
5973                 break;
5974         case MC_PMG_CMD_MRS:
5975                 *out_reg = MC_SEQ_PMG_CMD_MRS_LP;
5976                 break;
5977         case MC_PMG_CMD_MRS1:
5978                 *out_reg = MC_SEQ_PMG_CMD_MRS1_LP;
5979                 break;
5980         case MC_SEQ_PMG_TIMING:
5981                 *out_reg = MC_SEQ_PMG_TIMING_LP;
5982                 break;
5983         case MC_PMG_CMD_MRS2:
5984                 *out_reg = MC_SEQ_PMG_CMD_MRS2_LP;
5985                 break;
5986         case MC_SEQ_WR_CTL_2:
5987                 *out_reg = MC_SEQ_WR_CTL_2_LP;
5988                 break;
5989         default:
5990                 result = false;
5991                 break;
5992         }
5993
5994         return result;
5995 }
5996
5997 static void si_set_valid_flag(struct si_mc_reg_table *table)
5998 {
5999         u8 i, j;
6000
6001         for (i = 0; i < table->last; i++) {
6002                 for (j = 1; j < table->num_entries; j++) {
6003                         if (table->mc_reg_table_entry[j-1].mc_data[i] != table->mc_reg_table_entry[j].mc_data[i]) {
6004                                 table->valid_flag |= 1 << i;
6005                                 break;
6006                         }
6007                 }
6008         }
6009 }
6010
6011 static void si_set_s0_mc_reg_index(struct si_mc_reg_table *table)
6012 {
6013         u32 i;
6014         u16 address;
6015
6016         for (i = 0; i < table->last; i++)
6017                 table->mc_reg_address[i].s0 = si_check_s0_mc_reg_index(table->mc_reg_address[i].s1, &address) ?
6018                         address : table->mc_reg_address[i].s1;
6019
6020 }
6021
6022 static int si_copy_vbios_mc_reg_table(struct atom_mc_reg_table *table,
6023                                       struct si_mc_reg_table *si_table)
6024 {
6025         u8 i, j;
6026
6027         if (table->last > SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE)
6028                 return -EINVAL;
6029         if (table->num_entries > MAX_AC_TIMING_ENTRIES)
6030                 return -EINVAL;
6031
6032         for (i = 0; i < table->last; i++)
6033                 si_table->mc_reg_address[i].s1 = table->mc_reg_address[i].s1;
6034         si_table->last = table->last;
6035
6036         for (i = 0; i < table->num_entries; i++) {
6037                 si_table->mc_reg_table_entry[i].mclk_max =
6038                         table->mc_reg_table_entry[i].mclk_max;
6039                 for (j = 0; j < table->last; j++) {
6040                         si_table->mc_reg_table_entry[i].mc_data[j] =
6041                                 table->mc_reg_table_entry[i].mc_data[j];
6042                 }
6043         }
6044         si_table->num_entries = table->num_entries;
6045
6046         return 0;
6047 }
6048
6049 static int si_initialize_mc_reg_table(struct amdgpu_device *adev)
6050 {
6051         struct si_power_info *si_pi = si_get_pi(adev);
6052         struct atom_mc_reg_table *table;
6053         struct si_mc_reg_table *si_table = &si_pi->mc_reg_table;
6054         u8 module_index = rv770_get_memory_module_index(adev);
6055         int ret;
6056
6057         table = kzalloc(sizeof(struct atom_mc_reg_table), GFP_KERNEL);
6058         if (!table)
6059                 return -ENOMEM;
6060
6061         WREG32(MC_SEQ_RAS_TIMING_LP, RREG32(MC_SEQ_RAS_TIMING));
6062         WREG32(MC_SEQ_CAS_TIMING_LP, RREG32(MC_SEQ_CAS_TIMING));
6063         WREG32(MC_SEQ_MISC_TIMING_LP, RREG32(MC_SEQ_MISC_TIMING));
6064         WREG32(MC_SEQ_MISC_TIMING2_LP, RREG32(MC_SEQ_MISC_TIMING2));
6065         WREG32(MC_SEQ_PMG_CMD_EMRS_LP, RREG32(MC_PMG_CMD_EMRS));
6066         WREG32(MC_SEQ_PMG_CMD_MRS_LP, RREG32(MC_PMG_CMD_MRS));
6067         WREG32(MC_SEQ_PMG_CMD_MRS1_LP, RREG32(MC_PMG_CMD_MRS1));
6068         WREG32(MC_SEQ_WR_CTL_D0_LP, RREG32(MC_SEQ_WR_CTL_D0));
6069         WREG32(MC_SEQ_WR_CTL_D1_LP, RREG32(MC_SEQ_WR_CTL_D1));
6070         WREG32(MC_SEQ_RD_CTL_D0_LP, RREG32(MC_SEQ_RD_CTL_D0));
6071         WREG32(MC_SEQ_RD_CTL_D1_LP, RREG32(MC_SEQ_RD_CTL_D1));
6072         WREG32(MC_SEQ_PMG_TIMING_LP, RREG32(MC_SEQ_PMG_TIMING));
6073         WREG32(MC_SEQ_PMG_CMD_MRS2_LP, RREG32(MC_PMG_CMD_MRS2));
6074         WREG32(MC_SEQ_WR_CTL_2_LP, RREG32(MC_SEQ_WR_CTL_2));
6075
6076         ret = amdgpu_atombios_init_mc_reg_table(adev, module_index, table);
6077         if (ret)
6078                 goto init_mc_done;
6079
6080         ret = si_copy_vbios_mc_reg_table(table, si_table);
6081         if (ret)
6082                 goto init_mc_done;
6083
6084         si_set_s0_mc_reg_index(si_table);
6085
6086         ret = si_set_mc_special_registers(adev, si_table);
6087         if (ret)
6088                 goto init_mc_done;
6089
6090         si_set_valid_flag(si_table);
6091
6092 init_mc_done:
6093         kfree(table);
6094
6095         return ret;
6096
6097 }
6098
6099 static void si_populate_mc_reg_addresses(struct amdgpu_device *adev,
6100                                          SMC_SIslands_MCRegisters *mc_reg_table)
6101 {
6102         struct si_power_info *si_pi = si_get_pi(adev);
6103         u32 i, j;
6104
6105         for (i = 0, j = 0; j < si_pi->mc_reg_table.last; j++) {
6106                 if (si_pi->mc_reg_table.valid_flag & (1 << j)) {
6107                         if (i >= SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE)
6108                                 break;
6109                         mc_reg_table->address[i].s0 =
6110                                 cpu_to_be16(si_pi->mc_reg_table.mc_reg_address[j].s0);
6111                         mc_reg_table->address[i].s1 =
6112                                 cpu_to_be16(si_pi->mc_reg_table.mc_reg_address[j].s1);
6113                         i++;
6114                 }
6115         }
6116         mc_reg_table->last = (u8)i;
6117 }
6118
6119 static void si_convert_mc_registers(const struct si_mc_reg_entry *entry,
6120                                     SMC_SIslands_MCRegisterSet *data,
6121                                     u32 num_entries, u32 valid_flag)
6122 {
6123         u32 i, j;
6124
6125         for(i = 0, j = 0; j < num_entries; j++) {
6126                 if (valid_flag & (1 << j)) {
6127                         data->value[i] = cpu_to_be32(entry->mc_data[j]);
6128                         i++;
6129                 }
6130         }
6131 }
6132
6133 static void si_convert_mc_reg_table_entry_to_smc(struct amdgpu_device *adev,
6134                                                  struct rv7xx_pl *pl,
6135                                                  SMC_SIslands_MCRegisterSet *mc_reg_table_data)
6136 {
6137         struct si_power_info *si_pi = si_get_pi(adev);
6138         u32 i = 0;
6139
6140         for (i = 0; i < si_pi->mc_reg_table.num_entries; i++) {
6141                 if (pl->mclk <= si_pi->mc_reg_table.mc_reg_table_entry[i].mclk_max)
6142                         break;
6143         }
6144
6145         if ((i == si_pi->mc_reg_table.num_entries) && (i > 0))
6146                 --i;
6147
6148         si_convert_mc_registers(&si_pi->mc_reg_table.mc_reg_table_entry[i],
6149                                 mc_reg_table_data, si_pi->mc_reg_table.last,
6150                                 si_pi->mc_reg_table.valid_flag);
6151 }
6152
6153 static void si_convert_mc_reg_table_to_smc(struct amdgpu_device *adev,
6154                                            struct amdgpu_ps *amdgpu_state,
6155                                            SMC_SIslands_MCRegisters *mc_reg_table)
6156 {
6157         struct si_ps *state = si_get_ps(amdgpu_state);
6158         int i;
6159
6160         for (i = 0; i < state->performance_level_count; i++) {
6161                 si_convert_mc_reg_table_entry_to_smc(adev,
6162                                                      &state->performance_levels[i],
6163                                                      &mc_reg_table->data[SISLANDS_MCREGISTERTABLE_FIRST_DRIVERSTATE_SLOT + i]);
6164         }
6165 }
6166
6167 static int si_populate_mc_reg_table(struct amdgpu_device *adev,
6168                                     struct amdgpu_ps *amdgpu_boot_state)
6169 {
6170         struct  si_ps *boot_state = si_get_ps(amdgpu_boot_state);
6171         struct si_power_info *si_pi = si_get_pi(adev);
6172         struct si_ulv_param *ulv = &si_pi->ulv;
6173         SMC_SIslands_MCRegisters *smc_mc_reg_table = &si_pi->smc_mc_reg_table;
6174
6175         memset(smc_mc_reg_table, 0, sizeof(SMC_SIslands_MCRegisters));
6176
6177         si_write_smc_soft_register(adev, SI_SMC_SOFT_REGISTER_seq_index, 1);
6178
6179         si_populate_mc_reg_addresses(adev, smc_mc_reg_table);
6180
6181         si_convert_mc_reg_table_entry_to_smc(adev, &boot_state->performance_levels[0],
6182                                              &smc_mc_reg_table->data[SISLANDS_MCREGISTERTABLE_INITIAL_SLOT]);
6183
6184         si_convert_mc_registers(&si_pi->mc_reg_table.mc_reg_table_entry[0],
6185                                 &smc_mc_reg_table->data[SISLANDS_MCREGISTERTABLE_ACPI_SLOT],
6186                                 si_pi->mc_reg_table.last,
6187                                 si_pi->mc_reg_table.valid_flag);
6188
6189         if (ulv->supported && ulv->pl.vddc != 0)
6190                 si_convert_mc_reg_table_entry_to_smc(adev, &ulv->pl,
6191                                                      &smc_mc_reg_table->data[SISLANDS_MCREGISTERTABLE_ULV_SLOT]);
6192         else
6193                 si_convert_mc_registers(&si_pi->mc_reg_table.mc_reg_table_entry[0],
6194                                         &smc_mc_reg_table->data[SISLANDS_MCREGISTERTABLE_ULV_SLOT],
6195                                         si_pi->mc_reg_table.last,
6196                                         si_pi->mc_reg_table.valid_flag);
6197
6198         si_convert_mc_reg_table_to_smc(adev, amdgpu_boot_state, smc_mc_reg_table);
6199
6200         return amdgpu_si_copy_bytes_to_smc(adev, si_pi->mc_reg_table_start,
6201                                            (u8 *)smc_mc_reg_table,
6202                                            sizeof(SMC_SIslands_MCRegisters), si_pi->sram_end);
6203 }
6204
6205 static int si_upload_mc_reg_table(struct amdgpu_device *adev,
6206                                   struct amdgpu_ps *amdgpu_new_state)
6207 {
6208         struct si_ps *new_state = si_get_ps(amdgpu_new_state);
6209         struct si_power_info *si_pi = si_get_pi(adev);
6210         u32 address = si_pi->mc_reg_table_start +
6211                 offsetof(SMC_SIslands_MCRegisters,
6212                          data[SISLANDS_MCREGISTERTABLE_FIRST_DRIVERSTATE_SLOT]);
6213         SMC_SIslands_MCRegisters *smc_mc_reg_table = &si_pi->smc_mc_reg_table;
6214
6215         memset(smc_mc_reg_table, 0, sizeof(SMC_SIslands_MCRegisters));
6216
6217         si_convert_mc_reg_table_to_smc(adev, amdgpu_new_state, smc_mc_reg_table);
6218
6219         return amdgpu_si_copy_bytes_to_smc(adev, address,
6220                                            (u8 *)&smc_mc_reg_table->data[SISLANDS_MCREGISTERTABLE_FIRST_DRIVERSTATE_SLOT],
6221                                            sizeof(SMC_SIslands_MCRegisterSet) * new_state->performance_level_count,
6222                                            si_pi->sram_end);
6223 }
6224
6225 static void si_enable_voltage_control(struct amdgpu_device *adev, bool enable)
6226 {
6227         if (enable)
6228                 WREG32_P(GENERAL_PWRMGT, VOLT_PWRMGT_EN, ~VOLT_PWRMGT_EN);
6229         else
6230                 WREG32_P(GENERAL_PWRMGT, 0, ~VOLT_PWRMGT_EN);
6231 }
6232
6233 static enum amdgpu_pcie_gen si_get_maximum_link_speed(struct amdgpu_device *adev,
6234                                                       struct amdgpu_ps *amdgpu_state)
6235 {
6236         struct si_ps *state = si_get_ps(amdgpu_state);
6237         int i;
6238         u16 pcie_speed, max_speed = 0;
6239
6240         for (i = 0; i < state->performance_level_count; i++) {
6241                 pcie_speed = state->performance_levels[i].pcie_gen;
6242                 if (max_speed < pcie_speed)
6243                         max_speed = pcie_speed;
6244         }
6245         return max_speed;
6246 }
6247
6248 static u16 si_get_current_pcie_speed(struct amdgpu_device *adev)
6249 {
6250         u32 speed_cntl;
6251
6252         speed_cntl = RREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL) & LC_CURRENT_DATA_RATE_MASK;
6253         speed_cntl >>= LC_CURRENT_DATA_RATE_SHIFT;
6254
6255         return (u16)speed_cntl;
6256 }
6257
6258 static void si_request_link_speed_change_before_state_change(struct amdgpu_device *adev,
6259                                                              struct amdgpu_ps *amdgpu_new_state,
6260                                                              struct amdgpu_ps *amdgpu_current_state)
6261 {
6262         struct si_power_info *si_pi = si_get_pi(adev);
6263         enum amdgpu_pcie_gen target_link_speed = si_get_maximum_link_speed(adev, amdgpu_new_state);
6264         enum amdgpu_pcie_gen current_link_speed;
6265
6266         if (si_pi->force_pcie_gen == AMDGPU_PCIE_GEN_INVALID)
6267                 current_link_speed = si_get_maximum_link_speed(adev, amdgpu_current_state);
6268         else
6269                 current_link_speed = si_pi->force_pcie_gen;
6270
6271         si_pi->force_pcie_gen = AMDGPU_PCIE_GEN_INVALID;
6272         si_pi->pspp_notify_required = false;
6273         if (target_link_speed > current_link_speed) {
6274                 switch (target_link_speed) {
6275 #if defined(CONFIG_ACPI)
6276                 case AMDGPU_PCIE_GEN3:
6277                         if (amdgpu_acpi_pcie_performance_request(adev, PCIE_PERF_REQ_PECI_GEN3, false) == 0)
6278                                 break;
6279                         si_pi->force_pcie_gen = AMDGPU_PCIE_GEN2;
6280                         if (current_link_speed == AMDGPU_PCIE_GEN2)
6281                                 break;
6282                 case AMDGPU_PCIE_GEN2:
6283                         if (amdgpu_acpi_pcie_performance_request(adev, PCIE_PERF_REQ_PECI_GEN2, false) == 0)
6284                                 break;
6285 #endif
6286                 default:
6287                         si_pi->force_pcie_gen = si_get_current_pcie_speed(adev);
6288                         break;
6289                 }
6290         } else {
6291                 if (target_link_speed < current_link_speed)
6292                         si_pi->pspp_notify_required = true;
6293         }
6294 }
6295
6296 static void si_notify_link_speed_change_after_state_change(struct amdgpu_device *adev,
6297                                                            struct amdgpu_ps *amdgpu_new_state,
6298                                                            struct amdgpu_ps *amdgpu_current_state)
6299 {
6300         struct si_power_info *si_pi = si_get_pi(adev);
6301         enum amdgpu_pcie_gen target_link_speed = si_get_maximum_link_speed(adev, amdgpu_new_state);
6302         u8 request;
6303
6304         if (si_pi->pspp_notify_required) {
6305                 if (target_link_speed == AMDGPU_PCIE_GEN3)
6306                         request = PCIE_PERF_REQ_PECI_GEN3;
6307                 else if (target_link_speed == AMDGPU_PCIE_GEN2)
6308                         request = PCIE_PERF_REQ_PECI_GEN2;
6309                 else
6310                         request = PCIE_PERF_REQ_PECI_GEN1;
6311
6312                 if ((request == PCIE_PERF_REQ_PECI_GEN1) &&
6313                     (si_get_current_pcie_speed(adev) > 0))
6314                         return;
6315
6316 #if defined(CONFIG_ACPI)
6317                 amdgpu_acpi_pcie_performance_request(adev, request, false);
6318 #endif
6319         }
6320 }
6321
6322 #if 0
6323 static int si_ds_request(struct amdgpu_device *adev,
6324                          bool ds_status_on, u32 count_write)
6325 {
6326         struct evergreen_power_info *eg_pi = evergreen_get_pi(adev);
6327
6328         if (eg_pi->sclk_deep_sleep) {
6329                 if (ds_status_on)
6330                         return (amdgpu_si_send_msg_to_smc(adev, PPSMC_MSG_CancelThrottleOVRDSCLKDS) ==
6331                                 PPSMC_Result_OK) ?
6332                                 0 : -EINVAL;
6333                 else
6334                         return (amdgpu_si_send_msg_to_smc(adev, PPSMC_MSG_ThrottleOVRDSCLKDS) ==
6335                                 PPSMC_Result_OK) ? 0 : -EINVAL;
6336         }
6337         return 0;
6338 }
6339 #endif
6340
6341 static void si_set_max_cu_value(struct amdgpu_device *adev)
6342 {
6343         struct si_power_info *si_pi = si_get_pi(adev);
6344
6345         if (adev->asic_type == CHIP_VERDE) {
6346                 switch (adev->pdev->device) {
6347                 case 0x6820:
6348                 case 0x6825:
6349                 case 0x6821:
6350                 case 0x6823:
6351                 case 0x6827:
6352                         si_pi->max_cu = 10;
6353                         break;
6354                 case 0x682D:
6355                 case 0x6824:
6356                 case 0x682F:
6357                 case 0x6826:
6358                         si_pi->max_cu = 8;
6359                         break;
6360                 case 0x6828:
6361                 case 0x6830:
6362                 case 0x6831:
6363                 case 0x6838:
6364                 case 0x6839:
6365                 case 0x683D:
6366                         si_pi->max_cu = 10;
6367                         break;
6368                 case 0x683B:
6369                 case 0x683F:
6370                 case 0x6829:
6371                         si_pi->max_cu = 8;
6372                         break;
6373                 default:
6374                         si_pi->max_cu = 0;
6375                         break;
6376                 }
6377         } else {
6378                 si_pi->max_cu = 0;
6379         }
6380 }
6381
6382 static int si_patch_single_dependency_table_based_on_leakage(struct amdgpu_device *adev,
6383                                                              struct amdgpu_clock_voltage_dependency_table *table)
6384 {
6385         u32 i;
6386         int j;
6387         u16 leakage_voltage;
6388
6389         if (table) {
6390                 for (i = 0; i < table->count; i++) {
6391                         switch (si_get_leakage_voltage_from_leakage_index(adev,
6392                                                                           table->entries[i].v,
6393                                                                           &leakage_voltage)) {
6394                         case 0:
6395                                 table->entries[i].v = leakage_voltage;
6396                                 break;
6397                         case -EAGAIN:
6398                                 return -EINVAL;
6399                         case -EINVAL:
6400                         default:
6401                                 break;
6402                         }
6403                 }
6404
6405                 for (j = (table->count - 2); j >= 0; j--) {
6406                         table->entries[j].v = (table->entries[j].v <= table->entries[j + 1].v) ?
6407                                 table->entries[j].v : table->entries[j + 1].v;
6408                 }
6409         }
6410         return 0;
6411 }
6412
6413 static int si_patch_dependency_tables_based_on_leakage(struct amdgpu_device *adev)
6414 {
6415         int ret = 0;
6416
6417         ret = si_patch_single_dependency_table_based_on_leakage(adev,
6418                                                                 &adev->pm.dpm.dyn_state.vddc_dependency_on_sclk);
6419         if (ret)
6420                 DRM_ERROR("Could not patch vddc_on_sclk leakage table\n");
6421         ret = si_patch_single_dependency_table_based_on_leakage(adev,
6422                                                                 &adev->pm.dpm.dyn_state.vddc_dependency_on_mclk);
6423         if (ret)
6424                 DRM_ERROR("Could not patch vddc_on_mclk leakage table\n");
6425         ret = si_patch_single_dependency_table_based_on_leakage(adev,
6426                                                                 &adev->pm.dpm.dyn_state.vddci_dependency_on_mclk);
6427         if (ret)
6428                 DRM_ERROR("Could not patch vddci_on_mclk leakage table\n");
6429         return ret;
6430 }
6431
6432 static void si_set_pcie_lane_width_in_smc(struct amdgpu_device *adev,
6433                                           struct amdgpu_ps *amdgpu_new_state,
6434                                           struct amdgpu_ps *amdgpu_current_state)
6435 {
6436         u32 lane_width;
6437         u32 new_lane_width =
6438                 (amdgpu_new_state->caps & ATOM_PPLIB_PCIE_LINK_WIDTH_MASK) >> ATOM_PPLIB_PCIE_LINK_WIDTH_SHIFT;
6439         u32 current_lane_width =
6440                 (amdgpu_current_state->caps & ATOM_PPLIB_PCIE_LINK_WIDTH_MASK) >> ATOM_PPLIB_PCIE_LINK_WIDTH_SHIFT;
6441
6442         if (new_lane_width != current_lane_width) {
6443                 amdgpu_set_pcie_lanes(adev, new_lane_width);
6444                 lane_width = amdgpu_get_pcie_lanes(adev);
6445                 si_write_smc_soft_register(adev, SI_SMC_SOFT_REGISTER_non_ulv_pcie_link_width, lane_width);
6446         }
6447 }
6448
6449 static void si_dpm_setup_asic(struct amdgpu_device *adev)
6450 {
6451         si_read_clock_registers(adev);
6452         si_enable_acpi_power_management(adev);
6453 }
6454
6455 static int si_thermal_enable_alert(struct amdgpu_device *adev,
6456                                    bool enable)
6457 {
6458         u32 thermal_int = RREG32(CG_THERMAL_INT);
6459
6460         if (enable) {
6461                 PPSMC_Result result;
6462
6463                 thermal_int &= ~(THERM_INT_MASK_HIGH | THERM_INT_MASK_LOW);
6464                 WREG32(CG_THERMAL_INT, thermal_int);
6465                 result = amdgpu_si_send_msg_to_smc(adev, PPSMC_MSG_EnableThermalInterrupt);
6466                 if (result != PPSMC_Result_OK) {
6467                         DRM_DEBUG_KMS("Could not enable thermal interrupts.\n");
6468                         return -EINVAL;
6469                 }
6470         } else {
6471                 thermal_int |= THERM_INT_MASK_HIGH | THERM_INT_MASK_LOW;
6472                 WREG32(CG_THERMAL_INT, thermal_int);
6473         }
6474
6475         return 0;
6476 }
6477
6478 static int si_thermal_set_temperature_range(struct amdgpu_device *adev,
6479                                             int min_temp, int max_temp)
6480 {
6481         int low_temp = 0 * 1000;
6482         int high_temp = 255 * 1000;
6483
6484         if (low_temp < min_temp)
6485                 low_temp = min_temp;
6486         if (high_temp > max_temp)
6487                 high_temp = max_temp;
6488         if (high_temp < low_temp) {
6489                 DRM_ERROR("invalid thermal range: %d - %d\n", low_temp, high_temp);
6490                 return -EINVAL;
6491         }
6492
6493         WREG32_P(CG_THERMAL_INT, DIG_THERM_INTH(high_temp / 1000), ~DIG_THERM_INTH_MASK);
6494         WREG32_P(CG_THERMAL_INT, DIG_THERM_INTL(low_temp / 1000), ~DIG_THERM_INTL_MASK);
6495         WREG32_P(CG_THERMAL_CTRL, DIG_THERM_DPM(high_temp / 1000), ~DIG_THERM_DPM_MASK);
6496
6497         adev->pm.dpm.thermal.min_temp = low_temp;
6498         adev->pm.dpm.thermal.max_temp = high_temp;
6499
6500         return 0;
6501 }
6502
6503 static void si_fan_ctrl_set_static_mode(struct amdgpu_device *adev, u32 mode)
6504 {
6505         struct si_power_info *si_pi = si_get_pi(adev);
6506         u32 tmp;
6507
6508         if (si_pi->fan_ctrl_is_in_default_mode) {
6509                 tmp = (RREG32(CG_FDO_CTRL2) & FDO_PWM_MODE_MASK) >> FDO_PWM_MODE_SHIFT;
6510                 si_pi->fan_ctrl_default_mode = tmp;
6511                 tmp = (RREG32(CG_FDO_CTRL2) & TMIN_MASK) >> TMIN_SHIFT;
6512                 si_pi->t_min = tmp;
6513                 si_pi->fan_ctrl_is_in_default_mode = false;
6514         }
6515
6516         tmp = RREG32(CG_FDO_CTRL2) & ~TMIN_MASK;
6517         tmp |= TMIN(0);
6518         WREG32(CG_FDO_CTRL2, tmp);
6519
6520         tmp = RREG32(CG_FDO_CTRL2) & ~FDO_PWM_MODE_MASK;
6521         tmp |= FDO_PWM_MODE(mode);
6522         WREG32(CG_FDO_CTRL2, tmp);
6523 }
6524
6525 static int si_thermal_setup_fan_table(struct amdgpu_device *adev)
6526 {
6527         struct si_power_info *si_pi = si_get_pi(adev);
6528         PP_SIslands_FanTable fan_table = { FDO_MODE_HARDWARE };
6529         u32 duty100;
6530         u32 t_diff1, t_diff2, pwm_diff1, pwm_diff2;
6531         u16 fdo_min, slope1, slope2;
6532         u32 reference_clock, tmp;
6533         int ret;
6534         u64 tmp64;
6535
6536         if (!si_pi->fan_table_start) {
6537                 adev->pm.dpm.fan.ucode_fan_control = false;
6538                 return 0;
6539         }
6540
6541         duty100 = (RREG32(CG_FDO_CTRL1) & FMAX_DUTY100_MASK) >> FMAX_DUTY100_SHIFT;
6542
6543         if (duty100 == 0) {
6544                 adev->pm.dpm.fan.ucode_fan_control = false;
6545                 return 0;
6546         }
6547
6548         tmp64 = (u64)adev->pm.dpm.fan.pwm_min * duty100;
6549         do_div(tmp64, 10000);
6550         fdo_min = (u16)tmp64;
6551
6552         t_diff1 = adev->pm.dpm.fan.t_med - adev->pm.dpm.fan.t_min;
6553         t_diff2 = adev->pm.dpm.fan.t_high - adev->pm.dpm.fan.t_med;
6554
6555         pwm_diff1 = adev->pm.dpm.fan.pwm_med - adev->pm.dpm.fan.pwm_min;
6556         pwm_diff2 = adev->pm.dpm.fan.pwm_high - adev->pm.dpm.fan.pwm_med;
6557
6558         slope1 = (u16)((50 + ((16 * duty100 * pwm_diff1) / t_diff1)) / 100);
6559         slope2 = (u16)((50 + ((16 * duty100 * pwm_diff2) / t_diff2)) / 100);
6560
6561         fan_table.temp_min = cpu_to_be16((50 + adev->pm.dpm.fan.t_min) / 100);
6562         fan_table.temp_med = cpu_to_be16((50 + adev->pm.dpm.fan.t_med) / 100);
6563         fan_table.temp_max = cpu_to_be16((50 + adev->pm.dpm.fan.t_max) / 100);
6564         fan_table.slope1 = cpu_to_be16(slope1);
6565         fan_table.slope2 = cpu_to_be16(slope2);
6566         fan_table.fdo_min = cpu_to_be16(fdo_min);
6567         fan_table.hys_down = cpu_to_be16(adev->pm.dpm.fan.t_hyst);
6568         fan_table.hys_up = cpu_to_be16(1);
6569         fan_table.hys_slope = cpu_to_be16(1);
6570         fan_table.temp_resp_lim = cpu_to_be16(5);
6571         reference_clock = amdgpu_asic_get_xclk(adev);
6572
6573         fan_table.refresh_period = cpu_to_be32((adev->pm.dpm.fan.cycle_delay *
6574                                                 reference_clock) / 1600);
6575         fan_table.fdo_max = cpu_to_be16((u16)duty100);
6576
6577         tmp = (RREG32(CG_MULT_THERMAL_CTRL) & TEMP_SEL_MASK) >> TEMP_SEL_SHIFT;
6578         fan_table.temp_src = (uint8_t)tmp;
6579
6580         ret = amdgpu_si_copy_bytes_to_smc(adev,
6581                                           si_pi->fan_table_start,
6582                                           (u8 *)(&fan_table),
6583                                           sizeof(fan_table),
6584                                           si_pi->sram_end);
6585
6586         if (ret) {
6587                 DRM_ERROR("Failed to load fan table to the SMC.");
6588                 adev->pm.dpm.fan.ucode_fan_control = false;
6589         }
6590
6591         return ret;
6592 }
6593
6594 static int si_fan_ctrl_start_smc_fan_control(struct amdgpu_device *adev)
6595 {
6596         struct si_power_info *si_pi = si_get_pi(adev);
6597         PPSMC_Result ret;
6598
6599         ret = amdgpu_si_send_msg_to_smc(adev, PPSMC_StartFanControl);
6600         if (ret == PPSMC_Result_OK) {
6601                 si_pi->fan_is_controlled_by_smc = true;
6602                 return 0;
6603         } else {
6604                 return -EINVAL;
6605         }
6606 }
6607
6608 static int si_fan_ctrl_stop_smc_fan_control(struct amdgpu_device *adev)
6609 {
6610         struct si_power_info *si_pi = si_get_pi(adev);
6611         PPSMC_Result ret;
6612
6613         ret = amdgpu_si_send_msg_to_smc(adev, PPSMC_StopFanControl);
6614
6615         if (ret == PPSMC_Result_OK) {
6616                 si_pi->fan_is_controlled_by_smc = false;
6617                 return 0;
6618         } else {
6619                 return -EINVAL;
6620         }
6621 }
6622
6623 static int si_dpm_get_fan_speed_percent(struct amdgpu_device *adev,
6624                                       u32 *speed)
6625 {
6626         u32 duty, duty100;
6627         u64 tmp64;
6628
6629         if (adev->pm.no_fan)
6630                 return -ENOENT;
6631
6632         duty100 = (RREG32(CG_FDO_CTRL1) & FMAX_DUTY100_MASK) >> FMAX_DUTY100_SHIFT;
6633         duty = (RREG32(CG_THERMAL_STATUS) & FDO_PWM_DUTY_MASK) >> FDO_PWM_DUTY_SHIFT;
6634
6635         if (duty100 == 0)
6636                 return -EINVAL;
6637
6638         tmp64 = (u64)duty * 100;
6639         do_div(tmp64, duty100);
6640         *speed = (u32)tmp64;
6641
6642         if (*speed > 100)
6643                 *speed = 100;
6644
6645         return 0;
6646 }
6647
6648 static int si_dpm_set_fan_speed_percent(struct amdgpu_device *adev,
6649                                       u32 speed)
6650 {
6651         struct si_power_info *si_pi = si_get_pi(adev);
6652         u32 tmp;
6653         u32 duty, duty100;
6654         u64 tmp64;
6655
6656         if (adev->pm.no_fan)
6657                 return -ENOENT;
6658
6659         if (si_pi->fan_is_controlled_by_smc)
6660                 return -EINVAL;
6661
6662         if (speed > 100)
6663                 return -EINVAL;
6664
6665         duty100 = (RREG32(CG_FDO_CTRL1) & FMAX_DUTY100_MASK) >> FMAX_DUTY100_SHIFT;
6666
6667         if (duty100 == 0)
6668                 return -EINVAL;
6669
6670         tmp64 = (u64)speed * duty100;
6671         do_div(tmp64, 100);
6672         duty = (u32)tmp64;
6673
6674         tmp = RREG32(CG_FDO_CTRL0) & ~FDO_STATIC_DUTY_MASK;
6675         tmp |= FDO_STATIC_DUTY(duty);
6676         WREG32(CG_FDO_CTRL0, tmp);
6677
6678         return 0;
6679 }
6680
6681 static void si_dpm_set_fan_control_mode(struct amdgpu_device *adev, u32 mode)
6682 {
6683         if (mode) {
6684                 /* stop auto-manage */
6685                 if (adev->pm.dpm.fan.ucode_fan_control)
6686                         si_fan_ctrl_stop_smc_fan_control(adev);
6687                 si_fan_ctrl_set_static_mode(adev, mode);
6688         } else {
6689                 /* restart auto-manage */
6690                 if (adev->pm.dpm.fan.ucode_fan_control)
6691                         si_thermal_start_smc_fan_control(adev);
6692                 else
6693                         si_fan_ctrl_set_default_mode(adev);
6694         }
6695 }
6696
6697 static u32 si_dpm_get_fan_control_mode(struct amdgpu_device *adev)
6698 {
6699         struct si_power_info *si_pi = si_get_pi(adev);
6700         u32 tmp;
6701
6702         if (si_pi->fan_is_controlled_by_smc)
6703                 return 0;
6704
6705         tmp = RREG32(CG_FDO_CTRL2) & FDO_PWM_MODE_MASK;
6706         return (tmp >> FDO_PWM_MODE_SHIFT);
6707 }
6708
6709 #if 0
6710 static int si_fan_ctrl_get_fan_speed_rpm(struct amdgpu_device *adev,
6711                                          u32 *speed)
6712 {
6713         u32 tach_period;
6714         u32 xclk = amdgpu_asic_get_xclk(adev);
6715
6716         if (adev->pm.no_fan)
6717                 return -ENOENT;
6718
6719         if (adev->pm.fan_pulses_per_revolution == 0)
6720                 return -ENOENT;
6721
6722         tach_period = (RREG32(CG_TACH_STATUS) & TACH_PERIOD_MASK) >> TACH_PERIOD_SHIFT;
6723         if (tach_period == 0)
6724                 return -ENOENT;
6725
6726         *speed = 60 * xclk * 10000 / tach_period;
6727
6728         return 0;
6729 }
6730
6731 static int si_fan_ctrl_set_fan_speed_rpm(struct amdgpu_device *adev,
6732                                          u32 speed)
6733 {
6734         u32 tach_period, tmp;
6735         u32 xclk = amdgpu_asic_get_xclk(adev);
6736
6737         if (adev->pm.no_fan)
6738                 return -ENOENT;
6739
6740         if (adev->pm.fan_pulses_per_revolution == 0)
6741                 return -ENOENT;
6742
6743         if ((speed < adev->pm.fan_min_rpm) ||
6744             (speed > adev->pm.fan_max_rpm))
6745                 return -EINVAL;
6746
6747         if (adev->pm.dpm.fan.ucode_fan_control)
6748                 si_fan_ctrl_stop_smc_fan_control(adev);
6749
6750         tach_period = 60 * xclk * 10000 / (8 * speed);
6751         tmp = RREG32(CG_TACH_CTRL) & ~TARGET_PERIOD_MASK;
6752         tmp |= TARGET_PERIOD(tach_period);
6753         WREG32(CG_TACH_CTRL, tmp);
6754
6755         si_fan_ctrl_set_static_mode(adev, FDO_PWM_MODE_STATIC_RPM);
6756
6757         return 0;
6758 }
6759 #endif
6760
6761 static void si_fan_ctrl_set_default_mode(struct amdgpu_device *adev)
6762 {
6763         struct si_power_info *si_pi = si_get_pi(adev);
6764         u32 tmp;
6765
6766         if (!si_pi->fan_ctrl_is_in_default_mode) {
6767                 tmp = RREG32(CG_FDO_CTRL2) & ~FDO_PWM_MODE_MASK;
6768                 tmp |= FDO_PWM_MODE(si_pi->fan_ctrl_default_mode);
6769                 WREG32(CG_FDO_CTRL2, tmp);
6770
6771                 tmp = RREG32(CG_FDO_CTRL2) & ~TMIN_MASK;
6772                 tmp |= TMIN(si_pi->t_min);
6773                 WREG32(CG_FDO_CTRL2, tmp);
6774                 si_pi->fan_ctrl_is_in_default_mode = true;
6775         }
6776 }
6777
6778 static void si_thermal_start_smc_fan_control(struct amdgpu_device *adev)
6779 {
6780         if (adev->pm.dpm.fan.ucode_fan_control) {
6781                 si_fan_ctrl_start_smc_fan_control(adev);
6782                 si_fan_ctrl_set_static_mode(adev, FDO_PWM_MODE_STATIC);
6783         }
6784 }
6785
6786 static void si_thermal_initialize(struct amdgpu_device *adev)
6787 {
6788         u32 tmp;
6789
6790         if (adev->pm.fan_pulses_per_revolution) {
6791                 tmp = RREG32(CG_TACH_CTRL) & ~EDGE_PER_REV_MASK;
6792                 tmp |= EDGE_PER_REV(adev->pm.fan_pulses_per_revolution -1);
6793                 WREG32(CG_TACH_CTRL, tmp);
6794         }
6795
6796         tmp = RREG32(CG_FDO_CTRL2) & ~TACH_PWM_RESP_RATE_MASK;
6797         tmp |= TACH_PWM_RESP_RATE(0x28);
6798         WREG32(CG_FDO_CTRL2, tmp);
6799 }
6800
6801 static int si_thermal_start_thermal_controller(struct amdgpu_device *adev)
6802 {
6803         int ret;
6804
6805         si_thermal_initialize(adev);
6806         ret = si_thermal_set_temperature_range(adev, R600_TEMP_RANGE_MIN, R600_TEMP_RANGE_MAX);
6807         if (ret)
6808                 return ret;
6809         ret = si_thermal_enable_alert(adev, true);
6810         if (ret)
6811                 return ret;
6812         if (adev->pm.dpm.fan.ucode_fan_control) {
6813                 ret = si_halt_smc(adev);
6814                 if (ret)
6815                         return ret;
6816                 ret = si_thermal_setup_fan_table(adev);
6817                 if (ret)
6818                         return ret;
6819                 ret = si_resume_smc(adev);
6820                 if (ret)
6821                         return ret;
6822                 si_thermal_start_smc_fan_control(adev);
6823         }
6824
6825         return 0;
6826 }
6827
6828 static void si_thermal_stop_thermal_controller(struct amdgpu_device *adev)
6829 {
6830         if (!adev->pm.no_fan) {
6831                 si_fan_ctrl_set_default_mode(adev);
6832                 si_fan_ctrl_stop_smc_fan_control(adev);
6833         }
6834 }
6835
6836 static int si_dpm_enable(struct amdgpu_device *adev)
6837 {
6838         struct rv7xx_power_info *pi = rv770_get_pi(adev);
6839         struct evergreen_power_info *eg_pi = evergreen_get_pi(adev);
6840         struct si_power_info *si_pi = si_get_pi(adev);
6841         struct amdgpu_ps *boot_ps = adev->pm.dpm.boot_ps;
6842         int ret;
6843
6844         if (amdgpu_si_is_smc_running(adev))
6845                 return -EINVAL;
6846         if (pi->voltage_control || si_pi->voltage_control_svi2)
6847                 si_enable_voltage_control(adev, true);
6848         if (pi->mvdd_control)
6849                 si_get_mvdd_configuration(adev);
6850         if (pi->voltage_control || si_pi->voltage_control_svi2) {
6851                 ret = si_construct_voltage_tables(adev);
6852                 if (ret) {
6853                         DRM_ERROR("si_construct_voltage_tables failed\n");
6854                         return ret;
6855                 }
6856         }
6857         if (eg_pi->dynamic_ac_timing) {
6858                 ret = si_initialize_mc_reg_table(adev);
6859                 if (ret)
6860                         eg_pi->dynamic_ac_timing = false;
6861         }
6862         if (pi->dynamic_ss)
6863                 si_enable_spread_spectrum(adev, true);
6864         if (pi->thermal_protection)
6865                 si_enable_thermal_protection(adev, true);
6866         si_setup_bsp(adev);
6867         si_program_git(adev);
6868         si_program_tp(adev);
6869         si_program_tpp(adev);
6870         si_program_sstp(adev);
6871         si_enable_display_gap(adev);
6872         si_program_vc(adev);
6873         ret = si_upload_firmware(adev);
6874         if (ret) {
6875                 DRM_ERROR("si_upload_firmware failed\n");
6876                 return ret;
6877         }
6878         ret = si_process_firmware_header(adev);
6879         if (ret) {
6880                 DRM_ERROR("si_process_firmware_header failed\n");
6881                 return ret;
6882         }
6883         ret = si_initial_switch_from_arb_f0_to_f1(adev);
6884         if (ret) {
6885                 DRM_ERROR("si_initial_switch_from_arb_f0_to_f1 failed\n");
6886                 return ret;
6887         }
6888         ret = si_init_smc_table(adev);
6889         if (ret) {
6890                 DRM_ERROR("si_init_smc_table failed\n");
6891                 return ret;
6892         }
6893         ret = si_init_smc_spll_table(adev);
6894         if (ret) {
6895                 DRM_ERROR("si_init_smc_spll_table failed\n");
6896                 return ret;
6897         }
6898         ret = si_init_arb_table_index(adev);
6899         if (ret) {
6900                 DRM_ERROR("si_init_arb_table_index failed\n");
6901                 return ret;
6902         }
6903         if (eg_pi->dynamic_ac_timing) {
6904                 ret = si_populate_mc_reg_table(adev, boot_ps);
6905                 if (ret) {
6906                         DRM_ERROR("si_populate_mc_reg_table failed\n");
6907                         return ret;
6908                 }
6909         }
6910         ret = si_initialize_smc_cac_tables(adev);
6911         if (ret) {
6912                 DRM_ERROR("si_initialize_smc_cac_tables failed\n");
6913                 return ret;
6914         }
6915         ret = si_initialize_hardware_cac_manager(adev);
6916         if (ret) {
6917                 DRM_ERROR("si_initialize_hardware_cac_manager failed\n");
6918                 return ret;
6919         }
6920         ret = si_initialize_smc_dte_tables(adev);
6921         if (ret) {
6922                 DRM_ERROR("si_initialize_smc_dte_tables failed\n");
6923                 return ret;
6924         }
6925         ret = si_populate_smc_tdp_limits(adev, boot_ps);
6926         if (ret) {
6927                 DRM_ERROR("si_populate_smc_tdp_limits failed\n");
6928                 return ret;
6929         }
6930         ret = si_populate_smc_tdp_limits_2(adev, boot_ps);
6931         if (ret) {
6932                 DRM_ERROR("si_populate_smc_tdp_limits_2 failed\n");
6933                 return ret;
6934         }
6935         si_program_response_times(adev);
6936         si_program_ds_registers(adev);
6937         si_dpm_start_smc(adev);
6938         ret = si_notify_smc_display_change(adev, false);
6939         if (ret) {
6940                 DRM_ERROR("si_notify_smc_display_change failed\n");
6941                 return ret;
6942         }
6943         si_enable_sclk_control(adev, true);
6944         si_start_dpm(adev);
6945
6946         si_enable_auto_throttle_source(adev, AMDGPU_DPM_AUTO_THROTTLE_SRC_THERMAL, true);
6947         si_thermal_start_thermal_controller(adev);
6948         ni_update_current_ps(adev, boot_ps);
6949
6950         return 0;
6951 }
6952
6953 static int si_set_temperature_range(struct amdgpu_device *adev)
6954 {
6955         int ret;
6956
6957         ret = si_thermal_enable_alert(adev, false);
6958         if (ret)
6959                 return ret;
6960         ret = si_thermal_set_temperature_range(adev, R600_TEMP_RANGE_MIN, R600_TEMP_RANGE_MAX);
6961         if (ret)
6962                 return ret;
6963         ret = si_thermal_enable_alert(adev, true);
6964         if (ret)
6965                 return ret;
6966
6967         return ret;
6968 }
6969
6970 static void si_dpm_disable(struct amdgpu_device *adev)
6971 {
6972         struct rv7xx_power_info *pi = rv770_get_pi(adev);
6973         struct amdgpu_ps *boot_ps = adev->pm.dpm.boot_ps;
6974
6975         if (!amdgpu_si_is_smc_running(adev))
6976                 return;
6977         si_thermal_stop_thermal_controller(adev);
6978         si_disable_ulv(adev);
6979         si_clear_vc(adev);
6980         if (pi->thermal_protection)
6981                 si_enable_thermal_protection(adev, false);
6982         si_enable_power_containment(adev, boot_ps, false);
6983         si_enable_smc_cac(adev, boot_ps, false);
6984         si_enable_spread_spectrum(adev, false);
6985         si_enable_auto_throttle_source(adev, AMDGPU_DPM_AUTO_THROTTLE_SRC_THERMAL, false);
6986         si_stop_dpm(adev);
6987         si_reset_to_default(adev);
6988         si_dpm_stop_smc(adev);
6989         si_force_switch_to_arb_f0(adev);
6990
6991         ni_update_current_ps(adev, boot_ps);
6992 }
6993
6994 static int si_dpm_pre_set_power_state(struct amdgpu_device *adev)
6995 {
6996         struct evergreen_power_info *eg_pi = evergreen_get_pi(adev);
6997         struct amdgpu_ps requested_ps = *adev->pm.dpm.requested_ps;
6998         struct amdgpu_ps *new_ps = &requested_ps;
6999
7000         ni_update_requested_ps(adev, new_ps);
7001         si_apply_state_adjust_rules(adev, &eg_pi->requested_rps);
7002
7003         return 0;
7004 }
7005
7006 static int si_power_control_set_level(struct amdgpu_device *adev)
7007 {
7008         struct amdgpu_ps *new_ps = adev->pm.dpm.requested_ps;
7009         int ret;
7010
7011         ret = si_restrict_performance_levels_before_switch(adev);
7012         if (ret)
7013                 return ret;
7014         ret = si_halt_smc(adev);
7015         if (ret)
7016                 return ret;
7017         ret = si_populate_smc_tdp_limits(adev, new_ps);
7018         if (ret)
7019                 return ret;
7020         ret = si_populate_smc_tdp_limits_2(adev, new_ps);
7021         if (ret)
7022                 return ret;
7023         ret = si_resume_smc(adev);
7024         if (ret)
7025                 return ret;
7026         ret = si_set_sw_state(adev);
7027         if (ret)
7028                 return ret;
7029         return 0;
7030 }
7031
7032 static int si_dpm_set_power_state(struct amdgpu_device *adev)
7033 {
7034         struct evergreen_power_info *eg_pi = evergreen_get_pi(adev);
7035         struct amdgpu_ps *new_ps = &eg_pi->requested_rps;
7036         struct amdgpu_ps *old_ps = &eg_pi->current_rps;
7037         int ret;
7038
7039         ret = si_disable_ulv(adev);
7040         if (ret) {
7041                 DRM_ERROR("si_disable_ulv failed\n");
7042                 return ret;
7043         }
7044         ret = si_restrict_performance_levels_before_switch(adev);
7045         if (ret) {
7046                 DRM_ERROR("si_restrict_performance_levels_before_switch failed\n");
7047                 return ret;
7048         }
7049         if (eg_pi->pcie_performance_request)
7050                 si_request_link_speed_change_before_state_change(adev, new_ps, old_ps);
7051         ni_set_uvd_clock_before_set_eng_clock(adev, new_ps, old_ps);
7052         ret = si_enable_power_containment(adev, new_ps, false);
7053         if (ret) {
7054                 DRM_ERROR("si_enable_power_containment failed\n");
7055                 return ret;
7056         }
7057         ret = si_enable_smc_cac(adev, new_ps, false);
7058         if (ret) {
7059                 DRM_ERROR("si_enable_smc_cac failed\n");
7060                 return ret;
7061         }
7062         ret = si_halt_smc(adev);
7063         if (ret) {
7064                 DRM_ERROR("si_halt_smc failed\n");
7065                 return ret;
7066         }
7067         ret = si_upload_sw_state(adev, new_ps);
7068         if (ret) {
7069                 DRM_ERROR("si_upload_sw_state failed\n");
7070                 return ret;
7071         }
7072         ret = si_upload_smc_data(adev);
7073         if (ret) {
7074                 DRM_ERROR("si_upload_smc_data failed\n");
7075                 return ret;
7076         }
7077         ret = si_upload_ulv_state(adev);
7078         if (ret) {
7079                 DRM_ERROR("si_upload_ulv_state failed\n");
7080                 return ret;
7081         }
7082         if (eg_pi->dynamic_ac_timing) {
7083                 ret = si_upload_mc_reg_table(adev, new_ps);
7084                 if (ret) {
7085                         DRM_ERROR("si_upload_mc_reg_table failed\n");
7086                         return ret;
7087                 }
7088         }
7089         ret = si_program_memory_timing_parameters(adev, new_ps);
7090         if (ret) {
7091                 DRM_ERROR("si_program_memory_timing_parameters failed\n");
7092                 return ret;
7093         }
7094         si_set_pcie_lane_width_in_smc(adev, new_ps, old_ps);
7095
7096         ret = si_resume_smc(adev);
7097         if (ret) {
7098                 DRM_ERROR("si_resume_smc failed\n");
7099                 return ret;
7100         }
7101         ret = si_set_sw_state(adev);
7102         if (ret) {
7103                 DRM_ERROR("si_set_sw_state failed\n");
7104                 return ret;
7105         }
7106         ni_set_uvd_clock_after_set_eng_clock(adev, new_ps, old_ps);
7107         if (eg_pi->pcie_performance_request)
7108                 si_notify_link_speed_change_after_state_change(adev, new_ps, old_ps);
7109         ret = si_set_power_state_conditionally_enable_ulv(adev, new_ps);
7110         if (ret) {
7111                 DRM_ERROR("si_set_power_state_conditionally_enable_ulv failed\n");
7112                 return ret;
7113         }
7114         ret = si_enable_smc_cac(adev, new_ps, true);
7115         if (ret) {
7116                 DRM_ERROR("si_enable_smc_cac failed\n");
7117                 return ret;
7118         }
7119         ret = si_enable_power_containment(adev, new_ps, true);
7120         if (ret) {
7121                 DRM_ERROR("si_enable_power_containment failed\n");
7122                 return ret;
7123         }
7124
7125         ret = si_power_control_set_level(adev);
7126         if (ret) {
7127                 DRM_ERROR("si_power_control_set_level failed\n");
7128                 return ret;
7129         }
7130
7131         return 0;
7132 }
7133
7134 static void si_dpm_post_set_power_state(struct amdgpu_device *adev)
7135 {
7136         struct evergreen_power_info *eg_pi = evergreen_get_pi(adev);
7137         struct amdgpu_ps *new_ps = &eg_pi->requested_rps;
7138
7139         ni_update_current_ps(adev, new_ps);
7140 }
7141
7142 #if 0
7143 void si_dpm_reset_asic(struct amdgpu_device *adev)
7144 {
7145         si_restrict_performance_levels_before_switch(adev);
7146         si_disable_ulv(adev);
7147         si_set_boot_state(adev);
7148 }
7149 #endif
7150
7151 static void si_dpm_display_configuration_changed(struct amdgpu_device *adev)
7152 {
7153         si_program_display_gap(adev);
7154 }
7155
7156
7157 static void si_parse_pplib_non_clock_info(struct amdgpu_device *adev,
7158                                           struct amdgpu_ps *rps,
7159                                           struct _ATOM_PPLIB_NONCLOCK_INFO *non_clock_info,
7160                                           u8 table_rev)
7161 {
7162         rps->caps = le32_to_cpu(non_clock_info->ulCapsAndSettings);
7163         rps->class = le16_to_cpu(non_clock_info->usClassification);
7164         rps->class2 = le16_to_cpu(non_clock_info->usClassification2);
7165
7166         if (ATOM_PPLIB_NONCLOCKINFO_VER1 < table_rev) {
7167                 rps->vclk = le32_to_cpu(non_clock_info->ulVCLK);
7168                 rps->dclk = le32_to_cpu(non_clock_info->ulDCLK);
7169         } else if (r600_is_uvd_state(rps->class, rps->class2)) {
7170                 rps->vclk = RV770_DEFAULT_VCLK_FREQ;
7171                 rps->dclk = RV770_DEFAULT_DCLK_FREQ;
7172         } else {
7173                 rps->vclk = 0;
7174                 rps->dclk = 0;
7175         }
7176
7177         if (rps->class & ATOM_PPLIB_CLASSIFICATION_BOOT)
7178                 adev->pm.dpm.boot_ps = rps;
7179         if (rps->class & ATOM_PPLIB_CLASSIFICATION_UVDSTATE)
7180                 adev->pm.dpm.uvd_ps = rps;
7181 }
7182
7183 static void si_parse_pplib_clock_info(struct amdgpu_device *adev,
7184                                       struct amdgpu_ps *rps, int index,
7185                                       union pplib_clock_info *clock_info)
7186 {
7187         struct rv7xx_power_info *pi = rv770_get_pi(adev);
7188         struct evergreen_power_info *eg_pi = evergreen_get_pi(adev);
7189         struct si_power_info *si_pi = si_get_pi(adev);
7190         struct  si_ps *ps = si_get_ps(rps);
7191         u16 leakage_voltage;
7192         struct rv7xx_pl *pl = &ps->performance_levels[index];
7193         int ret;
7194
7195         ps->performance_level_count = index + 1;
7196
7197         pl->sclk = le16_to_cpu(clock_info->si.usEngineClockLow);
7198         pl->sclk |= clock_info->si.ucEngineClockHigh << 16;
7199         pl->mclk = le16_to_cpu(clock_info->si.usMemoryClockLow);
7200         pl->mclk |= clock_info->si.ucMemoryClockHigh << 16;
7201
7202         pl->vddc = le16_to_cpu(clock_info->si.usVDDC);
7203         pl->vddci = le16_to_cpu(clock_info->si.usVDDCI);
7204         pl->flags = le32_to_cpu(clock_info->si.ulFlags);
7205         pl->pcie_gen = r600_get_pcie_gen_support(adev,
7206                                                  si_pi->sys_pcie_mask,
7207                                                  si_pi->boot_pcie_gen,
7208                                                  clock_info->si.ucPCIEGen);
7209
7210         /* patch up vddc if necessary */
7211         ret = si_get_leakage_voltage_from_leakage_index(adev, pl->vddc,
7212                                                         &leakage_voltage);
7213         if (ret == 0)
7214                 pl->vddc = leakage_voltage;
7215
7216         if (rps->class & ATOM_PPLIB_CLASSIFICATION_ACPI) {
7217                 pi->acpi_vddc = pl->vddc;
7218                 eg_pi->acpi_vddci = pl->vddci;
7219                 si_pi->acpi_pcie_gen = pl->pcie_gen;
7220         }
7221
7222         if ((rps->class2 & ATOM_PPLIB_CLASSIFICATION2_ULV) &&
7223             index == 0) {
7224                 /* XXX disable for A0 tahiti */
7225                 si_pi->ulv.supported = false;
7226                 si_pi->ulv.pl = *pl;
7227                 si_pi->ulv.one_pcie_lane_in_ulv = false;
7228                 si_pi->ulv.volt_change_delay = SISLANDS_ULVVOLTAGECHANGEDELAY_DFLT;
7229                 si_pi->ulv.cg_ulv_parameter = SISLANDS_CGULVPARAMETER_DFLT;
7230                 si_pi->ulv.cg_ulv_control = SISLANDS_CGULVCONTROL_DFLT;
7231         }
7232
7233         if (pi->min_vddc_in_table > pl->vddc)
7234                 pi->min_vddc_in_table = pl->vddc;
7235
7236         if (pi->max_vddc_in_table < pl->vddc)
7237                 pi->max_vddc_in_table = pl->vddc;
7238
7239         /* patch up boot state */
7240         if (rps->class & ATOM_PPLIB_CLASSIFICATION_BOOT) {
7241                 u16 vddc, vddci, mvdd;
7242                 amdgpu_atombios_get_default_voltages(adev, &vddc, &vddci, &mvdd);
7243                 pl->mclk = adev->clock.default_mclk;
7244                 pl->sclk = adev->clock.default_sclk;
7245                 pl->vddc = vddc;
7246                 pl->vddci = vddci;
7247                 si_pi->mvdd_bootup_value = mvdd;
7248         }
7249
7250         if ((rps->class & ATOM_PPLIB_CLASSIFICATION_UI_MASK) ==
7251             ATOM_PPLIB_CLASSIFICATION_UI_PERFORMANCE) {
7252                 adev->pm.dpm.dyn_state.max_clock_voltage_on_ac.sclk = pl->sclk;
7253                 adev->pm.dpm.dyn_state.max_clock_voltage_on_ac.mclk = pl->mclk;
7254                 adev->pm.dpm.dyn_state.max_clock_voltage_on_ac.vddc = pl->vddc;
7255                 adev->pm.dpm.dyn_state.max_clock_voltage_on_ac.vddci = pl->vddci;
7256         }
7257 }
7258
7259 union pplib_power_state {
7260         struct _ATOM_PPLIB_STATE v1;
7261         struct _ATOM_PPLIB_STATE_V2 v2;
7262 };
7263
7264 static int si_parse_power_table(struct amdgpu_device *adev)
7265 {
7266         struct amdgpu_mode_info *mode_info = &adev->mode_info;
7267         struct _ATOM_PPLIB_NONCLOCK_INFO *non_clock_info;
7268         union pplib_power_state *power_state;
7269         int i, j, k, non_clock_array_index, clock_array_index;
7270         union pplib_clock_info *clock_info;
7271         struct _StateArray *state_array;
7272         struct _ClockInfoArray *clock_info_array;
7273         struct _NonClockInfoArray *non_clock_info_array;
7274         union power_info *power_info;
7275         int index = GetIndexIntoMasterTable(DATA, PowerPlayInfo);
7276         u16 data_offset;
7277         u8 frev, crev;
7278         u8 *power_state_offset;
7279         struct  si_ps *ps;
7280
7281         if (!amdgpu_atom_parse_data_header(mode_info->atom_context, index, NULL,
7282                                    &frev, &crev, &data_offset))
7283                 return -EINVAL;
7284         power_info = (union power_info *)(mode_info->atom_context->bios + data_offset);
7285
7286         amdgpu_add_thermal_controller(adev);
7287
7288         state_array = (struct _StateArray *)
7289                 (mode_info->atom_context->bios + data_offset +
7290                  le16_to_cpu(power_info->pplib.usStateArrayOffset));
7291         clock_info_array = (struct _ClockInfoArray *)
7292                 (mode_info->atom_context->bios + data_offset +
7293                  le16_to_cpu(power_info->pplib.usClockInfoArrayOffset));
7294         non_clock_info_array = (struct _NonClockInfoArray *)
7295                 (mode_info->atom_context->bios + data_offset +
7296                  le16_to_cpu(power_info->pplib.usNonClockInfoArrayOffset));
7297
7298         adev->pm.dpm.ps = kzalloc(sizeof(struct amdgpu_ps) *
7299                                   state_array->ucNumEntries, GFP_KERNEL);
7300         if (!adev->pm.dpm.ps)
7301                 return -ENOMEM;
7302         power_state_offset = (u8 *)state_array->states;
7303         for (i = 0; i < state_array->ucNumEntries; i++) {
7304                 u8 *idx;
7305                 power_state = (union pplib_power_state *)power_state_offset;
7306                 non_clock_array_index = power_state->v2.nonClockInfoIndex;
7307                 non_clock_info = (struct _ATOM_PPLIB_NONCLOCK_INFO *)
7308                         &non_clock_info_array->nonClockInfo[non_clock_array_index];
7309                 ps = kzalloc(sizeof(struct  si_ps), GFP_KERNEL);
7310                 if (ps == NULL) {
7311                         kfree(adev->pm.dpm.ps);
7312                         return -ENOMEM;
7313                 }
7314                 adev->pm.dpm.ps[i].ps_priv = ps;
7315                 si_parse_pplib_non_clock_info(adev, &adev->pm.dpm.ps[i],
7316                                               non_clock_info,
7317                                               non_clock_info_array->ucEntrySize);
7318                 k = 0;
7319                 idx = (u8 *)&power_state->v2.clockInfoIndex[0];
7320                 for (j = 0; j < power_state->v2.ucNumDPMLevels; j++) {
7321                         clock_array_index = idx[j];
7322                         if (clock_array_index >= clock_info_array->ucNumEntries)
7323                                 continue;
7324                         if (k >= SISLANDS_MAX_HARDWARE_POWERLEVELS)
7325                                 break;
7326                         clock_info = (union pplib_clock_info *)
7327                                 ((u8 *)&clock_info_array->clockInfo[0] +
7328                                  (clock_array_index * clock_info_array->ucEntrySize));
7329                         si_parse_pplib_clock_info(adev,
7330                                                   &adev->pm.dpm.ps[i], k,
7331                                                   clock_info);
7332                         k++;
7333                 }
7334                 power_state_offset += 2 + power_state->v2.ucNumDPMLevels;
7335         }
7336         adev->pm.dpm.num_ps = state_array->ucNumEntries;
7337
7338         /* fill in the vce power states */
7339         for (i = 0; i < adev->pm.dpm.num_of_vce_states; i++) {
7340                 u32 sclk, mclk;
7341                 clock_array_index = adev->pm.dpm.vce_states[i].clk_idx;
7342                 clock_info = (union pplib_clock_info *)
7343                         &clock_info_array->clockInfo[clock_array_index * clock_info_array->ucEntrySize];
7344                 sclk = le16_to_cpu(clock_info->si.usEngineClockLow);
7345                 sclk |= clock_info->si.ucEngineClockHigh << 16;
7346                 mclk = le16_to_cpu(clock_info->si.usMemoryClockLow);
7347                 mclk |= clock_info->si.ucMemoryClockHigh << 16;
7348                 adev->pm.dpm.vce_states[i].sclk = sclk;
7349                 adev->pm.dpm.vce_states[i].mclk = mclk;
7350         }
7351
7352         return 0;
7353 }
7354
7355 static int si_dpm_init(struct amdgpu_device *adev)
7356 {
7357         struct rv7xx_power_info *pi;
7358         struct evergreen_power_info *eg_pi;
7359         struct ni_power_info *ni_pi;
7360         struct si_power_info *si_pi;
7361         struct atom_clock_dividers dividers;
7362         int ret;
7363         u32 mask;
7364
7365         si_pi = kzalloc(sizeof(struct si_power_info), GFP_KERNEL);
7366         if (si_pi == NULL)
7367                 return -ENOMEM;
7368         adev->pm.dpm.priv = si_pi;
7369         ni_pi = &si_pi->ni;
7370         eg_pi = &ni_pi->eg;
7371         pi = &eg_pi->rv7xx;
7372
7373         ret = drm_pcie_get_speed_cap_mask(adev->ddev, &mask);
7374         if (ret)
7375                 si_pi->sys_pcie_mask = 0;
7376         else
7377                 si_pi->sys_pcie_mask = mask;
7378         si_pi->force_pcie_gen = AMDGPU_PCIE_GEN_INVALID;
7379         si_pi->boot_pcie_gen = si_get_current_pcie_speed(adev);
7380
7381         si_set_max_cu_value(adev);
7382
7383         rv770_get_max_vddc(adev);
7384         si_get_leakage_vddc(adev);
7385         si_patch_dependency_tables_based_on_leakage(adev);
7386
7387         pi->acpi_vddc = 0;
7388         eg_pi->acpi_vddci = 0;
7389         pi->min_vddc_in_table = 0;
7390         pi->max_vddc_in_table = 0;
7391
7392         ret = amdgpu_get_platform_caps(adev);
7393         if (ret)
7394                 return ret;
7395
7396         ret = amdgpu_parse_extended_power_table(adev);
7397         if (ret)
7398                 return ret;
7399
7400         ret = si_parse_power_table(adev);
7401         if (ret)
7402                 return ret;
7403
7404         adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries =
7405                 kzalloc(4 * sizeof(struct amdgpu_clock_voltage_dependency_entry), GFP_KERNEL);
7406         if (!adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries) {
7407                 amdgpu_free_extended_power_table(adev);
7408                 return -ENOMEM;
7409         }
7410         adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.count = 4;
7411         adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[0].clk = 0;
7412         adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[0].v = 0;
7413         adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[1].clk = 36000;
7414         adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[1].v = 720;
7415         adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[2].clk = 54000;
7416         adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[2].v = 810;
7417         adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[3].clk = 72000;
7418         adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[3].v = 900;
7419
7420         if (adev->pm.dpm.voltage_response_time == 0)
7421                 adev->pm.dpm.voltage_response_time = R600_VOLTAGERESPONSETIME_DFLT;
7422         if (adev->pm.dpm.backbias_response_time == 0)
7423                 adev->pm.dpm.backbias_response_time = R600_BACKBIASRESPONSETIME_DFLT;
7424
7425         ret = amdgpu_atombios_get_clock_dividers(adev, COMPUTE_ENGINE_PLL_PARAM,
7426                                              0, false, &dividers);
7427         if (ret)
7428                 pi->ref_div = dividers.ref_div + 1;
7429         else
7430                 pi->ref_div = R600_REFERENCEDIVIDER_DFLT;
7431
7432         eg_pi->smu_uvd_hs = false;
7433
7434         pi->mclk_strobe_mode_threshold = 40000;
7435         if (si_is_special_1gb_platform(adev))
7436                 pi->mclk_stutter_mode_threshold = 0;
7437         else
7438                 pi->mclk_stutter_mode_threshold = pi->mclk_strobe_mode_threshold;
7439         pi->mclk_edc_enable_threshold = 40000;
7440         eg_pi->mclk_edc_wr_enable_threshold = 40000;
7441
7442         ni_pi->mclk_rtt_mode_threshold = eg_pi->mclk_edc_wr_enable_threshold;
7443
7444         pi->voltage_control =
7445                 amdgpu_atombios_is_voltage_gpio(adev, SET_VOLTAGE_TYPE_ASIC_VDDC,
7446                                             VOLTAGE_OBJ_GPIO_LUT);
7447         if (!pi->voltage_control) {
7448                 si_pi->voltage_control_svi2 =
7449                         amdgpu_atombios_is_voltage_gpio(adev, SET_VOLTAGE_TYPE_ASIC_VDDC,
7450                                                     VOLTAGE_OBJ_SVID2);
7451                 if (si_pi->voltage_control_svi2)
7452                         amdgpu_atombios_get_svi2_info(adev, SET_VOLTAGE_TYPE_ASIC_VDDC,
7453                                                   &si_pi->svd_gpio_id, &si_pi->svc_gpio_id);
7454         }
7455
7456         pi->mvdd_control =
7457                 amdgpu_atombios_is_voltage_gpio(adev, SET_VOLTAGE_TYPE_ASIC_MVDDC,
7458                                             VOLTAGE_OBJ_GPIO_LUT);
7459
7460         eg_pi->vddci_control =
7461                 amdgpu_atombios_is_voltage_gpio(adev, SET_VOLTAGE_TYPE_ASIC_VDDCI,
7462                                             VOLTAGE_OBJ_GPIO_LUT);
7463         if (!eg_pi->vddci_control)
7464                 si_pi->vddci_control_svi2 =
7465                         amdgpu_atombios_is_voltage_gpio(adev, SET_VOLTAGE_TYPE_ASIC_VDDCI,
7466                                                     VOLTAGE_OBJ_SVID2);
7467
7468         si_pi->vddc_phase_shed_control =
7469                 amdgpu_atombios_is_voltage_gpio(adev, SET_VOLTAGE_TYPE_ASIC_VDDC,
7470                                             VOLTAGE_OBJ_PHASE_LUT);
7471
7472         rv770_get_engine_memory_ss(adev);
7473
7474         pi->asi = RV770_ASI_DFLT;
7475         pi->pasi = CYPRESS_HASI_DFLT;
7476         pi->vrc = SISLANDS_VRC_DFLT;
7477
7478         pi->gfx_clock_gating = true;
7479
7480         eg_pi->sclk_deep_sleep = true;
7481         si_pi->sclk_deep_sleep_above_low = false;
7482
7483         if (adev->pm.int_thermal_type != THERMAL_TYPE_NONE)
7484                 pi->thermal_protection = true;
7485         else
7486                 pi->thermal_protection = false;
7487
7488         eg_pi->dynamic_ac_timing = true;
7489
7490         eg_pi->light_sleep = true;
7491 #if defined(CONFIG_ACPI)
7492         eg_pi->pcie_performance_request =
7493                 amdgpu_acpi_is_pcie_performance_request_supported(adev);
7494 #else
7495         eg_pi->pcie_performance_request = false;
7496 #endif
7497
7498         si_pi->sram_end = SMC_RAM_END;
7499
7500         adev->pm.dpm.dyn_state.mclk_sclk_ratio = 4;
7501         adev->pm.dpm.dyn_state.sclk_mclk_delta = 15000;
7502         adev->pm.dpm.dyn_state.vddc_vddci_delta = 200;
7503         adev->pm.dpm.dyn_state.valid_sclk_values.count = 0;
7504         adev->pm.dpm.dyn_state.valid_sclk_values.values = NULL;
7505         adev->pm.dpm.dyn_state.valid_mclk_values.count = 0;
7506         adev->pm.dpm.dyn_state.valid_mclk_values.values = NULL;
7507
7508         si_initialize_powertune_defaults(adev);
7509
7510         /* make sure dc limits are valid */
7511         if ((adev->pm.dpm.dyn_state.max_clock_voltage_on_dc.sclk == 0) ||
7512             (adev->pm.dpm.dyn_state.max_clock_voltage_on_dc.mclk == 0))
7513                 adev->pm.dpm.dyn_state.max_clock_voltage_on_dc =
7514                         adev->pm.dpm.dyn_state.max_clock_voltage_on_ac;
7515
7516         si_pi->fan_ctrl_is_in_default_mode = true;
7517
7518         return 0;
7519 }
7520
7521 static void si_dpm_fini(struct amdgpu_device *adev)
7522 {
7523         int i;
7524
7525         if (adev->pm.dpm.ps)
7526                 for (i = 0; i < adev->pm.dpm.num_ps; i++)
7527                         kfree(adev->pm.dpm.ps[i].ps_priv);
7528         kfree(adev->pm.dpm.ps);
7529         kfree(adev->pm.dpm.priv);
7530         kfree(adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries);
7531         amdgpu_free_extended_power_table(adev);
7532 }
7533
7534 static void si_dpm_debugfs_print_current_performance_level(struct amdgpu_device *adev,
7535                                                     struct seq_file *m)
7536 {
7537         struct evergreen_power_info *eg_pi = evergreen_get_pi(adev);
7538         struct amdgpu_ps *rps = &eg_pi->current_rps;
7539         struct  si_ps *ps = si_get_ps(rps);
7540         struct rv7xx_pl *pl;
7541         u32 current_index =
7542                 (RREG32(TARGET_AND_CURRENT_PROFILE_INDEX) & CURRENT_STATE_INDEX_MASK) >>
7543                 CURRENT_STATE_INDEX_SHIFT;
7544
7545         if (current_index >= ps->performance_level_count) {
7546                 seq_printf(m, "invalid dpm profile %d\n", current_index);
7547         } else {
7548                 pl = &ps->performance_levels[current_index];
7549                 seq_printf(m, "uvd    vclk: %d dclk: %d\n", rps->vclk, rps->dclk);
7550                 seq_printf(m, "power level %d    sclk: %u mclk: %u vddc: %u vddci: %u pcie gen: %u\n",
7551                            current_index, pl->sclk, pl->mclk, pl->vddc, pl->vddci, pl->pcie_gen + 1);
7552         }
7553 }
7554
7555 static int si_dpm_set_interrupt_state(struct amdgpu_device *adev,
7556                                       struct amdgpu_irq_src *source,
7557                                       unsigned type,
7558                                       enum amdgpu_interrupt_state state)
7559 {
7560         u32 cg_thermal_int;
7561
7562         switch (type) {
7563         case AMDGPU_THERMAL_IRQ_LOW_TO_HIGH:
7564                 switch (state) {
7565                 case AMDGPU_IRQ_STATE_DISABLE:
7566                         cg_thermal_int = RREG32_SMC(CG_THERMAL_INT);
7567                         cg_thermal_int |= THERM_INT_MASK_HIGH;
7568                         WREG32_SMC(CG_THERMAL_INT, cg_thermal_int);
7569                         break;
7570                 case AMDGPU_IRQ_STATE_ENABLE:
7571                         cg_thermal_int = RREG32_SMC(CG_THERMAL_INT);
7572                         cg_thermal_int &= ~THERM_INT_MASK_HIGH;
7573                         WREG32_SMC(CG_THERMAL_INT, cg_thermal_int);
7574                         break;
7575                 default:
7576                         break;
7577                 }
7578                 break;
7579
7580         case AMDGPU_THERMAL_IRQ_HIGH_TO_LOW:
7581                 switch (state) {
7582                 case AMDGPU_IRQ_STATE_DISABLE:
7583                         cg_thermal_int = RREG32_SMC(CG_THERMAL_INT);
7584                         cg_thermal_int |= THERM_INT_MASK_LOW;
7585                         WREG32_SMC(CG_THERMAL_INT, cg_thermal_int);
7586                         break;
7587                 case AMDGPU_IRQ_STATE_ENABLE:
7588                         cg_thermal_int = RREG32_SMC(CG_THERMAL_INT);
7589                         cg_thermal_int &= ~THERM_INT_MASK_LOW;
7590                         WREG32_SMC(CG_THERMAL_INT, cg_thermal_int);
7591                         break;
7592                 default:
7593                         break;
7594                 }
7595                 break;
7596
7597         default:
7598                 break;
7599         }
7600         return 0;
7601 }
7602
7603 static int si_dpm_process_interrupt(struct amdgpu_device *adev,
7604                                     struct amdgpu_irq_src *source,
7605                                     struct amdgpu_iv_entry *entry)
7606 {
7607         bool queue_thermal = false;
7608
7609         if (entry == NULL)
7610                 return -EINVAL;
7611
7612         switch (entry->src_id) {
7613         case 230: /* thermal low to high */
7614                 DRM_DEBUG("IH: thermal low to high\n");
7615                 adev->pm.dpm.thermal.high_to_low = false;
7616                 queue_thermal = true;
7617                 break;
7618         case 231: /* thermal high to low */
7619                 DRM_DEBUG("IH: thermal high to low\n");
7620                 adev->pm.dpm.thermal.high_to_low = true;
7621                 queue_thermal = true;
7622                 break;
7623         default:
7624                 break;
7625         }
7626
7627         if (queue_thermal)
7628                 schedule_work(&adev->pm.dpm.thermal.work);
7629
7630         return 0;
7631 }
7632
7633 static int si_dpm_late_init(void *handle)
7634 {
7635         int ret;
7636         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
7637
7638         if (!amdgpu_dpm)
7639                 return 0;
7640
7641         /* init the sysfs and debugfs files late */
7642         ret = amdgpu_pm_sysfs_init(adev);
7643         if (ret)
7644                 return ret;
7645
7646         ret = si_set_temperature_range(adev);
7647         if (ret)
7648                 return ret;
7649 #if 0 //TODO ?
7650         si_dpm_powergate_uvd(adev, true);
7651 #endif
7652         return 0;
7653 }
7654
7655 /**
7656  * si_dpm_init_microcode - load ucode images from disk
7657  *
7658  * @adev: amdgpu_device pointer
7659  *
7660  * Use the firmware interface to load the ucode images into
7661  * the driver (not loaded into hw).
7662  * Returns 0 on success, error on failure.
7663  */
7664 static int si_dpm_init_microcode(struct amdgpu_device *adev)
7665 {
7666         const char *chip_name;
7667         char fw_name[30];
7668         int err;
7669
7670         DRM_DEBUG("\n");
7671         switch (adev->asic_type) {
7672         case CHIP_TAHITI:
7673                 chip_name = "tahiti";
7674                 break;
7675         case CHIP_PITCAIRN:
7676                 if ((adev->pdev->revision == 0x81) &&
7677                     ((adev->pdev->device == 0x6810) ||
7678                     (adev->pdev->device == 0x6811)))
7679                         chip_name = "pitcairn_k";
7680                 else
7681                         chip_name = "pitcairn";
7682                 break;
7683         case CHIP_VERDE:
7684                 if (((adev->pdev->device == 0x6820) &&
7685                         ((adev->pdev->revision == 0x81) ||
7686                         (adev->pdev->revision == 0x83))) ||
7687                     ((adev->pdev->device == 0x6821) &&
7688                         ((adev->pdev->revision == 0x83) ||
7689                         (adev->pdev->revision == 0x87))) ||
7690                     ((adev->pdev->revision == 0x87) &&
7691                         ((adev->pdev->device == 0x6823) ||
7692                         (adev->pdev->device == 0x682b))))
7693                         chip_name = "verde_k";
7694                 else
7695                         chip_name = "verde";
7696                 break;
7697         case CHIP_OLAND:
7698                 if (((adev->pdev->revision == 0x81) &&
7699                         ((adev->pdev->device == 0x6600) ||
7700                         (adev->pdev->device == 0x6604) ||
7701                         (adev->pdev->device == 0x6605) ||
7702                         (adev->pdev->device == 0x6610))) ||
7703                     ((adev->pdev->revision == 0x83) &&
7704                         (adev->pdev->device == 0x6610)))
7705                         chip_name = "oland_k";
7706                 else
7707                         chip_name = "oland";
7708                 break;
7709         case CHIP_HAINAN:
7710                 if (((adev->pdev->revision == 0x81) &&
7711                         (adev->pdev->device == 0x6660)) ||
7712                     ((adev->pdev->revision == 0x83) &&
7713                         ((adev->pdev->device == 0x6660) ||
7714                         (adev->pdev->device == 0x6663) ||
7715                         (adev->pdev->device == 0x6665) ||
7716                         (adev->pdev->device == 0x6667))) ||
7717                     ((adev->pdev->revision == 0xc3) &&
7718                         (adev->pdev->device == 0x6665)))
7719                         chip_name = "hainan_k";
7720                 else
7721                         chip_name = "hainan";
7722                 break;
7723         default: BUG();
7724         }
7725
7726         snprintf(fw_name, sizeof(fw_name), "radeon/%s_smc.bin", chip_name);
7727         err = request_firmware(&adev->pm.fw, fw_name, adev->dev);
7728         if (err)
7729                 goto out;
7730         err = amdgpu_ucode_validate(adev->pm.fw);
7731
7732 out:
7733         if (err) {
7734                 DRM_ERROR("si_smc: Failed to load firmware. err = %d\"%s\"\n",
7735                           err, fw_name);
7736                 release_firmware(adev->pm.fw);
7737                 adev->pm.fw = NULL;
7738         }
7739         return err;
7740
7741 }
7742
7743 static int si_dpm_sw_init(void *handle)
7744 {
7745         int ret;
7746         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
7747
7748         ret = amdgpu_irq_add_id(adev, 230, &adev->pm.dpm.thermal.irq);
7749         if (ret)
7750                 return ret;
7751
7752         ret = amdgpu_irq_add_id(adev, 231, &adev->pm.dpm.thermal.irq);
7753         if (ret)
7754                 return ret;
7755
7756         /* default to balanced state */
7757         adev->pm.dpm.state = POWER_STATE_TYPE_BALANCED;
7758         adev->pm.dpm.user_state = POWER_STATE_TYPE_BALANCED;
7759         adev->pm.dpm.forced_level = AMDGPU_DPM_FORCED_LEVEL_AUTO;
7760         adev->pm.default_sclk = adev->clock.default_sclk;
7761         adev->pm.default_mclk = adev->clock.default_mclk;
7762         adev->pm.current_sclk = adev->clock.default_sclk;
7763         adev->pm.current_mclk = adev->clock.default_mclk;
7764         adev->pm.int_thermal_type = THERMAL_TYPE_NONE;
7765
7766         if (amdgpu_dpm == 0)
7767                 return 0;
7768
7769         ret = si_dpm_init_microcode(adev);
7770         if (ret)
7771                 return ret;
7772
7773         INIT_WORK(&adev->pm.dpm.thermal.work, amdgpu_dpm_thermal_work_handler);
7774         mutex_lock(&adev->pm.mutex);
7775         ret = si_dpm_init(adev);
7776         if (ret)
7777                 goto dpm_failed;
7778         adev->pm.dpm.current_ps = adev->pm.dpm.requested_ps = adev->pm.dpm.boot_ps;
7779         if (amdgpu_dpm == 1)
7780                 amdgpu_pm_print_power_states(adev);
7781         mutex_unlock(&adev->pm.mutex);
7782         DRM_INFO("amdgpu: dpm initialized\n");
7783
7784         return 0;
7785
7786 dpm_failed:
7787         si_dpm_fini(adev);
7788         mutex_unlock(&adev->pm.mutex);
7789         DRM_ERROR("amdgpu: dpm initialization failed\n");
7790         return ret;
7791 }
7792
7793 static int si_dpm_sw_fini(void *handle)
7794 {
7795         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
7796
7797         flush_work(&adev->pm.dpm.thermal.work);
7798
7799         mutex_lock(&adev->pm.mutex);
7800         amdgpu_pm_sysfs_fini(adev);
7801         si_dpm_fini(adev);
7802         mutex_unlock(&adev->pm.mutex);
7803
7804         return 0;
7805 }
7806
7807 static int si_dpm_hw_init(void *handle)
7808 {
7809         int ret;
7810
7811         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
7812
7813         if (!amdgpu_dpm)
7814                 return 0;
7815
7816         mutex_lock(&adev->pm.mutex);
7817         si_dpm_setup_asic(adev);
7818         ret = si_dpm_enable(adev);
7819         if (ret)
7820                 adev->pm.dpm_enabled = false;
7821         else
7822                 adev->pm.dpm_enabled = true;
7823         mutex_unlock(&adev->pm.mutex);
7824
7825         return ret;
7826 }
7827
7828 static int si_dpm_hw_fini(void *handle)
7829 {
7830         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
7831
7832         if (adev->pm.dpm_enabled) {
7833                 mutex_lock(&adev->pm.mutex);
7834                 si_dpm_disable(adev);
7835                 mutex_unlock(&adev->pm.mutex);
7836         }
7837
7838         return 0;
7839 }
7840
7841 static int si_dpm_suspend(void *handle)
7842 {
7843         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
7844
7845         if (adev->pm.dpm_enabled) {
7846                 mutex_lock(&adev->pm.mutex);
7847                 /* disable dpm */
7848                 si_dpm_disable(adev);
7849                 /* reset the power state */
7850                 adev->pm.dpm.current_ps = adev->pm.dpm.requested_ps = adev->pm.dpm.boot_ps;
7851                 mutex_unlock(&adev->pm.mutex);
7852         }
7853         return 0;
7854 }
7855
7856 static int si_dpm_resume(void *handle)
7857 {
7858         int ret;
7859         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
7860
7861         if (adev->pm.dpm_enabled) {
7862                 /* asic init will reset to the boot state */
7863                 mutex_lock(&adev->pm.mutex);
7864                 si_dpm_setup_asic(adev);
7865                 ret = si_dpm_enable(adev);
7866                 if (ret)
7867                         adev->pm.dpm_enabled = false;
7868                 else
7869                         adev->pm.dpm_enabled = true;
7870                 mutex_unlock(&adev->pm.mutex);
7871                 if (adev->pm.dpm_enabled)
7872                         amdgpu_pm_compute_clocks(adev);
7873         }
7874         return 0;
7875 }
7876
7877 static bool si_dpm_is_idle(void *handle)
7878 {
7879         /* XXX */
7880         return true;
7881 }
7882
7883 static int si_dpm_wait_for_idle(void *handle)
7884 {
7885         /* XXX */
7886         return 0;
7887 }
7888
7889 static int si_dpm_soft_reset(void *handle)
7890 {
7891         return 0;
7892 }
7893
7894 static int si_dpm_set_clockgating_state(void *handle,
7895                                         enum amd_clockgating_state state)
7896 {
7897         return 0;
7898 }
7899
7900 static int si_dpm_set_powergating_state(void *handle,
7901                                         enum amd_powergating_state state)
7902 {
7903         return 0;
7904 }
7905
7906 /* get temperature in millidegrees */
7907 static int si_dpm_get_temp(struct amdgpu_device *adev)
7908 {
7909         u32 temp;
7910         int actual_temp = 0;
7911
7912         temp = (RREG32(CG_MULT_THERMAL_STATUS) & CTF_TEMP_MASK) >>
7913                 CTF_TEMP_SHIFT;
7914
7915         if (temp & 0x200)
7916                 actual_temp = 255;
7917         else
7918                 actual_temp = temp & 0x1ff;
7919
7920         actual_temp = (actual_temp * 1000);
7921
7922         return actual_temp;
7923 }
7924
7925 static u32 si_dpm_get_sclk(struct amdgpu_device *adev, bool low)
7926 {
7927         struct evergreen_power_info *eg_pi = evergreen_get_pi(adev);
7928         struct  si_ps *requested_state = si_get_ps(&eg_pi->requested_rps);
7929
7930         if (low)
7931                 return requested_state->performance_levels[0].sclk;
7932         else
7933                 return requested_state->performance_levels[requested_state->performance_level_count - 1].sclk;
7934 }
7935
7936 static u32 si_dpm_get_mclk(struct amdgpu_device *adev, bool low)
7937 {
7938         struct evergreen_power_info *eg_pi = evergreen_get_pi(adev);
7939         struct  si_ps *requested_state = si_get_ps(&eg_pi->requested_rps);
7940
7941         if (low)
7942                 return requested_state->performance_levels[0].mclk;
7943         else
7944                 return requested_state->performance_levels[requested_state->performance_level_count - 1].mclk;
7945 }
7946
7947 static void si_dpm_print_power_state(struct amdgpu_device *adev,
7948                                      struct amdgpu_ps *rps)
7949 {
7950         struct  si_ps *ps = si_get_ps(rps);
7951         struct rv7xx_pl *pl;
7952         int i;
7953
7954         amdgpu_dpm_print_class_info(rps->class, rps->class2);
7955         amdgpu_dpm_print_cap_info(rps->caps);
7956         DRM_INFO("\tuvd    vclk: %d dclk: %d\n", rps->vclk, rps->dclk);
7957         for (i = 0; i < ps->performance_level_count; i++) {
7958                 pl = &ps->performance_levels[i];
7959                 if (adev->asic_type >= CHIP_TAHITI)
7960                         DRM_INFO("\t\tpower level %d    sclk: %u mclk: %u vddc: %u vddci: %u pcie gen: %u\n",
7961                                  i, pl->sclk, pl->mclk, pl->vddc, pl->vddci, pl->pcie_gen + 1);
7962                 else
7963                         DRM_INFO("\t\tpower level %d    sclk: %u mclk: %u vddc: %u vddci: %u\n",
7964                                  i, pl->sclk, pl->mclk, pl->vddc, pl->vddci);
7965         }
7966         amdgpu_dpm_print_ps_status(adev, rps);
7967 }
7968
7969 static int si_dpm_early_init(void *handle)
7970 {
7971
7972         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
7973
7974         si_dpm_set_dpm_funcs(adev);
7975         si_dpm_set_irq_funcs(adev);
7976         return 0;
7977 }
7978
7979 static inline bool si_are_power_levels_equal(const struct rv7xx_pl  *si_cpl1,
7980                                                 const struct rv7xx_pl *si_cpl2)
7981 {
7982         return ((si_cpl1->mclk == si_cpl2->mclk) &&
7983                   (si_cpl1->sclk == si_cpl2->sclk) &&
7984                   (si_cpl1->pcie_gen == si_cpl2->pcie_gen) &&
7985                   (si_cpl1->vddc == si_cpl2->vddc) &&
7986                   (si_cpl1->vddci == si_cpl2->vddci));
7987 }
7988
7989 static int si_check_state_equal(struct amdgpu_device *adev,
7990                                 struct amdgpu_ps *cps,
7991                                 struct amdgpu_ps *rps,
7992                                 bool *equal)
7993 {
7994         struct si_ps *si_cps;
7995         struct si_ps *si_rps;
7996         int i;
7997
7998         if (adev == NULL || cps == NULL || rps == NULL || equal == NULL)
7999                 return -EINVAL;
8000
8001         si_cps = si_get_ps(cps);
8002         si_rps = si_get_ps(rps);
8003
8004         if (si_cps == NULL) {
8005                 printk("si_cps is NULL\n");
8006                 *equal = false;
8007                 return 0;
8008         }
8009
8010         if (si_cps->performance_level_count != si_rps->performance_level_count) {
8011                 *equal = false;
8012                 return 0;
8013         }
8014
8015         for (i = 0; i < si_cps->performance_level_count; i++) {
8016                 if (!si_are_power_levels_equal(&(si_cps->performance_levels[i]),
8017                                         &(si_rps->performance_levels[i]))) {
8018                         *equal = false;
8019                         return 0;
8020                 }
8021         }
8022
8023         /* If all performance levels are the same try to use the UVD clocks to break the tie.*/
8024         *equal = ((cps->vclk == rps->vclk) && (cps->dclk == rps->dclk));
8025         *equal &= ((cps->evclk == rps->evclk) && (cps->ecclk == rps->ecclk));
8026
8027         return 0;
8028 }
8029
8030
8031 const struct amd_ip_funcs si_dpm_ip_funcs = {
8032         .name = "si_dpm",
8033         .early_init = si_dpm_early_init,
8034         .late_init = si_dpm_late_init,
8035         .sw_init = si_dpm_sw_init,
8036         .sw_fini = si_dpm_sw_fini,
8037         .hw_init = si_dpm_hw_init,
8038         .hw_fini = si_dpm_hw_fini,
8039         .suspend = si_dpm_suspend,
8040         .resume = si_dpm_resume,
8041         .is_idle = si_dpm_is_idle,
8042         .wait_for_idle = si_dpm_wait_for_idle,
8043         .soft_reset = si_dpm_soft_reset,
8044         .set_clockgating_state = si_dpm_set_clockgating_state,
8045         .set_powergating_state = si_dpm_set_powergating_state,
8046 };
8047
8048 static const struct amdgpu_dpm_funcs si_dpm_funcs = {
8049         .get_temperature = &si_dpm_get_temp,
8050         .pre_set_power_state = &si_dpm_pre_set_power_state,
8051         .set_power_state = &si_dpm_set_power_state,
8052         .post_set_power_state = &si_dpm_post_set_power_state,
8053         .display_configuration_changed = &si_dpm_display_configuration_changed,
8054         .get_sclk = &si_dpm_get_sclk,
8055         .get_mclk = &si_dpm_get_mclk,
8056         .print_power_state = &si_dpm_print_power_state,
8057         .debugfs_print_current_performance_level = &si_dpm_debugfs_print_current_performance_level,
8058         .force_performance_level = &si_dpm_force_performance_level,
8059         .vblank_too_short = &si_dpm_vblank_too_short,
8060         .set_fan_control_mode = &si_dpm_set_fan_control_mode,
8061         .get_fan_control_mode = &si_dpm_get_fan_control_mode,
8062         .set_fan_speed_percent = &si_dpm_set_fan_speed_percent,
8063         .get_fan_speed_percent = &si_dpm_get_fan_speed_percent,
8064         .check_state_equal = &si_check_state_equal,
8065         .get_vce_clock_state = amdgpu_get_vce_clock_state,
8066 };
8067
8068 static void si_dpm_set_dpm_funcs(struct amdgpu_device *adev)
8069 {
8070         if (adev->pm.funcs == NULL)
8071                 adev->pm.funcs = &si_dpm_funcs;
8072 }
8073
8074 static const struct amdgpu_irq_src_funcs si_dpm_irq_funcs = {
8075         .set = si_dpm_set_interrupt_state,
8076         .process = si_dpm_process_interrupt,
8077 };
8078
8079 static void si_dpm_set_irq_funcs(struct amdgpu_device *adev)
8080 {
8081         adev->pm.dpm.thermal.irq.num_types = AMDGPU_THERMAL_IRQ_LAST;
8082         adev->pm.dpm.thermal.irq.funcs = &si_dpm_irq_funcs;
8083 }
8084
8085 const struct amdgpu_ip_block_version si_dpm_ip_block =
8086 {
8087         .type = AMD_IP_BLOCK_TYPE_SMC,
8088         .major = 6,
8089         .minor = 0,
8090         .rev = 0,
8091         .funcs = &si_dpm_ip_funcs,
8092 };