2 * Copyright 2016 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
23 #include <linux/firmware.h>
24 #include <linux/slab.h>
25 #include <linux/module.h>
26 #include <linux/pci.h>
29 #include "amdgpu_atombios.h"
30 #include "amdgpu_ih.h"
31 #include "amdgpu_uvd.h"
32 #include "amdgpu_vce.h"
33 #include "amdgpu_ucode.h"
34 #include "amdgpu_psp.h"
38 #include "uvd/uvd_7_0_offset.h"
39 #include "gc/gc_9_0_offset.h"
40 #include "gc/gc_9_0_sh_mask.h"
41 #include "sdma0/sdma0_4_0_offset.h"
42 #include "sdma1/sdma1_4_0_offset.h"
43 #include "hdp/hdp_4_0_offset.h"
44 #include "hdp/hdp_4_0_sh_mask.h"
45 #include "smuio/smuio_9_0_offset.h"
46 #include "smuio/smuio_9_0_sh_mask.h"
47 #include "nbio/nbio_7_0_default.h"
48 #include "nbio/nbio_7_0_offset.h"
49 #include "nbio/nbio_7_0_sh_mask.h"
50 #include "nbio/nbio_7_0_smn.h"
51 #include "mp/mp_9_0_offset.h"
54 #include "soc15_common.h"
57 #include "gfxhub_v1_0.h"
58 #include "mmhub_v1_0.h"
61 #include "nbio_v6_1.h"
62 #include "nbio_v7_0.h"
63 #include "nbio_v7_4.h"
64 #include "vega10_ih.h"
65 #include "sdma_v4_0.h"
70 #include "jpeg_v2_0.h"
72 #include "jpeg_v2_5.h"
73 #include "dce_virtual.h"
75 #include "amdgpu_smu.h"
76 #include "amdgpu_ras.h"
77 #include "amdgpu_xgmi.h"
78 #include <uapi/linux/kfd_ioctl.h>
80 #define mmMP0_MISC_CGTT_CTRL0 0x01b9
81 #define mmMP0_MISC_CGTT_CTRL0_BASE_IDX 0
82 #define mmMP0_MISC_LIGHT_SLEEP_CTRL 0x01ba
83 #define mmMP0_MISC_LIGHT_SLEEP_CTRL_BASE_IDX 0
85 /* for Vega20 register name change */
86 #define mmHDP_MEM_POWER_CTRL 0x00d4
87 #define HDP_MEM_POWER_CTRL__IPH_MEM_POWER_CTRL_EN_MASK 0x00000001L
88 #define HDP_MEM_POWER_CTRL__IPH_MEM_POWER_LS_EN_MASK 0x00000002L
89 #define HDP_MEM_POWER_CTRL__RC_MEM_POWER_CTRL_EN_MASK 0x00010000L
90 #define HDP_MEM_POWER_CTRL__RC_MEM_POWER_LS_EN_MASK 0x00020000L
91 #define mmHDP_MEM_POWER_CTRL_BASE_IDX 0
93 * Indirect registers accessor
95 static u32 soc15_pcie_rreg(struct amdgpu_device *adev, u32 reg)
97 unsigned long flags, address, data;
99 address = adev->nbio.funcs->get_pcie_index_offset(adev);
100 data = adev->nbio.funcs->get_pcie_data_offset(adev);
102 spin_lock_irqsave(&adev->pcie_idx_lock, flags);
103 WREG32(address, reg);
104 (void)RREG32(address);
106 spin_unlock_irqrestore(&adev->pcie_idx_lock, flags);
110 static void soc15_pcie_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
112 unsigned long flags, address, data;
114 address = adev->nbio.funcs->get_pcie_index_offset(adev);
115 data = adev->nbio.funcs->get_pcie_data_offset(adev);
117 spin_lock_irqsave(&adev->pcie_idx_lock, flags);
118 WREG32(address, reg);
119 (void)RREG32(address);
122 spin_unlock_irqrestore(&adev->pcie_idx_lock, flags);
125 static u64 soc15_pcie_rreg64(struct amdgpu_device *adev, u32 reg)
127 unsigned long flags, address, data;
129 address = adev->nbio.funcs->get_pcie_index_offset(adev);
130 data = adev->nbio.funcs->get_pcie_data_offset(adev);
132 spin_lock_irqsave(&adev->pcie_idx_lock, flags);
133 /* read low 32 bit */
134 WREG32(address, reg);
135 (void)RREG32(address);
138 /* read high 32 bit*/
139 WREG32(address, reg + 4);
140 (void)RREG32(address);
141 r |= ((u64)RREG32(data) << 32);
142 spin_unlock_irqrestore(&adev->pcie_idx_lock, flags);
146 static void soc15_pcie_wreg64(struct amdgpu_device *adev, u32 reg, u64 v)
148 unsigned long flags, address, data;
150 address = adev->nbio.funcs->get_pcie_index_offset(adev);
151 data = adev->nbio.funcs->get_pcie_data_offset(adev);
153 spin_lock_irqsave(&adev->pcie_idx_lock, flags);
154 /* write low 32 bit */
155 WREG32(address, reg);
156 (void)RREG32(address);
157 WREG32(data, (u32)(v & 0xffffffffULL));
160 /* write high 32 bit */
161 WREG32(address, reg + 4);
162 (void)RREG32(address);
163 WREG32(data, (u32)(v >> 32));
165 spin_unlock_irqrestore(&adev->pcie_idx_lock, flags);
168 static u32 soc15_uvd_ctx_rreg(struct amdgpu_device *adev, u32 reg)
170 unsigned long flags, address, data;
173 address = SOC15_REG_OFFSET(UVD, 0, mmUVD_CTX_INDEX);
174 data = SOC15_REG_OFFSET(UVD, 0, mmUVD_CTX_DATA);
176 spin_lock_irqsave(&adev->uvd_ctx_idx_lock, flags);
177 WREG32(address, ((reg) & 0x1ff));
179 spin_unlock_irqrestore(&adev->uvd_ctx_idx_lock, flags);
183 static void soc15_uvd_ctx_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
185 unsigned long flags, address, data;
187 address = SOC15_REG_OFFSET(UVD, 0, mmUVD_CTX_INDEX);
188 data = SOC15_REG_OFFSET(UVD, 0, mmUVD_CTX_DATA);
190 spin_lock_irqsave(&adev->uvd_ctx_idx_lock, flags);
191 WREG32(address, ((reg) & 0x1ff));
193 spin_unlock_irqrestore(&adev->uvd_ctx_idx_lock, flags);
196 static u32 soc15_didt_rreg(struct amdgpu_device *adev, u32 reg)
198 unsigned long flags, address, data;
201 address = SOC15_REG_OFFSET(GC, 0, mmDIDT_IND_INDEX);
202 data = SOC15_REG_OFFSET(GC, 0, mmDIDT_IND_DATA);
204 spin_lock_irqsave(&adev->didt_idx_lock, flags);
205 WREG32(address, (reg));
207 spin_unlock_irqrestore(&adev->didt_idx_lock, flags);
211 static void soc15_didt_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
213 unsigned long flags, address, data;
215 address = SOC15_REG_OFFSET(GC, 0, mmDIDT_IND_INDEX);
216 data = SOC15_REG_OFFSET(GC, 0, mmDIDT_IND_DATA);
218 spin_lock_irqsave(&adev->didt_idx_lock, flags);
219 WREG32(address, (reg));
221 spin_unlock_irqrestore(&adev->didt_idx_lock, flags);
224 static u32 soc15_gc_cac_rreg(struct amdgpu_device *adev, u32 reg)
229 spin_lock_irqsave(&adev->gc_cac_idx_lock, flags);
230 WREG32_SOC15(GC, 0, mmGC_CAC_IND_INDEX, (reg));
231 r = RREG32_SOC15(GC, 0, mmGC_CAC_IND_DATA);
232 spin_unlock_irqrestore(&adev->gc_cac_idx_lock, flags);
236 static void soc15_gc_cac_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
240 spin_lock_irqsave(&adev->gc_cac_idx_lock, flags);
241 WREG32_SOC15(GC, 0, mmGC_CAC_IND_INDEX, (reg));
242 WREG32_SOC15(GC, 0, mmGC_CAC_IND_DATA, (v));
243 spin_unlock_irqrestore(&adev->gc_cac_idx_lock, flags);
246 static u32 soc15_se_cac_rreg(struct amdgpu_device *adev, u32 reg)
251 spin_lock_irqsave(&adev->se_cac_idx_lock, flags);
252 WREG32_SOC15(GC, 0, mmSE_CAC_IND_INDEX, (reg));
253 r = RREG32_SOC15(GC, 0, mmSE_CAC_IND_DATA);
254 spin_unlock_irqrestore(&adev->se_cac_idx_lock, flags);
258 static void soc15_se_cac_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
262 spin_lock_irqsave(&adev->se_cac_idx_lock, flags);
263 WREG32_SOC15(GC, 0, mmSE_CAC_IND_INDEX, (reg));
264 WREG32_SOC15(GC, 0, mmSE_CAC_IND_DATA, (v));
265 spin_unlock_irqrestore(&adev->se_cac_idx_lock, flags);
268 static u32 soc15_get_config_memsize(struct amdgpu_device *adev)
270 return adev->nbio.funcs->get_memsize(adev);
273 static u32 soc15_get_xclk(struct amdgpu_device *adev)
275 u32 reference_clock = adev->clock.spll.reference_freq;
277 if (adev->asic_type == CHIP_RAVEN)
278 return reference_clock / 4;
280 return reference_clock;
284 void soc15_grbm_select(struct amdgpu_device *adev,
285 u32 me, u32 pipe, u32 queue, u32 vmid)
287 u32 grbm_gfx_cntl = 0;
288 grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, PIPEID, pipe);
289 grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, MEID, me);
290 grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, VMID, vmid);
291 grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, QUEUEID, queue);
293 WREG32_SOC15_RLC_SHADOW(GC, 0, mmGRBM_GFX_CNTL, grbm_gfx_cntl);
296 static void soc15_vga_set_state(struct amdgpu_device *adev, bool state)
301 static bool soc15_read_disabled_bios(struct amdgpu_device *adev)
307 static bool soc15_read_bios_from_rom(struct amdgpu_device *adev,
308 u8 *bios, u32 length_bytes)
315 if (length_bytes == 0)
317 /* APU vbios image is part of sbios image */
318 if (adev->flags & AMD_IS_APU)
321 dw_ptr = (u32 *)bios;
322 length_dw = ALIGN(length_bytes, 4) / 4;
324 /* set rom index to 0 */
325 WREG32(SOC15_REG_OFFSET(SMUIO, 0, mmROM_INDEX), 0);
326 /* read out the rom data */
327 for (i = 0; i < length_dw; i++)
328 dw_ptr[i] = RREG32(SOC15_REG_OFFSET(SMUIO, 0, mmROM_DATA));
333 static struct soc15_allowed_register_entry soc15_allowed_read_registers[] = {
334 { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS)},
335 { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS2)},
336 { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS_SE0)},
337 { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS_SE1)},
338 { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS_SE2)},
339 { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS_SE3)},
340 { SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_STATUS_REG)},
341 { SOC15_REG_ENTRY(SDMA1, 0, mmSDMA1_STATUS_REG)},
342 { SOC15_REG_ENTRY(GC, 0, mmCP_STAT)},
343 { SOC15_REG_ENTRY(GC, 0, mmCP_STALLED_STAT1)},
344 { SOC15_REG_ENTRY(GC, 0, mmCP_STALLED_STAT2)},
345 { SOC15_REG_ENTRY(GC, 0, mmCP_STALLED_STAT3)},
346 { SOC15_REG_ENTRY(GC, 0, mmCP_CPF_BUSY_STAT)},
347 { SOC15_REG_ENTRY(GC, 0, mmCP_CPF_STALLED_STAT1)},
348 { SOC15_REG_ENTRY(GC, 0, mmCP_CPF_STATUS)},
349 { SOC15_REG_ENTRY(GC, 0, mmCP_CPC_BUSY_STAT)},
350 { SOC15_REG_ENTRY(GC, 0, mmCP_CPC_STALLED_STAT1)},
351 { SOC15_REG_ENTRY(GC, 0, mmCP_CPC_STATUS)},
352 { SOC15_REG_ENTRY(GC, 0, mmGB_ADDR_CONFIG)},
353 { SOC15_REG_ENTRY(GC, 0, mmDB_DEBUG2)},
356 static uint32_t soc15_read_indexed_register(struct amdgpu_device *adev, u32 se_num,
357 u32 sh_num, u32 reg_offset)
361 mutex_lock(&adev->grbm_idx_mutex);
362 if (se_num != 0xffffffff || sh_num != 0xffffffff)
363 amdgpu_gfx_select_se_sh(adev, se_num, sh_num, 0xffffffff);
365 val = RREG32(reg_offset);
367 if (se_num != 0xffffffff || sh_num != 0xffffffff)
368 amdgpu_gfx_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
369 mutex_unlock(&adev->grbm_idx_mutex);
373 static uint32_t soc15_get_register_value(struct amdgpu_device *adev,
374 bool indexed, u32 se_num,
375 u32 sh_num, u32 reg_offset)
378 return soc15_read_indexed_register(adev, se_num, sh_num, reg_offset);
380 if (reg_offset == SOC15_REG_OFFSET(GC, 0, mmGB_ADDR_CONFIG))
381 return adev->gfx.config.gb_addr_config;
382 else if (reg_offset == SOC15_REG_OFFSET(GC, 0, mmDB_DEBUG2))
383 return adev->gfx.config.db_debug2;
384 return RREG32(reg_offset);
388 static int soc15_read_register(struct amdgpu_device *adev, u32 se_num,
389 u32 sh_num, u32 reg_offset, u32 *value)
392 struct soc15_allowed_register_entry *en;
395 for (i = 0; i < ARRAY_SIZE(soc15_allowed_read_registers); i++) {
396 en = &soc15_allowed_read_registers[i];
397 if (reg_offset != (adev->reg_offset[en->hwip][en->inst][en->seg]
401 *value = soc15_get_register_value(adev,
402 soc15_allowed_read_registers[i].grbm_indexed,
403 se_num, sh_num, reg_offset);
411 * soc15_program_register_sequence - program an array of registers.
413 * @adev: amdgpu_device pointer
414 * @regs: pointer to the register array
415 * @array_size: size of the register array
417 * Programs an array or registers with and and or masks.
418 * This is a helper for setting golden registers.
421 void soc15_program_register_sequence(struct amdgpu_device *adev,
422 const struct soc15_reg_golden *regs,
423 const u32 array_size)
425 const struct soc15_reg_golden *entry;
429 for (i = 0; i < array_size; ++i) {
431 reg = adev->reg_offset[entry->hwip][entry->instance][entry->segment] + entry->reg;
433 if (entry->and_mask == 0xffffffff) {
434 tmp = entry->or_mask;
437 tmp &= ~(entry->and_mask);
438 tmp |= (entry->or_mask & entry->and_mask);
441 if (reg == SOC15_REG_OFFSET(GC, 0, mmPA_SC_BINNER_EVENT_CNTL_3) ||
442 reg == SOC15_REG_OFFSET(GC, 0, mmPA_SC_ENHANCE) ||
443 reg == SOC15_REG_OFFSET(GC, 0, mmPA_SC_ENHANCE_1) ||
444 reg == SOC15_REG_OFFSET(GC, 0, mmSH_MEM_CONFIG))
445 WREG32_RLC(reg, tmp);
453 static int soc15_asic_mode1_reset(struct amdgpu_device *adev)
458 amdgpu_atombios_scratch_regs_engine_hung(adev, true);
460 dev_info(adev->dev, "GPU mode1 reset\n");
463 pci_clear_master(adev->pdev);
465 pci_save_state(adev->pdev);
467 ret = psp_gpu_reset(adev);
469 dev_err(adev->dev, "GPU mode1 reset failed\n");
471 pci_restore_state(adev->pdev);
473 /* wait for asic to come out of reset */
474 for (i = 0; i < adev->usec_timeout; i++) {
475 u32 memsize = adev->nbio.funcs->get_memsize(adev);
477 if (memsize != 0xffffffff)
482 amdgpu_atombios_scratch_regs_engine_hung(adev, false);
487 static int soc15_asic_baco_reset(struct amdgpu_device *adev)
489 struct amdgpu_ras *ras = amdgpu_ras_get_context(adev);
492 /* avoid NBIF got stuck when do RAS recovery in BACO reset */
493 if (ras && ras->supported)
494 adev->nbio.funcs->enable_doorbell_interrupt(adev, false);
496 ret = amdgpu_dpm_baco_reset(adev);
500 /* re-enable doorbell interrupt after BACO exit */
501 if (ras && ras->supported)
502 adev->nbio.funcs->enable_doorbell_interrupt(adev, true);
507 static enum amd_reset_method
508 soc15_asic_reset_method(struct amdgpu_device *adev)
510 bool baco_reset = false;
511 struct amdgpu_ras *ras = amdgpu_ras_get_context(adev);
513 switch (adev->asic_type) {
516 return AMD_RESET_METHOD_MODE2;
520 baco_reset = amdgpu_dpm_is_baco_supported(adev);
523 if (adev->psp.sos_fw_version >= 0x80067)
524 baco_reset = amdgpu_dpm_is_baco_supported(adev);
527 * 1. PMFW version > 0x284300: all cases use baco
528 * 2. PMFW version <= 0x284300: only sGPU w/o RAS use baco
530 if ((ras && ras->supported) && adev->pm.fw_version <= 0x283400)
538 return AMD_RESET_METHOD_BACO;
540 return AMD_RESET_METHOD_MODE1;
543 static int soc15_asic_reset(struct amdgpu_device *adev)
545 /* original raven doesn't have full asic reset */
546 if (adev->pdev->device == 0x15dd && adev->rev_id < 0x8)
549 switch (soc15_asic_reset_method(adev)) {
550 case AMD_RESET_METHOD_BACO:
551 if (!adev->in_suspend)
552 amdgpu_inc_vram_lost(adev);
553 return soc15_asic_baco_reset(adev);
554 case AMD_RESET_METHOD_MODE2:
555 return amdgpu_dpm_mode2_reset(adev);
557 if (!adev->in_suspend)
558 amdgpu_inc_vram_lost(adev);
559 return soc15_asic_mode1_reset(adev);
563 static bool soc15_supports_baco(struct amdgpu_device *adev)
565 switch (adev->asic_type) {
569 return amdgpu_dpm_is_baco_supported(adev);
571 if (adev->psp.sos_fw_version >= 0x80067)
572 return amdgpu_dpm_is_baco_supported(adev);
579 /*static int soc15_set_uvd_clock(struct amdgpu_device *adev, u32 clock,
580 u32 cntl_reg, u32 status_reg)
585 static int soc15_set_uvd_clocks(struct amdgpu_device *adev, u32 vclk, u32 dclk)
589 r = soc15_set_uvd_clock(adev, vclk, ixCG_VCLK_CNTL, ixCG_VCLK_STATUS);
593 r = soc15_set_uvd_clock(adev, dclk, ixCG_DCLK_CNTL, ixCG_DCLK_STATUS);
598 static int soc15_set_vce_clocks(struct amdgpu_device *adev, u32 evclk, u32 ecclk)
605 static void soc15_pcie_gen3_enable(struct amdgpu_device *adev)
607 if (pci_is_root_bus(adev->pdev->bus))
610 if (amdgpu_pcie_gen2 == 0)
613 if (adev->flags & AMD_IS_APU)
616 if (!(adev->pm.pcie_gen_mask & (CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2 |
617 CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3)))
623 static void soc15_program_aspm(struct amdgpu_device *adev)
626 if (amdgpu_aspm == 0)
632 static void soc15_enable_doorbell_aperture(struct amdgpu_device *adev,
635 adev->nbio.funcs->enable_doorbell_aperture(adev, enable);
636 adev->nbio.funcs->enable_doorbell_selfring_aperture(adev, enable);
639 static const struct amdgpu_ip_block_version vega10_common_ip_block =
641 .type = AMD_IP_BLOCK_TYPE_COMMON,
645 .funcs = &soc15_common_ip_funcs,
648 static uint32_t soc15_get_rev_id(struct amdgpu_device *adev)
650 return adev->nbio.funcs->get_rev_id(adev);
653 int soc15_set_ip_blocks(struct amdgpu_device *adev)
655 /* Set IP register base before any HW register access */
656 switch (adev->asic_type) {
661 vega10_reg_base_init(adev);
664 vega20_reg_base_init(adev);
667 arct_reg_base_init(adev);
673 if (adev->asic_type == CHIP_VEGA20 || adev->asic_type == CHIP_ARCTURUS)
674 adev->gmc.xgmi.supported = true;
676 if (adev->flags & AMD_IS_APU) {
677 adev->nbio.funcs = &nbio_v7_0_funcs;
678 adev->nbio.hdp_flush_reg = &nbio_v7_0_hdp_flush_reg;
679 } else if (adev->asic_type == CHIP_VEGA20 ||
680 adev->asic_type == CHIP_ARCTURUS) {
681 adev->nbio.funcs = &nbio_v7_4_funcs;
682 adev->nbio.hdp_flush_reg = &nbio_v7_4_hdp_flush_reg;
684 adev->nbio.funcs = &nbio_v6_1_funcs;
685 adev->nbio.hdp_flush_reg = &nbio_v6_1_hdp_flush_reg;
688 if (adev->asic_type == CHIP_VEGA20 || adev->asic_type == CHIP_ARCTURUS)
689 adev->df.funcs = &df_v3_6_funcs;
691 adev->df.funcs = &df_v1_7_funcs;
693 adev->rev_id = soc15_get_rev_id(adev);
694 adev->nbio.funcs->detect_hw_virt(adev);
696 if (amdgpu_sriov_vf(adev))
697 adev->virt.ops = &xgpu_ai_virt_ops;
699 switch (adev->asic_type) {
703 amdgpu_device_ip_block_add(adev, &vega10_common_ip_block);
704 amdgpu_device_ip_block_add(adev, &gmc_v9_0_ip_block);
706 /* For Vega10 SR-IOV, PSP need to be initialized before IH */
707 if (amdgpu_sriov_vf(adev)) {
708 if (likely(adev->firmware.load_type == AMDGPU_FW_LOAD_PSP)) {
709 if (adev->asic_type == CHIP_VEGA20)
710 amdgpu_device_ip_block_add(adev, &psp_v11_0_ip_block);
712 amdgpu_device_ip_block_add(adev, &psp_v3_1_ip_block);
714 amdgpu_device_ip_block_add(adev, &vega10_ih_ip_block);
716 amdgpu_device_ip_block_add(adev, &vega10_ih_ip_block);
717 if (likely(adev->firmware.load_type == AMDGPU_FW_LOAD_PSP)) {
718 if (adev->asic_type == CHIP_VEGA20)
719 amdgpu_device_ip_block_add(adev, &psp_v11_0_ip_block);
721 amdgpu_device_ip_block_add(adev, &psp_v3_1_ip_block);
724 amdgpu_device_ip_block_add(adev, &gfx_v9_0_ip_block);
725 amdgpu_device_ip_block_add(adev, &sdma_v4_0_ip_block);
726 if (is_support_sw_smu(adev)) {
727 if (!amdgpu_sriov_vf(adev))
728 amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block);
730 amdgpu_device_ip_block_add(adev, &pp_smu_ip_block);
732 if (adev->enable_virtual_display || amdgpu_sriov_vf(adev))
733 amdgpu_device_ip_block_add(adev, &dce_virtual_ip_block);
734 #if defined(CONFIG_DRM_AMD_DC)
735 else if (amdgpu_device_has_dc_support(adev))
736 amdgpu_device_ip_block_add(adev, &dm_ip_block);
738 if (!(adev->asic_type == CHIP_VEGA20 && amdgpu_sriov_vf(adev))) {
739 amdgpu_device_ip_block_add(adev, &uvd_v7_0_ip_block);
740 amdgpu_device_ip_block_add(adev, &vce_v4_0_ip_block);
744 amdgpu_device_ip_block_add(adev, &vega10_common_ip_block);
745 amdgpu_device_ip_block_add(adev, &gmc_v9_0_ip_block);
746 amdgpu_device_ip_block_add(adev, &vega10_ih_ip_block);
747 if (likely(adev->firmware.load_type == AMDGPU_FW_LOAD_PSP))
748 amdgpu_device_ip_block_add(adev, &psp_v10_0_ip_block);
749 amdgpu_device_ip_block_add(adev, &gfx_v9_0_ip_block);
750 amdgpu_device_ip_block_add(adev, &sdma_v4_0_ip_block);
751 amdgpu_device_ip_block_add(adev, &pp_smu_ip_block);
752 if (adev->enable_virtual_display || amdgpu_sriov_vf(adev))
753 amdgpu_device_ip_block_add(adev, &dce_virtual_ip_block);
754 #if defined(CONFIG_DRM_AMD_DC)
755 else if (amdgpu_device_has_dc_support(adev))
756 amdgpu_device_ip_block_add(adev, &dm_ip_block);
758 amdgpu_device_ip_block_add(adev, &vcn_v1_0_ip_block);
761 amdgpu_device_ip_block_add(adev, &vega10_common_ip_block);
762 amdgpu_device_ip_block_add(adev, &gmc_v9_0_ip_block);
764 if (amdgpu_sriov_vf(adev)) {
765 if (likely(adev->firmware.load_type == AMDGPU_FW_LOAD_PSP))
766 amdgpu_device_ip_block_add(adev, &psp_v11_0_ip_block);
767 amdgpu_device_ip_block_add(adev, &vega10_ih_ip_block);
769 amdgpu_device_ip_block_add(adev, &vega10_ih_ip_block);
770 if (likely(adev->firmware.load_type == AMDGPU_FW_LOAD_PSP))
771 amdgpu_device_ip_block_add(adev, &psp_v11_0_ip_block);
774 if (adev->enable_virtual_display || amdgpu_sriov_vf(adev))
775 amdgpu_device_ip_block_add(adev, &dce_virtual_ip_block);
776 amdgpu_device_ip_block_add(adev, &gfx_v9_0_ip_block);
777 amdgpu_device_ip_block_add(adev, &sdma_v4_0_ip_block);
778 amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block);
780 if (amdgpu_sriov_vf(adev)) {
781 if (likely(adev->firmware.load_type == AMDGPU_FW_LOAD_PSP))
782 amdgpu_device_ip_block_add(adev, &vcn_v2_5_ip_block);
784 amdgpu_device_ip_block_add(adev, &vcn_v2_5_ip_block);
786 if (!amdgpu_sriov_vf(adev))
787 amdgpu_device_ip_block_add(adev, &jpeg_v2_5_ip_block);
790 amdgpu_device_ip_block_add(adev, &vega10_common_ip_block);
791 amdgpu_device_ip_block_add(adev, &gmc_v9_0_ip_block);
792 amdgpu_device_ip_block_add(adev, &vega10_ih_ip_block);
793 if (likely(adev->firmware.load_type == AMDGPU_FW_LOAD_PSP))
794 amdgpu_device_ip_block_add(adev, &psp_v12_0_ip_block);
795 amdgpu_device_ip_block_add(adev, &smu_v12_0_ip_block);
796 amdgpu_device_ip_block_add(adev, &gfx_v9_0_ip_block);
797 amdgpu_device_ip_block_add(adev, &sdma_v4_0_ip_block);
798 if (adev->enable_virtual_display || amdgpu_sriov_vf(adev))
799 amdgpu_device_ip_block_add(adev, &dce_virtual_ip_block);
800 #if defined(CONFIG_DRM_AMD_DC)
801 else if (amdgpu_device_has_dc_support(adev))
802 amdgpu_device_ip_block_add(adev, &dm_ip_block);
804 amdgpu_device_ip_block_add(adev, &vcn_v2_0_ip_block);
805 amdgpu_device_ip_block_add(adev, &jpeg_v2_0_ip_block);
814 static void soc15_flush_hdp(struct amdgpu_device *adev, struct amdgpu_ring *ring)
816 adev->nbio.funcs->hdp_flush(adev, ring);
819 static void soc15_invalidate_hdp(struct amdgpu_device *adev,
820 struct amdgpu_ring *ring)
822 if (!ring || !ring->funcs->emit_wreg)
823 WREG32_SOC15_NO_KIQ(HDP, 0, mmHDP_READ_CACHE_INVALIDATE, 1);
825 amdgpu_ring_emit_wreg(ring, SOC15_REG_OFFSET(
826 HDP, 0, mmHDP_READ_CACHE_INVALIDATE), 1);
829 static bool soc15_need_full_reset(struct amdgpu_device *adev)
831 /* change this when we implement soft reset */
834 static void soc15_get_pcie_usage(struct amdgpu_device *adev, uint64_t *count0,
837 uint32_t perfctr = 0;
838 uint64_t cnt0_of, cnt1_of;
841 /* This reports 0 on APUs, so return to avoid writing/reading registers
842 * that may or may not be different from their GPU counterparts
844 if (adev->flags & AMD_IS_APU)
847 /* Set the 2 events that we wish to watch, defined above */
848 /* Reg 40 is # received msgs */
849 /* Reg 104 is # of posted requests sent */
850 perfctr = REG_SET_FIELD(perfctr, PCIE_PERF_CNTL_TXCLK, EVENT0_SEL, 40);
851 perfctr = REG_SET_FIELD(perfctr, PCIE_PERF_CNTL_TXCLK, EVENT1_SEL, 104);
853 /* Write to enable desired perf counters */
854 WREG32_PCIE(smnPCIE_PERF_CNTL_TXCLK, perfctr);
855 /* Zero out and enable the perf counters
857 * Bit 0 = Start all counters(1)
858 * Bit 2 = Global counter reset enable(1)
860 WREG32_PCIE(smnPCIE_PERF_COUNT_CNTL, 0x00000005);
864 /* Load the shadow and disable the perf counters
866 * Bit 0 = Stop counters(0)
867 * Bit 1 = Load the shadow counters(1)
869 WREG32_PCIE(smnPCIE_PERF_COUNT_CNTL, 0x00000002);
871 /* Read register values to get any >32bit overflow */
872 tmp = RREG32_PCIE(smnPCIE_PERF_CNTL_TXCLK);
873 cnt0_of = REG_GET_FIELD(tmp, PCIE_PERF_CNTL_TXCLK, COUNTER0_UPPER);
874 cnt1_of = REG_GET_FIELD(tmp, PCIE_PERF_CNTL_TXCLK, COUNTER1_UPPER);
876 /* Get the values and add the overflow */
877 *count0 = RREG32_PCIE(smnPCIE_PERF_COUNT0_TXCLK) | (cnt0_of << 32);
878 *count1 = RREG32_PCIE(smnPCIE_PERF_COUNT1_TXCLK) | (cnt1_of << 32);
881 static void vega20_get_pcie_usage(struct amdgpu_device *adev, uint64_t *count0,
884 uint32_t perfctr = 0;
885 uint64_t cnt0_of, cnt1_of;
888 /* This reports 0 on APUs, so return to avoid writing/reading registers
889 * that may or may not be different from their GPU counterparts
891 if (adev->flags & AMD_IS_APU)
894 /* Set the 2 events that we wish to watch, defined above */
895 /* Reg 40 is # received msgs */
896 /* Reg 108 is # of posted requests sent on VG20 */
897 perfctr = REG_SET_FIELD(perfctr, PCIE_PERF_CNTL_TXCLK3,
899 perfctr = REG_SET_FIELD(perfctr, PCIE_PERF_CNTL_TXCLK3,
902 /* Write to enable desired perf counters */
903 WREG32_PCIE(smnPCIE_PERF_CNTL_TXCLK3, perfctr);
904 /* Zero out and enable the perf counters
906 * Bit 0 = Start all counters(1)
907 * Bit 2 = Global counter reset enable(1)
909 WREG32_PCIE(smnPCIE_PERF_COUNT_CNTL, 0x00000005);
913 /* Load the shadow and disable the perf counters
915 * Bit 0 = Stop counters(0)
916 * Bit 1 = Load the shadow counters(1)
918 WREG32_PCIE(smnPCIE_PERF_COUNT_CNTL, 0x00000002);
920 /* Read register values to get any >32bit overflow */
921 tmp = RREG32_PCIE(smnPCIE_PERF_CNTL_TXCLK3);
922 cnt0_of = REG_GET_FIELD(tmp, PCIE_PERF_CNTL_TXCLK3, COUNTER0_UPPER);
923 cnt1_of = REG_GET_FIELD(tmp, PCIE_PERF_CNTL_TXCLK3, COUNTER1_UPPER);
925 /* Get the values and add the overflow */
926 *count0 = RREG32_PCIE(smnPCIE_PERF_COUNT0_TXCLK3) | (cnt0_of << 32);
927 *count1 = RREG32_PCIE(smnPCIE_PERF_COUNT1_TXCLK3) | (cnt1_of << 32);
930 static bool soc15_need_reset_on_init(struct amdgpu_device *adev)
934 /* Just return false for soc15 GPUs. Reset does not seem to
937 if (!amdgpu_passthrough(adev))
940 if (adev->flags & AMD_IS_APU)
943 /* Check sOS sign of life register to confirm sys driver and sOS
944 * are already been loaded.
946 sol_reg = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_81);
953 static uint64_t soc15_get_pcie_replay_count(struct amdgpu_device *adev)
955 uint64_t nak_r, nak_g;
957 /* Get the number of NAKs received and generated */
958 nak_r = RREG32_PCIE(smnPCIE_RX_NUM_NAK);
959 nak_g = RREG32_PCIE(smnPCIE_RX_NUM_NAK_GENERATED);
961 /* Add the total number of NAKs, i.e the number of replays */
962 return (nak_r + nak_g);
965 static const struct amdgpu_asic_funcs soc15_asic_funcs =
967 .read_disabled_bios = &soc15_read_disabled_bios,
968 .read_bios_from_rom = &soc15_read_bios_from_rom,
969 .read_register = &soc15_read_register,
970 .reset = &soc15_asic_reset,
971 .reset_method = &soc15_asic_reset_method,
972 .set_vga_state = &soc15_vga_set_state,
973 .get_xclk = &soc15_get_xclk,
974 .set_uvd_clocks = &soc15_set_uvd_clocks,
975 .set_vce_clocks = &soc15_set_vce_clocks,
976 .get_config_memsize = &soc15_get_config_memsize,
977 .flush_hdp = &soc15_flush_hdp,
978 .invalidate_hdp = &soc15_invalidate_hdp,
979 .need_full_reset = &soc15_need_full_reset,
980 .init_doorbell_index = &vega10_doorbell_index_init,
981 .get_pcie_usage = &soc15_get_pcie_usage,
982 .need_reset_on_init = &soc15_need_reset_on_init,
983 .get_pcie_replay_count = &soc15_get_pcie_replay_count,
984 .supports_baco = &soc15_supports_baco,
987 static const struct amdgpu_asic_funcs vega20_asic_funcs =
989 .read_disabled_bios = &soc15_read_disabled_bios,
990 .read_bios_from_rom = &soc15_read_bios_from_rom,
991 .read_register = &soc15_read_register,
992 .reset = &soc15_asic_reset,
993 .reset_method = &soc15_asic_reset_method,
994 .set_vga_state = &soc15_vga_set_state,
995 .get_xclk = &soc15_get_xclk,
996 .set_uvd_clocks = &soc15_set_uvd_clocks,
997 .set_vce_clocks = &soc15_set_vce_clocks,
998 .get_config_memsize = &soc15_get_config_memsize,
999 .flush_hdp = &soc15_flush_hdp,
1000 .invalidate_hdp = &soc15_invalidate_hdp,
1001 .need_full_reset = &soc15_need_full_reset,
1002 .init_doorbell_index = &vega20_doorbell_index_init,
1003 .get_pcie_usage = &vega20_get_pcie_usage,
1004 .need_reset_on_init = &soc15_need_reset_on_init,
1005 .get_pcie_replay_count = &soc15_get_pcie_replay_count,
1006 .supports_baco = &soc15_supports_baco,
1009 static int soc15_common_early_init(void *handle)
1011 #define MMIO_REG_HOLE_OFFSET (0x80000 - PAGE_SIZE)
1012 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1014 adev->rmmio_remap.reg_offset = MMIO_REG_HOLE_OFFSET;
1015 adev->rmmio_remap.bus_addr = adev->rmmio_base + MMIO_REG_HOLE_OFFSET;
1016 adev->smc_rreg = NULL;
1017 adev->smc_wreg = NULL;
1018 adev->pcie_rreg = &soc15_pcie_rreg;
1019 adev->pcie_wreg = &soc15_pcie_wreg;
1020 adev->pcie_rreg64 = &soc15_pcie_rreg64;
1021 adev->pcie_wreg64 = &soc15_pcie_wreg64;
1022 adev->uvd_ctx_rreg = &soc15_uvd_ctx_rreg;
1023 adev->uvd_ctx_wreg = &soc15_uvd_ctx_wreg;
1024 adev->didt_rreg = &soc15_didt_rreg;
1025 adev->didt_wreg = &soc15_didt_wreg;
1026 adev->gc_cac_rreg = &soc15_gc_cac_rreg;
1027 adev->gc_cac_wreg = &soc15_gc_cac_wreg;
1028 adev->se_cac_rreg = &soc15_se_cac_rreg;
1029 adev->se_cac_wreg = &soc15_se_cac_wreg;
1032 adev->external_rev_id = 0xFF;
1033 switch (adev->asic_type) {
1035 adev->asic_funcs = &soc15_asic_funcs;
1036 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
1037 AMD_CG_SUPPORT_GFX_MGLS |
1038 AMD_CG_SUPPORT_GFX_RLC_LS |
1039 AMD_CG_SUPPORT_GFX_CP_LS |
1040 AMD_CG_SUPPORT_GFX_3D_CGCG |
1041 AMD_CG_SUPPORT_GFX_3D_CGLS |
1042 AMD_CG_SUPPORT_GFX_CGCG |
1043 AMD_CG_SUPPORT_GFX_CGLS |
1044 AMD_CG_SUPPORT_BIF_MGCG |
1045 AMD_CG_SUPPORT_BIF_LS |
1046 AMD_CG_SUPPORT_HDP_LS |
1047 AMD_CG_SUPPORT_DRM_MGCG |
1048 AMD_CG_SUPPORT_DRM_LS |
1049 AMD_CG_SUPPORT_ROM_MGCG |
1050 AMD_CG_SUPPORT_DF_MGCG |
1051 AMD_CG_SUPPORT_SDMA_MGCG |
1052 AMD_CG_SUPPORT_SDMA_LS |
1053 AMD_CG_SUPPORT_MC_MGCG |
1054 AMD_CG_SUPPORT_MC_LS;
1056 adev->external_rev_id = 0x1;
1059 adev->asic_funcs = &soc15_asic_funcs;
1060 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
1061 AMD_CG_SUPPORT_GFX_MGLS |
1062 AMD_CG_SUPPORT_GFX_CGCG |
1063 AMD_CG_SUPPORT_GFX_CGLS |
1064 AMD_CG_SUPPORT_GFX_3D_CGCG |
1065 AMD_CG_SUPPORT_GFX_3D_CGLS |
1066 AMD_CG_SUPPORT_GFX_CP_LS |
1067 AMD_CG_SUPPORT_MC_LS |
1068 AMD_CG_SUPPORT_MC_MGCG |
1069 AMD_CG_SUPPORT_SDMA_MGCG |
1070 AMD_CG_SUPPORT_SDMA_LS |
1071 AMD_CG_SUPPORT_BIF_MGCG |
1072 AMD_CG_SUPPORT_BIF_LS |
1073 AMD_CG_SUPPORT_HDP_MGCG |
1074 AMD_CG_SUPPORT_HDP_LS |
1075 AMD_CG_SUPPORT_ROM_MGCG |
1076 AMD_CG_SUPPORT_VCE_MGCG |
1077 AMD_CG_SUPPORT_UVD_MGCG;
1079 adev->external_rev_id = adev->rev_id + 0x14;
1082 adev->asic_funcs = &vega20_asic_funcs;
1083 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
1084 AMD_CG_SUPPORT_GFX_MGLS |
1085 AMD_CG_SUPPORT_GFX_CGCG |
1086 AMD_CG_SUPPORT_GFX_CGLS |
1087 AMD_CG_SUPPORT_GFX_3D_CGCG |
1088 AMD_CG_SUPPORT_GFX_3D_CGLS |
1089 AMD_CG_SUPPORT_GFX_CP_LS |
1090 AMD_CG_SUPPORT_MC_LS |
1091 AMD_CG_SUPPORT_MC_MGCG |
1092 AMD_CG_SUPPORT_SDMA_MGCG |
1093 AMD_CG_SUPPORT_SDMA_LS |
1094 AMD_CG_SUPPORT_BIF_MGCG |
1095 AMD_CG_SUPPORT_BIF_LS |
1096 AMD_CG_SUPPORT_HDP_MGCG |
1097 AMD_CG_SUPPORT_HDP_LS |
1098 AMD_CG_SUPPORT_ROM_MGCG |
1099 AMD_CG_SUPPORT_VCE_MGCG |
1100 AMD_CG_SUPPORT_UVD_MGCG;
1102 adev->external_rev_id = adev->rev_id + 0x28;
1105 adev->asic_funcs = &soc15_asic_funcs;
1106 if (adev->rev_id >= 0x8)
1107 adev->external_rev_id = adev->rev_id + 0x79;
1108 else if (adev->pdev->device == 0x15d8)
1109 adev->external_rev_id = adev->rev_id + 0x41;
1110 else if (adev->rev_id == 1)
1111 adev->external_rev_id = adev->rev_id + 0x20;
1113 adev->external_rev_id = adev->rev_id + 0x01;
1115 if (adev->rev_id >= 0x8) {
1116 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
1117 AMD_CG_SUPPORT_GFX_MGLS |
1118 AMD_CG_SUPPORT_GFX_CP_LS |
1119 AMD_CG_SUPPORT_GFX_3D_CGCG |
1120 AMD_CG_SUPPORT_GFX_3D_CGLS |
1121 AMD_CG_SUPPORT_GFX_CGCG |
1122 AMD_CG_SUPPORT_GFX_CGLS |
1123 AMD_CG_SUPPORT_BIF_LS |
1124 AMD_CG_SUPPORT_HDP_LS |
1125 AMD_CG_SUPPORT_ROM_MGCG |
1126 AMD_CG_SUPPORT_MC_MGCG |
1127 AMD_CG_SUPPORT_MC_LS |
1128 AMD_CG_SUPPORT_SDMA_MGCG |
1129 AMD_CG_SUPPORT_SDMA_LS |
1130 AMD_CG_SUPPORT_VCN_MGCG;
1132 adev->pg_flags = AMD_PG_SUPPORT_SDMA | AMD_PG_SUPPORT_VCN;
1133 } else if (adev->pdev->device == 0x15d8) {
1134 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
1135 AMD_CG_SUPPORT_GFX_MGLS |
1136 AMD_CG_SUPPORT_GFX_CP_LS |
1137 AMD_CG_SUPPORT_GFX_3D_CGCG |
1138 AMD_CG_SUPPORT_GFX_3D_CGLS |
1139 AMD_CG_SUPPORT_GFX_CGCG |
1140 AMD_CG_SUPPORT_GFX_CGLS |
1141 AMD_CG_SUPPORT_BIF_LS |
1142 AMD_CG_SUPPORT_HDP_LS |
1143 AMD_CG_SUPPORT_ROM_MGCG |
1144 AMD_CG_SUPPORT_MC_MGCG |
1145 AMD_CG_SUPPORT_MC_LS |
1146 AMD_CG_SUPPORT_SDMA_MGCG |
1147 AMD_CG_SUPPORT_SDMA_LS;
1149 adev->pg_flags = AMD_PG_SUPPORT_SDMA |
1150 AMD_PG_SUPPORT_MMHUB |
1151 AMD_PG_SUPPORT_VCN |
1152 AMD_PG_SUPPORT_VCN_DPG;
1154 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
1155 AMD_CG_SUPPORT_GFX_MGLS |
1156 AMD_CG_SUPPORT_GFX_RLC_LS |
1157 AMD_CG_SUPPORT_GFX_CP_LS |
1158 AMD_CG_SUPPORT_GFX_3D_CGCG |
1159 AMD_CG_SUPPORT_GFX_3D_CGLS |
1160 AMD_CG_SUPPORT_GFX_CGCG |
1161 AMD_CG_SUPPORT_GFX_CGLS |
1162 AMD_CG_SUPPORT_BIF_MGCG |
1163 AMD_CG_SUPPORT_BIF_LS |
1164 AMD_CG_SUPPORT_HDP_MGCG |
1165 AMD_CG_SUPPORT_HDP_LS |
1166 AMD_CG_SUPPORT_DRM_MGCG |
1167 AMD_CG_SUPPORT_DRM_LS |
1168 AMD_CG_SUPPORT_ROM_MGCG |
1169 AMD_CG_SUPPORT_MC_MGCG |
1170 AMD_CG_SUPPORT_MC_LS |
1171 AMD_CG_SUPPORT_SDMA_MGCG |
1172 AMD_CG_SUPPORT_SDMA_LS |
1173 AMD_CG_SUPPORT_VCN_MGCG;
1175 adev->pg_flags = AMD_PG_SUPPORT_SDMA | AMD_PG_SUPPORT_VCN;
1179 adev->asic_funcs = &vega20_asic_funcs;
1180 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
1181 AMD_CG_SUPPORT_GFX_MGLS |
1182 AMD_CG_SUPPORT_GFX_CGCG |
1183 AMD_CG_SUPPORT_GFX_CGLS |
1184 AMD_CG_SUPPORT_GFX_CP_LS |
1185 AMD_CG_SUPPORT_HDP_MGCG |
1186 AMD_CG_SUPPORT_HDP_LS |
1187 AMD_CG_SUPPORT_SDMA_MGCG |
1188 AMD_CG_SUPPORT_SDMA_LS |
1189 AMD_CG_SUPPORT_MC_MGCG |
1190 AMD_CG_SUPPORT_MC_LS |
1191 AMD_CG_SUPPORT_IH_CG |
1192 AMD_CG_SUPPORT_VCN_MGCG |
1193 AMD_CG_SUPPORT_JPEG_MGCG;
1195 adev->external_rev_id = adev->rev_id + 0x32;
1198 adev->asic_funcs = &soc15_asic_funcs;
1199 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
1200 AMD_CG_SUPPORT_GFX_MGLS |
1201 AMD_CG_SUPPORT_GFX_3D_CGCG |
1202 AMD_CG_SUPPORT_GFX_3D_CGLS |
1203 AMD_CG_SUPPORT_GFX_CGCG |
1204 AMD_CG_SUPPORT_GFX_CGLS |
1205 AMD_CG_SUPPORT_GFX_CP_LS |
1206 AMD_CG_SUPPORT_MC_MGCG |
1207 AMD_CG_SUPPORT_MC_LS |
1208 AMD_CG_SUPPORT_SDMA_MGCG |
1209 AMD_CG_SUPPORT_SDMA_LS |
1210 AMD_CG_SUPPORT_BIF_LS |
1211 AMD_CG_SUPPORT_HDP_LS |
1212 AMD_CG_SUPPORT_ROM_MGCG |
1213 AMD_CG_SUPPORT_VCN_MGCG |
1214 AMD_CG_SUPPORT_JPEG_MGCG |
1215 AMD_CG_SUPPORT_IH_CG |
1216 AMD_CG_SUPPORT_ATHUB_LS |
1217 AMD_CG_SUPPORT_ATHUB_MGCG |
1218 AMD_CG_SUPPORT_DF_MGCG;
1219 adev->pg_flags = AMD_PG_SUPPORT_SDMA |
1220 AMD_PG_SUPPORT_VCN |
1221 AMD_PG_SUPPORT_JPEG |
1222 AMD_PG_SUPPORT_VCN_DPG;
1223 adev->external_rev_id = adev->rev_id + 0x91;
1226 /* FIXME: not supported yet */
1230 if (amdgpu_sriov_vf(adev)) {
1231 amdgpu_virt_init_setting(adev);
1232 xgpu_ai_mailbox_set_irq_funcs(adev);
1238 static int soc15_common_late_init(void *handle)
1240 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1243 if (amdgpu_sriov_vf(adev))
1244 xgpu_ai_mailbox_get_irq(adev);
1246 if (adev->nbio.funcs->ras_late_init)
1247 r = adev->nbio.funcs->ras_late_init(adev);
1252 static int soc15_common_sw_init(void *handle)
1254 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1256 if (amdgpu_sriov_vf(adev))
1257 xgpu_ai_mailbox_add_irq_id(adev);
1259 adev->df.funcs->sw_init(adev);
1264 static int soc15_common_sw_fini(void *handle)
1266 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1268 amdgpu_nbio_ras_fini(adev);
1269 adev->df.funcs->sw_fini(adev);
1273 static void soc15_doorbell_range_init(struct amdgpu_device *adev)
1276 struct amdgpu_ring *ring;
1278 /* sdma/ih doorbell range are programed by hypervisor */
1279 if (!amdgpu_sriov_vf(adev)) {
1280 for (i = 0; i < adev->sdma.num_instances; i++) {
1281 ring = &adev->sdma.instance[i].ring;
1282 adev->nbio.funcs->sdma_doorbell_range(adev, i,
1283 ring->use_doorbell, ring->doorbell_index,
1284 adev->doorbell_index.sdma_doorbell_range);
1287 adev->nbio.funcs->ih_doorbell_range(adev, adev->irq.ih.use_doorbell,
1288 adev->irq.ih.doorbell_index);
1292 static int soc15_common_hw_init(void *handle)
1294 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1296 /* enable pcie gen2/3 link */
1297 soc15_pcie_gen3_enable(adev);
1299 soc15_program_aspm(adev);
1300 /* setup nbio registers */
1301 adev->nbio.funcs->init_registers(adev);
1302 /* remap HDP registers to a hole in mmio space,
1303 * for the purpose of expose those registers
1306 if (adev->nbio.funcs->remap_hdp_registers)
1307 adev->nbio.funcs->remap_hdp_registers(adev);
1309 /* enable the doorbell aperture */
1310 soc15_enable_doorbell_aperture(adev, true);
1311 /* HW doorbell routing policy: doorbell writing not
1312 * in SDMA/IH/MM/ACV range will be routed to CP. So
1313 * we need to init SDMA/IH/MM/ACV doorbell range prior
1314 * to CP ip block init and ring test.
1316 soc15_doorbell_range_init(adev);
1321 static int soc15_common_hw_fini(void *handle)
1323 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1325 /* disable the doorbell aperture */
1326 soc15_enable_doorbell_aperture(adev, false);
1327 if (amdgpu_sriov_vf(adev))
1328 xgpu_ai_mailbox_put_irq(adev);
1330 if (adev->nbio.ras_if &&
1331 amdgpu_ras_is_supported(adev, adev->nbio.ras_if->block)) {
1332 if (adev->nbio.funcs->init_ras_controller_interrupt)
1333 amdgpu_irq_put(adev, &adev->nbio.ras_controller_irq, 0);
1334 if (adev->nbio.funcs->init_ras_err_event_athub_interrupt)
1335 amdgpu_irq_put(adev, &adev->nbio.ras_err_event_athub_irq, 0);
1341 static int soc15_common_suspend(void *handle)
1343 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1345 return soc15_common_hw_fini(adev);
1348 static int soc15_common_resume(void *handle)
1350 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1352 return soc15_common_hw_init(adev);
1355 static bool soc15_common_is_idle(void *handle)
1360 static int soc15_common_wait_for_idle(void *handle)
1365 static int soc15_common_soft_reset(void *handle)
1370 static void soc15_update_hdp_light_sleep(struct amdgpu_device *adev, bool enable)
1374 if (adev->asic_type == CHIP_VEGA20 ||
1375 adev->asic_type == CHIP_ARCTURUS) {
1376 def = data = RREG32(SOC15_REG_OFFSET(HDP, 0, mmHDP_MEM_POWER_CTRL));
1378 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_HDP_LS))
1379 data |= HDP_MEM_POWER_CTRL__IPH_MEM_POWER_CTRL_EN_MASK |
1380 HDP_MEM_POWER_CTRL__IPH_MEM_POWER_LS_EN_MASK |
1381 HDP_MEM_POWER_CTRL__RC_MEM_POWER_CTRL_EN_MASK |
1382 HDP_MEM_POWER_CTRL__RC_MEM_POWER_LS_EN_MASK;
1384 data &= ~(HDP_MEM_POWER_CTRL__IPH_MEM_POWER_CTRL_EN_MASK |
1385 HDP_MEM_POWER_CTRL__IPH_MEM_POWER_LS_EN_MASK |
1386 HDP_MEM_POWER_CTRL__RC_MEM_POWER_CTRL_EN_MASK |
1387 HDP_MEM_POWER_CTRL__RC_MEM_POWER_LS_EN_MASK);
1390 WREG32(SOC15_REG_OFFSET(HDP, 0, mmHDP_MEM_POWER_CTRL), data);
1392 def = data = RREG32(SOC15_REG_OFFSET(HDP, 0, mmHDP_MEM_POWER_LS));
1394 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_HDP_LS))
1395 data |= HDP_MEM_POWER_LS__LS_ENABLE_MASK;
1397 data &= ~HDP_MEM_POWER_LS__LS_ENABLE_MASK;
1400 WREG32(SOC15_REG_OFFSET(HDP, 0, mmHDP_MEM_POWER_LS), data);
1404 static void soc15_update_drm_clock_gating(struct amdgpu_device *adev, bool enable)
1408 def = data = RREG32(SOC15_REG_OFFSET(MP0, 0, mmMP0_MISC_CGTT_CTRL0));
1410 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_DRM_MGCG))
1411 data &= ~(0x01000000 |
1420 data |= (0x01000000 |
1430 WREG32(SOC15_REG_OFFSET(MP0, 0, mmMP0_MISC_CGTT_CTRL0), data);
1433 static void soc15_update_drm_light_sleep(struct amdgpu_device *adev, bool enable)
1437 def = data = RREG32(SOC15_REG_OFFSET(MP0, 0, mmMP0_MISC_LIGHT_SLEEP_CTRL));
1439 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_DRM_LS))
1445 WREG32(SOC15_REG_OFFSET(MP0, 0, mmMP0_MISC_LIGHT_SLEEP_CTRL), data);
1448 static void soc15_update_rom_medium_grain_clock_gating(struct amdgpu_device *adev,
1453 def = data = RREG32(SOC15_REG_OFFSET(SMUIO, 0, mmCGTT_ROM_CLK_CTRL0));
1455 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_ROM_MGCG))
1456 data &= ~(CGTT_ROM_CLK_CTRL0__SOFT_OVERRIDE0_MASK |
1457 CGTT_ROM_CLK_CTRL0__SOFT_OVERRIDE1_MASK);
1459 data |= CGTT_ROM_CLK_CTRL0__SOFT_OVERRIDE0_MASK |
1460 CGTT_ROM_CLK_CTRL0__SOFT_OVERRIDE1_MASK;
1463 WREG32(SOC15_REG_OFFSET(SMUIO, 0, mmCGTT_ROM_CLK_CTRL0), data);
1466 static int soc15_common_set_clockgating_state(void *handle,
1467 enum amd_clockgating_state state)
1469 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1471 if (amdgpu_sriov_vf(adev))
1474 switch (adev->asic_type) {
1478 adev->nbio.funcs->update_medium_grain_clock_gating(adev,
1479 state == AMD_CG_STATE_GATE);
1480 adev->nbio.funcs->update_medium_grain_light_sleep(adev,
1481 state == AMD_CG_STATE_GATE);
1482 soc15_update_hdp_light_sleep(adev,
1483 state == AMD_CG_STATE_GATE);
1484 soc15_update_drm_clock_gating(adev,
1485 state == AMD_CG_STATE_GATE);
1486 soc15_update_drm_light_sleep(adev,
1487 state == AMD_CG_STATE_GATE);
1488 soc15_update_rom_medium_grain_clock_gating(adev,
1489 state == AMD_CG_STATE_GATE);
1490 adev->df.funcs->update_medium_grain_clock_gating(adev,
1491 state == AMD_CG_STATE_GATE);
1495 adev->nbio.funcs->update_medium_grain_clock_gating(adev,
1496 state == AMD_CG_STATE_GATE);
1497 adev->nbio.funcs->update_medium_grain_light_sleep(adev,
1498 state == AMD_CG_STATE_GATE);
1499 soc15_update_hdp_light_sleep(adev,
1500 state == AMD_CG_STATE_GATE);
1501 soc15_update_drm_clock_gating(adev,
1502 state == AMD_CG_STATE_GATE);
1503 soc15_update_drm_light_sleep(adev,
1504 state == AMD_CG_STATE_GATE);
1505 soc15_update_rom_medium_grain_clock_gating(adev,
1506 state == AMD_CG_STATE_GATE);
1509 soc15_update_hdp_light_sleep(adev,
1510 state == AMD_CG_STATE_GATE);
1518 static void soc15_common_get_clockgating_state(void *handle, u32 *flags)
1520 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1523 if (amdgpu_sriov_vf(adev))
1526 adev->nbio.funcs->get_clockgating_state(adev, flags);
1528 /* AMD_CG_SUPPORT_HDP_LS */
1529 data = RREG32(SOC15_REG_OFFSET(HDP, 0, mmHDP_MEM_POWER_LS));
1530 if (data & HDP_MEM_POWER_LS__LS_ENABLE_MASK)
1531 *flags |= AMD_CG_SUPPORT_HDP_LS;
1533 /* AMD_CG_SUPPORT_DRM_MGCG */
1534 data = RREG32(SOC15_REG_OFFSET(MP0, 0, mmMP0_MISC_CGTT_CTRL0));
1535 if (!(data & 0x01000000))
1536 *flags |= AMD_CG_SUPPORT_DRM_MGCG;
1538 /* AMD_CG_SUPPORT_DRM_LS */
1539 data = RREG32(SOC15_REG_OFFSET(MP0, 0, mmMP0_MISC_LIGHT_SLEEP_CTRL));
1541 *flags |= AMD_CG_SUPPORT_DRM_LS;
1543 /* AMD_CG_SUPPORT_ROM_MGCG */
1544 data = RREG32(SOC15_REG_OFFSET(SMUIO, 0, mmCGTT_ROM_CLK_CTRL0));
1545 if (!(data & CGTT_ROM_CLK_CTRL0__SOFT_OVERRIDE0_MASK))
1546 *flags |= AMD_CG_SUPPORT_ROM_MGCG;
1548 adev->df.funcs->get_clockgating_state(adev, flags);
1551 static int soc15_common_set_powergating_state(void *handle,
1552 enum amd_powergating_state state)
1558 const struct amd_ip_funcs soc15_common_ip_funcs = {
1559 .name = "soc15_common",
1560 .early_init = soc15_common_early_init,
1561 .late_init = soc15_common_late_init,
1562 .sw_init = soc15_common_sw_init,
1563 .sw_fini = soc15_common_sw_fini,
1564 .hw_init = soc15_common_hw_init,
1565 .hw_fini = soc15_common_hw_fini,
1566 .suspend = soc15_common_suspend,
1567 .resume = soc15_common_resume,
1568 .is_idle = soc15_common_is_idle,
1569 .wait_for_idle = soc15_common_wait_for_idle,
1570 .soft_reset = soc15_common_soft_reset,
1571 .set_clockgating_state = soc15_common_set_clockgating_state,
1572 .set_powergating_state = soc15_common_set_powergating_state,
1573 .get_clockgating_state= soc15_common_get_clockgating_state,