2 * Copyright 2016 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
23 #include <linux/firmware.h>
24 #include <linux/slab.h>
25 #include <linux/module.h>
28 #include "amdgpu_atombios.h"
29 #include "amdgpu_ih.h"
30 #include "amdgpu_uvd.h"
31 #include "amdgpu_vce.h"
32 #include "amdgpu_ucode.h"
33 #include "amdgpu_psp.h"
37 #include "uvd/uvd_7_0_offset.h"
38 #include "gc/gc_9_0_offset.h"
39 #include "gc/gc_9_0_sh_mask.h"
40 #include "sdma0/sdma0_4_0_offset.h"
41 #include "sdma1/sdma1_4_0_offset.h"
42 #include "hdp/hdp_4_0_offset.h"
43 #include "hdp/hdp_4_0_sh_mask.h"
44 #include "smuio/smuio_9_0_offset.h"
45 #include "smuio/smuio_9_0_sh_mask.h"
46 #include "nbio/nbio_7_0_default.h"
47 #include "nbio/nbio_7_0_sh_mask.h"
48 #include "nbio/nbio_7_0_smn.h"
49 #include "mp/mp_9_0_offset.h"
52 #include "soc15_common.h"
55 #include "gfxhub_v1_0.h"
56 #include "mmhub_v1_0.h"
59 #include "vega10_ih.h"
60 #include "sdma_v4_0.h"
64 #include "dce_virtual.h"
66 #include "amdgpu_smu.h"
68 #define mmMP0_MISC_CGTT_CTRL0 0x01b9
69 #define mmMP0_MISC_CGTT_CTRL0_BASE_IDX 0
70 #define mmMP0_MISC_LIGHT_SLEEP_CTRL 0x01ba
71 #define mmMP0_MISC_LIGHT_SLEEP_CTRL_BASE_IDX 0
73 /* for Vega20 register name change */
74 #define mmHDP_MEM_POWER_CTRL 0x00d4
75 #define HDP_MEM_POWER_CTRL__IPH_MEM_POWER_CTRL_EN_MASK 0x00000001L
76 #define HDP_MEM_POWER_CTRL__IPH_MEM_POWER_LS_EN_MASK 0x00000002L
77 #define HDP_MEM_POWER_CTRL__RC_MEM_POWER_CTRL_EN_MASK 0x00010000L
78 #define HDP_MEM_POWER_CTRL__RC_MEM_POWER_LS_EN_MASK 0x00020000L
79 #define mmHDP_MEM_POWER_CTRL_BASE_IDX 0
81 * Indirect registers accessor
83 static u32 soc15_pcie_rreg(struct amdgpu_device *adev, u32 reg)
85 unsigned long flags, address, data;
87 address = adev->nbio_funcs->get_pcie_index_offset(adev);
88 data = adev->nbio_funcs->get_pcie_data_offset(adev);
90 spin_lock_irqsave(&adev->pcie_idx_lock, flags);
92 (void)RREG32(address);
94 spin_unlock_irqrestore(&adev->pcie_idx_lock, flags);
98 static void soc15_pcie_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
100 unsigned long flags, address, data;
102 address = adev->nbio_funcs->get_pcie_index_offset(adev);
103 data = adev->nbio_funcs->get_pcie_data_offset(adev);
105 spin_lock_irqsave(&adev->pcie_idx_lock, flags);
106 WREG32(address, reg);
107 (void)RREG32(address);
110 spin_unlock_irqrestore(&adev->pcie_idx_lock, flags);
113 static u32 soc15_uvd_ctx_rreg(struct amdgpu_device *adev, u32 reg)
115 unsigned long flags, address, data;
118 address = SOC15_REG_OFFSET(UVD, 0, mmUVD_CTX_INDEX);
119 data = SOC15_REG_OFFSET(UVD, 0, mmUVD_CTX_DATA);
121 spin_lock_irqsave(&adev->uvd_ctx_idx_lock, flags);
122 WREG32(address, ((reg) & 0x1ff));
124 spin_unlock_irqrestore(&adev->uvd_ctx_idx_lock, flags);
128 static void soc15_uvd_ctx_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
130 unsigned long flags, address, data;
132 address = SOC15_REG_OFFSET(UVD, 0, mmUVD_CTX_INDEX);
133 data = SOC15_REG_OFFSET(UVD, 0, mmUVD_CTX_DATA);
135 spin_lock_irqsave(&adev->uvd_ctx_idx_lock, flags);
136 WREG32(address, ((reg) & 0x1ff));
138 spin_unlock_irqrestore(&adev->uvd_ctx_idx_lock, flags);
141 static u32 soc15_didt_rreg(struct amdgpu_device *adev, u32 reg)
143 unsigned long flags, address, data;
146 address = SOC15_REG_OFFSET(GC, 0, mmDIDT_IND_INDEX);
147 data = SOC15_REG_OFFSET(GC, 0, mmDIDT_IND_DATA);
149 spin_lock_irqsave(&adev->didt_idx_lock, flags);
150 WREG32(address, (reg));
152 spin_unlock_irqrestore(&adev->didt_idx_lock, flags);
156 static void soc15_didt_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
158 unsigned long flags, address, data;
160 address = SOC15_REG_OFFSET(GC, 0, mmDIDT_IND_INDEX);
161 data = SOC15_REG_OFFSET(GC, 0, mmDIDT_IND_DATA);
163 spin_lock_irqsave(&adev->didt_idx_lock, flags);
164 WREG32(address, (reg));
166 spin_unlock_irqrestore(&adev->didt_idx_lock, flags);
169 static u32 soc15_gc_cac_rreg(struct amdgpu_device *adev, u32 reg)
174 spin_lock_irqsave(&adev->gc_cac_idx_lock, flags);
175 WREG32_SOC15(GC, 0, mmGC_CAC_IND_INDEX, (reg));
176 r = RREG32_SOC15(GC, 0, mmGC_CAC_IND_DATA);
177 spin_unlock_irqrestore(&adev->gc_cac_idx_lock, flags);
181 static void soc15_gc_cac_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
185 spin_lock_irqsave(&adev->gc_cac_idx_lock, flags);
186 WREG32_SOC15(GC, 0, mmGC_CAC_IND_INDEX, (reg));
187 WREG32_SOC15(GC, 0, mmGC_CAC_IND_DATA, (v));
188 spin_unlock_irqrestore(&adev->gc_cac_idx_lock, flags);
191 static u32 soc15_se_cac_rreg(struct amdgpu_device *adev, u32 reg)
196 spin_lock_irqsave(&adev->se_cac_idx_lock, flags);
197 WREG32_SOC15(GC, 0, mmSE_CAC_IND_INDEX, (reg));
198 r = RREG32_SOC15(GC, 0, mmSE_CAC_IND_DATA);
199 spin_unlock_irqrestore(&adev->se_cac_idx_lock, flags);
203 static void soc15_se_cac_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
207 spin_lock_irqsave(&adev->se_cac_idx_lock, flags);
208 WREG32_SOC15(GC, 0, mmSE_CAC_IND_INDEX, (reg));
209 WREG32_SOC15(GC, 0, mmSE_CAC_IND_DATA, (v));
210 spin_unlock_irqrestore(&adev->se_cac_idx_lock, flags);
213 static u32 soc15_get_config_memsize(struct amdgpu_device *adev)
215 return adev->nbio_funcs->get_memsize(adev);
218 static u32 soc15_get_xclk(struct amdgpu_device *adev)
220 return adev->clock.spll.reference_freq;
224 void soc15_grbm_select(struct amdgpu_device *adev,
225 u32 me, u32 pipe, u32 queue, u32 vmid)
227 u32 grbm_gfx_cntl = 0;
228 grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, PIPEID, pipe);
229 grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, MEID, me);
230 grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, VMID, vmid);
231 grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, QUEUEID, queue);
233 WREG32(SOC15_REG_OFFSET(GC, 0, mmGRBM_GFX_CNTL), grbm_gfx_cntl);
236 static void soc15_vga_set_state(struct amdgpu_device *adev, bool state)
241 static bool soc15_read_disabled_bios(struct amdgpu_device *adev)
247 static bool soc15_read_bios_from_rom(struct amdgpu_device *adev,
248 u8 *bios, u32 length_bytes)
255 if (length_bytes == 0)
257 /* APU vbios image is part of sbios image */
258 if (adev->flags & AMD_IS_APU)
261 dw_ptr = (u32 *)bios;
262 length_dw = ALIGN(length_bytes, 4) / 4;
264 /* set rom index to 0 */
265 WREG32(SOC15_REG_OFFSET(SMUIO, 0, mmROM_INDEX), 0);
266 /* read out the rom data */
267 for (i = 0; i < length_dw; i++)
268 dw_ptr[i] = RREG32(SOC15_REG_OFFSET(SMUIO, 0, mmROM_DATA));
273 struct soc15_allowed_register_entry {
282 static struct soc15_allowed_register_entry soc15_allowed_read_registers[] = {
283 { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS)},
284 { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS2)},
285 { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS_SE0)},
286 { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS_SE1)},
287 { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS_SE2)},
288 { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS_SE3)},
289 { SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_STATUS_REG)},
290 { SOC15_REG_ENTRY(SDMA1, 0, mmSDMA1_STATUS_REG)},
291 { SOC15_REG_ENTRY(GC, 0, mmCP_STAT)},
292 { SOC15_REG_ENTRY(GC, 0, mmCP_STALLED_STAT1)},
293 { SOC15_REG_ENTRY(GC, 0, mmCP_STALLED_STAT2)},
294 { SOC15_REG_ENTRY(GC, 0, mmCP_STALLED_STAT3)},
295 { SOC15_REG_ENTRY(GC, 0, mmCP_CPF_BUSY_STAT)},
296 { SOC15_REG_ENTRY(GC, 0, mmCP_CPF_STALLED_STAT1)},
297 { SOC15_REG_ENTRY(GC, 0, mmCP_CPF_STATUS)},
298 { SOC15_REG_ENTRY(GC, 0, mmCP_CPC_STALLED_STAT1)},
299 { SOC15_REG_ENTRY(GC, 0, mmCP_CPC_STATUS)},
300 { SOC15_REG_ENTRY(GC, 0, mmGB_ADDR_CONFIG)},
301 { SOC15_REG_ENTRY(GC, 0, mmDB_DEBUG2)},
304 static uint32_t soc15_read_indexed_register(struct amdgpu_device *adev, u32 se_num,
305 u32 sh_num, u32 reg_offset)
309 mutex_lock(&adev->grbm_idx_mutex);
310 if (se_num != 0xffffffff || sh_num != 0xffffffff)
311 amdgpu_gfx_select_se_sh(adev, se_num, sh_num, 0xffffffff);
313 val = RREG32(reg_offset);
315 if (se_num != 0xffffffff || sh_num != 0xffffffff)
316 amdgpu_gfx_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
317 mutex_unlock(&adev->grbm_idx_mutex);
321 static uint32_t soc15_get_register_value(struct amdgpu_device *adev,
322 bool indexed, u32 se_num,
323 u32 sh_num, u32 reg_offset)
326 return soc15_read_indexed_register(adev, se_num, sh_num, reg_offset);
328 if (reg_offset == SOC15_REG_OFFSET(GC, 0, mmGB_ADDR_CONFIG))
329 return adev->gfx.config.gb_addr_config;
330 else if (reg_offset == SOC15_REG_OFFSET(GC, 0, mmDB_DEBUG2))
331 return adev->gfx.config.db_debug2;
332 return RREG32(reg_offset);
336 static int soc15_read_register(struct amdgpu_device *adev, u32 se_num,
337 u32 sh_num, u32 reg_offset, u32 *value)
340 struct soc15_allowed_register_entry *en;
343 for (i = 0; i < ARRAY_SIZE(soc15_allowed_read_registers); i++) {
344 en = &soc15_allowed_read_registers[i];
345 if (reg_offset != (adev->reg_offset[en->hwip][en->inst][en->seg]
349 *value = soc15_get_register_value(adev,
350 soc15_allowed_read_registers[i].grbm_indexed,
351 se_num, sh_num, reg_offset);
359 * soc15_program_register_sequence - program an array of registers.
361 * @adev: amdgpu_device pointer
362 * @regs: pointer to the register array
363 * @array_size: size of the register array
365 * Programs an array or registers with and and or masks.
366 * This is a helper for setting golden registers.
369 void soc15_program_register_sequence(struct amdgpu_device *adev,
370 const struct soc15_reg_golden *regs,
371 const u32 array_size)
373 const struct soc15_reg_golden *entry;
377 for (i = 0; i < array_size; ++i) {
379 reg = adev->reg_offset[entry->hwip][entry->instance][entry->segment] + entry->reg;
381 if (entry->and_mask == 0xffffffff) {
382 tmp = entry->or_mask;
385 tmp &= ~(entry->and_mask);
386 tmp |= entry->or_mask;
393 static int soc15_asic_mode1_reset(struct amdgpu_device *adev)
397 amdgpu_atombios_scratch_regs_engine_hung(adev, true);
399 dev_info(adev->dev, "GPU mode1 reset\n");
402 pci_clear_master(adev->pdev);
404 pci_save_state(adev->pdev);
408 pci_restore_state(adev->pdev);
410 /* wait for asic to come out of reset */
411 for (i = 0; i < adev->usec_timeout; i++) {
412 u32 memsize = adev->nbio_funcs->get_memsize(adev);
414 if (memsize != 0xffffffff)
419 amdgpu_atombios_scratch_regs_engine_hung(adev, false);
424 static int soc15_asic_get_baco_capability(struct amdgpu_device *adev, bool *cap)
426 void *pp_handle = adev->powerplay.pp_handle;
427 const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs;
429 if (!pp_funcs || !pp_funcs->get_asic_baco_capability) {
434 return pp_funcs->get_asic_baco_capability(pp_handle, cap);
437 static int soc15_asic_baco_reset(struct amdgpu_device *adev)
439 void *pp_handle = adev->powerplay.pp_handle;
440 const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs;
442 if (!pp_funcs ||!pp_funcs->get_asic_baco_state ||!pp_funcs->set_asic_baco_state)
445 /* enter BACO state */
446 if (pp_funcs->set_asic_baco_state(pp_handle, 1))
449 /* exit BACO state */
450 if (pp_funcs->set_asic_baco_state(pp_handle, 0))
453 dev_info(adev->dev, "GPU BACO reset\n");
455 adev->in_baco_reset = 1;
460 static int soc15_asic_reset(struct amdgpu_device *adev)
465 switch (adev->asic_type) {
468 soc15_asic_get_baco_capability(adev, &baco_reset);
476 ret = soc15_asic_baco_reset(adev);
478 ret = soc15_asic_mode1_reset(adev);
483 /*static int soc15_set_uvd_clock(struct amdgpu_device *adev, u32 clock,
484 u32 cntl_reg, u32 status_reg)
489 static int soc15_set_uvd_clocks(struct amdgpu_device *adev, u32 vclk, u32 dclk)
493 r = soc15_set_uvd_clock(adev, vclk, ixCG_VCLK_CNTL, ixCG_VCLK_STATUS);
497 r = soc15_set_uvd_clock(adev, dclk, ixCG_DCLK_CNTL, ixCG_DCLK_STATUS);
502 static int soc15_set_vce_clocks(struct amdgpu_device *adev, u32 evclk, u32 ecclk)
509 static void soc15_pcie_gen3_enable(struct amdgpu_device *adev)
511 if (pci_is_root_bus(adev->pdev->bus))
514 if (amdgpu_pcie_gen2 == 0)
517 if (adev->flags & AMD_IS_APU)
520 if (!(adev->pm.pcie_gen_mask & (CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2 |
521 CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3)))
527 static void soc15_program_aspm(struct amdgpu_device *adev)
530 if (amdgpu_aspm == 0)
536 static void soc15_enable_doorbell_aperture(struct amdgpu_device *adev,
539 adev->nbio_funcs->enable_doorbell_aperture(adev, enable);
540 adev->nbio_funcs->enable_doorbell_selfring_aperture(adev, enable);
543 static const struct amdgpu_ip_block_version vega10_common_ip_block =
545 .type = AMD_IP_BLOCK_TYPE_COMMON,
549 .funcs = &soc15_common_ip_funcs,
552 static uint32_t soc15_get_rev_id(struct amdgpu_device *adev)
554 return adev->nbio_funcs->get_rev_id(adev);
557 int soc15_set_ip_blocks(struct amdgpu_device *adev)
559 /* Set IP register base before any HW register access */
560 switch (adev->asic_type) {
564 vega10_reg_base_init(adev);
567 vega20_reg_base_init(adev);
573 if (adev->asic_type == CHIP_VEGA20)
574 adev->gmc.xgmi.supported = true;
576 if (adev->flags & AMD_IS_APU)
577 adev->nbio_funcs = &nbio_v7_0_funcs;
578 else if (adev->asic_type == CHIP_VEGA20)
579 adev->nbio_funcs = &nbio_v7_4_funcs;
581 adev->nbio_funcs = &nbio_v6_1_funcs;
583 if (adev->asic_type == CHIP_VEGA20)
584 adev->df_funcs = &df_v3_6_funcs;
586 adev->df_funcs = &df_v1_7_funcs;
588 adev->rev_id = soc15_get_rev_id(adev);
589 adev->nbio_funcs->detect_hw_virt(adev);
591 if (amdgpu_sriov_vf(adev))
592 adev->virt.ops = &xgpu_ai_virt_ops;
594 switch (adev->asic_type) {
598 amdgpu_device_ip_block_add(adev, &vega10_common_ip_block);
599 amdgpu_device_ip_block_add(adev, &gmc_v9_0_ip_block);
600 amdgpu_device_ip_block_add(adev, &vega10_ih_ip_block);
601 if (likely(adev->firmware.load_type == AMDGPU_FW_LOAD_PSP)) {
602 if (adev->asic_type == CHIP_VEGA20)
603 amdgpu_device_ip_block_add(adev, &psp_v11_0_ip_block);
605 amdgpu_device_ip_block_add(adev, &psp_v3_1_ip_block);
607 amdgpu_device_ip_block_add(adev, &gfx_v9_0_ip_block);
608 amdgpu_device_ip_block_add(adev, &sdma_v4_0_ip_block);
609 if (!amdgpu_sriov_vf(adev)) {
610 if (is_support_sw_smu(adev))
611 amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block);
613 amdgpu_device_ip_block_add(adev, &pp_smu_ip_block);
615 if (adev->enable_virtual_display || amdgpu_sriov_vf(adev))
616 amdgpu_device_ip_block_add(adev, &dce_virtual_ip_block);
617 #if defined(CONFIG_DRM_AMD_DC)
618 else if (amdgpu_device_has_dc_support(adev))
619 amdgpu_device_ip_block_add(adev, &dm_ip_block);
621 # warning "Enable CONFIG_DRM_AMD_DC for display support on SOC15."
623 if (!(adev->asic_type == CHIP_VEGA20 && amdgpu_sriov_vf(adev))) {
624 amdgpu_device_ip_block_add(adev, &uvd_v7_0_ip_block);
625 amdgpu_device_ip_block_add(adev, &vce_v4_0_ip_block);
629 amdgpu_device_ip_block_add(adev, &vega10_common_ip_block);
630 amdgpu_device_ip_block_add(adev, &gmc_v9_0_ip_block);
631 amdgpu_device_ip_block_add(adev, &vega10_ih_ip_block);
632 if (likely(adev->firmware.load_type == AMDGPU_FW_LOAD_PSP))
633 amdgpu_device_ip_block_add(adev, &psp_v10_0_ip_block);
634 amdgpu_device_ip_block_add(adev, &gfx_v9_0_ip_block);
635 amdgpu_device_ip_block_add(adev, &sdma_v4_0_ip_block);
636 amdgpu_device_ip_block_add(adev, &pp_smu_ip_block);
637 if (adev->enable_virtual_display || amdgpu_sriov_vf(adev))
638 amdgpu_device_ip_block_add(adev, &dce_virtual_ip_block);
639 #if defined(CONFIG_DRM_AMD_DC)
640 else if (amdgpu_device_has_dc_support(adev))
641 amdgpu_device_ip_block_add(adev, &dm_ip_block);
643 # warning "Enable CONFIG_DRM_AMD_DC for display support on SOC15."
645 amdgpu_device_ip_block_add(adev, &vcn_v1_0_ip_block);
654 static void soc15_flush_hdp(struct amdgpu_device *adev, struct amdgpu_ring *ring)
656 adev->nbio_funcs->hdp_flush(adev, ring);
659 static void soc15_invalidate_hdp(struct amdgpu_device *adev,
660 struct amdgpu_ring *ring)
662 if (!ring || !ring->funcs->emit_wreg)
663 WREG32_SOC15_NO_KIQ(NBIO, 0, mmHDP_READ_CACHE_INVALIDATE, 1);
665 amdgpu_ring_emit_wreg(ring, SOC15_REG_OFFSET(
666 HDP, 0, mmHDP_READ_CACHE_INVALIDATE), 1);
669 static bool soc15_need_full_reset(struct amdgpu_device *adev)
671 /* change this when we implement soft reset */
674 static void soc15_get_pcie_usage(struct amdgpu_device *adev, uint64_t *count0,
677 uint32_t perfctr = 0;
678 uint64_t cnt0_of, cnt1_of;
681 /* This reports 0 on APUs, so return to avoid writing/reading registers
682 * that may or may not be different from their GPU counterparts
684 if (adev->flags & AMD_IS_APU)
687 /* Set the 2 events that we wish to watch, defined above */
688 /* Reg 40 is # received msgs, Reg 104 is # of posted requests sent */
689 perfctr = REG_SET_FIELD(perfctr, PCIE_PERF_CNTL_TXCLK, EVENT0_SEL, 40);
690 perfctr = REG_SET_FIELD(perfctr, PCIE_PERF_CNTL_TXCLK, EVENT1_SEL, 104);
692 /* Write to enable desired perf counters */
693 WREG32_PCIE(smnPCIE_PERF_CNTL_TXCLK, perfctr);
694 /* Zero out and enable the perf counters
696 * Bit 0 = Start all counters(1)
697 * Bit 2 = Global counter reset enable(1)
699 WREG32_PCIE(smnPCIE_PERF_COUNT_CNTL, 0x00000005);
703 /* Load the shadow and disable the perf counters
705 * Bit 0 = Stop counters(0)
706 * Bit 1 = Load the shadow counters(1)
708 WREG32_PCIE(smnPCIE_PERF_COUNT_CNTL, 0x00000002);
710 /* Read register values to get any >32bit overflow */
711 tmp = RREG32_PCIE(smnPCIE_PERF_CNTL_TXCLK);
712 cnt0_of = REG_GET_FIELD(tmp, PCIE_PERF_CNTL_TXCLK, COUNTER0_UPPER);
713 cnt1_of = REG_GET_FIELD(tmp, PCIE_PERF_CNTL_TXCLK, COUNTER1_UPPER);
715 /* Get the values and add the overflow */
716 *count0 = RREG32_PCIE(smnPCIE_PERF_COUNT0_TXCLK) | (cnt0_of << 32);
717 *count1 = RREG32_PCIE(smnPCIE_PERF_COUNT1_TXCLK) | (cnt1_of << 32);
720 static bool soc15_need_reset_on_init(struct amdgpu_device *adev)
724 if (adev->flags & AMD_IS_APU)
727 /* Check sOS sign of life register to confirm sys driver and sOS
728 * are already been loaded.
730 sol_reg = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_81);
737 static const struct amdgpu_asic_funcs soc15_asic_funcs =
739 .read_disabled_bios = &soc15_read_disabled_bios,
740 .read_bios_from_rom = &soc15_read_bios_from_rom,
741 .read_register = &soc15_read_register,
742 .reset = &soc15_asic_reset,
743 .set_vga_state = &soc15_vga_set_state,
744 .get_xclk = &soc15_get_xclk,
745 .set_uvd_clocks = &soc15_set_uvd_clocks,
746 .set_vce_clocks = &soc15_set_vce_clocks,
747 .get_config_memsize = &soc15_get_config_memsize,
748 .flush_hdp = &soc15_flush_hdp,
749 .invalidate_hdp = &soc15_invalidate_hdp,
750 .need_full_reset = &soc15_need_full_reset,
751 .init_doorbell_index = &vega10_doorbell_index_init,
752 .get_pcie_usage = &soc15_get_pcie_usage,
753 .need_reset_on_init = &soc15_need_reset_on_init,
756 static const struct amdgpu_asic_funcs vega20_asic_funcs =
758 .read_disabled_bios = &soc15_read_disabled_bios,
759 .read_bios_from_rom = &soc15_read_bios_from_rom,
760 .read_register = &soc15_read_register,
761 .reset = &soc15_asic_reset,
762 .set_vga_state = &soc15_vga_set_state,
763 .get_xclk = &soc15_get_xclk,
764 .set_uvd_clocks = &soc15_set_uvd_clocks,
765 .set_vce_clocks = &soc15_set_vce_clocks,
766 .get_config_memsize = &soc15_get_config_memsize,
767 .flush_hdp = &soc15_flush_hdp,
768 .invalidate_hdp = &soc15_invalidate_hdp,
769 .need_full_reset = &soc15_need_full_reset,
770 .init_doorbell_index = &vega20_doorbell_index_init,
771 .get_pcie_usage = &soc15_get_pcie_usage,
772 .need_reset_on_init = &soc15_need_reset_on_init,
775 static int soc15_common_early_init(void *handle)
777 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
779 adev->smc_rreg = NULL;
780 adev->smc_wreg = NULL;
781 adev->pcie_rreg = &soc15_pcie_rreg;
782 adev->pcie_wreg = &soc15_pcie_wreg;
783 adev->uvd_ctx_rreg = &soc15_uvd_ctx_rreg;
784 adev->uvd_ctx_wreg = &soc15_uvd_ctx_wreg;
785 adev->didt_rreg = &soc15_didt_rreg;
786 adev->didt_wreg = &soc15_didt_wreg;
787 adev->gc_cac_rreg = &soc15_gc_cac_rreg;
788 adev->gc_cac_wreg = &soc15_gc_cac_wreg;
789 adev->se_cac_rreg = &soc15_se_cac_rreg;
790 adev->se_cac_wreg = &soc15_se_cac_wreg;
793 adev->external_rev_id = 0xFF;
794 switch (adev->asic_type) {
796 adev->asic_funcs = &soc15_asic_funcs;
797 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
798 AMD_CG_SUPPORT_GFX_MGLS |
799 AMD_CG_SUPPORT_GFX_RLC_LS |
800 AMD_CG_SUPPORT_GFX_CP_LS |
801 AMD_CG_SUPPORT_GFX_3D_CGCG |
802 AMD_CG_SUPPORT_GFX_3D_CGLS |
803 AMD_CG_SUPPORT_GFX_CGCG |
804 AMD_CG_SUPPORT_GFX_CGLS |
805 AMD_CG_SUPPORT_BIF_MGCG |
806 AMD_CG_SUPPORT_BIF_LS |
807 AMD_CG_SUPPORT_HDP_LS |
808 AMD_CG_SUPPORT_DRM_MGCG |
809 AMD_CG_SUPPORT_DRM_LS |
810 AMD_CG_SUPPORT_ROM_MGCG |
811 AMD_CG_SUPPORT_DF_MGCG |
812 AMD_CG_SUPPORT_SDMA_MGCG |
813 AMD_CG_SUPPORT_SDMA_LS |
814 AMD_CG_SUPPORT_MC_MGCG |
815 AMD_CG_SUPPORT_MC_LS;
817 adev->external_rev_id = 0x1;
820 adev->asic_funcs = &soc15_asic_funcs;
821 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
822 AMD_CG_SUPPORT_GFX_MGLS |
823 AMD_CG_SUPPORT_GFX_CGCG |
824 AMD_CG_SUPPORT_GFX_CGLS |
825 AMD_CG_SUPPORT_GFX_3D_CGCG |
826 AMD_CG_SUPPORT_GFX_3D_CGLS |
827 AMD_CG_SUPPORT_GFX_CP_LS |
828 AMD_CG_SUPPORT_MC_LS |
829 AMD_CG_SUPPORT_MC_MGCG |
830 AMD_CG_SUPPORT_SDMA_MGCG |
831 AMD_CG_SUPPORT_SDMA_LS |
832 AMD_CG_SUPPORT_BIF_MGCG |
833 AMD_CG_SUPPORT_BIF_LS |
834 AMD_CG_SUPPORT_HDP_MGCG |
835 AMD_CG_SUPPORT_HDP_LS |
836 AMD_CG_SUPPORT_ROM_MGCG |
837 AMD_CG_SUPPORT_VCE_MGCG |
838 AMD_CG_SUPPORT_UVD_MGCG;
840 adev->external_rev_id = adev->rev_id + 0x14;
843 adev->asic_funcs = &vega20_asic_funcs;
844 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
845 AMD_CG_SUPPORT_GFX_MGLS |
846 AMD_CG_SUPPORT_GFX_CGCG |
847 AMD_CG_SUPPORT_GFX_CGLS |
848 AMD_CG_SUPPORT_GFX_3D_CGCG |
849 AMD_CG_SUPPORT_GFX_3D_CGLS |
850 AMD_CG_SUPPORT_GFX_CP_LS |
851 AMD_CG_SUPPORT_MC_LS |
852 AMD_CG_SUPPORT_MC_MGCG |
853 AMD_CG_SUPPORT_SDMA_MGCG |
854 AMD_CG_SUPPORT_SDMA_LS |
855 AMD_CG_SUPPORT_BIF_MGCG |
856 AMD_CG_SUPPORT_BIF_LS |
857 AMD_CG_SUPPORT_HDP_MGCG |
858 AMD_CG_SUPPORT_HDP_LS |
859 AMD_CG_SUPPORT_ROM_MGCG |
860 AMD_CG_SUPPORT_VCE_MGCG |
861 AMD_CG_SUPPORT_UVD_MGCG;
863 adev->external_rev_id = adev->rev_id + 0x28;
866 adev->asic_funcs = &soc15_asic_funcs;
867 if (adev->rev_id >= 0x8)
868 adev->external_rev_id = adev->rev_id + 0x79;
869 else if (adev->pdev->device == 0x15d8)
870 adev->external_rev_id = adev->rev_id + 0x41;
871 else if (adev->rev_id == 1)
872 adev->external_rev_id = adev->rev_id + 0x20;
874 adev->external_rev_id = adev->rev_id + 0x01;
876 if (adev->rev_id >= 0x8) {
877 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
878 AMD_CG_SUPPORT_GFX_MGLS |
879 AMD_CG_SUPPORT_GFX_CP_LS |
880 AMD_CG_SUPPORT_GFX_3D_CGCG |
881 AMD_CG_SUPPORT_GFX_3D_CGLS |
882 AMD_CG_SUPPORT_GFX_CGCG |
883 AMD_CG_SUPPORT_GFX_CGLS |
884 AMD_CG_SUPPORT_BIF_LS |
885 AMD_CG_SUPPORT_HDP_LS |
886 AMD_CG_SUPPORT_ROM_MGCG |
887 AMD_CG_SUPPORT_MC_MGCG |
888 AMD_CG_SUPPORT_MC_LS |
889 AMD_CG_SUPPORT_SDMA_MGCG |
890 AMD_CG_SUPPORT_SDMA_LS |
891 AMD_CG_SUPPORT_VCN_MGCG;
893 adev->pg_flags = AMD_PG_SUPPORT_SDMA | AMD_PG_SUPPORT_VCN;
894 } else if (adev->pdev->device == 0x15d8) {
895 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGLS |
896 AMD_CG_SUPPORT_GFX_CP_LS |
897 AMD_CG_SUPPORT_GFX_3D_CGCG |
898 AMD_CG_SUPPORT_GFX_3D_CGLS |
899 AMD_CG_SUPPORT_GFX_CGCG |
900 AMD_CG_SUPPORT_GFX_CGLS |
901 AMD_CG_SUPPORT_BIF_LS |
902 AMD_CG_SUPPORT_HDP_LS |
903 AMD_CG_SUPPORT_ROM_MGCG |
904 AMD_CG_SUPPORT_MC_MGCG |
905 AMD_CG_SUPPORT_MC_LS |
906 AMD_CG_SUPPORT_SDMA_MGCG |
907 AMD_CG_SUPPORT_SDMA_LS;
909 adev->pg_flags = AMD_PG_SUPPORT_SDMA |
910 AMD_PG_SUPPORT_MMHUB |
912 AMD_PG_SUPPORT_VCN_DPG;
914 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
915 AMD_CG_SUPPORT_GFX_MGLS |
916 AMD_CG_SUPPORT_GFX_RLC_LS |
917 AMD_CG_SUPPORT_GFX_CP_LS |
918 AMD_CG_SUPPORT_GFX_3D_CGCG |
919 AMD_CG_SUPPORT_GFX_3D_CGLS |
920 AMD_CG_SUPPORT_GFX_CGCG |
921 AMD_CG_SUPPORT_GFX_CGLS |
922 AMD_CG_SUPPORT_BIF_MGCG |
923 AMD_CG_SUPPORT_BIF_LS |
924 AMD_CG_SUPPORT_HDP_MGCG |
925 AMD_CG_SUPPORT_HDP_LS |
926 AMD_CG_SUPPORT_DRM_MGCG |
927 AMD_CG_SUPPORT_DRM_LS |
928 AMD_CG_SUPPORT_ROM_MGCG |
929 AMD_CG_SUPPORT_MC_MGCG |
930 AMD_CG_SUPPORT_MC_LS |
931 AMD_CG_SUPPORT_SDMA_MGCG |
932 AMD_CG_SUPPORT_SDMA_LS |
933 AMD_CG_SUPPORT_VCN_MGCG;
935 adev->pg_flags = AMD_PG_SUPPORT_SDMA | AMD_PG_SUPPORT_VCN;
938 if (adev->pm.pp_feature & PP_GFXOFF_MASK)
939 adev->pg_flags |= AMD_PG_SUPPORT_GFX_PG |
941 AMD_PG_SUPPORT_RLC_SMU_HS;
944 /* FIXME: not supported yet */
948 if (amdgpu_sriov_vf(adev)) {
949 amdgpu_virt_init_setting(adev);
950 xgpu_ai_mailbox_set_irq_funcs(adev);
956 static int soc15_common_late_init(void *handle)
958 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
960 if (amdgpu_sriov_vf(adev))
961 xgpu_ai_mailbox_get_irq(adev);
966 static int soc15_common_sw_init(void *handle)
968 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
970 if (amdgpu_sriov_vf(adev))
971 xgpu_ai_mailbox_add_irq_id(adev);
976 static int soc15_common_sw_fini(void *handle)
981 static void soc15_doorbell_range_init(struct amdgpu_device *adev)
984 struct amdgpu_ring *ring;
986 for (i = 0; i < adev->sdma.num_instances; i++) {
987 ring = &adev->sdma.instance[i].ring;
988 adev->nbio_funcs->sdma_doorbell_range(adev, i,
989 ring->use_doorbell, ring->doorbell_index,
990 adev->doorbell_index.sdma_doorbell_range);
993 adev->nbio_funcs->ih_doorbell_range(adev, adev->irq.ih.use_doorbell,
994 adev->irq.ih.doorbell_index);
997 static int soc15_common_hw_init(void *handle)
999 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1001 /* enable pcie gen2/3 link */
1002 soc15_pcie_gen3_enable(adev);
1004 soc15_program_aspm(adev);
1005 /* setup nbio registers */
1006 adev->nbio_funcs->init_registers(adev);
1007 /* enable the doorbell aperture */
1008 soc15_enable_doorbell_aperture(adev, true);
1009 /* HW doorbell routing policy: doorbell writing not
1010 * in SDMA/IH/MM/ACV range will be routed to CP. So
1011 * we need to init SDMA/IH/MM/ACV doorbell range prior
1012 * to CP ip block init and ring test.
1014 soc15_doorbell_range_init(adev);
1019 static int soc15_common_hw_fini(void *handle)
1021 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1023 /* disable the doorbell aperture */
1024 soc15_enable_doorbell_aperture(adev, false);
1025 if (amdgpu_sriov_vf(adev))
1026 xgpu_ai_mailbox_put_irq(adev);
1031 static int soc15_common_suspend(void *handle)
1033 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1035 return soc15_common_hw_fini(adev);
1038 static int soc15_common_resume(void *handle)
1040 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1042 return soc15_common_hw_init(adev);
1045 static bool soc15_common_is_idle(void *handle)
1050 static int soc15_common_wait_for_idle(void *handle)
1055 static int soc15_common_soft_reset(void *handle)
1060 static void soc15_update_hdp_light_sleep(struct amdgpu_device *adev, bool enable)
1064 if (adev->asic_type == CHIP_VEGA20) {
1065 def = data = RREG32(SOC15_REG_OFFSET(HDP, 0, mmHDP_MEM_POWER_CTRL));
1067 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_HDP_LS))
1068 data |= HDP_MEM_POWER_CTRL__IPH_MEM_POWER_CTRL_EN_MASK |
1069 HDP_MEM_POWER_CTRL__IPH_MEM_POWER_LS_EN_MASK |
1070 HDP_MEM_POWER_CTRL__RC_MEM_POWER_CTRL_EN_MASK |
1071 HDP_MEM_POWER_CTRL__RC_MEM_POWER_LS_EN_MASK;
1073 data &= ~(HDP_MEM_POWER_CTRL__IPH_MEM_POWER_CTRL_EN_MASK |
1074 HDP_MEM_POWER_CTRL__IPH_MEM_POWER_LS_EN_MASK |
1075 HDP_MEM_POWER_CTRL__RC_MEM_POWER_CTRL_EN_MASK |
1076 HDP_MEM_POWER_CTRL__RC_MEM_POWER_LS_EN_MASK);
1079 WREG32(SOC15_REG_OFFSET(HDP, 0, mmHDP_MEM_POWER_CTRL), data);
1081 def = data = RREG32(SOC15_REG_OFFSET(HDP, 0, mmHDP_MEM_POWER_LS));
1083 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_HDP_LS))
1084 data |= HDP_MEM_POWER_LS__LS_ENABLE_MASK;
1086 data &= ~HDP_MEM_POWER_LS__LS_ENABLE_MASK;
1089 WREG32(SOC15_REG_OFFSET(HDP, 0, mmHDP_MEM_POWER_LS), data);
1093 static void soc15_update_drm_clock_gating(struct amdgpu_device *adev, bool enable)
1097 def = data = RREG32(SOC15_REG_OFFSET(MP0, 0, mmMP0_MISC_CGTT_CTRL0));
1099 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_DRM_MGCG))
1100 data &= ~(0x01000000 |
1109 data |= (0x01000000 |
1119 WREG32(SOC15_REG_OFFSET(MP0, 0, mmMP0_MISC_CGTT_CTRL0), data);
1122 static void soc15_update_drm_light_sleep(struct amdgpu_device *adev, bool enable)
1126 def = data = RREG32(SOC15_REG_OFFSET(MP0, 0, mmMP0_MISC_LIGHT_SLEEP_CTRL));
1128 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_DRM_LS))
1134 WREG32(SOC15_REG_OFFSET(MP0, 0, mmMP0_MISC_LIGHT_SLEEP_CTRL), data);
1137 static void soc15_update_rom_medium_grain_clock_gating(struct amdgpu_device *adev,
1142 def = data = RREG32(SOC15_REG_OFFSET(SMUIO, 0, mmCGTT_ROM_CLK_CTRL0));
1144 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_ROM_MGCG))
1145 data &= ~(CGTT_ROM_CLK_CTRL0__SOFT_OVERRIDE0_MASK |
1146 CGTT_ROM_CLK_CTRL0__SOFT_OVERRIDE1_MASK);
1148 data |= CGTT_ROM_CLK_CTRL0__SOFT_OVERRIDE0_MASK |
1149 CGTT_ROM_CLK_CTRL0__SOFT_OVERRIDE1_MASK;
1152 WREG32(SOC15_REG_OFFSET(SMUIO, 0, mmCGTT_ROM_CLK_CTRL0), data);
1155 static int soc15_common_set_clockgating_state(void *handle,
1156 enum amd_clockgating_state state)
1158 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1160 if (amdgpu_sriov_vf(adev))
1163 switch (adev->asic_type) {
1167 adev->nbio_funcs->update_medium_grain_clock_gating(adev,
1168 state == AMD_CG_STATE_GATE ? true : false);
1169 adev->nbio_funcs->update_medium_grain_light_sleep(adev,
1170 state == AMD_CG_STATE_GATE ? true : false);
1171 soc15_update_hdp_light_sleep(adev,
1172 state == AMD_CG_STATE_GATE ? true : false);
1173 soc15_update_drm_clock_gating(adev,
1174 state == AMD_CG_STATE_GATE ? true : false);
1175 soc15_update_drm_light_sleep(adev,
1176 state == AMD_CG_STATE_GATE ? true : false);
1177 soc15_update_rom_medium_grain_clock_gating(adev,
1178 state == AMD_CG_STATE_GATE ? true : false);
1179 adev->df_funcs->update_medium_grain_clock_gating(adev,
1180 state == AMD_CG_STATE_GATE ? true : false);
1183 adev->nbio_funcs->update_medium_grain_clock_gating(adev,
1184 state == AMD_CG_STATE_GATE ? true : false);
1185 adev->nbio_funcs->update_medium_grain_light_sleep(adev,
1186 state == AMD_CG_STATE_GATE ? true : false);
1187 soc15_update_hdp_light_sleep(adev,
1188 state == AMD_CG_STATE_GATE ? true : false);
1189 soc15_update_drm_clock_gating(adev,
1190 state == AMD_CG_STATE_GATE ? true : false);
1191 soc15_update_drm_light_sleep(adev,
1192 state == AMD_CG_STATE_GATE ? true : false);
1193 soc15_update_rom_medium_grain_clock_gating(adev,
1194 state == AMD_CG_STATE_GATE ? true : false);
1202 static void soc15_common_get_clockgating_state(void *handle, u32 *flags)
1204 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1207 if (amdgpu_sriov_vf(adev))
1210 adev->nbio_funcs->get_clockgating_state(adev, flags);
1212 /* AMD_CG_SUPPORT_HDP_LS */
1213 data = RREG32(SOC15_REG_OFFSET(HDP, 0, mmHDP_MEM_POWER_LS));
1214 if (data & HDP_MEM_POWER_LS__LS_ENABLE_MASK)
1215 *flags |= AMD_CG_SUPPORT_HDP_LS;
1217 /* AMD_CG_SUPPORT_DRM_MGCG */
1218 data = RREG32(SOC15_REG_OFFSET(MP0, 0, mmMP0_MISC_CGTT_CTRL0));
1219 if (!(data & 0x01000000))
1220 *flags |= AMD_CG_SUPPORT_DRM_MGCG;
1222 /* AMD_CG_SUPPORT_DRM_LS */
1223 data = RREG32(SOC15_REG_OFFSET(MP0, 0, mmMP0_MISC_LIGHT_SLEEP_CTRL));
1225 *flags |= AMD_CG_SUPPORT_DRM_LS;
1227 /* AMD_CG_SUPPORT_ROM_MGCG */
1228 data = RREG32(SOC15_REG_OFFSET(SMUIO, 0, mmCGTT_ROM_CLK_CTRL0));
1229 if (!(data & CGTT_ROM_CLK_CTRL0__SOFT_OVERRIDE0_MASK))
1230 *flags |= AMD_CG_SUPPORT_ROM_MGCG;
1232 adev->df_funcs->get_clockgating_state(adev, flags);
1235 static int soc15_common_set_powergating_state(void *handle,
1236 enum amd_powergating_state state)
1242 const struct amd_ip_funcs soc15_common_ip_funcs = {
1243 .name = "soc15_common",
1244 .early_init = soc15_common_early_init,
1245 .late_init = soc15_common_late_init,
1246 .sw_init = soc15_common_sw_init,
1247 .sw_fini = soc15_common_sw_fini,
1248 .hw_init = soc15_common_hw_init,
1249 .hw_fini = soc15_common_hw_fini,
1250 .suspend = soc15_common_suspend,
1251 .resume = soc15_common_resume,
1252 .is_idle = soc15_common_is_idle,
1253 .wait_for_idle = soc15_common_wait_for_idle,
1254 .soft_reset = soc15_common_soft_reset,
1255 .set_clockgating_state = soc15_common_set_clockgating_state,
1256 .set_powergating_state = soc15_common_set_powergating_state,
1257 .get_clockgating_state= soc15_common_get_clockgating_state,