drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c

   1 /*
   2  * Copyright 2016 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23
  24 #include <linux/firmware.h>
  25 #include <drm/drmP.h>
  26 #include "amdgpu.h"
  27 #include "amdgpu_vcn.h"
  28 #include "soc15.h"
  29 #include "soc15d.h"
  30 #include "soc15_common.h"
  31
  32 #include "vcn/vcn_1_0_offset.h"
  33 #include "vcn/vcn_1_0_sh_mask.h"
  34 #include "hdp/hdp_4_0_offset.h"
  35 #include "mmhub/mmhub_9_1_offset.h"
  36 #include "mmhub/mmhub_9_1_sh_mask.h"
  37
  38 #include "ivsrcid/vcn/irqsrcs_vcn_1_0.h"
  39
  40 static int vcn_v1_0_stop(struct amdgpu_device *adev);
  41 static void vcn_v1_0_set_dec_ring_funcs(struct amdgpu_device *adev);
  42 static void vcn_v1_0_set_enc_ring_funcs(struct amdgpu_device *adev);
  43 static void vcn_v1_0_set_jpeg_ring_funcs(struct amdgpu_device *adev);
  44 static void vcn_v1_0_set_irq_funcs(struct amdgpu_device *adev);
  45 static void vcn_v1_0_jpeg_ring_set_patch_ring(struct amdgpu_ring *ring, uint32_t ptr);
  46
  47 /**
  48  * vcn_v1_0_early_init - set function pointers
  49  *
  50  * @handle: amdgpu_device pointer
  51  *
  52  * Set ring and irq function pointers
  53  */
  54 static int vcn_v1_0_early_init(void *handle)
  55 {
  56         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
  57
  58         adev->vcn.num_enc_rings = 2;
  59
  60         vcn_v1_0_set_dec_ring_funcs(adev);
  61         vcn_v1_0_set_enc_ring_funcs(adev);
  62         vcn_v1_0_set_jpeg_ring_funcs(adev);
  63         vcn_v1_0_set_irq_funcs(adev);
  64
  65         return 0;
  66 }
  67
  68 /**
  69  * vcn_v1_0_sw_init - sw init for VCN block
  70  *
  71  * @handle: amdgpu_device pointer
  72  *
  73  * Load firmware and sw initialization
  74  */
  75 static int vcn_v1_0_sw_init(void *handle)
  76 {
  77         struct amdgpu_ring *ring;
  78         int i, r;
  79         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
  80
  81         /* VCN DEC TRAP */
  82         r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_VCN, VCN_1_0__SRCID__UVD_SYSTEM_MESSAGE_INTERRUPT, &adev->vcn.irq);
  83         if (r)
  84                 return r;
  85
  86         /* VCN ENC TRAP */
  87         for (i = 0; i < adev->vcn.num_enc_rings; ++i) {
  88                 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_VCN, i + VCN_1_0__SRCID__UVD_ENC_GENERAL_PURPOSE,
  89                                         &adev->vcn.irq);
  90                 if (r)
  91                         return r;
  92         }
  93
  94         /* VCN JPEG TRAP */
  95         r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_VCN, 126, &adev->vcn.irq);
  96         if (r)
  97                 return r;
  98
  99         r = amdgpu_vcn_sw_init(adev);
 100         if (r)
 101                 return r;
 102
 103         if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
 104                 const struct common_firmware_header *hdr;
 105                 hdr = (const struct common_firmware_header *)adev->vcn.fw->data;
 106                 adev->firmware.ucode[AMDGPU_UCODE_ID_VCN].ucode_id = AMDGPU_UCODE_ID_VCN;
 107                 adev->firmware.ucode[AMDGPU_UCODE_ID_VCN].fw = adev->vcn.fw;
 108                 adev->firmware.fw_size +=
 109                         ALIGN(le32_to_cpu(hdr->ucode_size_bytes), PAGE_SIZE);
 110                 DRM_INFO("PSP loading VCN firmware\n");
 111         }
 112
 113         r = amdgpu_vcn_resume(adev);
 114         if (r)
 115                 return r;
 116
 117         ring = &adev->vcn.ring_dec;
 118         sprintf(ring->name, "vcn_dec");
 119         r = amdgpu_ring_init(adev, ring, 512, &adev->vcn.irq, 0);
 120         if (r)
 121                 return r;
 122
 123         for (i = 0; i < adev->vcn.num_enc_rings; ++i) {
 124                 ring = &adev->vcn.ring_enc[i];
 125                 sprintf(ring->name, "vcn_enc%d", i);
 126                 r = amdgpu_ring_init(adev, ring, 512, &adev->vcn.irq, 0);
 127                 if (r)
 128                         return r;
 129         }
 130
 131         ring = &adev->vcn.ring_jpeg;
 132         sprintf(ring->name, "vcn_jpeg");
 133         r = amdgpu_ring_init(adev, ring, 512, &adev->vcn.irq, 0);
 134         if (r)
 135                 return r;
 136
 137         return r;
 138 }
 139
 140 /**
 141  * vcn_v1_0_sw_fini - sw fini for VCN block
 142  *
 143  * @handle: amdgpu_device pointer
 144  *
 145  * VCN suspend and free up sw allocation
 146  */
 147 static int vcn_v1_0_sw_fini(void *handle)
 148 {
 149         int r;
 150         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 151
 152         r = amdgpu_vcn_suspend(adev);
 153         if (r)
 154                 return r;
 155
 156         r = amdgpu_vcn_sw_fini(adev);
 157
 158         return r;
 159 }
 160
 161 /**
 162  * vcn_v1_0_hw_init - start and test VCN block
 163  *
 164  * @handle: amdgpu_device pointer
 165  *
 166  * Initialize the hardware, boot up the VCPU and do some testing
 167  */
 168 static int vcn_v1_0_hw_init(void *handle)
 169 {
 170         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 171         struct amdgpu_ring *ring = &adev->vcn.ring_dec;
 172         int i, r;
 173
 174         ring->ready = true;
 175         r = amdgpu_ring_test_ring(ring);
 176         if (r) {
 177                 ring->ready = false;
 178                 goto done;
 179         }
 180
 181         for (i = 0; i < adev->vcn.num_enc_rings; ++i) {
 182                 ring = &adev->vcn.ring_enc[i];
 183                 ring->ready = true;
 184                 r = amdgpu_ring_test_ring(ring);
 185                 if (r) {
 186                         ring->ready = false;
 187                         goto done;
 188                 }
 189         }
 190
 191         ring = &adev->vcn.ring_jpeg;
 192         ring->ready = true;
 193         r = amdgpu_ring_test_ring(ring);
 194         if (r) {
 195                 ring->ready = false;
 196                 goto done;
 197         }
 198
 199 done:
 200         if (!r)
 201                 DRM_INFO("VCN decode and encode initialized successfully(under %s).\n",
 202                         (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG)?"DPG Mode":"SPG Mode");
 203
 204         return r;
 205 }
 206
 207 /**
 208  * vcn_v1_0_hw_fini - stop the hardware block
 209  *
 210  * @handle: amdgpu_device pointer
 211  *
 212  * Stop the VCN block, mark ring as not ready any more
 213  */
 214 static int vcn_v1_0_hw_fini(void *handle)
 215 {
 216         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 217         struct amdgpu_ring *ring = &adev->vcn.ring_dec;
 218
 219         if (RREG32_SOC15(VCN, 0, mmUVD_STATUS))
 220                 vcn_v1_0_stop(adev);
 221
 222         ring->ready = false;
 223
 224         return 0;
 225 }
 226
 227 /**
 228  * vcn_v1_0_suspend - suspend VCN block
 229  *
 230  * @handle: amdgpu_device pointer
 231  *
 232  * HW fini and suspend VCN block
 233  */
 234 static int vcn_v1_0_suspend(void *handle)
 235 {
 236         int r;
 237         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 238
 239         r = vcn_v1_0_hw_fini(adev);
 240         if (r)
 241                 return r;
 242
 243         r = amdgpu_vcn_suspend(adev);
 244
 245         return r;
 246 }
 247
 248 /**
 249  * vcn_v1_0_resume - resume VCN block
 250  *
 251  * @handle: amdgpu_device pointer
 252  *
 253  * Resume firmware and hw init VCN block
 254  */
 255 static int vcn_v1_0_resume(void *handle)
 256 {
 257         int r;
 258         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 259
 260         r = amdgpu_vcn_resume(adev);
 261         if (r)
 262                 return r;
 263
 264         r = vcn_v1_0_hw_init(adev);
 265
 266         return r;
 267 }
 268
 269 /**
 270  * vcn_v1_0_mc_resume_spg_mode - memory controller programming
 271  *
 272  * @adev: amdgpu_device pointer
 273  *
 274  * Let the VCN memory controller know it's offsets
 275  */
 276 static void vcn_v1_0_mc_resume_spg_mode(struct amdgpu_device *adev)
 277 {
 278         uint32_t size = AMDGPU_GPU_PAGE_ALIGN(adev->vcn.fw->size + 4);
 279         uint32_t offset;
 280
 281         /* cache window 0: fw */
 282         if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
 283                 WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW,
 284                              (adev->firmware.ucode[AMDGPU_UCODE_ID_VCN].tmr_mc_addr_lo));
 285                 WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH,
 286                              (adev->firmware.ucode[AMDGPU_UCODE_ID_VCN].tmr_mc_addr_hi));
 287                 WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_OFFSET0, 0);
 288                 offset = 0;
 289         } else {
 290                 WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW,
 291                         lower_32_bits(adev->vcn.gpu_addr));
 292                 WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH,
 293                         upper_32_bits(adev->vcn.gpu_addr));
 294                 offset = size;
 295                 WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_OFFSET0,
 296                              AMDGPU_UVD_FIRMWARE_OFFSET >> 3);
 297         }
 298
 299         WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_SIZE0, size);
 300
 301         /* cache window 1: stack */
 302         WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW,
 303                      lower_32_bits(adev->vcn.gpu_addr + offset));
 304         WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH,
 305                      upper_32_bits(adev->vcn.gpu_addr + offset));
 306         WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_OFFSET1, 0);
 307         WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_SIZE1, AMDGPU_VCN_STACK_SIZE);
 308
 309         /* cache window 2: context */
 310         WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW,
 311                      lower_32_bits(adev->vcn.gpu_addr + offset + AMDGPU_VCN_STACK_SIZE));
 312         WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH,
 313                      upper_32_bits(adev->vcn.gpu_addr + offset + AMDGPU_VCN_STACK_SIZE));
 314         WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_OFFSET2, 0);
 315         WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_SIZE2, AMDGPU_VCN_CONTEXT_SIZE);
 316
 317         WREG32_SOC15(UVD, 0, mmUVD_UDEC_ADDR_CONFIG,
 318                         adev->gfx.config.gb_addr_config);
 319         WREG32_SOC15(UVD, 0, mmUVD_UDEC_DB_ADDR_CONFIG,
 320                         adev->gfx.config.gb_addr_config);
 321         WREG32_SOC15(UVD, 0, mmUVD_UDEC_DBW_ADDR_CONFIG,
 322                         adev->gfx.config.gb_addr_config);
 323 }
 324
 325 static void vcn_v1_0_mc_resume_dpg_mode(struct amdgpu_device *adev)
 326 {
 327         uint32_t size = AMDGPU_GPU_PAGE_ALIGN(adev->vcn.fw->size + 4);
 328         uint32_t offset;
 329
 330         /* cache window 0: fw */
 331         if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
 332                 WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW,
 333                              (adev->firmware.ucode[AMDGPU_UCODE_ID_VCN].tmr_mc_addr_lo),
 334                              0xFFFFFFFF, 0);
 335                 WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH,
 336                              (adev->firmware.ucode[AMDGPU_UCODE_ID_VCN].tmr_mc_addr_hi),
 337                              0xFFFFFFFF, 0);
 338                 WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_VCPU_CACHE_OFFSET0, 0,
 339                              0xFFFFFFFF, 0);
 340                 offset = 0;
 341         } else {
 342                 WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW,
 343                         lower_32_bits(adev->vcn.gpu_addr), 0xFFFFFFFF, 0);
 344                 WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH,
 345                         upper_32_bits(adev->vcn.gpu_addr), 0xFFFFFFFF, 0);
 346                 offset = size;
 347                 WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_VCPU_CACHE_OFFSET0,
 348                              AMDGPU_UVD_FIRMWARE_OFFSET >> 3, 0xFFFFFFFF, 0);
 349         }
 350
 351         WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_VCPU_CACHE_SIZE0, size, 0xFFFFFFFF, 0);
 352
 353         /* cache window 1: stack */
 354         WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW,
 355                      lower_32_bits(adev->vcn.gpu_addr + offset), 0xFFFFFFFF, 0);
 356         WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH,
 357                      upper_32_bits(adev->vcn.gpu_addr + offset), 0xFFFFFFFF, 0);
 358         WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_VCPU_CACHE_OFFSET1, 0,
 359                              0xFFFFFFFF, 0);
 360         WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_VCPU_CACHE_SIZE1, AMDGPU_VCN_STACK_SIZE,
 361                              0xFFFFFFFF, 0);
 362
 363         /* cache window 2: context */
 364         WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW,
 365                      lower_32_bits(adev->vcn.gpu_addr + offset + AMDGPU_VCN_STACK_SIZE),
 366                              0xFFFFFFFF, 0);
 367         WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH,
 368                      upper_32_bits(adev->vcn.gpu_addr + offset + AMDGPU_VCN_STACK_SIZE),
 369                              0xFFFFFFFF, 0);
 370         WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_VCPU_CACHE_OFFSET2, 0, 0xFFFFFFFF, 0);
 371         WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_VCPU_CACHE_SIZE2, AMDGPU_VCN_CONTEXT_SIZE,
 372                              0xFFFFFFFF, 0);
 373
 374         WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_UDEC_ADDR_CONFIG,
 375                         adev->gfx.config.gb_addr_config, 0xFFFFFFFF, 0);
 376         WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_UDEC_DB_ADDR_CONFIG,
 377                         adev->gfx.config.gb_addr_config, 0xFFFFFFFF, 0);
 378         WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_UDEC_DBW_ADDR_CONFIG,
 379                         adev->gfx.config.gb_addr_config, 0xFFFFFFFF, 0);
 380         WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_JPEG_ADDR_CONFIG,
 381                         adev->gfx.config.gb_addr_config, 0xFFFFFFFF, 0);
 382         WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_JPEG_UV_ADDR_CONFIG,
 383                         adev->gfx.config.gb_addr_config, 0xFFFFFFFF, 0);
 384 }
 385
 386 /**
 387  * vcn_v1_0_disable_clock_gating - disable VCN clock gating
 388  *
 389  * @adev: amdgpu_device pointer
 390  * @sw: enable SW clock gating
 391  *
 392  * Disable clock gating for VCN block
 393  */
 394 static void vcn_v1_0_disable_clock_gating(struct amdgpu_device *adev)
 395 {
 396         uint32_t data;
 397
 398         /* JPEG disable CGC */
 399         data = RREG32_SOC15(VCN, 0, mmJPEG_CGC_CTRL);
 400
 401         if (adev->cg_flags & AMD_CG_SUPPORT_VCN_MGCG)
 402                 data |= 1 << JPEG_CGC_CTRL__DYN_CLOCK_MODE__SHIFT;
 403         else
 404                 data &= ~JPEG_CGC_CTRL__DYN_CLOCK_MODE_MASK;
 405
 406         data |= 1 << JPEG_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT;
 407         data |= 4 << JPEG_CGC_CTRL__CLK_OFF_DELAY__SHIFT;
 408         WREG32_SOC15(VCN, 0, mmJPEG_CGC_CTRL, data);
 409
 410         data = RREG32_SOC15(VCN, 0, mmJPEG_CGC_GATE);
 411         data &= ~(JPEG_CGC_GATE__JPEG_MASK | JPEG_CGC_GATE__JPEG2_MASK);
 412         WREG32_SOC15(VCN, 0, mmJPEG_CGC_GATE, data);
 413
 414         /* UVD disable CGC */
 415         data = RREG32_SOC15(VCN, 0, mmUVD_CGC_CTRL);
 416         if (adev->cg_flags & AMD_CG_SUPPORT_VCN_MGCG)
 417                 data |= 1 << UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT;
 418         else
 419                 data &= ~ UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK;
 420
 421         data |= 1 << UVD_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT;
 422         data |= 4 << UVD_CGC_CTRL__CLK_OFF_DELAY__SHIFT;
 423         WREG32_SOC15(VCN, 0, mmUVD_CGC_CTRL, data);
 424
 425         data = RREG32_SOC15(VCN, 0, mmUVD_CGC_GATE);
 426         data &= ~(UVD_CGC_GATE__SYS_MASK
 427                 | UVD_CGC_GATE__UDEC_MASK
 428                 | UVD_CGC_GATE__MPEG2_MASK
 429                 | UVD_CGC_GATE__REGS_MASK
 430                 | UVD_CGC_GATE__RBC_MASK
 431                 | UVD_CGC_GATE__LMI_MC_MASK
 432                 | UVD_CGC_GATE__LMI_UMC_MASK
 433                 | UVD_CGC_GATE__IDCT_MASK
 434                 | UVD_CGC_GATE__MPRD_MASK
 435                 | UVD_CGC_GATE__MPC_MASK
 436                 | UVD_CGC_GATE__LBSI_MASK
 437                 | UVD_CGC_GATE__LRBBM_MASK
 438                 | UVD_CGC_GATE__UDEC_RE_MASK
 439                 | UVD_CGC_GATE__UDEC_CM_MASK
 440                 | UVD_CGC_GATE__UDEC_IT_MASK
 441                 | UVD_CGC_GATE__UDEC_DB_MASK
 442                 | UVD_CGC_GATE__UDEC_MP_MASK
 443                 | UVD_CGC_GATE__WCB_MASK
 444                 | UVD_CGC_GATE__VCPU_MASK
 445                 | UVD_CGC_GATE__SCPU_MASK);
 446         WREG32_SOC15(VCN, 0, mmUVD_CGC_GATE, data);
 447
 448         data = RREG32_SOC15(VCN, 0, mmUVD_CGC_CTRL);
 449         data &= ~(UVD_CGC_CTRL__UDEC_RE_MODE_MASK
 450                 | UVD_CGC_CTRL__UDEC_CM_MODE_MASK
 451                 | UVD_CGC_CTRL__UDEC_IT_MODE_MASK
 452                 | UVD_CGC_CTRL__UDEC_DB_MODE_MASK
 453                 | UVD_CGC_CTRL__UDEC_MP_MODE_MASK
 454                 | UVD_CGC_CTRL__SYS_MODE_MASK
 455                 | UVD_CGC_CTRL__UDEC_MODE_MASK
 456                 | UVD_CGC_CTRL__MPEG2_MODE_MASK
 457                 | UVD_CGC_CTRL__REGS_MODE_MASK
 458                 | UVD_CGC_CTRL__RBC_MODE_MASK
 459                 | UVD_CGC_CTRL__LMI_MC_MODE_MASK
 460                 | UVD_CGC_CTRL__LMI_UMC_MODE_MASK
 461                 | UVD_CGC_CTRL__IDCT_MODE_MASK
 462                 | UVD_CGC_CTRL__MPRD_MODE_MASK
 463                 | UVD_CGC_CTRL__MPC_MODE_MASK
 464                 | UVD_CGC_CTRL__LBSI_MODE_MASK
 465                 | UVD_CGC_CTRL__LRBBM_MODE_MASK
 466                 | UVD_CGC_CTRL__WCB_MODE_MASK
 467                 | UVD_CGC_CTRL__VCPU_MODE_MASK
 468                 | UVD_CGC_CTRL__SCPU_MODE_MASK);
 469         WREG32_SOC15(VCN, 0, mmUVD_CGC_CTRL, data);
 470
 471         /* turn on */
 472         data = RREG32_SOC15(VCN, 0, mmUVD_SUVD_CGC_GATE);
 473         data |= (UVD_SUVD_CGC_GATE__SRE_MASK
 474                 | UVD_SUVD_CGC_GATE__SIT_MASK
 475                 | UVD_SUVD_CGC_GATE__SMP_MASK
 476                 | UVD_SUVD_CGC_GATE__SCM_MASK
 477                 | UVD_SUVD_CGC_GATE__SDB_MASK
 478                 | UVD_SUVD_CGC_GATE__SRE_H264_MASK
 479                 | UVD_SUVD_CGC_GATE__SRE_HEVC_MASK
 480                 | UVD_SUVD_CGC_GATE__SIT_H264_MASK
 481                 | UVD_SUVD_CGC_GATE__SIT_HEVC_MASK
 482                 | UVD_SUVD_CGC_GATE__SCM_H264_MASK
 483                 | UVD_SUVD_CGC_GATE__SCM_HEVC_MASK
 484                 | UVD_SUVD_CGC_GATE__SDB_H264_MASK
 485                 | UVD_SUVD_CGC_GATE__SDB_HEVC_MASK
 486                 | UVD_SUVD_CGC_GATE__SCLR_MASK
 487                 | UVD_SUVD_CGC_GATE__UVD_SC_MASK
 488                 | UVD_SUVD_CGC_GATE__ENT_MASK
 489                 | UVD_SUVD_CGC_GATE__SIT_HEVC_DEC_MASK
 490                 | UVD_SUVD_CGC_GATE__SIT_HEVC_ENC_MASK
 491                 | UVD_SUVD_CGC_GATE__SITE_MASK
 492                 | UVD_SUVD_CGC_GATE__SRE_VP9_MASK
 493                 | UVD_SUVD_CGC_GATE__SCM_VP9_MASK
 494                 | UVD_SUVD_CGC_GATE__SIT_VP9_DEC_MASK
 495                 | UVD_SUVD_CGC_GATE__SDB_VP9_MASK
 496                 | UVD_SUVD_CGC_GATE__IME_HEVC_MASK);
 497         WREG32_SOC15(VCN, 0, mmUVD_SUVD_CGC_GATE, data);
 498
 499         data = RREG32_SOC15(VCN, 0, mmUVD_SUVD_CGC_CTRL);
 500         data &= ~(UVD_SUVD_CGC_CTRL__SRE_MODE_MASK
 501                 | UVD_SUVD_CGC_CTRL__SIT_MODE_MASK
 502                 | UVD_SUVD_CGC_CTRL__SMP_MODE_MASK
 503                 | UVD_SUVD_CGC_CTRL__SCM_MODE_MASK
 504                 | UVD_SUVD_CGC_CTRL__SDB_MODE_MASK
 505                 | UVD_SUVD_CGC_CTRL__SCLR_MODE_MASK
 506                 | UVD_SUVD_CGC_CTRL__UVD_SC_MODE_MASK
 507                 | UVD_SUVD_CGC_CTRL__ENT_MODE_MASK
 508                 | UVD_SUVD_CGC_CTRL__IME_MODE_MASK
 509                 | UVD_SUVD_CGC_CTRL__SITE_MODE_MASK);
 510         WREG32_SOC15(VCN, 0, mmUVD_SUVD_CGC_CTRL, data);
 511 }
 512
 513 /**
 514  * vcn_v1_0_enable_clock_gating - enable VCN clock gating
 515  *
 516  * @adev: amdgpu_device pointer
 517  * @sw: enable SW clock gating
 518  *
 519  * Enable clock gating for VCN block
 520  */
 521 static void vcn_v1_0_enable_clock_gating(struct amdgpu_device *adev)
 522 {
 523         uint32_t data = 0;
 524
 525         /* enable JPEG CGC */
 526         data = RREG32_SOC15(VCN, 0, mmJPEG_CGC_CTRL);
 527         if (adev->cg_flags & AMD_CG_SUPPORT_VCN_MGCG)
 528                 data |= 1 << JPEG_CGC_CTRL__DYN_CLOCK_MODE__SHIFT;
 529         else
 530                 data |= 0 << JPEG_CGC_CTRL__DYN_CLOCK_MODE__SHIFT;
 531         data |= 1 << JPEG_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT;
 532         data |= 4 << JPEG_CGC_CTRL__CLK_OFF_DELAY__SHIFT;
 533         WREG32_SOC15(VCN, 0, mmJPEG_CGC_CTRL, data);
 534
 535         data = RREG32_SOC15(VCN, 0, mmJPEG_CGC_GATE);
 536         data |= (JPEG_CGC_GATE__JPEG_MASK | JPEG_CGC_GATE__JPEG2_MASK);
 537         WREG32_SOC15(VCN, 0, mmJPEG_CGC_GATE, data);
 538
 539         /* enable UVD CGC */
 540         data = RREG32_SOC15(VCN, 0, mmUVD_CGC_CTRL);
 541         if (adev->cg_flags & AMD_CG_SUPPORT_VCN_MGCG)
 542                 data |= 1 << UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT;
 543         else
 544                 data |= 0 << UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT;
 545         data |= 1 << UVD_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT;
 546         data |= 4 << UVD_CGC_CTRL__CLK_OFF_DELAY__SHIFT;
 547         WREG32_SOC15(VCN, 0, mmUVD_CGC_CTRL, data);
 548
 549         data = RREG32_SOC15(VCN, 0, mmUVD_CGC_CTRL);
 550         data |= (UVD_CGC_CTRL__UDEC_RE_MODE_MASK
 551                 | UVD_CGC_CTRL__UDEC_CM_MODE_MASK
 552                 | UVD_CGC_CTRL__UDEC_IT_MODE_MASK
 553                 | UVD_CGC_CTRL__UDEC_DB_MODE_MASK
 554                 | UVD_CGC_CTRL__UDEC_MP_MODE_MASK
 555                 | UVD_CGC_CTRL__SYS_MODE_MASK
 556                 | UVD_CGC_CTRL__UDEC_MODE_MASK
 557                 | UVD_CGC_CTRL__MPEG2_MODE_MASK
 558                 | UVD_CGC_CTRL__REGS_MODE_MASK
 559                 | UVD_CGC_CTRL__RBC_MODE_MASK
 560                 | UVD_CGC_CTRL__LMI_MC_MODE_MASK
 561                 | UVD_CGC_CTRL__LMI_UMC_MODE_MASK
 562                 | UVD_CGC_CTRL__IDCT_MODE_MASK
 563                 | UVD_CGC_CTRL__MPRD_MODE_MASK
 564                 | UVD_CGC_CTRL__MPC_MODE_MASK
 565                 | UVD_CGC_CTRL__LBSI_MODE_MASK
 566                 | UVD_CGC_CTRL__LRBBM_MODE_MASK
 567                 | UVD_CGC_CTRL__WCB_MODE_MASK
 568                 | UVD_CGC_CTRL__VCPU_MODE_MASK
 569                 | UVD_CGC_CTRL__SCPU_MODE_MASK);
 570         WREG32_SOC15(VCN, 0, mmUVD_CGC_CTRL, data);
 571
 572         data = RREG32_SOC15(VCN, 0, mmUVD_SUVD_CGC_CTRL);
 573         data |= (UVD_SUVD_CGC_CTRL__SRE_MODE_MASK
 574                 | UVD_SUVD_CGC_CTRL__SIT_MODE_MASK
 575                 | UVD_SUVD_CGC_CTRL__SMP_MODE_MASK
 576                 | UVD_SUVD_CGC_CTRL__SCM_MODE_MASK
 577                 | UVD_SUVD_CGC_CTRL__SDB_MODE_MASK
 578                 | UVD_SUVD_CGC_CTRL__SCLR_MODE_MASK
 579                 | UVD_SUVD_CGC_CTRL__UVD_SC_MODE_MASK
 580                 | UVD_SUVD_CGC_CTRL__ENT_MODE_MASK
 581                 | UVD_SUVD_CGC_CTRL__IME_MODE_MASK
 582                 | UVD_SUVD_CGC_CTRL__SITE_MODE_MASK);
 583         WREG32_SOC15(VCN, 0, mmUVD_SUVD_CGC_CTRL, data);
 584 }
 585
 586 static void vcn_v1_0_clock_gating_dpg_mode(struct amdgpu_device *adev, uint8_t sram_sel)
 587 {
 588         uint32_t reg_data = 0;
 589
 590         /* disable JPEG CGC */
 591         if (adev->cg_flags & AMD_CG_SUPPORT_VCN_MGCG)
 592                 reg_data = 1 << JPEG_CGC_CTRL__DYN_CLOCK_MODE__SHIFT;
 593         else
 594                 reg_data = 0 << JPEG_CGC_CTRL__DYN_CLOCK_MODE__SHIFT;
 595         reg_data |= 1 << JPEG_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT;
 596         reg_data |= 4 << JPEG_CGC_CTRL__CLK_OFF_DELAY__SHIFT;
 597         WREG32_SOC15_DPG_MODE(UVD, 0, mmJPEG_CGC_CTRL, reg_data, 0xFFFFFFFF, sram_sel);
 598
 599         WREG32_SOC15_DPG_MODE(UVD, 0, mmJPEG_CGC_GATE, 0, 0xFFFFFFFF, sram_sel);
 600
 601         /* enable sw clock gating control */
 602         if (adev->cg_flags & AMD_CG_SUPPORT_VCN_MGCG)
 603                 reg_data = 1 << UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT;
 604         else
 605                 reg_data = 0 << UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT;
 606         reg_data |= 1 << UVD_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT;
 607         reg_data |= 4 << UVD_CGC_CTRL__CLK_OFF_DELAY__SHIFT;
 608         reg_data &= ~(UVD_CGC_CTRL__UDEC_RE_MODE_MASK |
 609                  UVD_CGC_CTRL__UDEC_CM_MODE_MASK |
 610                  UVD_CGC_CTRL__UDEC_IT_MODE_MASK |
 611                  UVD_CGC_CTRL__UDEC_DB_MODE_MASK |
 612                  UVD_CGC_CTRL__UDEC_MP_MODE_MASK |
 613                  UVD_CGC_CTRL__SYS_MODE_MASK |
 614                  UVD_CGC_CTRL__UDEC_MODE_MASK |
 615                  UVD_CGC_CTRL__MPEG2_MODE_MASK |
 616                  UVD_CGC_CTRL__REGS_MODE_MASK |
 617                  UVD_CGC_CTRL__RBC_MODE_MASK |
 618                  UVD_CGC_CTRL__LMI_MC_MODE_MASK |
 619                  UVD_CGC_CTRL__LMI_UMC_MODE_MASK |
 620                  UVD_CGC_CTRL__IDCT_MODE_MASK |
 621                  UVD_CGC_CTRL__MPRD_MODE_MASK |
 622                  UVD_CGC_CTRL__MPC_MODE_MASK |
 623                  UVD_CGC_CTRL__LBSI_MODE_MASK |
 624                  UVD_CGC_CTRL__LRBBM_MODE_MASK |
 625                  UVD_CGC_CTRL__WCB_MODE_MASK |
 626                  UVD_CGC_CTRL__VCPU_MODE_MASK |
 627                  UVD_CGC_CTRL__SCPU_MODE_MASK);
 628         WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_CGC_CTRL, reg_data, 0xFFFFFFFF, sram_sel);
 629
 630         /* turn off clock gating */
 631         WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_CGC_GATE, 0, 0xFFFFFFFF, sram_sel);
 632
 633         /* turn on SUVD clock gating */
 634         WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_SUVD_CGC_GATE, 1, 0xFFFFFFFF, sram_sel);
 635
 636         /* turn on sw mode in UVD_SUVD_CGC_CTRL */
 637         WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_SUVD_CGC_CTRL, 0, 0xFFFFFFFF, sram_sel);
 638 }
 639
 640 static void vcn_1_0_disable_static_power_gating(struct amdgpu_device *adev)
 641 {
 642         uint32_t data = 0;
 643         int ret;
 644
 645         if (adev->pg_flags & AMD_PG_SUPPORT_VCN) {
 646                 data = (1 << UVD_PGFSM_CONFIG__UVDM_PWR_CONFIG__SHIFT
 647                         | 1 << UVD_PGFSM_CONFIG__UVDU_PWR_CONFIG__SHIFT
 648                         | 2 << UVD_PGFSM_CONFIG__UVDF_PWR_CONFIG__SHIFT
 649                         | 2 << UVD_PGFSM_CONFIG__UVDC_PWR_CONFIG__SHIFT
 650                         | 2 << UVD_PGFSM_CONFIG__UVDB_PWR_CONFIG__SHIFT
 651                         | 2 << UVD_PGFSM_CONFIG__UVDIL_PWR_CONFIG__SHIFT
 652                         | 2 << UVD_PGFSM_CONFIG__UVDIR_PWR_CONFIG__SHIFT
 653                         | 2 << UVD_PGFSM_CONFIG__UVDTD_PWR_CONFIG__SHIFT
 654                         | 2 << UVD_PGFSM_CONFIG__UVDTE_PWR_CONFIG__SHIFT
 655                         | 2 << UVD_PGFSM_CONFIG__UVDE_PWR_CONFIG__SHIFT
 656                         | 2 << UVD_PGFSM_CONFIG__UVDW_PWR_CONFIG__SHIFT);
 657
 658                 WREG32_SOC15(VCN, 0, mmUVD_PGFSM_CONFIG, data);
 659                 SOC15_WAIT_ON_RREG(VCN, 0, mmUVD_PGFSM_STATUS, UVD_PGFSM_STATUS__UVDM_UVDU_PWR_ON, 0xFFFFFF, ret);
 660         } else {
 661                 data = (1 << UVD_PGFSM_CONFIG__UVDM_PWR_CONFIG__SHIFT
 662                         | 1 << UVD_PGFSM_CONFIG__UVDU_PWR_CONFIG__SHIFT
 663                         | 1 << UVD_PGFSM_CONFIG__UVDF_PWR_CONFIG__SHIFT
 664                         | 1 << UVD_PGFSM_CONFIG__UVDC_PWR_CONFIG__SHIFT
 665                         | 1 << UVD_PGFSM_CONFIG__UVDB_PWR_CONFIG__SHIFT
 666                         | 1 << UVD_PGFSM_CONFIG__UVDIL_PWR_CONFIG__SHIFT
 667                         | 1 << UVD_PGFSM_CONFIG__UVDIR_PWR_CONFIG__SHIFT
 668                         | 1 << UVD_PGFSM_CONFIG__UVDTD_PWR_CONFIG__SHIFT
 669                         | 1 << UVD_PGFSM_CONFIG__UVDTE_PWR_CONFIG__SHIFT
 670                         | 1 << UVD_PGFSM_CONFIG__UVDE_PWR_CONFIG__SHIFT
 671                         | 1 << UVD_PGFSM_CONFIG__UVDW_PWR_CONFIG__SHIFT);
 672                 WREG32_SOC15(VCN, 0, mmUVD_PGFSM_CONFIG, data);
 673                 SOC15_WAIT_ON_RREG(VCN, 0, mmUVD_PGFSM_STATUS, 0,  0xFFFFFFFF, ret);
 674         }
 675
 676         /* polling UVD_PGFSM_STATUS to confirm UVDM_PWR_STATUS , UVDU_PWR_STATUS are 0 (power on) */
 677
 678         data = RREG32_SOC15(VCN, 0, mmUVD_POWER_STATUS);
 679         data &= ~0x103;
 680         if (adev->pg_flags & AMD_PG_SUPPORT_VCN)
 681                 data |= UVD_PGFSM_CONFIG__UVDM_UVDU_PWR_ON | UVD_POWER_STATUS__UVD_PG_EN_MASK;
 682
 683         WREG32_SOC15(VCN, 0, mmUVD_POWER_STATUS, data);
 684 }
 685
 686 static void vcn_1_0_enable_static_power_gating(struct amdgpu_device *adev)
 687 {
 688         uint32_t data = 0;
 689         int ret;
 690
 691         if (adev->pg_flags & AMD_PG_SUPPORT_VCN) {
 692                 /* Before power off, this indicator has to be turned on */
 693                 data = RREG32_SOC15(VCN, 0, mmUVD_POWER_STATUS);
 694                 data &= ~UVD_POWER_STATUS__UVD_POWER_STATUS_MASK;
 695                 data |= UVD_POWER_STATUS__UVD_POWER_STATUS_TILES_OFF;
 696                 WREG32_SOC15(VCN, 0, mmUVD_POWER_STATUS, data);
 697
 698
 699                 data = (2 << UVD_PGFSM_CONFIG__UVDM_PWR_CONFIG__SHIFT
 700                         | 2 << UVD_PGFSM_CONFIG__UVDU_PWR_CONFIG__SHIFT
 701                         | 2 << UVD_PGFSM_CONFIG__UVDF_PWR_CONFIG__SHIFT
 702                         | 2 << UVD_PGFSM_CONFIG__UVDC_PWR_CONFIG__SHIFT
 703                         | 2 << UVD_PGFSM_CONFIG__UVDB_PWR_CONFIG__SHIFT
 704                         | 2 << UVD_PGFSM_CONFIG__UVDIL_PWR_CONFIG__SHIFT
 705                         | 2 << UVD_PGFSM_CONFIG__UVDIR_PWR_CONFIG__SHIFT
 706                         | 2 << UVD_PGFSM_CONFIG__UVDTD_PWR_CONFIG__SHIFT
 707                         | 2 << UVD_PGFSM_CONFIG__UVDTE_PWR_CONFIG__SHIFT
 708                         | 2 << UVD_PGFSM_CONFIG__UVDE_PWR_CONFIG__SHIFT
 709                         | 2 << UVD_PGFSM_CONFIG__UVDW_PWR_CONFIG__SHIFT);
 710
 711                 WREG32_SOC15(VCN, 0, mmUVD_PGFSM_CONFIG, data);
 712
 713                 data = (2 << UVD_PGFSM_STATUS__UVDM_PWR_STATUS__SHIFT
 714                         | 2 << UVD_PGFSM_STATUS__UVDU_PWR_STATUS__SHIFT
 715                         | 2 << UVD_PGFSM_STATUS__UVDF_PWR_STATUS__SHIFT
 716                         | 2 << UVD_PGFSM_STATUS__UVDC_PWR_STATUS__SHIFT
 717                         | 2 << UVD_PGFSM_STATUS__UVDB_PWR_STATUS__SHIFT
 718                         | 2 << UVD_PGFSM_STATUS__UVDIL_PWR_STATUS__SHIFT
 719                         | 2 << UVD_PGFSM_STATUS__UVDIR_PWR_STATUS__SHIFT
 720                         | 2 << UVD_PGFSM_STATUS__UVDTD_PWR_STATUS__SHIFT
 721                         | 2 << UVD_PGFSM_STATUS__UVDTE_PWR_STATUS__SHIFT
 722                         | 2 << UVD_PGFSM_STATUS__UVDE_PWR_STATUS__SHIFT
 723                         | 2 << UVD_PGFSM_STATUS__UVDW_PWR_STATUS__SHIFT);
 724                 SOC15_WAIT_ON_RREG(VCN, 0, mmUVD_PGFSM_STATUS, data, 0xFFFFFFFF, ret);
 725         }
 726 }
 727
 728 /**
 729  * vcn_v1_0_start - start VCN block
 730  *
 731  * @adev: amdgpu_device pointer
 732  *
 733  * Setup and start the VCN block
 734  */
 735 static int vcn_v1_0_start_spg_mode(struct amdgpu_device *adev)
 736 {
 737         struct amdgpu_ring *ring = &adev->vcn.ring_dec;
 738         uint32_t rb_bufsz, tmp;
 739         uint32_t lmi_swap_cntl;
 740         int i, j, r;
 741
 742         /* disable byte swapping */
 743         lmi_swap_cntl = 0;
 744
 745         vcn_1_0_disable_static_power_gating(adev);
 746         /* disable clock gating */
 747         vcn_v1_0_disable_clock_gating(adev);
 748
 749         vcn_v1_0_mc_resume_spg_mode(adev);
 750
 751         /* disable interupt */
 752         WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_MASTINT_EN), 0,
 753                         ~UVD_MASTINT_EN__VCPU_EN_MASK);
 754
 755         /* stall UMC and register bus before resetting VCPU */
 756         WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_CTRL2),
 757                         UVD_LMI_CTRL2__STALL_ARB_UMC_MASK,
 758                         ~UVD_LMI_CTRL2__STALL_ARB_UMC_MASK);
 759         mdelay(1);
 760
 761         /* put LMI, VCPU, RBC etc... into reset */
 762         WREG32_SOC15(UVD, 0, mmUVD_SOFT_RESET,
 763                 UVD_SOFT_RESET__LMI_SOFT_RESET_MASK |
 764                 UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK |
 765                 UVD_SOFT_RESET__LBSI_SOFT_RESET_MASK |
 766                 UVD_SOFT_RESET__RBC_SOFT_RESET_MASK |
 767                 UVD_SOFT_RESET__CSM_SOFT_RESET_MASK |
 768                 UVD_SOFT_RESET__CXW_SOFT_RESET_MASK |
 769                 UVD_SOFT_RESET__TAP_SOFT_RESET_MASK |
 770                 UVD_SOFT_RESET__LMI_UMC_SOFT_RESET_MASK);
 771         mdelay(5);
 772
 773         /* initialize VCN memory controller */
 774         WREG32_SOC15(UVD, 0, mmUVD_LMI_CTRL,
 775                 (0x40 << UVD_LMI_CTRL__WRITE_CLEAN_TIMER__SHIFT) |
 776                 UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN_MASK |
 777                 UVD_LMI_CTRL__DATA_COHERENCY_EN_MASK |
 778                 UVD_LMI_CTRL__VCPU_DATA_COHERENCY_EN_MASK |
 779                 UVD_LMI_CTRL__REQ_MODE_MASK |
 780                 0x00100000L);
 781
 782 #ifdef __BIG_ENDIAN
 783         /* swap (8 in 32) RB and IB */
 784         lmi_swap_cntl = 0xa;
 785 #endif
 786         WREG32_SOC15(UVD, 0, mmUVD_LMI_SWAP_CNTL, lmi_swap_cntl);
 787
 788         tmp = RREG32_SOC15(UVD, 0, mmUVD_MPC_CNTL);
 789         tmp &= ~UVD_MPC_CNTL__REPLACEMENT_MODE_MASK;
 790         tmp |= 0x2 << UVD_MPC_CNTL__REPLACEMENT_MODE__SHIFT;
 791         WREG32_SOC15(UVD, 0, mmUVD_MPC_CNTL, tmp);
 792
 793         WREG32_SOC15(UVD, 0, mmUVD_MPC_SET_MUXA0,
 794                 ((0x1 << UVD_MPC_SET_MUXA0__VARA_1__SHIFT) |
 795                 (0x2 << UVD_MPC_SET_MUXA0__VARA_2__SHIFT) |
 796                 (0x3 << UVD_MPC_SET_MUXA0__VARA_3__SHIFT) |
 797                 (0x4 << UVD_MPC_SET_MUXA0__VARA_4__SHIFT)));
 798
 799         WREG32_SOC15(UVD, 0, mmUVD_MPC_SET_MUXB0,
 800                 ((0x1 << UVD_MPC_SET_MUXB0__VARB_1__SHIFT) |
 801                 (0x2 << UVD_MPC_SET_MUXB0__VARB_2__SHIFT) |
 802                 (0x3 << UVD_MPC_SET_MUXB0__VARB_3__SHIFT) |
 803                 (0x4 << UVD_MPC_SET_MUXB0__VARB_4__SHIFT)));
 804
 805         WREG32_SOC15(UVD, 0, mmUVD_MPC_SET_MUX,
 806                 ((0x0 << UVD_MPC_SET_MUX__SET_0__SHIFT) |
 807                 (0x1 << UVD_MPC_SET_MUX__SET_1__SHIFT) |
 808                 (0x2 << UVD_MPC_SET_MUX__SET_2__SHIFT)));
 809
 810         /* take all subblocks out of reset, except VCPU */
 811         WREG32_SOC15(UVD, 0, mmUVD_SOFT_RESET,
 812                         UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK);
 813         mdelay(5);
 814
 815         /* enable VCPU clock */
 816         WREG32_SOC15(UVD, 0, mmUVD_VCPU_CNTL,
 817                         UVD_VCPU_CNTL__CLK_EN_MASK);
 818
 819         /* enable UMC */
 820         WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_CTRL2), 0,
 821                         ~UVD_LMI_CTRL2__STALL_ARB_UMC_MASK);
 822
 823         /* boot up the VCPU */
 824         WREG32_SOC15(UVD, 0, mmUVD_SOFT_RESET, 0);
 825         mdelay(10);
 826
 827         for (i = 0; i < 10; ++i) {
 828                 uint32_t status;
 829
 830                 for (j = 0; j < 100; ++j) {
 831                         status = RREG32_SOC15(UVD, 0, mmUVD_STATUS);
 832                         if (status & UVD_STATUS__IDLE)
 833                                 break;
 834                         mdelay(10);
 835                 }
 836                 r = 0;
 837                 if (status & UVD_STATUS__IDLE)
 838                         break;
 839
 840                 DRM_ERROR("VCN decode not responding, trying to reset the VCPU!!!\n");
 841                 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_SOFT_RESET),
 842                                 UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK,
 843                                 ~UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK);
 844                 mdelay(10);
 845                 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_SOFT_RESET), 0,
 846                                 ~UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK);
 847                 mdelay(10);
 848                 r = -1;
 849         }
 850
 851         if (r) {
 852                 DRM_ERROR("VCN decode not responding, giving up!!!\n");
 853                 return r;
 854         }
 855         /* enable master interrupt */
 856         WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_MASTINT_EN),
 857                 (UVD_MASTINT_EN__VCPU_EN_MASK|UVD_MASTINT_EN__SYS_EN_MASK),
 858                 ~(UVD_MASTINT_EN__VCPU_EN_MASK|UVD_MASTINT_EN__SYS_EN_MASK));
 859
 860         /* enable system interrupt for JRBC, TODO: move to set interrupt*/
 861         WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_SYS_INT_EN),
 862                 UVD_SYS_INT_EN__UVD_JRBC_EN_MASK,
 863                 ~UVD_SYS_INT_EN__UVD_JRBC_EN_MASK);
 864
 865         /* clear the bit 4 of VCN_STATUS */
 866         WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_STATUS), 0,
 867                         ~(2 << UVD_STATUS__VCPU_REPORT__SHIFT));
 868
 869         /* force RBC into idle state */
 870         rb_bufsz = order_base_2(ring->ring_size);
 871         tmp = REG_SET_FIELD(0, UVD_RBC_RB_CNTL, RB_BUFSZ, rb_bufsz);
 872         tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_BLKSZ, 1);
 873         tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_FETCH, 1);
 874         tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_WPTR_POLL_EN, 0);
 875         tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_UPDATE, 1);
 876         tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_RPTR_WR_EN, 1);
 877         WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_CNTL, tmp);
 878
 879         /* set the write pointer delay */
 880         WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_WPTR_CNTL, 0);
 881
 882         /* set the wb address */
 883         WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_RPTR_ADDR,
 884                         (upper_32_bits(ring->gpu_addr) >> 2));
 885
 886         /* programm the RB_BASE for ring buffer */
 887         WREG32_SOC15(UVD, 0, mmUVD_LMI_RBC_RB_64BIT_BAR_LOW,
 888                         lower_32_bits(ring->gpu_addr));
 889         WREG32_SOC15(UVD, 0, mmUVD_LMI_RBC_RB_64BIT_BAR_HIGH,
 890                         upper_32_bits(ring->gpu_addr));
 891
 892         /* Initialize the ring buffer's read and write pointers */
 893         WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_RPTR, 0);
 894
 895         WREG32_SOC15(UVD, 0, mmUVD_SCRATCH2, 0);
 896
 897         ring->wptr = RREG32_SOC15(UVD, 0, mmUVD_RBC_RB_RPTR);
 898         WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_WPTR,
 899                         lower_32_bits(ring->wptr));
 900
 901         WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_RBC_RB_CNTL), 0,
 902                         ~UVD_RBC_RB_CNTL__RB_NO_FETCH_MASK);
 903
 904         ring = &adev->vcn.ring_enc[0];
 905         WREG32_SOC15(UVD, 0, mmUVD_RB_RPTR, lower_32_bits(ring->wptr));
 906         WREG32_SOC15(UVD, 0, mmUVD_RB_WPTR, lower_32_bits(ring->wptr));
 907         WREG32_SOC15(UVD, 0, mmUVD_RB_BASE_LO, ring->gpu_addr);
 908         WREG32_SOC15(UVD, 0, mmUVD_RB_BASE_HI, upper_32_bits(ring->gpu_addr));
 909         WREG32_SOC15(UVD, 0, mmUVD_RB_SIZE, ring->ring_size / 4);
 910
 911         ring = &adev->vcn.ring_enc[1];
 912         WREG32_SOC15(UVD, 0, mmUVD_RB_RPTR2, lower_32_bits(ring->wptr));
 913         WREG32_SOC15(UVD, 0, mmUVD_RB_WPTR2, lower_32_bits(ring->wptr));
 914         WREG32_SOC15(UVD, 0, mmUVD_RB_BASE_LO2, ring->gpu_addr);
 915         WREG32_SOC15(UVD, 0, mmUVD_RB_BASE_HI2, upper_32_bits(ring->gpu_addr));
 916         WREG32_SOC15(UVD, 0, mmUVD_RB_SIZE2, ring->ring_size / 4);
 917
 918         ring = &adev->vcn.ring_jpeg;
 919         WREG32_SOC15(UVD, 0, mmUVD_LMI_JRBC_RB_VMID, 0);
 920         WREG32_SOC15(UVD, 0, mmUVD_JRBC_RB_CNTL, UVD_JRBC_RB_CNTL__RB_NO_FETCH_MASK |
 921                         UVD_JRBC_RB_CNTL__RB_RPTR_WR_EN_MASK);
 922         WREG32_SOC15(UVD, 0, mmUVD_LMI_JRBC_RB_64BIT_BAR_LOW, lower_32_bits(ring->gpu_addr));
 923         WREG32_SOC15(UVD, 0, mmUVD_LMI_JRBC_RB_64BIT_BAR_HIGH, upper_32_bits(ring->gpu_addr));
 924         WREG32_SOC15(UVD, 0, mmUVD_JRBC_RB_RPTR, 0);
 925         WREG32_SOC15(UVD, 0, mmUVD_JRBC_RB_WPTR, 0);
 926         WREG32_SOC15(UVD, 0, mmUVD_JRBC_RB_CNTL, UVD_JRBC_RB_CNTL__RB_RPTR_WR_EN_MASK);
 927
 928         /* initialize wptr */
 929         ring->wptr = RREG32_SOC15(UVD, 0, mmUVD_JRBC_RB_WPTR);
 930
 931         /* copy patch commands to the jpeg ring */
 932         vcn_v1_0_jpeg_ring_set_patch_ring(ring,
 933                 (ring->wptr + ring->max_dw * amdgpu_sched_hw_submission));
 934
 935         return 0;
 936 }
 937
 938 static int vcn_v1_0_start_dpg_mode(struct amdgpu_device *adev)
 939 {
 940         struct amdgpu_ring *ring = &adev->vcn.ring_dec;
 941         uint32_t rb_bufsz, tmp, reg_data;
 942         uint32_t lmi_swap_cntl;
 943
 944         /* disable byte swapping */
 945         lmi_swap_cntl = 0;
 946
 947         vcn_1_0_enable_static_power_gating(adev);
 948
 949         /* enable dynamic power gating mode */
 950         reg_data = RREG32_SOC15(UVD, 0, mmUVD_POWER_STATUS);
 951         reg_data |= UVD_POWER_STATUS__UVD_PG_MODE_MASK;
 952         reg_data |= UVD_POWER_STATUS__UVD_PG_EN_MASK;
 953         WREG32_SOC15(UVD, 0, mmUVD_POWER_STATUS, reg_data);
 954
 955         /* enable clock gating */
 956         vcn_v1_0_clock_gating_dpg_mode(adev, 0);
 957
 958         /* enable VCPU clock */
 959         reg_data = (0xFF << UVD_VCPU_CNTL__PRB_TIMEOUT_VAL__SHIFT);
 960         reg_data |= UVD_VCPU_CNTL__CLK_EN_MASK;
 961         reg_data |= UVD_VCPU_CNTL__MIF_WR_LOW_THRESHOLD_BP_MASK;
 962         WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_VCPU_CNTL, reg_data, 0xFFFFFFFF, 0);
 963
 964         /* disable interupt */
 965         WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_MASTINT_EN,
 966                         0, UVD_MASTINT_EN__VCPU_EN_MASK, 0);
 967
 968         /* stall UMC and register bus before resetting VCPU */
 969         WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_LMI_CTRL2,
 970                         UVD_LMI_CTRL2__STALL_ARB_UMC_MASK, UVD_LMI_CTRL2__STALL_ARB_UMC_MASK, 0);
 971
 972         /* put LMI, VCPU, RBC etc... into reset */
 973         WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_SOFT_RESET,
 974                 UVD_SOFT_RESET__LMI_SOFT_RESET_MASK |
 975                 UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK |
 976                 UVD_SOFT_RESET__LBSI_SOFT_RESET_MASK |
 977                 UVD_SOFT_RESET__RBC_SOFT_RESET_MASK |
 978                 UVD_SOFT_RESET__CSM_SOFT_RESET_MASK |
 979                 UVD_SOFT_RESET__CXW_SOFT_RESET_MASK |
 980                 UVD_SOFT_RESET__TAP_SOFT_RESET_MASK |
 981                 UVD_SOFT_RESET__LMI_UMC_SOFT_RESET_MASK,
 982                 0xFFFFFFFF, 0);
 983
 984         /* initialize VCN memory controller */
 985         WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_LMI_CTRL,
 986                 (0x40 << UVD_LMI_CTRL__WRITE_CLEAN_TIMER__SHIFT) |
 987                 UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN_MASK |
 988                 UVD_LMI_CTRL__DATA_COHERENCY_EN_MASK |
 989                 UVD_LMI_CTRL__VCPU_DATA_COHERENCY_EN_MASK |
 990                 UVD_LMI_CTRL__REQ_MODE_MASK |
 991                 0x00100000L, 0xFFFFFFFF, 0);
 992
 993 #ifdef __BIG_ENDIAN
 994         /* swap (8 in 32) RB and IB */
 995         lmi_swap_cntl = 0xa;
 996 #endif
 997         WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_LMI_SWAP_CNTL, lmi_swap_cntl, 0xFFFFFFFF, 0);
 998
 999         WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_MPC_CNTL,
1000                 0x2 << UVD_MPC_CNTL__REPLACEMENT_MODE__SHIFT, 0xFFFFFFFF, 0);
1001
1002         WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_MPC_SET_MUXA0,
1003                 ((0x1 << UVD_MPC_SET_MUXA0__VARA_1__SHIFT) |
1004                  (0x2 << UVD_MPC_SET_MUXA0__VARA_2__SHIFT) |
1005                  (0x3 << UVD_MPC_SET_MUXA0__VARA_3__SHIFT) |
1006                  (0x4 << UVD_MPC_SET_MUXA0__VARA_4__SHIFT)), 0xFFFFFFFF, 0);
1007
1008         WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_MPC_SET_MUXB0,
1009                 ((0x1 << UVD_MPC_SET_MUXB0__VARB_1__SHIFT) |
1010                  (0x2 << UVD_MPC_SET_MUXB0__VARB_2__SHIFT) |
1011                  (0x3 << UVD_MPC_SET_MUXB0__VARB_3__SHIFT) |
1012                  (0x4 << UVD_MPC_SET_MUXB0__VARB_4__SHIFT)), 0xFFFFFFFF, 0);
1013
1014         WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_MPC_SET_MUX,
1015                 ((0x0 << UVD_MPC_SET_MUX__SET_0__SHIFT) |
1016                  (0x1 << UVD_MPC_SET_MUX__SET_1__SHIFT) |
1017                  (0x2 << UVD_MPC_SET_MUX__SET_2__SHIFT)), 0xFFFFFFFF, 0);
1018
1019         vcn_v1_0_mc_resume_dpg_mode(adev);
1020
1021         /* take all subblocks out of reset, except VCPU */
1022         WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_SOFT_RESET,
1023                         UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK, 0xFFFFFFFF, 0);
1024
1025         /* enable VCPU clock */
1026         WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_VCPU_CNTL,
1027                         UVD_VCPU_CNTL__CLK_EN_MASK, 0xFFFFFFFF, 0);
1028
1029         /* enable UMC */
1030         WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_LMI_CTRL2,
1031                         0, UVD_LMI_CTRL2__STALL_ARB_UMC_MASK, 0);
1032
1033         /* boot up the VCPU */
1034         WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_SOFT_RESET, 0, 0xFFFFFFFF, 0);
1035
1036         /* enable master interrupt */
1037         WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_MASTINT_EN,
1038                         (UVD_MASTINT_EN__VCPU_EN_MASK|UVD_MASTINT_EN__SYS_EN_MASK),
1039                         (UVD_MASTINT_EN__VCPU_EN_MASK|UVD_MASTINT_EN__SYS_EN_MASK), 0);
1040
1041         vcn_v1_0_clock_gating_dpg_mode(adev, 1);
1042         /* setup mmUVD_LMI_CTRL */
1043         WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_LMI_CTRL,
1044                         (UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN_MASK |
1045                                 UVD_LMI_CTRL__CRC_RESET_MASK |
1046                                 UVD_LMI_CTRL__MASK_MC_URGENT_MASK |
1047                                 UVD_LMI_CTRL__DATA_COHERENCY_EN_MASK |
1048                                 UVD_LMI_CTRL__VCPU_DATA_COHERENCY_EN_MASK |
1049                                 (8 << UVD_LMI_CTRL__WRITE_CLEAN_TIMER__SHIFT) |
1050                                 0x00100000L), 0xFFFFFFFF, 1);
1051
1052         tmp = adev->gfx.config.gb_addr_config;
1053         /* setup VCN global tiling registers */
1054         WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_JPEG_ADDR_CONFIG, tmp, 0xFFFFFFFF, 1);
1055         WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_JPEG_UV_ADDR_CONFIG, tmp, 0xFFFFFFFF, 1);
1056
1057         /* enable System Interrupt for JRBC */
1058         WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_SYS_INT_EN,
1059                                                                         UVD_SYS_INT_EN__UVD_JRBC_EN_MASK, 0xFFFFFFFF, 1);
1060
1061         /* force RBC into idle state */
1062         rb_bufsz = order_base_2(ring->ring_size);
1063         tmp = REG_SET_FIELD(0, UVD_RBC_RB_CNTL, RB_BUFSZ, rb_bufsz);
1064         tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_BLKSZ, 1);
1065         tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_FETCH, 1);
1066         tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_WPTR_POLL_EN, 0);
1067         tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_UPDATE, 1);
1068         tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_RPTR_WR_EN, 1);
1069         WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_CNTL, tmp);
1070
1071         /* set the write pointer delay */
1072         WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_WPTR_CNTL, 0);
1073
1074         /* set the wb address */
1075         WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_RPTR_ADDR,
1076                                                                 (upper_32_bits(ring->gpu_addr) >> 2));
1077
1078         /* programm the RB_BASE for ring buffer */
1079         WREG32_SOC15(UVD, 0, mmUVD_LMI_RBC_RB_64BIT_BAR_LOW,
1080                                                                 lower_32_bits(ring->gpu_addr));
1081         WREG32_SOC15(UVD, 0, mmUVD_LMI_RBC_RB_64BIT_BAR_HIGH,
1082                                                                 upper_32_bits(ring->gpu_addr));
1083
1084         /* Initialize the ring buffer's read and write pointers */
1085         WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_RPTR, 0);
1086
1087         WREG32_SOC15(UVD, 0, mmUVD_SCRATCH2, 0);
1088
1089         ring->wptr = RREG32_SOC15(UVD, 0, mmUVD_RBC_RB_RPTR);
1090         WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_WPTR,
1091                                                                 lower_32_bits(ring->wptr));
1092
1093         WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_RBC_RB_CNTL), 0,
1094                         ~UVD_RBC_RB_CNTL__RB_NO_FETCH_MASK);
1095
1096         /* initialize wptr */
1097         ring->wptr = RREG32_SOC15(UVD, 0, mmUVD_JRBC_RB_WPTR);
1098
1099         /* copy patch commands to the jpeg ring */
1100         vcn_v1_0_jpeg_ring_set_patch_ring(ring,
1101                 (ring->wptr + ring->max_dw * amdgpu_sched_hw_submission));
1102
1103         return 0;
1104 }
1105
1106 static int vcn_v1_0_start(struct amdgpu_device *adev)
1107 {
1108         int r;
1109
1110         if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG)
1111                 r = vcn_v1_0_start_dpg_mode(adev);
1112         else
1113                 r = vcn_v1_0_start_spg_mode(adev);
1114         return r;
1115 }
1116
1117 /**
1118  * vcn_v1_0_stop - stop VCN block
1119  *
1120  * @adev: amdgpu_device pointer
1121  *
1122  * stop the VCN block
1123  */
1124 static int vcn_v1_0_stop_spg_mode(struct amdgpu_device *adev)
1125 {
1126         /* force RBC into idle state */
1127         WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_CNTL, 0x11010101);
1128
1129         /* Stall UMC and register bus before resetting VCPU */
1130         WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_CTRL2),
1131                         UVD_LMI_CTRL2__STALL_ARB_UMC_MASK,
1132                         ~UVD_LMI_CTRL2__STALL_ARB_UMC_MASK);
1133         mdelay(1);
1134
1135         /* put VCPU into reset */
1136         WREG32_SOC15(UVD, 0, mmUVD_SOFT_RESET,
1137                         UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK);
1138         mdelay(5);
1139
1140         /* disable VCPU clock */
1141         WREG32_SOC15(UVD, 0, mmUVD_VCPU_CNTL, 0x0);
1142
1143         /* Unstall UMC and register bus */
1144         WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_CTRL2), 0,
1145                         ~UVD_LMI_CTRL2__STALL_ARB_UMC_MASK);
1146
1147         WREG32_SOC15(VCN, 0, mmUVD_STATUS, 0);
1148
1149         vcn_v1_0_enable_clock_gating(adev);
1150         vcn_1_0_enable_static_power_gating(adev);
1151         return 0;
1152 }
1153
1154 static int vcn_v1_0_stop_dpg_mode(struct amdgpu_device *adev)
1155 {
1156         int ret_code;
1157
1158         /* Wait for power status to be UVD_POWER_STATUS__UVD_POWER_STATUS_TILES_OFF */
1159         SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_POWER_STATUS,
1160                         UVD_POWER_STATUS__UVD_POWER_STATUS_TILES_OFF,
1161                         UVD_POWER_STATUS__UVD_POWER_STATUS_MASK, ret_code);
1162
1163         /* disable dynamic power gating mode */
1164         WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_POWER_STATUS), 0,
1165                         ~UVD_POWER_STATUS__UVD_PG_MODE_MASK);
1166
1167         return 0;
1168 }
1169
1170 static int vcn_v1_0_stop(struct amdgpu_device *adev)
1171 {
1172         int r;
1173
1174         if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG)
1175                 r = vcn_v1_0_stop_dpg_mode(adev);
1176         else
1177                 r = vcn_v1_0_stop_spg_mode(adev);
1178
1179         return r;
1180 }
1181
1182 static bool vcn_v1_0_is_idle(void *handle)
1183 {
1184         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1185
1186         return (RREG32_SOC15(VCN, 0, mmUVD_STATUS) == UVD_STATUS__IDLE);
1187 }
1188
1189 static int vcn_v1_0_wait_for_idle(void *handle)
1190 {
1191         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1192         int ret = 0;
1193
1194         SOC15_WAIT_ON_RREG(VCN, 0, mmUVD_STATUS, UVD_STATUS__IDLE,
1195                 UVD_STATUS__IDLE, ret);
1196
1197         return ret;
1198 }
1199
1200 static int vcn_v1_0_set_clockgating_state(void *handle,
1201                                           enum amd_clockgating_state state)
1202 {
1203         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1204         bool enable = (state == AMD_CG_STATE_GATE) ? true : false;
1205
1206         if (enable) {
1207                 /* wait for STATUS to clear */
1208                 if (vcn_v1_0_is_idle(handle))
1209                         return -EBUSY;
1210                 vcn_v1_0_enable_clock_gating(adev);
1211         } else {
1212                 /* disable HW gating and enable Sw gating */
1213                 vcn_v1_0_disable_clock_gating(adev);
1214         }
1215         return 0;
1216 }
1217
1218 /**
1219  * vcn_v1_0_dec_ring_get_rptr - get read pointer
1220  *
1221  * @ring: amdgpu_ring pointer
1222  *
1223  * Returns the current hardware read pointer
1224  */
1225 static uint64_t vcn_v1_0_dec_ring_get_rptr(struct amdgpu_ring *ring)
1226 {
1227         struct amdgpu_device *adev = ring->adev;
1228
1229         return RREG32_SOC15(UVD, 0, mmUVD_RBC_RB_RPTR);
1230 }
1231
1232 /**
1233  * vcn_v1_0_dec_ring_get_wptr - get write pointer
1234  *
1235  * @ring: amdgpu_ring pointer
1236  *
1237  * Returns the current hardware write pointer
1238  */
1239 static uint64_t vcn_v1_0_dec_ring_get_wptr(struct amdgpu_ring *ring)
1240 {
1241         struct amdgpu_device *adev = ring->adev;
1242
1243         return RREG32_SOC15(UVD, 0, mmUVD_RBC_RB_WPTR);
1244 }
1245
1246 /**
1247  * vcn_v1_0_dec_ring_set_wptr - set write pointer
1248  *
1249  * @ring: amdgpu_ring pointer
1250  *
1251  * Commits the write pointer to the hardware
1252  */
1253 static void vcn_v1_0_dec_ring_set_wptr(struct amdgpu_ring *ring)
1254 {
1255         struct amdgpu_device *adev = ring->adev;
1256
1257         if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG)
1258                 WREG32_SOC15(UVD, 0, mmUVD_SCRATCH2,
1259                         lower_32_bits(ring->wptr) | 0x80000000);
1260
1261         WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_WPTR, lower_32_bits(ring->wptr));
1262 }
1263
1264 /**
1265  * vcn_v1_0_dec_ring_insert_start - insert a start command
1266  *
1267  * @ring: amdgpu_ring pointer
1268  *
1269  * Write a start command to the ring.
1270  */
1271 static void vcn_v1_0_dec_ring_insert_start(struct amdgpu_ring *ring)
1272 {
1273         struct amdgpu_device *adev = ring->adev;
1274
1275         amdgpu_ring_write(ring,
1276                 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_DATA0), 0));
1277         amdgpu_ring_write(ring, 0);
1278         amdgpu_ring_write(ring,
1279                 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_CMD), 0));
1280         amdgpu_ring_write(ring, VCN_DEC_CMD_PACKET_START << 1);
1281 }
1282
1283 /**
1284  * vcn_v1_0_dec_ring_insert_end - insert a end command
1285  *
1286  * @ring: amdgpu_ring pointer
1287  *
1288  * Write a end command to the ring.
1289  */
1290 static void vcn_v1_0_dec_ring_insert_end(struct amdgpu_ring *ring)
1291 {
1292         struct amdgpu_device *adev = ring->adev;
1293
1294         amdgpu_ring_write(ring,
1295                 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_CMD), 0));
1296         amdgpu_ring_write(ring, VCN_DEC_CMD_PACKET_END << 1);
1297 }
1298
1299 /**
1300  * vcn_v1_0_dec_ring_emit_fence - emit an fence & trap command
1301  *
1302  * @ring: amdgpu_ring pointer
1303  * @fence: fence to emit
1304  *
1305  * Write a fence and a trap command to the ring.
1306  */
1307 static void vcn_v1_0_dec_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 seq,
1308                                      unsigned flags)
1309 {
1310         struct amdgpu_device *adev = ring->adev;
1311
1312         WARN_ON(flags & AMDGPU_FENCE_FLAG_64BIT);
1313
1314         amdgpu_ring_write(ring,
1315                 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_CONTEXT_ID), 0));
1316         amdgpu_ring_write(ring, seq);
1317         amdgpu_ring_write(ring,
1318                 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_DATA0), 0));
1319         amdgpu_ring_write(ring, addr & 0xffffffff);
1320         amdgpu_ring_write(ring,
1321                 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_DATA1), 0));
1322         amdgpu_ring_write(ring, upper_32_bits(addr) & 0xff);
1323         amdgpu_ring_write(ring,
1324                 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_CMD), 0));
1325         amdgpu_ring_write(ring, VCN_DEC_CMD_FENCE << 1);
1326
1327         amdgpu_ring_write(ring,
1328                 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_DATA0), 0));
1329         amdgpu_ring_write(ring, 0);
1330         amdgpu_ring_write(ring,
1331                 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_DATA1), 0));
1332         amdgpu_ring_write(ring, 0);
1333         amdgpu_ring_write(ring,
1334                 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_CMD), 0));
1335         amdgpu_ring_write(ring, VCN_DEC_CMD_TRAP << 1);
1336 }
1337
1338 /**
1339  * vcn_v1_0_dec_ring_emit_ib - execute indirect buffer
1340  *
1341  * @ring: amdgpu_ring pointer
1342  * @ib: indirect buffer to execute
1343  *
1344  * Write ring commands to execute the indirect buffer
1345  */
1346 static void vcn_v1_0_dec_ring_emit_ib(struct amdgpu_ring *ring,
1347                                   struct amdgpu_ib *ib,
1348                                   unsigned vmid, bool ctx_switch)
1349 {
1350         struct amdgpu_device *adev = ring->adev;
1351
1352         amdgpu_ring_write(ring,
1353                 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_RBC_IB_VMID), 0));
1354         amdgpu_ring_write(ring, vmid);
1355
1356         amdgpu_ring_write(ring,
1357                 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_RBC_IB_64BIT_BAR_LOW), 0));
1358         amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr));
1359         amdgpu_ring_write(ring,
1360                 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_RBC_IB_64BIT_BAR_HIGH), 0));
1361         amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr));
1362         amdgpu_ring_write(ring,
1363                 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_RBC_IB_SIZE), 0));
1364         amdgpu_ring_write(ring, ib->length_dw);
1365 }
1366
1367 static void vcn_v1_0_dec_ring_emit_reg_wait(struct amdgpu_ring *ring,
1368                                             uint32_t reg, uint32_t val,
1369                                             uint32_t mask)
1370 {
1371         struct amdgpu_device *adev = ring->adev;
1372
1373         amdgpu_ring_write(ring,
1374                 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_DATA0), 0));
1375         amdgpu_ring_write(ring, reg << 2);
1376         amdgpu_ring_write(ring,
1377                 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_DATA1), 0));
1378         amdgpu_ring_write(ring, val);
1379         amdgpu_ring_write(ring,
1380                 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GP_SCRATCH8), 0));
1381         amdgpu_ring_write(ring, mask);
1382         amdgpu_ring_write(ring,
1383                 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_CMD), 0));
1384         amdgpu_ring_write(ring, VCN_DEC_CMD_REG_READ_COND_WAIT << 1);
1385 }
1386
1387 static void vcn_v1_0_dec_ring_emit_vm_flush(struct amdgpu_ring *ring,
1388                                             unsigned vmid, uint64_t pd_addr)
1389 {
1390         struct amdgpu_vmhub *hub = &ring->adev->vmhub[ring->funcs->vmhub];
1391         uint32_t data0, data1, mask;
1392
1393         pd_addr = amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr);
1394
1395         /* wait for register write */
1396         data0 = hub->ctx0_ptb_addr_lo32 + vmid * 2;
1397         data1 = lower_32_bits(pd_addr);
1398         mask = 0xffffffff;
1399         vcn_v1_0_dec_ring_emit_reg_wait(ring, data0, data1, mask);
1400 }
1401
1402 static void vcn_v1_0_dec_ring_emit_wreg(struct amdgpu_ring *ring,
1403                                         uint32_t reg, uint32_t val)
1404 {
1405         struct amdgpu_device *adev = ring->adev;
1406
1407         amdgpu_ring_write(ring,
1408                 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_DATA0), 0));
1409         amdgpu_ring_write(ring, reg << 2);
1410         amdgpu_ring_write(ring,
1411                 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_DATA1), 0));
1412         amdgpu_ring_write(ring, val);
1413         amdgpu_ring_write(ring,
1414                 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_CMD), 0));
1415         amdgpu_ring_write(ring, VCN_DEC_CMD_WRITE_REG << 1);
1416 }
1417
1418 /**
1419  * vcn_v1_0_enc_ring_get_rptr - get enc read pointer
1420  *
1421  * @ring: amdgpu_ring pointer
1422  *
1423  * Returns the current hardware enc read pointer
1424  */
1425 static uint64_t vcn_v1_0_enc_ring_get_rptr(struct amdgpu_ring *ring)
1426 {
1427         struct amdgpu_device *adev = ring->adev;
1428
1429         if (ring == &adev->vcn.ring_enc[0])
1430                 return RREG32_SOC15(UVD, 0, mmUVD_RB_RPTR);
1431         else
1432                 return RREG32_SOC15(UVD, 0, mmUVD_RB_RPTR2);
1433 }
1434
1435  /**
1436  * vcn_v1_0_enc_ring_get_wptr - get enc write pointer
1437  *
1438  * @ring: amdgpu_ring pointer
1439  *
1440  * Returns the current hardware enc write pointer
1441  */
1442 static uint64_t vcn_v1_0_enc_ring_get_wptr(struct amdgpu_ring *ring)
1443 {
1444         struct amdgpu_device *adev = ring->adev;
1445
1446         if (ring == &adev->vcn.ring_enc[0])
1447                 return RREG32_SOC15(UVD, 0, mmUVD_RB_WPTR);
1448         else
1449                 return RREG32_SOC15(UVD, 0, mmUVD_RB_WPTR2);
1450 }
1451
1452  /**
1453  * vcn_v1_0_enc_ring_set_wptr - set enc write pointer
1454  *
1455  * @ring: amdgpu_ring pointer
1456  *
1457  * Commits the enc write pointer to the hardware
1458  */
1459 static void vcn_v1_0_enc_ring_set_wptr(struct amdgpu_ring *ring)
1460 {
1461         struct amdgpu_device *adev = ring->adev;
1462
1463         if (ring == &adev->vcn.ring_enc[0])
1464                 WREG32_SOC15(UVD, 0, mmUVD_RB_WPTR,
1465                         lower_32_bits(ring->wptr));
1466         else
1467                 WREG32_SOC15(UVD, 0, mmUVD_RB_WPTR2,
1468                         lower_32_bits(ring->wptr));
1469 }
1470
1471 /**
1472  * vcn_v1_0_enc_ring_emit_fence - emit an enc fence & trap command
1473  *
1474  * @ring: amdgpu_ring pointer
1475  * @fence: fence to emit
1476  *
1477  * Write enc a fence and a trap command to the ring.
1478  */
1479 static void vcn_v1_0_enc_ring_emit_fence(struct amdgpu_ring *ring, u64 addr,
1480                         u64 seq, unsigned flags)
1481 {
1482         WARN_ON(flags & AMDGPU_FENCE_FLAG_64BIT);
1483
1484         amdgpu_ring_write(ring, VCN_ENC_CMD_FENCE);
1485         amdgpu_ring_write(ring, addr);
1486         amdgpu_ring_write(ring, upper_32_bits(addr));
1487         amdgpu_ring_write(ring, seq);
1488         amdgpu_ring_write(ring, VCN_ENC_CMD_TRAP);
1489 }
1490
1491 static void vcn_v1_0_enc_ring_insert_end(struct amdgpu_ring *ring)
1492 {
1493         amdgpu_ring_write(ring, VCN_ENC_CMD_END);
1494 }
1495
1496 /**
1497  * vcn_v1_0_enc_ring_emit_ib - enc execute indirect buffer
1498  *
1499  * @ring: amdgpu_ring pointer
1500  * @ib: indirect buffer to execute
1501  *
1502  * Write enc ring commands to execute the indirect buffer
1503  */
1504 static void vcn_v1_0_enc_ring_emit_ib(struct amdgpu_ring *ring,
1505                 struct amdgpu_ib *ib, unsigned int vmid, bool ctx_switch)
1506 {
1507         amdgpu_ring_write(ring, VCN_ENC_CMD_IB);
1508         amdgpu_ring_write(ring, vmid);
1509         amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr));
1510         amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr));
1511         amdgpu_ring_write(ring, ib->length_dw);
1512 }
1513
1514 static void vcn_v1_0_enc_ring_emit_reg_wait(struct amdgpu_ring *ring,
1515                                             uint32_t reg, uint32_t val,
1516                                             uint32_t mask)
1517 {
1518         amdgpu_ring_write(ring, VCN_ENC_CMD_REG_WAIT);
1519         amdgpu_ring_write(ring, reg << 2);
1520         amdgpu_ring_write(ring, mask);
1521         amdgpu_ring_write(ring, val);
1522 }
1523
1524 static void vcn_v1_0_enc_ring_emit_vm_flush(struct amdgpu_ring *ring,
1525                                             unsigned int vmid, uint64_t pd_addr)
1526 {
1527         struct amdgpu_vmhub *hub = &ring->adev->vmhub[ring->funcs->vmhub];
1528
1529         pd_addr = amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr);
1530
1531         /* wait for reg writes */
1532         vcn_v1_0_enc_ring_emit_reg_wait(ring, hub->ctx0_ptb_addr_lo32 + vmid * 2,
1533                                         lower_32_bits(pd_addr), 0xffffffff);
1534 }
1535
1536 static void vcn_v1_0_enc_ring_emit_wreg(struct amdgpu_ring *ring,
1537                                         uint32_t reg, uint32_t val)
1538 {
1539         amdgpu_ring_write(ring, VCN_ENC_CMD_REG_WRITE);
1540         amdgpu_ring_write(ring, reg << 2);
1541         amdgpu_ring_write(ring, val);
1542 }
1543
1544
1545 /**
1546  * vcn_v1_0_jpeg_ring_get_rptr - get read pointer
1547  *
1548  * @ring: amdgpu_ring pointer
1549  *
1550  * Returns the current hardware read pointer
1551  */
1552 static uint64_t vcn_v1_0_jpeg_ring_get_rptr(struct amdgpu_ring *ring)
1553 {
1554         struct amdgpu_device *adev = ring->adev;
1555
1556         return RREG32_SOC15(UVD, 0, mmUVD_JRBC_RB_RPTR);
1557 }
1558
1559 /**
1560  * vcn_v1_0_jpeg_ring_get_wptr - get write pointer
1561  *
1562  * @ring: amdgpu_ring pointer
1563  *
1564  * Returns the current hardware write pointer
1565  */
1566 static uint64_t vcn_v1_0_jpeg_ring_get_wptr(struct amdgpu_ring *ring)
1567 {
1568         struct amdgpu_device *adev = ring->adev;
1569
1570         return RREG32_SOC15(UVD, 0, mmUVD_JRBC_RB_WPTR);
1571 }
1572
1573 /**
1574  * vcn_v1_0_jpeg_ring_set_wptr - set write pointer
1575  *
1576  * @ring: amdgpu_ring pointer
1577  *
1578  * Commits the write pointer to the hardware
1579  */
1580 static void vcn_v1_0_jpeg_ring_set_wptr(struct amdgpu_ring *ring)
1581 {
1582         struct amdgpu_device *adev = ring->adev;
1583
1584         WREG32_SOC15(UVD, 0, mmUVD_JRBC_RB_WPTR, lower_32_bits(ring->wptr));
1585 }
1586
1587 /**
1588  * vcn_v1_0_jpeg_ring_insert_start - insert a start command
1589  *
1590  * @ring: amdgpu_ring pointer
1591  *
1592  * Write a start command to the ring.
1593  */
1594 static void vcn_v1_0_jpeg_ring_insert_start(struct amdgpu_ring *ring)
1595 {
1596         struct amdgpu_device *adev = ring->adev;
1597
1598         amdgpu_ring_write(ring,
1599                 PACKETJ(SOC15_REG_OFFSET(UVD, 0, mmUVD_JRBC_EXTERNAL_REG_BASE), 0, 0, PACKETJ_TYPE0));
1600         amdgpu_ring_write(ring, 0x68e04);
1601
1602         amdgpu_ring_write(ring, PACKETJ(0, 0, 0, PACKETJ_TYPE0));
1603         amdgpu_ring_write(ring, 0x80010000);
1604 }
1605
1606 /**
1607  * vcn_v1_0_jpeg_ring_insert_end - insert a end command
1608  *
1609  * @ring: amdgpu_ring pointer
1610  *
1611  * Write a end command to the ring.
1612  */
1613 static void vcn_v1_0_jpeg_ring_insert_end(struct amdgpu_ring *ring)
1614 {
1615         struct amdgpu_device *adev = ring->adev;
1616
1617         amdgpu_ring_write(ring,
1618                 PACKETJ(SOC15_REG_OFFSET(UVD, 0, mmUVD_JRBC_EXTERNAL_REG_BASE), 0, 0, PACKETJ_TYPE0));
1619         amdgpu_ring_write(ring, 0x68e04);
1620
1621         amdgpu_ring_write(ring, PACKETJ(0, 0, 0, PACKETJ_TYPE0));
1622         amdgpu_ring_write(ring, 0x00010000);
1623 }
1624
1625 /**
1626  * vcn_v1_0_jpeg_ring_emit_fence - emit an fence & trap command
1627  *
1628  * @ring: amdgpu_ring pointer
1629  * @fence: fence to emit
1630  *
1631  * Write a fence and a trap command to the ring.
1632  */
1633 static void vcn_v1_0_jpeg_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 seq,
1634                                      unsigned flags)
1635 {
1636         struct amdgpu_device *adev = ring->adev;
1637
1638         WARN_ON(flags & AMDGPU_FENCE_FLAG_64BIT);
1639
1640         amdgpu_ring_write(ring,
1641                 PACKETJ(SOC15_REG_OFFSET(UVD, 0, mmUVD_JPEG_GPCOM_DATA0), 0, 0, PACKETJ_TYPE0));
1642         amdgpu_ring_write(ring, seq);
1643
1644         amdgpu_ring_write(ring,
1645                 PACKETJ(SOC15_REG_OFFSET(UVD, 0, mmUVD_JPEG_GPCOM_DATA1), 0, 0, PACKETJ_TYPE0));
1646         amdgpu_ring_write(ring, seq);
1647
1648         amdgpu_ring_write(ring,
1649                 PACKETJ(SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_JRBC_RB_MEM_WR_64BIT_BAR_LOW), 0, 0, PACKETJ_TYPE0));
1650         amdgpu_ring_write(ring, lower_32_bits(addr));
1651
1652         amdgpu_ring_write(ring,
1653                 PACKETJ(SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_JRBC_RB_MEM_WR_64BIT_BAR_HIGH), 0, 0, PACKETJ_TYPE0));
1654         amdgpu_ring_write(ring, upper_32_bits(addr));
1655
1656         amdgpu_ring_write(ring,
1657                 PACKETJ(SOC15_REG_OFFSET(UVD, 0, mmUVD_JPEG_GPCOM_CMD), 0, 0, PACKETJ_TYPE0));
1658         amdgpu_ring_write(ring, 0x8);
1659
1660         amdgpu_ring_write(ring,
1661                 PACKETJ(SOC15_REG_OFFSET(UVD, 0, mmUVD_JPEG_GPCOM_CMD), 0, PACKETJ_CONDITION_CHECK0, PACKETJ_TYPE4));
1662         amdgpu_ring_write(ring, 0);
1663
1664         amdgpu_ring_write(ring,
1665                 PACKETJ(SOC15_REG_OFFSET(UVD, 0, mmUVD_JRBC_RB_COND_RD_TIMER), 0, 0, PACKETJ_TYPE0));
1666         amdgpu_ring_write(ring, 0x01400200);
1667
1668         amdgpu_ring_write(ring,
1669                 PACKETJ(SOC15_REG_OFFSET(UVD, 0, mmUVD_JRBC_RB_REF_DATA), 0, 0, PACKETJ_TYPE0));
1670         amdgpu_ring_write(ring, seq);
1671
1672         amdgpu_ring_write(ring,
1673                 PACKETJ(SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_JRBC_RB_MEM_RD_64BIT_BAR_LOW), 0, 0, PACKETJ_TYPE0));
1674         amdgpu_ring_write(ring, lower_32_bits(addr));
1675
1676         amdgpu_ring_write(ring,
1677                 PACKETJ(SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_JRBC_RB_MEM_RD_64BIT_BAR_HIGH), 0, 0, PACKETJ_TYPE0));
1678         amdgpu_ring_write(ring, upper_32_bits(addr));
1679
1680         amdgpu_ring_write(ring,
1681                 PACKETJ(0, 0, PACKETJ_CONDITION_CHECK3, PACKETJ_TYPE2));
1682         amdgpu_ring_write(ring, 0xffffffff);
1683
1684         amdgpu_ring_write(ring,
1685                 PACKETJ(SOC15_REG_OFFSET(UVD, 0, mmUVD_JRBC_EXTERNAL_REG_BASE), 0, 0, PACKETJ_TYPE0));
1686         amdgpu_ring_write(ring, 0x3fbc);
1687
1688         amdgpu_ring_write(ring,
1689                 PACKETJ(0, 0, 0, PACKETJ_TYPE0));
1690         amdgpu_ring_write(ring, 0x1);
1691
1692         /* emit trap */
1693         amdgpu_ring_write(ring, PACKETJ(0, 0, 0, PACKETJ_TYPE7));
1694         amdgpu_ring_write(ring, 0);
1695 }
1696
1697 /**
1698  * vcn_v1_0_jpeg_ring_emit_ib - execute indirect buffer
1699  *
1700  * @ring: amdgpu_ring pointer
1701  * @ib: indirect buffer to execute
1702  *
1703  * Write ring commands to execute the indirect buffer.
1704  */
1705 static void vcn_v1_0_jpeg_ring_emit_ib(struct amdgpu_ring *ring,
1706                                   struct amdgpu_ib *ib,
1707                                   unsigned vmid, bool ctx_switch)
1708 {
1709         struct amdgpu_device *adev = ring->adev;
1710
1711         amdgpu_ring_write(ring,
1712                 PACKETJ(SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_JRBC_IB_VMID), 0, 0, PACKETJ_TYPE0));
1713         amdgpu_ring_write(ring, (vmid | (vmid << 4)));
1714
1715         amdgpu_ring_write(ring,
1716                 PACKETJ(SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_JPEG_VMID), 0, 0, PACKETJ_TYPE0));
1717         amdgpu_ring_write(ring, (vmid | (vmid << 4)));
1718
1719         amdgpu_ring_write(ring,
1720                 PACKETJ(SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_JRBC_IB_64BIT_BAR_LOW), 0, 0, PACKETJ_TYPE0));
1721         amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr));
1722
1723         amdgpu_ring_write(ring,
1724                 PACKETJ(SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_JRBC_IB_64BIT_BAR_HIGH), 0, 0, PACKETJ_TYPE0));
1725         amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr));
1726
1727         amdgpu_ring_write(ring,
1728                 PACKETJ(SOC15_REG_OFFSET(UVD, 0, mmUVD_JRBC_IB_SIZE), 0, 0, PACKETJ_TYPE0));
1729         amdgpu_ring_write(ring, ib->length_dw);
1730
1731         amdgpu_ring_write(ring,
1732                 PACKETJ(SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_JRBC_RB_MEM_RD_64BIT_BAR_LOW), 0, 0, PACKETJ_TYPE0));
1733         amdgpu_ring_write(ring, lower_32_bits(ring->gpu_addr));
1734
1735         amdgpu_ring_write(ring,
1736                 PACKETJ(SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_JRBC_RB_MEM_RD_64BIT_BAR_HIGH), 0, 0, PACKETJ_TYPE0));
1737         amdgpu_ring_write(ring, upper_32_bits(ring->gpu_addr));
1738
1739         amdgpu_ring_write(ring,
1740                 PACKETJ(0, 0, PACKETJ_CONDITION_CHECK0, PACKETJ_TYPE2));
1741         amdgpu_ring_write(ring, 0);
1742
1743         amdgpu_ring_write(ring,
1744                 PACKETJ(SOC15_REG_OFFSET(UVD, 0, mmUVD_JRBC_RB_COND_RD_TIMER), 0, 0, PACKETJ_TYPE0));
1745         amdgpu_ring_write(ring, 0x01400200);
1746
1747         amdgpu_ring_write(ring,
1748                 PACKETJ(SOC15_REG_OFFSET(UVD, 0, mmUVD_JRBC_RB_REF_DATA), 0, 0, PACKETJ_TYPE0));
1749         amdgpu_ring_write(ring, 0x2);
1750
1751         amdgpu_ring_write(ring,
1752                 PACKETJ(SOC15_REG_OFFSET(UVD, 0, mmUVD_JRBC_STATUS), 0, PACKETJ_CONDITION_CHECK3, PACKETJ_TYPE3));
1753         amdgpu_ring_write(ring, 0x2);
1754 }
1755
1756 static void vcn_v1_0_jpeg_ring_emit_reg_wait(struct amdgpu_ring *ring,
1757                                             uint32_t reg, uint32_t val,
1758                                             uint32_t mask)
1759 {
1760         struct amdgpu_device *adev = ring->adev;
1761         uint32_t reg_offset = (reg << 2);
1762
1763         amdgpu_ring_write(ring,
1764                 PACKETJ(SOC15_REG_OFFSET(UVD, 0, mmUVD_JRBC_RB_COND_RD_TIMER), 0, 0, PACKETJ_TYPE0));
1765         amdgpu_ring_write(ring, 0x01400200);
1766
1767         amdgpu_ring_write(ring,
1768                 PACKETJ(SOC15_REG_OFFSET(UVD, 0, mmUVD_JRBC_RB_REF_DATA), 0, 0, PACKETJ_TYPE0));
1769         amdgpu_ring_write(ring, val);
1770
1771         amdgpu_ring_write(ring,
1772                 PACKETJ(SOC15_REG_OFFSET(UVD, 0, mmUVD_JRBC_EXTERNAL_REG_BASE), 0, 0, PACKETJ_TYPE0));
1773         if (((reg_offset >= 0x1f800) && (reg_offset <= 0x21fff)) ||
1774                 ((reg_offset >= 0x1e000) && (reg_offset <= 0x1e1ff))) {
1775                 amdgpu_ring_write(ring, 0);
1776                 amdgpu_ring_write(ring,
1777                         PACKETJ((reg_offset >> 2), 0, 0, PACKETJ_TYPE3));
1778         } else {
1779                 amdgpu_ring_write(ring, reg_offset);
1780                 amdgpu_ring_write(ring,
1781                         PACKETJ(0, 0, 0, PACKETJ_TYPE3));
1782         }
1783         amdgpu_ring_write(ring, mask);
1784 }
1785
1786 static void vcn_v1_0_jpeg_ring_emit_vm_flush(struct amdgpu_ring *ring,
1787                 unsigned vmid, uint64_t pd_addr)
1788 {
1789         struct amdgpu_vmhub *hub = &ring->adev->vmhub[ring->funcs->vmhub];
1790         uint32_t data0, data1, mask;
1791
1792         pd_addr = amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr);
1793
1794         /* wait for register write */
1795         data0 = hub->ctx0_ptb_addr_lo32 + vmid * 2;
1796         data1 = lower_32_bits(pd_addr);
1797         mask = 0xffffffff;
1798         vcn_v1_0_jpeg_ring_emit_reg_wait(ring, data0, data1, mask);
1799 }
1800
1801 static void vcn_v1_0_jpeg_ring_emit_wreg(struct amdgpu_ring *ring,
1802                                         uint32_t reg, uint32_t val)
1803 {
1804         struct amdgpu_device *adev = ring->adev;
1805         uint32_t reg_offset = (reg << 2);
1806
1807         amdgpu_ring_write(ring,
1808                 PACKETJ(SOC15_REG_OFFSET(UVD, 0, mmUVD_JRBC_EXTERNAL_REG_BASE), 0, 0, PACKETJ_TYPE0));
1809         if (((reg_offset >= 0x1f800) && (reg_offset <= 0x21fff)) ||
1810                         ((reg_offset >= 0x1e000) && (reg_offset <= 0x1e1ff))) {
1811                 amdgpu_ring_write(ring, 0);
1812                 amdgpu_ring_write(ring,
1813                         PACKETJ((reg_offset >> 2), 0, 0, PACKETJ_TYPE0));
1814         } else {
1815                 amdgpu_ring_write(ring, reg_offset);
1816                 amdgpu_ring_write(ring,
1817                         PACKETJ(0, 0, 0, PACKETJ_TYPE0));
1818         }
1819         amdgpu_ring_write(ring, val);
1820 }
1821
1822 static void vcn_v1_0_jpeg_ring_nop(struct amdgpu_ring *ring, uint32_t count)
1823 {
1824         int i;
1825
1826         WARN_ON(ring->wptr % 2 || count % 2);
1827
1828         for (i = 0; i < count / 2; i++) {
1829                 amdgpu_ring_write(ring, PACKETJ(0, 0, 0, PACKETJ_TYPE6));
1830                 amdgpu_ring_write(ring, 0);
1831         }
1832 }
1833
1834 static void vcn_v1_0_jpeg_ring_patch_wreg(struct amdgpu_ring *ring, uint32_t *ptr, uint32_t reg_offset, uint32_t val)
1835 {
1836         struct amdgpu_device *adev = ring->adev;
1837         ring->ring[(*ptr)++] = PACKETJ(SOC15_REG_OFFSET(UVD, 0, mmUVD_JRBC_EXTERNAL_REG_BASE), 0, 0, PACKETJ_TYPE0);
1838         if (((reg_offset >= 0x1f800) && (reg_offset <= 0x21fff)) ||
1839                 ((reg_offset >= 0x1e000) && (reg_offset <= 0x1e1ff))) {
1840                 ring->ring[(*ptr)++] = 0;
1841                 ring->ring[(*ptr)++] = PACKETJ((reg_offset >> 2), 0, 0, PACKETJ_TYPE0);
1842         } else {
1843                 ring->ring[(*ptr)++] = reg_offset;
1844                 ring->ring[(*ptr)++] = PACKETJ(0, 0, 0, PACKETJ_TYPE0);
1845         }
1846         ring->ring[(*ptr)++] = val;
1847 }
1848
1849 static void vcn_v1_0_jpeg_ring_set_patch_ring(struct amdgpu_ring *ring, uint32_t ptr)
1850 {
1851         struct amdgpu_device *adev = ring->adev;
1852
1853         uint32_t reg, reg_offset, val, mask, i;
1854
1855         // 1st: program mmUVD_LMI_JRBC_RB_MEM_RD_64BIT_BAR_LOW
1856         reg = SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_JRBC_RB_MEM_RD_64BIT_BAR_LOW);
1857         reg_offset = (reg << 2);
1858         val = lower_32_bits(ring->gpu_addr);
1859         vcn_v1_0_jpeg_ring_patch_wreg(ring, &ptr, reg_offset, val);
1860
1861         // 2nd: program mmUVD_LMI_JRBC_RB_MEM_RD_64BIT_BAR_HIGH
1862         reg = SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_JRBC_RB_MEM_RD_64BIT_BAR_HIGH);
1863         reg_offset = (reg << 2);
1864         val = upper_32_bits(ring->gpu_addr);
1865         vcn_v1_0_jpeg_ring_patch_wreg(ring, &ptr, reg_offset, val);
1866
1867         // 3rd to 5th: issue MEM_READ commands
1868         for (i = 0; i <= 2; i++) {
1869                 ring->ring[ptr++] = PACKETJ(0, 0, 0, PACKETJ_TYPE2);
1870                 ring->ring[ptr++] = 0;
1871         }
1872
1873         // 6th: program mmUVD_JRBC_RB_CNTL register to enable NO_FETCH and RPTR write ability
1874         reg = SOC15_REG_OFFSET(UVD, 0, mmUVD_JRBC_RB_CNTL);
1875         reg_offset = (reg << 2);
1876         val = 0x13;
1877         vcn_v1_0_jpeg_ring_patch_wreg(ring, &ptr, reg_offset, val);
1878
1879         // 7th: program mmUVD_JRBC_RB_REF_DATA
1880         reg = SOC15_REG_OFFSET(UVD, 0, mmUVD_JRBC_RB_REF_DATA);
1881         reg_offset = (reg << 2);
1882         val = 0x1;
1883         vcn_v1_0_jpeg_ring_patch_wreg(ring, &ptr, reg_offset, val);
1884
1885         // 8th: issue conditional register read mmUVD_JRBC_RB_CNTL
1886         reg = SOC15_REG_OFFSET(UVD, 0, mmUVD_JRBC_RB_CNTL);
1887         reg_offset = (reg << 2);
1888         val = 0x1;
1889         mask = 0x1;
1890
1891         ring->ring[ptr++] = PACKETJ(SOC15_REG_OFFSET(UVD, 0, mmUVD_JRBC_RB_COND_RD_TIMER), 0, 0, PACKETJ_TYPE0);
1892         ring->ring[ptr++] = 0x01400200;
1893         ring->ring[ptr++] = PACKETJ(SOC15_REG_OFFSET(UVD, 0, mmUVD_JRBC_RB_REF_DATA), 0, 0, PACKETJ_TYPE0);
1894         ring->ring[ptr++] = val;
1895         ring->ring[ptr++] = PACKETJ(SOC15_REG_OFFSET(UVD, 0, mmUVD_JRBC_EXTERNAL_REG_BASE), 0, 0, PACKETJ_TYPE0);
1896         if (((reg_offset >= 0x1f800) && (reg_offset <= 0x21fff)) ||
1897                 ((reg_offset >= 0x1e000) && (reg_offset <= 0x1e1ff))) {
1898                 ring->ring[ptr++] = 0;
1899                 ring->ring[ptr++] = PACKETJ((reg_offset >> 2), 0, 0, PACKETJ_TYPE3);
1900         } else {
1901                 ring->ring[ptr++] = reg_offset;
1902                 ring->ring[ptr++] = PACKETJ(0, 0, 0, PACKETJ_TYPE3);
1903         }
1904         ring->ring[ptr++] = mask;
1905
1906         //9th to 21st: insert no-op
1907         for (i = 0; i <= 12; i++) {
1908                 ring->ring[ptr++] = PACKETJ(0, 0, 0, PACKETJ_TYPE6);
1909                 ring->ring[ptr++] = 0;
1910         }
1911
1912         //22nd: reset mmUVD_JRBC_RB_RPTR
1913         reg = SOC15_REG_OFFSET(UVD, 0, mmUVD_JRBC_RB_RPTR);
1914         reg_offset = (reg << 2);
1915         val = 0;
1916         vcn_v1_0_jpeg_ring_patch_wreg(ring, &ptr, reg_offset, val);
1917
1918         //23rd: program mmUVD_JRBC_RB_CNTL to disable no_fetch
1919         reg = SOC15_REG_OFFSET(UVD, 0, mmUVD_JRBC_RB_CNTL);
1920         reg_offset = (reg << 2);
1921         val = 0x12;
1922         vcn_v1_0_jpeg_ring_patch_wreg(ring, &ptr, reg_offset, val);
1923 }
1924
1925 static int vcn_v1_0_set_interrupt_state(struct amdgpu_device *adev,
1926                                         struct amdgpu_irq_src *source,
1927                                         unsigned type,
1928                                         enum amdgpu_interrupt_state state)
1929 {
1930         return 0;
1931 }
1932
1933 static int vcn_v1_0_process_interrupt(struct amdgpu_device *adev,
1934                                       struct amdgpu_irq_src *source,
1935                                       struct amdgpu_iv_entry *entry)
1936 {
1937         DRM_DEBUG("IH: VCN TRAP\n");
1938
1939         switch (entry->src_id) {
1940         case 124:
1941                 amdgpu_fence_process(&adev->vcn.ring_dec);
1942                 break;
1943         case 119:
1944                 amdgpu_fence_process(&adev->vcn.ring_enc[0]);
1945                 break;
1946         case 120:
1947                 amdgpu_fence_process(&adev->vcn.ring_enc[1]);
1948                 break;
1949         case 126:
1950                 amdgpu_fence_process(&adev->vcn.ring_jpeg);
1951                 break;
1952         default:
1953                 DRM_ERROR("Unhandled interrupt: %d %d\n",
1954                           entry->src_id, entry->src_data[0]);
1955                 break;
1956         }
1957
1958         return 0;
1959 }
1960
1961 static void vcn_v1_0_dec_ring_insert_nop(struct amdgpu_ring *ring, uint32_t count)
1962 {
1963         struct amdgpu_device *adev = ring->adev;
1964         int i;
1965
1966         WARN_ON(ring->wptr % 2 || count % 2);
1967
1968         for (i = 0; i < count / 2; i++) {
1969                 amdgpu_ring_write(ring, PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_NO_OP), 0));
1970                 amdgpu_ring_write(ring, 0);
1971         }
1972 }
1973
1974 static int vcn_v1_0_set_powergating_state(void *handle,
1975                                           enum amd_powergating_state state)
1976 {
1977         /* This doesn't actually powergate the VCN block.
1978          * That's done in the dpm code via the SMC.  This
1979          * just re-inits the block as necessary.  The actual
1980          * gating still happens in the dpm code.  We should
1981          * revisit this when there is a cleaner line between
1982          * the smc and the hw blocks
1983          */
1984         int ret;
1985         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1986
1987         if(state == adev->vcn.cur_state)
1988                 return 0;
1989
1990         if (state == AMD_PG_STATE_GATE)
1991                 ret = vcn_v1_0_stop(adev);
1992         else
1993                 ret = vcn_v1_0_start(adev);
1994
1995         if(!ret)
1996                 adev->vcn.cur_state = state;
1997         return ret;
1998 }
1999
2000 static const struct amd_ip_funcs vcn_v1_0_ip_funcs = {
2001         .name = "vcn_v1_0",
2002         .early_init = vcn_v1_0_early_init,
2003         .late_init = NULL,
2004         .sw_init = vcn_v1_0_sw_init,
2005         .sw_fini = vcn_v1_0_sw_fini,
2006         .hw_init = vcn_v1_0_hw_init,
2007         .hw_fini = vcn_v1_0_hw_fini,
2008         .suspend = vcn_v1_0_suspend,
2009         .resume = vcn_v1_0_resume,
2010         .is_idle = vcn_v1_0_is_idle,
2011         .wait_for_idle = vcn_v1_0_wait_for_idle,
2012         .check_soft_reset = NULL /* vcn_v1_0_check_soft_reset */,
2013         .pre_soft_reset = NULL /* vcn_v1_0_pre_soft_reset */,
2014         .soft_reset = NULL /* vcn_v1_0_soft_reset */,
2015         .post_soft_reset = NULL /* vcn_v1_0_post_soft_reset */,
2016         .set_clockgating_state = vcn_v1_0_set_clockgating_state,
2017         .set_powergating_state = vcn_v1_0_set_powergating_state,
2018 };
2019
2020 static const struct amdgpu_ring_funcs vcn_v1_0_dec_ring_vm_funcs = {
2021         .type = AMDGPU_RING_TYPE_VCN_DEC,
2022         .align_mask = 0xf,
2023         .support_64bit_ptrs = false,
2024         .vmhub = AMDGPU_MMHUB,
2025         .get_rptr = vcn_v1_0_dec_ring_get_rptr,
2026         .get_wptr = vcn_v1_0_dec_ring_get_wptr,
2027         .set_wptr = vcn_v1_0_dec_ring_set_wptr,
2028         .emit_frame_size =
2029                 6 + 6 + /* hdp invalidate / flush */
2030                 SOC15_FLUSH_GPU_TLB_NUM_WREG * 6 +
2031                 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 8 +
2032                 8 + /* vcn_v1_0_dec_ring_emit_vm_flush */
2033                 14 + 14 + /* vcn_v1_0_dec_ring_emit_fence x2 vm fence */
2034                 6,
2035         .emit_ib_size = 8, /* vcn_v1_0_dec_ring_emit_ib */
2036         .emit_ib = vcn_v1_0_dec_ring_emit_ib,
2037         .emit_fence = vcn_v1_0_dec_ring_emit_fence,
2038         .emit_vm_flush = vcn_v1_0_dec_ring_emit_vm_flush,
2039         .test_ring = amdgpu_vcn_dec_ring_test_ring,
2040         .test_ib = amdgpu_vcn_dec_ring_test_ib,
2041         .insert_nop = vcn_v1_0_dec_ring_insert_nop,
2042         .insert_start = vcn_v1_0_dec_ring_insert_start,
2043         .insert_end = vcn_v1_0_dec_ring_insert_end,
2044         .pad_ib = amdgpu_ring_generic_pad_ib,
2045         .begin_use = amdgpu_vcn_ring_begin_use,
2046         .end_use = amdgpu_vcn_ring_end_use,
2047         .emit_wreg = vcn_v1_0_dec_ring_emit_wreg,
2048         .emit_reg_wait = vcn_v1_0_dec_ring_emit_reg_wait,
2049         .emit_reg_write_reg_wait = amdgpu_ring_emit_reg_write_reg_wait_helper,
2050 };
2051
2052 static const struct amdgpu_ring_funcs vcn_v1_0_enc_ring_vm_funcs = {
2053         .type = AMDGPU_RING_TYPE_VCN_ENC,
2054         .align_mask = 0x3f,
2055         .nop = VCN_ENC_CMD_NO_OP,
2056         .support_64bit_ptrs = false,
2057         .vmhub = AMDGPU_MMHUB,
2058         .get_rptr = vcn_v1_0_enc_ring_get_rptr,
2059         .get_wptr = vcn_v1_0_enc_ring_get_wptr,
2060         .set_wptr = vcn_v1_0_enc_ring_set_wptr,
2061         .emit_frame_size =
2062                 SOC15_FLUSH_GPU_TLB_NUM_WREG * 3 +
2063                 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 4 +
2064                 4 + /* vcn_v1_0_enc_ring_emit_vm_flush */
2065                 5 + 5 + /* vcn_v1_0_enc_ring_emit_fence x2 vm fence */
2066                 1, /* vcn_v1_0_enc_ring_insert_end */
2067         .emit_ib_size = 5, /* vcn_v1_0_enc_ring_emit_ib */
2068         .emit_ib = vcn_v1_0_enc_ring_emit_ib,
2069         .emit_fence = vcn_v1_0_enc_ring_emit_fence,
2070         .emit_vm_flush = vcn_v1_0_enc_ring_emit_vm_flush,
2071         .test_ring = amdgpu_vcn_enc_ring_test_ring,
2072         .test_ib = amdgpu_vcn_enc_ring_test_ib,
2073         .insert_nop = amdgpu_ring_insert_nop,
2074         .insert_end = vcn_v1_0_enc_ring_insert_end,
2075         .pad_ib = amdgpu_ring_generic_pad_ib,
2076         .begin_use = amdgpu_vcn_ring_begin_use,
2077         .end_use = amdgpu_vcn_ring_end_use,
2078         .emit_wreg = vcn_v1_0_enc_ring_emit_wreg,
2079         .emit_reg_wait = vcn_v1_0_enc_ring_emit_reg_wait,
2080         .emit_reg_write_reg_wait = amdgpu_ring_emit_reg_write_reg_wait_helper,
2081 };
2082
2083 static const struct amdgpu_ring_funcs vcn_v1_0_jpeg_ring_vm_funcs = {
2084         .type = AMDGPU_RING_TYPE_VCN_JPEG,
2085         .align_mask = 0xf,
2086         .nop = PACKET0(0x81ff, 0),
2087         .support_64bit_ptrs = false,
2088         .vmhub = AMDGPU_MMHUB,
2089         .extra_dw = 64,
2090         .get_rptr = vcn_v1_0_jpeg_ring_get_rptr,
2091         .get_wptr = vcn_v1_0_jpeg_ring_get_wptr,
2092         .set_wptr = vcn_v1_0_jpeg_ring_set_wptr,
2093         .emit_frame_size =
2094                 6 + 6 + /* hdp invalidate / flush */
2095                 SOC15_FLUSH_GPU_TLB_NUM_WREG * 6 +
2096                 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 8 +
2097                 8 + /* vcn_v1_0_jpeg_ring_emit_vm_flush */
2098                 26 + 26 + /* vcn_v1_0_jpeg_ring_emit_fence x2 vm fence */
2099                 6,
2100         .emit_ib_size = 22, /* vcn_v1_0_jpeg_ring_emit_ib */
2101         .emit_ib = vcn_v1_0_jpeg_ring_emit_ib,
2102         .emit_fence = vcn_v1_0_jpeg_ring_emit_fence,
2103         .emit_vm_flush = vcn_v1_0_jpeg_ring_emit_vm_flush,
2104         .test_ring = amdgpu_vcn_jpeg_ring_test_ring,
2105         .test_ib = amdgpu_vcn_jpeg_ring_test_ib,
2106         .insert_nop = vcn_v1_0_jpeg_ring_nop,
2107         .insert_start = vcn_v1_0_jpeg_ring_insert_start,
2108         .insert_end = vcn_v1_0_jpeg_ring_insert_end,
2109         .pad_ib = amdgpu_ring_generic_pad_ib,
2110         .begin_use = amdgpu_vcn_ring_begin_use,
2111         .end_use = amdgpu_vcn_ring_end_use,
2112         .emit_wreg = vcn_v1_0_jpeg_ring_emit_wreg,
2113         .emit_reg_wait = vcn_v1_0_jpeg_ring_emit_reg_wait,
2114         .emit_reg_write_reg_wait = amdgpu_ring_emit_reg_write_reg_wait_helper,
2115 };
2116
2117 static void vcn_v1_0_set_dec_ring_funcs(struct amdgpu_device *adev)
2118 {
2119         adev->vcn.ring_dec.funcs = &vcn_v1_0_dec_ring_vm_funcs;
2120         DRM_INFO("VCN decode is enabled in VM mode\n");
2121 }
2122
2123 static void vcn_v1_0_set_enc_ring_funcs(struct amdgpu_device *adev)
2124 {
2125         int i;
2126
2127         for (i = 0; i < adev->vcn.num_enc_rings; ++i)
2128                 adev->vcn.ring_enc[i].funcs = &vcn_v1_0_enc_ring_vm_funcs;
2129
2130         DRM_INFO("VCN encode is enabled in VM mode\n");
2131 }
2132
2133 static void vcn_v1_0_set_jpeg_ring_funcs(struct amdgpu_device *adev)
2134 {
2135         adev->vcn.ring_jpeg.funcs = &vcn_v1_0_jpeg_ring_vm_funcs;
2136         DRM_INFO("VCN jpeg decode is enabled in VM mode\n");
2137 }
2138
2139 static const struct amdgpu_irq_src_funcs vcn_v1_0_irq_funcs = {
2140         .set = vcn_v1_0_set_interrupt_state,
2141         .process = vcn_v1_0_process_interrupt,
2142 };
2143
2144 static void vcn_v1_0_set_irq_funcs(struct amdgpu_device *adev)
2145 {
2146         adev->vcn.irq.num_types = adev->vcn.num_enc_rings + 2;
2147         adev->vcn.irq.funcs = &vcn_v1_0_irq_funcs;
2148 }
2149
2150 const struct amdgpu_ip_block_version vcn_v1_0_ip_block =
2151 {
2152                 .type = AMD_IP_BLOCK_TYPE_VCN,
2153                 .major = 1,
2154                 .minor = 0,
2155                 .rev = 0,
2156                 .funcs = &vcn_v1_0_ip_funcs,
2157 };