2 * Copyright 2016 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
24 #include <linux/pci.h>
27 #include "amdgpu_ih.h"
30 #include "oss/osssys_4_0_offset.h"
31 #include "oss/osssys_4_0_sh_mask.h"
33 #include "soc15_common.h"
34 #include "vega10_ih.h"
36 #define MAX_REARM_RETRY 10
38 static void vega10_ih_set_interrupt_funcs(struct amdgpu_device *adev);
41 * vega10_ih_enable_interrupts - Enable the interrupt ring buffer
43 * @adev: amdgpu_device pointer
45 * Enable the interrupt ring buffer (VEGA10).
47 static void vega10_ih_enable_interrupts(struct amdgpu_device *adev)
49 u32 ih_rb_cntl = RREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL);
51 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, RB_ENABLE, 1);
52 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, ENABLE_INTR, 1);
53 if (amdgpu_sriov_vf(adev)) {
54 if (psp_reg_program(&adev->psp, PSP_REG_IH_RB_CNTL, ih_rb_cntl)) {
55 DRM_ERROR("PSP program IH_RB_CNTL failed!\n");
59 WREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL, ih_rb_cntl);
61 adev->irq.ih.enabled = true;
63 if (adev->irq.ih1.ring_size) {
64 ih_rb_cntl = RREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING1);
65 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL_RING1,
67 if (amdgpu_sriov_vf(adev)) {
68 if (psp_reg_program(&adev->psp, PSP_REG_IH_RB_CNTL_RING1,
70 DRM_ERROR("program IH_RB_CNTL_RING1 failed!\n");
74 WREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING1, ih_rb_cntl);
76 adev->irq.ih1.enabled = true;
79 if (adev->irq.ih2.ring_size) {
80 ih_rb_cntl = RREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING2);
81 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL_RING2,
83 if (amdgpu_sriov_vf(adev)) {
84 if (psp_reg_program(&adev->psp, PSP_REG_IH_RB_CNTL_RING2,
86 DRM_ERROR("program IH_RB_CNTL_RING2 failed!\n");
90 WREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING2, ih_rb_cntl);
92 adev->irq.ih2.enabled = true;
97 * vega10_ih_disable_interrupts - Disable the interrupt ring buffer
99 * @adev: amdgpu_device pointer
101 * Disable the interrupt ring buffer (VEGA10).
103 static void vega10_ih_disable_interrupts(struct amdgpu_device *adev)
105 u32 ih_rb_cntl = RREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL);
107 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, RB_ENABLE, 0);
108 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, ENABLE_INTR, 0);
109 if (amdgpu_sriov_vf(adev)) {
110 if (psp_reg_program(&adev->psp, PSP_REG_IH_RB_CNTL, ih_rb_cntl)) {
111 DRM_ERROR("PSP program IH_RB_CNTL failed!\n");
115 WREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL, ih_rb_cntl);
118 /* set rptr, wptr to 0 */
119 WREG32_SOC15(OSSSYS, 0, mmIH_RB_RPTR, 0);
120 WREG32_SOC15(OSSSYS, 0, mmIH_RB_WPTR, 0);
121 adev->irq.ih.enabled = false;
122 adev->irq.ih.rptr = 0;
124 if (adev->irq.ih1.ring_size) {
125 ih_rb_cntl = RREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING1);
126 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL_RING1,
128 if (amdgpu_sriov_vf(adev)) {
129 if (psp_reg_program(&adev->psp, PSP_REG_IH_RB_CNTL_RING1,
131 DRM_ERROR("program IH_RB_CNTL_RING1 failed!\n");
135 WREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING1, ih_rb_cntl);
137 /* set rptr, wptr to 0 */
138 WREG32_SOC15(OSSSYS, 0, mmIH_RB_RPTR_RING1, 0);
139 WREG32_SOC15(OSSSYS, 0, mmIH_RB_WPTR_RING1, 0);
140 adev->irq.ih1.enabled = false;
141 adev->irq.ih1.rptr = 0;
144 if (adev->irq.ih2.ring_size) {
145 ih_rb_cntl = RREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING2);
146 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL_RING2,
148 if (amdgpu_sriov_vf(adev)) {
149 if (psp_reg_program(&adev->psp, PSP_REG_IH_RB_CNTL_RING2,
151 DRM_ERROR("program IH_RB_CNTL_RING2 failed!\n");
155 WREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING2, ih_rb_cntl);
158 /* set rptr, wptr to 0 */
159 WREG32_SOC15(OSSSYS, 0, mmIH_RB_RPTR_RING2, 0);
160 WREG32_SOC15(OSSSYS, 0, mmIH_RB_WPTR_RING2, 0);
161 adev->irq.ih2.enabled = false;
162 adev->irq.ih2.rptr = 0;
166 static uint32_t vega10_ih_rb_cntl(struct amdgpu_ih_ring *ih, uint32_t ih_rb_cntl)
168 int rb_bufsz = order_base_2(ih->ring_size / 4);
170 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL,
171 MC_SPACE, ih->use_bus_addr ? 1 : 4);
172 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL,
173 WPTR_OVERFLOW_CLEAR, 1);
174 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL,
175 WPTR_OVERFLOW_ENABLE, 1);
176 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, RB_SIZE, rb_bufsz);
177 /* Ring Buffer write pointer writeback. If enabled, IH_RB_WPTR register
178 * value is written to memory
180 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL,
181 WPTR_WRITEBACK_ENABLE, 1);
182 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, MC_SNOOP, 1);
183 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, MC_RO, 0);
184 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, MC_VMID, 0);
189 static uint32_t vega10_ih_doorbell_rptr(struct amdgpu_ih_ring *ih)
191 u32 ih_doorbell_rtpr = 0;
193 if (ih->use_doorbell) {
194 ih_doorbell_rtpr = REG_SET_FIELD(ih_doorbell_rtpr,
195 IH_DOORBELL_RPTR, OFFSET,
197 ih_doorbell_rtpr = REG_SET_FIELD(ih_doorbell_rtpr,
201 ih_doorbell_rtpr = REG_SET_FIELD(ih_doorbell_rtpr,
205 return ih_doorbell_rtpr;
209 * vega10_ih_irq_init - init and enable the interrupt ring
211 * @adev: amdgpu_device pointer
213 * Allocate a ring buffer for the interrupt controller,
214 * enable the RLC, disable interrupts, enable the IH
215 * ring buffer and enable it (VI).
216 * Called at device load and reume.
217 * Returns 0 for success, errors for failure.
219 static int vega10_ih_irq_init(struct amdgpu_device *adev)
221 struct amdgpu_ih_ring *ih;
222 u32 ih_rb_cntl, ih_chicken;
227 vega10_ih_disable_interrupts(adev);
229 adev->nbio.funcs->ih_control(adev);
232 /* Ring Buffer base. [39:8] of 40-bit address of the beginning of the ring buffer*/
233 WREG32_SOC15(OSSSYS, 0, mmIH_RB_BASE, ih->gpu_addr >> 8);
234 WREG32_SOC15(OSSSYS, 0, mmIH_RB_BASE_HI, (ih->gpu_addr >> 40) & 0xff);
236 ih_rb_cntl = RREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL);
237 ih_chicken = RREG32_SOC15(OSSSYS, 0, mmIH_CHICKEN);
238 ih_rb_cntl = vega10_ih_rb_cntl(ih, ih_rb_cntl);
239 if (adev->irq.ih.use_bus_addr) {
240 ih_chicken = REG_SET_FIELD(ih_chicken, IH_CHICKEN, MC_SPACE_GPA_ENABLE, 1);
242 ih_chicken = REG_SET_FIELD(ih_chicken, IH_CHICKEN, MC_SPACE_FBPA_ENABLE, 1);
244 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, RPTR_REARM,
245 !!adev->irq.msi_enabled);
247 if (amdgpu_sriov_vf(adev)) {
248 if (psp_reg_program(&adev->psp, PSP_REG_IH_RB_CNTL, ih_rb_cntl)) {
249 DRM_ERROR("PSP program IH_RB_CNTL failed!\n");
253 WREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL, ih_rb_cntl);
256 if ((adev->asic_type == CHIP_ARCTURUS
257 && adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT)
258 || adev->asic_type == CHIP_RENOIR)
259 WREG32_SOC15(OSSSYS, 0, mmIH_CHICKEN, ih_chicken);
261 /* set the writeback address whether it's enabled or not */
262 WREG32_SOC15(OSSSYS, 0, mmIH_RB_WPTR_ADDR_LO,
263 lower_32_bits(ih->wptr_addr));
264 WREG32_SOC15(OSSSYS, 0, mmIH_RB_WPTR_ADDR_HI,
265 upper_32_bits(ih->wptr_addr) & 0xFFFF);
267 /* set rptr, wptr to 0 */
268 WREG32_SOC15(OSSSYS, 0, mmIH_RB_WPTR, 0);
269 WREG32_SOC15(OSSSYS, 0, mmIH_RB_RPTR, 0);
271 WREG32_SOC15(OSSSYS, 0, mmIH_DOORBELL_RPTR,
272 vega10_ih_doorbell_rptr(ih));
276 WREG32_SOC15(OSSSYS, 0, mmIH_RB_BASE_RING1, ih->gpu_addr >> 8);
277 WREG32_SOC15(OSSSYS, 0, mmIH_RB_BASE_HI_RING1,
278 (ih->gpu_addr >> 40) & 0xff);
280 ih_rb_cntl = RREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING1);
281 ih_rb_cntl = vega10_ih_rb_cntl(ih, ih_rb_cntl);
282 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL,
283 WPTR_OVERFLOW_ENABLE, 0);
284 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL,
285 RB_FULL_DRAIN_ENABLE, 1);
286 if (amdgpu_sriov_vf(adev)) {
287 if (psp_reg_program(&adev->psp, PSP_REG_IH_RB_CNTL_RING1,
289 DRM_ERROR("program IH_RB_CNTL_RING1 failed!\n");
293 WREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING1, ih_rb_cntl);
296 /* set rptr, wptr to 0 */
297 WREG32_SOC15(OSSSYS, 0, mmIH_RB_WPTR_RING1, 0);
298 WREG32_SOC15(OSSSYS, 0, mmIH_RB_RPTR_RING1, 0);
300 WREG32_SOC15(OSSSYS, 0, mmIH_DOORBELL_RPTR_RING1,
301 vega10_ih_doorbell_rptr(ih));
306 WREG32_SOC15(OSSSYS, 0, mmIH_RB_BASE_RING2, ih->gpu_addr >> 8);
307 WREG32_SOC15(OSSSYS, 0, mmIH_RB_BASE_HI_RING2,
308 (ih->gpu_addr >> 40) & 0xff);
310 ih_rb_cntl = RREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING2);
311 ih_rb_cntl = vega10_ih_rb_cntl(ih, ih_rb_cntl);
313 if (amdgpu_sriov_vf(adev)) {
314 if (psp_reg_program(&adev->psp, PSP_REG_IH_RB_CNTL_RING2,
316 DRM_ERROR("program IH_RB_CNTL_RING2 failed!\n");
320 WREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING2, ih_rb_cntl);
323 /* set rptr, wptr to 0 */
324 WREG32_SOC15(OSSSYS, 0, mmIH_RB_WPTR_RING2, 0);
325 WREG32_SOC15(OSSSYS, 0, mmIH_RB_RPTR_RING2, 0);
327 WREG32_SOC15(OSSSYS, 0, mmIH_DOORBELL_RPTR_RING2,
328 vega10_ih_doorbell_rptr(ih));
331 tmp = RREG32_SOC15(OSSSYS, 0, mmIH_STORM_CLIENT_LIST_CNTL);
332 tmp = REG_SET_FIELD(tmp, IH_STORM_CLIENT_LIST_CNTL,
333 CLIENT18_IS_STORM_CLIENT, 1);
334 WREG32_SOC15(OSSSYS, 0, mmIH_STORM_CLIENT_LIST_CNTL, tmp);
336 tmp = RREG32_SOC15(OSSSYS, 0, mmIH_INT_FLOOD_CNTL);
337 tmp = REG_SET_FIELD(tmp, IH_INT_FLOOD_CNTL, FLOOD_CNTL_ENABLE, 1);
338 WREG32_SOC15(OSSSYS, 0, mmIH_INT_FLOOD_CNTL, tmp);
340 pci_set_master(adev->pdev);
342 /* enable interrupts */
343 vega10_ih_enable_interrupts(adev);
349 * vega10_ih_irq_disable - disable interrupts
351 * @adev: amdgpu_device pointer
353 * Disable interrupts on the hw (VEGA10).
355 static void vega10_ih_irq_disable(struct amdgpu_device *adev)
357 vega10_ih_disable_interrupts(adev);
359 /* Wait and acknowledge irq */
364 * vega10_ih_get_wptr - get the IH ring buffer wptr
366 * @adev: amdgpu_device pointer
368 * Get the IH ring buffer wptr from either the register
369 * or the writeback memory buffer (VEGA10). Also check for
370 * ring buffer overflow and deal with it.
371 * Returns the value of the wptr.
373 static u32 vega10_ih_get_wptr(struct amdgpu_device *adev,
374 struct amdgpu_ih_ring *ih)
378 wptr = le32_to_cpu(*ih->wptr_cpu);
380 if (!REG_GET_FIELD(wptr, IH_RB_WPTR, RB_OVERFLOW))
383 /* Double check that the overflow wasn't already cleared. */
385 if (ih == &adev->irq.ih)
386 reg = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_WPTR);
387 else if (ih == &adev->irq.ih1)
388 reg = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_WPTR_RING1);
389 else if (ih == &adev->irq.ih2)
390 reg = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_WPTR_RING2);
394 wptr = RREG32_NO_KIQ(reg);
395 if (!REG_GET_FIELD(wptr, IH_RB_WPTR, RB_OVERFLOW))
398 wptr = REG_SET_FIELD(wptr, IH_RB_WPTR, RB_OVERFLOW, 0);
400 /* When a ring buffer overflow happen start parsing interrupt
401 * from the last not overwritten vector (wptr + 32). Hopefully
402 * this should allow us to catchup.
404 tmp = (wptr + 32) & ih->ptr_mask;
405 dev_warn(adev->dev, "IH ring buffer overflow "
406 "(0x%08X, 0x%08X, 0x%08X)\n",
407 wptr, ih->rptr, tmp);
410 if (ih == &adev->irq.ih)
411 reg = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_CNTL);
412 else if (ih == &adev->irq.ih1)
413 reg = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_CNTL_RING1);
414 else if (ih == &adev->irq.ih2)
415 reg = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_CNTL_RING2);
419 tmp = RREG32_NO_KIQ(reg);
420 tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, WPTR_OVERFLOW_CLEAR, 1);
421 WREG32_NO_KIQ(reg, tmp);
424 return (wptr & ih->ptr_mask);
428 * vega10_ih_decode_iv - decode an interrupt vector
430 * @adev: amdgpu_device pointer
432 * Decodes the interrupt vector at the current rptr
433 * position and also advance the position.
435 static void vega10_ih_decode_iv(struct amdgpu_device *adev,
436 struct amdgpu_ih_ring *ih,
437 struct amdgpu_iv_entry *entry)
439 /* wptr/rptr are in bytes! */
440 u32 ring_index = ih->rptr >> 2;
443 dw[0] = le32_to_cpu(ih->ring[ring_index + 0]);
444 dw[1] = le32_to_cpu(ih->ring[ring_index + 1]);
445 dw[2] = le32_to_cpu(ih->ring[ring_index + 2]);
446 dw[3] = le32_to_cpu(ih->ring[ring_index + 3]);
447 dw[4] = le32_to_cpu(ih->ring[ring_index + 4]);
448 dw[5] = le32_to_cpu(ih->ring[ring_index + 5]);
449 dw[6] = le32_to_cpu(ih->ring[ring_index + 6]);
450 dw[7] = le32_to_cpu(ih->ring[ring_index + 7]);
452 entry->client_id = dw[0] & 0xff;
453 entry->src_id = (dw[0] >> 8) & 0xff;
454 entry->ring_id = (dw[0] >> 16) & 0xff;
455 entry->vmid = (dw[0] >> 24) & 0xf;
456 entry->vmid_src = (dw[0] >> 31);
457 entry->timestamp = dw[1] | ((u64)(dw[2] & 0xffff) << 32);
458 entry->timestamp_src = dw[2] >> 31;
459 entry->pasid = dw[3] & 0xffff;
460 entry->pasid_src = dw[3] >> 31;
461 entry->src_data[0] = dw[4];
462 entry->src_data[1] = dw[5];
463 entry->src_data[2] = dw[6];
464 entry->src_data[3] = dw[7];
466 /* wptr/rptr are in bytes! */
471 * vega10_ih_irq_rearm - rearm IRQ if lost
473 * @adev: amdgpu_device pointer
476 static void vega10_ih_irq_rearm(struct amdgpu_device *adev,
477 struct amdgpu_ih_ring *ih)
479 uint32_t reg_rptr = 0;
483 if (ih == &adev->irq.ih)
484 reg_rptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_RPTR);
485 else if (ih == &adev->irq.ih1)
486 reg_rptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_RPTR_RING1);
487 else if (ih == &adev->irq.ih2)
488 reg_rptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_RPTR_RING2);
492 /* Rearm IRQ / re-wwrite doorbell if doorbell write is lost */
493 for (i = 0; i < MAX_REARM_RETRY; i++) {
494 v = RREG32_NO_KIQ(reg_rptr);
495 if ((v < ih->ring_size) && (v != ih->rptr))
496 WDOORBELL32(ih->doorbell_index, ih->rptr);
503 * vega10_ih_set_rptr - set the IH ring buffer rptr
505 * @adev: amdgpu_device pointer
507 * Set the IH ring buffer rptr.
509 static void vega10_ih_set_rptr(struct amdgpu_device *adev,
510 struct amdgpu_ih_ring *ih)
512 if (ih->use_doorbell) {
513 /* XXX check if swapping is necessary on BE */
514 *ih->rptr_cpu = ih->rptr;
515 WDOORBELL32(ih->doorbell_index, ih->rptr);
517 if (amdgpu_sriov_vf(adev))
518 vega10_ih_irq_rearm(adev, ih);
519 } else if (ih == &adev->irq.ih) {
520 WREG32_SOC15(OSSSYS, 0, mmIH_RB_RPTR, ih->rptr);
521 } else if (ih == &adev->irq.ih1) {
522 WREG32_SOC15(OSSSYS, 0, mmIH_RB_RPTR_RING1, ih->rptr);
523 } else if (ih == &adev->irq.ih2) {
524 WREG32_SOC15(OSSSYS, 0, mmIH_RB_RPTR_RING2, ih->rptr);
529 * vega10_ih_self_irq - dispatch work for ring 1 and 2
531 * @adev: amdgpu_device pointer
532 * @source: irq source
533 * @entry: IV with WPTR update
535 * Update the WPTR from the IV and schedule work to handle the entries.
537 static int vega10_ih_self_irq(struct amdgpu_device *adev,
538 struct amdgpu_irq_src *source,
539 struct amdgpu_iv_entry *entry)
541 uint32_t wptr = cpu_to_le32(entry->src_data[0]);
543 switch (entry->ring_id) {
545 *adev->irq.ih1.wptr_cpu = wptr;
546 schedule_work(&adev->irq.ih1_work);
549 *adev->irq.ih2.wptr_cpu = wptr;
550 schedule_work(&adev->irq.ih2_work);
557 static const struct amdgpu_irq_src_funcs vega10_ih_self_irq_funcs = {
558 .process = vega10_ih_self_irq,
561 static void vega10_ih_set_self_irq_funcs(struct amdgpu_device *adev)
563 adev->irq.self_irq.num_types = 0;
564 adev->irq.self_irq.funcs = &vega10_ih_self_irq_funcs;
567 static int vega10_ih_early_init(void *handle)
569 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
571 vega10_ih_set_interrupt_funcs(adev);
572 vega10_ih_set_self_irq_funcs(adev);
576 static int vega10_ih_sw_init(void *handle)
578 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
581 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_IH, 0,
582 &adev->irq.self_irq);
586 r = amdgpu_ih_ring_init(adev, &adev->irq.ih, 256 * 1024, true);
590 adev->irq.ih.use_doorbell = true;
591 adev->irq.ih.doorbell_index = adev->doorbell_index.ih << 1;
593 r = amdgpu_ih_ring_init(adev, &adev->irq.ih1, PAGE_SIZE, true);
597 adev->irq.ih1.use_doorbell = true;
598 adev->irq.ih1.doorbell_index = (adev->doorbell_index.ih + 1) << 1;
600 r = amdgpu_ih_ring_init(adev, &adev->irq.ih2, PAGE_SIZE, true);
604 adev->irq.ih2.use_doorbell = true;
605 adev->irq.ih2.doorbell_index = (adev->doorbell_index.ih + 2) << 1;
607 r = amdgpu_irq_init(adev);
612 static int vega10_ih_sw_fini(void *handle)
614 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
616 amdgpu_irq_fini(adev);
617 amdgpu_ih_ring_fini(adev, &adev->irq.ih2);
618 amdgpu_ih_ring_fini(adev, &adev->irq.ih1);
619 amdgpu_ih_ring_fini(adev, &adev->irq.ih);
624 static int vega10_ih_hw_init(void *handle)
627 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
629 r = vega10_ih_irq_init(adev);
636 static int vega10_ih_hw_fini(void *handle)
638 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
640 vega10_ih_irq_disable(adev);
645 static int vega10_ih_suspend(void *handle)
647 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
649 return vega10_ih_hw_fini(adev);
652 static int vega10_ih_resume(void *handle)
654 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
656 return vega10_ih_hw_init(adev);
659 static bool vega10_ih_is_idle(void *handle)
665 static int vega10_ih_wait_for_idle(void *handle)
671 static int vega10_ih_soft_reset(void *handle)
678 static void vega10_ih_update_clockgating_state(struct amdgpu_device *adev,
681 uint32_t data, def, field_val;
683 if (adev->cg_flags & AMD_CG_SUPPORT_IH_CG) {
684 def = data = RREG32_SOC15(OSSSYS, 0, mmIH_CLK_CTRL);
685 field_val = enable ? 0 : 1;
687 * Vega10 does not have IH_RETRY_INT_CAM_MEM_CLK_SOFT_OVERRIDE
688 * and IH_BUFFER_MEM_CLK_SOFT_OVERRIDE field.
690 if (adev->asic_type > CHIP_VEGA10) {
691 data = REG_SET_FIELD(data, IH_CLK_CTRL,
692 IH_RETRY_INT_CAM_MEM_CLK_SOFT_OVERRIDE, field_val);
693 data = REG_SET_FIELD(data, IH_CLK_CTRL,
694 IH_BUFFER_MEM_CLK_SOFT_OVERRIDE, field_val);
697 data = REG_SET_FIELD(data, IH_CLK_CTRL,
698 DBUS_MUX_CLK_SOFT_OVERRIDE, field_val);
699 data = REG_SET_FIELD(data, IH_CLK_CTRL,
700 OSSSYS_SHARE_CLK_SOFT_OVERRIDE, field_val);
701 data = REG_SET_FIELD(data, IH_CLK_CTRL,
702 LIMIT_SMN_CLK_SOFT_OVERRIDE, field_val);
703 data = REG_SET_FIELD(data, IH_CLK_CTRL,
704 DYN_CLK_SOFT_OVERRIDE, field_val);
705 data = REG_SET_FIELD(data, IH_CLK_CTRL,
706 REG_CLK_SOFT_OVERRIDE, field_val);
708 WREG32_SOC15(OSSSYS, 0, mmIH_CLK_CTRL, data);
712 static int vega10_ih_set_clockgating_state(void *handle,
713 enum amd_clockgating_state state)
715 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
717 vega10_ih_update_clockgating_state(adev,
718 state == AMD_CG_STATE_GATE ? true : false);
723 static int vega10_ih_set_powergating_state(void *handle,
724 enum amd_powergating_state state)
729 const struct amd_ip_funcs vega10_ih_ip_funcs = {
731 .early_init = vega10_ih_early_init,
733 .sw_init = vega10_ih_sw_init,
734 .sw_fini = vega10_ih_sw_fini,
735 .hw_init = vega10_ih_hw_init,
736 .hw_fini = vega10_ih_hw_fini,
737 .suspend = vega10_ih_suspend,
738 .resume = vega10_ih_resume,
739 .is_idle = vega10_ih_is_idle,
740 .wait_for_idle = vega10_ih_wait_for_idle,
741 .soft_reset = vega10_ih_soft_reset,
742 .set_clockgating_state = vega10_ih_set_clockgating_state,
743 .set_powergating_state = vega10_ih_set_powergating_state,
746 static const struct amdgpu_ih_funcs vega10_ih_funcs = {
747 .get_wptr = vega10_ih_get_wptr,
748 .decode_iv = vega10_ih_decode_iv,
749 .set_rptr = vega10_ih_set_rptr
752 static void vega10_ih_set_interrupt_funcs(struct amdgpu_device *adev)
754 adev->irq.ih_funcs = &vega10_ih_funcs;
757 const struct amdgpu_ip_block_version vega10_ih_ip_block =
759 .type = AMD_IP_BLOCK_TYPE_IH,
763 .funcs = &vega10_ih_ip_funcs,