2 * Copyright 2015 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
26 /* The caprices of the preprocessor require that this be declared right here */
27 #define CREATE_TRACE_POINTS
29 #include "dm_services_types.h"
31 #include "dc/inc/core_types.h"
35 #include "amdgpu_display.h"
36 #include "amdgpu_ucode.h"
38 #include "amdgpu_dm.h"
39 #include "amdgpu_pm.h"
41 #include "amd_shared.h"
42 #include "amdgpu_dm_irq.h"
43 #include "dm_helpers.h"
44 #include "amdgpu_dm_mst_types.h"
45 #if defined(CONFIG_DEBUG_FS)
46 #include "amdgpu_dm_debugfs.h"
49 #include "ivsrcid/ivsrcid_vislands30.h"
51 #include <linux/module.h>
52 #include <linux/moduleparam.h>
53 #include <linux/version.h>
54 #include <linux/types.h>
55 #include <linux/pm_runtime.h>
56 #include <linux/firmware.h>
59 #include <drm/drm_atomic.h>
60 #include <drm/drm_atomic_uapi.h>
61 #include <drm/drm_atomic_helper.h>
62 #include <drm/drm_dp_mst_helper.h>
63 #include <drm/drm_fb_helper.h>
64 #include <drm/drm_edid.h>
66 #if defined(CONFIG_DRM_AMD_DC_DCN1_0)
67 #include "ivsrcid/irqsrcs_dcn_1_0.h"
69 #include "dcn/dcn_1_0_offset.h"
70 #include "dcn/dcn_1_0_sh_mask.h"
71 #include "soc15_hw_ip.h"
72 #include "vega10_ip_offset.h"
74 #include "soc15_common.h"
77 #include "modules/inc/mod_freesync.h"
78 #include "modules/power/power_helpers.h"
79 #include "modules/inc/mod_info_packet.h"
81 #define FIRMWARE_RAVEN_DMCU "amdgpu/raven_dmcu.bin"
82 MODULE_FIRMWARE(FIRMWARE_RAVEN_DMCU);
87 * The AMDgpu display manager, **amdgpu_dm** (or even simpler,
88 * **dm**) sits between DRM and DC. It acts as a liason, converting DRM
89 * requests into DC requests, and DC responses into DRM responses.
91 * The root control structure is &struct amdgpu_display_manager.
94 /* basic init/fini API */
95 static int amdgpu_dm_init(struct amdgpu_device *adev);
96 static void amdgpu_dm_fini(struct amdgpu_device *adev);
99 * initializes drm_device display related structures, based on the information
100 * provided by DAL. The drm strcutures are: drm_crtc, drm_connector,
101 * drm_encoder, drm_mode_config
103 * Returns 0 on success
105 static int amdgpu_dm_initialize_drm_device(struct amdgpu_device *adev);
106 /* removes and deallocates the drm structures, created by the above function */
107 static void amdgpu_dm_destroy_drm_device(struct amdgpu_display_manager *dm);
110 amdgpu_dm_update_connector_after_detect(struct amdgpu_dm_connector *aconnector);
112 static int amdgpu_dm_plane_init(struct amdgpu_display_manager *dm,
113 struct drm_plane *plane,
114 unsigned long possible_crtcs);
115 static int amdgpu_dm_crtc_init(struct amdgpu_display_manager *dm,
116 struct drm_plane *plane,
117 uint32_t link_index);
118 static int amdgpu_dm_connector_init(struct amdgpu_display_manager *dm,
119 struct amdgpu_dm_connector *amdgpu_dm_connector,
121 struct amdgpu_encoder *amdgpu_encoder);
122 static int amdgpu_dm_encoder_init(struct drm_device *dev,
123 struct amdgpu_encoder *aencoder,
124 uint32_t link_index);
126 static int amdgpu_dm_connector_get_modes(struct drm_connector *connector);
128 static int amdgpu_dm_atomic_commit(struct drm_device *dev,
129 struct drm_atomic_state *state,
132 static void amdgpu_dm_atomic_commit_tail(struct drm_atomic_state *state);
134 static int amdgpu_dm_atomic_check(struct drm_device *dev,
135 struct drm_atomic_state *state);
137 static void handle_cursor_update(struct drm_plane *plane,
138 struct drm_plane_state *old_plane_state);
142 static const enum drm_plane_type dm_plane_type_default[AMDGPU_MAX_PLANES] = {
143 DRM_PLANE_TYPE_PRIMARY,
144 DRM_PLANE_TYPE_PRIMARY,
145 DRM_PLANE_TYPE_PRIMARY,
146 DRM_PLANE_TYPE_PRIMARY,
147 DRM_PLANE_TYPE_PRIMARY,
148 DRM_PLANE_TYPE_PRIMARY,
151 static const enum drm_plane_type dm_plane_type_carizzo[AMDGPU_MAX_PLANES] = {
152 DRM_PLANE_TYPE_PRIMARY,
153 DRM_PLANE_TYPE_PRIMARY,
154 DRM_PLANE_TYPE_PRIMARY,
155 DRM_PLANE_TYPE_OVERLAY,/* YUV Capable Underlay */
158 static const enum drm_plane_type dm_plane_type_stoney[AMDGPU_MAX_PLANES] = {
159 DRM_PLANE_TYPE_PRIMARY,
160 DRM_PLANE_TYPE_PRIMARY,
161 DRM_PLANE_TYPE_OVERLAY, /* YUV Capable Underlay */
165 * dm_vblank_get_counter
168 * Get counter for number of vertical blanks
171 * struct amdgpu_device *adev - [in] desired amdgpu device
172 * int disp_idx - [in] which CRTC to get the counter from
175 * Counter for vertical blanks
177 static u32 dm_vblank_get_counter(struct amdgpu_device *adev, int crtc)
179 if (crtc >= adev->mode_info.num_crtc)
182 struct amdgpu_crtc *acrtc = adev->mode_info.crtcs[crtc];
183 struct dm_crtc_state *acrtc_state = to_dm_crtc_state(
187 if (acrtc_state->stream == NULL) {
188 DRM_ERROR("dc_stream_state is NULL for crtc '%d'!\n",
193 return dc_stream_get_vblank_counter(acrtc_state->stream);
197 static int dm_crtc_get_scanoutpos(struct amdgpu_device *adev, int crtc,
198 u32 *vbl, u32 *position)
200 uint32_t v_blank_start, v_blank_end, h_position, v_position;
202 if ((crtc < 0) || (crtc >= adev->mode_info.num_crtc))
205 struct amdgpu_crtc *acrtc = adev->mode_info.crtcs[crtc];
206 struct dm_crtc_state *acrtc_state = to_dm_crtc_state(
209 if (acrtc_state->stream == NULL) {
210 DRM_ERROR("dc_stream_state is NULL for crtc '%d'!\n",
216 * TODO rework base driver to use values directly.
217 * for now parse it back into reg-format
219 dc_stream_get_scanoutpos(acrtc_state->stream,
225 *position = v_position | (h_position << 16);
226 *vbl = v_blank_start | (v_blank_end << 16);
232 static bool dm_is_idle(void *handle)
238 static int dm_wait_for_idle(void *handle)
244 static bool dm_check_soft_reset(void *handle)
249 static int dm_soft_reset(void *handle)
255 static struct amdgpu_crtc *
256 get_crtc_by_otg_inst(struct amdgpu_device *adev,
259 struct drm_device *dev = adev->ddev;
260 struct drm_crtc *crtc;
261 struct amdgpu_crtc *amdgpu_crtc;
263 if (otg_inst == -1) {
265 return adev->mode_info.crtcs[0];
268 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
269 amdgpu_crtc = to_amdgpu_crtc(crtc);
271 if (amdgpu_crtc->otg_inst == otg_inst)
278 static void dm_pflip_high_irq(void *interrupt_params)
280 struct amdgpu_crtc *amdgpu_crtc;
281 struct common_irq_params *irq_params = interrupt_params;
282 struct amdgpu_device *adev = irq_params->adev;
285 amdgpu_crtc = get_crtc_by_otg_inst(adev, irq_params->irq_src - IRQ_TYPE_PFLIP);
287 /* IRQ could occur when in initial stage */
288 /* TODO work and BO cleanup */
289 if (amdgpu_crtc == NULL) {
290 DRM_DEBUG_DRIVER("CRTC is null, returning.\n");
294 spin_lock_irqsave(&adev->ddev->event_lock, flags);
296 if (amdgpu_crtc->pflip_status != AMDGPU_FLIP_SUBMITTED){
297 DRM_DEBUG_DRIVER("amdgpu_crtc->pflip_status = %d !=AMDGPU_FLIP_SUBMITTED(%d) on crtc:%d[%p] \n",
298 amdgpu_crtc->pflip_status,
299 AMDGPU_FLIP_SUBMITTED,
300 amdgpu_crtc->crtc_id,
302 spin_unlock_irqrestore(&adev->ddev->event_lock, flags);
306 /* Update to correct count(s) if racing with vblank irq */
307 amdgpu_crtc->last_flip_vblank = drm_crtc_accurate_vblank_count(&amdgpu_crtc->base);
309 /* wake up userspace */
310 if (amdgpu_crtc->event) {
311 drm_crtc_send_vblank_event(&amdgpu_crtc->base, amdgpu_crtc->event);
313 /* page flip completed. clean up */
314 amdgpu_crtc->event = NULL;
319 amdgpu_crtc->pflip_status = AMDGPU_FLIP_NONE;
320 spin_unlock_irqrestore(&adev->ddev->event_lock, flags);
322 DRM_DEBUG_DRIVER("%s - crtc :%d[%p], pflip_stat:AMDGPU_FLIP_NONE\n",
323 __func__, amdgpu_crtc->crtc_id, amdgpu_crtc);
325 drm_crtc_vblank_put(&amdgpu_crtc->base);
328 static void dm_crtc_high_irq(void *interrupt_params)
330 struct common_irq_params *irq_params = interrupt_params;
331 struct amdgpu_device *adev = irq_params->adev;
332 struct amdgpu_crtc *acrtc;
333 struct dm_crtc_state *acrtc_state;
335 acrtc = get_crtc_by_otg_inst(adev, irq_params->irq_src - IRQ_TYPE_VBLANK);
338 drm_crtc_handle_vblank(&acrtc->base);
339 amdgpu_dm_crtc_handle_crc_irq(&acrtc->base);
341 acrtc_state = to_dm_crtc_state(acrtc->base.state);
343 if (acrtc_state->stream &&
344 acrtc_state->vrr_params.supported &&
345 acrtc_state->freesync_config.state == VRR_STATE_ACTIVE_VARIABLE) {
346 mod_freesync_handle_v_update(
347 adev->dm.freesync_module,
349 &acrtc_state->vrr_params);
351 dc_stream_adjust_vmin_vmax(
354 &acrtc_state->vrr_params.adjust);
359 static int dm_set_clockgating_state(void *handle,
360 enum amd_clockgating_state state)
365 static int dm_set_powergating_state(void *handle,
366 enum amd_powergating_state state)
371 /* Prototypes of private functions */
372 static int dm_early_init(void* handle);
374 /* Allocate memory for FBC compressed data */
375 static void amdgpu_dm_fbc_init(struct drm_connector *connector)
377 struct drm_device *dev = connector->dev;
378 struct amdgpu_device *adev = dev->dev_private;
379 struct dm_comressor_info *compressor = &adev->dm.compressor;
380 struct amdgpu_dm_connector *aconn = to_amdgpu_dm_connector(connector);
381 struct drm_display_mode *mode;
382 unsigned long max_size = 0;
384 if (adev->dm.dc->fbc_compressor == NULL)
387 if (aconn->dc_link->connector_signal != SIGNAL_TYPE_EDP)
390 if (compressor->bo_ptr)
394 list_for_each_entry(mode, &connector->modes, head) {
395 if (max_size < mode->htotal * mode->vtotal)
396 max_size = mode->htotal * mode->vtotal;
400 int r = amdgpu_bo_create_kernel(adev, max_size * 4, PAGE_SIZE,
401 AMDGPU_GEM_DOMAIN_GTT, &compressor->bo_ptr,
402 &compressor->gpu_addr, &compressor->cpu_addr);
405 DRM_ERROR("DM: Failed to initialize FBC\n");
407 adev->dm.dc->ctx->fbc_gpu_addr = compressor->gpu_addr;
408 DRM_INFO("DM: FBC alloc %lu\n", max_size*4);
415 static int amdgpu_dm_init(struct amdgpu_device *adev)
417 struct dc_init_data init_data;
418 adev->dm.ddev = adev->ddev;
419 adev->dm.adev = adev;
421 /* Zero all the fields */
422 memset(&init_data, 0, sizeof(init_data));
424 mutex_init(&adev->dm.dc_lock);
426 if(amdgpu_dm_irq_init(adev)) {
427 DRM_ERROR("amdgpu: failed to initialize DM IRQ support.\n");
431 init_data.asic_id.chip_family = adev->family;
433 init_data.asic_id.pci_revision_id = adev->rev_id;
434 init_data.asic_id.hw_internal_rev = adev->external_rev_id;
436 init_data.asic_id.vram_width = adev->gmc.vram_width;
437 /* TODO: initialize init_data.asic_id.vram_type here!!!! */
438 init_data.asic_id.atombios_base_address =
439 adev->mode_info.atom_context->bios;
441 init_data.driver = adev;
443 adev->dm.cgs_device = amdgpu_cgs_create_device(adev);
445 if (!adev->dm.cgs_device) {
446 DRM_ERROR("amdgpu: failed to create cgs device.\n");
450 init_data.cgs_device = adev->dm.cgs_device;
452 init_data.dce_environment = DCE_ENV_PRODUCTION_DRV;
455 * TODO debug why this doesn't work on Raven
457 if (adev->flags & AMD_IS_APU &&
458 adev->asic_type >= CHIP_CARRIZO &&
459 adev->asic_type < CHIP_RAVEN)
460 init_data.flags.gpu_vm_support = true;
462 if (amdgpu_dc_feature_mask & DC_FBC_MASK)
463 init_data.flags.fbc_support = true;
465 /* Display Core create. */
466 adev->dm.dc = dc_create(&init_data);
469 DRM_INFO("Display Core initialized with v%s!\n", DC_VER);
471 DRM_INFO("Display Core failed to initialize with v%s!\n", DC_VER);
475 adev->dm.freesync_module = mod_freesync_create(adev->dm.dc);
476 if (!adev->dm.freesync_module) {
478 "amdgpu: failed to initialize freesync_module.\n");
480 DRM_DEBUG_DRIVER("amdgpu: freesync_module init done %p.\n",
481 adev->dm.freesync_module);
483 amdgpu_dm_init_color_mod();
485 if (amdgpu_dm_initialize_drm_device(adev)) {
487 "amdgpu: failed to initialize sw for display support.\n");
491 /* Update the actual used number of crtc */
492 adev->mode_info.num_crtc = adev->dm.display_indexes_num;
494 /* TODO: Add_display_info? */
496 /* TODO use dynamic cursor width */
497 adev->ddev->mode_config.cursor_width = adev->dm.dc->caps.max_cursor_size;
498 adev->ddev->mode_config.cursor_height = adev->dm.dc->caps.max_cursor_size;
500 if (drm_vblank_init(adev->ddev, adev->dm.display_indexes_num)) {
502 "amdgpu: failed to initialize sw for display support.\n");
506 #if defined(CONFIG_DEBUG_FS)
507 if (dtn_debugfs_init(adev))
508 DRM_ERROR("amdgpu: failed initialize dtn debugfs support.\n");
511 DRM_DEBUG_DRIVER("KMS initialized.\n");
515 amdgpu_dm_fini(adev);
520 static void amdgpu_dm_fini(struct amdgpu_device *adev)
522 amdgpu_dm_destroy_drm_device(&adev->dm);
524 * TODO: pageflip, vlank interrupt
526 * amdgpu_dm_irq_fini(adev);
529 if (adev->dm.cgs_device) {
530 amdgpu_cgs_destroy_device(adev->dm.cgs_device);
531 adev->dm.cgs_device = NULL;
533 if (adev->dm.freesync_module) {
534 mod_freesync_destroy(adev->dm.freesync_module);
535 adev->dm.freesync_module = NULL;
537 /* DC Destroy TODO: Replace destroy DAL */
539 dc_destroy(&adev->dm.dc);
541 mutex_destroy(&adev->dm.dc_lock);
546 static int load_dmcu_fw(struct amdgpu_device *adev)
548 const char *fw_name_dmcu;
550 const struct dmcu_firmware_header_v1_0 *hdr;
552 switch(adev->asic_type) {
571 fw_name_dmcu = FIRMWARE_RAVEN_DMCU;
574 DRM_ERROR("Unsupported ASIC type: 0x%X\n", adev->asic_type);
578 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) {
579 DRM_DEBUG_KMS("dm: DMCU firmware not supported on direct or SMU loading\n");
583 r = request_firmware_direct(&adev->dm.fw_dmcu, fw_name_dmcu, adev->dev);
585 /* DMCU firmware is not necessary, so don't raise a fuss if it's missing */
586 DRM_DEBUG_KMS("dm: DMCU firmware not found\n");
587 adev->dm.fw_dmcu = NULL;
591 dev_err(adev->dev, "amdgpu_dm: Can't load firmware \"%s\"\n",
596 r = amdgpu_ucode_validate(adev->dm.fw_dmcu);
598 dev_err(adev->dev, "amdgpu_dm: Can't validate firmware \"%s\"\n",
600 release_firmware(adev->dm.fw_dmcu);
601 adev->dm.fw_dmcu = NULL;
605 hdr = (const struct dmcu_firmware_header_v1_0 *)adev->dm.fw_dmcu->data;
606 adev->firmware.ucode[AMDGPU_UCODE_ID_DMCU_ERAM].ucode_id = AMDGPU_UCODE_ID_DMCU_ERAM;
607 adev->firmware.ucode[AMDGPU_UCODE_ID_DMCU_ERAM].fw = adev->dm.fw_dmcu;
608 adev->firmware.fw_size +=
609 ALIGN(le32_to_cpu(hdr->header.ucode_size_bytes) - le32_to_cpu(hdr->intv_size_bytes), PAGE_SIZE);
611 adev->firmware.ucode[AMDGPU_UCODE_ID_DMCU_INTV].ucode_id = AMDGPU_UCODE_ID_DMCU_INTV;
612 adev->firmware.ucode[AMDGPU_UCODE_ID_DMCU_INTV].fw = adev->dm.fw_dmcu;
613 adev->firmware.fw_size +=
614 ALIGN(le32_to_cpu(hdr->intv_size_bytes), PAGE_SIZE);
616 adev->dm.dmcu_fw_version = le32_to_cpu(hdr->header.ucode_version);
618 DRM_DEBUG_KMS("PSP loading DMCU firmware\n");
623 static int dm_sw_init(void *handle)
625 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
627 return load_dmcu_fw(adev);
630 static int dm_sw_fini(void *handle)
632 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
634 if(adev->dm.fw_dmcu) {
635 release_firmware(adev->dm.fw_dmcu);
636 adev->dm.fw_dmcu = NULL;
642 static int detect_mst_link_for_all_connectors(struct drm_device *dev)
644 struct amdgpu_dm_connector *aconnector;
645 struct drm_connector *connector;
648 drm_modeset_lock(&dev->mode_config.connection_mutex, NULL);
650 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
651 aconnector = to_amdgpu_dm_connector(connector);
652 if (aconnector->dc_link->type == dc_connection_mst_branch &&
653 aconnector->mst_mgr.aux) {
654 DRM_DEBUG_DRIVER("DM_MST: starting TM on aconnector: %p [id: %d]\n",
655 aconnector, aconnector->base.base.id);
657 ret = drm_dp_mst_topology_mgr_set_mst(&aconnector->mst_mgr, true);
659 DRM_ERROR("DM_MST: Failed to start MST\n");
660 ((struct dc_link *)aconnector->dc_link)->type = dc_connection_single;
666 drm_modeset_unlock(&dev->mode_config.connection_mutex);
670 static int dm_late_init(void *handle)
672 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
674 struct dmcu_iram_parameters params;
675 unsigned int linear_lut[16];
677 struct dmcu *dmcu = adev->dm.dc->res_pool->dmcu;
680 for (i = 0; i < 16; i++)
681 linear_lut[i] = 0xFFFF * i / 15;
684 params.backlight_ramping_start = 0xCCCC;
685 params.backlight_ramping_reduction = 0xCCCCCCCC;
686 params.backlight_lut_array_size = 16;
687 params.backlight_lut_array = linear_lut;
689 ret = dmcu_load_iram(dmcu, params);
694 return detect_mst_link_for_all_connectors(adev->ddev);
697 static void s3_handle_mst(struct drm_device *dev, bool suspend)
699 struct amdgpu_dm_connector *aconnector;
700 struct drm_connector *connector;
701 struct drm_dp_mst_topology_mgr *mgr;
703 bool need_hotplug = false;
705 drm_modeset_lock(&dev->mode_config.connection_mutex, NULL);
707 list_for_each_entry(connector, &dev->mode_config.connector_list,
709 aconnector = to_amdgpu_dm_connector(connector);
710 if (aconnector->dc_link->type != dc_connection_mst_branch ||
711 aconnector->mst_port)
714 mgr = &aconnector->mst_mgr;
717 drm_dp_mst_topology_mgr_suspend(mgr);
719 ret = drm_dp_mst_topology_mgr_resume(mgr);
721 drm_dp_mst_topology_mgr_set_mst(mgr, false);
727 drm_modeset_unlock(&dev->mode_config.connection_mutex);
730 drm_kms_helper_hotplug_event(dev);
734 * dm_hw_init() - Initialize DC device
735 * @handle: The base driver device containing the amdpgu_dm device.
737 * Initialize the &struct amdgpu_display_manager device. This involves calling
738 * the initializers of each DM component, then populating the struct with them.
740 * Although the function implies hardware initialization, both hardware and
741 * software are initialized here. Splitting them out to their relevant init
742 * hooks is a future TODO item.
744 * Some notable things that are initialized here:
746 * - Display Core, both software and hardware
747 * - DC modules that we need (freesync and color management)
748 * - DRM software states
749 * - Interrupt sources and handlers
751 * - Debug FS entries, if enabled
753 static int dm_hw_init(void *handle)
755 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
756 /* Create DAL display manager */
757 amdgpu_dm_init(adev);
758 amdgpu_dm_hpd_init(adev);
764 * dm_hw_fini() - Teardown DC device
765 * @handle: The base driver device containing the amdpgu_dm device.
767 * Teardown components within &struct amdgpu_display_manager that require
768 * cleanup. This involves cleaning up the DRM device, DC, and any modules that
769 * were loaded. Also flush IRQ workqueues and disable them.
771 static int dm_hw_fini(void *handle)
773 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
775 amdgpu_dm_hpd_fini(adev);
777 amdgpu_dm_irq_fini(adev);
778 amdgpu_dm_fini(adev);
782 static int dm_suspend(void *handle)
784 struct amdgpu_device *adev = handle;
785 struct amdgpu_display_manager *dm = &adev->dm;
788 WARN_ON(adev->dm.cached_state);
789 adev->dm.cached_state = drm_atomic_helper_suspend(adev->ddev);
791 s3_handle_mst(adev->ddev, true);
793 amdgpu_dm_irq_suspend(adev);
796 dc_set_power_state(dm->dc, DC_ACPI_CM_POWER_STATE_D3);
801 static struct amdgpu_dm_connector *
802 amdgpu_dm_find_first_crtc_matching_connector(struct drm_atomic_state *state,
803 struct drm_crtc *crtc)
806 struct drm_connector_state *new_con_state;
807 struct drm_connector *connector;
808 struct drm_crtc *crtc_from_state;
810 for_each_new_connector_in_state(state, connector, new_con_state, i) {
811 crtc_from_state = new_con_state->crtc;
813 if (crtc_from_state == crtc)
814 return to_amdgpu_dm_connector(connector);
820 static void emulated_link_detect(struct dc_link *link)
822 struct dc_sink_init_data sink_init_data = { 0 };
823 struct display_sink_capability sink_caps = { 0 };
824 enum dc_edid_status edid_status;
825 struct dc_context *dc_ctx = link->ctx;
826 struct dc_sink *sink = NULL;
827 struct dc_sink *prev_sink = NULL;
829 link->type = dc_connection_none;
830 prev_sink = link->local_sink;
832 if (prev_sink != NULL)
833 dc_sink_retain(prev_sink);
835 switch (link->connector_signal) {
836 case SIGNAL_TYPE_HDMI_TYPE_A: {
837 sink_caps.transaction_type = DDC_TRANSACTION_TYPE_I2C;
838 sink_caps.signal = SIGNAL_TYPE_HDMI_TYPE_A;
842 case SIGNAL_TYPE_DVI_SINGLE_LINK: {
843 sink_caps.transaction_type = DDC_TRANSACTION_TYPE_I2C;
844 sink_caps.signal = SIGNAL_TYPE_DVI_SINGLE_LINK;
848 case SIGNAL_TYPE_DVI_DUAL_LINK: {
849 sink_caps.transaction_type = DDC_TRANSACTION_TYPE_I2C;
850 sink_caps.signal = SIGNAL_TYPE_DVI_DUAL_LINK;
854 case SIGNAL_TYPE_LVDS: {
855 sink_caps.transaction_type = DDC_TRANSACTION_TYPE_I2C;
856 sink_caps.signal = SIGNAL_TYPE_LVDS;
860 case SIGNAL_TYPE_EDP: {
861 sink_caps.transaction_type =
862 DDC_TRANSACTION_TYPE_I2C_OVER_AUX;
863 sink_caps.signal = SIGNAL_TYPE_EDP;
867 case SIGNAL_TYPE_DISPLAY_PORT: {
868 sink_caps.transaction_type =
869 DDC_TRANSACTION_TYPE_I2C_OVER_AUX;
870 sink_caps.signal = SIGNAL_TYPE_VIRTUAL;
875 DC_ERROR("Invalid connector type! signal:%d\n",
876 link->connector_signal);
880 sink_init_data.link = link;
881 sink_init_data.sink_signal = sink_caps.signal;
883 sink = dc_sink_create(&sink_init_data);
885 DC_ERROR("Failed to create sink!\n");
889 /* dc_sink_create returns a new reference */
890 link->local_sink = sink;
892 edid_status = dm_helpers_read_local_edid(
897 if (edid_status != EDID_OK)
898 DC_ERROR("Failed to read EDID");
902 static int dm_resume(void *handle)
904 struct amdgpu_device *adev = handle;
905 struct drm_device *ddev = adev->ddev;
906 struct amdgpu_display_manager *dm = &adev->dm;
907 struct amdgpu_dm_connector *aconnector;
908 struct drm_connector *connector;
909 struct drm_crtc *crtc;
910 struct drm_crtc_state *new_crtc_state;
911 struct dm_crtc_state *dm_new_crtc_state;
912 struct drm_plane *plane;
913 struct drm_plane_state *new_plane_state;
914 struct dm_plane_state *dm_new_plane_state;
915 enum dc_connection_type new_connection_type = dc_connection_none;
918 /* power on hardware */
919 dc_set_power_state(dm->dc, DC_ACPI_CM_POWER_STATE_D0);
921 /* program HPD filter */
924 /* On resume we need to rewrite the MSTM control bits to enamble MST*/
925 s3_handle_mst(ddev, false);
928 * early enable HPD Rx IRQ, should be done before set mode as short
929 * pulse interrupts are used for MST
931 amdgpu_dm_irq_resume_early(adev);
934 list_for_each_entry(connector, &ddev->mode_config.connector_list, head) {
935 aconnector = to_amdgpu_dm_connector(connector);
938 * this is the case when traversing through already created
939 * MST connectors, should be skipped
941 if (aconnector->mst_port)
944 mutex_lock(&aconnector->hpd_lock);
945 if (!dc_link_detect_sink(aconnector->dc_link, &new_connection_type))
946 DRM_ERROR("KMS: Failed to detect connector\n");
948 if (aconnector->base.force && new_connection_type == dc_connection_none)
949 emulated_link_detect(aconnector->dc_link);
951 dc_link_detect(aconnector->dc_link, DETECT_REASON_HPD);
953 if (aconnector->fake_enable && aconnector->dc_link->local_sink)
954 aconnector->fake_enable = false;
956 if (aconnector->dc_sink)
957 dc_sink_release(aconnector->dc_sink);
958 aconnector->dc_sink = NULL;
959 amdgpu_dm_update_connector_after_detect(aconnector);
960 mutex_unlock(&aconnector->hpd_lock);
963 /* Force mode set in atomic commit */
964 for_each_new_crtc_in_state(dm->cached_state, crtc, new_crtc_state, i)
965 new_crtc_state->active_changed = true;
968 * atomic_check is expected to create the dc states. We need to release
969 * them here, since they were duplicated as part of the suspend
972 for_each_new_crtc_in_state(dm->cached_state, crtc, new_crtc_state, i) {
973 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
974 if (dm_new_crtc_state->stream) {
975 WARN_ON(kref_read(&dm_new_crtc_state->stream->refcount) > 1);
976 dc_stream_release(dm_new_crtc_state->stream);
977 dm_new_crtc_state->stream = NULL;
981 for_each_new_plane_in_state(dm->cached_state, plane, new_plane_state, i) {
982 dm_new_plane_state = to_dm_plane_state(new_plane_state);
983 if (dm_new_plane_state->dc_state) {
984 WARN_ON(kref_read(&dm_new_plane_state->dc_state->refcount) > 1);
985 dc_plane_state_release(dm_new_plane_state->dc_state);
986 dm_new_plane_state->dc_state = NULL;
990 drm_atomic_helper_resume(ddev, dm->cached_state);
992 dm->cached_state = NULL;
994 amdgpu_dm_irq_resume_late(adev);
1002 * DM (and consequently DC) is registered in the amdgpu base driver as a IP
1003 * block. When CONFIG_DRM_AMD_DC is enabled, the DM device IP block is added to
1004 * the base driver's device list to be initialized and torn down accordingly.
1006 * The functions to do so are provided as hooks in &struct amd_ip_funcs.
1009 static const struct amd_ip_funcs amdgpu_dm_funcs = {
1011 .early_init = dm_early_init,
1012 .late_init = dm_late_init,
1013 .sw_init = dm_sw_init,
1014 .sw_fini = dm_sw_fini,
1015 .hw_init = dm_hw_init,
1016 .hw_fini = dm_hw_fini,
1017 .suspend = dm_suspend,
1018 .resume = dm_resume,
1019 .is_idle = dm_is_idle,
1020 .wait_for_idle = dm_wait_for_idle,
1021 .check_soft_reset = dm_check_soft_reset,
1022 .soft_reset = dm_soft_reset,
1023 .set_clockgating_state = dm_set_clockgating_state,
1024 .set_powergating_state = dm_set_powergating_state,
1027 const struct amdgpu_ip_block_version dm_ip_block =
1029 .type = AMD_IP_BLOCK_TYPE_DCE,
1033 .funcs = &amdgpu_dm_funcs,
1043 static const struct drm_mode_config_funcs amdgpu_dm_mode_funcs = {
1044 .fb_create = amdgpu_display_user_framebuffer_create,
1045 .output_poll_changed = drm_fb_helper_output_poll_changed,
1046 .atomic_check = amdgpu_dm_atomic_check,
1047 .atomic_commit = amdgpu_dm_atomic_commit,
1050 static struct drm_mode_config_helper_funcs amdgpu_dm_mode_config_helperfuncs = {
1051 .atomic_commit_tail = amdgpu_dm_atomic_commit_tail
1055 amdgpu_dm_update_connector_after_detect(struct amdgpu_dm_connector *aconnector)
1057 struct drm_connector *connector = &aconnector->base;
1058 struct drm_device *dev = connector->dev;
1059 struct dc_sink *sink;
1061 /* MST handled by drm_mst framework */
1062 if (aconnector->mst_mgr.mst_state == true)
1066 sink = aconnector->dc_link->local_sink;
1068 dc_sink_retain(sink);
1071 * Edid mgmt connector gets first update only in mode_valid hook and then
1072 * the connector sink is set to either fake or physical sink depends on link status.
1073 * Skip if already done during boot.
1075 if (aconnector->base.force != DRM_FORCE_UNSPECIFIED
1076 && aconnector->dc_em_sink) {
1079 * For S3 resume with headless use eml_sink to fake stream
1080 * because on resume connector->sink is set to NULL
1082 mutex_lock(&dev->mode_config.mutex);
1085 if (aconnector->dc_sink) {
1086 amdgpu_dm_update_freesync_caps(connector, NULL);
1088 * retain and release below are used to
1089 * bump up refcount for sink because the link doesn't point
1090 * to it anymore after disconnect, so on next crtc to connector
1091 * reshuffle by UMD we will get into unwanted dc_sink release
1093 dc_sink_release(aconnector->dc_sink);
1095 aconnector->dc_sink = sink;
1096 dc_sink_retain(aconnector->dc_sink);
1097 amdgpu_dm_update_freesync_caps(connector,
1100 amdgpu_dm_update_freesync_caps(connector, NULL);
1101 if (!aconnector->dc_sink) {
1102 aconnector->dc_sink = aconnector->dc_em_sink;
1103 dc_sink_retain(aconnector->dc_sink);
1107 mutex_unlock(&dev->mode_config.mutex);
1110 dc_sink_release(sink);
1115 * TODO: temporary guard to look for proper fix
1116 * if this sink is MST sink, we should not do anything
1118 if (sink && sink->sink_signal == SIGNAL_TYPE_DISPLAY_PORT_MST) {
1119 dc_sink_release(sink);
1123 if (aconnector->dc_sink == sink) {
1125 * We got a DP short pulse (Link Loss, DP CTS, etc...).
1128 DRM_DEBUG_DRIVER("DCHPD: connector_id=%d: dc_sink didn't change.\n",
1129 aconnector->connector_id);
1131 dc_sink_release(sink);
1135 DRM_DEBUG_DRIVER("DCHPD: connector_id=%d: Old sink=%p New sink=%p\n",
1136 aconnector->connector_id, aconnector->dc_sink, sink);
1138 mutex_lock(&dev->mode_config.mutex);
1141 * 1. Update status of the drm connector
1142 * 2. Send an event and let userspace tell us what to do
1146 * TODO: check if we still need the S3 mode update workaround.
1147 * If yes, put it here.
1149 if (aconnector->dc_sink)
1150 amdgpu_dm_update_freesync_caps(connector, NULL);
1152 aconnector->dc_sink = sink;
1153 dc_sink_retain(aconnector->dc_sink);
1154 if (sink->dc_edid.length == 0) {
1155 aconnector->edid = NULL;
1156 drm_dp_cec_unset_edid(&aconnector->dm_dp_aux.aux);
1159 (struct edid *) sink->dc_edid.raw_edid;
1162 drm_connector_update_edid_property(connector,
1164 drm_dp_cec_set_edid(&aconnector->dm_dp_aux.aux,
1167 amdgpu_dm_update_freesync_caps(connector, aconnector->edid);
1170 drm_dp_cec_unset_edid(&aconnector->dm_dp_aux.aux);
1171 amdgpu_dm_update_freesync_caps(connector, NULL);
1172 drm_connector_update_edid_property(connector, NULL);
1173 aconnector->num_modes = 0;
1174 dc_sink_release(aconnector->dc_sink);
1175 aconnector->dc_sink = NULL;
1176 aconnector->edid = NULL;
1179 mutex_unlock(&dev->mode_config.mutex);
1182 dc_sink_release(sink);
1185 static void handle_hpd_irq(void *param)
1187 struct amdgpu_dm_connector *aconnector = (struct amdgpu_dm_connector *)param;
1188 struct drm_connector *connector = &aconnector->base;
1189 struct drm_device *dev = connector->dev;
1190 enum dc_connection_type new_connection_type = dc_connection_none;
1193 * In case of failure or MST no need to update connector status or notify the OS
1194 * since (for MST case) MST does this in its own context.
1196 mutex_lock(&aconnector->hpd_lock);
1198 if (aconnector->fake_enable)
1199 aconnector->fake_enable = false;
1201 if (!dc_link_detect_sink(aconnector->dc_link, &new_connection_type))
1202 DRM_ERROR("KMS: Failed to detect connector\n");
1204 if (aconnector->base.force && new_connection_type == dc_connection_none) {
1205 emulated_link_detect(aconnector->dc_link);
1208 drm_modeset_lock_all(dev);
1209 dm_restore_drm_connector_state(dev, connector);
1210 drm_modeset_unlock_all(dev);
1212 if (aconnector->base.force == DRM_FORCE_UNSPECIFIED)
1213 drm_kms_helper_hotplug_event(dev);
1215 } else if (dc_link_detect(aconnector->dc_link, DETECT_REASON_HPD)) {
1216 amdgpu_dm_update_connector_after_detect(aconnector);
1219 drm_modeset_lock_all(dev);
1220 dm_restore_drm_connector_state(dev, connector);
1221 drm_modeset_unlock_all(dev);
1223 if (aconnector->base.force == DRM_FORCE_UNSPECIFIED)
1224 drm_kms_helper_hotplug_event(dev);
1226 mutex_unlock(&aconnector->hpd_lock);
1230 static void dm_handle_hpd_rx_irq(struct amdgpu_dm_connector *aconnector)
1232 uint8_t esi[DP_PSR_ERROR_STATUS - DP_SINK_COUNT_ESI] = { 0 };
1234 bool new_irq_handled = false;
1236 int dpcd_bytes_to_read;
1238 const int max_process_count = 30;
1239 int process_count = 0;
1241 const struct dc_link_status *link_status = dc_link_get_status(aconnector->dc_link);
1243 if (link_status->dpcd_caps->dpcd_rev.raw < 0x12) {
1244 dpcd_bytes_to_read = DP_LANE0_1_STATUS - DP_SINK_COUNT;
1245 /* DPCD 0x200 - 0x201 for downstream IRQ */
1246 dpcd_addr = DP_SINK_COUNT;
1248 dpcd_bytes_to_read = DP_PSR_ERROR_STATUS - DP_SINK_COUNT_ESI;
1249 /* DPCD 0x2002 - 0x2005 for downstream IRQ */
1250 dpcd_addr = DP_SINK_COUNT_ESI;
1253 dret = drm_dp_dpcd_read(
1254 &aconnector->dm_dp_aux.aux,
1257 dpcd_bytes_to_read);
1259 while (dret == dpcd_bytes_to_read &&
1260 process_count < max_process_count) {
1266 DRM_DEBUG_DRIVER("ESI %02x %02x %02x\n", esi[0], esi[1], esi[2]);
1267 /* handle HPD short pulse irq */
1268 if (aconnector->mst_mgr.mst_state)
1270 &aconnector->mst_mgr,
1274 if (new_irq_handled) {
1275 /* ACK at DPCD to notify down stream */
1276 const int ack_dpcd_bytes_to_write =
1277 dpcd_bytes_to_read - 1;
1279 for (retry = 0; retry < 3; retry++) {
1282 wret = drm_dp_dpcd_write(
1283 &aconnector->dm_dp_aux.aux,
1286 ack_dpcd_bytes_to_write);
1287 if (wret == ack_dpcd_bytes_to_write)
1291 /* check if there is new irq to be handled */
1292 dret = drm_dp_dpcd_read(
1293 &aconnector->dm_dp_aux.aux,
1296 dpcd_bytes_to_read);
1298 new_irq_handled = false;
1304 if (process_count == max_process_count)
1305 DRM_DEBUG_DRIVER("Loop exceeded max iterations\n");
1308 static void handle_hpd_rx_irq(void *param)
1310 struct amdgpu_dm_connector *aconnector = (struct amdgpu_dm_connector *)param;
1311 struct drm_connector *connector = &aconnector->base;
1312 struct drm_device *dev = connector->dev;
1313 struct dc_link *dc_link = aconnector->dc_link;
1314 bool is_mst_root_connector = aconnector->mst_mgr.mst_state;
1315 enum dc_connection_type new_connection_type = dc_connection_none;
1318 * TODO:Temporary add mutex to protect hpd interrupt not have a gpio
1319 * conflict, after implement i2c helper, this mutex should be
1322 if (dc_link->type != dc_connection_mst_branch)
1323 mutex_lock(&aconnector->hpd_lock);
1325 if (dc_link_handle_hpd_rx_irq(dc_link, NULL, NULL) &&
1326 !is_mst_root_connector) {
1327 /* Downstream Port status changed. */
1328 if (!dc_link_detect_sink(dc_link, &new_connection_type))
1329 DRM_ERROR("KMS: Failed to detect connector\n");
1331 if (aconnector->base.force && new_connection_type == dc_connection_none) {
1332 emulated_link_detect(dc_link);
1334 if (aconnector->fake_enable)
1335 aconnector->fake_enable = false;
1337 amdgpu_dm_update_connector_after_detect(aconnector);
1340 drm_modeset_lock_all(dev);
1341 dm_restore_drm_connector_state(dev, connector);
1342 drm_modeset_unlock_all(dev);
1344 drm_kms_helper_hotplug_event(dev);
1345 } else if (dc_link_detect(dc_link, DETECT_REASON_HPDRX)) {
1347 if (aconnector->fake_enable)
1348 aconnector->fake_enable = false;
1350 amdgpu_dm_update_connector_after_detect(aconnector);
1353 drm_modeset_lock_all(dev);
1354 dm_restore_drm_connector_state(dev, connector);
1355 drm_modeset_unlock_all(dev);
1357 drm_kms_helper_hotplug_event(dev);
1360 if ((dc_link->cur_link_settings.lane_count != LANE_COUNT_UNKNOWN) ||
1361 (dc_link->type == dc_connection_mst_branch))
1362 dm_handle_hpd_rx_irq(aconnector);
1364 if (dc_link->type != dc_connection_mst_branch) {
1365 drm_dp_cec_irq(&aconnector->dm_dp_aux.aux);
1366 mutex_unlock(&aconnector->hpd_lock);
1370 static void register_hpd_handlers(struct amdgpu_device *adev)
1372 struct drm_device *dev = adev->ddev;
1373 struct drm_connector *connector;
1374 struct amdgpu_dm_connector *aconnector;
1375 const struct dc_link *dc_link;
1376 struct dc_interrupt_params int_params = {0};
1378 int_params.requested_polarity = INTERRUPT_POLARITY_DEFAULT;
1379 int_params.current_polarity = INTERRUPT_POLARITY_DEFAULT;
1381 list_for_each_entry(connector,
1382 &dev->mode_config.connector_list, head) {
1384 aconnector = to_amdgpu_dm_connector(connector);
1385 dc_link = aconnector->dc_link;
1387 if (DC_IRQ_SOURCE_INVALID != dc_link->irq_source_hpd) {
1388 int_params.int_context = INTERRUPT_LOW_IRQ_CONTEXT;
1389 int_params.irq_source = dc_link->irq_source_hpd;
1391 amdgpu_dm_irq_register_interrupt(adev, &int_params,
1393 (void *) aconnector);
1396 if (DC_IRQ_SOURCE_INVALID != dc_link->irq_source_hpd_rx) {
1398 /* Also register for DP short pulse (hpd_rx). */
1399 int_params.int_context = INTERRUPT_LOW_IRQ_CONTEXT;
1400 int_params.irq_source = dc_link->irq_source_hpd_rx;
1402 amdgpu_dm_irq_register_interrupt(adev, &int_params,
1404 (void *) aconnector);
1409 /* Register IRQ sources and initialize IRQ callbacks */
1410 static int dce110_register_irq_handlers(struct amdgpu_device *adev)
1412 struct dc *dc = adev->dm.dc;
1413 struct common_irq_params *c_irq_params;
1414 struct dc_interrupt_params int_params = {0};
1417 unsigned client_id = AMDGPU_IRQ_CLIENTID_LEGACY;
1419 if (adev->asic_type == CHIP_VEGA10 ||
1420 adev->asic_type == CHIP_VEGA12 ||
1421 adev->asic_type == CHIP_VEGA20 ||
1422 adev->asic_type == CHIP_RAVEN)
1423 client_id = SOC15_IH_CLIENTID_DCE;
1425 int_params.requested_polarity = INTERRUPT_POLARITY_DEFAULT;
1426 int_params.current_polarity = INTERRUPT_POLARITY_DEFAULT;
1429 * Actions of amdgpu_irq_add_id():
1430 * 1. Register a set() function with base driver.
1431 * Base driver will call set() function to enable/disable an
1432 * interrupt in DC hardware.
1433 * 2. Register amdgpu_dm_irq_handler().
1434 * Base driver will call amdgpu_dm_irq_handler() for ALL interrupts
1435 * coming from DC hardware.
1436 * amdgpu_dm_irq_handler() will re-direct the interrupt to DC
1437 * for acknowledging and handling. */
1439 /* Use VBLANK interrupt */
1440 for (i = VISLANDS30_IV_SRCID_D1_VERTICAL_INTERRUPT0; i <= VISLANDS30_IV_SRCID_D6_VERTICAL_INTERRUPT0; i++) {
1441 r = amdgpu_irq_add_id(adev, client_id, i, &adev->crtc_irq);
1443 DRM_ERROR("Failed to add crtc irq id!\n");
1447 int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT;
1448 int_params.irq_source =
1449 dc_interrupt_to_irq_source(dc, i, 0);
1451 c_irq_params = &adev->dm.vblank_params[int_params.irq_source - DC_IRQ_SOURCE_VBLANK1];
1453 c_irq_params->adev = adev;
1454 c_irq_params->irq_src = int_params.irq_source;
1456 amdgpu_dm_irq_register_interrupt(adev, &int_params,
1457 dm_crtc_high_irq, c_irq_params);
1460 /* Use GRPH_PFLIP interrupt */
1461 for (i = VISLANDS30_IV_SRCID_D1_GRPH_PFLIP;
1462 i <= VISLANDS30_IV_SRCID_D6_GRPH_PFLIP; i += 2) {
1463 r = amdgpu_irq_add_id(adev, client_id, i, &adev->pageflip_irq);
1465 DRM_ERROR("Failed to add page flip irq id!\n");
1469 int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT;
1470 int_params.irq_source =
1471 dc_interrupt_to_irq_source(dc, i, 0);
1473 c_irq_params = &adev->dm.pflip_params[int_params.irq_source - DC_IRQ_SOURCE_PFLIP_FIRST];
1475 c_irq_params->adev = adev;
1476 c_irq_params->irq_src = int_params.irq_source;
1478 amdgpu_dm_irq_register_interrupt(adev, &int_params,
1479 dm_pflip_high_irq, c_irq_params);
1484 r = amdgpu_irq_add_id(adev, client_id,
1485 VISLANDS30_IV_SRCID_HOTPLUG_DETECT_A, &adev->hpd_irq);
1487 DRM_ERROR("Failed to add hpd irq id!\n");
1491 register_hpd_handlers(adev);
1496 #if defined(CONFIG_DRM_AMD_DC_DCN1_0)
1497 /* Register IRQ sources and initialize IRQ callbacks */
1498 static int dcn10_register_irq_handlers(struct amdgpu_device *adev)
1500 struct dc *dc = adev->dm.dc;
1501 struct common_irq_params *c_irq_params;
1502 struct dc_interrupt_params int_params = {0};
1506 int_params.requested_polarity = INTERRUPT_POLARITY_DEFAULT;
1507 int_params.current_polarity = INTERRUPT_POLARITY_DEFAULT;
1510 * Actions of amdgpu_irq_add_id():
1511 * 1. Register a set() function with base driver.
1512 * Base driver will call set() function to enable/disable an
1513 * interrupt in DC hardware.
1514 * 2. Register amdgpu_dm_irq_handler().
1515 * Base driver will call amdgpu_dm_irq_handler() for ALL interrupts
1516 * coming from DC hardware.
1517 * amdgpu_dm_irq_handler() will re-direct the interrupt to DC
1518 * for acknowledging and handling.
1521 /* Use VSTARTUP interrupt */
1522 for (i = DCN_1_0__SRCID__DC_D1_OTG_VSTARTUP;
1523 i <= DCN_1_0__SRCID__DC_D1_OTG_VSTARTUP + adev->mode_info.num_crtc - 1;
1525 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_DCE, i, &adev->crtc_irq);
1528 DRM_ERROR("Failed to add crtc irq id!\n");
1532 int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT;
1533 int_params.irq_source =
1534 dc_interrupt_to_irq_source(dc, i, 0);
1536 c_irq_params = &adev->dm.vblank_params[int_params.irq_source - DC_IRQ_SOURCE_VBLANK1];
1538 c_irq_params->adev = adev;
1539 c_irq_params->irq_src = int_params.irq_source;
1541 amdgpu_dm_irq_register_interrupt(adev, &int_params,
1542 dm_crtc_high_irq, c_irq_params);
1545 /* Use GRPH_PFLIP interrupt */
1546 for (i = DCN_1_0__SRCID__HUBP0_FLIP_INTERRUPT;
1547 i <= DCN_1_0__SRCID__HUBP0_FLIP_INTERRUPT + adev->mode_info.num_crtc - 1;
1549 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_DCE, i, &adev->pageflip_irq);
1551 DRM_ERROR("Failed to add page flip irq id!\n");
1555 int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT;
1556 int_params.irq_source =
1557 dc_interrupt_to_irq_source(dc, i, 0);
1559 c_irq_params = &adev->dm.pflip_params[int_params.irq_source - DC_IRQ_SOURCE_PFLIP_FIRST];
1561 c_irq_params->adev = adev;
1562 c_irq_params->irq_src = int_params.irq_source;
1564 amdgpu_dm_irq_register_interrupt(adev, &int_params,
1565 dm_pflip_high_irq, c_irq_params);
1570 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_DCE, DCN_1_0__SRCID__DC_HPD1_INT,
1573 DRM_ERROR("Failed to add hpd irq id!\n");
1577 register_hpd_handlers(adev);
1584 * Acquires the lock for the atomic state object and returns
1585 * the new atomic state.
1587 * This should only be called during atomic check.
1589 static int dm_atomic_get_state(struct drm_atomic_state *state,
1590 struct dm_atomic_state **dm_state)
1592 struct drm_device *dev = state->dev;
1593 struct amdgpu_device *adev = dev->dev_private;
1594 struct amdgpu_display_manager *dm = &adev->dm;
1595 struct drm_private_state *priv_state;
1601 ret = drm_modeset_lock(&dm->atomic_obj_lock, state->acquire_ctx);
1605 priv_state = drm_atomic_get_private_obj_state(state, &dm->atomic_obj);
1606 if (IS_ERR(priv_state))
1607 return PTR_ERR(priv_state);
1609 *dm_state = to_dm_atomic_state(priv_state);
1614 struct dm_atomic_state *
1615 dm_atomic_get_new_state(struct drm_atomic_state *state)
1617 struct drm_device *dev = state->dev;
1618 struct amdgpu_device *adev = dev->dev_private;
1619 struct amdgpu_display_manager *dm = &adev->dm;
1620 struct drm_private_obj *obj;
1621 struct drm_private_state *new_obj_state;
1624 for_each_new_private_obj_in_state(state, obj, new_obj_state, i) {
1625 if (obj->funcs == dm->atomic_obj.funcs)
1626 return to_dm_atomic_state(new_obj_state);
1632 struct dm_atomic_state *
1633 dm_atomic_get_old_state(struct drm_atomic_state *state)
1635 struct drm_device *dev = state->dev;
1636 struct amdgpu_device *adev = dev->dev_private;
1637 struct amdgpu_display_manager *dm = &adev->dm;
1638 struct drm_private_obj *obj;
1639 struct drm_private_state *old_obj_state;
1642 for_each_old_private_obj_in_state(state, obj, old_obj_state, i) {
1643 if (obj->funcs == dm->atomic_obj.funcs)
1644 return to_dm_atomic_state(old_obj_state);
1650 static struct drm_private_state *
1651 dm_atomic_duplicate_state(struct drm_private_obj *obj)
1653 struct dm_atomic_state *old_state, *new_state;
1655 new_state = kzalloc(sizeof(*new_state), GFP_KERNEL);
1659 __drm_atomic_helper_private_obj_duplicate_state(obj, &new_state->base);
1661 new_state->context = dc_create_state();
1662 if (!new_state->context) {
1667 old_state = to_dm_atomic_state(obj->state);
1668 if (old_state && old_state->context)
1669 dc_resource_state_copy_construct(old_state->context,
1670 new_state->context);
1672 return &new_state->base;
1675 static void dm_atomic_destroy_state(struct drm_private_obj *obj,
1676 struct drm_private_state *state)
1678 struct dm_atomic_state *dm_state = to_dm_atomic_state(state);
1680 if (dm_state && dm_state->context)
1681 dc_release_state(dm_state->context);
1686 static struct drm_private_state_funcs dm_atomic_state_funcs = {
1687 .atomic_duplicate_state = dm_atomic_duplicate_state,
1688 .atomic_destroy_state = dm_atomic_destroy_state,
1691 static int amdgpu_dm_mode_config_init(struct amdgpu_device *adev)
1693 struct dm_atomic_state *state;
1696 adev->mode_info.mode_config_initialized = true;
1698 adev->ddev->mode_config.funcs = (void *)&amdgpu_dm_mode_funcs;
1699 adev->ddev->mode_config.helper_private = &amdgpu_dm_mode_config_helperfuncs;
1701 adev->ddev->mode_config.max_width = 16384;
1702 adev->ddev->mode_config.max_height = 16384;
1704 adev->ddev->mode_config.preferred_depth = 24;
1705 adev->ddev->mode_config.prefer_shadow = 1;
1706 /* indicates support for immediate flip */
1707 adev->ddev->mode_config.async_page_flip = true;
1709 adev->ddev->mode_config.fb_base = adev->gmc.aper_base;
1711 drm_modeset_lock_init(&adev->dm.atomic_obj_lock);
1713 state = kzalloc(sizeof(*state), GFP_KERNEL);
1717 state->context = dc_create_state();
1718 if (!state->context) {
1723 dc_resource_state_copy_construct_current(adev->dm.dc, state->context);
1725 drm_atomic_private_obj_init(adev->ddev,
1726 &adev->dm.atomic_obj,
1728 &dm_atomic_state_funcs);
1730 r = amdgpu_display_modeset_create_props(adev);
1737 #define AMDGPU_DM_DEFAULT_MIN_BACKLIGHT 12
1738 #define AMDGPU_DM_DEFAULT_MAX_BACKLIGHT 255
1740 #if defined(CONFIG_BACKLIGHT_CLASS_DEVICE) ||\
1741 defined(CONFIG_BACKLIGHT_CLASS_DEVICE_MODULE)
1743 static void amdgpu_dm_update_backlight_caps(struct amdgpu_display_manager *dm)
1745 #if defined(CONFIG_ACPI)
1746 struct amdgpu_dm_backlight_caps caps;
1748 if (dm->backlight_caps.caps_valid)
1751 amdgpu_acpi_get_backlight_caps(dm->adev, &caps);
1752 if (caps.caps_valid) {
1753 dm->backlight_caps.min_input_signal = caps.min_input_signal;
1754 dm->backlight_caps.max_input_signal = caps.max_input_signal;
1755 dm->backlight_caps.caps_valid = true;
1757 dm->backlight_caps.min_input_signal =
1758 AMDGPU_DM_DEFAULT_MIN_BACKLIGHT;
1759 dm->backlight_caps.max_input_signal =
1760 AMDGPU_DM_DEFAULT_MAX_BACKLIGHT;
1763 dm->backlight_caps.min_input_signal = AMDGPU_DM_DEFAULT_MIN_BACKLIGHT;
1764 dm->backlight_caps.max_input_signal = AMDGPU_DM_DEFAULT_MAX_BACKLIGHT;
1768 static int amdgpu_dm_backlight_update_status(struct backlight_device *bd)
1770 struct amdgpu_display_manager *dm = bl_get_data(bd);
1771 struct amdgpu_dm_backlight_caps caps;
1772 uint32_t brightness = bd->props.brightness;
1774 amdgpu_dm_update_backlight_caps(dm);
1775 caps = dm->backlight_caps;
1777 * The brightness input is in the range 0-255
1778 * It needs to be rescaled to be between the
1779 * requested min and max input signal
1781 * It also needs to be scaled up by 0x101 to
1782 * match the DC interface which has a range of
1788 * (caps.max_input_signal - caps.min_input_signal)
1789 / AMDGPU_MAX_BL_LEVEL
1790 + caps.min_input_signal * 0x101;
1792 if (dc_link_set_backlight_level(dm->backlight_link,
1799 static int amdgpu_dm_backlight_get_brightness(struct backlight_device *bd)
1801 struct amdgpu_display_manager *dm = bl_get_data(bd);
1802 int ret = dc_link_get_backlight_level(dm->backlight_link);
1804 if (ret == DC_ERROR_UNEXPECTED)
1805 return bd->props.brightness;
1809 static const struct backlight_ops amdgpu_dm_backlight_ops = {
1810 .get_brightness = amdgpu_dm_backlight_get_brightness,
1811 .update_status = amdgpu_dm_backlight_update_status,
1815 amdgpu_dm_register_backlight_device(struct amdgpu_display_manager *dm)
1818 struct backlight_properties props = { 0 };
1820 amdgpu_dm_update_backlight_caps(dm);
1822 props.max_brightness = AMDGPU_MAX_BL_LEVEL;
1823 props.brightness = AMDGPU_MAX_BL_LEVEL;
1824 props.type = BACKLIGHT_RAW;
1826 snprintf(bl_name, sizeof(bl_name), "amdgpu_bl%d",
1827 dm->adev->ddev->primary->index);
1829 dm->backlight_dev = backlight_device_register(bl_name,
1830 dm->adev->ddev->dev,
1832 &amdgpu_dm_backlight_ops,
1835 if (IS_ERR(dm->backlight_dev))
1836 DRM_ERROR("DM: Backlight registration failed!\n");
1838 DRM_DEBUG_DRIVER("DM: Registered Backlight device: %s\n", bl_name);
1843 static int initialize_plane(struct amdgpu_display_manager *dm,
1844 struct amdgpu_mode_info *mode_info,
1847 struct drm_plane *plane;
1848 unsigned long possible_crtcs;
1851 plane = kzalloc(sizeof(struct drm_plane), GFP_KERNEL);
1852 mode_info->planes[plane_id] = plane;
1855 DRM_ERROR("KMS: Failed to allocate plane\n");
1858 plane->type = mode_info->plane_type[plane_id];
1861 * HACK: IGT tests expect that each plane can only have
1862 * one possible CRTC. For now, set one CRTC for each
1863 * plane that is not an underlay, but still allow multiple
1864 * CRTCs for underlay planes.
1866 possible_crtcs = 1 << plane_id;
1867 if (plane_id >= dm->dc->caps.max_streams)
1868 possible_crtcs = 0xff;
1870 ret = amdgpu_dm_plane_init(dm, mode_info->planes[plane_id], possible_crtcs);
1873 DRM_ERROR("KMS: Failed to initialize plane\n");
1881 static void register_backlight_device(struct amdgpu_display_manager *dm,
1882 struct dc_link *link)
1884 #if defined(CONFIG_BACKLIGHT_CLASS_DEVICE) ||\
1885 defined(CONFIG_BACKLIGHT_CLASS_DEVICE_MODULE)
1887 if ((link->connector_signal & (SIGNAL_TYPE_EDP | SIGNAL_TYPE_LVDS)) &&
1888 link->type != dc_connection_none) {
1890 * Event if registration failed, we should continue with
1891 * DM initialization because not having a backlight control
1892 * is better then a black screen.
1894 amdgpu_dm_register_backlight_device(dm);
1896 if (dm->backlight_dev)
1897 dm->backlight_link = link;
1904 * In this architecture, the association
1905 * connector -> encoder -> crtc
1906 * id not really requried. The crtc and connector will hold the
1907 * display_index as an abstraction to use with DAL component
1909 * Returns 0 on success
1911 static int amdgpu_dm_initialize_drm_device(struct amdgpu_device *adev)
1913 struct amdgpu_display_manager *dm = &adev->dm;
1915 struct amdgpu_dm_connector *aconnector = NULL;
1916 struct amdgpu_encoder *aencoder = NULL;
1917 struct amdgpu_mode_info *mode_info = &adev->mode_info;
1919 int32_t total_overlay_planes, total_primary_planes;
1920 enum dc_connection_type new_connection_type = dc_connection_none;
1922 link_cnt = dm->dc->caps.max_links;
1923 if (amdgpu_dm_mode_config_init(dm->adev)) {
1924 DRM_ERROR("DM: Failed to initialize mode config\n");
1928 /* Identify the number of planes to be initialized */
1929 total_overlay_planes = dm->dc->caps.max_slave_planes;
1930 total_primary_planes = dm->dc->caps.max_planes - dm->dc->caps.max_slave_planes;
1932 /* First initialize overlay planes, index starting after primary planes */
1933 for (i = (total_overlay_planes - 1); i >= 0; i--) {
1934 if (initialize_plane(dm, mode_info, (total_primary_planes + i))) {
1935 DRM_ERROR("KMS: Failed to initialize overlay plane\n");
1940 /* Initialize primary planes */
1941 for (i = (total_primary_planes - 1); i >= 0; i--) {
1942 if (initialize_plane(dm, mode_info, i)) {
1943 DRM_ERROR("KMS: Failed to initialize primary plane\n");
1948 for (i = 0; i < dm->dc->caps.max_streams; i++)
1949 if (amdgpu_dm_crtc_init(dm, mode_info->planes[i], i)) {
1950 DRM_ERROR("KMS: Failed to initialize crtc\n");
1954 dm->display_indexes_num = dm->dc->caps.max_streams;
1956 /* loops over all connectors on the board */
1957 for (i = 0; i < link_cnt; i++) {
1958 struct dc_link *link = NULL;
1960 if (i > AMDGPU_DM_MAX_DISPLAY_INDEX) {
1962 "KMS: Cannot support more than %d display indexes\n",
1963 AMDGPU_DM_MAX_DISPLAY_INDEX);
1967 aconnector = kzalloc(sizeof(*aconnector), GFP_KERNEL);
1971 aencoder = kzalloc(sizeof(*aencoder), GFP_KERNEL);
1975 if (amdgpu_dm_encoder_init(dm->ddev, aencoder, i)) {
1976 DRM_ERROR("KMS: Failed to initialize encoder\n");
1980 if (amdgpu_dm_connector_init(dm, aconnector, i, aencoder)) {
1981 DRM_ERROR("KMS: Failed to initialize connector\n");
1985 link = dc_get_link_at_index(dm->dc, i);
1987 if (!dc_link_detect_sink(link, &new_connection_type))
1988 DRM_ERROR("KMS: Failed to detect connector\n");
1990 if (aconnector->base.force && new_connection_type == dc_connection_none) {
1991 emulated_link_detect(link);
1992 amdgpu_dm_update_connector_after_detect(aconnector);
1994 } else if (dc_link_detect(link, DETECT_REASON_BOOT)) {
1995 amdgpu_dm_update_connector_after_detect(aconnector);
1996 register_backlight_device(dm, link);
2002 /* Software is initialized. Now we can register interrupt handlers. */
2003 switch (adev->asic_type) {
2013 case CHIP_POLARIS11:
2014 case CHIP_POLARIS10:
2015 case CHIP_POLARIS12:
2020 if (dce110_register_irq_handlers(dm->adev)) {
2021 DRM_ERROR("DM: Failed to initialize IRQ\n");
2025 #if defined(CONFIG_DRM_AMD_DC_DCN1_0)
2027 if (dcn10_register_irq_handlers(dm->adev)) {
2028 DRM_ERROR("DM: Failed to initialize IRQ\n");
2034 DRM_ERROR("Unsupported ASIC type: 0x%X\n", adev->asic_type);
2038 if (adev->asic_type != CHIP_CARRIZO && adev->asic_type != CHIP_STONEY)
2039 dm->dc->debug.disable_stutter = amdgpu_pp_feature_mask & PP_STUTTER_MODE ? false : true;
2045 for (i = 0; i < dm->dc->caps.max_planes; i++)
2046 kfree(mode_info->planes[i]);
2050 static void amdgpu_dm_destroy_drm_device(struct amdgpu_display_manager *dm)
2052 drm_mode_config_cleanup(dm->ddev);
2053 drm_atomic_private_obj_fini(&dm->atomic_obj);
2057 /******************************************************************************
2058 * amdgpu_display_funcs functions
2059 *****************************************************************************/
2062 * dm_bandwidth_update - program display watermarks
2064 * @adev: amdgpu_device pointer
2066 * Calculate and program the display watermarks and line buffer allocation.
2068 static void dm_bandwidth_update(struct amdgpu_device *adev)
2070 /* TODO: implement later */
2073 static const struct amdgpu_display_funcs dm_display_funcs = {
2074 .bandwidth_update = dm_bandwidth_update, /* called unconditionally */
2075 .vblank_get_counter = dm_vblank_get_counter,/* called unconditionally */
2076 .backlight_set_level = NULL, /* never called for DC */
2077 .backlight_get_level = NULL, /* never called for DC */
2078 .hpd_sense = NULL,/* called unconditionally */
2079 .hpd_set_polarity = NULL, /* called unconditionally */
2080 .hpd_get_gpio_reg = NULL, /* VBIOS parsing. DAL does it. */
2081 .page_flip_get_scanoutpos =
2082 dm_crtc_get_scanoutpos,/* called unconditionally */
2083 .add_encoder = NULL, /* VBIOS parsing. DAL does it. */
2084 .add_connector = NULL, /* VBIOS parsing. DAL does it. */
2087 #if defined(CONFIG_DEBUG_KERNEL_DC)
2089 static ssize_t s3_debug_store(struct device *device,
2090 struct device_attribute *attr,
2096 struct pci_dev *pdev = to_pci_dev(device);
2097 struct drm_device *drm_dev = pci_get_drvdata(pdev);
2098 struct amdgpu_device *adev = drm_dev->dev_private;
2100 ret = kstrtoint(buf, 0, &s3_state);
2105 drm_kms_helper_hotplug_event(adev->ddev);
2110 return ret == 0 ? count : 0;
2113 DEVICE_ATTR_WO(s3_debug);
2117 static int dm_early_init(void *handle)
2119 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2121 switch (adev->asic_type) {
2124 adev->mode_info.num_crtc = 6;
2125 adev->mode_info.num_hpd = 6;
2126 adev->mode_info.num_dig = 6;
2127 adev->mode_info.plane_type = dm_plane_type_default;
2130 adev->mode_info.num_crtc = 4;
2131 adev->mode_info.num_hpd = 6;
2132 adev->mode_info.num_dig = 7;
2133 adev->mode_info.plane_type = dm_plane_type_default;
2137 adev->mode_info.num_crtc = 2;
2138 adev->mode_info.num_hpd = 6;
2139 adev->mode_info.num_dig = 6;
2140 adev->mode_info.plane_type = dm_plane_type_default;
2144 adev->mode_info.num_crtc = 6;
2145 adev->mode_info.num_hpd = 6;
2146 adev->mode_info.num_dig = 7;
2147 adev->mode_info.plane_type = dm_plane_type_default;
2150 adev->mode_info.num_crtc = 3;
2151 adev->mode_info.num_hpd = 6;
2152 adev->mode_info.num_dig = 9;
2153 adev->mode_info.plane_type = dm_plane_type_carizzo;
2156 adev->mode_info.num_crtc = 2;
2157 adev->mode_info.num_hpd = 6;
2158 adev->mode_info.num_dig = 9;
2159 adev->mode_info.plane_type = dm_plane_type_stoney;
2161 case CHIP_POLARIS11:
2162 case CHIP_POLARIS12:
2163 adev->mode_info.num_crtc = 5;
2164 adev->mode_info.num_hpd = 5;
2165 adev->mode_info.num_dig = 5;
2166 adev->mode_info.plane_type = dm_plane_type_default;
2168 case CHIP_POLARIS10:
2170 adev->mode_info.num_crtc = 6;
2171 adev->mode_info.num_hpd = 6;
2172 adev->mode_info.num_dig = 6;
2173 adev->mode_info.plane_type = dm_plane_type_default;
2178 adev->mode_info.num_crtc = 6;
2179 adev->mode_info.num_hpd = 6;
2180 adev->mode_info.num_dig = 6;
2181 adev->mode_info.plane_type = dm_plane_type_default;
2183 #if defined(CONFIG_DRM_AMD_DC_DCN1_0)
2185 adev->mode_info.num_crtc = 4;
2186 adev->mode_info.num_hpd = 4;
2187 adev->mode_info.num_dig = 4;
2188 adev->mode_info.plane_type = dm_plane_type_default;
2192 DRM_ERROR("Unsupported ASIC type: 0x%X\n", adev->asic_type);
2196 amdgpu_dm_set_irq_funcs(adev);
2198 if (adev->mode_info.funcs == NULL)
2199 adev->mode_info.funcs = &dm_display_funcs;
2202 * Note: Do NOT change adev->audio_endpt_rreg and
2203 * adev->audio_endpt_wreg because they are initialised in
2204 * amdgpu_device_init()
2206 #if defined(CONFIG_DEBUG_KERNEL_DC)
2209 &dev_attr_s3_debug);
2215 static bool modeset_required(struct drm_crtc_state *crtc_state,
2216 struct dc_stream_state *new_stream,
2217 struct dc_stream_state *old_stream)
2219 if (!drm_atomic_crtc_needs_modeset(crtc_state))
2222 if (!crtc_state->enable)
2225 return crtc_state->active;
2228 static bool modereset_required(struct drm_crtc_state *crtc_state)
2230 if (!drm_atomic_crtc_needs_modeset(crtc_state))
2233 return !crtc_state->enable || !crtc_state->active;
2236 static void amdgpu_dm_encoder_destroy(struct drm_encoder *encoder)
2238 drm_encoder_cleanup(encoder);
2242 static const struct drm_encoder_funcs amdgpu_dm_encoder_funcs = {
2243 .destroy = amdgpu_dm_encoder_destroy,
2246 static bool fill_rects_from_plane_state(const struct drm_plane_state *state,
2247 struct dc_plane_state *plane_state)
2249 plane_state->src_rect.x = state->src_x >> 16;
2250 plane_state->src_rect.y = state->src_y >> 16;
2251 /* we ignore the mantissa for now and do not deal with floating pixels :( */
2252 plane_state->src_rect.width = state->src_w >> 16;
2254 if (plane_state->src_rect.width == 0)
2257 plane_state->src_rect.height = state->src_h >> 16;
2258 if (plane_state->src_rect.height == 0)
2261 plane_state->dst_rect.x = state->crtc_x;
2262 plane_state->dst_rect.y = state->crtc_y;
2264 if (state->crtc_w == 0)
2267 plane_state->dst_rect.width = state->crtc_w;
2269 if (state->crtc_h == 0)
2272 plane_state->dst_rect.height = state->crtc_h;
2274 plane_state->clip_rect = plane_state->dst_rect;
2276 switch (state->rotation & DRM_MODE_ROTATE_MASK) {
2277 case DRM_MODE_ROTATE_0:
2278 plane_state->rotation = ROTATION_ANGLE_0;
2280 case DRM_MODE_ROTATE_90:
2281 plane_state->rotation = ROTATION_ANGLE_90;
2283 case DRM_MODE_ROTATE_180:
2284 plane_state->rotation = ROTATION_ANGLE_180;
2286 case DRM_MODE_ROTATE_270:
2287 plane_state->rotation = ROTATION_ANGLE_270;
2290 plane_state->rotation = ROTATION_ANGLE_0;
2296 static int get_fb_info(const struct amdgpu_framebuffer *amdgpu_fb,
2297 uint64_t *tiling_flags)
2299 struct amdgpu_bo *rbo = gem_to_amdgpu_bo(amdgpu_fb->base.obj[0]);
2300 int r = amdgpu_bo_reserve(rbo, false);
2303 /* Don't show error message when returning -ERESTARTSYS */
2304 if (r != -ERESTARTSYS)
2305 DRM_ERROR("Unable to reserve buffer: %d\n", r);
2310 amdgpu_bo_get_tiling_flags(rbo, tiling_flags);
2312 amdgpu_bo_unreserve(rbo);
2317 static inline uint64_t get_dcc_address(uint64_t address, uint64_t tiling_flags)
2319 uint32_t offset = AMDGPU_TILING_GET(tiling_flags, DCC_OFFSET_256B);
2321 return offset ? (address + offset * 256) : 0;
2324 static bool fill_plane_dcc_attributes(struct amdgpu_device *adev,
2325 const struct amdgpu_framebuffer *afb,
2326 struct dc_plane_state *plane_state,
2329 struct dc *dc = adev->dm.dc;
2330 struct dc_dcc_surface_param input;
2331 struct dc_surface_dcc_cap output;
2332 uint32_t offset = AMDGPU_TILING_GET(info, DCC_OFFSET_256B);
2333 uint32_t i64b = AMDGPU_TILING_GET(info, DCC_INDEPENDENT_64B) != 0;
2334 uint64_t dcc_address;
2336 memset(&input, 0, sizeof(input));
2337 memset(&output, 0, sizeof(output));
2342 if (!dc->cap_funcs.get_dcc_compression_cap)
2345 input.format = plane_state->format;
2346 input.surface_size.width =
2347 plane_state->plane_size.grph.surface_size.width;
2348 input.surface_size.height =
2349 plane_state->plane_size.grph.surface_size.height;
2350 input.swizzle_mode = plane_state->tiling_info.gfx9.swizzle;
2352 if (plane_state->rotation == ROTATION_ANGLE_0 ||
2353 plane_state->rotation == ROTATION_ANGLE_180)
2354 input.scan = SCAN_DIRECTION_HORIZONTAL;
2355 else if (plane_state->rotation == ROTATION_ANGLE_90 ||
2356 plane_state->rotation == ROTATION_ANGLE_270)
2357 input.scan = SCAN_DIRECTION_VERTICAL;
2359 if (!dc->cap_funcs.get_dcc_compression_cap(dc, &input, &output))
2362 if (!output.capable)
2365 if (i64b == 0 && output.grph.rgb.independent_64b_blks != 0)
2368 plane_state->dcc.enable = 1;
2369 plane_state->dcc.grph.meta_pitch =
2370 AMDGPU_TILING_GET(info, DCC_PITCH_MAX) + 1;
2371 plane_state->dcc.grph.independent_64b_blks = i64b;
2373 dcc_address = get_dcc_address(afb->address, info);
2374 plane_state->address.grph.meta_addr.low_part =
2375 lower_32_bits(dcc_address);
2376 plane_state->address.grph.meta_addr.high_part =
2377 upper_32_bits(dcc_address);
2382 static int fill_plane_attributes_from_fb(struct amdgpu_device *adev,
2383 struct dc_plane_state *plane_state,
2384 const struct amdgpu_framebuffer *amdgpu_fb)
2386 uint64_t tiling_flags;
2387 unsigned int awidth;
2388 const struct drm_framebuffer *fb = &amdgpu_fb->base;
2390 struct drm_format_name_buf format_name;
2399 switch (fb->format->format) {
2401 plane_state->format = SURFACE_PIXEL_FORMAT_GRPH_PALETA_256_COLORS;
2403 case DRM_FORMAT_RGB565:
2404 plane_state->format = SURFACE_PIXEL_FORMAT_GRPH_RGB565;
2406 case DRM_FORMAT_XRGB8888:
2407 case DRM_FORMAT_ARGB8888:
2408 plane_state->format = SURFACE_PIXEL_FORMAT_GRPH_ARGB8888;
2410 case DRM_FORMAT_XRGB2101010:
2411 case DRM_FORMAT_ARGB2101010:
2412 plane_state->format = SURFACE_PIXEL_FORMAT_GRPH_ARGB2101010;
2414 case DRM_FORMAT_XBGR2101010:
2415 case DRM_FORMAT_ABGR2101010:
2416 plane_state->format = SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010;
2418 case DRM_FORMAT_XBGR8888:
2419 case DRM_FORMAT_ABGR8888:
2420 plane_state->format = SURFACE_PIXEL_FORMAT_GRPH_ABGR8888;
2422 case DRM_FORMAT_NV21:
2423 plane_state->format = SURFACE_PIXEL_FORMAT_VIDEO_420_YCbCr;
2425 case DRM_FORMAT_NV12:
2426 plane_state->format = SURFACE_PIXEL_FORMAT_VIDEO_420_YCrCb;
2429 DRM_ERROR("Unsupported screen format %s\n",
2430 drm_get_format_name(fb->format->format, &format_name));
2434 memset(&plane_state->address, 0, sizeof(plane_state->address));
2435 memset(&plane_state->tiling_info, 0, sizeof(plane_state->tiling_info));
2436 memset(&plane_state->dcc, 0, sizeof(plane_state->dcc));
2438 if (plane_state->format < SURFACE_PIXEL_FORMAT_VIDEO_BEGIN) {
2439 plane_state->address.type = PLN_ADDR_TYPE_GRAPHICS;
2440 plane_state->plane_size.grph.surface_size.x = 0;
2441 plane_state->plane_size.grph.surface_size.y = 0;
2442 plane_state->plane_size.grph.surface_size.width = fb->width;
2443 plane_state->plane_size.grph.surface_size.height = fb->height;
2444 plane_state->plane_size.grph.surface_pitch =
2445 fb->pitches[0] / fb->format->cpp[0];
2446 /* TODO: unhardcode */
2447 plane_state->color_space = COLOR_SPACE_SRGB;
2450 awidth = ALIGN(fb->width, 64);
2451 plane_state->address.type = PLN_ADDR_TYPE_VIDEO_PROGRESSIVE;
2452 plane_state->plane_size.video.luma_size.x = 0;
2453 plane_state->plane_size.video.luma_size.y = 0;
2454 plane_state->plane_size.video.luma_size.width = awidth;
2455 plane_state->plane_size.video.luma_size.height = fb->height;
2456 /* TODO: unhardcode */
2457 plane_state->plane_size.video.luma_pitch = awidth;
2459 plane_state->plane_size.video.chroma_size.x = 0;
2460 plane_state->plane_size.video.chroma_size.y = 0;
2461 plane_state->plane_size.video.chroma_size.width = awidth;
2462 plane_state->plane_size.video.chroma_size.height = fb->height;
2463 plane_state->plane_size.video.chroma_pitch = awidth / 2;
2465 /* TODO: unhardcode */
2466 plane_state->color_space = COLOR_SPACE_YCBCR709;
2469 /* Fill GFX8 params */
2470 if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE) == DC_ARRAY_2D_TILED_THIN1) {
2471 unsigned int bankw, bankh, mtaspect, tile_split, num_banks;
2473 bankw = AMDGPU_TILING_GET(tiling_flags, BANK_WIDTH);
2474 bankh = AMDGPU_TILING_GET(tiling_flags, BANK_HEIGHT);
2475 mtaspect = AMDGPU_TILING_GET(tiling_flags, MACRO_TILE_ASPECT);
2476 tile_split = AMDGPU_TILING_GET(tiling_flags, TILE_SPLIT);
2477 num_banks = AMDGPU_TILING_GET(tiling_flags, NUM_BANKS);
2479 /* XXX fix me for VI */
2480 plane_state->tiling_info.gfx8.num_banks = num_banks;
2481 plane_state->tiling_info.gfx8.array_mode =
2482 DC_ARRAY_2D_TILED_THIN1;
2483 plane_state->tiling_info.gfx8.tile_split = tile_split;
2484 plane_state->tiling_info.gfx8.bank_width = bankw;
2485 plane_state->tiling_info.gfx8.bank_height = bankh;
2486 plane_state->tiling_info.gfx8.tile_aspect = mtaspect;
2487 plane_state->tiling_info.gfx8.tile_mode =
2488 DC_ADDR_SURF_MICRO_TILING_DISPLAY;
2489 } else if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE)
2490 == DC_ARRAY_1D_TILED_THIN1) {
2491 plane_state->tiling_info.gfx8.array_mode = DC_ARRAY_1D_TILED_THIN1;
2494 plane_state->tiling_info.gfx8.pipe_config =
2495 AMDGPU_TILING_GET(tiling_flags, PIPE_CONFIG);
2497 if (adev->asic_type == CHIP_VEGA10 ||
2498 adev->asic_type == CHIP_VEGA12 ||
2499 adev->asic_type == CHIP_VEGA20 ||
2500 adev->asic_type == CHIP_RAVEN) {
2501 /* Fill GFX9 params */
2502 plane_state->tiling_info.gfx9.num_pipes =
2503 adev->gfx.config.gb_addr_config_fields.num_pipes;
2504 plane_state->tiling_info.gfx9.num_banks =
2505 adev->gfx.config.gb_addr_config_fields.num_banks;
2506 plane_state->tiling_info.gfx9.pipe_interleave =
2507 adev->gfx.config.gb_addr_config_fields.pipe_interleave_size;
2508 plane_state->tiling_info.gfx9.num_shader_engines =
2509 adev->gfx.config.gb_addr_config_fields.num_se;
2510 plane_state->tiling_info.gfx9.max_compressed_frags =
2511 adev->gfx.config.gb_addr_config_fields.max_compress_frags;
2512 plane_state->tiling_info.gfx9.num_rb_per_se =
2513 adev->gfx.config.gb_addr_config_fields.num_rb_per_se;
2514 plane_state->tiling_info.gfx9.swizzle =
2515 AMDGPU_TILING_GET(tiling_flags, SWIZZLE_MODE);
2516 plane_state->tiling_info.gfx9.shaderEnable = 1;
2518 fill_plane_dcc_attributes(adev, amdgpu_fb, plane_state,
2522 plane_state->visible = true;
2523 plane_state->scaling_quality.h_taps_c = 0;
2524 plane_state->scaling_quality.v_taps_c = 0;
2526 /* is this needed? is plane_state zeroed at allocation? */
2527 plane_state->scaling_quality.h_taps = 0;
2528 plane_state->scaling_quality.v_taps = 0;
2529 plane_state->stereo_format = PLANE_STEREO_FORMAT_NONE;
2535 static int fill_plane_attributes(struct amdgpu_device *adev,
2536 struct dc_plane_state *dc_plane_state,
2537 struct drm_plane_state *plane_state,
2538 struct drm_crtc_state *crtc_state)
2540 const struct amdgpu_framebuffer *amdgpu_fb =
2541 to_amdgpu_framebuffer(plane_state->fb);
2542 const struct drm_crtc *crtc = plane_state->crtc;
2545 if (!fill_rects_from_plane_state(plane_state, dc_plane_state))
2548 ret = fill_plane_attributes_from_fb(
2549 crtc->dev->dev_private,
2557 * Always set input transfer function, since plane state is refreshed
2560 ret = amdgpu_dm_set_degamma_lut(crtc_state, dc_plane_state);
2562 dc_transfer_func_release(dc_plane_state->in_transfer_func);
2563 dc_plane_state->in_transfer_func = NULL;
2569 static void update_stream_scaling_settings(const struct drm_display_mode *mode,
2570 const struct dm_connector_state *dm_state,
2571 struct dc_stream_state *stream)
2573 enum amdgpu_rmx_type rmx_type;
2575 struct rect src = { 0 }; /* viewport in composition space*/
2576 struct rect dst = { 0 }; /* stream addressable area */
2578 /* no mode. nothing to be done */
2582 /* Full screen scaling by default */
2583 src.width = mode->hdisplay;
2584 src.height = mode->vdisplay;
2585 dst.width = stream->timing.h_addressable;
2586 dst.height = stream->timing.v_addressable;
2589 rmx_type = dm_state->scaling;
2590 if (rmx_type == RMX_ASPECT || rmx_type == RMX_OFF) {
2591 if (src.width * dst.height <
2592 src.height * dst.width) {
2593 /* height needs less upscaling/more downscaling */
2594 dst.width = src.width *
2595 dst.height / src.height;
2597 /* width needs less upscaling/more downscaling */
2598 dst.height = src.height *
2599 dst.width / src.width;
2601 } else if (rmx_type == RMX_CENTER) {
2605 dst.x = (stream->timing.h_addressable - dst.width) / 2;
2606 dst.y = (stream->timing.v_addressable - dst.height) / 2;
2608 if (dm_state->underscan_enable) {
2609 dst.x += dm_state->underscan_hborder / 2;
2610 dst.y += dm_state->underscan_vborder / 2;
2611 dst.width -= dm_state->underscan_hborder;
2612 dst.height -= dm_state->underscan_vborder;
2619 DRM_DEBUG_DRIVER("Destination Rectangle x:%d y:%d width:%d height:%d\n",
2620 dst.x, dst.y, dst.width, dst.height);
2624 static enum dc_color_depth
2625 convert_color_depth_from_display_info(const struct drm_connector *connector)
2627 struct dm_connector_state *dm_conn_state =
2628 to_dm_connector_state(connector->state);
2629 uint32_t bpc = connector->display_info.bpc;
2631 /* TODO: Remove this when there's support for max_bpc in drm */
2632 if (dm_conn_state && bpc > dm_conn_state->max_bpc)
2633 /* Round down to nearest even number. */
2634 bpc = dm_conn_state->max_bpc - (dm_conn_state->max_bpc & 1);
2639 * Temporary Work around, DRM doesn't parse color depth for
2640 * EDID revision before 1.4
2641 * TODO: Fix edid parsing
2643 return COLOR_DEPTH_888;
2645 return COLOR_DEPTH_666;
2647 return COLOR_DEPTH_888;
2649 return COLOR_DEPTH_101010;
2651 return COLOR_DEPTH_121212;
2653 return COLOR_DEPTH_141414;
2655 return COLOR_DEPTH_161616;
2657 return COLOR_DEPTH_UNDEFINED;
2661 static enum dc_aspect_ratio
2662 get_aspect_ratio(const struct drm_display_mode *mode_in)
2664 /* 1-1 mapping, since both enums follow the HDMI spec. */
2665 return (enum dc_aspect_ratio) mode_in->picture_aspect_ratio;
2668 static enum dc_color_space
2669 get_output_color_space(const struct dc_crtc_timing *dc_crtc_timing)
2671 enum dc_color_space color_space = COLOR_SPACE_SRGB;
2673 switch (dc_crtc_timing->pixel_encoding) {
2674 case PIXEL_ENCODING_YCBCR422:
2675 case PIXEL_ENCODING_YCBCR444:
2676 case PIXEL_ENCODING_YCBCR420:
2679 * 27030khz is the separation point between HDTV and SDTV
2680 * according to HDMI spec, we use YCbCr709 and YCbCr601
2683 if (dc_crtc_timing->pix_clk_100hz > 270300) {
2684 if (dc_crtc_timing->flags.Y_ONLY)
2686 COLOR_SPACE_YCBCR709_LIMITED;
2688 color_space = COLOR_SPACE_YCBCR709;
2690 if (dc_crtc_timing->flags.Y_ONLY)
2692 COLOR_SPACE_YCBCR601_LIMITED;
2694 color_space = COLOR_SPACE_YCBCR601;
2699 case PIXEL_ENCODING_RGB:
2700 color_space = COLOR_SPACE_SRGB;
2711 static void reduce_mode_colour_depth(struct dc_crtc_timing *timing_out)
2713 if (timing_out->display_color_depth <= COLOR_DEPTH_888)
2716 timing_out->display_color_depth--;
2719 static void adjust_colour_depth_from_display_info(struct dc_crtc_timing *timing_out,
2720 const struct drm_display_info *info)
2723 if (timing_out->display_color_depth <= COLOR_DEPTH_888)
2726 normalized_clk = timing_out->pix_clk_100hz / 10;
2727 /* YCbCr 4:2:0 requires additional adjustment of 1/2 */
2728 if (timing_out->pixel_encoding == PIXEL_ENCODING_YCBCR420)
2729 normalized_clk /= 2;
2730 /* Adjusting pix clock following on HDMI spec based on colour depth */
2731 switch (timing_out->display_color_depth) {
2732 case COLOR_DEPTH_101010:
2733 normalized_clk = (normalized_clk * 30) / 24;
2735 case COLOR_DEPTH_121212:
2736 normalized_clk = (normalized_clk * 36) / 24;
2738 case COLOR_DEPTH_161616:
2739 normalized_clk = (normalized_clk * 48) / 24;
2744 if (normalized_clk <= info->max_tmds_clock)
2746 reduce_mode_colour_depth(timing_out);
2748 } while (timing_out->display_color_depth > COLOR_DEPTH_888);
2753 fill_stream_properties_from_drm_display_mode(struct dc_stream_state *stream,
2754 const struct drm_display_mode *mode_in,
2755 const struct drm_connector *connector,
2756 const struct dc_stream_state *old_stream)
2758 struct dc_crtc_timing *timing_out = &stream->timing;
2759 const struct drm_display_info *info = &connector->display_info;
2761 memset(timing_out, 0, sizeof(struct dc_crtc_timing));
2763 timing_out->h_border_left = 0;
2764 timing_out->h_border_right = 0;
2765 timing_out->v_border_top = 0;
2766 timing_out->v_border_bottom = 0;
2767 /* TODO: un-hardcode */
2768 if (drm_mode_is_420_only(info, mode_in)
2769 && stream->signal == SIGNAL_TYPE_HDMI_TYPE_A)
2770 timing_out->pixel_encoding = PIXEL_ENCODING_YCBCR420;
2771 else if ((connector->display_info.color_formats & DRM_COLOR_FORMAT_YCRCB444)
2772 && stream->signal == SIGNAL_TYPE_HDMI_TYPE_A)
2773 timing_out->pixel_encoding = PIXEL_ENCODING_YCBCR444;
2775 timing_out->pixel_encoding = PIXEL_ENCODING_RGB;
2777 timing_out->timing_3d_format = TIMING_3D_FORMAT_NONE;
2778 timing_out->display_color_depth = convert_color_depth_from_display_info(
2780 timing_out->scan_type = SCANNING_TYPE_NODATA;
2781 timing_out->hdmi_vic = 0;
2784 timing_out->vic = old_stream->timing.vic;
2785 timing_out->flags.HSYNC_POSITIVE_POLARITY = old_stream->timing.flags.HSYNC_POSITIVE_POLARITY;
2786 timing_out->flags.VSYNC_POSITIVE_POLARITY = old_stream->timing.flags.VSYNC_POSITIVE_POLARITY;
2788 timing_out->vic = drm_match_cea_mode(mode_in);
2789 if (mode_in->flags & DRM_MODE_FLAG_PHSYNC)
2790 timing_out->flags.HSYNC_POSITIVE_POLARITY = 1;
2791 if (mode_in->flags & DRM_MODE_FLAG_PVSYNC)
2792 timing_out->flags.VSYNC_POSITIVE_POLARITY = 1;
2795 timing_out->h_addressable = mode_in->crtc_hdisplay;
2796 timing_out->h_total = mode_in->crtc_htotal;
2797 timing_out->h_sync_width =
2798 mode_in->crtc_hsync_end - mode_in->crtc_hsync_start;
2799 timing_out->h_front_porch =
2800 mode_in->crtc_hsync_start - mode_in->crtc_hdisplay;
2801 timing_out->v_total = mode_in->crtc_vtotal;
2802 timing_out->v_addressable = mode_in->crtc_vdisplay;
2803 timing_out->v_front_porch =
2804 mode_in->crtc_vsync_start - mode_in->crtc_vdisplay;
2805 timing_out->v_sync_width =
2806 mode_in->crtc_vsync_end - mode_in->crtc_vsync_start;
2807 timing_out->pix_clk_100hz = mode_in->crtc_clock * 10;
2808 timing_out->aspect_ratio = get_aspect_ratio(mode_in);
2810 stream->output_color_space = get_output_color_space(timing_out);
2812 stream->out_transfer_func->type = TF_TYPE_PREDEFINED;
2813 stream->out_transfer_func->tf = TRANSFER_FUNCTION_SRGB;
2814 if (stream->signal == SIGNAL_TYPE_HDMI_TYPE_A)
2815 adjust_colour_depth_from_display_info(timing_out, info);
2818 static void fill_audio_info(struct audio_info *audio_info,
2819 const struct drm_connector *drm_connector,
2820 const struct dc_sink *dc_sink)
2823 int cea_revision = 0;
2824 const struct dc_edid_caps *edid_caps = &dc_sink->edid_caps;
2826 audio_info->manufacture_id = edid_caps->manufacturer_id;
2827 audio_info->product_id = edid_caps->product_id;
2829 cea_revision = drm_connector->display_info.cea_rev;
2831 strscpy(audio_info->display_name,
2832 edid_caps->display_name,
2833 AUDIO_INFO_DISPLAY_NAME_SIZE_IN_CHARS);
2835 if (cea_revision >= 3) {
2836 audio_info->mode_count = edid_caps->audio_mode_count;
2838 for (i = 0; i < audio_info->mode_count; ++i) {
2839 audio_info->modes[i].format_code =
2840 (enum audio_format_code)
2841 (edid_caps->audio_modes[i].format_code);
2842 audio_info->modes[i].channel_count =
2843 edid_caps->audio_modes[i].channel_count;
2844 audio_info->modes[i].sample_rates.all =
2845 edid_caps->audio_modes[i].sample_rate;
2846 audio_info->modes[i].sample_size =
2847 edid_caps->audio_modes[i].sample_size;
2851 audio_info->flags.all = edid_caps->speaker_flags;
2853 /* TODO: We only check for the progressive mode, check for interlace mode too */
2854 if (drm_connector->latency_present[0]) {
2855 audio_info->video_latency = drm_connector->video_latency[0];
2856 audio_info->audio_latency = drm_connector->audio_latency[0];
2859 /* TODO: For DP, video and audio latency should be calculated from DPCD caps */
2864 copy_crtc_timing_for_drm_display_mode(const struct drm_display_mode *src_mode,
2865 struct drm_display_mode *dst_mode)
2867 dst_mode->crtc_hdisplay = src_mode->crtc_hdisplay;
2868 dst_mode->crtc_vdisplay = src_mode->crtc_vdisplay;
2869 dst_mode->crtc_clock = src_mode->crtc_clock;
2870 dst_mode->crtc_hblank_start = src_mode->crtc_hblank_start;
2871 dst_mode->crtc_hblank_end = src_mode->crtc_hblank_end;
2872 dst_mode->crtc_hsync_start = src_mode->crtc_hsync_start;
2873 dst_mode->crtc_hsync_end = src_mode->crtc_hsync_end;
2874 dst_mode->crtc_htotal = src_mode->crtc_htotal;
2875 dst_mode->crtc_hskew = src_mode->crtc_hskew;
2876 dst_mode->crtc_vblank_start = src_mode->crtc_vblank_start;
2877 dst_mode->crtc_vblank_end = src_mode->crtc_vblank_end;
2878 dst_mode->crtc_vsync_start = src_mode->crtc_vsync_start;
2879 dst_mode->crtc_vsync_end = src_mode->crtc_vsync_end;
2880 dst_mode->crtc_vtotal = src_mode->crtc_vtotal;
2884 decide_crtc_timing_for_drm_display_mode(struct drm_display_mode *drm_mode,
2885 const struct drm_display_mode *native_mode,
2888 if (scale_enabled) {
2889 copy_crtc_timing_for_drm_display_mode(native_mode, drm_mode);
2890 } else if (native_mode->clock == drm_mode->clock &&
2891 native_mode->htotal == drm_mode->htotal &&
2892 native_mode->vtotal == drm_mode->vtotal) {
2893 copy_crtc_timing_for_drm_display_mode(native_mode, drm_mode);
2895 /* no scaling nor amdgpu inserted, no need to patch */
2899 static struct dc_sink *
2900 create_fake_sink(struct amdgpu_dm_connector *aconnector)
2902 struct dc_sink_init_data sink_init_data = { 0 };
2903 struct dc_sink *sink = NULL;
2904 sink_init_data.link = aconnector->dc_link;
2905 sink_init_data.sink_signal = aconnector->dc_link->connector_signal;
2907 sink = dc_sink_create(&sink_init_data);
2909 DRM_ERROR("Failed to create sink!\n");
2912 sink->sink_signal = SIGNAL_TYPE_VIRTUAL;
2917 static void set_multisync_trigger_params(
2918 struct dc_stream_state *stream)
2920 if (stream->triggered_crtc_reset.enabled) {
2921 stream->triggered_crtc_reset.event = CRTC_EVENT_VSYNC_RISING;
2922 stream->triggered_crtc_reset.delay = TRIGGER_DELAY_NEXT_LINE;
2926 static void set_master_stream(struct dc_stream_state *stream_set[],
2929 int j, highest_rfr = 0, master_stream = 0;
2931 for (j = 0; j < stream_count; j++) {
2932 if (stream_set[j] && stream_set[j]->triggered_crtc_reset.enabled) {
2933 int refresh_rate = 0;
2935 refresh_rate = (stream_set[j]->timing.pix_clk_100hz*100)/
2936 (stream_set[j]->timing.h_total*stream_set[j]->timing.v_total);
2937 if (refresh_rate > highest_rfr) {
2938 highest_rfr = refresh_rate;
2943 for (j = 0; j < stream_count; j++) {
2945 stream_set[j]->triggered_crtc_reset.event_source = stream_set[master_stream];
2949 static void dm_enable_per_frame_crtc_master_sync(struct dc_state *context)
2953 if (context->stream_count < 2)
2955 for (i = 0; i < context->stream_count ; i++) {
2956 if (!context->streams[i])
2959 * TODO: add a function to read AMD VSDB bits and set
2960 * crtc_sync_master.multi_sync_enabled flag
2961 * For now it's set to false
2963 set_multisync_trigger_params(context->streams[i]);
2965 set_master_stream(context->streams, context->stream_count);
2968 static struct dc_stream_state *
2969 create_stream_for_sink(struct amdgpu_dm_connector *aconnector,
2970 const struct drm_display_mode *drm_mode,
2971 const struct dm_connector_state *dm_state,
2972 const struct dc_stream_state *old_stream)
2974 struct drm_display_mode *preferred_mode = NULL;
2975 struct drm_connector *drm_connector;
2976 struct dc_stream_state *stream = NULL;
2977 struct drm_display_mode mode = *drm_mode;
2978 bool native_mode_found = false;
2979 bool scale = dm_state ? (dm_state->scaling != RMX_OFF) : false;
2981 int preferred_refresh = 0;
2983 struct dc_sink *sink = NULL;
2984 if (aconnector == NULL) {
2985 DRM_ERROR("aconnector is NULL!\n");
2989 drm_connector = &aconnector->base;
2991 if (!aconnector->dc_sink) {
2992 sink = create_fake_sink(aconnector);
2996 sink = aconnector->dc_sink;
2997 dc_sink_retain(sink);
3000 stream = dc_create_stream_for_sink(sink);
3002 if (stream == NULL) {
3003 DRM_ERROR("Failed to create stream for sink!\n");
3007 stream->dm_stream_context = aconnector;
3009 list_for_each_entry(preferred_mode, &aconnector->base.modes, head) {
3010 /* Search for preferred mode */
3011 if (preferred_mode->type & DRM_MODE_TYPE_PREFERRED) {
3012 native_mode_found = true;
3016 if (!native_mode_found)
3017 preferred_mode = list_first_entry_or_null(
3018 &aconnector->base.modes,
3019 struct drm_display_mode,
3022 mode_refresh = drm_mode_vrefresh(&mode);
3024 if (preferred_mode == NULL) {
3026 * This may not be an error, the use case is when we have no
3027 * usermode calls to reset and set mode upon hotplug. In this
3028 * case, we call set mode ourselves to restore the previous mode
3029 * and the modelist may not be filled in in time.
3031 DRM_DEBUG_DRIVER("No preferred mode found\n");
3033 decide_crtc_timing_for_drm_display_mode(
3034 &mode, preferred_mode,
3035 dm_state ? (dm_state->scaling != RMX_OFF) : false);
3036 preferred_refresh = drm_mode_vrefresh(preferred_mode);
3040 drm_mode_set_crtcinfo(&mode, 0);
3043 * If scaling is enabled and refresh rate didn't change
3044 * we copy the vic and polarities of the old timings
3046 if (!scale || mode_refresh != preferred_refresh)
3047 fill_stream_properties_from_drm_display_mode(stream,
3048 &mode, &aconnector->base, NULL);
3050 fill_stream_properties_from_drm_display_mode(stream,
3051 &mode, &aconnector->base, old_stream);
3053 update_stream_scaling_settings(&mode, dm_state, stream);
3056 &stream->audio_info,
3060 update_stream_signal(stream, sink);
3063 dc_sink_release(sink);
3068 static void amdgpu_dm_crtc_destroy(struct drm_crtc *crtc)
3070 drm_crtc_cleanup(crtc);
3074 static void dm_crtc_destroy_state(struct drm_crtc *crtc,
3075 struct drm_crtc_state *state)
3077 struct dm_crtc_state *cur = to_dm_crtc_state(state);
3079 /* TODO Destroy dc_stream objects are stream object is flattened */
3081 dc_stream_release(cur->stream);
3084 __drm_atomic_helper_crtc_destroy_state(state);
3090 static void dm_crtc_reset_state(struct drm_crtc *crtc)
3092 struct dm_crtc_state *state;
3095 dm_crtc_destroy_state(crtc, crtc->state);
3097 state = kzalloc(sizeof(*state), GFP_KERNEL);
3098 if (WARN_ON(!state))
3101 crtc->state = &state->base;
3102 crtc->state->crtc = crtc;
3106 static struct drm_crtc_state *
3107 dm_crtc_duplicate_state(struct drm_crtc *crtc)
3109 struct dm_crtc_state *state, *cur;
3111 cur = to_dm_crtc_state(crtc->state);
3113 if (WARN_ON(!crtc->state))
3116 state = kzalloc(sizeof(*state), GFP_KERNEL);
3120 __drm_atomic_helper_crtc_duplicate_state(crtc, &state->base);
3123 state->stream = cur->stream;
3124 dc_stream_retain(state->stream);
3127 state->vrr_params = cur->vrr_params;
3128 state->vrr_infopacket = cur->vrr_infopacket;
3129 state->abm_level = cur->abm_level;
3130 state->vrr_supported = cur->vrr_supported;
3131 state->freesync_config = cur->freesync_config;
3132 state->crc_enabled = cur->crc_enabled;
3134 /* TODO Duplicate dc_stream after objects are stream object is flattened */
3136 return &state->base;
3140 static inline int dm_set_vblank(struct drm_crtc *crtc, bool enable)
3142 enum dc_irq_source irq_source;
3143 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
3144 struct amdgpu_device *adev = crtc->dev->dev_private;
3146 irq_source = IRQ_TYPE_VBLANK + acrtc->otg_inst;
3147 return dc_interrupt_set(adev->dm.dc, irq_source, enable) ? 0 : -EBUSY;
3150 static int dm_enable_vblank(struct drm_crtc *crtc)
3152 return dm_set_vblank(crtc, true);
3155 static void dm_disable_vblank(struct drm_crtc *crtc)
3157 dm_set_vblank(crtc, false);
3160 /* Implemented only the options currently availible for the driver */
3161 static const struct drm_crtc_funcs amdgpu_dm_crtc_funcs = {
3162 .reset = dm_crtc_reset_state,
3163 .destroy = amdgpu_dm_crtc_destroy,
3164 .gamma_set = drm_atomic_helper_legacy_gamma_set,
3165 .set_config = drm_atomic_helper_set_config,
3166 .page_flip = drm_atomic_helper_page_flip,
3167 .atomic_duplicate_state = dm_crtc_duplicate_state,
3168 .atomic_destroy_state = dm_crtc_destroy_state,
3169 .set_crc_source = amdgpu_dm_crtc_set_crc_source,
3170 .verify_crc_source = amdgpu_dm_crtc_verify_crc_source,
3171 .enable_vblank = dm_enable_vblank,
3172 .disable_vblank = dm_disable_vblank,
3175 static enum drm_connector_status
3176 amdgpu_dm_connector_detect(struct drm_connector *connector, bool force)
3179 struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
3183 * 1. This interface is NOT called in context of HPD irq.
3184 * 2. This interface *is called* in context of user-mode ioctl. Which
3185 * makes it a bad place for *any* MST-related activity.
3188 if (aconnector->base.force == DRM_FORCE_UNSPECIFIED &&
3189 !aconnector->fake_enable)
3190 connected = (aconnector->dc_sink != NULL);
3192 connected = (aconnector->base.force == DRM_FORCE_ON);
3194 return (connected ? connector_status_connected :
3195 connector_status_disconnected);
3198 int amdgpu_dm_connector_atomic_set_property(struct drm_connector *connector,
3199 struct drm_connector_state *connector_state,
3200 struct drm_property *property,
3203 struct drm_device *dev = connector->dev;
3204 struct amdgpu_device *adev = dev->dev_private;
3205 struct dm_connector_state *dm_old_state =
3206 to_dm_connector_state(connector->state);
3207 struct dm_connector_state *dm_new_state =
3208 to_dm_connector_state(connector_state);
3212 if (property == dev->mode_config.scaling_mode_property) {
3213 enum amdgpu_rmx_type rmx_type;
3216 case DRM_MODE_SCALE_CENTER:
3217 rmx_type = RMX_CENTER;
3219 case DRM_MODE_SCALE_ASPECT:
3220 rmx_type = RMX_ASPECT;
3222 case DRM_MODE_SCALE_FULLSCREEN:
3223 rmx_type = RMX_FULL;
3225 case DRM_MODE_SCALE_NONE:
3231 if (dm_old_state->scaling == rmx_type)
3234 dm_new_state->scaling = rmx_type;
3236 } else if (property == adev->mode_info.underscan_hborder_property) {
3237 dm_new_state->underscan_hborder = val;
3239 } else if (property == adev->mode_info.underscan_vborder_property) {
3240 dm_new_state->underscan_vborder = val;
3242 } else if (property == adev->mode_info.underscan_property) {
3243 dm_new_state->underscan_enable = val;
3245 } else if (property == adev->mode_info.max_bpc_property) {
3246 dm_new_state->max_bpc = val;
3248 } else if (property == adev->mode_info.abm_level_property) {
3249 dm_new_state->abm_level = val;
3256 int amdgpu_dm_connector_atomic_get_property(struct drm_connector *connector,
3257 const struct drm_connector_state *state,
3258 struct drm_property *property,
3261 struct drm_device *dev = connector->dev;
3262 struct amdgpu_device *adev = dev->dev_private;
3263 struct dm_connector_state *dm_state =
3264 to_dm_connector_state(state);
3267 if (property == dev->mode_config.scaling_mode_property) {
3268 switch (dm_state->scaling) {
3270 *val = DRM_MODE_SCALE_CENTER;
3273 *val = DRM_MODE_SCALE_ASPECT;
3276 *val = DRM_MODE_SCALE_FULLSCREEN;
3280 *val = DRM_MODE_SCALE_NONE;
3284 } else if (property == adev->mode_info.underscan_hborder_property) {
3285 *val = dm_state->underscan_hborder;
3287 } else if (property == adev->mode_info.underscan_vborder_property) {
3288 *val = dm_state->underscan_vborder;
3290 } else if (property == adev->mode_info.underscan_property) {
3291 *val = dm_state->underscan_enable;
3293 } else if (property == adev->mode_info.max_bpc_property) {
3294 *val = dm_state->max_bpc;
3296 } else if (property == adev->mode_info.abm_level_property) {
3297 *val = dm_state->abm_level;
3304 static void amdgpu_dm_connector_destroy(struct drm_connector *connector)
3306 struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
3307 const struct dc_link *link = aconnector->dc_link;
3308 struct amdgpu_device *adev = connector->dev->dev_private;
3309 struct amdgpu_display_manager *dm = &adev->dm;
3311 #if defined(CONFIG_BACKLIGHT_CLASS_DEVICE) ||\
3312 defined(CONFIG_BACKLIGHT_CLASS_DEVICE_MODULE)
3314 if ((link->connector_signal & (SIGNAL_TYPE_EDP | SIGNAL_TYPE_LVDS)) &&
3315 link->type != dc_connection_none &&
3316 dm->backlight_dev) {
3317 backlight_device_unregister(dm->backlight_dev);
3318 dm->backlight_dev = NULL;
3322 if (aconnector->dc_em_sink)
3323 dc_sink_release(aconnector->dc_em_sink);
3324 aconnector->dc_em_sink = NULL;
3325 if (aconnector->dc_sink)
3326 dc_sink_release(aconnector->dc_sink);
3327 aconnector->dc_sink = NULL;
3329 drm_dp_cec_unregister_connector(&aconnector->dm_dp_aux.aux);
3330 drm_connector_unregister(connector);
3331 drm_connector_cleanup(connector);
3335 void amdgpu_dm_connector_funcs_reset(struct drm_connector *connector)
3337 struct dm_connector_state *state =
3338 to_dm_connector_state(connector->state);
3340 if (connector->state)
3341 __drm_atomic_helper_connector_destroy_state(connector->state);
3345 state = kzalloc(sizeof(*state), GFP_KERNEL);
3348 state->scaling = RMX_OFF;
3349 state->underscan_enable = false;
3350 state->underscan_hborder = 0;
3351 state->underscan_vborder = 0;
3354 __drm_atomic_helper_connector_reset(connector, &state->base);
3358 struct drm_connector_state *
3359 amdgpu_dm_connector_atomic_duplicate_state(struct drm_connector *connector)
3361 struct dm_connector_state *state =
3362 to_dm_connector_state(connector->state);
3364 struct dm_connector_state *new_state =
3365 kmemdup(state, sizeof(*state), GFP_KERNEL);
3370 __drm_atomic_helper_connector_duplicate_state(connector, &new_state->base);
3372 new_state->freesync_capable = state->freesync_capable;
3373 new_state->abm_level = state->abm_level;
3374 new_state->scaling = state->scaling;
3375 new_state->underscan_enable = state->underscan_enable;
3376 new_state->underscan_hborder = state->underscan_hborder;
3377 new_state->underscan_vborder = state->underscan_vborder;
3378 new_state->max_bpc = state->max_bpc;
3380 return &new_state->base;
3383 static const struct drm_connector_funcs amdgpu_dm_connector_funcs = {
3384 .reset = amdgpu_dm_connector_funcs_reset,
3385 .detect = amdgpu_dm_connector_detect,
3386 .fill_modes = drm_helper_probe_single_connector_modes,
3387 .destroy = amdgpu_dm_connector_destroy,
3388 .atomic_duplicate_state = amdgpu_dm_connector_atomic_duplicate_state,
3389 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
3390 .atomic_set_property = amdgpu_dm_connector_atomic_set_property,
3391 .atomic_get_property = amdgpu_dm_connector_atomic_get_property
3394 static int get_modes(struct drm_connector *connector)
3396 return amdgpu_dm_connector_get_modes(connector);
3399 static void create_eml_sink(struct amdgpu_dm_connector *aconnector)
3401 struct dc_sink_init_data init_params = {
3402 .link = aconnector->dc_link,
3403 .sink_signal = SIGNAL_TYPE_VIRTUAL
3407 if (!aconnector->base.edid_blob_ptr) {
3408 DRM_ERROR("No EDID firmware found on connector: %s ,forcing to OFF!\n",
3409 aconnector->base.name);
3411 aconnector->base.force = DRM_FORCE_OFF;
3412 aconnector->base.override_edid = false;
3416 edid = (struct edid *) aconnector->base.edid_blob_ptr->data;
3418 aconnector->edid = edid;
3420 aconnector->dc_em_sink = dc_link_add_remote_sink(
3421 aconnector->dc_link,
3423 (edid->extensions + 1) * EDID_LENGTH,
3426 if (aconnector->base.force == DRM_FORCE_ON) {
3427 aconnector->dc_sink = aconnector->dc_link->local_sink ?
3428 aconnector->dc_link->local_sink :
3429 aconnector->dc_em_sink;
3430 dc_sink_retain(aconnector->dc_sink);
3434 static void handle_edid_mgmt(struct amdgpu_dm_connector *aconnector)
3436 struct dc_link *link = (struct dc_link *)aconnector->dc_link;
3439 * In case of headless boot with force on for DP managed connector
3440 * Those settings have to be != 0 to get initial modeset
3442 if (link->connector_signal == SIGNAL_TYPE_DISPLAY_PORT) {
3443 link->verified_link_cap.lane_count = LANE_COUNT_FOUR;
3444 link->verified_link_cap.link_rate = LINK_RATE_HIGH2;
3448 aconnector->base.override_edid = true;
3449 create_eml_sink(aconnector);
3452 enum drm_mode_status amdgpu_dm_connector_mode_valid(struct drm_connector *connector,
3453 struct drm_display_mode *mode)
3455 int result = MODE_ERROR;
3456 struct dc_sink *dc_sink;
3457 struct amdgpu_device *adev = connector->dev->dev_private;
3458 /* TODO: Unhardcode stream count */
3459 struct dc_stream_state *stream;
3460 struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
3461 enum dc_status dc_result = DC_OK;
3463 if ((mode->flags & DRM_MODE_FLAG_INTERLACE) ||
3464 (mode->flags & DRM_MODE_FLAG_DBLSCAN))
3468 * Only run this the first time mode_valid is called to initilialize
3471 if (aconnector->base.force != DRM_FORCE_UNSPECIFIED &&
3472 !aconnector->dc_em_sink)
3473 handle_edid_mgmt(aconnector);
3475 dc_sink = to_amdgpu_dm_connector(connector)->dc_sink;
3477 if (dc_sink == NULL) {
3478 DRM_ERROR("dc_sink is NULL!\n");
3482 stream = create_stream_for_sink(aconnector, mode, NULL, NULL);
3483 if (stream == NULL) {
3484 DRM_ERROR("Failed to create stream for sink!\n");
3488 dc_result = dc_validate_stream(adev->dm.dc, stream);
3490 if (dc_result == DC_OK)
3493 DRM_DEBUG_KMS("Mode %dx%d (clk %d) failed DC validation with error %d\n",
3499 dc_stream_release(stream);
3502 /* TODO: error handling*/
3506 static const struct drm_connector_helper_funcs
3507 amdgpu_dm_connector_helper_funcs = {
3509 * If hotplugging a second bigger display in FB Con mode, bigger resolution
3510 * modes will be filtered by drm_mode_validate_size(), and those modes
3511 * are missing after user start lightdm. So we need to renew modes list.
3512 * in get_modes call back, not just return the modes count
3514 .get_modes = get_modes,
3515 .mode_valid = amdgpu_dm_connector_mode_valid,
3518 static void dm_crtc_helper_disable(struct drm_crtc *crtc)
3522 static int dm_crtc_helper_atomic_check(struct drm_crtc *crtc,
3523 struct drm_crtc_state *state)
3525 struct amdgpu_device *adev = crtc->dev->dev_private;
3526 struct dc *dc = adev->dm.dc;
3527 struct dm_crtc_state *dm_crtc_state = to_dm_crtc_state(state);
3530 if (unlikely(!dm_crtc_state->stream &&
3531 modeset_required(state, NULL, dm_crtc_state->stream))) {
3536 /* In some use cases, like reset, no stream is attached */
3537 if (!dm_crtc_state->stream)
3540 if (dc_validate_stream(dc, dm_crtc_state->stream) == DC_OK)
3546 static bool dm_crtc_helper_mode_fixup(struct drm_crtc *crtc,
3547 const struct drm_display_mode *mode,
3548 struct drm_display_mode *adjusted_mode)
3553 static const struct drm_crtc_helper_funcs amdgpu_dm_crtc_helper_funcs = {
3554 .disable = dm_crtc_helper_disable,
3555 .atomic_check = dm_crtc_helper_atomic_check,
3556 .mode_fixup = dm_crtc_helper_mode_fixup
3559 static void dm_encoder_helper_disable(struct drm_encoder *encoder)
3564 static int dm_encoder_helper_atomic_check(struct drm_encoder *encoder,
3565 struct drm_crtc_state *crtc_state,
3566 struct drm_connector_state *conn_state)
3571 const struct drm_encoder_helper_funcs amdgpu_dm_encoder_helper_funcs = {
3572 .disable = dm_encoder_helper_disable,
3573 .atomic_check = dm_encoder_helper_atomic_check
3576 static void dm_drm_plane_reset(struct drm_plane *plane)
3578 struct dm_plane_state *amdgpu_state = NULL;
3581 plane->funcs->atomic_destroy_state(plane, plane->state);
3583 amdgpu_state = kzalloc(sizeof(*amdgpu_state), GFP_KERNEL);
3584 WARN_ON(amdgpu_state == NULL);
3587 plane->state = &amdgpu_state->base;
3588 plane->state->plane = plane;
3589 plane->state->rotation = DRM_MODE_ROTATE_0;
3593 static struct drm_plane_state *
3594 dm_drm_plane_duplicate_state(struct drm_plane *plane)
3596 struct dm_plane_state *dm_plane_state, *old_dm_plane_state;
3598 old_dm_plane_state = to_dm_plane_state(plane->state);
3599 dm_plane_state = kzalloc(sizeof(*dm_plane_state), GFP_KERNEL);
3600 if (!dm_plane_state)
3603 __drm_atomic_helper_plane_duplicate_state(plane, &dm_plane_state->base);
3605 if (old_dm_plane_state->dc_state) {
3606 dm_plane_state->dc_state = old_dm_plane_state->dc_state;
3607 dc_plane_state_retain(dm_plane_state->dc_state);
3610 return &dm_plane_state->base;
3613 void dm_drm_plane_destroy_state(struct drm_plane *plane,
3614 struct drm_plane_state *state)
3616 struct dm_plane_state *dm_plane_state = to_dm_plane_state(state);
3618 if (dm_plane_state->dc_state)
3619 dc_plane_state_release(dm_plane_state->dc_state);
3621 drm_atomic_helper_plane_destroy_state(plane, state);
3624 static const struct drm_plane_funcs dm_plane_funcs = {
3625 .update_plane = drm_atomic_helper_update_plane,
3626 .disable_plane = drm_atomic_helper_disable_plane,
3627 .destroy = drm_primary_helper_destroy,
3628 .reset = dm_drm_plane_reset,
3629 .atomic_duplicate_state = dm_drm_plane_duplicate_state,
3630 .atomic_destroy_state = dm_drm_plane_destroy_state,
3633 static int dm_plane_helper_prepare_fb(struct drm_plane *plane,
3634 struct drm_plane_state *new_state)
3636 struct amdgpu_framebuffer *afb;
3637 struct drm_gem_object *obj;
3638 struct amdgpu_device *adev;
3639 struct amdgpu_bo *rbo;
3640 uint64_t chroma_addr = 0;
3641 struct dm_plane_state *dm_plane_state_new, *dm_plane_state_old;
3642 uint64_t tiling_flags, dcc_address;
3643 unsigned int awidth;
3647 dm_plane_state_old = to_dm_plane_state(plane->state);
3648 dm_plane_state_new = to_dm_plane_state(new_state);
3650 if (!new_state->fb) {
3651 DRM_DEBUG_DRIVER("No FB bound\n");
3655 afb = to_amdgpu_framebuffer(new_state->fb);
3656 obj = new_state->fb->obj[0];
3657 rbo = gem_to_amdgpu_bo(obj);
3658 adev = amdgpu_ttm_adev(rbo->tbo.bdev);
3659 r = amdgpu_bo_reserve(rbo, false);
3660 if (unlikely(r != 0))
3663 if (plane->type != DRM_PLANE_TYPE_CURSOR)
3664 domain = amdgpu_display_supported_domains(adev);
3666 domain = AMDGPU_GEM_DOMAIN_VRAM;
3668 r = amdgpu_bo_pin(rbo, domain);
3669 if (unlikely(r != 0)) {
3670 if (r != -ERESTARTSYS)
3671 DRM_ERROR("Failed to pin framebuffer with error %d\n", r);
3672 amdgpu_bo_unreserve(rbo);
3676 r = amdgpu_ttm_alloc_gart(&rbo->tbo);
3677 if (unlikely(r != 0)) {
3678 amdgpu_bo_unpin(rbo);
3679 amdgpu_bo_unreserve(rbo);
3680 DRM_ERROR("%p bind failed\n", rbo);
3684 amdgpu_bo_get_tiling_flags(rbo, &tiling_flags);
3686 amdgpu_bo_unreserve(rbo);
3688 afb->address = amdgpu_bo_gpu_offset(rbo);
3692 if (dm_plane_state_new->dc_state &&
3693 dm_plane_state_old->dc_state != dm_plane_state_new->dc_state) {
3694 struct dc_plane_state *plane_state = dm_plane_state_new->dc_state;
3696 if (plane_state->format < SURFACE_PIXEL_FORMAT_VIDEO_BEGIN) {
3697 plane_state->address.grph.addr.low_part = lower_32_bits(afb->address);
3698 plane_state->address.grph.addr.high_part = upper_32_bits(afb->address);
3701 get_dcc_address(afb->address, tiling_flags);
3702 plane_state->address.grph.meta_addr.low_part =
3703 lower_32_bits(dcc_address);
3704 plane_state->address.grph.meta_addr.high_part =
3705 upper_32_bits(dcc_address);
3707 awidth = ALIGN(new_state->fb->width, 64);
3708 plane_state->address.type = PLN_ADDR_TYPE_VIDEO_PROGRESSIVE;
3709 plane_state->address.video_progressive.luma_addr.low_part
3710 = lower_32_bits(afb->address);
3711 plane_state->address.video_progressive.luma_addr.high_part
3712 = upper_32_bits(afb->address);
3713 chroma_addr = afb->address + (u64)awidth * new_state->fb->height;
3714 plane_state->address.video_progressive.chroma_addr.low_part
3715 = lower_32_bits(chroma_addr);
3716 plane_state->address.video_progressive.chroma_addr.high_part
3717 = upper_32_bits(chroma_addr);
3724 static void dm_plane_helper_cleanup_fb(struct drm_plane *plane,
3725 struct drm_plane_state *old_state)
3727 struct amdgpu_bo *rbo;
3733 rbo = gem_to_amdgpu_bo(old_state->fb->obj[0]);
3734 r = amdgpu_bo_reserve(rbo, false);
3736 DRM_ERROR("failed to reserve rbo before unpin\n");
3740 amdgpu_bo_unpin(rbo);
3741 amdgpu_bo_unreserve(rbo);
3742 amdgpu_bo_unref(&rbo);
3745 static int dm_plane_atomic_check(struct drm_plane *plane,
3746 struct drm_plane_state *state)
3748 struct amdgpu_device *adev = plane->dev->dev_private;
3749 struct dc *dc = adev->dm.dc;
3750 struct dm_plane_state *dm_plane_state = to_dm_plane_state(state);
3752 if (!dm_plane_state->dc_state)
3755 if (!fill_rects_from_plane_state(state, dm_plane_state->dc_state))
3758 if (dc_validate_plane(dc, dm_plane_state->dc_state) == DC_OK)
3764 static int dm_plane_atomic_async_check(struct drm_plane *plane,
3765 struct drm_plane_state *new_plane_state)
3767 struct drm_plane_state *old_plane_state =
3768 drm_atomic_get_old_plane_state(new_plane_state->state, plane);
3770 /* Only support async updates on cursor planes. */
3771 if (plane->type != DRM_PLANE_TYPE_CURSOR)
3775 * DRM calls prepare_fb and cleanup_fb on new_plane_state for
3776 * async commits so don't allow fb changes.
3778 if (old_plane_state->fb != new_plane_state->fb)
3784 static void dm_plane_atomic_async_update(struct drm_plane *plane,
3785 struct drm_plane_state *new_state)
3787 struct drm_plane_state *old_state =
3788 drm_atomic_get_old_plane_state(new_state->state, plane);
3790 if (plane->state->fb != new_state->fb)
3791 drm_atomic_set_fb_for_plane(plane->state, new_state->fb);
3793 plane->state->src_x = new_state->src_x;
3794 plane->state->src_y = new_state->src_y;
3795 plane->state->src_w = new_state->src_w;
3796 plane->state->src_h = new_state->src_h;
3797 plane->state->crtc_x = new_state->crtc_x;
3798 plane->state->crtc_y = new_state->crtc_y;
3799 plane->state->crtc_w = new_state->crtc_w;
3800 plane->state->crtc_h = new_state->crtc_h;
3802 handle_cursor_update(plane, old_state);
3805 static const struct drm_plane_helper_funcs dm_plane_helper_funcs = {
3806 .prepare_fb = dm_plane_helper_prepare_fb,
3807 .cleanup_fb = dm_plane_helper_cleanup_fb,
3808 .atomic_check = dm_plane_atomic_check,
3809 .atomic_async_check = dm_plane_atomic_async_check,
3810 .atomic_async_update = dm_plane_atomic_async_update
3814 * TODO: these are currently initialized to rgb formats only.
3815 * For future use cases we should either initialize them dynamically based on
3816 * plane capabilities, or initialize this array to all formats, so internal drm
3817 * check will succeed, and let DC implement proper check
3819 static const uint32_t rgb_formats[] = {
3820 DRM_FORMAT_XRGB8888,
3821 DRM_FORMAT_ARGB8888,
3822 DRM_FORMAT_RGBA8888,
3823 DRM_FORMAT_XRGB2101010,
3824 DRM_FORMAT_XBGR2101010,
3825 DRM_FORMAT_ARGB2101010,
3826 DRM_FORMAT_ABGR2101010,
3827 DRM_FORMAT_XBGR8888,
3828 DRM_FORMAT_ABGR8888,
3831 static const uint32_t yuv_formats[] = {
3836 static const u32 cursor_formats[] = {
3840 static int amdgpu_dm_plane_init(struct amdgpu_display_manager *dm,
3841 struct drm_plane *plane,
3842 unsigned long possible_crtcs)
3846 switch (plane->type) {
3847 case DRM_PLANE_TYPE_PRIMARY:
3848 res = drm_universal_plane_init(
3854 ARRAY_SIZE(rgb_formats),
3855 NULL, plane->type, NULL);
3857 case DRM_PLANE_TYPE_OVERLAY:
3858 res = drm_universal_plane_init(
3864 ARRAY_SIZE(yuv_formats),
3865 NULL, plane->type, NULL);
3867 case DRM_PLANE_TYPE_CURSOR:
3868 res = drm_universal_plane_init(
3874 ARRAY_SIZE(cursor_formats),
3875 NULL, plane->type, NULL);
3879 drm_plane_helper_add(plane, &dm_plane_helper_funcs);
3881 /* Create (reset) the plane state */
3882 if (plane->funcs->reset)
3883 plane->funcs->reset(plane);
3889 static int amdgpu_dm_crtc_init(struct amdgpu_display_manager *dm,
3890 struct drm_plane *plane,
3891 uint32_t crtc_index)
3893 struct amdgpu_crtc *acrtc = NULL;
3894 struct drm_plane *cursor_plane;
3898 cursor_plane = kzalloc(sizeof(*cursor_plane), GFP_KERNEL);
3902 cursor_plane->type = DRM_PLANE_TYPE_CURSOR;
3903 res = amdgpu_dm_plane_init(dm, cursor_plane, 0);
3905 acrtc = kzalloc(sizeof(struct amdgpu_crtc), GFP_KERNEL);
3909 res = drm_crtc_init_with_planes(
3914 &amdgpu_dm_crtc_funcs, NULL);
3919 drm_crtc_helper_add(&acrtc->base, &amdgpu_dm_crtc_helper_funcs);
3921 /* Create (reset) the plane state */
3922 if (acrtc->base.funcs->reset)
3923 acrtc->base.funcs->reset(&acrtc->base);
3925 acrtc->max_cursor_width = dm->adev->dm.dc->caps.max_cursor_size;
3926 acrtc->max_cursor_height = dm->adev->dm.dc->caps.max_cursor_size;
3928 acrtc->crtc_id = crtc_index;
3929 acrtc->base.enabled = false;
3930 acrtc->otg_inst = -1;
3932 dm->adev->mode_info.crtcs[crtc_index] = acrtc;
3933 drm_crtc_enable_color_mgmt(&acrtc->base, MAX_COLOR_LUT_ENTRIES,
3934 true, MAX_COLOR_LUT_ENTRIES);
3935 drm_mode_crtc_set_gamma_size(&acrtc->base, MAX_COLOR_LEGACY_LUT_ENTRIES);
3941 kfree(cursor_plane);
3946 static int to_drm_connector_type(enum signal_type st)
3949 case SIGNAL_TYPE_HDMI_TYPE_A:
3950 return DRM_MODE_CONNECTOR_HDMIA;
3951 case SIGNAL_TYPE_EDP:
3952 return DRM_MODE_CONNECTOR_eDP;
3953 case SIGNAL_TYPE_LVDS:
3954 return DRM_MODE_CONNECTOR_LVDS;
3955 case SIGNAL_TYPE_RGB:
3956 return DRM_MODE_CONNECTOR_VGA;
3957 case SIGNAL_TYPE_DISPLAY_PORT:
3958 case SIGNAL_TYPE_DISPLAY_PORT_MST:
3959 return DRM_MODE_CONNECTOR_DisplayPort;
3960 case SIGNAL_TYPE_DVI_DUAL_LINK:
3961 case SIGNAL_TYPE_DVI_SINGLE_LINK:
3962 return DRM_MODE_CONNECTOR_DVID;
3963 case SIGNAL_TYPE_VIRTUAL:
3964 return DRM_MODE_CONNECTOR_VIRTUAL;
3967 return DRM_MODE_CONNECTOR_Unknown;
3971 static struct drm_encoder *amdgpu_dm_connector_to_encoder(struct drm_connector *connector)
3973 return drm_encoder_find(connector->dev, NULL, connector->encoder_ids[0]);
3976 static void amdgpu_dm_get_native_mode(struct drm_connector *connector)
3978 struct drm_encoder *encoder;
3979 struct amdgpu_encoder *amdgpu_encoder;
3981 encoder = amdgpu_dm_connector_to_encoder(connector);
3983 if (encoder == NULL)
3986 amdgpu_encoder = to_amdgpu_encoder(encoder);
3988 amdgpu_encoder->native_mode.clock = 0;
3990 if (!list_empty(&connector->probed_modes)) {
3991 struct drm_display_mode *preferred_mode = NULL;
3993 list_for_each_entry(preferred_mode,
3994 &connector->probed_modes,
3996 if (preferred_mode->type & DRM_MODE_TYPE_PREFERRED)
3997 amdgpu_encoder->native_mode = *preferred_mode;
4005 static struct drm_display_mode *
4006 amdgpu_dm_create_common_mode(struct drm_encoder *encoder,
4008 int hdisplay, int vdisplay)
4010 struct drm_device *dev = encoder->dev;
4011 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
4012 struct drm_display_mode *mode = NULL;
4013 struct drm_display_mode *native_mode = &amdgpu_encoder->native_mode;
4015 mode = drm_mode_duplicate(dev, native_mode);
4020 mode->hdisplay = hdisplay;
4021 mode->vdisplay = vdisplay;
4022 mode->type &= ~DRM_MODE_TYPE_PREFERRED;
4023 strscpy(mode->name, name, DRM_DISPLAY_MODE_LEN);
4029 static void amdgpu_dm_connector_add_common_modes(struct drm_encoder *encoder,
4030 struct drm_connector *connector)
4032 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
4033 struct drm_display_mode *mode = NULL;
4034 struct drm_display_mode *native_mode = &amdgpu_encoder->native_mode;
4035 struct amdgpu_dm_connector *amdgpu_dm_connector =
4036 to_amdgpu_dm_connector(connector);
4040 char name[DRM_DISPLAY_MODE_LEN];
4043 } common_modes[] = {
4044 { "640x480", 640, 480},
4045 { "800x600", 800, 600},
4046 { "1024x768", 1024, 768},
4047 { "1280x720", 1280, 720},
4048 { "1280x800", 1280, 800},
4049 {"1280x1024", 1280, 1024},
4050 { "1440x900", 1440, 900},
4051 {"1680x1050", 1680, 1050},
4052 {"1600x1200", 1600, 1200},
4053 {"1920x1080", 1920, 1080},
4054 {"1920x1200", 1920, 1200}
4057 n = ARRAY_SIZE(common_modes);
4059 for (i = 0; i < n; i++) {
4060 struct drm_display_mode *curmode = NULL;
4061 bool mode_existed = false;
4063 if (common_modes[i].w > native_mode->hdisplay ||
4064 common_modes[i].h > native_mode->vdisplay ||
4065 (common_modes[i].w == native_mode->hdisplay &&
4066 common_modes[i].h == native_mode->vdisplay))
4069 list_for_each_entry(curmode, &connector->probed_modes, head) {
4070 if (common_modes[i].w == curmode->hdisplay &&
4071 common_modes[i].h == curmode->vdisplay) {
4072 mode_existed = true;
4080 mode = amdgpu_dm_create_common_mode(encoder,
4081 common_modes[i].name, common_modes[i].w,
4083 drm_mode_probed_add(connector, mode);
4084 amdgpu_dm_connector->num_modes++;
4088 static void amdgpu_dm_connector_ddc_get_modes(struct drm_connector *connector,
4091 struct amdgpu_dm_connector *amdgpu_dm_connector =
4092 to_amdgpu_dm_connector(connector);
4095 /* empty probed_modes */
4096 INIT_LIST_HEAD(&connector->probed_modes);
4097 amdgpu_dm_connector->num_modes =
4098 drm_add_edid_modes(connector, edid);
4100 amdgpu_dm_get_native_mode(connector);
4102 amdgpu_dm_connector->num_modes = 0;
4106 static int amdgpu_dm_connector_get_modes(struct drm_connector *connector)
4108 struct amdgpu_dm_connector *amdgpu_dm_connector =
4109 to_amdgpu_dm_connector(connector);
4110 struct drm_encoder *encoder;
4111 struct edid *edid = amdgpu_dm_connector->edid;
4113 encoder = amdgpu_dm_connector_to_encoder(connector);
4115 if (!edid || !drm_edid_is_valid(edid)) {
4116 amdgpu_dm_connector->num_modes =
4117 drm_add_modes_noedid(connector, 640, 480);
4119 amdgpu_dm_connector_ddc_get_modes(connector, edid);
4120 amdgpu_dm_connector_add_common_modes(encoder, connector);
4122 amdgpu_dm_fbc_init(connector);
4124 return amdgpu_dm_connector->num_modes;
4127 void amdgpu_dm_connector_init_helper(struct amdgpu_display_manager *dm,
4128 struct amdgpu_dm_connector *aconnector,
4130 struct dc_link *link,
4133 struct amdgpu_device *adev = dm->ddev->dev_private;
4135 aconnector->connector_id = link_index;
4136 aconnector->dc_link = link;
4137 aconnector->base.interlace_allowed = false;
4138 aconnector->base.doublescan_allowed = false;
4139 aconnector->base.stereo_allowed = false;
4140 aconnector->base.dpms = DRM_MODE_DPMS_OFF;
4141 aconnector->hpd.hpd = AMDGPU_HPD_NONE; /* not used */
4142 mutex_init(&aconnector->hpd_lock);
4145 * configure support HPD hot plug connector_>polled default value is 0
4146 * which means HPD hot plug not supported
4148 switch (connector_type) {
4149 case DRM_MODE_CONNECTOR_HDMIA:
4150 aconnector->base.polled = DRM_CONNECTOR_POLL_HPD;
4151 aconnector->base.ycbcr_420_allowed =
4152 link->link_enc->features.hdmi_ycbcr420_supported ? true : false;
4154 case DRM_MODE_CONNECTOR_DisplayPort:
4155 aconnector->base.polled = DRM_CONNECTOR_POLL_HPD;
4156 aconnector->base.ycbcr_420_allowed =
4157 link->link_enc->features.dp_ycbcr420_supported ? true : false;
4159 case DRM_MODE_CONNECTOR_DVID:
4160 aconnector->base.polled = DRM_CONNECTOR_POLL_HPD;
4166 drm_object_attach_property(&aconnector->base.base,
4167 dm->ddev->mode_config.scaling_mode_property,
4168 DRM_MODE_SCALE_NONE);
4170 drm_object_attach_property(&aconnector->base.base,
4171 adev->mode_info.underscan_property,
4173 drm_object_attach_property(&aconnector->base.base,
4174 adev->mode_info.underscan_hborder_property,
4176 drm_object_attach_property(&aconnector->base.base,
4177 adev->mode_info.underscan_vborder_property,
4179 drm_object_attach_property(&aconnector->base.base,
4180 adev->mode_info.max_bpc_property,
4183 if (connector_type == DRM_MODE_CONNECTOR_eDP &&
4184 dc_is_dmcu_initialized(adev->dm.dc)) {
4185 drm_object_attach_property(&aconnector->base.base,
4186 adev->mode_info.abm_level_property, 0);
4189 if (connector_type == DRM_MODE_CONNECTOR_HDMIA ||
4190 connector_type == DRM_MODE_CONNECTOR_DisplayPort ||
4191 connector_type == DRM_MODE_CONNECTOR_eDP) {
4192 drm_connector_attach_vrr_capable_property(
4197 static int amdgpu_dm_i2c_xfer(struct i2c_adapter *i2c_adap,
4198 struct i2c_msg *msgs, int num)
4200 struct amdgpu_i2c_adapter *i2c = i2c_get_adapdata(i2c_adap);
4201 struct ddc_service *ddc_service = i2c->ddc_service;
4202 struct i2c_command cmd;
4206 cmd.payloads = kcalloc(num, sizeof(struct i2c_payload), GFP_KERNEL);
4211 cmd.number_of_payloads = num;
4212 cmd.engine = I2C_COMMAND_ENGINE_DEFAULT;
4215 for (i = 0; i < num; i++) {
4216 cmd.payloads[i].write = !(msgs[i].flags & I2C_M_RD);
4217 cmd.payloads[i].address = msgs[i].addr;
4218 cmd.payloads[i].length = msgs[i].len;
4219 cmd.payloads[i].data = msgs[i].buf;
4223 ddc_service->ctx->dc,
4224 ddc_service->ddc_pin->hw_info.ddc_channel,
4228 kfree(cmd.payloads);
4232 static u32 amdgpu_dm_i2c_func(struct i2c_adapter *adap)
4234 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
4237 static const struct i2c_algorithm amdgpu_dm_i2c_algo = {
4238 .master_xfer = amdgpu_dm_i2c_xfer,
4239 .functionality = amdgpu_dm_i2c_func,
4242 static struct amdgpu_i2c_adapter *
4243 create_i2c(struct ddc_service *ddc_service,
4247 struct amdgpu_device *adev = ddc_service->ctx->driver_context;
4248 struct amdgpu_i2c_adapter *i2c;
4250 i2c = kzalloc(sizeof(struct amdgpu_i2c_adapter), GFP_KERNEL);
4253 i2c->base.owner = THIS_MODULE;
4254 i2c->base.class = I2C_CLASS_DDC;
4255 i2c->base.dev.parent = &adev->pdev->dev;
4256 i2c->base.algo = &amdgpu_dm_i2c_algo;
4257 snprintf(i2c->base.name, sizeof(i2c->base.name), "AMDGPU DM i2c hw bus %d", link_index);
4258 i2c_set_adapdata(&i2c->base, i2c);
4259 i2c->ddc_service = ddc_service;
4260 i2c->ddc_service->ddc_pin->hw_info.ddc_channel = link_index;
4267 * Note: this function assumes that dc_link_detect() was called for the
4268 * dc_link which will be represented by this aconnector.
4270 static int amdgpu_dm_connector_init(struct amdgpu_display_manager *dm,
4271 struct amdgpu_dm_connector *aconnector,
4272 uint32_t link_index,
4273 struct amdgpu_encoder *aencoder)
4277 struct dc *dc = dm->dc;
4278 struct dc_link *link = dc_get_link_at_index(dc, link_index);
4279 struct amdgpu_i2c_adapter *i2c;
4281 link->priv = aconnector;
4283 DRM_DEBUG_DRIVER("%s()\n", __func__);
4285 i2c = create_i2c(link->ddc, link->link_index, &res);
4287 DRM_ERROR("Failed to create i2c adapter data\n");
4291 aconnector->i2c = i2c;
4292 res = i2c_add_adapter(&i2c->base);
4295 DRM_ERROR("Failed to register hw i2c %d\n", link->link_index);
4299 connector_type = to_drm_connector_type(link->connector_signal);
4301 res = drm_connector_init(
4304 &amdgpu_dm_connector_funcs,
4308 DRM_ERROR("connector_init failed\n");
4309 aconnector->connector_id = -1;
4313 drm_connector_helper_add(
4315 &amdgpu_dm_connector_helper_funcs);
4317 if (aconnector->base.funcs->reset)
4318 aconnector->base.funcs->reset(&aconnector->base);
4320 amdgpu_dm_connector_init_helper(
4327 drm_connector_attach_encoder(
4328 &aconnector->base, &aencoder->base);
4330 drm_connector_register(&aconnector->base);
4331 #if defined(CONFIG_DEBUG_FS)
4332 res = connector_debugfs_init(aconnector);
4334 DRM_ERROR("Failed to create debugfs for connector");
4339 if (connector_type == DRM_MODE_CONNECTOR_DisplayPort
4340 || connector_type == DRM_MODE_CONNECTOR_eDP)
4341 amdgpu_dm_initialize_dp_connector(dm, aconnector);
4346 aconnector->i2c = NULL;
4351 int amdgpu_dm_get_encoder_crtc_mask(struct amdgpu_device *adev)
4353 switch (adev->mode_info.num_crtc) {
4370 static int amdgpu_dm_encoder_init(struct drm_device *dev,
4371 struct amdgpu_encoder *aencoder,
4372 uint32_t link_index)
4374 struct amdgpu_device *adev = dev->dev_private;
4376 int res = drm_encoder_init(dev,
4378 &amdgpu_dm_encoder_funcs,
4379 DRM_MODE_ENCODER_TMDS,
4382 aencoder->base.possible_crtcs = amdgpu_dm_get_encoder_crtc_mask(adev);
4385 aencoder->encoder_id = link_index;
4387 aencoder->encoder_id = -1;
4389 drm_encoder_helper_add(&aencoder->base, &amdgpu_dm_encoder_helper_funcs);
4394 static void manage_dm_interrupts(struct amdgpu_device *adev,
4395 struct amdgpu_crtc *acrtc,
4399 * this is not correct translation but will work as soon as VBLANK
4400 * constant is the same as PFLIP
4403 amdgpu_display_crtc_idx_to_irq_type(
4408 drm_crtc_vblank_on(&acrtc->base);
4411 &adev->pageflip_irq,
4417 &adev->pageflip_irq,
4419 drm_crtc_vblank_off(&acrtc->base);
4424 is_scaling_state_different(const struct dm_connector_state *dm_state,
4425 const struct dm_connector_state *old_dm_state)
4427 if (dm_state->scaling != old_dm_state->scaling)
4429 if (!dm_state->underscan_enable && old_dm_state->underscan_enable) {
4430 if (old_dm_state->underscan_hborder != 0 && old_dm_state->underscan_vborder != 0)
4432 } else if (dm_state->underscan_enable && !old_dm_state->underscan_enable) {
4433 if (dm_state->underscan_hborder != 0 && dm_state->underscan_vborder != 0)
4435 } else if (dm_state->underscan_hborder != old_dm_state->underscan_hborder ||
4436 dm_state->underscan_vborder != old_dm_state->underscan_vborder)
4441 static void remove_stream(struct amdgpu_device *adev,
4442 struct amdgpu_crtc *acrtc,
4443 struct dc_stream_state *stream)
4445 /* this is the update mode case */
4447 acrtc->otg_inst = -1;
4448 acrtc->enabled = false;
4451 static int get_cursor_position(struct drm_plane *plane, struct drm_crtc *crtc,
4452 struct dc_cursor_position *position)
4454 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
4456 int xorigin = 0, yorigin = 0;
4458 if (!crtc || !plane->state->fb) {
4459 position->enable = false;
4465 if ((plane->state->crtc_w > amdgpu_crtc->max_cursor_width) ||
4466 (plane->state->crtc_h > amdgpu_crtc->max_cursor_height)) {
4467 DRM_ERROR("%s: bad cursor width or height %d x %d\n",
4469 plane->state->crtc_w,
4470 plane->state->crtc_h);
4474 x = plane->state->crtc_x;
4475 y = plane->state->crtc_y;
4476 /* avivo cursor are offset into the total surface */
4477 x += crtc->primary->state->src_x >> 16;
4478 y += crtc->primary->state->src_y >> 16;
4480 xorigin = min(-x, amdgpu_crtc->max_cursor_width - 1);
4484 yorigin = min(-y, amdgpu_crtc->max_cursor_height - 1);
4487 position->enable = true;
4490 position->x_hotspot = xorigin;
4491 position->y_hotspot = yorigin;
4496 static void handle_cursor_update(struct drm_plane *plane,
4497 struct drm_plane_state *old_plane_state)
4499 struct amdgpu_device *adev = plane->dev->dev_private;
4500 struct amdgpu_framebuffer *afb = to_amdgpu_framebuffer(plane->state->fb);
4501 struct drm_crtc *crtc = afb ? plane->state->crtc : old_plane_state->crtc;
4502 struct dm_crtc_state *crtc_state = crtc ? to_dm_crtc_state(crtc->state) : NULL;
4503 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
4504 uint64_t address = afb ? afb->address : 0;
4505 struct dc_cursor_position position;
4506 struct dc_cursor_attributes attributes;
4509 if (!plane->state->fb && !old_plane_state->fb)
4512 DRM_DEBUG_DRIVER("%s: crtc_id=%d with size %d to %d\n",
4514 amdgpu_crtc->crtc_id,
4515 plane->state->crtc_w,
4516 plane->state->crtc_h);
4518 ret = get_cursor_position(plane, crtc, &position);
4522 if (!position.enable) {
4523 /* turn off cursor */
4524 if (crtc_state && crtc_state->stream) {
4525 mutex_lock(&adev->dm.dc_lock);
4526 dc_stream_set_cursor_position(crtc_state->stream,
4528 mutex_unlock(&adev->dm.dc_lock);
4533 amdgpu_crtc->cursor_width = plane->state->crtc_w;
4534 amdgpu_crtc->cursor_height = plane->state->crtc_h;
4536 attributes.address.high_part = upper_32_bits(address);
4537 attributes.address.low_part = lower_32_bits(address);
4538 attributes.width = plane->state->crtc_w;
4539 attributes.height = plane->state->crtc_h;
4540 attributes.color_format = CURSOR_MODE_COLOR_PRE_MULTIPLIED_ALPHA;
4541 attributes.rotation_angle = 0;
4542 attributes.attribute_flags.value = 0;
4544 attributes.pitch = attributes.width;
4546 if (crtc_state->stream) {
4547 mutex_lock(&adev->dm.dc_lock);
4548 if (!dc_stream_set_cursor_attributes(crtc_state->stream,
4550 DRM_ERROR("DC failed to set cursor attributes\n");
4552 if (!dc_stream_set_cursor_position(crtc_state->stream,
4554 DRM_ERROR("DC failed to set cursor position\n");
4555 mutex_unlock(&adev->dm.dc_lock);
4559 static void prepare_flip_isr(struct amdgpu_crtc *acrtc)
4562 assert_spin_locked(&acrtc->base.dev->event_lock);
4563 WARN_ON(acrtc->event);
4565 acrtc->event = acrtc->base.state->event;
4567 /* Set the flip status */
4568 acrtc->pflip_status = AMDGPU_FLIP_SUBMITTED;
4570 /* Mark this event as consumed */
4571 acrtc->base.state->event = NULL;
4573 DRM_DEBUG_DRIVER("crtc:%d, pflip_stat:AMDGPU_FLIP_SUBMITTED\n",
4577 static void update_freesync_state_on_stream(
4578 struct amdgpu_display_manager *dm,
4579 struct dm_crtc_state *new_crtc_state,
4580 struct dc_stream_state *new_stream,
4581 struct dc_plane_state *surface,
4582 u32 flip_timestamp_in_us)
4584 struct mod_vrr_params vrr_params = new_crtc_state->vrr_params;
4585 struct dc_info_packet vrr_infopacket = {0};
4586 struct mod_freesync_config config = new_crtc_state->freesync_config;
4592 * TODO: Determine why min/max totals and vrefresh can be 0 here.
4593 * For now it's sufficient to just guard against these conditions.
4596 if (!new_stream->timing.h_total || !new_stream->timing.v_total)
4599 if (new_crtc_state->vrr_supported &&
4600 config.min_refresh_in_uhz &&
4601 config.max_refresh_in_uhz) {
4602 config.state = new_crtc_state->base.vrr_enabled ?
4603 VRR_STATE_ACTIVE_VARIABLE :
4606 config.state = VRR_STATE_UNSUPPORTED;
4609 mod_freesync_build_vrr_params(dm->freesync_module,
4611 &config, &vrr_params);
4614 mod_freesync_handle_preflip(
4615 dm->freesync_module,
4618 flip_timestamp_in_us,
4622 mod_freesync_build_vrr_infopacket(
4623 dm->freesync_module,
4627 TRANSFER_FUNC_UNKNOWN,
4630 new_crtc_state->freesync_timing_changed |=
4631 (memcmp(&new_crtc_state->vrr_params.adjust,
4633 sizeof(vrr_params.adjust)) != 0);
4635 new_crtc_state->freesync_vrr_info_changed |=
4636 (memcmp(&new_crtc_state->vrr_infopacket,
4638 sizeof(vrr_infopacket)) != 0);
4640 new_crtc_state->vrr_params = vrr_params;
4641 new_crtc_state->vrr_infopacket = vrr_infopacket;
4643 new_stream->adjust = new_crtc_state->vrr_params.adjust;
4644 new_stream->vrr_infopacket = vrr_infopacket;
4646 if (new_crtc_state->freesync_vrr_info_changed)
4647 DRM_DEBUG_KMS("VRR packet update: crtc=%u enabled=%d state=%d",
4648 new_crtc_state->base.crtc->base.id,
4649 (int)new_crtc_state->base.vrr_enabled,
4650 (int)vrr_params.state);
4653 static void amdgpu_dm_commit_planes(struct drm_atomic_state *state,
4654 struct dc_state *dc_state,
4655 struct drm_device *dev,
4656 struct amdgpu_display_manager *dm,
4657 struct drm_crtc *pcrtc,
4658 bool *wait_for_vblank)
4661 uint64_t timestamp_ns;
4662 struct drm_plane *plane;
4663 struct drm_plane_state *old_plane_state, *new_plane_state;
4664 struct amdgpu_crtc *acrtc_attach = to_amdgpu_crtc(pcrtc);
4665 struct drm_crtc_state *new_pcrtc_state =
4666 drm_atomic_get_new_crtc_state(state, pcrtc);
4667 struct dm_crtc_state *acrtc_state = to_dm_crtc_state(new_pcrtc_state);
4668 struct dm_crtc_state *dm_old_crtc_state =
4669 to_dm_crtc_state(drm_atomic_get_old_crtc_state(state, pcrtc));
4670 int flip_count = 0, planes_count = 0, vpos, hpos;
4671 unsigned long flags;
4672 struct amdgpu_bo *abo;
4673 uint64_t tiling_flags, dcc_address;
4674 uint32_t target, target_vblank;
4675 uint64_t last_flip_vblank;
4676 bool vrr_active = acrtc_state->freesync_config.state == VRR_STATE_ACTIVE_VARIABLE;
4679 struct dc_surface_update surface_updates[MAX_SURFACES];
4680 struct dc_flip_addrs flip_addrs[MAX_SURFACES];
4681 struct dc_stream_update stream_update;
4685 struct dc_surface_update surface_updates[MAX_SURFACES];
4686 struct dc_plane_info plane_infos[MAX_SURFACES];
4687 struct dc_scaling_info scaling_infos[MAX_SURFACES];
4688 struct dc_stream_update stream_update;
4691 flip = kzalloc(sizeof(*flip), GFP_KERNEL);
4692 full = kzalloc(sizeof(*full), GFP_KERNEL);
4694 if (!flip || !full) {
4695 dm_error("Failed to allocate update bundles\n");
4699 /* update planes when needed */
4700 for_each_oldnew_plane_in_state(state, plane, old_plane_state, new_plane_state, i) {
4701 struct drm_crtc *crtc = new_plane_state->crtc;
4702 struct drm_crtc_state *new_crtc_state;
4703 struct drm_framebuffer *fb = new_plane_state->fb;
4704 struct amdgpu_framebuffer *afb = to_amdgpu_framebuffer(fb);
4706 struct dc_plane_state *dc_plane;
4707 struct dm_plane_state *dm_new_plane_state = to_dm_plane_state(new_plane_state);
4709 /* Cursor plane is handled after stream updates */
4710 if (plane->type == DRM_PLANE_TYPE_CURSOR)
4713 if (!fb || !crtc || pcrtc != crtc)
4716 new_crtc_state = drm_atomic_get_new_crtc_state(state, crtc);
4717 if (!new_crtc_state->active)
4720 pflip_needed = old_plane_state->fb &&
4721 old_plane_state->fb != new_plane_state->fb;
4723 dc_plane = dm_new_plane_state->dc_state;
4727 * Assume even ONE crtc with immediate flip means
4728 * entire can't wait for VBLANK
4729 * TODO Check if it's correct
4731 if (new_pcrtc_state->pageflip_flags & DRM_MODE_PAGE_FLIP_ASYNC)
4732 *wait_for_vblank = false;
4735 * TODO This might fail and hence better not used, wait
4736 * explicitly on fences instead
4737 * and in general should be called for
4738 * blocking commit to as per framework helpers
4740 abo = gem_to_amdgpu_bo(fb->obj[0]);
4741 r = amdgpu_bo_reserve(abo, true);
4742 if (unlikely(r != 0))
4743 DRM_ERROR("failed to reserve buffer before flip\n");
4746 * Wait for all fences on this FB. Do limited wait to avoid
4747 * deadlock during GPU reset when this fence will not signal
4748 * but we hold reservation lock for the BO.
4750 r = reservation_object_wait_timeout_rcu(abo->tbo.resv,
4752 msecs_to_jiffies(5000));
4753 if (unlikely(r == 0))
4754 DRM_ERROR("Waiting for fences timed out.");
4758 amdgpu_bo_get_tiling_flags(abo, &tiling_flags);
4760 amdgpu_bo_unreserve(abo);
4762 flip->flip_addrs[flip_count].address.grph.addr.low_part = lower_32_bits(afb->address);
4763 flip->flip_addrs[flip_count].address.grph.addr.high_part = upper_32_bits(afb->address);
4765 dcc_address = get_dcc_address(afb->address, tiling_flags);
4766 flip->flip_addrs[flip_count].address.grph.meta_addr.low_part = lower_32_bits(dcc_address);
4767 flip->flip_addrs[flip_count].address.grph.meta_addr.high_part = upper_32_bits(dcc_address);
4769 flip->flip_addrs[flip_count].flip_immediate =
4770 (crtc->state->pageflip_flags & DRM_MODE_PAGE_FLIP_ASYNC) != 0;
4772 timestamp_ns = ktime_get_ns();
4773 flip->flip_addrs[flip_count].flip_timestamp_in_us = div_u64(timestamp_ns, 1000);
4774 flip->surface_updates[flip_count].flip_addr = &flip->flip_addrs[flip_count];
4775 flip->surface_updates[flip_count].surface = dc_plane;
4777 if (!flip->surface_updates[flip_count].surface) {
4778 DRM_ERROR("No surface for CRTC: id=%d\n",
4779 acrtc_attach->crtc_id);
4783 if (plane == pcrtc->primary)
4784 update_freesync_state_on_stream(
4787 acrtc_state->stream,
4789 flip->flip_addrs[flip_count].flip_timestamp_in_us);
4791 DRM_DEBUG_DRIVER("%s Flipping to hi: 0x%x, low: 0x%x\n",
4793 flip->flip_addrs[flip_count].address.grph.addr.high_part,
4794 flip->flip_addrs[flip_count].address.grph.addr.low_part);
4799 full->surface_updates[planes_count].surface = dc_plane;
4800 if (new_pcrtc_state->color_mgmt_changed) {
4801 full->surface_updates[planes_count].gamma = dc_plane->gamma_correction;
4802 full->surface_updates[planes_count].in_transfer_func = dc_plane->in_transfer_func;
4806 full->scaling_infos[planes_count].scaling_quality = dc_plane->scaling_quality;
4807 full->scaling_infos[planes_count].src_rect = dc_plane->src_rect;
4808 full->scaling_infos[planes_count].dst_rect = dc_plane->dst_rect;
4809 full->scaling_infos[planes_count].clip_rect = dc_plane->clip_rect;
4810 full->surface_updates[planes_count].scaling_info = &full->scaling_infos[planes_count];
4813 full->plane_infos[planes_count].color_space = dc_plane->color_space;
4814 full->plane_infos[planes_count].format = dc_plane->format;
4815 full->plane_infos[planes_count].plane_size = dc_plane->plane_size;
4816 full->plane_infos[planes_count].rotation = dc_plane->rotation;
4817 full->plane_infos[planes_count].horizontal_mirror = dc_plane->horizontal_mirror;
4818 full->plane_infos[planes_count].stereo_format = dc_plane->stereo_format;
4819 full->plane_infos[planes_count].tiling_info = dc_plane->tiling_info;
4820 full->plane_infos[planes_count].visible = dc_plane->visible;
4821 full->plane_infos[planes_count].per_pixel_alpha = dc_plane->per_pixel_alpha;
4822 full->plane_infos[planes_count].dcc = dc_plane->dcc;
4823 full->surface_updates[planes_count].plane_info = &full->plane_infos[planes_count];
4830 * TODO: For proper atomic behaviour, we should be calling into DC once with
4831 * all the changes. However, DC refuses to do pageflips and non-pageflip
4832 * changes in the same call. Change DC to respect atomic behaviour,
4833 * hopefully eliminating dc_*_update structs in their entirety.
4837 /* Use old throttling in non-vrr fixed refresh rate mode
4838 * to keep flip scheduling based on target vblank counts
4839 * working in a backwards compatible way, e.g., for
4840 * clients using the GLX_OML_sync_control extension or
4841 * DRI3/Present extension with defined target_msc.
4843 last_flip_vblank = drm_crtc_vblank_count(pcrtc);
4846 /* For variable refresh rate mode only:
4847 * Get vblank of last completed flip to avoid > 1 vrr
4848 * flips per video frame by use of throttling, but allow
4849 * flip programming anywhere in the possibly large
4850 * variable vrr vblank interval for fine-grained flip
4851 * timing control and more opportunity to avoid stutter
4852 * on late submission of flips.
4854 spin_lock_irqsave(&pcrtc->dev->event_lock, flags);
4855 last_flip_vblank = acrtc_attach->last_flip_vblank;
4856 spin_unlock_irqrestore(&pcrtc->dev->event_lock, flags);
4859 target = (uint32_t)last_flip_vblank + *wait_for_vblank;
4861 /* Prepare wait for target vblank early - before the fence-waits */
4862 target_vblank = target - (uint32_t)drm_crtc_vblank_count(pcrtc) +
4863 amdgpu_get_vblank_counter_kms(pcrtc->dev, acrtc_attach->crtc_id);
4866 * Wait until we're out of the vertical blank period before the one
4867 * targeted by the flip
4869 while ((acrtc_attach->enabled &&
4870 (amdgpu_display_get_crtc_scanoutpos(dm->ddev, acrtc_attach->crtc_id,
4871 0, &vpos, &hpos, NULL,
4872 NULL, &pcrtc->hwmode)
4873 & (DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_IN_VBLANK)) ==
4874 (DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_IN_VBLANK) &&
4875 (int)(target_vblank -
4876 amdgpu_get_vblank_counter_kms(dm->ddev, acrtc_attach->crtc_id)) > 0)) {
4877 usleep_range(1000, 1100);
4880 if (acrtc_attach->base.state->event) {
4881 drm_crtc_vblank_get(pcrtc);
4883 spin_lock_irqsave(&pcrtc->dev->event_lock, flags);
4885 WARN_ON(acrtc_attach->pflip_status != AMDGPU_FLIP_NONE);
4886 prepare_flip_isr(acrtc_attach);
4888 spin_unlock_irqrestore(&pcrtc->dev->event_lock, flags);
4891 if (acrtc_state->stream) {
4893 if (acrtc_state->freesync_timing_changed)
4894 flip->stream_update.adjust =
4895 &acrtc_state->stream->adjust;
4897 if (acrtc_state->freesync_vrr_info_changed)
4898 flip->stream_update.vrr_infopacket =
4899 &acrtc_state->stream->vrr_infopacket;
4902 mutex_lock(&dm->dc_lock);
4903 dc_commit_updates_for_stream(dm->dc,
4904 flip->surface_updates,
4906 acrtc_state->stream,
4907 &flip->stream_update,
4909 mutex_unlock(&dm->dc_lock);
4913 if (new_pcrtc_state->mode_changed) {
4914 full->stream_update.src = acrtc_state->stream->src;
4915 full->stream_update.dst = acrtc_state->stream->dst;
4918 if (new_pcrtc_state->color_mgmt_changed)
4919 full->stream_update.out_transfer_func = acrtc_state->stream->out_transfer_func;
4921 acrtc_state->stream->abm_level = acrtc_state->abm_level;
4922 if (acrtc_state->abm_level != dm_old_crtc_state->abm_level)
4923 full->stream_update.abm_level = &acrtc_state->abm_level;
4925 mutex_lock(&dm->dc_lock);
4926 dc_commit_updates_for_stream(dm->dc,
4927 full->surface_updates,
4929 acrtc_state->stream,
4930 &full->stream_update,
4932 mutex_unlock(&dm->dc_lock);
4935 for_each_oldnew_plane_in_state(state, plane, old_plane_state, new_plane_state, i)
4936 if (plane->type == DRM_PLANE_TYPE_CURSOR)
4937 handle_cursor_update(plane, old_plane_state);
4945 * amdgpu_dm_crtc_copy_transient_flags - copy mirrored flags from DRM to DC
4946 * @crtc_state: the DRM CRTC state
4947 * @stream_state: the DC stream state.
4949 * Copy the mirrored transient state flags from DRM, to DC. It is used to bring
4950 * a dc_stream_state's flags in sync with a drm_crtc_state's flags.
4952 static void amdgpu_dm_crtc_copy_transient_flags(struct drm_crtc_state *crtc_state,
4953 struct dc_stream_state *stream_state)
4955 stream_state->mode_changed =
4956 crtc_state->mode_changed || crtc_state->active_changed;
4959 static int amdgpu_dm_atomic_commit(struct drm_device *dev,
4960 struct drm_atomic_state *state,
4963 struct drm_crtc *crtc;
4964 struct drm_crtc_state *old_crtc_state, *new_crtc_state;
4965 struct amdgpu_device *adev = dev->dev_private;
4969 * We evade vblanks and pflips on crtc that
4970 * should be changed. We do it here to flush & disable
4971 * interrupts before drm_swap_state is called in drm_atomic_helper_commit
4972 * it will update crtc->dm_crtc_state->stream pointer which is used in
4975 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
4976 struct dm_crtc_state *dm_old_crtc_state = to_dm_crtc_state(old_crtc_state);
4977 struct dm_crtc_state *dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
4978 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
4980 if (drm_atomic_crtc_needs_modeset(new_crtc_state)
4981 && dm_old_crtc_state->stream) {
4983 * If the stream is removed and CRC capture was
4984 * enabled on the CRTC the extra vblank reference
4985 * needs to be dropped since CRC capture will be
4988 if (!dm_new_crtc_state->stream
4989 && dm_new_crtc_state->crc_enabled) {
4990 drm_crtc_vblank_put(crtc);
4991 dm_new_crtc_state->crc_enabled = false;
4994 manage_dm_interrupts(adev, acrtc, false);
4998 * Add check here for SoC's that support hardware cursor plane, to
4999 * unset legacy_cursor_update
5002 return drm_atomic_helper_commit(dev, state, nonblock);
5004 /*TODO Handle EINTR, reenable IRQ*/
5008 * amdgpu_dm_atomic_commit_tail() - AMDgpu DM's commit tail implementation.
5009 * @state: The atomic state to commit
5011 * This will tell DC to commit the constructed DC state from atomic_check,
5012 * programming the hardware. Any failures here implies a hardware failure, since
5013 * atomic check should have filtered anything non-kosher.
5015 static void amdgpu_dm_atomic_commit_tail(struct drm_atomic_state *state)
5017 struct drm_device *dev = state->dev;
5018 struct amdgpu_device *adev = dev->dev_private;
5019 struct amdgpu_display_manager *dm = &adev->dm;
5020 struct dm_atomic_state *dm_state;
5021 struct dc_state *dc_state = NULL, *dc_state_temp = NULL;
5023 struct drm_crtc *crtc;
5024 struct drm_crtc_state *old_crtc_state, *new_crtc_state;
5025 unsigned long flags;
5026 bool wait_for_vblank = true;
5027 struct drm_connector *connector;
5028 struct drm_connector_state *old_con_state, *new_con_state;
5029 struct dm_crtc_state *dm_old_crtc_state, *dm_new_crtc_state;
5030 int crtc_disable_count = 0;
5032 drm_atomic_helper_update_legacy_modeset_state(dev, state);
5034 dm_state = dm_atomic_get_new_state(state);
5035 if (dm_state && dm_state->context) {
5036 dc_state = dm_state->context;
5038 /* No state changes, retain current state. */
5039 dc_state_temp = dc_create_state();
5040 ASSERT(dc_state_temp);
5041 dc_state = dc_state_temp;
5042 dc_resource_state_copy_construct_current(dm->dc, dc_state);
5045 /* update changed items */
5046 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
5047 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
5049 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
5050 dm_old_crtc_state = to_dm_crtc_state(old_crtc_state);
5053 "amdgpu_crtc id:%d crtc_state_flags: enable:%d, active:%d, "
5054 "planes_changed:%d, mode_changed:%d,active_changed:%d,"
5055 "connectors_changed:%d\n",
5057 new_crtc_state->enable,
5058 new_crtc_state->active,
5059 new_crtc_state->planes_changed,
5060 new_crtc_state->mode_changed,
5061 new_crtc_state->active_changed,
5062 new_crtc_state->connectors_changed);
5064 /* Copy all transient state flags into dc state */
5065 if (dm_new_crtc_state->stream) {
5066 amdgpu_dm_crtc_copy_transient_flags(&dm_new_crtc_state->base,
5067 dm_new_crtc_state->stream);
5070 /* handles headless hotplug case, updating new_state and
5071 * aconnector as needed
5074 if (modeset_required(new_crtc_state, dm_new_crtc_state->stream, dm_old_crtc_state->stream)) {
5076 DRM_DEBUG_DRIVER("Atomic commit: SET crtc id %d: [%p]\n", acrtc->crtc_id, acrtc);
5078 if (!dm_new_crtc_state->stream) {
5080 * this could happen because of issues with
5081 * userspace notifications delivery.
5082 * In this case userspace tries to set mode on
5083 * display which is disconnected in fact.
5084 * dc_sink is NULL in this case on aconnector.
5085 * We expect reset mode will come soon.
5087 * This can also happen when unplug is done
5088 * during resume sequence ended
5090 * In this case, we want to pretend we still
5091 * have a sink to keep the pipe running so that
5092 * hw state is consistent with the sw state
5094 DRM_DEBUG_DRIVER("%s: Failed to create new stream for crtc %d\n",
5095 __func__, acrtc->base.base.id);
5099 if (dm_old_crtc_state->stream)
5100 remove_stream(adev, acrtc, dm_old_crtc_state->stream);
5102 pm_runtime_get_noresume(dev->dev);
5104 acrtc->enabled = true;
5105 acrtc->hw_mode = new_crtc_state->mode;
5106 crtc->hwmode = new_crtc_state->mode;
5107 } else if (modereset_required(new_crtc_state)) {
5108 DRM_DEBUG_DRIVER("Atomic commit: RESET. crtc id %d:[%p]\n", acrtc->crtc_id, acrtc);
5110 /* i.e. reset mode */
5111 if (dm_old_crtc_state->stream)
5112 remove_stream(adev, acrtc, dm_old_crtc_state->stream);
5114 } /* for_each_crtc_in_state() */
5117 dm_enable_per_frame_crtc_master_sync(dc_state);
5118 mutex_lock(&dm->dc_lock);
5119 WARN_ON(!dc_commit_state(dm->dc, dc_state));
5120 mutex_unlock(&dm->dc_lock);
5123 for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) {
5124 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
5126 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
5128 if (dm_new_crtc_state->stream != NULL) {
5129 const struct dc_stream_status *status =
5130 dc_stream_get_status(dm_new_crtc_state->stream);
5133 status = dc_stream_get_status_from_state(dc_state,
5134 dm_new_crtc_state->stream);
5137 DC_ERR("got no status for stream %p on acrtc%p\n", dm_new_crtc_state->stream, acrtc);
5139 acrtc->otg_inst = status->primary_otg_inst;
5143 /* Handle connector state changes */
5144 for_each_oldnew_connector_in_state(state, connector, old_con_state, new_con_state, i) {
5145 struct dm_connector_state *dm_new_con_state = to_dm_connector_state(new_con_state);
5146 struct dm_connector_state *dm_old_con_state = to_dm_connector_state(old_con_state);
5147 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(dm_new_con_state->base.crtc);
5148 struct dc_surface_update dummy_updates[MAX_SURFACES];
5149 struct dc_stream_update stream_update;
5150 struct dc_stream_status *status = NULL;
5152 memset(&dummy_updates, 0, sizeof(dummy_updates));
5153 memset(&stream_update, 0, sizeof(stream_update));
5156 new_crtc_state = drm_atomic_get_new_crtc_state(state, &acrtc->base);
5157 old_crtc_state = drm_atomic_get_old_crtc_state(state, &acrtc->base);
5160 /* Skip any modesets/resets */
5161 if (!acrtc || drm_atomic_crtc_needs_modeset(new_crtc_state))
5164 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
5165 dm_old_crtc_state = to_dm_crtc_state(old_crtc_state);
5167 if (!is_scaling_state_different(dm_new_con_state, dm_old_con_state) &&
5168 (dm_new_crtc_state->abm_level == dm_old_crtc_state->abm_level))
5171 if (is_scaling_state_different(dm_new_con_state, dm_old_con_state)) {
5172 update_stream_scaling_settings(&dm_new_con_state->base.crtc->mode,
5173 dm_new_con_state, (struct dc_stream_state *)dm_new_crtc_state->stream);
5175 stream_update.src = dm_new_crtc_state->stream->src;
5176 stream_update.dst = dm_new_crtc_state->stream->dst;
5179 if (dm_new_crtc_state->abm_level != dm_old_crtc_state->abm_level) {
5180 dm_new_crtc_state->stream->abm_level = dm_new_crtc_state->abm_level;
5182 stream_update.abm_level = &dm_new_crtc_state->abm_level;
5185 status = dc_stream_get_status(dm_new_crtc_state->stream);
5187 WARN_ON(!status->plane_count);
5190 * TODO: DC refuses to perform stream updates without a dc_surface_update.
5191 * Here we create an empty update on each plane.
5192 * To fix this, DC should permit updating only stream properties.
5194 for (j = 0; j < status->plane_count; j++)
5195 dummy_updates[j].surface = status->plane_states[0];
5198 mutex_lock(&dm->dc_lock);
5199 dc_commit_updates_for_stream(dm->dc,
5201 status->plane_count,
5202 dm_new_crtc_state->stream,
5205 mutex_unlock(&dm->dc_lock);
5208 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state,
5209 new_crtc_state, i) {
5211 * loop to enable interrupts on newly arrived crtc
5213 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
5214 bool modeset_needed;
5216 if (old_crtc_state->active && !new_crtc_state->active)
5217 crtc_disable_count++;
5219 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
5220 dm_old_crtc_state = to_dm_crtc_state(old_crtc_state);
5221 modeset_needed = modeset_required(
5223 dm_new_crtc_state->stream,
5224 dm_old_crtc_state->stream);
5226 if (dm_new_crtc_state->stream == NULL || !modeset_needed)
5229 manage_dm_interrupts(adev, acrtc, true);
5231 #ifdef CONFIG_DEBUG_FS
5232 /* The stream has changed so CRC capture needs to re-enabled. */
5233 if (dm_new_crtc_state->crc_enabled)
5234 amdgpu_dm_crtc_set_crc_source(crtc, "auto");
5238 /* update planes when needed per crtc*/
5239 for_each_new_crtc_in_state(state, crtc, new_crtc_state, j) {
5240 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
5242 if (dm_new_crtc_state->stream)
5243 amdgpu_dm_commit_planes(state, dc_state, dev,
5244 dm, crtc, &wait_for_vblank);
5249 * send vblank event on all events not handled in flip and
5250 * mark consumed event for drm_atomic_helper_commit_hw_done
5252 spin_lock_irqsave(&adev->ddev->event_lock, flags);
5253 for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) {
5255 if (new_crtc_state->event)
5256 drm_send_event_locked(dev, &new_crtc_state->event->base);
5258 new_crtc_state->event = NULL;
5260 spin_unlock_irqrestore(&adev->ddev->event_lock, flags);
5262 /* Signal HW programming completion */
5263 drm_atomic_helper_commit_hw_done(state);
5265 if (wait_for_vblank)
5266 drm_atomic_helper_wait_for_flip_done(dev, state);
5268 drm_atomic_helper_cleanup_planes(dev, state);
5271 * Finally, drop a runtime PM reference for each newly disabled CRTC,
5272 * so we can put the GPU into runtime suspend if we're not driving any
5275 for (i = 0; i < crtc_disable_count; i++)
5276 pm_runtime_put_autosuspend(dev->dev);
5277 pm_runtime_mark_last_busy(dev->dev);
5280 dc_release_state(dc_state_temp);
5284 static int dm_force_atomic_commit(struct drm_connector *connector)
5287 struct drm_device *ddev = connector->dev;
5288 struct drm_atomic_state *state = drm_atomic_state_alloc(ddev);
5289 struct amdgpu_crtc *disconnected_acrtc = to_amdgpu_crtc(connector->encoder->crtc);
5290 struct drm_plane *plane = disconnected_acrtc->base.primary;
5291 struct drm_connector_state *conn_state;
5292 struct drm_crtc_state *crtc_state;
5293 struct drm_plane_state *plane_state;
5298 state->acquire_ctx = ddev->mode_config.acquire_ctx;
5300 /* Construct an atomic state to restore previous display setting */
5303 * Attach connectors to drm_atomic_state
5305 conn_state = drm_atomic_get_connector_state(state, connector);
5307 ret = PTR_ERR_OR_ZERO(conn_state);
5311 /* Attach crtc to drm_atomic_state*/
5312 crtc_state = drm_atomic_get_crtc_state(state, &disconnected_acrtc->base);
5314 ret = PTR_ERR_OR_ZERO(crtc_state);
5318 /* force a restore */
5319 crtc_state->mode_changed = true;
5321 /* Attach plane to drm_atomic_state */
5322 plane_state = drm_atomic_get_plane_state(state, plane);
5324 ret = PTR_ERR_OR_ZERO(plane_state);
5329 /* Call commit internally with the state we just constructed */
5330 ret = drm_atomic_commit(state);
5335 DRM_ERROR("Restoring old state failed with %i\n", ret);
5336 drm_atomic_state_put(state);
5342 * This function handles all cases when set mode does not come upon hotplug.
5343 * This includes when a display is unplugged then plugged back into the
5344 * same port and when running without usermode desktop manager supprot
5346 void dm_restore_drm_connector_state(struct drm_device *dev,
5347 struct drm_connector *connector)
5349 struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
5350 struct amdgpu_crtc *disconnected_acrtc;
5351 struct dm_crtc_state *acrtc_state;
5353 if (!aconnector->dc_sink || !connector->state || !connector->encoder)
5356 disconnected_acrtc = to_amdgpu_crtc(connector->encoder->crtc);
5357 if (!disconnected_acrtc)
5360 acrtc_state = to_dm_crtc_state(disconnected_acrtc->base.state);
5361 if (!acrtc_state->stream)
5365 * If the previous sink is not released and different from the current,
5366 * we deduce we are in a state where we can not rely on usermode call
5367 * to turn on the display, so we do it here
5369 if (acrtc_state->stream->sink != aconnector->dc_sink)
5370 dm_force_atomic_commit(&aconnector->base);
5374 * Grabs all modesetting locks to serialize against any blocking commits,
5375 * Waits for completion of all non blocking commits.
5377 static int do_aquire_global_lock(struct drm_device *dev,
5378 struct drm_atomic_state *state)
5380 struct drm_crtc *crtc;
5381 struct drm_crtc_commit *commit;
5385 * Adding all modeset locks to aquire_ctx will
5386 * ensure that when the framework release it the
5387 * extra locks we are locking here will get released to
5389 ret = drm_modeset_lock_all_ctx(dev, state->acquire_ctx);
5393 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
5394 spin_lock(&crtc->commit_lock);
5395 commit = list_first_entry_or_null(&crtc->commit_list,
5396 struct drm_crtc_commit, commit_entry);
5398 drm_crtc_commit_get(commit);
5399 spin_unlock(&crtc->commit_lock);
5405 * Make sure all pending HW programming completed and
5408 ret = wait_for_completion_interruptible_timeout(&commit->hw_done, 10*HZ);
5411 ret = wait_for_completion_interruptible_timeout(
5412 &commit->flip_done, 10*HZ);
5415 DRM_ERROR("[CRTC:%d:%s] hw_done or flip_done "
5416 "timed out\n", crtc->base.id, crtc->name);
5418 drm_crtc_commit_put(commit);
5421 return ret < 0 ? ret : 0;
5424 static void get_freesync_config_for_crtc(
5425 struct dm_crtc_state *new_crtc_state,
5426 struct dm_connector_state *new_con_state)
5428 struct mod_freesync_config config = {0};
5429 struct amdgpu_dm_connector *aconnector =
5430 to_amdgpu_dm_connector(new_con_state->base.connector);
5431 struct drm_display_mode *mode = &new_crtc_state->base.mode;
5432 int vrefresh = drm_mode_vrefresh(mode);
5434 new_crtc_state->vrr_supported = new_con_state->freesync_capable &&
5435 vrefresh >= aconnector->min_vfreq &&
5436 vrefresh <= aconnector->max_vfreq;
5438 if (new_crtc_state->vrr_supported) {
5439 new_crtc_state->stream->ignore_msa_timing_param = true;
5440 config.state = new_crtc_state->base.vrr_enabled ?
5441 VRR_STATE_ACTIVE_VARIABLE :
5443 config.min_refresh_in_uhz =
5444 aconnector->min_vfreq * 1000000;
5445 config.max_refresh_in_uhz =
5446 aconnector->max_vfreq * 1000000;
5447 config.vsif_supported = true;
5451 new_crtc_state->freesync_config = config;
5454 static void reset_freesync_config_for_crtc(
5455 struct dm_crtc_state *new_crtc_state)
5457 new_crtc_state->vrr_supported = false;
5459 memset(&new_crtc_state->vrr_params, 0,
5460 sizeof(new_crtc_state->vrr_params));
5461 memset(&new_crtc_state->vrr_infopacket, 0,
5462 sizeof(new_crtc_state->vrr_infopacket));
5465 static int dm_update_crtc_state(struct amdgpu_display_manager *dm,
5466 struct drm_atomic_state *state,
5467 struct drm_crtc *crtc,
5468 struct drm_crtc_state *old_crtc_state,
5469 struct drm_crtc_state *new_crtc_state,
5471 bool *lock_and_validation_needed)
5473 struct dm_atomic_state *dm_state = NULL;
5474 struct dm_crtc_state *dm_old_crtc_state, *dm_new_crtc_state;
5475 struct dc_stream_state *new_stream;
5479 * TODO Move this code into dm_crtc_atomic_check once we get rid of dc_validation_set
5480 * update changed items
5482 struct amdgpu_crtc *acrtc = NULL;
5483 struct amdgpu_dm_connector *aconnector = NULL;
5484 struct drm_connector_state *drm_new_conn_state = NULL, *drm_old_conn_state = NULL;
5485 struct dm_connector_state *dm_new_conn_state = NULL, *dm_old_conn_state = NULL;
5486 struct drm_plane_state *new_plane_state = NULL;
5490 dm_old_crtc_state = to_dm_crtc_state(old_crtc_state);
5491 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
5492 acrtc = to_amdgpu_crtc(crtc);
5494 new_plane_state = drm_atomic_get_new_plane_state(state, new_crtc_state->crtc->primary);
5496 if (new_crtc_state->enable && new_plane_state && !new_plane_state->fb) {
5501 aconnector = amdgpu_dm_find_first_crtc_matching_connector(state, crtc);
5503 /* TODO This hack should go away */
5504 if (aconnector && enable) {
5505 /* Make sure fake sink is created in plug-in scenario */
5506 drm_new_conn_state = drm_atomic_get_new_connector_state(state,
5508 drm_old_conn_state = drm_atomic_get_old_connector_state(state,
5511 if (IS_ERR(drm_new_conn_state)) {
5512 ret = PTR_ERR_OR_ZERO(drm_new_conn_state);
5516 dm_new_conn_state = to_dm_connector_state(drm_new_conn_state);
5517 dm_old_conn_state = to_dm_connector_state(drm_old_conn_state);
5519 if (!drm_atomic_crtc_needs_modeset(new_crtc_state))
5522 new_stream = create_stream_for_sink(aconnector,
5523 &new_crtc_state->mode,
5525 dm_old_crtc_state->stream);
5528 * we can have no stream on ACTION_SET if a display
5529 * was disconnected during S3, in this case it is not an
5530 * error, the OS will be updated after detection, and
5531 * will do the right thing on next atomic commit
5535 DRM_DEBUG_DRIVER("%s: Failed to create new stream for crtc %d\n",
5536 __func__, acrtc->base.base.id);
5541 dm_new_crtc_state->abm_level = dm_new_conn_state->abm_level;
5543 if (dc_is_stream_unchanged(new_stream, dm_old_crtc_state->stream) &&
5544 dc_is_stream_scaling_unchanged(new_stream, dm_old_crtc_state->stream)) {
5545 new_crtc_state->mode_changed = false;
5546 DRM_DEBUG_DRIVER("Mode change not required, setting mode_changed to %d",
5547 new_crtc_state->mode_changed);
5551 /* mode_changed flag may get updated above, need to check again */
5552 if (!drm_atomic_crtc_needs_modeset(new_crtc_state))
5556 "amdgpu_crtc id:%d crtc_state_flags: enable:%d, active:%d, "
5557 "planes_changed:%d, mode_changed:%d,active_changed:%d,"
5558 "connectors_changed:%d\n",
5560 new_crtc_state->enable,
5561 new_crtc_state->active,
5562 new_crtc_state->planes_changed,
5563 new_crtc_state->mode_changed,
5564 new_crtc_state->active_changed,
5565 new_crtc_state->connectors_changed);
5567 /* Remove stream for any changed/disabled CRTC */
5570 if (!dm_old_crtc_state->stream)
5573 ret = dm_atomic_get_state(state, &dm_state);
5577 DRM_DEBUG_DRIVER("Disabling DRM crtc: %d\n",
5580 /* i.e. reset mode */
5581 if (dc_remove_stream_from_ctx(
5584 dm_old_crtc_state->stream) != DC_OK) {
5589 dc_stream_release(dm_old_crtc_state->stream);
5590 dm_new_crtc_state->stream = NULL;
5592 reset_freesync_config_for_crtc(dm_new_crtc_state);
5594 *lock_and_validation_needed = true;
5596 } else {/* Add stream for any updated/enabled CRTC */
5598 * Quick fix to prevent NULL pointer on new_stream when
5599 * added MST connectors not found in existing crtc_state in the chained mode
5600 * TODO: need to dig out the root cause of that
5602 if (!aconnector || (!aconnector->dc_sink && aconnector->mst_port))
5605 if (modereset_required(new_crtc_state))
5608 if (modeset_required(new_crtc_state, new_stream,
5609 dm_old_crtc_state->stream)) {
5611 WARN_ON(dm_new_crtc_state->stream);
5613 ret = dm_atomic_get_state(state, &dm_state);
5617 dm_new_crtc_state->stream = new_stream;
5619 dc_stream_retain(new_stream);
5621 DRM_DEBUG_DRIVER("Enabling DRM crtc: %d\n",
5624 if (dc_add_stream_to_ctx(
5627 dm_new_crtc_state->stream) != DC_OK) {
5632 *lock_and_validation_needed = true;
5637 /* Release extra reference */
5639 dc_stream_release(new_stream);
5642 * We want to do dc stream updates that do not require a
5643 * full modeset below.
5645 if (!(enable && aconnector && new_crtc_state->enable &&
5646 new_crtc_state->active))
5649 * Given above conditions, the dc state cannot be NULL because:
5650 * 1. We're in the process of enabling CRTCs (just been added
5651 * to the dc context, or already is on the context)
5652 * 2. Has a valid connector attached, and
5653 * 3. Is currently active and enabled.
5654 * => The dc stream state currently exists.
5656 BUG_ON(dm_new_crtc_state->stream == NULL);
5658 /* Scaling or underscan settings */
5659 if (is_scaling_state_different(dm_old_conn_state, dm_new_conn_state))
5660 update_stream_scaling_settings(
5661 &new_crtc_state->mode, dm_new_conn_state, dm_new_crtc_state->stream);
5664 * Color management settings. We also update color properties
5665 * when a modeset is needed, to ensure it gets reprogrammed.
5667 if (dm_new_crtc_state->base.color_mgmt_changed ||
5668 drm_atomic_crtc_needs_modeset(new_crtc_state)) {
5669 ret = amdgpu_dm_set_regamma_lut(dm_new_crtc_state);
5672 amdgpu_dm_set_ctm(dm_new_crtc_state);
5675 /* Update Freesync settings. */
5676 get_freesync_config_for_crtc(dm_new_crtc_state,
5683 dc_stream_release(new_stream);
5687 static int dm_update_plane_state(struct dc *dc,
5688 struct drm_atomic_state *state,
5689 struct drm_plane *plane,
5690 struct drm_plane_state *old_plane_state,
5691 struct drm_plane_state *new_plane_state,
5693 bool *lock_and_validation_needed)
5696 struct dm_atomic_state *dm_state = NULL;
5697 struct drm_crtc *new_plane_crtc, *old_plane_crtc;
5698 struct drm_crtc_state *old_crtc_state, *new_crtc_state;
5699 struct dm_crtc_state *dm_new_crtc_state, *dm_old_crtc_state;
5700 struct dm_plane_state *dm_new_plane_state, *dm_old_plane_state;
5701 /* TODO return page_flip_needed() function */
5702 bool pflip_needed = !state->allow_modeset;
5706 new_plane_crtc = new_plane_state->crtc;
5707 old_plane_crtc = old_plane_state->crtc;
5708 dm_new_plane_state = to_dm_plane_state(new_plane_state);
5709 dm_old_plane_state = to_dm_plane_state(old_plane_state);
5711 /*TODO Implement atomic check for cursor plane */
5712 if (plane->type == DRM_PLANE_TYPE_CURSOR)
5715 /* Remove any changed/removed planes */
5718 plane->type != DRM_PLANE_TYPE_OVERLAY)
5721 if (!old_plane_crtc)
5724 old_crtc_state = drm_atomic_get_old_crtc_state(
5725 state, old_plane_crtc);
5726 dm_old_crtc_state = to_dm_crtc_state(old_crtc_state);
5728 if (!dm_old_crtc_state->stream)
5731 DRM_DEBUG_ATOMIC("Disabling DRM plane: %d on DRM crtc %d\n",
5732 plane->base.id, old_plane_crtc->base.id);
5734 ret = dm_atomic_get_state(state, &dm_state);
5738 if (!dc_remove_plane_from_context(
5740 dm_old_crtc_state->stream,
5741 dm_old_plane_state->dc_state,
5742 dm_state->context)) {
5749 dc_plane_state_release(dm_old_plane_state->dc_state);
5750 dm_new_plane_state->dc_state = NULL;
5752 *lock_and_validation_needed = true;
5754 } else { /* Add new planes */
5755 struct dc_plane_state *dc_new_plane_state;
5757 if (drm_atomic_plane_disabling(plane->state, new_plane_state))
5760 if (!new_plane_crtc)
5763 new_crtc_state = drm_atomic_get_new_crtc_state(state, new_plane_crtc);
5764 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
5766 if (!dm_new_crtc_state->stream)
5769 if (pflip_needed && plane->type != DRM_PLANE_TYPE_OVERLAY)
5772 WARN_ON(dm_new_plane_state->dc_state);
5774 dc_new_plane_state = dc_create_plane_state(dc);
5775 if (!dc_new_plane_state)
5778 DRM_DEBUG_DRIVER("Enabling DRM plane: %d on DRM crtc %d\n",
5779 plane->base.id, new_plane_crtc->base.id);
5781 ret = fill_plane_attributes(
5782 new_plane_crtc->dev->dev_private,
5787 dc_plane_state_release(dc_new_plane_state);
5791 ret = dm_atomic_get_state(state, &dm_state);
5793 dc_plane_state_release(dc_new_plane_state);
5798 * Any atomic check errors that occur after this will
5799 * not need a release. The plane state will be attached
5800 * to the stream, and therefore part of the atomic
5801 * state. It'll be released when the atomic state is
5804 if (!dc_add_plane_to_context(
5806 dm_new_crtc_state->stream,
5808 dm_state->context)) {
5810 dc_plane_state_release(dc_new_plane_state);
5814 dm_new_plane_state->dc_state = dc_new_plane_state;
5816 /* Tell DC to do a full surface update every time there
5817 * is a plane change. Inefficient, but works for now.
5819 dm_new_plane_state->dc_state->update_flags.bits.full_update = 1;
5821 *lock_and_validation_needed = true;
5829 dm_determine_update_type_for_commit(struct dc *dc,
5830 struct drm_atomic_state *state,
5831 enum surface_update_type *out_type)
5833 struct dm_atomic_state *dm_state = NULL, *old_dm_state = NULL;
5834 int i, j, num_plane, ret = 0;
5835 struct drm_plane_state *old_plane_state, *new_plane_state;
5836 struct dm_plane_state *new_dm_plane_state, *old_dm_plane_state;
5837 struct drm_crtc *new_plane_crtc, *old_plane_crtc;
5838 struct drm_plane *plane;
5840 struct drm_crtc *crtc;
5841 struct drm_crtc_state *new_crtc_state, *old_crtc_state;
5842 struct dm_crtc_state *new_dm_crtc_state, *old_dm_crtc_state;
5843 struct dc_stream_status *status = NULL;
5845 struct dc_surface_update *updates;
5846 struct dc_plane_state *surface;
5847 enum surface_update_type update_type = UPDATE_TYPE_FAST;
5849 updates = kcalloc(MAX_SURFACES, sizeof(*updates), GFP_KERNEL);
5850 surface = kcalloc(MAX_SURFACES, sizeof(*surface), GFP_KERNEL);
5852 if (!updates || !surface) {
5853 DRM_ERROR("Plane or surface update failed to allocate");
5854 /* Set type to FULL to avoid crashing in DC*/
5855 update_type = UPDATE_TYPE_FULL;
5859 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
5860 struct dc_stream_update stream_update = { 0 };
5862 new_dm_crtc_state = to_dm_crtc_state(new_crtc_state);
5863 old_dm_crtc_state = to_dm_crtc_state(old_crtc_state);
5866 if (new_dm_crtc_state->stream != old_dm_crtc_state->stream) {
5867 update_type = UPDATE_TYPE_FULL;
5871 if (!new_dm_crtc_state->stream)
5874 for_each_oldnew_plane_in_state(state, plane, old_plane_state, new_plane_state, j) {
5875 new_plane_crtc = new_plane_state->crtc;
5876 old_plane_crtc = old_plane_state->crtc;
5877 new_dm_plane_state = to_dm_plane_state(new_plane_state);
5878 old_dm_plane_state = to_dm_plane_state(old_plane_state);
5880 if (plane->type == DRM_PLANE_TYPE_CURSOR)
5883 if (new_dm_plane_state->dc_state != old_dm_plane_state->dc_state) {
5884 update_type = UPDATE_TYPE_FULL;
5888 if (!state->allow_modeset)
5891 if (crtc != new_plane_crtc)
5894 updates[num_plane].surface = &surface[num_plane];
5896 if (new_crtc_state->mode_changed) {
5897 updates[num_plane].surface->src_rect =
5898 new_dm_plane_state->dc_state->src_rect;
5899 updates[num_plane].surface->dst_rect =
5900 new_dm_plane_state->dc_state->dst_rect;
5901 updates[num_plane].surface->rotation =
5902 new_dm_plane_state->dc_state->rotation;
5903 updates[num_plane].surface->in_transfer_func =
5904 new_dm_plane_state->dc_state->in_transfer_func;
5905 stream_update.dst = new_dm_crtc_state->stream->dst;
5906 stream_update.src = new_dm_crtc_state->stream->src;
5909 if (new_crtc_state->color_mgmt_changed) {
5910 updates[num_plane].gamma =
5911 new_dm_plane_state->dc_state->gamma_correction;
5912 updates[num_plane].in_transfer_func =
5913 new_dm_plane_state->dc_state->in_transfer_func;
5914 stream_update.gamut_remap =
5915 &new_dm_crtc_state->stream->gamut_remap_matrix;
5916 stream_update.out_transfer_func =
5917 new_dm_crtc_state->stream->out_transfer_func;
5926 ret = dm_atomic_get_state(state, &dm_state);
5930 old_dm_state = dm_atomic_get_old_state(state);
5931 if (!old_dm_state) {
5936 status = dc_stream_get_status_from_state(old_dm_state->context,
5937 new_dm_crtc_state->stream);
5939 update_type = dc_check_update_surfaces_for_stream(dc, updates, num_plane,
5940 &stream_update, status);
5942 if (update_type > UPDATE_TYPE_MED) {
5943 update_type = UPDATE_TYPE_FULL;
5952 *out_type = update_type;
5957 * amdgpu_dm_atomic_check() - Atomic check implementation for AMDgpu DM.
5958 * @dev: The DRM device
5959 * @state: The atomic state to commit
5961 * Validate that the given atomic state is programmable by DC into hardware.
5962 * This involves constructing a &struct dc_state reflecting the new hardware
5963 * state we wish to commit, then querying DC to see if it is programmable. It's
5964 * important not to modify the existing DC state. Otherwise, atomic_check
5965 * may unexpectedly commit hardware changes.
5967 * When validating the DC state, it's important that the right locks are
5968 * acquired. For full updates case which removes/adds/updates streams on one
5969 * CRTC while flipping on another CRTC, acquiring global lock will guarantee
5970 * that any such full update commit will wait for completion of any outstanding
5971 * flip using DRMs synchronization events. See
5972 * dm_determine_update_type_for_commit()
5974 * Note that DM adds the affected connectors for all CRTCs in state, when that
5975 * might not seem necessary. This is because DC stream creation requires the
5976 * DC sink, which is tied to the DRM connector state. Cleaning this up should
5977 * be possible but non-trivial - a possible TODO item.
5979 * Return: -Error code if validation failed.
5981 static int amdgpu_dm_atomic_check(struct drm_device *dev,
5982 struct drm_atomic_state *state)
5984 struct amdgpu_device *adev = dev->dev_private;
5985 struct dm_atomic_state *dm_state = NULL;
5986 struct dc *dc = adev->dm.dc;
5987 struct drm_connector *connector;
5988 struct drm_connector_state *old_con_state, *new_con_state;
5989 struct drm_crtc *crtc;
5990 struct drm_crtc_state *old_crtc_state, *new_crtc_state;
5991 struct drm_plane *plane;
5992 struct drm_plane_state *old_plane_state, *new_plane_state;
5993 enum surface_update_type update_type = UPDATE_TYPE_FAST;
5994 enum surface_update_type overall_update_type = UPDATE_TYPE_FAST;
5999 * This bool will be set for true for any modeset/reset
6000 * or plane update which implies non fast surface update.
6002 bool lock_and_validation_needed = false;
6004 ret = drm_atomic_helper_check_modeset(dev, state);
6008 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
6009 if (!drm_atomic_crtc_needs_modeset(new_crtc_state) &&
6010 !new_crtc_state->color_mgmt_changed &&
6011 old_crtc_state->vrr_enabled == new_crtc_state->vrr_enabled)
6014 if (!new_crtc_state->enable)
6017 ret = drm_atomic_add_affected_connectors(state, crtc);
6021 ret = drm_atomic_add_affected_planes(state, crtc);
6027 * Add all primary and overlay planes on the CRTC to the state
6028 * whenever a plane is enabled to maintain correct z-ordering
6029 * and to enable fast surface updates.
6031 drm_for_each_crtc(crtc, dev) {
6032 bool modified = false;
6034 for_each_oldnew_plane_in_state(state, plane, old_plane_state, new_plane_state, i) {
6035 if (plane->type == DRM_PLANE_TYPE_CURSOR)
6038 if (new_plane_state->crtc == crtc ||
6039 old_plane_state->crtc == crtc) {
6048 drm_for_each_plane_mask(plane, state->dev, crtc->state->plane_mask) {
6049 if (plane->type == DRM_PLANE_TYPE_CURSOR)
6053 drm_atomic_get_plane_state(state, plane);
6055 if (IS_ERR(new_plane_state)) {
6056 ret = PTR_ERR(new_plane_state);
6062 /* Remove exiting planes if they are modified */
6063 for_each_oldnew_plane_in_state_reverse(state, plane, old_plane_state, new_plane_state, i) {
6064 ret = dm_update_plane_state(dc, state, plane,
6068 &lock_and_validation_needed);
6073 /* Disable all crtcs which require disable */
6074 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
6075 ret = dm_update_crtc_state(&adev->dm, state, crtc,
6079 &lock_and_validation_needed);
6084 /* Enable all crtcs which require enable */
6085 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
6086 ret = dm_update_crtc_state(&adev->dm, state, crtc,
6090 &lock_and_validation_needed);
6095 /* Add new/modified planes */
6096 for_each_oldnew_plane_in_state_reverse(state, plane, old_plane_state, new_plane_state, i) {
6097 ret = dm_update_plane_state(dc, state, plane,
6101 &lock_and_validation_needed);
6106 /* Run this here since we want to validate the streams we created */
6107 ret = drm_atomic_helper_check_planes(dev, state);
6111 /* Check scaling and underscan changes*/
6112 /* TODO Removed scaling changes validation due to inability to commit
6113 * new stream into context w\o causing full reset. Need to
6114 * decide how to handle.
6116 for_each_oldnew_connector_in_state(state, connector, old_con_state, new_con_state, i) {
6117 struct dm_connector_state *dm_old_con_state = to_dm_connector_state(old_con_state);
6118 struct dm_connector_state *dm_new_con_state = to_dm_connector_state(new_con_state);
6119 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(dm_new_con_state->base.crtc);
6121 /* Skip any modesets/resets */
6122 if (!acrtc || drm_atomic_crtc_needs_modeset(
6123 drm_atomic_get_new_crtc_state(state, &acrtc->base)))
6126 /* Skip any thing not scale or underscan changes */
6127 if (!is_scaling_state_different(dm_new_con_state, dm_old_con_state))
6130 overall_update_type = UPDATE_TYPE_FULL;
6131 lock_and_validation_needed = true;
6134 ret = dm_determine_update_type_for_commit(dc, state, &update_type);
6138 if (overall_update_type < update_type)
6139 overall_update_type = update_type;
6142 * lock_and_validation_needed was an old way to determine if we need to set
6143 * the global lock. Leaving it in to check if we broke any corner cases
6144 * lock_and_validation_needed true = UPDATE_TYPE_FULL or UPDATE_TYPE_MED
6145 * lock_and_validation_needed false = UPDATE_TYPE_FAST
6147 if (lock_and_validation_needed && overall_update_type <= UPDATE_TYPE_FAST)
6148 WARN(1, "Global lock should be Set, overall_update_type should be UPDATE_TYPE_MED or UPDATE_TYPE_FULL");
6149 else if (!lock_and_validation_needed && overall_update_type > UPDATE_TYPE_FAST)
6150 WARN(1, "Global lock should NOT be set, overall_update_type should be UPDATE_TYPE_FAST");
6153 if (overall_update_type > UPDATE_TYPE_FAST) {
6154 ret = dm_atomic_get_state(state, &dm_state);
6158 ret = do_aquire_global_lock(dev, state);
6162 if (dc_validate_global_state(dc, dm_state->context) != DC_OK) {
6166 } else if (state->legacy_cursor_update) {
6168 * This is a fast cursor update coming from the plane update
6169 * helper, check if it can be done asynchronously for better
6172 state->async_update = !drm_atomic_helper_async_check(dev, state);
6175 /* Must be success */
6180 if (ret == -EDEADLK)
6181 DRM_DEBUG_DRIVER("Atomic check stopped to avoid deadlock.\n");
6182 else if (ret == -EINTR || ret == -EAGAIN || ret == -ERESTARTSYS)
6183 DRM_DEBUG_DRIVER("Atomic check stopped due to signal.\n");
6185 DRM_DEBUG_DRIVER("Atomic check failed with err: %d \n", ret);
6190 static bool is_dp_capable_without_timing_msa(struct dc *dc,
6191 struct amdgpu_dm_connector *amdgpu_dm_connector)
6194 bool capable = false;
6196 if (amdgpu_dm_connector->dc_link &&
6197 dm_helpers_dp_read_dpcd(
6199 amdgpu_dm_connector->dc_link,
6200 DP_DOWN_STREAM_PORT_COUNT,
6202 sizeof(dpcd_data))) {
6203 capable = (dpcd_data & DP_MSA_TIMING_PAR_IGNORED) ? true:false;
6208 void amdgpu_dm_update_freesync_caps(struct drm_connector *connector,
6212 bool edid_check_required;
6213 struct detailed_timing *timing;
6214 struct detailed_non_pixel *data;
6215 struct detailed_data_monitor_range *range;
6216 struct amdgpu_dm_connector *amdgpu_dm_connector =
6217 to_amdgpu_dm_connector(connector);
6218 struct dm_connector_state *dm_con_state = NULL;
6220 struct drm_device *dev = connector->dev;
6221 struct amdgpu_device *adev = dev->dev_private;
6222 bool freesync_capable = false;
6224 if (!connector->state) {
6225 DRM_ERROR("%s - Connector has no state", __func__);
6230 dm_con_state = to_dm_connector_state(connector->state);
6232 amdgpu_dm_connector->min_vfreq = 0;
6233 amdgpu_dm_connector->max_vfreq = 0;
6234 amdgpu_dm_connector->pixel_clock_mhz = 0;
6239 dm_con_state = to_dm_connector_state(connector->state);
6241 edid_check_required = false;
6242 if (!amdgpu_dm_connector->dc_sink) {
6243 DRM_ERROR("dc_sink NULL, could not add free_sync module.\n");
6246 if (!adev->dm.freesync_module)
6249 * if edid non zero restrict freesync only for dp and edp
6252 if (amdgpu_dm_connector->dc_sink->sink_signal == SIGNAL_TYPE_DISPLAY_PORT
6253 || amdgpu_dm_connector->dc_sink->sink_signal == SIGNAL_TYPE_EDP) {
6254 edid_check_required = is_dp_capable_without_timing_msa(
6256 amdgpu_dm_connector);
6259 if (edid_check_required == true && (edid->version > 1 ||
6260 (edid->version == 1 && edid->revision > 1))) {
6261 for (i = 0; i < 4; i++) {
6263 timing = &edid->detailed_timings[i];
6264 data = &timing->data.other_data;
6265 range = &data->data.range;
6267 * Check if monitor has continuous frequency mode
6269 if (data->type != EDID_DETAIL_MONITOR_RANGE)
6272 * Check for flag range limits only. If flag == 1 then
6273 * no additional timing information provided.
6274 * Default GTF, GTF Secondary curve and CVT are not
6277 if (range->flags != 1)
6280 amdgpu_dm_connector->min_vfreq = range->min_vfreq;
6281 amdgpu_dm_connector->max_vfreq = range->max_vfreq;
6282 amdgpu_dm_connector->pixel_clock_mhz =
6283 range->pixel_clock_mhz * 10;
6287 if (amdgpu_dm_connector->max_vfreq -
6288 amdgpu_dm_connector->min_vfreq > 10) {
6290 freesync_capable = true;
6296 dm_con_state->freesync_capable = freesync_capable;
6298 if (connector->vrr_capable_property)
6299 drm_connector_set_vrr_capable_property(connector,