2 * Copyright 2015 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
26 #include "dm_services_types.h"
28 #include "dc/inc/core_types.h"
32 #include "amdgpu_display.h"
34 #include "amdgpu_dm.h"
35 #include "amdgpu_pm.h"
37 #include "amd_shared.h"
38 #include "amdgpu_dm_irq.h"
39 #include "dm_helpers.h"
40 #include "dm_services_types.h"
41 #include "amdgpu_dm_mst_types.h"
43 #include "ivsrcid/ivsrcid_vislands30.h"
45 #include <linux/module.h>
46 #include <linux/moduleparam.h>
47 #include <linux/version.h>
48 #include <linux/types.h>
51 #include <drm/drm_atomic.h>
52 #include <drm/drm_atomic_helper.h>
53 #include <drm/drm_dp_mst_helper.h>
54 #include <drm/drm_fb_helper.h>
55 #include <drm/drm_edid.h>
57 #include "modules/inc/mod_freesync.h"
59 #if defined(CONFIG_DRM_AMD_DC_DCN1_0)
60 #include "ivsrcid/irqsrcs_dcn_1_0.h"
62 #include "raven1/DCN/dcn_1_0_offset.h"
63 #include "raven1/DCN/dcn_1_0_sh_mask.h"
64 #include "vega10/soc15ip.h"
66 #include "soc15_common.h"
69 #include "modules/inc/mod_freesync.h"
71 #include "i2caux_interface.h"
73 /* basic init/fini API */
74 static int amdgpu_dm_init(struct amdgpu_device *adev);
75 static void amdgpu_dm_fini(struct amdgpu_device *adev);
77 /* initializes drm_device display related structures, based on the information
78 * provided by DAL. The drm strcutures are: drm_crtc, drm_connector,
79 * drm_encoder, drm_mode_config
81 * Returns 0 on success
83 static int amdgpu_dm_initialize_drm_device(struct amdgpu_device *adev);
84 /* removes and deallocates the drm structures, created by the above function */
85 static void amdgpu_dm_destroy_drm_device(struct amdgpu_display_manager *dm);
88 amdgpu_dm_update_connector_after_detect(struct amdgpu_dm_connector *aconnector);
90 static int amdgpu_dm_plane_init(struct amdgpu_display_manager *dm,
91 struct amdgpu_plane *aplane,
92 unsigned long possible_crtcs);
93 static int amdgpu_dm_crtc_init(struct amdgpu_display_manager *dm,
94 struct drm_plane *plane,
96 static int amdgpu_dm_connector_init(struct amdgpu_display_manager *dm,
97 struct amdgpu_dm_connector *amdgpu_dm_connector,
99 struct amdgpu_encoder *amdgpu_encoder);
100 static int amdgpu_dm_encoder_init(struct drm_device *dev,
101 struct amdgpu_encoder *aencoder,
102 uint32_t link_index);
104 static int amdgpu_dm_connector_get_modes(struct drm_connector *connector);
106 static int amdgpu_dm_atomic_commit(struct drm_device *dev,
107 struct drm_atomic_state *state,
110 static void amdgpu_dm_atomic_commit_tail(struct drm_atomic_state *state);
112 static int amdgpu_dm_atomic_check(struct drm_device *dev,
113 struct drm_atomic_state *state);
118 static const enum drm_plane_type dm_plane_type_default[AMDGPU_MAX_PLANES] = {
119 DRM_PLANE_TYPE_PRIMARY,
120 DRM_PLANE_TYPE_PRIMARY,
121 DRM_PLANE_TYPE_PRIMARY,
122 DRM_PLANE_TYPE_PRIMARY,
123 DRM_PLANE_TYPE_PRIMARY,
124 DRM_PLANE_TYPE_PRIMARY,
127 static const enum drm_plane_type dm_plane_type_carizzo[AMDGPU_MAX_PLANES] = {
128 DRM_PLANE_TYPE_PRIMARY,
129 DRM_PLANE_TYPE_PRIMARY,
130 DRM_PLANE_TYPE_PRIMARY,
131 DRM_PLANE_TYPE_OVERLAY,/* YUV Capable Underlay */
134 static const enum drm_plane_type dm_plane_type_stoney[AMDGPU_MAX_PLANES] = {
135 DRM_PLANE_TYPE_PRIMARY,
136 DRM_PLANE_TYPE_PRIMARY,
137 DRM_PLANE_TYPE_OVERLAY, /* YUV Capable Underlay */
141 * dm_vblank_get_counter
144 * Get counter for number of vertical blanks
147 * struct amdgpu_device *adev - [in] desired amdgpu device
148 * int disp_idx - [in] which CRTC to get the counter from
151 * Counter for vertical blanks
153 static u32 dm_vblank_get_counter(struct amdgpu_device *adev, int crtc)
155 if (crtc >= adev->mode_info.num_crtc)
158 struct amdgpu_crtc *acrtc = adev->mode_info.crtcs[crtc];
159 struct dm_crtc_state *acrtc_state = to_dm_crtc_state(
163 if (acrtc_state->stream == NULL) {
164 DRM_ERROR("dc_stream_state is NULL for crtc '%d'!\n",
169 return dc_stream_get_vblank_counter(acrtc_state->stream);
173 static int dm_crtc_get_scanoutpos(struct amdgpu_device *adev, int crtc,
174 u32 *vbl, u32 *position)
176 uint32_t v_blank_start, v_blank_end, h_position, v_position;
178 if ((crtc < 0) || (crtc >= adev->mode_info.num_crtc))
181 struct amdgpu_crtc *acrtc = adev->mode_info.crtcs[crtc];
182 struct dm_crtc_state *acrtc_state = to_dm_crtc_state(
185 if (acrtc_state->stream == NULL) {
186 DRM_ERROR("dc_stream_state is NULL for crtc '%d'!\n",
192 * TODO rework base driver to use values directly.
193 * for now parse it back into reg-format
195 dc_stream_get_scanoutpos(acrtc_state->stream,
201 *position = v_position | (h_position << 16);
202 *vbl = v_blank_start | (v_blank_end << 16);
208 static bool dm_is_idle(void *handle)
214 static int dm_wait_for_idle(void *handle)
220 static bool dm_check_soft_reset(void *handle)
225 static int dm_soft_reset(void *handle)
231 static struct amdgpu_crtc *
232 get_crtc_by_otg_inst(struct amdgpu_device *adev,
235 struct drm_device *dev = adev->ddev;
236 struct drm_crtc *crtc;
237 struct amdgpu_crtc *amdgpu_crtc;
240 * following if is check inherited from both functions where this one is
241 * used now. Need to be checked why it could happen.
243 if (otg_inst == -1) {
245 return adev->mode_info.crtcs[0];
248 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
249 amdgpu_crtc = to_amdgpu_crtc(crtc);
251 if (amdgpu_crtc->otg_inst == otg_inst)
258 static void dm_pflip_high_irq(void *interrupt_params)
260 struct amdgpu_crtc *amdgpu_crtc;
261 struct common_irq_params *irq_params = interrupt_params;
262 struct amdgpu_device *adev = irq_params->adev;
265 amdgpu_crtc = get_crtc_by_otg_inst(adev, irq_params->irq_src - IRQ_TYPE_PFLIP);
267 /* IRQ could occur when in initial stage */
268 /*TODO work and BO cleanup */
269 if (amdgpu_crtc == NULL) {
270 DRM_DEBUG_DRIVER("CRTC is null, returning.\n");
274 spin_lock_irqsave(&adev->ddev->event_lock, flags);
276 if (amdgpu_crtc->pflip_status != AMDGPU_FLIP_SUBMITTED){
277 DRM_DEBUG_DRIVER("amdgpu_crtc->pflip_status = %d !=AMDGPU_FLIP_SUBMITTED(%d) on crtc:%d[%p] \n",
278 amdgpu_crtc->pflip_status,
279 AMDGPU_FLIP_SUBMITTED,
280 amdgpu_crtc->crtc_id,
282 spin_unlock_irqrestore(&adev->ddev->event_lock, flags);
287 /* wakeup usersapce */
288 if (amdgpu_crtc->event) {
289 /* Update to correct count/ts if racing with vblank irq */
290 drm_crtc_accurate_vblank_count(&amdgpu_crtc->base);
292 drm_crtc_send_vblank_event(&amdgpu_crtc->base, amdgpu_crtc->event);
294 /* page flip completed. clean up */
295 amdgpu_crtc->event = NULL;
300 amdgpu_crtc->pflip_status = AMDGPU_FLIP_NONE;
301 spin_unlock_irqrestore(&adev->ddev->event_lock, flags);
303 DRM_DEBUG_DRIVER("%s - crtc :%d[%p], pflip_stat:AMDGPU_FLIP_NONE\n",
304 __func__, amdgpu_crtc->crtc_id, amdgpu_crtc);
306 drm_crtc_vblank_put(&amdgpu_crtc->base);
309 static void dm_crtc_high_irq(void *interrupt_params)
311 struct common_irq_params *irq_params = interrupt_params;
312 struct amdgpu_device *adev = irq_params->adev;
313 uint8_t crtc_index = 0;
314 struct amdgpu_crtc *acrtc;
316 acrtc = get_crtc_by_otg_inst(adev, irq_params->irq_src - IRQ_TYPE_VBLANK);
319 crtc_index = acrtc->crtc_id;
321 drm_handle_vblank(adev->ddev, crtc_index);
324 static int dm_set_clockgating_state(void *handle,
325 enum amd_clockgating_state state)
330 static int dm_set_powergating_state(void *handle,
331 enum amd_powergating_state state)
336 /* Prototypes of private functions */
337 static int dm_early_init(void* handle);
339 static void hotplug_notify_work_func(struct work_struct *work)
341 struct amdgpu_display_manager *dm = container_of(work, struct amdgpu_display_manager, mst_hotplug_work);
342 struct drm_device *dev = dm->ddev;
344 drm_kms_helper_hotplug_event(dev);
347 #if defined(CONFIG_DRM_AMD_DC_FBC)
348 #include "dal_asic_id.h"
349 /* Allocate memory for FBC compressed data */
350 /* TODO: Dynamic allocation */
351 #define AMDGPU_FBC_SIZE (3840 * 2160 * 4)
353 static void amdgpu_dm_initialize_fbc(struct amdgpu_device *adev)
356 struct dm_comressor_info *compressor = &adev->dm.compressor;
358 if (!compressor->bo_ptr) {
359 r = amdgpu_bo_create_kernel(adev, AMDGPU_FBC_SIZE, PAGE_SIZE,
360 AMDGPU_GEM_DOMAIN_VRAM, &compressor->bo_ptr,
361 &compressor->gpu_addr, &compressor->cpu_addr);
364 DRM_ERROR("DM: Failed to initialize fbc\n");
373 * Returns 0 on success
375 static int amdgpu_dm_init(struct amdgpu_device *adev)
377 struct dc_init_data init_data;
378 adev->dm.ddev = adev->ddev;
379 adev->dm.adev = adev;
381 /* Zero all the fields */
382 memset(&init_data, 0, sizeof(init_data));
384 /* initialize DAL's lock (for SYNC context use) */
385 spin_lock_init(&adev->dm.dal_lock);
387 /* initialize DAL's mutex */
388 mutex_init(&adev->dm.dal_mutex);
390 if(amdgpu_dm_irq_init(adev)) {
391 DRM_ERROR("amdgpu: failed to initialize DM IRQ support.\n");
395 init_data.asic_id.chip_family = adev->family;
397 init_data.asic_id.pci_revision_id = adev->rev_id;
398 init_data.asic_id.hw_internal_rev = adev->external_rev_id;
400 init_data.asic_id.vram_width = adev->mc.vram_width;
401 /* TODO: initialize init_data.asic_id.vram_type here!!!! */
402 init_data.asic_id.atombios_base_address =
403 adev->mode_info.atom_context->bios;
405 init_data.driver = adev;
407 adev->dm.cgs_device = amdgpu_cgs_create_device(adev);
409 if (!adev->dm.cgs_device) {
410 DRM_ERROR("amdgpu: failed to create cgs device.\n");
414 init_data.cgs_device = adev->dm.cgs_device;
418 init_data.dce_environment = DCE_ENV_PRODUCTION_DRV;
421 init_data.log_mask = DC_DEFAULT_LOG_MASK;
423 init_data.log_mask = DC_MIN_LOG_MASK;
425 #if defined(CONFIG_DRM_AMD_DC_FBC)
426 if (adev->family == FAMILY_CZ)
427 amdgpu_dm_initialize_fbc(adev);
428 init_data.fbc_gpu_addr = adev->dm.compressor.gpu_addr;
430 /* Display Core create. */
431 adev->dm.dc = dc_create(&init_data);
434 DRM_INFO("Display Core initialized!\n");
436 DRM_INFO("Display Core failed to initialize!\n");
440 INIT_WORK(&adev->dm.mst_hotplug_work, hotplug_notify_work_func);
442 adev->dm.freesync_module = mod_freesync_create(adev->dm.dc);
443 if (!adev->dm.freesync_module) {
445 "amdgpu: failed to initialize freesync_module.\n");
447 DRM_DEBUG_DRIVER("amdgpu: freesync_module init done %p.\n",
448 adev->dm.freesync_module);
450 if (amdgpu_dm_initialize_drm_device(adev)) {
452 "amdgpu: failed to initialize sw for display support.\n");
456 /* Update the actual used number of crtc */
457 adev->mode_info.num_crtc = adev->dm.display_indexes_num;
459 /* TODO: Add_display_info? */
461 /* TODO use dynamic cursor width */
462 adev->ddev->mode_config.cursor_width = adev->dm.dc->caps.max_cursor_size;
463 adev->ddev->mode_config.cursor_height = adev->dm.dc->caps.max_cursor_size;
465 if (drm_vblank_init(adev->ddev, adev->dm.display_indexes_num)) {
467 "amdgpu: failed to initialize sw for display support.\n");
471 DRM_DEBUG_DRIVER("KMS initialized.\n");
475 amdgpu_dm_fini(adev);
480 static void amdgpu_dm_fini(struct amdgpu_device *adev)
482 amdgpu_dm_destroy_drm_device(&adev->dm);
484 * TODO: pageflip, vlank interrupt
486 * amdgpu_dm_irq_fini(adev);
489 if (adev->dm.cgs_device) {
490 amdgpu_cgs_destroy_device(adev->dm.cgs_device);
491 adev->dm.cgs_device = NULL;
493 if (adev->dm.freesync_module) {
494 mod_freesync_destroy(adev->dm.freesync_module);
495 adev->dm.freesync_module = NULL;
497 /* DC Destroy TODO: Replace destroy DAL */
499 dc_destroy(&adev->dm.dc);
503 static int dm_sw_init(void *handle)
508 static int dm_sw_fini(void *handle)
513 static int detect_mst_link_for_all_connectors(struct drm_device *dev)
515 struct amdgpu_dm_connector *aconnector;
516 struct drm_connector *connector;
519 drm_modeset_lock(&dev->mode_config.connection_mutex, NULL);
521 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
522 aconnector = to_amdgpu_dm_connector(connector);
523 if (aconnector->dc_link->type == dc_connection_mst_branch) {
524 DRM_DEBUG_DRIVER("DM_MST: starting TM on aconnector: %p [id: %d]\n",
525 aconnector, aconnector->base.base.id);
527 ret = drm_dp_mst_topology_mgr_set_mst(&aconnector->mst_mgr, true);
529 DRM_ERROR("DM_MST: Failed to start MST\n");
530 ((struct dc_link *)aconnector->dc_link)->type = dc_connection_single;
536 drm_modeset_unlock(&dev->mode_config.connection_mutex);
540 static int dm_late_init(void *handle)
542 struct drm_device *dev = ((struct amdgpu_device *)handle)->ddev;
544 return detect_mst_link_for_all_connectors(dev);
547 static void s3_handle_mst(struct drm_device *dev, bool suspend)
549 struct amdgpu_dm_connector *aconnector;
550 struct drm_connector *connector;
552 drm_modeset_lock(&dev->mode_config.connection_mutex, NULL);
554 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
555 aconnector = to_amdgpu_dm_connector(connector);
556 if (aconnector->dc_link->type == dc_connection_mst_branch &&
557 !aconnector->mst_port) {
560 drm_dp_mst_topology_mgr_suspend(&aconnector->mst_mgr);
562 drm_dp_mst_topology_mgr_resume(&aconnector->mst_mgr);
566 drm_modeset_unlock(&dev->mode_config.connection_mutex);
569 static int dm_hw_init(void *handle)
571 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
572 /* Create DAL display manager */
573 amdgpu_dm_init(adev);
574 amdgpu_dm_hpd_init(adev);
579 static int dm_hw_fini(void *handle)
581 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
583 amdgpu_dm_hpd_fini(adev);
585 amdgpu_dm_irq_fini(adev);
586 amdgpu_dm_fini(adev);
590 static int dm_suspend(void *handle)
592 struct amdgpu_device *adev = handle;
593 struct amdgpu_display_manager *dm = &adev->dm;
596 s3_handle_mst(adev->ddev, true);
598 amdgpu_dm_irq_suspend(adev);
600 WARN_ON(adev->dm.cached_state);
601 adev->dm.cached_state = drm_atomic_helper_suspend(adev->ddev);
603 dc_set_power_state(dm->dc, DC_ACPI_CM_POWER_STATE_D3);
608 static struct amdgpu_dm_connector *
609 amdgpu_dm_find_first_crtc_matching_connector(struct drm_atomic_state *state,
610 struct drm_crtc *crtc)
613 struct drm_connector_state *new_con_state;
614 struct drm_connector *connector;
615 struct drm_crtc *crtc_from_state;
617 for_each_new_connector_in_state(state, connector, new_con_state, i) {
618 crtc_from_state = new_con_state->crtc;
620 if (crtc_from_state == crtc)
621 return to_amdgpu_dm_connector(connector);
627 static int dm_resume(void *handle)
629 struct amdgpu_device *adev = handle;
630 struct amdgpu_display_manager *dm = &adev->dm;
632 /* power on hardware */
633 dc_set_power_state(dm->dc, DC_ACPI_CM_POWER_STATE_D0);
638 int amdgpu_dm_display_resume(struct amdgpu_device *adev)
640 struct drm_device *ddev = adev->ddev;
641 struct amdgpu_display_manager *dm = &adev->dm;
642 struct amdgpu_dm_connector *aconnector;
643 struct drm_connector *connector;
644 struct drm_crtc *crtc;
645 struct drm_crtc_state *new_crtc_state;
646 struct dm_crtc_state *dm_new_crtc_state;
647 struct drm_plane *plane;
648 struct drm_plane_state *new_plane_state;
649 struct dm_plane_state *dm_new_plane_state;
654 /* program HPD filter */
657 /* On resume we need to rewrite the MSTM control bits to enamble MST*/
658 s3_handle_mst(ddev, false);
661 * early enable HPD Rx IRQ, should be done before set mode as short
662 * pulse interrupts are used for MST
664 amdgpu_dm_irq_resume_early(adev);
667 list_for_each_entry(connector,
668 &ddev->mode_config.connector_list, head) {
669 aconnector = to_amdgpu_dm_connector(connector);
672 * this is the case when traversing through already created
673 * MST connectors, should be skipped
675 if (aconnector->mst_port)
678 mutex_lock(&aconnector->hpd_lock);
679 dc_link_detect(aconnector->dc_link, DETECT_REASON_HPD);
680 aconnector->dc_sink = NULL;
681 amdgpu_dm_update_connector_after_detect(aconnector);
682 mutex_unlock(&aconnector->hpd_lock);
685 /* Force mode set in atomic comit */
686 for_each_new_crtc_in_state(adev->dm.cached_state, crtc, new_crtc_state, i)
687 new_crtc_state->active_changed = true;
690 * atomic_check is expected to create the dc states. We need to release
691 * them here, since they were duplicated as part of the suspend
694 for_each_new_crtc_in_state(adev->dm.cached_state, crtc, new_crtc_state, i) {
695 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
696 if (dm_new_crtc_state->stream) {
697 WARN_ON(kref_read(&dm_new_crtc_state->stream->refcount) > 1);
698 dc_stream_release(dm_new_crtc_state->stream);
699 dm_new_crtc_state->stream = NULL;
703 for_each_new_plane_in_state(adev->dm.cached_state, plane, new_plane_state, i) {
704 dm_new_plane_state = to_dm_plane_state(new_plane_state);
705 if (dm_new_plane_state->dc_state) {
706 WARN_ON(kref_read(&dm_new_plane_state->dc_state->refcount) > 1);
707 dc_plane_state_release(dm_new_plane_state->dc_state);
708 dm_new_plane_state->dc_state = NULL;
712 ret = drm_atomic_helper_resume(ddev, adev->dm.cached_state);
714 drm_atomic_state_put(adev->dm.cached_state);
715 adev->dm.cached_state = NULL;
717 amdgpu_dm_irq_resume_late(adev);
722 static const struct amd_ip_funcs amdgpu_dm_funcs = {
724 .early_init = dm_early_init,
725 .late_init = dm_late_init,
726 .sw_init = dm_sw_init,
727 .sw_fini = dm_sw_fini,
728 .hw_init = dm_hw_init,
729 .hw_fini = dm_hw_fini,
730 .suspend = dm_suspend,
732 .is_idle = dm_is_idle,
733 .wait_for_idle = dm_wait_for_idle,
734 .check_soft_reset = dm_check_soft_reset,
735 .soft_reset = dm_soft_reset,
736 .set_clockgating_state = dm_set_clockgating_state,
737 .set_powergating_state = dm_set_powergating_state,
740 const struct amdgpu_ip_block_version dm_ip_block =
742 .type = AMD_IP_BLOCK_TYPE_DCE,
746 .funcs = &amdgpu_dm_funcs,
750 static struct drm_atomic_state *
751 dm_atomic_state_alloc(struct drm_device *dev)
753 struct dm_atomic_state *state = kzalloc(sizeof(*state), GFP_KERNEL);
758 if (drm_atomic_state_init(dev, &state->base) < 0)
769 dm_atomic_state_clear(struct drm_atomic_state *state)
771 struct dm_atomic_state *dm_state = to_dm_atomic_state(state);
773 if (dm_state->context) {
774 dc_release_state(dm_state->context);
775 dm_state->context = NULL;
778 drm_atomic_state_default_clear(state);
782 dm_atomic_state_alloc_free(struct drm_atomic_state *state)
784 struct dm_atomic_state *dm_state = to_dm_atomic_state(state);
785 drm_atomic_state_default_release(state);
789 static const struct drm_mode_config_funcs amdgpu_dm_mode_funcs = {
790 .fb_create = amdgpu_user_framebuffer_create,
791 .output_poll_changed = amdgpu_output_poll_changed,
792 .atomic_check = amdgpu_dm_atomic_check,
793 .atomic_commit = amdgpu_dm_atomic_commit,
794 .atomic_state_alloc = dm_atomic_state_alloc,
795 .atomic_state_clear = dm_atomic_state_clear,
796 .atomic_state_free = dm_atomic_state_alloc_free
799 static struct drm_mode_config_helper_funcs amdgpu_dm_mode_config_helperfuncs = {
800 .atomic_commit_tail = amdgpu_dm_atomic_commit_tail
804 amdgpu_dm_update_connector_after_detect(struct amdgpu_dm_connector *aconnector)
806 struct drm_connector *connector = &aconnector->base;
807 struct drm_device *dev = connector->dev;
808 struct dc_sink *sink;
810 /* MST handled by drm_mst framework */
811 if (aconnector->mst_mgr.mst_state == true)
815 sink = aconnector->dc_link->local_sink;
817 /* Edid mgmt connector gets first update only in mode_valid hook and then
818 * the connector sink is set to either fake or physical sink depends on link status.
819 * don't do it here if u are during boot
821 if (aconnector->base.force != DRM_FORCE_UNSPECIFIED
822 && aconnector->dc_em_sink) {
824 /* For S3 resume with headless use eml_sink to fake stream
825 * because on resume connecotr->sink is set ti NULL
827 mutex_lock(&dev->mode_config.mutex);
830 if (aconnector->dc_sink) {
831 amdgpu_dm_remove_sink_from_freesync_module(
833 /* retain and release bellow are used for
834 * bump up refcount for sink because the link don't point
835 * to it anymore after disconnect so on next crtc to connector
836 * reshuffle by UMD we will get into unwanted dc_sink release
838 if (aconnector->dc_sink != aconnector->dc_em_sink)
839 dc_sink_release(aconnector->dc_sink);
841 aconnector->dc_sink = sink;
842 amdgpu_dm_add_sink_to_freesync_module(
843 connector, aconnector->edid);
845 amdgpu_dm_remove_sink_from_freesync_module(connector);
846 if (!aconnector->dc_sink)
847 aconnector->dc_sink = aconnector->dc_em_sink;
848 else if (aconnector->dc_sink != aconnector->dc_em_sink)
849 dc_sink_retain(aconnector->dc_sink);
852 mutex_unlock(&dev->mode_config.mutex);
857 * TODO: temporary guard to look for proper fix
858 * if this sink is MST sink, we should not do anything
860 if (sink && sink->sink_signal == SIGNAL_TYPE_DISPLAY_PORT_MST)
863 if (aconnector->dc_sink == sink) {
864 /* We got a DP short pulse (Link Loss, DP CTS, etc...).
866 DRM_DEBUG_DRIVER("DCHPD: connector_id=%d: dc_sink didn't change.\n",
867 aconnector->connector_id);
871 DRM_DEBUG_DRIVER("DCHPD: connector_id=%d: Old sink=%p New sink=%p\n",
872 aconnector->connector_id, aconnector->dc_sink, sink);
874 mutex_lock(&dev->mode_config.mutex);
876 /* 1. Update status of the drm connector
877 * 2. Send an event and let userspace tell us what to do */
879 /* TODO: check if we still need the S3 mode update workaround.
880 * If yes, put it here. */
881 if (aconnector->dc_sink)
882 amdgpu_dm_remove_sink_from_freesync_module(
885 aconnector->dc_sink = sink;
886 if (sink->dc_edid.length == 0) {
887 aconnector->edid = NULL;
890 (struct edid *) sink->dc_edid.raw_edid;
893 drm_mode_connector_update_edid_property(connector,
896 amdgpu_dm_add_sink_to_freesync_module(connector, aconnector->edid);
899 amdgpu_dm_remove_sink_from_freesync_module(connector);
900 drm_mode_connector_update_edid_property(connector, NULL);
901 aconnector->num_modes = 0;
902 aconnector->dc_sink = NULL;
905 mutex_unlock(&dev->mode_config.mutex);
908 static void handle_hpd_irq(void *param)
910 struct amdgpu_dm_connector *aconnector = (struct amdgpu_dm_connector *)param;
911 struct drm_connector *connector = &aconnector->base;
912 struct drm_device *dev = connector->dev;
914 /* In case of failure or MST no need to update connector status or notify the OS
915 * since (for MST case) MST does this in it's own context.
917 mutex_lock(&aconnector->hpd_lock);
919 if (aconnector->fake_enable)
920 aconnector->fake_enable = false;
922 if (dc_link_detect(aconnector->dc_link, DETECT_REASON_HPD)) {
923 amdgpu_dm_update_connector_after_detect(aconnector);
926 drm_modeset_lock_all(dev);
927 dm_restore_drm_connector_state(dev, connector);
928 drm_modeset_unlock_all(dev);
930 if (aconnector->base.force == DRM_FORCE_UNSPECIFIED)
931 drm_kms_helper_hotplug_event(dev);
933 mutex_unlock(&aconnector->hpd_lock);
937 static void dm_handle_hpd_rx_irq(struct amdgpu_dm_connector *aconnector)
939 uint8_t esi[DP_PSR_ERROR_STATUS - DP_SINK_COUNT_ESI] = { 0 };
941 bool new_irq_handled = false;
943 int dpcd_bytes_to_read;
945 const int max_process_count = 30;
946 int process_count = 0;
948 const struct dc_link_status *link_status = dc_link_get_status(aconnector->dc_link);
950 if (link_status->dpcd_caps->dpcd_rev.raw < 0x12) {
951 dpcd_bytes_to_read = DP_LANE0_1_STATUS - DP_SINK_COUNT;
952 /* DPCD 0x200 - 0x201 for downstream IRQ */
953 dpcd_addr = DP_SINK_COUNT;
955 dpcd_bytes_to_read = DP_PSR_ERROR_STATUS - DP_SINK_COUNT_ESI;
956 /* DPCD 0x2002 - 0x2005 for downstream IRQ */
957 dpcd_addr = DP_SINK_COUNT_ESI;
960 dret = drm_dp_dpcd_read(
961 &aconnector->dm_dp_aux.aux,
966 while (dret == dpcd_bytes_to_read &&
967 process_count < max_process_count) {
973 DRM_DEBUG_DRIVER("ESI %02x %02x %02x\n", esi[0], esi[1], esi[2]);
974 /* handle HPD short pulse irq */
975 if (aconnector->mst_mgr.mst_state)
977 &aconnector->mst_mgr,
981 if (new_irq_handled) {
982 /* ACK at DPCD to notify down stream */
983 const int ack_dpcd_bytes_to_write =
984 dpcd_bytes_to_read - 1;
986 for (retry = 0; retry < 3; retry++) {
989 wret = drm_dp_dpcd_write(
990 &aconnector->dm_dp_aux.aux,
993 ack_dpcd_bytes_to_write);
994 if (wret == ack_dpcd_bytes_to_write)
998 /* check if there is new irq to be handle */
999 dret = drm_dp_dpcd_read(
1000 &aconnector->dm_dp_aux.aux,
1003 dpcd_bytes_to_read);
1005 new_irq_handled = false;
1011 if (process_count == max_process_count)
1012 DRM_DEBUG_DRIVER("Loop exceeded max iterations\n");
1015 static void handle_hpd_rx_irq(void *param)
1017 struct amdgpu_dm_connector *aconnector = (struct amdgpu_dm_connector *)param;
1018 struct drm_connector *connector = &aconnector->base;
1019 struct drm_device *dev = connector->dev;
1020 struct dc_link *dc_link = aconnector->dc_link;
1021 bool is_mst_root_connector = aconnector->mst_mgr.mst_state;
1023 /* TODO:Temporary add mutex to protect hpd interrupt not have a gpio
1024 * conflict, after implement i2c helper, this mutex should be
1027 if (dc_link->type != dc_connection_mst_branch)
1028 mutex_lock(&aconnector->hpd_lock);
1030 if (dc_link_handle_hpd_rx_irq(dc_link, NULL) &&
1031 !is_mst_root_connector) {
1032 /* Downstream Port status changed. */
1033 if (dc_link_detect(dc_link, DETECT_REASON_HPDRX)) {
1034 amdgpu_dm_update_connector_after_detect(aconnector);
1037 drm_modeset_lock_all(dev);
1038 dm_restore_drm_connector_state(dev, connector);
1039 drm_modeset_unlock_all(dev);
1041 drm_kms_helper_hotplug_event(dev);
1044 if ((dc_link->cur_link_settings.lane_count != LANE_COUNT_UNKNOWN) ||
1045 (dc_link->type == dc_connection_mst_branch))
1046 dm_handle_hpd_rx_irq(aconnector);
1048 if (dc_link->type != dc_connection_mst_branch)
1049 mutex_unlock(&aconnector->hpd_lock);
1052 static void register_hpd_handlers(struct amdgpu_device *adev)
1054 struct drm_device *dev = adev->ddev;
1055 struct drm_connector *connector;
1056 struct amdgpu_dm_connector *aconnector;
1057 const struct dc_link *dc_link;
1058 struct dc_interrupt_params int_params = {0};
1060 int_params.requested_polarity = INTERRUPT_POLARITY_DEFAULT;
1061 int_params.current_polarity = INTERRUPT_POLARITY_DEFAULT;
1063 list_for_each_entry(connector,
1064 &dev->mode_config.connector_list, head) {
1066 aconnector = to_amdgpu_dm_connector(connector);
1067 dc_link = aconnector->dc_link;
1069 if (DC_IRQ_SOURCE_INVALID != dc_link->irq_source_hpd) {
1070 int_params.int_context = INTERRUPT_LOW_IRQ_CONTEXT;
1071 int_params.irq_source = dc_link->irq_source_hpd;
1073 amdgpu_dm_irq_register_interrupt(adev, &int_params,
1075 (void *) aconnector);
1078 if (DC_IRQ_SOURCE_INVALID != dc_link->irq_source_hpd_rx) {
1080 /* Also register for DP short pulse (hpd_rx). */
1081 int_params.int_context = INTERRUPT_LOW_IRQ_CONTEXT;
1082 int_params.irq_source = dc_link->irq_source_hpd_rx;
1084 amdgpu_dm_irq_register_interrupt(adev, &int_params,
1086 (void *) aconnector);
1091 /* Register IRQ sources and initialize IRQ callbacks */
1092 static int dce110_register_irq_handlers(struct amdgpu_device *adev)
1094 struct dc *dc = adev->dm.dc;
1095 struct common_irq_params *c_irq_params;
1096 struct dc_interrupt_params int_params = {0};
1099 unsigned client_id = AMDGPU_IH_CLIENTID_LEGACY;
1101 if (adev->asic_type == CHIP_VEGA10 ||
1102 adev->asic_type == CHIP_RAVEN)
1103 client_id = AMDGPU_IH_CLIENTID_DCE;
1105 int_params.requested_polarity = INTERRUPT_POLARITY_DEFAULT;
1106 int_params.current_polarity = INTERRUPT_POLARITY_DEFAULT;
1108 /* Actions of amdgpu_irq_add_id():
1109 * 1. Register a set() function with base driver.
1110 * Base driver will call set() function to enable/disable an
1111 * interrupt in DC hardware.
1112 * 2. Register amdgpu_dm_irq_handler().
1113 * Base driver will call amdgpu_dm_irq_handler() for ALL interrupts
1114 * coming from DC hardware.
1115 * amdgpu_dm_irq_handler() will re-direct the interrupt to DC
1116 * for acknowledging and handling. */
1118 /* Use VBLANK interrupt */
1119 for (i = VISLANDS30_IV_SRCID_D1_VERTICAL_INTERRUPT0; i <= VISLANDS30_IV_SRCID_D6_VERTICAL_INTERRUPT0; i++) {
1120 r = amdgpu_irq_add_id(adev, client_id, i, &adev->crtc_irq);
1122 DRM_ERROR("Failed to add crtc irq id!\n");
1126 int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT;
1127 int_params.irq_source =
1128 dc_interrupt_to_irq_source(dc, i, 0);
1130 c_irq_params = &adev->dm.vblank_params[int_params.irq_source - DC_IRQ_SOURCE_VBLANK1];
1132 c_irq_params->adev = adev;
1133 c_irq_params->irq_src = int_params.irq_source;
1135 amdgpu_dm_irq_register_interrupt(adev, &int_params,
1136 dm_crtc_high_irq, c_irq_params);
1139 /* Use GRPH_PFLIP interrupt */
1140 for (i = VISLANDS30_IV_SRCID_D1_GRPH_PFLIP;
1141 i <= VISLANDS30_IV_SRCID_D6_GRPH_PFLIP; i += 2) {
1142 r = amdgpu_irq_add_id(adev, client_id, i, &adev->pageflip_irq);
1144 DRM_ERROR("Failed to add page flip irq id!\n");
1148 int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT;
1149 int_params.irq_source =
1150 dc_interrupt_to_irq_source(dc, i, 0);
1152 c_irq_params = &adev->dm.pflip_params[int_params.irq_source - DC_IRQ_SOURCE_PFLIP_FIRST];
1154 c_irq_params->adev = adev;
1155 c_irq_params->irq_src = int_params.irq_source;
1157 amdgpu_dm_irq_register_interrupt(adev, &int_params,
1158 dm_pflip_high_irq, c_irq_params);
1163 r = amdgpu_irq_add_id(adev, client_id,
1164 VISLANDS30_IV_SRCID_HOTPLUG_DETECT_A, &adev->hpd_irq);
1166 DRM_ERROR("Failed to add hpd irq id!\n");
1170 register_hpd_handlers(adev);
1175 #if defined(CONFIG_DRM_AMD_DC_DCN1_0)
1176 /* Register IRQ sources and initialize IRQ callbacks */
1177 static int dcn10_register_irq_handlers(struct amdgpu_device *adev)
1179 struct dc *dc = adev->dm.dc;
1180 struct common_irq_params *c_irq_params;
1181 struct dc_interrupt_params int_params = {0};
1185 int_params.requested_polarity = INTERRUPT_POLARITY_DEFAULT;
1186 int_params.current_polarity = INTERRUPT_POLARITY_DEFAULT;
1188 /* Actions of amdgpu_irq_add_id():
1189 * 1. Register a set() function with base driver.
1190 * Base driver will call set() function to enable/disable an
1191 * interrupt in DC hardware.
1192 * 2. Register amdgpu_dm_irq_handler().
1193 * Base driver will call amdgpu_dm_irq_handler() for ALL interrupts
1194 * coming from DC hardware.
1195 * amdgpu_dm_irq_handler() will re-direct the interrupt to DC
1196 * for acknowledging and handling.
1199 /* Use VSTARTUP interrupt */
1200 for (i = DCN_1_0__SRCID__DC_D1_OTG_VSTARTUP;
1201 i <= DCN_1_0__SRCID__DC_D1_OTG_VSTARTUP + adev->mode_info.num_crtc - 1;
1203 r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_DCE, i, &adev->crtc_irq);
1206 DRM_ERROR("Failed to add crtc irq id!\n");
1210 int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT;
1211 int_params.irq_source =
1212 dc_interrupt_to_irq_source(dc, i, 0);
1214 c_irq_params = &adev->dm.vblank_params[int_params.irq_source - DC_IRQ_SOURCE_VBLANK1];
1216 c_irq_params->adev = adev;
1217 c_irq_params->irq_src = int_params.irq_source;
1219 amdgpu_dm_irq_register_interrupt(adev, &int_params,
1220 dm_crtc_high_irq, c_irq_params);
1223 /* Use GRPH_PFLIP interrupt */
1224 for (i = DCN_1_0__SRCID__HUBP0_FLIP_INTERRUPT;
1225 i <= DCN_1_0__SRCID__HUBP0_FLIP_INTERRUPT + adev->mode_info.num_crtc - 1;
1227 r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_DCE, i, &adev->pageflip_irq);
1229 DRM_ERROR("Failed to add page flip irq id!\n");
1233 int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT;
1234 int_params.irq_source =
1235 dc_interrupt_to_irq_source(dc, i, 0);
1237 c_irq_params = &adev->dm.pflip_params[int_params.irq_source - DC_IRQ_SOURCE_PFLIP_FIRST];
1239 c_irq_params->adev = adev;
1240 c_irq_params->irq_src = int_params.irq_source;
1242 amdgpu_dm_irq_register_interrupt(adev, &int_params,
1243 dm_pflip_high_irq, c_irq_params);
1248 r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_DCE, DCN_1_0__SRCID__DC_HPD1_INT,
1251 DRM_ERROR("Failed to add hpd irq id!\n");
1255 register_hpd_handlers(adev);
1261 static int amdgpu_dm_mode_config_init(struct amdgpu_device *adev)
1265 adev->mode_info.mode_config_initialized = true;
1267 adev->ddev->mode_config.funcs = (void *)&amdgpu_dm_mode_funcs;
1268 adev->ddev->mode_config.helper_private = &amdgpu_dm_mode_config_helperfuncs;
1270 adev->ddev->mode_config.max_width = 16384;
1271 adev->ddev->mode_config.max_height = 16384;
1273 adev->ddev->mode_config.preferred_depth = 24;
1274 adev->ddev->mode_config.prefer_shadow = 1;
1275 /* indicate support of immediate flip */
1276 adev->ddev->mode_config.async_page_flip = true;
1278 adev->ddev->mode_config.fb_base = adev->mc.aper_base;
1280 r = amdgpu_modeset_create_props(adev);
1287 #if defined(CONFIG_BACKLIGHT_CLASS_DEVICE) ||\
1288 defined(CONFIG_BACKLIGHT_CLASS_DEVICE_MODULE)
1290 static int amdgpu_dm_backlight_update_status(struct backlight_device *bd)
1292 struct amdgpu_display_manager *dm = bl_get_data(bd);
1294 if (dc_link_set_backlight_level(dm->backlight_link,
1295 bd->props.brightness, 0, 0))
1301 static int amdgpu_dm_backlight_get_brightness(struct backlight_device *bd)
1303 return bd->props.brightness;
1306 static const struct backlight_ops amdgpu_dm_backlight_ops = {
1307 .get_brightness = amdgpu_dm_backlight_get_brightness,
1308 .update_status = amdgpu_dm_backlight_update_status,
1312 amdgpu_dm_register_backlight_device(struct amdgpu_display_manager *dm)
1315 struct backlight_properties props = { 0 };
1317 props.max_brightness = AMDGPU_MAX_BL_LEVEL;
1318 props.type = BACKLIGHT_RAW;
1320 snprintf(bl_name, sizeof(bl_name), "amdgpu_bl%d",
1321 dm->adev->ddev->primary->index);
1323 dm->backlight_dev = backlight_device_register(bl_name,
1324 dm->adev->ddev->dev,
1326 &amdgpu_dm_backlight_ops,
1329 if (IS_ERR(dm->backlight_dev))
1330 DRM_ERROR("DM: Backlight registration failed!\n");
1332 DRM_DEBUG_DRIVER("DM: Registered Backlight device: %s\n", bl_name);
1337 /* In this architecture, the association
1338 * connector -> encoder -> crtc
1339 * id not really requried. The crtc and connector will hold the
1340 * display_index as an abstraction to use with DAL component
1342 * Returns 0 on success
1344 static int amdgpu_dm_initialize_drm_device(struct amdgpu_device *adev)
1346 struct amdgpu_display_manager *dm = &adev->dm;
1348 struct amdgpu_dm_connector *aconnector = NULL;
1349 struct amdgpu_encoder *aencoder = NULL;
1350 struct amdgpu_mode_info *mode_info = &adev->mode_info;
1352 unsigned long possible_crtcs;
1354 link_cnt = dm->dc->caps.max_links;
1355 if (amdgpu_dm_mode_config_init(dm->adev)) {
1356 DRM_ERROR("DM: Failed to initialize mode config\n");
1360 for (i = 0; i < dm->dc->caps.max_planes; i++) {
1361 struct amdgpu_plane *plane;
1363 plane = kzalloc(sizeof(struct amdgpu_plane), GFP_KERNEL);
1364 mode_info->planes[i] = plane;
1367 DRM_ERROR("KMS: Failed to allocate plane\n");
1370 plane->base.type = mode_info->plane_type[i];
1373 * HACK: IGT tests expect that each plane can only have one
1374 * one possible CRTC. For now, set one CRTC for each
1375 * plane that is not an underlay, but still allow multiple
1376 * CRTCs for underlay planes.
1378 possible_crtcs = 1 << i;
1379 if (i >= dm->dc->caps.max_streams)
1380 possible_crtcs = 0xff;
1382 if (amdgpu_dm_plane_init(dm, mode_info->planes[i], possible_crtcs)) {
1383 DRM_ERROR("KMS: Failed to initialize plane\n");
1388 for (i = 0; i < dm->dc->caps.max_streams; i++)
1389 if (amdgpu_dm_crtc_init(dm, &mode_info->planes[i]->base, i)) {
1390 DRM_ERROR("KMS: Failed to initialize crtc\n");
1394 dm->display_indexes_num = dm->dc->caps.max_streams;
1396 /* loops over all connectors on the board */
1397 for (i = 0; i < link_cnt; i++) {
1399 if (i > AMDGPU_DM_MAX_DISPLAY_INDEX) {
1401 "KMS: Cannot support more than %d display indexes\n",
1402 AMDGPU_DM_MAX_DISPLAY_INDEX);
1406 aconnector = kzalloc(sizeof(*aconnector), GFP_KERNEL);
1410 aencoder = kzalloc(sizeof(*aencoder), GFP_KERNEL);
1414 if (amdgpu_dm_encoder_init(dm->ddev, aencoder, i)) {
1415 DRM_ERROR("KMS: Failed to initialize encoder\n");
1419 if (amdgpu_dm_connector_init(dm, aconnector, i, aencoder)) {
1420 DRM_ERROR("KMS: Failed to initialize connector\n");
1424 if (dc_link_detect(dc_get_link_at_index(dm->dc, i),
1425 DETECT_REASON_BOOT))
1426 amdgpu_dm_update_connector_after_detect(aconnector);
1429 /* Software is initialized. Now we can register interrupt handlers. */
1430 switch (adev->asic_type) {
1440 case CHIP_POLARIS11:
1441 case CHIP_POLARIS10:
1442 case CHIP_POLARIS12:
1444 if (dce110_register_irq_handlers(dm->adev)) {
1445 DRM_ERROR("DM: Failed to initialize IRQ\n");
1449 #if defined(CONFIG_DRM_AMD_DC_DCN1_0)
1451 if (dcn10_register_irq_handlers(dm->adev)) {
1452 DRM_ERROR("DM: Failed to initialize IRQ\n");
1456 * Temporary disable until pplib/smu interaction is implemented
1458 dm->dc->debug.disable_stutter = true;
1462 DRM_ERROR("Usupported ASIC type: 0x%X\n", adev->asic_type);
1470 for (i = 0; i < dm->dc->caps.max_planes; i++)
1471 kfree(mode_info->planes[i]);
1475 static void amdgpu_dm_destroy_drm_device(struct amdgpu_display_manager *dm)
1477 drm_mode_config_cleanup(dm->ddev);
1481 /******************************************************************************
1482 * amdgpu_display_funcs functions
1483 *****************************************************************************/
1486 * dm_bandwidth_update - program display watermarks
1488 * @adev: amdgpu_device pointer
1490 * Calculate and program the display watermarks and line buffer allocation.
1492 static void dm_bandwidth_update(struct amdgpu_device *adev)
1494 /* TODO: implement later */
1497 static void dm_set_backlight_level(struct amdgpu_encoder *amdgpu_encoder,
1500 /* TODO: translate amdgpu_encoder to display_index and call DAL */
1503 static u8 dm_get_backlight_level(struct amdgpu_encoder *amdgpu_encoder)
1505 /* TODO: translate amdgpu_encoder to display_index and call DAL */
1509 static int amdgpu_notify_freesync(struct drm_device *dev, void *data,
1510 struct drm_file *filp)
1512 struct mod_freesync_params freesync_params;
1513 uint8_t num_streams;
1516 struct amdgpu_device *adev = dev->dev_private;
1519 /* Get freesync enable flag from DRM */
1521 num_streams = dc_get_current_stream_count(adev->dm.dc);
1523 for (i = 0; i < num_streams; i++) {
1524 struct dc_stream_state *stream;
1525 stream = dc_get_stream_at_index(adev->dm.dc, i);
1527 mod_freesync_update_state(adev->dm.freesync_module,
1528 &stream, 1, &freesync_params);
1534 static const struct amdgpu_display_funcs dm_display_funcs = {
1535 .bandwidth_update = dm_bandwidth_update, /* called unconditionally */
1536 .vblank_get_counter = dm_vblank_get_counter,/* called unconditionally */
1537 .vblank_wait = NULL,
1538 .backlight_set_level =
1539 dm_set_backlight_level,/* called unconditionally */
1540 .backlight_get_level =
1541 dm_get_backlight_level,/* called unconditionally */
1542 .hpd_sense = NULL,/* called unconditionally */
1543 .hpd_set_polarity = NULL, /* called unconditionally */
1544 .hpd_get_gpio_reg = NULL, /* VBIOS parsing. DAL does it. */
1545 .page_flip_get_scanoutpos =
1546 dm_crtc_get_scanoutpos,/* called unconditionally */
1547 .add_encoder = NULL, /* VBIOS parsing. DAL does it. */
1548 .add_connector = NULL, /* VBIOS parsing. DAL does it. */
1549 .notify_freesync = amdgpu_notify_freesync,
1553 #if defined(CONFIG_DEBUG_KERNEL_DC)
1555 static ssize_t s3_debug_store(struct device *device,
1556 struct device_attribute *attr,
1562 struct pci_dev *pdev = to_pci_dev(device);
1563 struct drm_device *drm_dev = pci_get_drvdata(pdev);
1564 struct amdgpu_device *adev = drm_dev->dev_private;
1566 ret = kstrtoint(buf, 0, &s3_state);
1571 amdgpu_dm_display_resume(adev);
1572 drm_kms_helper_hotplug_event(adev->ddev);
1577 return ret == 0 ? count : 0;
1580 DEVICE_ATTR_WO(s3_debug);
1584 static int dm_early_init(void *handle)
1586 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1588 adev->ddev->driver->driver_features |= DRIVER_ATOMIC;
1589 amdgpu_dm_set_irq_funcs(adev);
1591 switch (adev->asic_type) {
1594 adev->mode_info.num_crtc = 6;
1595 adev->mode_info.num_hpd = 6;
1596 adev->mode_info.num_dig = 6;
1597 adev->mode_info.plane_type = dm_plane_type_default;
1600 adev->mode_info.num_crtc = 4;
1601 adev->mode_info.num_hpd = 6;
1602 adev->mode_info.num_dig = 7;
1603 adev->mode_info.plane_type = dm_plane_type_default;
1607 adev->mode_info.num_crtc = 2;
1608 adev->mode_info.num_hpd = 6;
1609 adev->mode_info.num_dig = 6;
1610 adev->mode_info.plane_type = dm_plane_type_default;
1614 adev->mode_info.num_crtc = 6;
1615 adev->mode_info.num_hpd = 6;
1616 adev->mode_info.num_dig = 7;
1617 adev->mode_info.plane_type = dm_plane_type_default;
1620 adev->mode_info.num_crtc = 3;
1621 adev->mode_info.num_hpd = 6;
1622 adev->mode_info.num_dig = 9;
1623 adev->mode_info.plane_type = dm_plane_type_carizzo;
1626 adev->mode_info.num_crtc = 2;
1627 adev->mode_info.num_hpd = 6;
1628 adev->mode_info.num_dig = 9;
1629 adev->mode_info.plane_type = dm_plane_type_stoney;
1631 case CHIP_POLARIS11:
1632 case CHIP_POLARIS12:
1633 adev->mode_info.num_crtc = 5;
1634 adev->mode_info.num_hpd = 5;
1635 adev->mode_info.num_dig = 5;
1636 adev->mode_info.plane_type = dm_plane_type_default;
1638 case CHIP_POLARIS10:
1639 adev->mode_info.num_crtc = 6;
1640 adev->mode_info.num_hpd = 6;
1641 adev->mode_info.num_dig = 6;
1642 adev->mode_info.plane_type = dm_plane_type_default;
1645 adev->mode_info.num_crtc = 6;
1646 adev->mode_info.num_hpd = 6;
1647 adev->mode_info.num_dig = 6;
1648 adev->mode_info.plane_type = dm_plane_type_default;
1650 #if defined(CONFIG_DRM_AMD_DC_DCN1_0)
1652 adev->mode_info.num_crtc = 4;
1653 adev->mode_info.num_hpd = 4;
1654 adev->mode_info.num_dig = 4;
1655 adev->mode_info.plane_type = dm_plane_type_default;
1659 DRM_ERROR("Usupported ASIC type: 0x%X\n", adev->asic_type);
1663 if (adev->mode_info.funcs == NULL)
1664 adev->mode_info.funcs = &dm_display_funcs;
1666 /* Note: Do NOT change adev->audio_endpt_rreg and
1667 * adev->audio_endpt_wreg because they are initialised in
1668 * amdgpu_device_init() */
1669 #if defined(CONFIG_DEBUG_KERNEL_DC)
1672 &dev_attr_s3_debug);
1678 struct dm_connector_state {
1679 struct drm_connector_state base;
1681 enum amdgpu_rmx_type scaling;
1682 uint8_t underscan_vborder;
1683 uint8_t underscan_hborder;
1684 bool underscan_enable;
1687 #define to_dm_connector_state(x)\
1688 container_of((x), struct dm_connector_state, base)
1690 static bool modeset_required(struct drm_crtc_state *crtc_state,
1691 struct dc_stream_state *new_stream,
1692 struct dc_stream_state *old_stream)
1694 if (!drm_atomic_crtc_needs_modeset(crtc_state))
1697 if (!crtc_state->enable)
1700 return crtc_state->active;
1703 static bool modereset_required(struct drm_crtc_state *crtc_state)
1705 if (!drm_atomic_crtc_needs_modeset(crtc_state))
1708 return !crtc_state->enable || !crtc_state->active;
1711 static void amdgpu_dm_encoder_destroy(struct drm_encoder *encoder)
1713 drm_encoder_cleanup(encoder);
1717 static const struct drm_encoder_funcs amdgpu_dm_encoder_funcs = {
1718 .destroy = amdgpu_dm_encoder_destroy,
1721 static bool fill_rects_from_plane_state(const struct drm_plane_state *state,
1722 struct dc_plane_state *plane_state)
1724 plane_state->src_rect.x = state->src_x >> 16;
1725 plane_state->src_rect.y = state->src_y >> 16;
1726 /*we ignore for now mantissa and do not to deal with floating pixels :(*/
1727 plane_state->src_rect.width = state->src_w >> 16;
1729 if (plane_state->src_rect.width == 0)
1732 plane_state->src_rect.height = state->src_h >> 16;
1733 if (plane_state->src_rect.height == 0)
1736 plane_state->dst_rect.x = state->crtc_x;
1737 plane_state->dst_rect.y = state->crtc_y;
1739 if (state->crtc_w == 0)
1742 plane_state->dst_rect.width = state->crtc_w;
1744 if (state->crtc_h == 0)
1747 plane_state->dst_rect.height = state->crtc_h;
1749 plane_state->clip_rect = plane_state->dst_rect;
1751 switch (state->rotation & DRM_MODE_ROTATE_MASK) {
1752 case DRM_MODE_ROTATE_0:
1753 plane_state->rotation = ROTATION_ANGLE_0;
1755 case DRM_MODE_ROTATE_90:
1756 plane_state->rotation = ROTATION_ANGLE_90;
1758 case DRM_MODE_ROTATE_180:
1759 plane_state->rotation = ROTATION_ANGLE_180;
1761 case DRM_MODE_ROTATE_270:
1762 plane_state->rotation = ROTATION_ANGLE_270;
1765 plane_state->rotation = ROTATION_ANGLE_0;
1771 static int get_fb_info(const struct amdgpu_framebuffer *amdgpu_fb,
1772 uint64_t *tiling_flags,
1773 uint64_t *fb_location)
1775 struct amdgpu_bo *rbo = gem_to_amdgpu_bo(amdgpu_fb->obj);
1776 int r = amdgpu_bo_reserve(rbo, false);
1779 // Don't show error msg. when return -ERESTARTSYS
1780 if (r != -ERESTARTSYS)
1781 DRM_ERROR("Unable to reserve buffer: %d\n", r);
1786 *fb_location = amdgpu_bo_gpu_offset(rbo);
1789 amdgpu_bo_get_tiling_flags(rbo, tiling_flags);
1791 amdgpu_bo_unreserve(rbo);
1796 static int fill_plane_attributes_from_fb(struct amdgpu_device *adev,
1797 struct dc_plane_state *plane_state,
1798 const struct amdgpu_framebuffer *amdgpu_fb,
1801 uint64_t tiling_flags;
1802 uint64_t fb_location = 0;
1803 uint64_t chroma_addr = 0;
1804 unsigned int awidth;
1805 const struct drm_framebuffer *fb = &amdgpu_fb->base;
1807 struct drm_format_name_buf format_name;
1812 addReq == true ? &fb_location:NULL);
1817 switch (fb->format->format) {
1819 plane_state->format = SURFACE_PIXEL_FORMAT_GRPH_PALETA_256_COLORS;
1821 case DRM_FORMAT_RGB565:
1822 plane_state->format = SURFACE_PIXEL_FORMAT_GRPH_RGB565;
1824 case DRM_FORMAT_XRGB8888:
1825 case DRM_FORMAT_ARGB8888:
1826 plane_state->format = SURFACE_PIXEL_FORMAT_GRPH_ARGB8888;
1828 case DRM_FORMAT_XRGB2101010:
1829 case DRM_FORMAT_ARGB2101010:
1830 plane_state->format = SURFACE_PIXEL_FORMAT_GRPH_ARGB2101010;
1832 case DRM_FORMAT_XBGR2101010:
1833 case DRM_FORMAT_ABGR2101010:
1834 plane_state->format = SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010;
1836 case DRM_FORMAT_NV21:
1837 plane_state->format = SURFACE_PIXEL_FORMAT_VIDEO_420_YCbCr;
1839 case DRM_FORMAT_NV12:
1840 plane_state->format = SURFACE_PIXEL_FORMAT_VIDEO_420_YCrCb;
1843 DRM_ERROR("Unsupported screen format %s\n",
1844 drm_get_format_name(fb->format->format, &format_name));
1848 if (plane_state->format < SURFACE_PIXEL_FORMAT_VIDEO_BEGIN) {
1849 plane_state->address.type = PLN_ADDR_TYPE_GRAPHICS;
1850 plane_state->address.grph.addr.low_part = lower_32_bits(fb_location);
1851 plane_state->address.grph.addr.high_part = upper_32_bits(fb_location);
1852 plane_state->plane_size.grph.surface_size.x = 0;
1853 plane_state->plane_size.grph.surface_size.y = 0;
1854 plane_state->plane_size.grph.surface_size.width = fb->width;
1855 plane_state->plane_size.grph.surface_size.height = fb->height;
1856 plane_state->plane_size.grph.surface_pitch =
1857 fb->pitches[0] / fb->format->cpp[0];
1858 /* TODO: unhardcode */
1859 plane_state->color_space = COLOR_SPACE_SRGB;
1862 awidth = ALIGN(fb->width, 64);
1863 plane_state->address.type = PLN_ADDR_TYPE_VIDEO_PROGRESSIVE;
1864 plane_state->address.video_progressive.luma_addr.low_part
1865 = lower_32_bits(fb_location);
1866 plane_state->address.video_progressive.luma_addr.high_part
1867 = upper_32_bits(fb_location);
1868 chroma_addr = fb_location + (u64)(awidth * fb->height);
1869 plane_state->address.video_progressive.chroma_addr.low_part
1870 = lower_32_bits(chroma_addr);
1871 plane_state->address.video_progressive.chroma_addr.high_part
1872 = upper_32_bits(chroma_addr);
1873 plane_state->plane_size.video.luma_size.x = 0;
1874 plane_state->plane_size.video.luma_size.y = 0;
1875 plane_state->plane_size.video.luma_size.width = awidth;
1876 plane_state->plane_size.video.luma_size.height = fb->height;
1877 /* TODO: unhardcode */
1878 plane_state->plane_size.video.luma_pitch = awidth;
1880 plane_state->plane_size.video.chroma_size.x = 0;
1881 plane_state->plane_size.video.chroma_size.y = 0;
1882 plane_state->plane_size.video.chroma_size.width = awidth;
1883 plane_state->plane_size.video.chroma_size.height = fb->height;
1884 plane_state->plane_size.video.chroma_pitch = awidth / 2;
1886 /* TODO: unhardcode */
1887 plane_state->color_space = COLOR_SPACE_YCBCR709;
1890 memset(&plane_state->tiling_info, 0, sizeof(plane_state->tiling_info));
1892 /* Fill GFX8 params */
1893 if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE) == DC_ARRAY_2D_TILED_THIN1) {
1894 unsigned int bankw, bankh, mtaspect, tile_split, num_banks;
1896 bankw = AMDGPU_TILING_GET(tiling_flags, BANK_WIDTH);
1897 bankh = AMDGPU_TILING_GET(tiling_flags, BANK_HEIGHT);
1898 mtaspect = AMDGPU_TILING_GET(tiling_flags, MACRO_TILE_ASPECT);
1899 tile_split = AMDGPU_TILING_GET(tiling_flags, TILE_SPLIT);
1900 num_banks = AMDGPU_TILING_GET(tiling_flags, NUM_BANKS);
1902 /* XXX fix me for VI */
1903 plane_state->tiling_info.gfx8.num_banks = num_banks;
1904 plane_state->tiling_info.gfx8.array_mode =
1905 DC_ARRAY_2D_TILED_THIN1;
1906 plane_state->tiling_info.gfx8.tile_split = tile_split;
1907 plane_state->tiling_info.gfx8.bank_width = bankw;
1908 plane_state->tiling_info.gfx8.bank_height = bankh;
1909 plane_state->tiling_info.gfx8.tile_aspect = mtaspect;
1910 plane_state->tiling_info.gfx8.tile_mode =
1911 DC_ADDR_SURF_MICRO_TILING_DISPLAY;
1912 } else if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE)
1913 == DC_ARRAY_1D_TILED_THIN1) {
1914 plane_state->tiling_info.gfx8.array_mode = DC_ARRAY_1D_TILED_THIN1;
1917 plane_state->tiling_info.gfx8.pipe_config =
1918 AMDGPU_TILING_GET(tiling_flags, PIPE_CONFIG);
1920 if (adev->asic_type == CHIP_VEGA10 ||
1921 adev->asic_type == CHIP_RAVEN) {
1922 /* Fill GFX9 params */
1923 plane_state->tiling_info.gfx9.num_pipes =
1924 adev->gfx.config.gb_addr_config_fields.num_pipes;
1925 plane_state->tiling_info.gfx9.num_banks =
1926 adev->gfx.config.gb_addr_config_fields.num_banks;
1927 plane_state->tiling_info.gfx9.pipe_interleave =
1928 adev->gfx.config.gb_addr_config_fields.pipe_interleave_size;
1929 plane_state->tiling_info.gfx9.num_shader_engines =
1930 adev->gfx.config.gb_addr_config_fields.num_se;
1931 plane_state->tiling_info.gfx9.max_compressed_frags =
1932 adev->gfx.config.gb_addr_config_fields.max_compress_frags;
1933 plane_state->tiling_info.gfx9.num_rb_per_se =
1934 adev->gfx.config.gb_addr_config_fields.num_rb_per_se;
1935 plane_state->tiling_info.gfx9.swizzle =
1936 AMDGPU_TILING_GET(tiling_flags, SWIZZLE_MODE);
1937 plane_state->tiling_info.gfx9.shaderEnable = 1;
1940 plane_state->visible = true;
1941 plane_state->scaling_quality.h_taps_c = 0;
1942 plane_state->scaling_quality.v_taps_c = 0;
1944 /* is this needed? is plane_state zeroed at allocation? */
1945 plane_state->scaling_quality.h_taps = 0;
1946 plane_state->scaling_quality.v_taps = 0;
1947 plane_state->stereo_format = PLANE_STEREO_FORMAT_NONE;
1953 static void fill_gamma_from_crtc_state(const struct drm_crtc_state *crtc_state,
1954 struct dc_plane_state *plane_state)
1957 struct dc_gamma *gamma;
1958 struct drm_color_lut *lut =
1959 (struct drm_color_lut *) crtc_state->gamma_lut->data;
1961 gamma = dc_create_gamma();
1963 if (gamma == NULL) {
1968 gamma->type = GAMMA_RGB_256;
1969 gamma->num_entries = GAMMA_RGB_256_ENTRIES;
1970 for (i = 0; i < GAMMA_RGB_256_ENTRIES; i++) {
1971 gamma->entries.red[i] = dal_fixed31_32_from_int(lut[i].red);
1972 gamma->entries.green[i] = dal_fixed31_32_from_int(lut[i].green);
1973 gamma->entries.blue[i] = dal_fixed31_32_from_int(lut[i].blue);
1976 plane_state->gamma_correction = gamma;
1979 static int fill_plane_attributes(struct amdgpu_device *adev,
1980 struct dc_plane_state *dc_plane_state,
1981 struct drm_plane_state *plane_state,
1982 struct drm_crtc_state *crtc_state,
1985 const struct amdgpu_framebuffer *amdgpu_fb =
1986 to_amdgpu_framebuffer(plane_state->fb);
1987 const struct drm_crtc *crtc = plane_state->crtc;
1988 struct dc_transfer_func *input_tf;
1991 if (!fill_rects_from_plane_state(plane_state, dc_plane_state))
1994 ret = fill_plane_attributes_from_fb(
1995 crtc->dev->dev_private,
2003 input_tf = dc_create_transfer_func();
2005 if (input_tf == NULL)
2008 input_tf->type = TF_TYPE_PREDEFINED;
2009 input_tf->tf = TRANSFER_FUNCTION_SRGB;
2011 dc_plane_state->in_transfer_func = input_tf;
2013 /* In case of gamma set, update gamma value */
2014 if (crtc_state->gamma_lut)
2015 fill_gamma_from_crtc_state(crtc_state, dc_plane_state);
2020 /*****************************************************************************/
2022 static void update_stream_scaling_settings(const struct drm_display_mode *mode,
2023 const struct dm_connector_state *dm_state,
2024 struct dc_stream_state *stream)
2026 enum amdgpu_rmx_type rmx_type;
2028 struct rect src = { 0 }; /* viewport in composition space*/
2029 struct rect dst = { 0 }; /* stream addressable area */
2031 /* no mode. nothing to be done */
2035 /* Full screen scaling by default */
2036 src.width = mode->hdisplay;
2037 src.height = mode->vdisplay;
2038 dst.width = stream->timing.h_addressable;
2039 dst.height = stream->timing.v_addressable;
2041 rmx_type = dm_state->scaling;
2042 if (rmx_type == RMX_ASPECT || rmx_type == RMX_OFF) {
2043 if (src.width * dst.height <
2044 src.height * dst.width) {
2045 /* height needs less upscaling/more downscaling */
2046 dst.width = src.width *
2047 dst.height / src.height;
2049 /* width needs less upscaling/more downscaling */
2050 dst.height = src.height *
2051 dst.width / src.width;
2053 } else if (rmx_type == RMX_CENTER) {
2057 dst.x = (stream->timing.h_addressable - dst.width) / 2;
2058 dst.y = (stream->timing.v_addressable - dst.height) / 2;
2060 if (dm_state->underscan_enable) {
2061 dst.x += dm_state->underscan_hborder / 2;
2062 dst.y += dm_state->underscan_vborder / 2;
2063 dst.width -= dm_state->underscan_hborder;
2064 dst.height -= dm_state->underscan_vborder;
2070 DRM_DEBUG_DRIVER("Destination Rectangle x:%d y:%d width:%d height:%d\n",
2071 dst.x, dst.y, dst.width, dst.height);
2075 static enum dc_color_depth
2076 convert_color_depth_from_display_info(const struct drm_connector *connector)
2078 uint32_t bpc = connector->display_info.bpc;
2080 /* Limited color depth to 8bit
2081 * TODO: Still need to handle deep color
2088 /* Temporary Work around, DRM don't parse color depth for
2089 * EDID revision before 1.4
2090 * TODO: Fix edid parsing
2092 return COLOR_DEPTH_888;
2094 return COLOR_DEPTH_666;
2096 return COLOR_DEPTH_888;
2098 return COLOR_DEPTH_101010;
2100 return COLOR_DEPTH_121212;
2102 return COLOR_DEPTH_141414;
2104 return COLOR_DEPTH_161616;
2106 return COLOR_DEPTH_UNDEFINED;
2110 static enum dc_aspect_ratio
2111 get_aspect_ratio(const struct drm_display_mode *mode_in)
2113 int32_t width = mode_in->crtc_hdisplay * 9;
2114 int32_t height = mode_in->crtc_vdisplay * 16;
2116 if ((width - height) < 10 && (width - height) > -10)
2117 return ASPECT_RATIO_16_9;
2119 return ASPECT_RATIO_4_3;
2122 static enum dc_color_space
2123 get_output_color_space(const struct dc_crtc_timing *dc_crtc_timing)
2125 enum dc_color_space color_space = COLOR_SPACE_SRGB;
2127 switch (dc_crtc_timing->pixel_encoding) {
2128 case PIXEL_ENCODING_YCBCR422:
2129 case PIXEL_ENCODING_YCBCR444:
2130 case PIXEL_ENCODING_YCBCR420:
2133 * 27030khz is the separation point between HDTV and SDTV
2134 * according to HDMI spec, we use YCbCr709 and YCbCr601
2137 if (dc_crtc_timing->pix_clk_khz > 27030) {
2138 if (dc_crtc_timing->flags.Y_ONLY)
2140 COLOR_SPACE_YCBCR709_LIMITED;
2142 color_space = COLOR_SPACE_YCBCR709;
2144 if (dc_crtc_timing->flags.Y_ONLY)
2146 COLOR_SPACE_YCBCR601_LIMITED;
2148 color_space = COLOR_SPACE_YCBCR601;
2153 case PIXEL_ENCODING_RGB:
2154 color_space = COLOR_SPACE_SRGB;
2165 /*****************************************************************************/
2168 fill_stream_properties_from_drm_display_mode(struct dc_stream_state *stream,
2169 const struct drm_display_mode *mode_in,
2170 const struct drm_connector *connector)
2172 struct dc_crtc_timing *timing_out = &stream->timing;
2174 memset(timing_out, 0, sizeof(struct dc_crtc_timing));
2176 timing_out->h_border_left = 0;
2177 timing_out->h_border_right = 0;
2178 timing_out->v_border_top = 0;
2179 timing_out->v_border_bottom = 0;
2180 /* TODO: un-hardcode */
2182 if ((connector->display_info.color_formats & DRM_COLOR_FORMAT_YCRCB444)
2183 && stream->sink->sink_signal == SIGNAL_TYPE_HDMI_TYPE_A)
2184 timing_out->pixel_encoding = PIXEL_ENCODING_YCBCR444;
2186 timing_out->pixel_encoding = PIXEL_ENCODING_RGB;
2188 timing_out->timing_3d_format = TIMING_3D_FORMAT_NONE;
2189 timing_out->display_color_depth = convert_color_depth_from_display_info(
2191 timing_out->scan_type = SCANNING_TYPE_NODATA;
2192 timing_out->hdmi_vic = 0;
2193 timing_out->vic = drm_match_cea_mode(mode_in);
2195 timing_out->h_addressable = mode_in->crtc_hdisplay;
2196 timing_out->h_total = mode_in->crtc_htotal;
2197 timing_out->h_sync_width =
2198 mode_in->crtc_hsync_end - mode_in->crtc_hsync_start;
2199 timing_out->h_front_porch =
2200 mode_in->crtc_hsync_start - mode_in->crtc_hdisplay;
2201 timing_out->v_total = mode_in->crtc_vtotal;
2202 timing_out->v_addressable = mode_in->crtc_vdisplay;
2203 timing_out->v_front_porch =
2204 mode_in->crtc_vsync_start - mode_in->crtc_vdisplay;
2205 timing_out->v_sync_width =
2206 mode_in->crtc_vsync_end - mode_in->crtc_vsync_start;
2207 timing_out->pix_clk_khz = mode_in->crtc_clock;
2208 timing_out->aspect_ratio = get_aspect_ratio(mode_in);
2209 if (mode_in->flags & DRM_MODE_FLAG_PHSYNC)
2210 timing_out->flags.HSYNC_POSITIVE_POLARITY = 1;
2211 if (mode_in->flags & DRM_MODE_FLAG_PVSYNC)
2212 timing_out->flags.VSYNC_POSITIVE_POLARITY = 1;
2214 stream->output_color_space = get_output_color_space(timing_out);
2217 struct dc_transfer_func *tf = dc_create_transfer_func();
2219 tf->type = TF_TYPE_PREDEFINED;
2220 tf->tf = TRANSFER_FUNCTION_SRGB;
2221 stream->out_transfer_func = tf;
2225 static void fill_audio_info(struct audio_info *audio_info,
2226 const struct drm_connector *drm_connector,
2227 const struct dc_sink *dc_sink)
2230 int cea_revision = 0;
2231 const struct dc_edid_caps *edid_caps = &dc_sink->edid_caps;
2233 audio_info->manufacture_id = edid_caps->manufacturer_id;
2234 audio_info->product_id = edid_caps->product_id;
2236 cea_revision = drm_connector->display_info.cea_rev;
2238 strncpy(audio_info->display_name,
2239 edid_caps->display_name,
2240 AUDIO_INFO_DISPLAY_NAME_SIZE_IN_CHARS - 1);
2242 if (cea_revision >= 3) {
2243 audio_info->mode_count = edid_caps->audio_mode_count;
2245 for (i = 0; i < audio_info->mode_count; ++i) {
2246 audio_info->modes[i].format_code =
2247 (enum audio_format_code)
2248 (edid_caps->audio_modes[i].format_code);
2249 audio_info->modes[i].channel_count =
2250 edid_caps->audio_modes[i].channel_count;
2251 audio_info->modes[i].sample_rates.all =
2252 edid_caps->audio_modes[i].sample_rate;
2253 audio_info->modes[i].sample_size =
2254 edid_caps->audio_modes[i].sample_size;
2258 audio_info->flags.all = edid_caps->speaker_flags;
2260 /* TODO: We only check for the progressive mode, check for interlace mode too */
2261 if (drm_connector->latency_present[0]) {
2262 audio_info->video_latency = drm_connector->video_latency[0];
2263 audio_info->audio_latency = drm_connector->audio_latency[0];
2266 /* TODO: For DP, video and audio latency should be calculated from DPCD caps */
2271 copy_crtc_timing_for_drm_display_mode(const struct drm_display_mode *src_mode,
2272 struct drm_display_mode *dst_mode)
2274 dst_mode->crtc_hdisplay = src_mode->crtc_hdisplay;
2275 dst_mode->crtc_vdisplay = src_mode->crtc_vdisplay;
2276 dst_mode->crtc_clock = src_mode->crtc_clock;
2277 dst_mode->crtc_hblank_start = src_mode->crtc_hblank_start;
2278 dst_mode->crtc_hblank_end = src_mode->crtc_hblank_end;
2279 dst_mode->crtc_hsync_start = src_mode->crtc_hsync_start;
2280 dst_mode->crtc_hsync_end = src_mode->crtc_hsync_end;
2281 dst_mode->crtc_htotal = src_mode->crtc_htotal;
2282 dst_mode->crtc_hskew = src_mode->crtc_hskew;
2283 dst_mode->crtc_vblank_start = src_mode->crtc_vblank_start;
2284 dst_mode->crtc_vblank_end = src_mode->crtc_vblank_end;
2285 dst_mode->crtc_vsync_start = src_mode->crtc_vsync_start;
2286 dst_mode->crtc_vsync_end = src_mode->crtc_vsync_end;
2287 dst_mode->crtc_vtotal = src_mode->crtc_vtotal;
2291 decide_crtc_timing_for_drm_display_mode(struct drm_display_mode *drm_mode,
2292 const struct drm_display_mode *native_mode,
2295 if (scale_enabled) {
2296 copy_crtc_timing_for_drm_display_mode(native_mode, drm_mode);
2297 } else if (native_mode->clock == drm_mode->clock &&
2298 native_mode->htotal == drm_mode->htotal &&
2299 native_mode->vtotal == drm_mode->vtotal) {
2300 copy_crtc_timing_for_drm_display_mode(native_mode, drm_mode);
2302 /* no scaling nor amdgpu inserted, no need to patch */
2306 static int create_fake_sink(struct amdgpu_dm_connector *aconnector)
2308 struct dc_sink *sink = NULL;
2309 struct dc_sink_init_data sink_init_data = { 0 };
2311 sink_init_data.link = aconnector->dc_link;
2312 sink_init_data.sink_signal = aconnector->dc_link->connector_signal;
2314 sink = dc_sink_create(&sink_init_data);
2316 DRM_ERROR("Failed to create sink!\n");
2320 sink->sink_signal = SIGNAL_TYPE_VIRTUAL;
2321 aconnector->fake_enable = true;
2323 aconnector->dc_sink = sink;
2324 aconnector->dc_link->local_sink = sink;
2329 static struct dc_stream_state *
2330 create_stream_for_sink(struct amdgpu_dm_connector *aconnector,
2331 const struct drm_display_mode *drm_mode,
2332 const struct dm_connector_state *dm_state)
2334 struct drm_display_mode *preferred_mode = NULL;
2335 const struct drm_connector *drm_connector;
2336 struct dc_stream_state *stream = NULL;
2337 struct drm_display_mode mode = *drm_mode;
2338 bool native_mode_found = false;
2340 if (aconnector == NULL) {
2341 DRM_ERROR("aconnector is NULL!\n");
2342 goto drm_connector_null;
2345 if (dm_state == NULL) {
2346 DRM_ERROR("dm_state is NULL!\n");
2350 drm_connector = &aconnector->base;
2352 if (!aconnector->dc_sink) {
2354 * Exclude MST from creating fake_sink
2355 * TODO: need to enable MST into fake_sink feature
2357 if (aconnector->mst_port)
2358 goto stream_create_fail;
2360 if (create_fake_sink(aconnector))
2361 goto stream_create_fail;
2364 stream = dc_create_stream_for_sink(aconnector->dc_sink);
2366 if (stream == NULL) {
2367 DRM_ERROR("Failed to create stream for sink!\n");
2368 goto stream_create_fail;
2371 list_for_each_entry(preferred_mode, &aconnector->base.modes, head) {
2372 /* Search for preferred mode */
2373 if (preferred_mode->type & DRM_MODE_TYPE_PREFERRED) {
2374 native_mode_found = true;
2378 if (!native_mode_found)
2379 preferred_mode = list_first_entry_or_null(
2380 &aconnector->base.modes,
2381 struct drm_display_mode,
2384 if (preferred_mode == NULL) {
2385 /* This may not be an error, the use case is when we we have no
2386 * usermode calls to reset and set mode upon hotplug. In this
2387 * case, we call set mode ourselves to restore the previous mode
2388 * and the modelist may not be filled in in time.
2390 DRM_DEBUG_DRIVER("No preferred mode found\n");
2392 decide_crtc_timing_for_drm_display_mode(
2393 &mode, preferred_mode,
2394 dm_state->scaling != RMX_OFF);
2397 fill_stream_properties_from_drm_display_mode(stream,
2398 &mode, &aconnector->base);
2399 update_stream_scaling_settings(&mode, dm_state, stream);
2402 &stream->audio_info,
2404 aconnector->dc_sink);
2412 static void amdgpu_dm_crtc_destroy(struct drm_crtc *crtc)
2414 drm_crtc_cleanup(crtc);
2418 static void dm_crtc_destroy_state(struct drm_crtc *crtc,
2419 struct drm_crtc_state *state)
2421 struct dm_crtc_state *cur = to_dm_crtc_state(state);
2423 /* TODO Destroy dc_stream objects are stream object is flattened */
2425 dc_stream_release(cur->stream);
2428 __drm_atomic_helper_crtc_destroy_state(state);
2434 static void dm_crtc_reset_state(struct drm_crtc *crtc)
2436 struct dm_crtc_state *state;
2439 dm_crtc_destroy_state(crtc, crtc->state);
2441 state = kzalloc(sizeof(*state), GFP_KERNEL);
2442 if (WARN_ON(!state))
2445 crtc->state = &state->base;
2446 crtc->state->crtc = crtc;
2450 static struct drm_crtc_state *
2451 dm_crtc_duplicate_state(struct drm_crtc *crtc)
2453 struct dm_crtc_state *state, *cur;
2455 cur = to_dm_crtc_state(crtc->state);
2457 if (WARN_ON(!crtc->state))
2460 state = kzalloc(sizeof(*state), GFP_KERNEL);
2464 __drm_atomic_helper_crtc_duplicate_state(crtc, &state->base);
2467 state->stream = cur->stream;
2468 dc_stream_retain(state->stream);
2471 /* TODO Duplicate dc_stream after objects are stream object is flattened */
2473 return &state->base;
2476 /* Implemented only the options currently availible for the driver */
2477 static const struct drm_crtc_funcs amdgpu_dm_crtc_funcs = {
2478 .reset = dm_crtc_reset_state,
2479 .destroy = amdgpu_dm_crtc_destroy,
2480 .gamma_set = drm_atomic_helper_legacy_gamma_set,
2481 .set_config = drm_atomic_helper_set_config,
2482 .page_flip = drm_atomic_helper_page_flip,
2483 .atomic_duplicate_state = dm_crtc_duplicate_state,
2484 .atomic_destroy_state = dm_crtc_destroy_state,
2487 static enum drm_connector_status
2488 amdgpu_dm_connector_detect(struct drm_connector *connector, bool force)
2491 struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
2494 * 1. This interface is NOT called in context of HPD irq.
2495 * 2. This interface *is called* in context of user-mode ioctl. Which
2496 * makes it a bad place for *any* MST-related activit. */
2498 if (aconnector->base.force == DRM_FORCE_UNSPECIFIED &&
2499 !aconnector->fake_enable)
2500 connected = (aconnector->dc_sink != NULL);
2502 connected = (aconnector->base.force == DRM_FORCE_ON);
2504 return (connected ? connector_status_connected :
2505 connector_status_disconnected);
2508 int amdgpu_dm_connector_atomic_set_property(struct drm_connector *connector,
2509 struct drm_connector_state *connector_state,
2510 struct drm_property *property,
2513 struct drm_device *dev = connector->dev;
2514 struct amdgpu_device *adev = dev->dev_private;
2515 struct dm_connector_state *dm_old_state =
2516 to_dm_connector_state(connector->state);
2517 struct dm_connector_state *dm_new_state =
2518 to_dm_connector_state(connector_state);
2522 if (property == dev->mode_config.scaling_mode_property) {
2523 enum amdgpu_rmx_type rmx_type;
2526 case DRM_MODE_SCALE_CENTER:
2527 rmx_type = RMX_CENTER;
2529 case DRM_MODE_SCALE_ASPECT:
2530 rmx_type = RMX_ASPECT;
2532 case DRM_MODE_SCALE_FULLSCREEN:
2533 rmx_type = RMX_FULL;
2535 case DRM_MODE_SCALE_NONE:
2541 if (dm_old_state->scaling == rmx_type)
2544 dm_new_state->scaling = rmx_type;
2546 } else if (property == adev->mode_info.underscan_hborder_property) {
2547 dm_new_state->underscan_hborder = val;
2549 } else if (property == adev->mode_info.underscan_vborder_property) {
2550 dm_new_state->underscan_vborder = val;
2552 } else if (property == adev->mode_info.underscan_property) {
2553 dm_new_state->underscan_enable = val;
2560 int amdgpu_dm_connector_atomic_get_property(struct drm_connector *connector,
2561 const struct drm_connector_state *state,
2562 struct drm_property *property,
2565 struct drm_device *dev = connector->dev;
2566 struct amdgpu_device *adev = dev->dev_private;
2567 struct dm_connector_state *dm_state =
2568 to_dm_connector_state(state);
2571 if (property == dev->mode_config.scaling_mode_property) {
2572 switch (dm_state->scaling) {
2574 *val = DRM_MODE_SCALE_CENTER;
2577 *val = DRM_MODE_SCALE_ASPECT;
2580 *val = DRM_MODE_SCALE_FULLSCREEN;
2584 *val = DRM_MODE_SCALE_NONE;
2588 } else if (property == adev->mode_info.underscan_hborder_property) {
2589 *val = dm_state->underscan_hborder;
2591 } else if (property == adev->mode_info.underscan_vborder_property) {
2592 *val = dm_state->underscan_vborder;
2594 } else if (property == adev->mode_info.underscan_property) {
2595 *val = dm_state->underscan_enable;
2601 static void amdgpu_dm_connector_destroy(struct drm_connector *connector)
2603 struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
2604 const struct dc_link *link = aconnector->dc_link;
2605 struct amdgpu_device *adev = connector->dev->dev_private;
2606 struct amdgpu_display_manager *dm = &adev->dm;
2607 #if defined(CONFIG_BACKLIGHT_CLASS_DEVICE) ||\
2608 defined(CONFIG_BACKLIGHT_CLASS_DEVICE_MODULE)
2610 if (link->connector_signal & (SIGNAL_TYPE_EDP | SIGNAL_TYPE_LVDS)) {
2611 amdgpu_dm_register_backlight_device(dm);
2613 if (dm->backlight_dev) {
2614 backlight_device_unregister(dm->backlight_dev);
2615 dm->backlight_dev = NULL;
2620 drm_connector_unregister(connector);
2621 drm_connector_cleanup(connector);
2625 void amdgpu_dm_connector_funcs_reset(struct drm_connector *connector)
2627 struct dm_connector_state *state =
2628 to_dm_connector_state(connector->state);
2632 state = kzalloc(sizeof(*state), GFP_KERNEL);
2635 state->scaling = RMX_OFF;
2636 state->underscan_enable = false;
2637 state->underscan_hborder = 0;
2638 state->underscan_vborder = 0;
2640 connector->state = &state->base;
2641 connector->state->connector = connector;
2645 struct drm_connector_state *
2646 amdgpu_dm_connector_atomic_duplicate_state(struct drm_connector *connector)
2648 struct dm_connector_state *state =
2649 to_dm_connector_state(connector->state);
2651 struct dm_connector_state *new_state =
2652 kmemdup(state, sizeof(*state), GFP_KERNEL);
2655 __drm_atomic_helper_connector_duplicate_state(connector,
2657 return &new_state->base;
2663 static const struct drm_connector_funcs amdgpu_dm_connector_funcs = {
2664 .reset = amdgpu_dm_connector_funcs_reset,
2665 .detect = amdgpu_dm_connector_detect,
2666 .fill_modes = drm_helper_probe_single_connector_modes,
2667 .destroy = amdgpu_dm_connector_destroy,
2668 .atomic_duplicate_state = amdgpu_dm_connector_atomic_duplicate_state,
2669 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
2670 .atomic_set_property = amdgpu_dm_connector_atomic_set_property,
2671 .atomic_get_property = amdgpu_dm_connector_atomic_get_property
2674 static struct drm_encoder *best_encoder(struct drm_connector *connector)
2676 int enc_id = connector->encoder_ids[0];
2677 struct drm_mode_object *obj;
2678 struct drm_encoder *encoder;
2680 DRM_DEBUG_DRIVER("Finding the best encoder\n");
2682 /* pick the encoder ids */
2684 obj = drm_mode_object_find(connector->dev, NULL, enc_id, DRM_MODE_OBJECT_ENCODER);
2686 DRM_ERROR("Couldn't find a matching encoder for our connector\n");
2689 encoder = obj_to_encoder(obj);
2692 DRM_ERROR("No encoder id\n");
2696 static int get_modes(struct drm_connector *connector)
2698 return amdgpu_dm_connector_get_modes(connector);
2701 static void create_eml_sink(struct amdgpu_dm_connector *aconnector)
2703 struct dc_sink_init_data init_params = {
2704 .link = aconnector->dc_link,
2705 .sink_signal = SIGNAL_TYPE_VIRTUAL
2707 struct edid *edid = (struct edid *) aconnector->base.edid_blob_ptr->data;
2709 if (!aconnector->base.edid_blob_ptr ||
2710 !aconnector->base.edid_blob_ptr->data) {
2711 DRM_ERROR("No EDID firmware found on connector: %s ,forcing to OFF!\n",
2712 aconnector->base.name);
2714 aconnector->base.force = DRM_FORCE_OFF;
2715 aconnector->base.override_edid = false;
2719 aconnector->edid = edid;
2721 aconnector->dc_em_sink = dc_link_add_remote_sink(
2722 aconnector->dc_link,
2724 (edid->extensions + 1) * EDID_LENGTH,
2727 if (aconnector->base.force == DRM_FORCE_ON)
2728 aconnector->dc_sink = aconnector->dc_link->local_sink ?
2729 aconnector->dc_link->local_sink :
2730 aconnector->dc_em_sink;
2733 static void handle_edid_mgmt(struct amdgpu_dm_connector *aconnector)
2735 struct dc_link *link = (struct dc_link *)aconnector->dc_link;
2737 /* In case of headless boot with force on for DP managed connector
2738 * Those settings have to be != 0 to get initial modeset
2740 if (link->connector_signal == SIGNAL_TYPE_DISPLAY_PORT) {
2741 link->verified_link_cap.lane_count = LANE_COUNT_FOUR;
2742 link->verified_link_cap.link_rate = LINK_RATE_HIGH2;
2746 aconnector->base.override_edid = true;
2747 create_eml_sink(aconnector);
2750 int amdgpu_dm_connector_mode_valid(struct drm_connector *connector,
2751 struct drm_display_mode *mode)
2753 int result = MODE_ERROR;
2754 struct dc_sink *dc_sink;
2755 struct amdgpu_device *adev = connector->dev->dev_private;
2756 /* TODO: Unhardcode stream count */
2757 struct dc_stream_state *stream;
2758 struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
2760 if ((mode->flags & DRM_MODE_FLAG_INTERLACE) ||
2761 (mode->flags & DRM_MODE_FLAG_DBLSCAN))
2764 /* Only run this the first time mode_valid is called to initilialize
2767 if (aconnector->base.force != DRM_FORCE_UNSPECIFIED &&
2768 !aconnector->dc_em_sink)
2769 handle_edid_mgmt(aconnector);
2771 dc_sink = to_amdgpu_dm_connector(connector)->dc_sink;
2773 if (dc_sink == NULL) {
2774 DRM_ERROR("dc_sink is NULL!\n");
2778 stream = dc_create_stream_for_sink(dc_sink);
2779 if (stream == NULL) {
2780 DRM_ERROR("Failed to create stream for sink!\n");
2784 drm_mode_set_crtcinfo(mode, 0);
2785 fill_stream_properties_from_drm_display_mode(stream, mode, connector);
2787 stream->src.width = mode->hdisplay;
2788 stream->src.height = mode->vdisplay;
2789 stream->dst = stream->src;
2791 if (dc_validate_stream(adev->dm.dc, stream) == DC_OK)
2794 dc_stream_release(stream);
2797 /* TODO: error handling*/
2801 static const struct drm_connector_helper_funcs
2802 amdgpu_dm_connector_helper_funcs = {
2804 * If hotplug a second bigger display in FB Con mode, bigger resolution
2805 * modes will be filtered by drm_mode_validate_size(), and those modes
2806 * is missing after user start lightdm. So we need to renew modes list.
2807 * in get_modes call back, not just return the modes count
2809 .get_modes = get_modes,
2810 .mode_valid = amdgpu_dm_connector_mode_valid,
2811 .best_encoder = best_encoder
2814 static void dm_crtc_helper_disable(struct drm_crtc *crtc)
2818 static int dm_crtc_helper_atomic_check(struct drm_crtc *crtc,
2819 struct drm_crtc_state *state)
2821 struct amdgpu_device *adev = crtc->dev->dev_private;
2822 struct dc *dc = adev->dm.dc;
2823 struct dm_crtc_state *dm_crtc_state = to_dm_crtc_state(state);
2826 if (unlikely(!dm_crtc_state->stream &&
2827 modeset_required(state, NULL, dm_crtc_state->stream))) {
2832 /* In some use cases, like reset, no stream is attached */
2833 if (!dm_crtc_state->stream)
2836 if (dc_validate_stream(dc, dm_crtc_state->stream) == DC_OK)
2842 static bool dm_crtc_helper_mode_fixup(struct drm_crtc *crtc,
2843 const struct drm_display_mode *mode,
2844 struct drm_display_mode *adjusted_mode)
2849 static const struct drm_crtc_helper_funcs amdgpu_dm_crtc_helper_funcs = {
2850 .disable = dm_crtc_helper_disable,
2851 .atomic_check = dm_crtc_helper_atomic_check,
2852 .mode_fixup = dm_crtc_helper_mode_fixup
2855 static void dm_encoder_helper_disable(struct drm_encoder *encoder)
2860 static int dm_encoder_helper_atomic_check(struct drm_encoder *encoder,
2861 struct drm_crtc_state *crtc_state,
2862 struct drm_connector_state *conn_state)
2867 const struct drm_encoder_helper_funcs amdgpu_dm_encoder_helper_funcs = {
2868 .disable = dm_encoder_helper_disable,
2869 .atomic_check = dm_encoder_helper_atomic_check
2872 static void dm_drm_plane_reset(struct drm_plane *plane)
2874 struct dm_plane_state *amdgpu_state = NULL;
2877 plane->funcs->atomic_destroy_state(plane, plane->state);
2879 amdgpu_state = kzalloc(sizeof(*amdgpu_state), GFP_KERNEL);
2880 WARN_ON(amdgpu_state == NULL);
2883 plane->state = &amdgpu_state->base;
2884 plane->state->plane = plane;
2885 plane->state->rotation = DRM_MODE_ROTATE_0;
2889 static struct drm_plane_state *
2890 dm_drm_plane_duplicate_state(struct drm_plane *plane)
2892 struct dm_plane_state *dm_plane_state, *old_dm_plane_state;
2894 old_dm_plane_state = to_dm_plane_state(plane->state);
2895 dm_plane_state = kzalloc(sizeof(*dm_plane_state), GFP_KERNEL);
2896 if (!dm_plane_state)
2899 __drm_atomic_helper_plane_duplicate_state(plane, &dm_plane_state->base);
2901 if (old_dm_plane_state->dc_state) {
2902 dm_plane_state->dc_state = old_dm_plane_state->dc_state;
2903 dc_plane_state_retain(dm_plane_state->dc_state);
2906 return &dm_plane_state->base;
2909 void dm_drm_plane_destroy_state(struct drm_plane *plane,
2910 struct drm_plane_state *state)
2912 struct dm_plane_state *dm_plane_state = to_dm_plane_state(state);
2914 if (dm_plane_state->dc_state)
2915 dc_plane_state_release(dm_plane_state->dc_state);
2917 drm_atomic_helper_plane_destroy_state(plane, state);
2920 static const struct drm_plane_funcs dm_plane_funcs = {
2921 .update_plane = drm_atomic_helper_update_plane,
2922 .disable_plane = drm_atomic_helper_disable_plane,
2923 .destroy = drm_plane_cleanup,
2924 .reset = dm_drm_plane_reset,
2925 .atomic_duplicate_state = dm_drm_plane_duplicate_state,
2926 .atomic_destroy_state = dm_drm_plane_destroy_state,
2929 static int dm_plane_helper_prepare_fb(struct drm_plane *plane,
2930 struct drm_plane_state *new_state)
2932 struct amdgpu_framebuffer *afb;
2933 struct drm_gem_object *obj;
2934 struct amdgpu_bo *rbo;
2935 uint64_t chroma_addr = 0;
2937 struct dm_plane_state *dm_plane_state_new, *dm_plane_state_old;
2938 unsigned int awidth;
2940 dm_plane_state_old = to_dm_plane_state(plane->state);
2941 dm_plane_state_new = to_dm_plane_state(new_state);
2943 if (!new_state->fb) {
2944 DRM_DEBUG_DRIVER("No FB bound\n");
2948 afb = to_amdgpu_framebuffer(new_state->fb);
2951 rbo = gem_to_amdgpu_bo(obj);
2952 r = amdgpu_bo_reserve(rbo, false);
2953 if (unlikely(r != 0))
2956 r = amdgpu_bo_pin(rbo, AMDGPU_GEM_DOMAIN_VRAM, &afb->address);
2959 amdgpu_bo_unreserve(rbo);
2961 if (unlikely(r != 0)) {
2962 if (r != -ERESTARTSYS)
2963 DRM_ERROR("Failed to pin framebuffer with error %d\n", r);
2969 if (dm_plane_state_new->dc_state &&
2970 dm_plane_state_old->dc_state != dm_plane_state_new->dc_state) {
2971 struct dc_plane_state *plane_state = dm_plane_state_new->dc_state;
2973 if (plane_state->format < SURFACE_PIXEL_FORMAT_VIDEO_BEGIN) {
2974 plane_state->address.grph.addr.low_part = lower_32_bits(afb->address);
2975 plane_state->address.grph.addr.high_part = upper_32_bits(afb->address);
2977 awidth = ALIGN(new_state->fb->width, 64);
2978 plane_state->address.type = PLN_ADDR_TYPE_VIDEO_PROGRESSIVE;
2979 plane_state->address.video_progressive.luma_addr.low_part
2980 = lower_32_bits(afb->address);
2981 plane_state->address.video_progressive.luma_addr.high_part
2982 = upper_32_bits(afb->address);
2983 chroma_addr = afb->address + (u64)(awidth * new_state->fb->height);
2984 plane_state->address.video_progressive.chroma_addr.low_part
2985 = lower_32_bits(chroma_addr);
2986 plane_state->address.video_progressive.chroma_addr.high_part
2987 = upper_32_bits(chroma_addr);
2991 /* It's a hack for s3 since in 4.9 kernel filter out cursor buffer
2992 * prepare and cleanup in drm_atomic_helper_prepare_planes
2993 * and drm_atomic_helper_cleanup_planes because fb doens't in s3.
2994 * IN 4.10 kernel this code should be removed and amdgpu_device_suspend
2995 * code touching fram buffers should be avoided for DC.
2997 if (plane->type == DRM_PLANE_TYPE_CURSOR) {
2998 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(new_state->crtc);
3000 acrtc->cursor_bo = obj;
3005 static void dm_plane_helper_cleanup_fb(struct drm_plane *plane,
3006 struct drm_plane_state *old_state)
3008 struct amdgpu_bo *rbo;
3009 struct amdgpu_framebuffer *afb;
3015 afb = to_amdgpu_framebuffer(old_state->fb);
3016 rbo = gem_to_amdgpu_bo(afb->obj);
3017 r = amdgpu_bo_reserve(rbo, false);
3019 DRM_ERROR("failed to reserve rbo before unpin\n");
3023 amdgpu_bo_unpin(rbo);
3024 amdgpu_bo_unreserve(rbo);
3025 amdgpu_bo_unref(&rbo);
3028 static int dm_plane_atomic_check(struct drm_plane *plane,
3029 struct drm_plane_state *state)
3031 struct amdgpu_device *adev = plane->dev->dev_private;
3032 struct dc *dc = adev->dm.dc;
3033 struct dm_plane_state *dm_plane_state = to_dm_plane_state(state);
3035 if (!dm_plane_state->dc_state)
3038 if (dc_validate_plane(dc, dm_plane_state->dc_state) == DC_OK)
3044 static const struct drm_plane_helper_funcs dm_plane_helper_funcs = {
3045 .prepare_fb = dm_plane_helper_prepare_fb,
3046 .cleanup_fb = dm_plane_helper_cleanup_fb,
3047 .atomic_check = dm_plane_atomic_check,
3051 * TODO: these are currently initialized to rgb formats only.
3052 * For future use cases we should either initialize them dynamically based on
3053 * plane capabilities, or initialize this array to all formats, so internal drm
3054 * check will succeed, and let DC to implement proper check
3056 static const uint32_t rgb_formats[] = {
3058 DRM_FORMAT_XRGB8888,
3059 DRM_FORMAT_ARGB8888,
3060 DRM_FORMAT_RGBA8888,
3061 DRM_FORMAT_XRGB2101010,
3062 DRM_FORMAT_XBGR2101010,
3063 DRM_FORMAT_ARGB2101010,
3064 DRM_FORMAT_ABGR2101010,
3067 static const uint32_t yuv_formats[] = {
3072 static const u32 cursor_formats[] = {
3076 static int amdgpu_dm_plane_init(struct amdgpu_display_manager *dm,
3077 struct amdgpu_plane *aplane,
3078 unsigned long possible_crtcs)
3082 switch (aplane->base.type) {
3083 case DRM_PLANE_TYPE_PRIMARY:
3084 aplane->base.format_default = true;
3086 res = drm_universal_plane_init(
3092 ARRAY_SIZE(rgb_formats),
3093 NULL, aplane->base.type, NULL);
3095 case DRM_PLANE_TYPE_OVERLAY:
3096 res = drm_universal_plane_init(
3102 ARRAY_SIZE(yuv_formats),
3103 NULL, aplane->base.type, NULL);
3105 case DRM_PLANE_TYPE_CURSOR:
3106 res = drm_universal_plane_init(
3112 ARRAY_SIZE(cursor_formats),
3113 NULL, aplane->base.type, NULL);
3117 drm_plane_helper_add(&aplane->base, &dm_plane_helper_funcs);
3119 /* Create (reset) the plane state */
3120 if (aplane->base.funcs->reset)
3121 aplane->base.funcs->reset(&aplane->base);
3127 static int amdgpu_dm_crtc_init(struct amdgpu_display_manager *dm,
3128 struct drm_plane *plane,
3129 uint32_t crtc_index)
3131 struct amdgpu_crtc *acrtc = NULL;
3132 struct amdgpu_plane *cursor_plane;
3136 cursor_plane = kzalloc(sizeof(*cursor_plane), GFP_KERNEL);
3140 cursor_plane->base.type = DRM_PLANE_TYPE_CURSOR;
3141 res = amdgpu_dm_plane_init(dm, cursor_plane, 0);
3143 acrtc = kzalloc(sizeof(struct amdgpu_crtc), GFP_KERNEL);
3147 res = drm_crtc_init_with_planes(
3151 &cursor_plane->base,
3152 &amdgpu_dm_crtc_funcs, NULL);
3157 drm_crtc_helper_add(&acrtc->base, &amdgpu_dm_crtc_helper_funcs);
3159 /* Create (reset) the plane state */
3160 if (acrtc->base.funcs->reset)
3161 acrtc->base.funcs->reset(&acrtc->base);
3163 acrtc->max_cursor_width = dm->adev->dm.dc->caps.max_cursor_size;
3164 acrtc->max_cursor_height = dm->adev->dm.dc->caps.max_cursor_size;
3166 acrtc->crtc_id = crtc_index;
3167 acrtc->base.enabled = false;
3169 dm->adev->mode_info.crtcs[crtc_index] = acrtc;
3170 drm_mode_crtc_set_gamma_size(&acrtc->base, 256);
3176 kfree(cursor_plane);
3181 static int to_drm_connector_type(enum signal_type st)
3184 case SIGNAL_TYPE_HDMI_TYPE_A:
3185 return DRM_MODE_CONNECTOR_HDMIA;
3186 case SIGNAL_TYPE_EDP:
3187 return DRM_MODE_CONNECTOR_eDP;
3188 case SIGNAL_TYPE_RGB:
3189 return DRM_MODE_CONNECTOR_VGA;
3190 case SIGNAL_TYPE_DISPLAY_PORT:
3191 case SIGNAL_TYPE_DISPLAY_PORT_MST:
3192 return DRM_MODE_CONNECTOR_DisplayPort;
3193 case SIGNAL_TYPE_DVI_DUAL_LINK:
3194 case SIGNAL_TYPE_DVI_SINGLE_LINK:
3195 return DRM_MODE_CONNECTOR_DVID;
3196 case SIGNAL_TYPE_VIRTUAL:
3197 return DRM_MODE_CONNECTOR_VIRTUAL;
3200 return DRM_MODE_CONNECTOR_Unknown;
3204 static void amdgpu_dm_get_native_mode(struct drm_connector *connector)
3206 const struct drm_connector_helper_funcs *helper =
3207 connector->helper_private;
3208 struct drm_encoder *encoder;
3209 struct amdgpu_encoder *amdgpu_encoder;
3211 encoder = helper->best_encoder(connector);
3213 if (encoder == NULL)
3216 amdgpu_encoder = to_amdgpu_encoder(encoder);
3218 amdgpu_encoder->native_mode.clock = 0;
3220 if (!list_empty(&connector->probed_modes)) {
3221 struct drm_display_mode *preferred_mode = NULL;
3223 list_for_each_entry(preferred_mode,
3224 &connector->probed_modes,
3226 if (preferred_mode->type & DRM_MODE_TYPE_PREFERRED)
3227 amdgpu_encoder->native_mode = *preferred_mode;
3235 static struct drm_display_mode *
3236 amdgpu_dm_create_common_mode(struct drm_encoder *encoder,
3238 int hdisplay, int vdisplay)
3240 struct drm_device *dev = encoder->dev;
3241 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
3242 struct drm_display_mode *mode = NULL;
3243 struct drm_display_mode *native_mode = &amdgpu_encoder->native_mode;
3245 mode = drm_mode_duplicate(dev, native_mode);
3250 mode->hdisplay = hdisplay;
3251 mode->vdisplay = vdisplay;
3252 mode->type &= ~DRM_MODE_TYPE_PREFERRED;
3253 strncpy(mode->name, name, DRM_DISPLAY_MODE_LEN);
3259 static void amdgpu_dm_connector_add_common_modes(struct drm_encoder *encoder,
3260 struct drm_connector *connector)
3262 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
3263 struct drm_display_mode *mode = NULL;
3264 struct drm_display_mode *native_mode = &amdgpu_encoder->native_mode;
3265 struct amdgpu_dm_connector *amdgpu_dm_connector =
3266 to_amdgpu_dm_connector(connector);
3270 char name[DRM_DISPLAY_MODE_LEN];
3273 } common_modes[] = {
3274 { "640x480", 640, 480},
3275 { "800x600", 800, 600},
3276 { "1024x768", 1024, 768},
3277 { "1280x720", 1280, 720},
3278 { "1280x800", 1280, 800},
3279 {"1280x1024", 1280, 1024},
3280 { "1440x900", 1440, 900},
3281 {"1680x1050", 1680, 1050},
3282 {"1600x1200", 1600, 1200},
3283 {"1920x1080", 1920, 1080},
3284 {"1920x1200", 1920, 1200}
3287 n = ARRAY_SIZE(common_modes);
3289 for (i = 0; i < n; i++) {
3290 struct drm_display_mode *curmode = NULL;
3291 bool mode_existed = false;
3293 if (common_modes[i].w > native_mode->hdisplay ||
3294 common_modes[i].h > native_mode->vdisplay ||
3295 (common_modes[i].w == native_mode->hdisplay &&
3296 common_modes[i].h == native_mode->vdisplay))
3299 list_for_each_entry(curmode, &connector->probed_modes, head) {
3300 if (common_modes[i].w == curmode->hdisplay &&
3301 common_modes[i].h == curmode->vdisplay) {
3302 mode_existed = true;
3310 mode = amdgpu_dm_create_common_mode(encoder,
3311 common_modes[i].name, common_modes[i].w,
3313 drm_mode_probed_add(connector, mode);
3314 amdgpu_dm_connector->num_modes++;
3318 static void amdgpu_dm_connector_ddc_get_modes(struct drm_connector *connector,
3321 struct amdgpu_dm_connector *amdgpu_dm_connector =
3322 to_amdgpu_dm_connector(connector);
3325 /* empty probed_modes */
3326 INIT_LIST_HEAD(&connector->probed_modes);
3327 amdgpu_dm_connector->num_modes =
3328 drm_add_edid_modes(connector, edid);
3330 drm_edid_to_eld(connector, edid);
3332 amdgpu_dm_get_native_mode(connector);
3334 amdgpu_dm_connector->num_modes = 0;
3338 static int amdgpu_dm_connector_get_modes(struct drm_connector *connector)
3340 const struct drm_connector_helper_funcs *helper =
3341 connector->helper_private;
3342 struct amdgpu_dm_connector *amdgpu_dm_connector =
3343 to_amdgpu_dm_connector(connector);
3344 struct drm_encoder *encoder;
3345 struct edid *edid = amdgpu_dm_connector->edid;
3347 encoder = helper->best_encoder(connector);
3349 amdgpu_dm_connector_ddc_get_modes(connector, edid);
3350 amdgpu_dm_connector_add_common_modes(encoder, connector);
3351 return amdgpu_dm_connector->num_modes;
3354 void amdgpu_dm_connector_init_helper(struct amdgpu_display_manager *dm,
3355 struct amdgpu_dm_connector *aconnector,
3357 struct dc_link *link,
3360 struct amdgpu_device *adev = dm->ddev->dev_private;
3362 aconnector->connector_id = link_index;
3363 aconnector->dc_link = link;
3364 aconnector->base.interlace_allowed = false;
3365 aconnector->base.doublescan_allowed = false;
3366 aconnector->base.stereo_allowed = false;
3367 aconnector->base.dpms = DRM_MODE_DPMS_OFF;
3368 aconnector->hpd.hpd = AMDGPU_HPD_NONE; /* not used */
3370 mutex_init(&aconnector->hpd_lock);
3372 /* configure support HPD hot plug connector_>polled default value is 0
3373 * which means HPD hot plug not supported
3375 switch (connector_type) {
3376 case DRM_MODE_CONNECTOR_HDMIA:
3377 aconnector->base.polled = DRM_CONNECTOR_POLL_HPD;
3379 case DRM_MODE_CONNECTOR_DisplayPort:
3380 aconnector->base.polled = DRM_CONNECTOR_POLL_HPD;
3382 case DRM_MODE_CONNECTOR_DVID:
3383 aconnector->base.polled = DRM_CONNECTOR_POLL_HPD;
3389 drm_object_attach_property(&aconnector->base.base,
3390 dm->ddev->mode_config.scaling_mode_property,
3391 DRM_MODE_SCALE_NONE);
3393 drm_object_attach_property(&aconnector->base.base,
3394 adev->mode_info.underscan_property,
3396 drm_object_attach_property(&aconnector->base.base,
3397 adev->mode_info.underscan_hborder_property,
3399 drm_object_attach_property(&aconnector->base.base,
3400 adev->mode_info.underscan_vborder_property,
3405 static int amdgpu_dm_i2c_xfer(struct i2c_adapter *i2c_adap,
3406 struct i2c_msg *msgs, int num)
3408 struct amdgpu_i2c_adapter *i2c = i2c_get_adapdata(i2c_adap);
3409 struct ddc_service *ddc_service = i2c->ddc_service;
3410 struct i2c_command cmd;
3414 cmd.payloads = kcalloc(num, sizeof(struct i2c_payload), GFP_KERNEL);
3419 cmd.number_of_payloads = num;
3420 cmd.engine = I2C_COMMAND_ENGINE_DEFAULT;
3423 for (i = 0; i < num; i++) {
3424 cmd.payloads[i].write = !(msgs[i].flags & I2C_M_RD);
3425 cmd.payloads[i].address = msgs[i].addr;
3426 cmd.payloads[i].length = msgs[i].len;
3427 cmd.payloads[i].data = msgs[i].buf;
3430 if (dal_i2caux_submit_i2c_command(
3431 ddc_service->ctx->i2caux,
3432 ddc_service->ddc_pin,
3436 kfree(cmd.payloads);
3440 static u32 amdgpu_dm_i2c_func(struct i2c_adapter *adap)
3442 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
3445 static const struct i2c_algorithm amdgpu_dm_i2c_algo = {
3446 .master_xfer = amdgpu_dm_i2c_xfer,
3447 .functionality = amdgpu_dm_i2c_func,
3450 static struct amdgpu_i2c_adapter *
3451 create_i2c(struct ddc_service *ddc_service,
3455 struct amdgpu_device *adev = ddc_service->ctx->driver_context;
3456 struct amdgpu_i2c_adapter *i2c;
3458 i2c = kzalloc(sizeof(struct amdgpu_i2c_adapter), GFP_KERNEL);
3461 i2c->base.owner = THIS_MODULE;
3462 i2c->base.class = I2C_CLASS_DDC;
3463 i2c->base.dev.parent = &adev->pdev->dev;
3464 i2c->base.algo = &amdgpu_dm_i2c_algo;
3465 snprintf(i2c->base.name, sizeof(i2c->base.name), "AMDGPU DM i2c hw bus %d", link_index);
3466 i2c_set_adapdata(&i2c->base, i2c);
3467 i2c->ddc_service = ddc_service;
3472 /* Note: this function assumes that dc_link_detect() was called for the
3473 * dc_link which will be represented by this aconnector.
3475 static int amdgpu_dm_connector_init(struct amdgpu_display_manager *dm,
3476 struct amdgpu_dm_connector *aconnector,
3477 uint32_t link_index,
3478 struct amdgpu_encoder *aencoder)
3482 struct dc *dc = dm->dc;
3483 struct dc_link *link = dc_get_link_at_index(dc, link_index);
3484 struct amdgpu_i2c_adapter *i2c;
3486 link->priv = aconnector;
3488 DRM_DEBUG_DRIVER("%s()\n", __func__);
3490 i2c = create_i2c(link->ddc, link->link_index, &res);
3492 DRM_ERROR("Failed to create i2c adapter data\n");
3496 aconnector->i2c = i2c;
3497 res = i2c_add_adapter(&i2c->base);
3500 DRM_ERROR("Failed to register hw i2c %d\n", link->link_index);
3504 connector_type = to_drm_connector_type(link->connector_signal);
3506 res = drm_connector_init(
3509 &amdgpu_dm_connector_funcs,
3513 DRM_ERROR("connector_init failed\n");
3514 aconnector->connector_id = -1;
3518 drm_connector_helper_add(
3520 &amdgpu_dm_connector_helper_funcs);
3522 if (aconnector->base.funcs->reset)
3523 aconnector->base.funcs->reset(&aconnector->base);
3525 amdgpu_dm_connector_init_helper(
3532 drm_mode_connector_attach_encoder(
3533 &aconnector->base, &aencoder->base);
3535 drm_connector_register(&aconnector->base);
3537 if (connector_type == DRM_MODE_CONNECTOR_DisplayPort
3538 || connector_type == DRM_MODE_CONNECTOR_eDP)
3539 amdgpu_dm_initialize_dp_connector(dm, aconnector);
3541 #if defined(CONFIG_BACKLIGHT_CLASS_DEVICE) ||\
3542 defined(CONFIG_BACKLIGHT_CLASS_DEVICE_MODULE)
3544 /* NOTE: this currently will create backlight device even if a panel
3545 * is not connected to the eDP/LVDS connector.
3547 * This is less than ideal but we don't have sink information at this
3548 * stage since detection happens after. We can't do detection earlier
3549 * since MST detection needs connectors to be created first.
3551 if (link->connector_signal & (SIGNAL_TYPE_EDP | SIGNAL_TYPE_LVDS)) {
3552 /* Event if registration failed, we should continue with
3553 * DM initialization because not having a backlight control
3554 * is better then a black screen.
3556 amdgpu_dm_register_backlight_device(dm);
3558 if (dm->backlight_dev)
3559 dm->backlight_link = link;
3566 aconnector->i2c = NULL;
3571 int amdgpu_dm_get_encoder_crtc_mask(struct amdgpu_device *adev)
3573 switch (adev->mode_info.num_crtc) {
3590 static int amdgpu_dm_encoder_init(struct drm_device *dev,
3591 struct amdgpu_encoder *aencoder,
3592 uint32_t link_index)
3594 struct amdgpu_device *adev = dev->dev_private;
3596 int res = drm_encoder_init(dev,
3598 &amdgpu_dm_encoder_funcs,
3599 DRM_MODE_ENCODER_TMDS,
3602 aencoder->base.possible_crtcs = amdgpu_dm_get_encoder_crtc_mask(adev);
3605 aencoder->encoder_id = link_index;
3607 aencoder->encoder_id = -1;
3609 drm_encoder_helper_add(&aencoder->base, &amdgpu_dm_encoder_helper_funcs);
3614 static void manage_dm_interrupts(struct amdgpu_device *adev,
3615 struct amdgpu_crtc *acrtc,
3619 * this is not correct translation but will work as soon as VBLANK
3620 * constant is the same as PFLIP
3623 amdgpu_crtc_idx_to_irq_type(
3628 drm_crtc_vblank_on(&acrtc->base);
3631 &adev->pageflip_irq,
3637 &adev->pageflip_irq,
3639 drm_crtc_vblank_off(&acrtc->base);
3644 is_scaling_state_different(const struct dm_connector_state *dm_state,
3645 const struct dm_connector_state *old_dm_state)
3647 if (dm_state->scaling != old_dm_state->scaling)
3649 if (!dm_state->underscan_enable && old_dm_state->underscan_enable) {
3650 if (old_dm_state->underscan_hborder != 0 && old_dm_state->underscan_vborder != 0)
3652 } else if (dm_state->underscan_enable && !old_dm_state->underscan_enable) {
3653 if (dm_state->underscan_hborder != 0 && dm_state->underscan_vborder != 0)
3655 } else if (dm_state->underscan_hborder != old_dm_state->underscan_hborder ||
3656 dm_state->underscan_vborder != old_dm_state->underscan_vborder)
3661 static void remove_stream(struct amdgpu_device *adev,
3662 struct amdgpu_crtc *acrtc,
3663 struct dc_stream_state *stream)
3665 /* this is the update mode case */
3666 if (adev->dm.freesync_module)
3667 mod_freesync_remove_stream(adev->dm.freesync_module, stream);
3669 acrtc->otg_inst = -1;
3670 acrtc->enabled = false;
3673 static int get_cursor_position(struct drm_plane *plane, struct drm_crtc *crtc,
3674 struct dc_cursor_position *position)
3676 struct amdgpu_crtc *amdgpu_crtc = amdgpu_crtc = to_amdgpu_crtc(crtc);
3678 int xorigin = 0, yorigin = 0;
3680 if (!crtc || !plane->state->fb) {
3681 position->enable = false;
3687 if ((plane->state->crtc_w > amdgpu_crtc->max_cursor_width) ||
3688 (plane->state->crtc_h > amdgpu_crtc->max_cursor_height)) {
3689 DRM_ERROR("%s: bad cursor width or height %d x %d\n",
3691 plane->state->crtc_w,
3692 plane->state->crtc_h);
3696 x = plane->state->crtc_x;
3697 y = plane->state->crtc_y;
3698 /* avivo cursor are offset into the total surface */
3699 x += crtc->primary->state->src_x >> 16;
3700 y += crtc->primary->state->src_y >> 16;
3702 xorigin = min(-x, amdgpu_crtc->max_cursor_width - 1);
3706 yorigin = min(-y, amdgpu_crtc->max_cursor_height - 1);
3709 position->enable = true;
3712 position->x_hotspot = xorigin;
3713 position->y_hotspot = yorigin;
3718 static void handle_cursor_update(struct drm_plane *plane,
3719 struct drm_plane_state *old_plane_state)
3721 struct amdgpu_framebuffer *afb = to_amdgpu_framebuffer(plane->state->fb);
3722 struct drm_crtc *crtc = afb ? plane->state->crtc : old_plane_state->crtc;
3723 struct dm_crtc_state *crtc_state = crtc ? to_dm_crtc_state(crtc->state) : NULL;
3724 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
3725 uint64_t address = afb ? afb->address : 0;
3726 struct dc_cursor_position position;
3727 struct dc_cursor_attributes attributes;
3730 if (!plane->state->fb && !old_plane_state->fb)
3733 DRM_DEBUG_DRIVER("%s: crtc_id=%d with size %d to %d\n",
3735 amdgpu_crtc->crtc_id,
3736 plane->state->crtc_w,
3737 plane->state->crtc_h);
3739 ret = get_cursor_position(plane, crtc, &position);
3743 if (!position.enable) {
3744 /* turn off cursor */
3745 if (crtc_state && crtc_state->stream)
3746 dc_stream_set_cursor_position(crtc_state->stream,
3751 amdgpu_crtc->cursor_width = plane->state->crtc_w;
3752 amdgpu_crtc->cursor_height = plane->state->crtc_h;
3754 attributes.address.high_part = upper_32_bits(address);
3755 attributes.address.low_part = lower_32_bits(address);
3756 attributes.width = plane->state->crtc_w;
3757 attributes.height = plane->state->crtc_h;
3758 attributes.color_format = CURSOR_MODE_COLOR_PRE_MULTIPLIED_ALPHA;
3759 attributes.rotation_angle = 0;
3760 attributes.attribute_flags.value = 0;
3762 attributes.pitch = attributes.width;
3764 if (crtc_state->stream) {
3765 if (!dc_stream_set_cursor_attributes(crtc_state->stream,
3767 DRM_ERROR("DC failed to set cursor attributes\n");
3769 if (!dc_stream_set_cursor_position(crtc_state->stream,
3771 DRM_ERROR("DC failed to set cursor position\n");
3775 static void prepare_flip_isr(struct amdgpu_crtc *acrtc)
3778 assert_spin_locked(&acrtc->base.dev->event_lock);
3779 WARN_ON(acrtc->event);
3781 acrtc->event = acrtc->base.state->event;
3783 /* Set the flip status */
3784 acrtc->pflip_status = AMDGPU_FLIP_SUBMITTED;
3786 /* Mark this event as consumed */
3787 acrtc->base.state->event = NULL;
3789 DRM_DEBUG_DRIVER("crtc:%d, pflip_stat:AMDGPU_FLIP_SUBMITTED\n",
3796 * Waits on all BO's fences and for proper vblank count
3798 static void amdgpu_dm_do_flip(struct drm_crtc *crtc,
3799 struct drm_framebuffer *fb,
3801 struct dc_state *state)
3803 unsigned long flags;
3804 uint32_t target_vblank;
3806 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
3807 struct amdgpu_framebuffer *afb = to_amdgpu_framebuffer(fb);
3808 struct amdgpu_bo *abo = gem_to_amdgpu_bo(afb->obj);
3809 struct amdgpu_device *adev = crtc->dev->dev_private;
3810 bool async_flip = (crtc->state->pageflip_flags & DRM_MODE_PAGE_FLIP_ASYNC) != 0;
3811 struct dc_flip_addrs addr = { {0} };
3812 /* TODO eliminate or rename surface_update */
3813 struct dc_surface_update surface_updates[1] = { {0} };
3814 struct dm_crtc_state *acrtc_state = to_dm_crtc_state(crtc->state);
3817 /* Prepare wait for target vblank early - before the fence-waits */
3818 target_vblank = target - drm_crtc_vblank_count(crtc) +
3819 amdgpu_get_vblank_counter_kms(crtc->dev, acrtc->crtc_id);
3821 /* TODO This might fail and hence better not used, wait
3822 * explicitly on fences instead
3823 * and in general should be called for
3824 * blocking commit to as per framework helpers
3826 r = amdgpu_bo_reserve(abo, true);
3827 if (unlikely(r != 0)) {
3828 DRM_ERROR("failed to reserve buffer before flip\n");
3832 /* Wait for all fences on this FB */
3833 WARN_ON(reservation_object_wait_timeout_rcu(abo->tbo.resv, true, false,
3834 MAX_SCHEDULE_TIMEOUT) < 0);
3836 amdgpu_bo_unreserve(abo);
3838 /* Wait until we're out of the vertical blank period before the one
3839 * targeted by the flip
3841 while ((acrtc->enabled &&
3842 (amdgpu_get_crtc_scanoutpos(adev->ddev, acrtc->crtc_id, 0,
3843 &vpos, &hpos, NULL, NULL,
3845 & (DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_IN_VBLANK)) ==
3846 (DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_IN_VBLANK) &&
3847 (int)(target_vblank -
3848 amdgpu_get_vblank_counter_kms(adev->ddev, acrtc->crtc_id)) > 0)) {
3849 usleep_range(1000, 1100);
3853 spin_lock_irqsave(&crtc->dev->event_lock, flags);
3854 /* update crtc fb */
3855 crtc->primary->fb = fb;
3857 WARN_ON(acrtc->pflip_status != AMDGPU_FLIP_NONE);
3858 WARN_ON(!acrtc_state->stream);
3860 addr.address.grph.addr.low_part = lower_32_bits(afb->address);
3861 addr.address.grph.addr.high_part = upper_32_bits(afb->address);
3862 addr.flip_immediate = async_flip;
3865 if (acrtc->base.state->event)
3866 prepare_flip_isr(acrtc);
3868 surface_updates->surface = dc_stream_get_status(acrtc_state->stream)->plane_states[0];
3869 surface_updates->flip_addr = &addr;
3872 dc_commit_updates_for_stream(adev->dm.dc,
3875 acrtc_state->stream,
3877 &surface_updates->surface,
3880 DRM_DEBUG_DRIVER("%s Flipping to hi: 0x%x, low: 0x%x \n",
3882 addr.address.grph.addr.high_part,
3883 addr.address.grph.addr.low_part);
3886 spin_unlock_irqrestore(&crtc->dev->event_lock, flags);
3889 static void amdgpu_dm_commit_planes(struct drm_atomic_state *state,
3890 struct drm_device *dev,
3891 struct amdgpu_display_manager *dm,
3892 struct drm_crtc *pcrtc,
3893 bool *wait_for_vblank)
3896 struct drm_plane *plane;
3897 struct drm_plane_state *old_plane_state, *new_plane_state;
3898 struct dc_stream_state *dc_stream_attach;
3899 struct dc_plane_state *plane_states_constructed[MAX_SURFACES];
3900 struct amdgpu_crtc *acrtc_attach = to_amdgpu_crtc(pcrtc);
3901 struct drm_crtc_state *new_pcrtc_state =
3902 drm_atomic_get_new_crtc_state(state, pcrtc);
3903 struct dm_crtc_state *acrtc_state = to_dm_crtc_state(new_pcrtc_state);
3904 struct dm_atomic_state *dm_state = to_dm_atomic_state(state);
3905 int planes_count = 0;
3906 unsigned long flags;
3908 /* update planes when needed */
3909 for_each_oldnew_plane_in_state(state, plane, old_plane_state, new_plane_state, i) {
3910 struct drm_crtc *crtc = new_plane_state->crtc;
3911 struct drm_crtc_state *new_crtc_state;
3912 struct drm_framebuffer *fb = new_plane_state->fb;
3914 struct dm_plane_state *dm_new_plane_state = to_dm_plane_state(new_plane_state);
3916 if (plane->type == DRM_PLANE_TYPE_CURSOR) {
3917 handle_cursor_update(plane, old_plane_state);
3921 if (!fb || !crtc || pcrtc != crtc)
3924 new_crtc_state = drm_atomic_get_new_crtc_state(state, crtc);
3925 if (!new_crtc_state->active)
3928 pflip_needed = !state->allow_modeset;
3930 spin_lock_irqsave(&crtc->dev->event_lock, flags);
3931 if (acrtc_attach->pflip_status != AMDGPU_FLIP_NONE) {
3932 DRM_ERROR("%s: acrtc %d, already busy\n",
3934 acrtc_attach->crtc_id);
3935 /* In commit tail framework this cannot happen */
3938 spin_unlock_irqrestore(&crtc->dev->event_lock, flags);
3940 if (!pflip_needed) {
3941 WARN_ON(!dm_new_plane_state->dc_state);
3943 plane_states_constructed[planes_count] = dm_new_plane_state->dc_state;
3945 dc_stream_attach = acrtc_state->stream;
3948 } else if (new_crtc_state->planes_changed) {
3949 /* Assume even ONE crtc with immediate flip means
3950 * entire can't wait for VBLANK
3951 * TODO Check if it's correct
3954 new_pcrtc_state->pageflip_flags & DRM_MODE_PAGE_FLIP_ASYNC ?
3957 /* TODO: Needs rework for multiplane flip */
3958 if (plane->type == DRM_PLANE_TYPE_PRIMARY)
3959 drm_crtc_vblank_get(crtc);
3964 drm_crtc_vblank_count(crtc) + *wait_for_vblank,
3971 unsigned long flags;
3973 if (new_pcrtc_state->event) {
3975 drm_crtc_vblank_get(pcrtc);
3977 spin_lock_irqsave(&pcrtc->dev->event_lock, flags);
3978 prepare_flip_isr(acrtc_attach);
3979 spin_unlock_irqrestore(&pcrtc->dev->event_lock, flags);
3982 if (false == dc_commit_planes_to_stream(dm->dc,
3983 plane_states_constructed,
3987 dm_error("%s: Failed to attach plane!\n", __func__);
3989 /*TODO BUG Here should go disable planes on CRTC. */
3994 static int amdgpu_dm_atomic_commit(struct drm_device *dev,
3995 struct drm_atomic_state *state,
3998 struct drm_crtc *crtc;
3999 struct drm_crtc_state *old_crtc_state, *new_crtc_state;
4000 struct amdgpu_device *adev = dev->dev_private;
4004 * We evade vblanks and pflips on crtc that
4005 * should be changed. We do it here to flush & disable
4006 * interrupts before drm_swap_state is called in drm_atomic_helper_commit
4007 * it will update crtc->dm_crtc_state->stream pointer which is used in
4010 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
4011 struct dm_crtc_state *dm_old_crtc_state = to_dm_crtc_state(old_crtc_state);
4012 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
4014 if (drm_atomic_crtc_needs_modeset(new_crtc_state) && dm_old_crtc_state->stream)
4015 manage_dm_interrupts(adev, acrtc, false);
4017 /* Add check here for SoC's that support hardware cursor plane, to
4018 * unset legacy_cursor_update */
4020 return drm_atomic_helper_commit(dev, state, nonblock);
4022 /*TODO Handle EINTR, reenable IRQ*/
4025 static void amdgpu_dm_atomic_commit_tail(struct drm_atomic_state *state)
4027 struct drm_device *dev = state->dev;
4028 struct amdgpu_device *adev = dev->dev_private;
4029 struct amdgpu_display_manager *dm = &adev->dm;
4030 struct dm_atomic_state *dm_state;
4032 uint32_t new_crtcs_count = 0;
4033 struct drm_crtc *crtc;
4034 struct drm_crtc_state *old_crtc_state, *new_crtc_state;
4035 struct amdgpu_crtc *new_crtcs[MAX_STREAMS];
4036 struct dc_stream_state *new_stream = NULL;
4037 unsigned long flags;
4038 bool wait_for_vblank = true;
4039 struct drm_connector *connector;
4040 struct drm_connector_state *old_con_state, *new_con_state;
4041 struct dm_crtc_state *dm_old_crtc_state, *dm_new_crtc_state;
4043 drm_atomic_helper_update_legacy_modeset_state(dev, state);
4045 dm_state = to_dm_atomic_state(state);
4047 /* update changed items */
4048 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
4049 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
4051 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
4052 dm_old_crtc_state = to_dm_crtc_state(old_crtc_state);
4055 "amdgpu_crtc id:%d crtc_state_flags: enable:%d, active:%d, "
4056 "planes_changed:%d, mode_changed:%d,active_changed:%d,"
4057 "connectors_changed:%d\n",
4059 new_crtc_state->enable,
4060 new_crtc_state->active,
4061 new_crtc_state->planes_changed,
4062 new_crtc_state->mode_changed,
4063 new_crtc_state->active_changed,
4064 new_crtc_state->connectors_changed);
4066 /* handles headless hotplug case, updating new_state and
4067 * aconnector as needed
4070 if (modeset_required(new_crtc_state, dm_new_crtc_state->stream, dm_old_crtc_state->stream)) {
4072 DRM_DEBUG_DRIVER("Atomic commit: SET crtc id %d: [%p]\n", acrtc->crtc_id, acrtc);
4074 if (!dm_new_crtc_state->stream) {
4076 * this could happen because of issues with
4077 * userspace notifications delivery.
4078 * In this case userspace tries to set mode on
4079 * display which is disconnect in fact.
4080 * dc_sink in NULL in this case on aconnector.
4081 * We expect reset mode will come soon.
4083 * This can also happen when unplug is done
4084 * during resume sequence ended
4086 * In this case, we want to pretend we still
4087 * have a sink to keep the pipe running so that
4088 * hw state is consistent with the sw state
4090 DRM_DEBUG_DRIVER("%s: Failed to create new stream for crtc %d\n",
4091 __func__, acrtc->base.base.id);
4096 if (dm_old_crtc_state->stream)
4097 remove_stream(adev, acrtc, dm_old_crtc_state->stream);
4101 * this loop saves set mode crtcs
4102 * we needed to enable vblanks once all
4103 * resources acquired in dc after dc_commit_streams
4106 /*TODO move all this into dm_crtc_state, get rid of
4107 * new_crtcs array and use old and new atomic states
4110 new_crtcs[new_crtcs_count] = acrtc;
4113 new_crtc_state = drm_atomic_get_new_crtc_state(state, crtc);
4114 acrtc->enabled = true;
4115 acrtc->hw_mode = new_crtc_state->mode;
4116 crtc->hwmode = new_crtc_state->mode;
4117 } else if (modereset_required(new_crtc_state)) {
4118 DRM_DEBUG_DRIVER("Atomic commit: RESET. crtc id %d:[%p]\n", acrtc->crtc_id, acrtc);
4120 /* i.e. reset mode */
4121 if (dm_old_crtc_state->stream)
4122 remove_stream(adev, acrtc, dm_old_crtc_state->stream);
4124 } /* for_each_crtc_in_state() */
4127 * Add streams after required streams from new and replaced streams
4128 * are removed from freesync module
4130 if (adev->dm.freesync_module) {
4131 for (i = 0; i < new_crtcs_count; i++) {
4132 struct amdgpu_dm_connector *aconnector = NULL;
4134 new_crtc_state = drm_atomic_get_new_crtc_state(state,
4135 &new_crtcs[i]->base);
4136 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
4138 new_stream = dm_new_crtc_state->stream;
4139 aconnector = amdgpu_dm_find_first_crtc_matching_connector(
4141 &new_crtcs[i]->base);
4143 DRM_DEBUG_DRIVER("Atomic commit: Failed to find connector for acrtc id:%d "
4144 "skipping freesync init\n",
4145 new_crtcs[i]->crtc_id);
4149 mod_freesync_add_stream(adev->dm.freesync_module,
4150 new_stream, &aconnector->caps);
4154 if (dm_state->context)
4155 WARN_ON(!dc_commit_state(dm->dc, dm_state->context));
4157 for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) {
4158 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
4160 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
4162 if (dm_new_crtc_state->stream != NULL) {
4163 const struct dc_stream_status *status =
4164 dc_stream_get_status(dm_new_crtc_state->stream);
4167 DC_ERR("got no status for stream %p on acrtc%p\n", dm_new_crtc_state->stream, acrtc);
4169 acrtc->otg_inst = status->primary_otg_inst;
4173 /* Handle scaling and underscan changes*/
4174 for_each_oldnew_connector_in_state(state, connector, old_con_state, new_con_state, i) {
4175 struct dm_connector_state *dm_new_con_state = to_dm_connector_state(new_con_state);
4176 struct dm_connector_state *dm_old_con_state = to_dm_connector_state(old_con_state);
4177 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(dm_new_con_state->base.crtc);
4178 struct dc_stream_status *status = NULL;
4181 new_crtc_state = drm_atomic_get_new_crtc_state(state, &acrtc->base);
4183 /* Skip any modesets/resets */
4184 if (!acrtc || drm_atomic_crtc_needs_modeset(new_crtc_state))
4187 /* Skip any thing not scale or underscan changes */
4188 if (!is_scaling_state_different(dm_new_con_state, dm_old_con_state))
4191 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
4193 update_stream_scaling_settings(&dm_new_con_state->base.crtc->mode,
4194 dm_new_con_state, (struct dc_stream_state *)dm_new_crtc_state->stream);
4196 status = dc_stream_get_status(dm_new_crtc_state->stream);
4198 WARN_ON(!status->plane_count);
4200 if (!dm_new_crtc_state->stream)
4203 /*TODO How it works with MPO ?*/
4204 if (!dc_commit_planes_to_stream(
4206 status->plane_states,
4207 status->plane_count,
4208 dm_new_crtc_state->stream,
4210 dm_error("%s: Failed to update stream scaling!\n", __func__);
4213 for (i = 0; i < new_crtcs_count; i++) {
4215 * loop to enable interrupts on newly arrived crtc
4217 struct amdgpu_crtc *acrtc = new_crtcs[i];
4219 new_crtc_state = drm_atomic_get_new_crtc_state(state, &acrtc->base);
4220 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
4222 if (adev->dm.freesync_module)
4223 mod_freesync_notify_mode_change(
4224 adev->dm.freesync_module, &dm_new_crtc_state->stream, 1);
4226 manage_dm_interrupts(adev, acrtc, true);
4229 /* update planes when needed per crtc*/
4230 for_each_new_crtc_in_state(state, crtc, new_crtc_state, j) {
4231 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
4233 if (dm_new_crtc_state->stream)
4234 amdgpu_dm_commit_planes(state, dev, dm, crtc, &wait_for_vblank);
4239 * send vblank event on all events not handled in flip and
4240 * mark consumed event for drm_atomic_helper_commit_hw_done
4242 spin_lock_irqsave(&adev->ddev->event_lock, flags);
4243 for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) {
4245 if (new_crtc_state->event)
4246 drm_send_event_locked(dev, &new_crtc_state->event->base);
4248 new_crtc_state->event = NULL;
4250 spin_unlock_irqrestore(&adev->ddev->event_lock, flags);
4252 /* Signal HW programming completion */
4253 drm_atomic_helper_commit_hw_done(state);
4255 if (wait_for_vblank)
4256 drm_atomic_helper_wait_for_vblanks(dev, state);
4258 drm_atomic_helper_cleanup_planes(dev, state);
4262 static int dm_force_atomic_commit(struct drm_connector *connector)
4265 struct drm_device *ddev = connector->dev;
4266 struct drm_atomic_state *state = drm_atomic_state_alloc(ddev);
4267 struct amdgpu_crtc *disconnected_acrtc = to_amdgpu_crtc(connector->encoder->crtc);
4268 struct drm_plane *plane = disconnected_acrtc->base.primary;
4269 struct drm_connector_state *conn_state;
4270 struct drm_crtc_state *crtc_state;
4271 struct drm_plane_state *plane_state;
4276 state->acquire_ctx = ddev->mode_config.acquire_ctx;
4278 /* Construct an atomic state to restore previous display setting */
4281 * Attach connectors to drm_atomic_state
4283 conn_state = drm_atomic_get_connector_state(state, connector);
4285 ret = PTR_ERR_OR_ZERO(conn_state);
4289 /* Attach crtc to drm_atomic_state*/
4290 crtc_state = drm_atomic_get_crtc_state(state, &disconnected_acrtc->base);
4292 ret = PTR_ERR_OR_ZERO(crtc_state);
4296 /* force a restore */
4297 crtc_state->mode_changed = true;
4299 /* Attach plane to drm_atomic_state */
4300 plane_state = drm_atomic_get_plane_state(state, plane);
4302 ret = PTR_ERR_OR_ZERO(plane_state);
4307 /* Call commit internally with the state we just constructed */
4308 ret = drm_atomic_commit(state);
4313 DRM_ERROR("Restoring old state failed with %i\n", ret);
4314 drm_atomic_state_put(state);
4320 * This functions handle all cases when set mode does not come upon hotplug.
4321 * This include when the same display is unplugged then plugged back into the
4322 * same port and when we are running without usermode desktop manager supprot
4324 void dm_restore_drm_connector_state(struct drm_device *dev,
4325 struct drm_connector *connector)
4327 struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
4328 struct amdgpu_crtc *disconnected_acrtc;
4329 struct dm_crtc_state *acrtc_state;
4331 if (!aconnector->dc_sink || !connector->state || !connector->encoder)
4334 disconnected_acrtc = to_amdgpu_crtc(connector->encoder->crtc);
4335 acrtc_state = to_dm_crtc_state(disconnected_acrtc->base.state);
4337 if (!disconnected_acrtc || !acrtc_state->stream)
4341 * If the previous sink is not released and different from the current,
4342 * we deduce we are in a state where we can not rely on usermode call
4343 * to turn on the display, so we do it here
4345 if (acrtc_state->stream->sink != aconnector->dc_sink)
4346 dm_force_atomic_commit(&aconnector->base);
4350 * Grabs all modesetting locks to serialize against any blocking commits,
4351 * Waits for completion of all non blocking commits.
4353 static int do_aquire_global_lock(struct drm_device *dev,
4354 struct drm_atomic_state *state)
4356 struct drm_crtc *crtc;
4357 struct drm_crtc_commit *commit;
4360 /* Adding all modeset locks to aquire_ctx will
4361 * ensure that when the framework release it the
4362 * extra locks we are locking here will get released to
4364 ret = drm_modeset_lock_all_ctx(dev, state->acquire_ctx);
4368 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
4369 spin_lock(&crtc->commit_lock);
4370 commit = list_first_entry_or_null(&crtc->commit_list,
4371 struct drm_crtc_commit, commit_entry);
4373 drm_crtc_commit_get(commit);
4374 spin_unlock(&crtc->commit_lock);
4379 /* Make sure all pending HW programming completed and
4382 ret = wait_for_completion_interruptible_timeout(&commit->hw_done, 10*HZ);
4385 ret = wait_for_completion_interruptible_timeout(
4386 &commit->flip_done, 10*HZ);
4389 DRM_ERROR("[CRTC:%d:%s] hw_done or flip_done "
4390 "timed out\n", crtc->base.id, crtc->name);
4392 drm_crtc_commit_put(commit);
4395 return ret < 0 ? ret : 0;
4398 static int dm_update_crtcs_state(struct dc *dc,
4399 struct drm_atomic_state *state,
4401 bool *lock_and_validation_needed)
4403 struct drm_crtc *crtc;
4404 struct drm_crtc_state *old_crtc_state, *new_crtc_state;
4406 struct dm_crtc_state *dm_old_crtc_state, *dm_new_crtc_state;
4407 struct dm_atomic_state *dm_state = to_dm_atomic_state(state);
4408 struct dc_stream_state *new_stream;
4411 /*TODO Move this code into dm_crtc_atomic_check once we get rid of dc_validation_set */
4412 /* update changed items */
4413 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
4414 struct amdgpu_crtc *acrtc = NULL;
4415 struct amdgpu_dm_connector *aconnector = NULL;
4416 struct drm_connector_state *new_con_state = NULL;
4417 struct dm_connector_state *dm_conn_state = NULL;
4421 dm_old_crtc_state = to_dm_crtc_state(old_crtc_state);
4422 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
4423 acrtc = to_amdgpu_crtc(crtc);
4425 aconnector = amdgpu_dm_find_first_crtc_matching_connector(state, crtc);
4427 /* TODO This hack should go away */
4428 if (aconnector && enable) {
4429 // Make sure fake sink is created in plug-in scenario
4430 new_con_state = drm_atomic_get_connector_state(state,
4433 if (IS_ERR(new_con_state)) {
4434 ret = PTR_ERR_OR_ZERO(new_con_state);
4438 dm_conn_state = to_dm_connector_state(new_con_state);
4440 new_stream = create_stream_for_sink(aconnector,
4441 &new_crtc_state->mode,
4445 * we can have no stream on ACTION_SET if a display
4446 * was disconnected during S3, in this case it not and
4447 * error, the OS will be updated after detection, and
4448 * do the right thing on next atomic commit
4452 DRM_DEBUG_DRIVER("%s: Failed to create new stream for crtc %d\n",
4453 __func__, acrtc->base.base.id);
4458 if (dc_is_stream_unchanged(new_stream, dm_old_crtc_state->stream) &&
4459 dc_is_stream_scaling_unchanged(new_stream, dm_old_crtc_state->stream)) {
4461 new_crtc_state->mode_changed = false;
4463 DRM_DEBUG_DRIVER("Mode change not required, setting mode_changed to %d",
4464 new_crtc_state->mode_changed);
4468 if (!drm_atomic_crtc_needs_modeset(new_crtc_state))
4472 "amdgpu_crtc id:%d crtc_state_flags: enable:%d, active:%d, "
4473 "planes_changed:%d, mode_changed:%d,active_changed:%d,"
4474 "connectors_changed:%d\n",
4476 new_crtc_state->enable,
4477 new_crtc_state->active,
4478 new_crtc_state->planes_changed,
4479 new_crtc_state->mode_changed,
4480 new_crtc_state->active_changed,
4481 new_crtc_state->connectors_changed);
4483 /* Remove stream for any changed/disabled CRTC */
4486 if (!dm_old_crtc_state->stream)
4489 DRM_DEBUG_DRIVER("Disabling DRM crtc: %d\n",
4492 /* i.e. reset mode */
4493 if (dc_remove_stream_from_ctx(
4496 dm_old_crtc_state->stream) != DC_OK) {
4501 dc_stream_release(dm_old_crtc_state->stream);
4502 dm_new_crtc_state->stream = NULL;
4504 *lock_and_validation_needed = true;
4506 } else {/* Add stream for any updated/enabled CRTC */
4508 * Quick fix to prevent NULL pointer on new_stream when
4509 * added MST connectors not found in existing crtc_state in the chained mode
4510 * TODO: need to dig out the root cause of that
4512 if (!aconnector || (!aconnector->dc_sink && aconnector->mst_port))
4515 if (modereset_required(new_crtc_state))
4518 if (modeset_required(new_crtc_state, new_stream,
4519 dm_old_crtc_state->stream)) {
4521 WARN_ON(dm_new_crtc_state->stream);
4523 dm_new_crtc_state->stream = new_stream;
4524 dc_stream_retain(new_stream);
4526 DRM_DEBUG_DRIVER("Enabling DRM crtc: %d\n",
4529 if (dc_add_stream_to_ctx(
4532 dm_new_crtc_state->stream) != DC_OK) {
4537 *lock_and_validation_needed = true;
4542 /* Release extra reference */
4544 dc_stream_release(new_stream);
4551 dc_stream_release(new_stream);
4555 static int dm_update_planes_state(struct dc *dc,
4556 struct drm_atomic_state *state,
4558 bool *lock_and_validation_needed)
4560 struct drm_crtc *new_plane_crtc, *old_plane_crtc;
4561 struct drm_crtc_state *old_crtc_state, *new_crtc_state;
4562 struct drm_plane *plane;
4563 struct drm_plane_state *old_plane_state, *new_plane_state;
4564 struct dm_crtc_state *dm_new_crtc_state, *dm_old_crtc_state;
4565 struct dm_atomic_state *dm_state = to_dm_atomic_state(state);
4566 struct dm_plane_state *dm_new_plane_state, *dm_old_plane_state;
4568 /* TODO return page_flip_needed() function */
4569 bool pflip_needed = !state->allow_modeset;
4575 /* Add new planes */
4576 for_each_oldnew_plane_in_state(state, plane, old_plane_state, new_plane_state, i) {
4577 new_plane_crtc = new_plane_state->crtc;
4578 old_plane_crtc = old_plane_state->crtc;
4579 dm_new_plane_state = to_dm_plane_state(new_plane_state);
4580 dm_old_plane_state = to_dm_plane_state(old_plane_state);
4582 /*TODO Implement atomic check for cursor plane */
4583 if (plane->type == DRM_PLANE_TYPE_CURSOR)
4586 /* Remove any changed/removed planes */
4589 if (!old_plane_crtc)
4592 old_crtc_state = drm_atomic_get_old_crtc_state(
4593 state, old_plane_crtc);
4594 dm_old_crtc_state = to_dm_crtc_state(old_crtc_state);
4596 if (!dm_old_crtc_state->stream)
4599 DRM_DEBUG_DRIVER("Disabling DRM plane: %d on DRM crtc %d\n",
4600 plane->base.id, old_plane_crtc->base.id);
4602 if (!dc_remove_plane_from_context(
4604 dm_old_crtc_state->stream,
4605 dm_old_plane_state->dc_state,
4606 dm_state->context)) {
4613 dc_plane_state_release(dm_old_plane_state->dc_state);
4614 dm_new_plane_state->dc_state = NULL;
4616 *lock_and_validation_needed = true;
4618 } else { /* Add new planes */
4620 if (drm_atomic_plane_disabling(plane->state, new_plane_state))
4623 if (!new_plane_crtc)
4626 new_crtc_state = drm_atomic_get_new_crtc_state(state, new_plane_crtc);
4627 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
4629 if (!dm_new_crtc_state->stream)
4633 WARN_ON(dm_new_plane_state->dc_state);
4635 dm_new_plane_state->dc_state = dc_create_plane_state(dc);
4637 DRM_DEBUG_DRIVER("Enabling DRM plane: %d on DRM crtc %d\n",
4638 plane->base.id, new_plane_crtc->base.id);
4640 if (!dm_new_plane_state->dc_state) {
4645 ret = fill_plane_attributes(
4646 new_plane_crtc->dev->dev_private,
4647 dm_new_plane_state->dc_state,
4655 if (!dc_add_plane_to_context(
4657 dm_new_crtc_state->stream,
4658 dm_new_plane_state->dc_state,
4659 dm_state->context)) {
4665 *lock_and_validation_needed = true;
4673 static int amdgpu_dm_atomic_check(struct drm_device *dev,
4674 struct drm_atomic_state *state)
4678 struct amdgpu_device *adev = dev->dev_private;
4679 struct dc *dc = adev->dm.dc;
4680 struct dm_atomic_state *dm_state = to_dm_atomic_state(state);
4681 struct drm_connector *connector;
4682 struct drm_connector_state *old_con_state, *new_con_state;
4683 struct drm_crtc *crtc;
4684 struct drm_crtc_state *old_crtc_state, *new_crtc_state;
4687 * This bool will be set for true for any modeset/reset
4688 * or plane update which implies non fast surface update.
4690 bool lock_and_validation_needed = false;
4692 ret = drm_atomic_helper_check_modeset(dev, state);
4697 * legacy_cursor_update should be made false for SoC's having
4698 * a dedicated hardware plane for cursor in amdgpu_dm_atomic_commit(),
4699 * otherwise for software cursor plane,
4700 * we should not add it to list of affected planes.
4702 if (state->legacy_cursor_update) {
4703 for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) {
4704 if (new_crtc_state->color_mgmt_changed) {
4705 ret = drm_atomic_add_affected_planes(state, crtc);
4711 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
4712 if (!drm_atomic_crtc_needs_modeset(new_crtc_state))
4715 if (!new_crtc_state->enable)
4718 ret = drm_atomic_add_affected_connectors(state, crtc);
4722 ret = drm_atomic_add_affected_planes(state, crtc);
4728 dm_state->context = dc_create_state();
4729 ASSERT(dm_state->context);
4730 dc_resource_state_copy_construct_current(dc, dm_state->context);
4732 /* Remove exiting planes if they are modified */
4733 ret = dm_update_planes_state(dc, state, false, &lock_and_validation_needed);
4738 /* Disable all crtcs which require disable */
4739 ret = dm_update_crtcs_state(dc, state, false, &lock_and_validation_needed);
4744 /* Enable all crtcs which require enable */
4745 ret = dm_update_crtcs_state(dc, state, true, &lock_and_validation_needed);
4750 /* Add new/modified planes */
4751 ret = dm_update_planes_state(dc, state, true, &lock_and_validation_needed);
4756 /* Run this here since we want to validate the streams we created */
4757 ret = drm_atomic_helper_check_planes(dev, state);
4761 /* Check scaling and underscan changes*/
4762 /*TODO Removed scaling changes validation due to inability to commit
4763 * new stream into context w\o causing full reset. Need to
4764 * decide how to handle.
4766 for_each_oldnew_connector_in_state(state, connector, old_con_state, new_con_state, i) {
4767 struct dm_connector_state *dm_old_con_state = to_dm_connector_state(old_con_state);
4768 struct dm_connector_state *dm_new_con_state = to_dm_connector_state(new_con_state);
4769 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(dm_new_con_state->base.crtc);
4771 /* Skip any modesets/resets */
4772 if (!acrtc || drm_atomic_crtc_needs_modeset(
4773 drm_atomic_get_new_crtc_state(state, &acrtc->base)))
4776 /* Skip any thing not scale or underscan changes */
4777 if (!is_scaling_state_different(dm_new_con_state, dm_old_con_state))
4780 lock_and_validation_needed = true;
4784 * For full updates case when
4785 * removing/adding/updating streams on once CRTC while flipping
4787 * acquiring global lock will guarantee that any such full
4789 * will wait for completion of any outstanding flip using DRMs
4790 * synchronization events.
4793 if (lock_and_validation_needed) {
4795 ret = do_aquire_global_lock(dev, state);
4799 if (dc_validate_global_state(dc, dm_state->context) != DC_OK) {
4805 /* Must be success */
4810 if (ret == -EDEADLK)
4811 DRM_DEBUG_DRIVER("Atomic check stopped to avoid deadlock.\n");
4812 else if (ret == -EINTR || ret == -EAGAIN || ret == -ERESTARTSYS)
4813 DRM_DEBUG_DRIVER("Atomic check stopped due to signal.\n");
4815 DRM_DEBUG_DRIVER("Atomic check failed with err: %d \n", ret);
4820 static bool is_dp_capable_without_timing_msa(struct dc *dc,
4821 struct amdgpu_dm_connector *amdgpu_dm_connector)
4824 bool capable = false;
4826 if (amdgpu_dm_connector->dc_link &&
4827 dm_helpers_dp_read_dpcd(
4829 amdgpu_dm_connector->dc_link,
4830 DP_DOWN_STREAM_PORT_COUNT,
4832 sizeof(dpcd_data))) {
4833 capable = (dpcd_data & DP_MSA_TIMING_PAR_IGNORED) ? true:false;
4838 void amdgpu_dm_add_sink_to_freesync_module(struct drm_connector *connector,
4842 uint64_t val_capable;
4843 bool edid_check_required;
4844 struct detailed_timing *timing;
4845 struct detailed_non_pixel *data;
4846 struct detailed_data_monitor_range *range;
4847 struct amdgpu_dm_connector *amdgpu_dm_connector =
4848 to_amdgpu_dm_connector(connector);
4850 struct drm_device *dev = connector->dev;
4851 struct amdgpu_device *adev = dev->dev_private;
4853 edid_check_required = false;
4854 if (!amdgpu_dm_connector->dc_sink) {
4855 DRM_ERROR("dc_sink NULL, could not add free_sync module.\n");
4858 if (!adev->dm.freesync_module)
4861 * if edid non zero restrict freesync only for dp and edp
4864 if (amdgpu_dm_connector->dc_sink->sink_signal == SIGNAL_TYPE_DISPLAY_PORT
4865 || amdgpu_dm_connector->dc_sink->sink_signal == SIGNAL_TYPE_EDP) {
4866 edid_check_required = is_dp_capable_without_timing_msa(
4868 amdgpu_dm_connector);
4872 if (edid_check_required == true && (edid->version > 1 ||
4873 (edid->version == 1 && edid->revision > 1))) {
4874 for (i = 0; i < 4; i++) {
4876 timing = &edid->detailed_timings[i];
4877 data = &timing->data.other_data;
4878 range = &data->data.range;
4880 * Check if monitor has continuous frequency mode
4882 if (data->type != EDID_DETAIL_MONITOR_RANGE)
4885 * Check for flag range limits only. If flag == 1 then
4886 * no additional timing information provided.
4887 * Default GTF, GTF Secondary curve and CVT are not
4890 if (range->flags != 1)
4893 amdgpu_dm_connector->min_vfreq = range->min_vfreq;
4894 amdgpu_dm_connector->max_vfreq = range->max_vfreq;
4895 amdgpu_dm_connector->pixel_clock_mhz =
4896 range->pixel_clock_mhz * 10;
4900 if (amdgpu_dm_connector->max_vfreq -
4901 amdgpu_dm_connector->min_vfreq > 10) {
4902 amdgpu_dm_connector->caps.supported = true;
4903 amdgpu_dm_connector->caps.min_refresh_in_micro_hz =
4904 amdgpu_dm_connector->min_vfreq * 1000000;
4905 amdgpu_dm_connector->caps.max_refresh_in_micro_hz =
4906 amdgpu_dm_connector->max_vfreq * 1000000;
4912 * TODO figure out how to notify user-mode or DRM of freesync caps
4913 * once we figure out how to deal with freesync in an upstreamable
4919 void amdgpu_dm_remove_sink_from_freesync_module(struct drm_connector *connector)
4922 * TODO fill in once we figure out how to deal with freesync in
4923 * an upstreamable fashion