2 * Copyright 2015 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
26 /* The caprices of the preprocessor require that this be declared right here */
27 #define CREATE_TRACE_POINTS
29 #include "dm_services_types.h"
31 #include "dc/inc/core_types.h"
32 #include "dal_asic_id.h"
33 #include "dmub/inc/dmub_srv.h"
34 #include "dc/inc/hw/dmcu.h"
35 #include "dc/inc/hw/abm.h"
36 #include "dc/dc_dmub_srv.h"
40 #include "amdgpu_display.h"
41 #include "amdgpu_ucode.h"
43 #include "amdgpu_dm.h"
44 #ifdef CONFIG_DRM_AMD_DC_HDCP
45 #include "amdgpu_dm_hdcp.h"
46 #include <drm/drm_hdcp.h>
48 #include "amdgpu_pm.h"
50 #include "amd_shared.h"
51 #include "amdgpu_dm_irq.h"
52 #include "dm_helpers.h"
53 #include "amdgpu_dm_mst_types.h"
54 #if defined(CONFIG_DEBUG_FS)
55 #include "amdgpu_dm_debugfs.h"
58 #include "ivsrcid/ivsrcid_vislands30.h"
60 #include <linux/module.h>
61 #include <linux/moduleparam.h>
62 #include <linux/version.h>
63 #include <linux/types.h>
64 #include <linux/pm_runtime.h>
65 #include <linux/pci.h>
66 #include <linux/firmware.h>
67 #include <linux/component.h>
69 #include <drm/drm_atomic.h>
70 #include <drm/drm_atomic_uapi.h>
71 #include <drm/drm_atomic_helper.h>
72 #include <drm/drm_dp_mst_helper.h>
73 #include <drm/drm_fb_helper.h>
74 #include <drm/drm_fourcc.h>
75 #include <drm/drm_edid.h>
76 #include <drm/drm_vblank.h>
77 #include <drm/drm_audio_component.h>
78 #include <drm/drm_hdcp.h>
80 #if defined(CONFIG_DRM_AMD_DC_DCN)
81 #include "ivsrcid/dcn/irqsrcs_dcn_1_0.h"
83 #include "dcn/dcn_1_0_offset.h"
84 #include "dcn/dcn_1_0_sh_mask.h"
85 #include "soc15_hw_ip.h"
86 #include "vega10_ip_offset.h"
88 #include "soc15_common.h"
91 #include "modules/inc/mod_freesync.h"
92 #include "modules/power/power_helpers.h"
93 #include "modules/inc/mod_info_packet.h"
95 #define FIRMWARE_RENOIR_DMUB "amdgpu/renoir_dmcub.bin"
96 MODULE_FIRMWARE(FIRMWARE_RENOIR_DMUB);
98 #define FIRMWARE_RAVEN_DMCU "amdgpu/raven_dmcu.bin"
99 MODULE_FIRMWARE(FIRMWARE_RAVEN_DMCU);
101 /* Number of bytes in PSP header for firmware. */
102 #define PSP_HEADER_BYTES 0x100
104 /* Number of bytes in PSP footer for firmware. */
105 #define PSP_FOOTER_BYTES 0x100
110 * The AMDgpu display manager, **amdgpu_dm** (or even simpler,
111 * **dm**) sits between DRM and DC. It acts as a liason, converting DRM
112 * requests into DC requests, and DC responses into DRM responses.
114 * The root control structure is &struct amdgpu_display_manager.
117 /* basic init/fini API */
118 static int amdgpu_dm_init(struct amdgpu_device *adev);
119 static void amdgpu_dm_fini(struct amdgpu_device *adev);
122 * initializes drm_device display related structures, based on the information
123 * provided by DAL. The drm strcutures are: drm_crtc, drm_connector,
124 * drm_encoder, drm_mode_config
126 * Returns 0 on success
128 static int amdgpu_dm_initialize_drm_device(struct amdgpu_device *adev);
129 /* removes and deallocates the drm structures, created by the above function */
130 static void amdgpu_dm_destroy_drm_device(struct amdgpu_display_manager *dm);
133 amdgpu_dm_update_connector_after_detect(struct amdgpu_dm_connector *aconnector);
135 static int amdgpu_dm_plane_init(struct amdgpu_display_manager *dm,
136 struct drm_plane *plane,
137 unsigned long possible_crtcs,
138 const struct dc_plane_cap *plane_cap);
139 static int amdgpu_dm_crtc_init(struct amdgpu_display_manager *dm,
140 struct drm_plane *plane,
141 uint32_t link_index);
142 static int amdgpu_dm_connector_init(struct amdgpu_display_manager *dm,
143 struct amdgpu_dm_connector *amdgpu_dm_connector,
145 struct amdgpu_encoder *amdgpu_encoder);
146 static int amdgpu_dm_encoder_init(struct drm_device *dev,
147 struct amdgpu_encoder *aencoder,
148 uint32_t link_index);
150 static int amdgpu_dm_connector_get_modes(struct drm_connector *connector);
152 static int amdgpu_dm_atomic_commit(struct drm_device *dev,
153 struct drm_atomic_state *state,
156 static void amdgpu_dm_atomic_commit_tail(struct drm_atomic_state *state);
158 static int amdgpu_dm_atomic_check(struct drm_device *dev,
159 struct drm_atomic_state *state);
161 static void handle_cursor_update(struct drm_plane *plane,
162 struct drm_plane_state *old_plane_state);
164 static void amdgpu_dm_set_psr_caps(struct dc_link *link);
165 static bool amdgpu_dm_psr_enable(struct dc_stream_state *stream);
166 static bool amdgpu_dm_link_setup_psr(struct dc_stream_state *stream);
167 static bool amdgpu_dm_psr_disable(struct dc_stream_state *stream);
171 * dm_vblank_get_counter
174 * Get counter for number of vertical blanks
177 * struct amdgpu_device *adev - [in] desired amdgpu device
178 * int disp_idx - [in] which CRTC to get the counter from
181 * Counter for vertical blanks
183 static u32 dm_vblank_get_counter(struct amdgpu_device *adev, int crtc)
185 if (crtc >= adev->mode_info.num_crtc)
188 struct amdgpu_crtc *acrtc = adev->mode_info.crtcs[crtc];
189 struct dm_crtc_state *acrtc_state = to_dm_crtc_state(
193 if (acrtc_state->stream == NULL) {
194 DRM_ERROR("dc_stream_state is NULL for crtc '%d'!\n",
199 return dc_stream_get_vblank_counter(acrtc_state->stream);
203 static int dm_crtc_get_scanoutpos(struct amdgpu_device *adev, int crtc,
204 u32 *vbl, u32 *position)
206 uint32_t v_blank_start, v_blank_end, h_position, v_position;
208 if ((crtc < 0) || (crtc >= adev->mode_info.num_crtc))
211 struct amdgpu_crtc *acrtc = adev->mode_info.crtcs[crtc];
212 struct dm_crtc_state *acrtc_state = to_dm_crtc_state(
215 if (acrtc_state->stream == NULL) {
216 DRM_ERROR("dc_stream_state is NULL for crtc '%d'!\n",
222 * TODO rework base driver to use values directly.
223 * for now parse it back into reg-format
225 dc_stream_get_scanoutpos(acrtc_state->stream,
231 *position = v_position | (h_position << 16);
232 *vbl = v_blank_start | (v_blank_end << 16);
238 static bool dm_is_idle(void *handle)
244 static int dm_wait_for_idle(void *handle)
250 static bool dm_check_soft_reset(void *handle)
255 static int dm_soft_reset(void *handle)
261 static struct amdgpu_crtc *
262 get_crtc_by_otg_inst(struct amdgpu_device *adev,
265 struct drm_device *dev = adev->ddev;
266 struct drm_crtc *crtc;
267 struct amdgpu_crtc *amdgpu_crtc;
269 if (otg_inst == -1) {
271 return adev->mode_info.crtcs[0];
274 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
275 amdgpu_crtc = to_amdgpu_crtc(crtc);
277 if (amdgpu_crtc->otg_inst == otg_inst)
284 static inline bool amdgpu_dm_vrr_active(struct dm_crtc_state *dm_state)
286 return dm_state->freesync_config.state == VRR_STATE_ACTIVE_VARIABLE ||
287 dm_state->freesync_config.state == VRR_STATE_ACTIVE_FIXED;
291 * dm_pflip_high_irq() - Handle pageflip interrupt
292 * @interrupt_params: ignored
294 * Handles the pageflip interrupt by notifying all interested parties
295 * that the pageflip has been completed.
297 static void dm_pflip_high_irq(void *interrupt_params)
299 struct amdgpu_crtc *amdgpu_crtc;
300 struct common_irq_params *irq_params = interrupt_params;
301 struct amdgpu_device *adev = irq_params->adev;
303 struct drm_pending_vblank_event *e;
304 struct dm_crtc_state *acrtc_state;
305 uint32_t vpos, hpos, v_blank_start, v_blank_end;
308 amdgpu_crtc = get_crtc_by_otg_inst(adev, irq_params->irq_src - IRQ_TYPE_PFLIP);
310 /* IRQ could occur when in initial stage */
311 /* TODO work and BO cleanup */
312 if (amdgpu_crtc == NULL) {
313 DRM_DEBUG_DRIVER("CRTC is null, returning.\n");
317 spin_lock_irqsave(&adev->ddev->event_lock, flags);
319 if (amdgpu_crtc->pflip_status != AMDGPU_FLIP_SUBMITTED){
320 DRM_DEBUG_DRIVER("amdgpu_crtc->pflip_status = %d !=AMDGPU_FLIP_SUBMITTED(%d) on crtc:%d[%p] \n",
321 amdgpu_crtc->pflip_status,
322 AMDGPU_FLIP_SUBMITTED,
323 amdgpu_crtc->crtc_id,
325 spin_unlock_irqrestore(&adev->ddev->event_lock, flags);
329 /* page flip completed. */
330 e = amdgpu_crtc->event;
331 amdgpu_crtc->event = NULL;
336 acrtc_state = to_dm_crtc_state(amdgpu_crtc->base.state);
337 vrr_active = amdgpu_dm_vrr_active(acrtc_state);
339 /* Fixed refresh rate, or VRR scanout position outside front-porch? */
341 !dc_stream_get_scanoutpos(acrtc_state->stream, &v_blank_start,
342 &v_blank_end, &hpos, &vpos) ||
343 (vpos < v_blank_start)) {
344 /* Update to correct count and vblank timestamp if racing with
345 * vblank irq. This also updates to the correct vblank timestamp
346 * even in VRR mode, as scanout is past the front-porch atm.
348 drm_crtc_accurate_vblank_count(&amdgpu_crtc->base);
350 /* Wake up userspace by sending the pageflip event with proper
351 * count and timestamp of vblank of flip completion.
354 drm_crtc_send_vblank_event(&amdgpu_crtc->base, e);
356 /* Event sent, so done with vblank for this flip */
357 drm_crtc_vblank_put(&amdgpu_crtc->base);
360 /* VRR active and inside front-porch: vblank count and
361 * timestamp for pageflip event will only be up to date after
362 * drm_crtc_handle_vblank() has been executed from late vblank
363 * irq handler after start of back-porch (vline 0). We queue the
364 * pageflip event for send-out by drm_crtc_handle_vblank() with
365 * updated timestamp and count, once it runs after us.
367 * We need to open-code this instead of using the helper
368 * drm_crtc_arm_vblank_event(), as that helper would
369 * call drm_crtc_accurate_vblank_count(), which we must
370 * not call in VRR mode while we are in front-porch!
373 /* sequence will be replaced by real count during send-out. */
374 e->sequence = drm_crtc_vblank_count(&amdgpu_crtc->base);
375 e->pipe = amdgpu_crtc->crtc_id;
377 list_add_tail(&e->base.link, &adev->ddev->vblank_event_list);
381 /* Keep track of vblank of this flip for flip throttling. We use the
382 * cooked hw counter, as that one incremented at start of this vblank
383 * of pageflip completion, so last_flip_vblank is the forbidden count
384 * for queueing new pageflips if vsync + VRR is enabled.
386 amdgpu_crtc->last_flip_vblank = amdgpu_get_vblank_counter_kms(adev->ddev,
387 amdgpu_crtc->crtc_id);
389 amdgpu_crtc->pflip_status = AMDGPU_FLIP_NONE;
390 spin_unlock_irqrestore(&adev->ddev->event_lock, flags);
392 DRM_DEBUG_DRIVER("crtc:%d[%p], pflip_stat:AMDGPU_FLIP_NONE, vrr[%d]-fp %d\n",
393 amdgpu_crtc->crtc_id, amdgpu_crtc,
394 vrr_active, (int) !e);
397 static void dm_vupdate_high_irq(void *interrupt_params)
399 struct common_irq_params *irq_params = interrupt_params;
400 struct amdgpu_device *adev = irq_params->adev;
401 struct amdgpu_crtc *acrtc;
402 struct dm_crtc_state *acrtc_state;
405 acrtc = get_crtc_by_otg_inst(adev, irq_params->irq_src - IRQ_TYPE_VUPDATE);
408 acrtc_state = to_dm_crtc_state(acrtc->base.state);
410 DRM_DEBUG_DRIVER("crtc:%d, vupdate-vrr:%d\n", acrtc->crtc_id,
411 amdgpu_dm_vrr_active(acrtc_state));
413 /* Core vblank handling is done here after end of front-porch in
414 * vrr mode, as vblank timestamping will give valid results
415 * while now done after front-porch. This will also deliver
416 * page-flip completion events that have been queued to us
417 * if a pageflip happened inside front-porch.
419 if (amdgpu_dm_vrr_active(acrtc_state)) {
420 drm_crtc_handle_vblank(&acrtc->base);
422 /* BTR processing for pre-DCE12 ASICs */
423 if (acrtc_state->stream &&
424 adev->family < AMDGPU_FAMILY_AI) {
425 spin_lock_irqsave(&adev->ddev->event_lock, flags);
426 mod_freesync_handle_v_update(
427 adev->dm.freesync_module,
429 &acrtc_state->vrr_params);
431 dc_stream_adjust_vmin_vmax(
434 &acrtc_state->vrr_params.adjust);
435 spin_unlock_irqrestore(&adev->ddev->event_lock, flags);
442 * dm_crtc_high_irq() - Handles CRTC interrupt
443 * @interrupt_params: ignored
445 * Handles the CRTC/VSYNC interrupt by notfying DRM's VBLANK
448 static void dm_crtc_high_irq(void *interrupt_params)
450 struct common_irq_params *irq_params = interrupt_params;
451 struct amdgpu_device *adev = irq_params->adev;
452 struct amdgpu_crtc *acrtc;
453 struct dm_crtc_state *acrtc_state;
456 acrtc = get_crtc_by_otg_inst(adev, irq_params->irq_src - IRQ_TYPE_VBLANK);
459 acrtc_state = to_dm_crtc_state(acrtc->base.state);
461 DRM_DEBUG_DRIVER("crtc:%d, vupdate-vrr:%d\n", acrtc->crtc_id,
462 amdgpu_dm_vrr_active(acrtc_state));
464 /* Core vblank handling at start of front-porch is only possible
465 * in non-vrr mode, as only there vblank timestamping will give
466 * valid results while done in front-porch. Otherwise defer it
467 * to dm_vupdate_high_irq after end of front-porch.
469 if (!amdgpu_dm_vrr_active(acrtc_state))
470 drm_crtc_handle_vblank(&acrtc->base);
472 /* Following stuff must happen at start of vblank, for crc
473 * computation and below-the-range btr support in vrr mode.
475 amdgpu_dm_crtc_handle_crc_irq(&acrtc->base);
477 if (acrtc_state->stream && adev->family >= AMDGPU_FAMILY_AI &&
478 acrtc_state->vrr_params.supported &&
479 acrtc_state->freesync_config.state == VRR_STATE_ACTIVE_VARIABLE) {
480 spin_lock_irqsave(&adev->ddev->event_lock, flags);
481 mod_freesync_handle_v_update(
482 adev->dm.freesync_module,
484 &acrtc_state->vrr_params);
486 dc_stream_adjust_vmin_vmax(
489 &acrtc_state->vrr_params.adjust);
490 spin_unlock_irqrestore(&adev->ddev->event_lock, flags);
495 #if defined(CONFIG_DRM_AMD_DC_DCN)
497 * dm_dcn_crtc_high_irq() - Handles VStartup interrupt for DCN generation ASICs
498 * @interrupt params - interrupt parameters
500 * Notify DRM's vblank event handler at VSTARTUP
502 * Unlike DCE hardware, we trigger the handler at VSTARTUP. at which:
503 * * We are close enough to VUPDATE - the point of no return for hw
504 * * We are in the fixed portion of variable front porch when vrr is enabled
505 * * We are before VUPDATE, where double-buffered vrr registers are swapped
507 * It is therefore the correct place to signal vblank, send user flip events,
510 static void dm_dcn_crtc_high_irq(void *interrupt_params)
512 struct common_irq_params *irq_params = interrupt_params;
513 struct amdgpu_device *adev = irq_params->adev;
514 struct amdgpu_crtc *acrtc;
515 struct dm_crtc_state *acrtc_state;
518 acrtc = get_crtc_by_otg_inst(adev, irq_params->irq_src - IRQ_TYPE_VBLANK);
523 acrtc_state = to_dm_crtc_state(acrtc->base.state);
525 DRM_DEBUG_DRIVER("crtc:%d, vupdate-vrr:%d\n", acrtc->crtc_id,
526 amdgpu_dm_vrr_active(acrtc_state));
528 amdgpu_dm_crtc_handle_crc_irq(&acrtc->base);
529 drm_crtc_handle_vblank(&acrtc->base);
531 spin_lock_irqsave(&adev->ddev->event_lock, flags);
533 if (acrtc_state->vrr_params.supported &&
534 acrtc_state->freesync_config.state == VRR_STATE_ACTIVE_VARIABLE) {
535 mod_freesync_handle_v_update(
536 adev->dm.freesync_module,
538 &acrtc_state->vrr_params);
540 dc_stream_adjust_vmin_vmax(
543 &acrtc_state->vrr_params.adjust);
546 if (acrtc->pflip_status == AMDGPU_FLIP_SUBMITTED) {
548 drm_crtc_send_vblank_event(&acrtc->base, acrtc->event);
550 drm_crtc_vblank_put(&acrtc->base);
552 acrtc->pflip_status = AMDGPU_FLIP_NONE;
555 spin_unlock_irqrestore(&adev->ddev->event_lock, flags);
559 static int dm_set_clockgating_state(void *handle,
560 enum amd_clockgating_state state)
565 static int dm_set_powergating_state(void *handle,
566 enum amd_powergating_state state)
571 /* Prototypes of private functions */
572 static int dm_early_init(void* handle);
574 /* Allocate memory for FBC compressed data */
575 static void amdgpu_dm_fbc_init(struct drm_connector *connector)
577 struct drm_device *dev = connector->dev;
578 struct amdgpu_device *adev = dev->dev_private;
579 struct dm_comressor_info *compressor = &adev->dm.compressor;
580 struct amdgpu_dm_connector *aconn = to_amdgpu_dm_connector(connector);
581 struct drm_display_mode *mode;
582 unsigned long max_size = 0;
584 if (adev->dm.dc->fbc_compressor == NULL)
587 if (aconn->dc_link->connector_signal != SIGNAL_TYPE_EDP)
590 if (compressor->bo_ptr)
594 list_for_each_entry(mode, &connector->modes, head) {
595 if (max_size < mode->htotal * mode->vtotal)
596 max_size = mode->htotal * mode->vtotal;
600 int r = amdgpu_bo_create_kernel(adev, max_size * 4, PAGE_SIZE,
601 AMDGPU_GEM_DOMAIN_GTT, &compressor->bo_ptr,
602 &compressor->gpu_addr, &compressor->cpu_addr);
605 DRM_ERROR("DM: Failed to initialize FBC\n");
607 adev->dm.dc->ctx->fbc_gpu_addr = compressor->gpu_addr;
608 DRM_INFO("DM: FBC alloc %lu\n", max_size*4);
615 static int amdgpu_dm_audio_component_get_eld(struct device *kdev, int port,
616 int pipe, bool *enabled,
617 unsigned char *buf, int max_bytes)
619 struct drm_device *dev = dev_get_drvdata(kdev);
620 struct amdgpu_device *adev = dev->dev_private;
621 struct drm_connector *connector;
622 struct drm_connector_list_iter conn_iter;
623 struct amdgpu_dm_connector *aconnector;
628 mutex_lock(&adev->dm.audio_lock);
630 drm_connector_list_iter_begin(dev, &conn_iter);
631 drm_for_each_connector_iter(connector, &conn_iter) {
632 aconnector = to_amdgpu_dm_connector(connector);
633 if (aconnector->audio_inst != port)
637 ret = drm_eld_size(connector->eld);
638 memcpy(buf, connector->eld, min(max_bytes, ret));
642 drm_connector_list_iter_end(&conn_iter);
644 mutex_unlock(&adev->dm.audio_lock);
646 DRM_DEBUG_KMS("Get ELD : idx=%d ret=%d en=%d\n", port, ret, *enabled);
651 static const struct drm_audio_component_ops amdgpu_dm_audio_component_ops = {
652 .get_eld = amdgpu_dm_audio_component_get_eld,
655 static int amdgpu_dm_audio_component_bind(struct device *kdev,
656 struct device *hda_kdev, void *data)
658 struct drm_device *dev = dev_get_drvdata(kdev);
659 struct amdgpu_device *adev = dev->dev_private;
660 struct drm_audio_component *acomp = data;
662 acomp->ops = &amdgpu_dm_audio_component_ops;
664 adev->dm.audio_component = acomp;
669 static void amdgpu_dm_audio_component_unbind(struct device *kdev,
670 struct device *hda_kdev, void *data)
672 struct drm_device *dev = dev_get_drvdata(kdev);
673 struct amdgpu_device *adev = dev->dev_private;
674 struct drm_audio_component *acomp = data;
678 adev->dm.audio_component = NULL;
681 static const struct component_ops amdgpu_dm_audio_component_bind_ops = {
682 .bind = amdgpu_dm_audio_component_bind,
683 .unbind = amdgpu_dm_audio_component_unbind,
686 static int amdgpu_dm_audio_init(struct amdgpu_device *adev)
693 adev->mode_info.audio.enabled = true;
695 adev->mode_info.audio.num_pins = adev->dm.dc->res_pool->audio_count;
697 for (i = 0; i < adev->mode_info.audio.num_pins; i++) {
698 adev->mode_info.audio.pin[i].channels = -1;
699 adev->mode_info.audio.pin[i].rate = -1;
700 adev->mode_info.audio.pin[i].bits_per_sample = -1;
701 adev->mode_info.audio.pin[i].status_bits = 0;
702 adev->mode_info.audio.pin[i].category_code = 0;
703 adev->mode_info.audio.pin[i].connected = false;
704 adev->mode_info.audio.pin[i].id =
705 adev->dm.dc->res_pool->audios[i]->inst;
706 adev->mode_info.audio.pin[i].offset = 0;
709 ret = component_add(adev->dev, &amdgpu_dm_audio_component_bind_ops);
713 adev->dm.audio_registered = true;
718 static void amdgpu_dm_audio_fini(struct amdgpu_device *adev)
723 if (!adev->mode_info.audio.enabled)
726 if (adev->dm.audio_registered) {
727 component_del(adev->dev, &amdgpu_dm_audio_component_bind_ops);
728 adev->dm.audio_registered = false;
731 /* TODO: Disable audio? */
733 adev->mode_info.audio.enabled = false;
736 void amdgpu_dm_audio_eld_notify(struct amdgpu_device *adev, int pin)
738 struct drm_audio_component *acomp = adev->dm.audio_component;
740 if (acomp && acomp->audio_ops && acomp->audio_ops->pin_eld_notify) {
741 DRM_DEBUG_KMS("Notify ELD: %d\n", pin);
743 acomp->audio_ops->pin_eld_notify(acomp->audio_ops->audio_ptr,
748 static int dm_dmub_hw_init(struct amdgpu_device *adev)
750 const struct dmcub_firmware_header_v1_0 *hdr;
751 struct dmub_srv *dmub_srv = adev->dm.dmub_srv;
752 struct dmub_srv_fb_info *fb_info = adev->dm.dmub_fb_info;
753 const struct firmware *dmub_fw = adev->dm.dmub_fw;
754 struct dmcu *dmcu = adev->dm.dc->res_pool->dmcu;
755 struct abm *abm = adev->dm.dc->res_pool->abm;
756 struct dmub_srv_hw_params hw_params;
757 enum dmub_status status;
758 const unsigned char *fw_inst_const, *fw_bss_data;
759 uint32_t i, fw_inst_const_size, fw_bss_data_size;
763 /* DMUB isn't supported on the ASIC. */
767 DRM_ERROR("No framebuffer info for DMUB service.\n");
772 /* Firmware required for DMUB support. */
773 DRM_ERROR("No firmware provided for DMUB.\n");
777 status = dmub_srv_has_hw_support(dmub_srv, &has_hw_support);
778 if (status != DMUB_STATUS_OK) {
779 DRM_ERROR("Error checking HW support for DMUB: %d\n", status);
783 if (!has_hw_support) {
784 DRM_INFO("DMUB unsupported on ASIC\n");
788 hdr = (const struct dmcub_firmware_header_v1_0 *)dmub_fw->data;
790 fw_inst_const = dmub_fw->data +
791 le32_to_cpu(hdr->header.ucode_array_offset_bytes) +
794 fw_bss_data = dmub_fw->data +
795 le32_to_cpu(hdr->header.ucode_array_offset_bytes) +
796 le32_to_cpu(hdr->inst_const_bytes);
798 /* Copy firmware and bios info into FB memory. */
799 fw_inst_const_size = le32_to_cpu(hdr->inst_const_bytes) -
800 PSP_HEADER_BYTES - PSP_FOOTER_BYTES;
802 fw_bss_data_size = le32_to_cpu(hdr->bss_data_bytes);
804 memcpy(fb_info->fb[DMUB_WINDOW_0_INST_CONST].cpu_addr, fw_inst_const,
806 memcpy(fb_info->fb[DMUB_WINDOW_2_BSS_DATA].cpu_addr, fw_bss_data,
808 memcpy(fb_info->fb[DMUB_WINDOW_3_VBIOS].cpu_addr, adev->bios,
811 /* Reset regions that need to be reset. */
812 memset(fb_info->fb[DMUB_WINDOW_4_MAILBOX].cpu_addr, 0,
813 fb_info->fb[DMUB_WINDOW_4_MAILBOX].size);
815 memset(fb_info->fb[DMUB_WINDOW_5_TRACEBUFF].cpu_addr, 0,
816 fb_info->fb[DMUB_WINDOW_5_TRACEBUFF].size);
818 memset(fb_info->fb[DMUB_WINDOW_6_FW_STATE].cpu_addr, 0,
819 fb_info->fb[DMUB_WINDOW_6_FW_STATE].size);
821 /* Initialize hardware. */
822 memset(&hw_params, 0, sizeof(hw_params));
823 hw_params.fb_base = adev->gmc.fb_start;
824 hw_params.fb_offset = adev->gmc.aper_base;
827 hw_params.psp_version = dmcu->psp_version;
829 for (i = 0; i < fb_info->num_fb; ++i)
830 hw_params.fb[i] = &fb_info->fb[i];
832 status = dmub_srv_hw_init(dmub_srv, &hw_params);
833 if (status != DMUB_STATUS_OK) {
834 DRM_ERROR("Error initializing DMUB HW: %d\n", status);
838 /* Wait for firmware load to finish. */
839 status = dmub_srv_wait_for_auto_load(dmub_srv, 100000);
840 if (status != DMUB_STATUS_OK)
841 DRM_WARN("Wait for DMUB auto-load failed: %d\n", status);
843 /* Init DMCU and ABM if available. */
845 dmcu->funcs->dmcu_init(dmcu);
846 abm->dmcu_is_running = dmcu->funcs->is_dmcu_initialized(dmcu);
849 adev->dm.dc->ctx->dmub_srv = dc_dmub_srv_create(adev->dm.dc, dmub_srv);
850 if (!adev->dm.dc->ctx->dmub_srv) {
851 DRM_ERROR("Couldn't allocate DC DMUB server!\n");
855 DRM_INFO("DMUB hardware initialized: version=0x%08X\n",
856 adev->dm.dmcub_fw_version);
861 static int amdgpu_dm_init(struct amdgpu_device *adev)
863 struct dc_init_data init_data;
864 #ifdef CONFIG_DRM_AMD_DC_HDCP
865 struct dc_callback_init init_params;
869 adev->dm.ddev = adev->ddev;
870 adev->dm.adev = adev;
872 /* Zero all the fields */
873 memset(&init_data, 0, sizeof(init_data));
874 #ifdef CONFIG_DRM_AMD_DC_HDCP
875 memset(&init_params, 0, sizeof(init_params));
878 mutex_init(&adev->dm.dc_lock);
879 mutex_init(&adev->dm.audio_lock);
881 if(amdgpu_dm_irq_init(adev)) {
882 DRM_ERROR("amdgpu: failed to initialize DM IRQ support.\n");
886 init_data.asic_id.chip_family = adev->family;
888 init_data.asic_id.pci_revision_id = adev->rev_id;
889 init_data.asic_id.hw_internal_rev = adev->external_rev_id;
891 init_data.asic_id.vram_width = adev->gmc.vram_width;
892 /* TODO: initialize init_data.asic_id.vram_type here!!!! */
893 init_data.asic_id.atombios_base_address =
894 adev->mode_info.atom_context->bios;
896 init_data.driver = adev;
898 adev->dm.cgs_device = amdgpu_cgs_create_device(adev);
900 if (!adev->dm.cgs_device) {
901 DRM_ERROR("amdgpu: failed to create cgs device.\n");
905 init_data.cgs_device = adev->dm.cgs_device;
907 init_data.dce_environment = DCE_ENV_PRODUCTION_DRV;
910 * TODO debug why this doesn't work on Raven
912 if (adev->flags & AMD_IS_APU &&
913 adev->asic_type >= CHIP_CARRIZO &&
914 adev->asic_type < CHIP_RAVEN)
915 init_data.flags.gpu_vm_support = true;
917 if (amdgpu_dc_feature_mask & DC_FBC_MASK)
918 init_data.flags.fbc_support = true;
920 if (amdgpu_dc_feature_mask & DC_MULTI_MON_PP_MCLK_SWITCH_MASK)
921 init_data.flags.multi_mon_pp_mclk_switch = true;
923 if (amdgpu_dc_feature_mask & DC_DISABLE_FRACTIONAL_PWM_MASK)
924 init_data.flags.disable_fractional_pwm = true;
926 init_data.flags.power_down_display_on_boot = true;
928 init_data.soc_bounding_box = adev->dm.soc_bounding_box;
930 /* Display Core create. */
931 adev->dm.dc = dc_create(&init_data);
934 DRM_INFO("Display Core initialized with v%s!\n", DC_VER);
936 DRM_INFO("Display Core failed to initialize with v%s!\n", DC_VER);
940 dc_hardware_init(adev->dm.dc);
942 r = dm_dmub_hw_init(adev);
944 DRM_ERROR("DMUB interface failed to initialize: status=%d\n", r);
948 adev->dm.freesync_module = mod_freesync_create(adev->dm.dc);
949 if (!adev->dm.freesync_module) {
951 "amdgpu: failed to initialize freesync_module.\n");
953 DRM_DEBUG_DRIVER("amdgpu: freesync_module init done %p.\n",
954 adev->dm.freesync_module);
956 amdgpu_dm_init_color_mod();
958 #ifdef CONFIG_DRM_AMD_DC_HDCP
959 if (adev->asic_type >= CHIP_RAVEN) {
960 adev->dm.hdcp_workqueue = hdcp_create_workqueue(&adev->psp, &init_params.cp_psp, adev->dm.dc);
962 if (!adev->dm.hdcp_workqueue)
963 DRM_ERROR("amdgpu: failed to initialize hdcp_workqueue.\n");
965 DRM_DEBUG_DRIVER("amdgpu: hdcp_workqueue init done %p.\n", adev->dm.hdcp_workqueue);
967 dc_init_callbacks(adev->dm.dc, &init_params);
970 if (amdgpu_dm_initialize_drm_device(adev)) {
972 "amdgpu: failed to initialize sw for display support.\n");
976 /* Update the actual used number of crtc */
977 adev->mode_info.num_crtc = adev->dm.display_indexes_num;
979 /* TODO: Add_display_info? */
981 /* TODO use dynamic cursor width */
982 adev->ddev->mode_config.cursor_width = adev->dm.dc->caps.max_cursor_size;
983 adev->ddev->mode_config.cursor_height = adev->dm.dc->caps.max_cursor_size;
985 if (drm_vblank_init(adev->ddev, adev->dm.display_indexes_num)) {
987 "amdgpu: failed to initialize sw for display support.\n");
991 #if defined(CONFIG_DEBUG_FS)
992 if (dtn_debugfs_init(adev))
993 DRM_ERROR("amdgpu: failed initialize dtn debugfs support.\n");
996 DRM_DEBUG_DRIVER("KMS initialized.\n");
1000 amdgpu_dm_fini(adev);
1005 static void amdgpu_dm_fini(struct amdgpu_device *adev)
1007 amdgpu_dm_audio_fini(adev);
1009 amdgpu_dm_destroy_drm_device(&adev->dm);
1011 #ifdef CONFIG_DRM_AMD_DC_HDCP
1012 if (adev->dm.hdcp_workqueue) {
1013 hdcp_destroy(adev->dm.hdcp_workqueue);
1014 adev->dm.hdcp_workqueue = NULL;
1018 dc_deinit_callbacks(adev->dm.dc);
1020 if (adev->dm.dc->ctx->dmub_srv) {
1021 dc_dmub_srv_destroy(&adev->dm.dc->ctx->dmub_srv);
1022 adev->dm.dc->ctx->dmub_srv = NULL;
1025 if (adev->dm.dmub_bo)
1026 amdgpu_bo_free_kernel(&adev->dm.dmub_bo,
1027 &adev->dm.dmub_bo_gpu_addr,
1028 &adev->dm.dmub_bo_cpu_addr);
1030 /* DC Destroy TODO: Replace destroy DAL */
1032 dc_destroy(&adev->dm.dc);
1034 * TODO: pageflip, vlank interrupt
1036 * amdgpu_dm_irq_fini(adev);
1039 if (adev->dm.cgs_device) {
1040 amdgpu_cgs_destroy_device(adev->dm.cgs_device);
1041 adev->dm.cgs_device = NULL;
1043 if (adev->dm.freesync_module) {
1044 mod_freesync_destroy(adev->dm.freesync_module);
1045 adev->dm.freesync_module = NULL;
1048 mutex_destroy(&adev->dm.audio_lock);
1049 mutex_destroy(&adev->dm.dc_lock);
1054 static int load_dmcu_fw(struct amdgpu_device *adev)
1056 const char *fw_name_dmcu = NULL;
1058 const struct dmcu_firmware_header_v1_0 *hdr;
1060 switch(adev->asic_type) {
1070 case CHIP_POLARIS11:
1071 case CHIP_POLARIS10:
1072 case CHIP_POLARIS12:
1083 if (ASICREV_IS_PICASSO(adev->external_rev_id))
1084 fw_name_dmcu = FIRMWARE_RAVEN_DMCU;
1085 else if (ASICREV_IS_RAVEN2(adev->external_rev_id))
1086 fw_name_dmcu = FIRMWARE_RAVEN_DMCU;
1091 DRM_ERROR("Unsupported ASIC type: 0x%X\n", adev->asic_type);
1095 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) {
1096 DRM_DEBUG_KMS("dm: DMCU firmware not supported on direct or SMU loading\n");
1100 r = request_firmware_direct(&adev->dm.fw_dmcu, fw_name_dmcu, adev->dev);
1102 /* DMCU firmware is not necessary, so don't raise a fuss if it's missing */
1103 DRM_DEBUG_KMS("dm: DMCU firmware not found\n");
1104 adev->dm.fw_dmcu = NULL;
1108 dev_err(adev->dev, "amdgpu_dm: Can't load firmware \"%s\"\n",
1113 r = amdgpu_ucode_validate(adev->dm.fw_dmcu);
1115 dev_err(adev->dev, "amdgpu_dm: Can't validate firmware \"%s\"\n",
1117 release_firmware(adev->dm.fw_dmcu);
1118 adev->dm.fw_dmcu = NULL;
1122 hdr = (const struct dmcu_firmware_header_v1_0 *)adev->dm.fw_dmcu->data;
1123 adev->firmware.ucode[AMDGPU_UCODE_ID_DMCU_ERAM].ucode_id = AMDGPU_UCODE_ID_DMCU_ERAM;
1124 adev->firmware.ucode[AMDGPU_UCODE_ID_DMCU_ERAM].fw = adev->dm.fw_dmcu;
1125 adev->firmware.fw_size +=
1126 ALIGN(le32_to_cpu(hdr->header.ucode_size_bytes) - le32_to_cpu(hdr->intv_size_bytes), PAGE_SIZE);
1128 adev->firmware.ucode[AMDGPU_UCODE_ID_DMCU_INTV].ucode_id = AMDGPU_UCODE_ID_DMCU_INTV;
1129 adev->firmware.ucode[AMDGPU_UCODE_ID_DMCU_INTV].fw = adev->dm.fw_dmcu;
1130 adev->firmware.fw_size +=
1131 ALIGN(le32_to_cpu(hdr->intv_size_bytes), PAGE_SIZE);
1133 adev->dm.dmcu_fw_version = le32_to_cpu(hdr->header.ucode_version);
1135 DRM_DEBUG_KMS("PSP loading DMCU firmware\n");
1140 static uint32_t amdgpu_dm_dmub_reg_read(void *ctx, uint32_t address)
1142 struct amdgpu_device *adev = ctx;
1144 return dm_read_reg(adev->dm.dc->ctx, address);
1147 static void amdgpu_dm_dmub_reg_write(void *ctx, uint32_t address,
1150 struct amdgpu_device *adev = ctx;
1152 return dm_write_reg(adev->dm.dc->ctx, address, value);
1155 static int dm_dmub_sw_init(struct amdgpu_device *adev)
1157 struct dmub_srv_create_params create_params;
1158 struct dmub_srv_region_params region_params;
1159 struct dmub_srv_region_info region_info;
1160 struct dmub_srv_fb_params fb_params;
1161 struct dmub_srv_fb_info *fb_info;
1162 struct dmub_srv *dmub_srv;
1163 const struct dmcub_firmware_header_v1_0 *hdr;
1164 const char *fw_name_dmub;
1165 enum dmub_asic dmub_asic;
1166 enum dmub_status status;
1169 switch (adev->asic_type) {
1171 dmub_asic = DMUB_ASIC_DCN21;
1172 fw_name_dmub = FIRMWARE_RENOIR_DMUB;
1176 /* ASIC doesn't support DMUB. */
1180 r = request_firmware_direct(&adev->dm.dmub_fw, fw_name_dmub, adev->dev);
1182 DRM_ERROR("DMUB firmware loading failed: %d\n", r);
1186 r = amdgpu_ucode_validate(adev->dm.dmub_fw);
1188 DRM_ERROR("Couldn't validate DMUB firmware: %d\n", r);
1192 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) {
1193 DRM_WARN("Only PSP firmware loading is supported for DMUB\n");
1197 hdr = (const struct dmcub_firmware_header_v1_0 *)adev->dm.dmub_fw->data;
1198 adev->firmware.ucode[AMDGPU_UCODE_ID_DMCUB].ucode_id =
1199 AMDGPU_UCODE_ID_DMCUB;
1200 adev->firmware.ucode[AMDGPU_UCODE_ID_DMCUB].fw = adev->dm.dmub_fw;
1201 adev->firmware.fw_size +=
1202 ALIGN(le32_to_cpu(hdr->inst_const_bytes), PAGE_SIZE);
1204 adev->dm.dmcub_fw_version = le32_to_cpu(hdr->header.ucode_version);
1206 DRM_INFO("Loading DMUB firmware via PSP: version=0x%08X\n",
1207 adev->dm.dmcub_fw_version);
1209 adev->dm.dmub_srv = kzalloc(sizeof(*adev->dm.dmub_srv), GFP_KERNEL);
1210 dmub_srv = adev->dm.dmub_srv;
1213 DRM_ERROR("Failed to allocate DMUB service!\n");
1217 memset(&create_params, 0, sizeof(create_params));
1218 create_params.user_ctx = adev;
1219 create_params.funcs.reg_read = amdgpu_dm_dmub_reg_read;
1220 create_params.funcs.reg_write = amdgpu_dm_dmub_reg_write;
1221 create_params.asic = dmub_asic;
1223 /* Create the DMUB service. */
1224 status = dmub_srv_create(dmub_srv, &create_params);
1225 if (status != DMUB_STATUS_OK) {
1226 DRM_ERROR("Error creating DMUB service: %d\n", status);
1230 /* Calculate the size of all the regions for the DMUB service. */
1231 memset(®ion_params, 0, sizeof(region_params));
1233 region_params.inst_const_size = le32_to_cpu(hdr->inst_const_bytes) -
1234 PSP_HEADER_BYTES - PSP_FOOTER_BYTES;
1235 region_params.bss_data_size = le32_to_cpu(hdr->bss_data_bytes);
1236 region_params.vbios_size = adev->bios_size;
1237 region_params.fw_bss_data =
1238 adev->dm.dmub_fw->data +
1239 le32_to_cpu(hdr->header.ucode_array_offset_bytes) +
1240 le32_to_cpu(hdr->inst_const_bytes);
1242 status = dmub_srv_calc_region_info(dmub_srv, ®ion_params,
1245 if (status != DMUB_STATUS_OK) {
1246 DRM_ERROR("Error calculating DMUB region info: %d\n", status);
1251 * Allocate a framebuffer based on the total size of all the regions.
1252 * TODO: Move this into GART.
1254 r = amdgpu_bo_create_kernel(adev, region_info.fb_size, PAGE_SIZE,
1255 AMDGPU_GEM_DOMAIN_VRAM, &adev->dm.dmub_bo,
1256 &adev->dm.dmub_bo_gpu_addr,
1257 &adev->dm.dmub_bo_cpu_addr);
1261 /* Rebase the regions on the framebuffer address. */
1262 memset(&fb_params, 0, sizeof(fb_params));
1263 fb_params.cpu_addr = adev->dm.dmub_bo_cpu_addr;
1264 fb_params.gpu_addr = adev->dm.dmub_bo_gpu_addr;
1265 fb_params.region_info = ®ion_info;
1267 adev->dm.dmub_fb_info =
1268 kzalloc(sizeof(*adev->dm.dmub_fb_info), GFP_KERNEL);
1269 fb_info = adev->dm.dmub_fb_info;
1273 "Failed to allocate framebuffer info for DMUB service!\n");
1277 status = dmub_srv_calc_fb_info(dmub_srv, &fb_params, fb_info);
1278 if (status != DMUB_STATUS_OK) {
1279 DRM_ERROR("Error calculating DMUB FB info: %d\n", status);
1286 static int dm_sw_init(void *handle)
1288 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1291 r = dm_dmub_sw_init(adev);
1295 return load_dmcu_fw(adev);
1298 static int dm_sw_fini(void *handle)
1300 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1302 kfree(adev->dm.dmub_fb_info);
1303 adev->dm.dmub_fb_info = NULL;
1305 if (adev->dm.dmub_srv) {
1306 dmub_srv_destroy(adev->dm.dmub_srv);
1307 adev->dm.dmub_srv = NULL;
1310 if (adev->dm.dmub_fw) {
1311 release_firmware(adev->dm.dmub_fw);
1312 adev->dm.dmub_fw = NULL;
1315 if(adev->dm.fw_dmcu) {
1316 release_firmware(adev->dm.fw_dmcu);
1317 adev->dm.fw_dmcu = NULL;
1323 static int detect_mst_link_for_all_connectors(struct drm_device *dev)
1325 struct amdgpu_dm_connector *aconnector;
1326 struct drm_connector *connector;
1327 struct drm_connector_list_iter iter;
1330 drm_connector_list_iter_begin(dev, &iter);
1331 drm_for_each_connector_iter(connector, &iter) {
1332 aconnector = to_amdgpu_dm_connector(connector);
1333 if (aconnector->dc_link->type == dc_connection_mst_branch &&
1334 aconnector->mst_mgr.aux) {
1335 DRM_DEBUG_DRIVER("DM_MST: starting TM on aconnector: %p [id: %d]\n",
1337 aconnector->base.base.id);
1339 ret = drm_dp_mst_topology_mgr_set_mst(&aconnector->mst_mgr, true);
1341 DRM_ERROR("DM_MST: Failed to start MST\n");
1342 aconnector->dc_link->type =
1343 dc_connection_single;
1348 drm_connector_list_iter_end(&iter);
1353 static int dm_late_init(void *handle)
1355 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1357 struct dmcu_iram_parameters params;
1358 unsigned int linear_lut[16];
1360 struct dmcu *dmcu = adev->dm.dc->res_pool->dmcu;
1363 for (i = 0; i < 16; i++)
1364 linear_lut[i] = 0xFFFF * i / 15;
1367 params.backlight_ramping_start = 0xCCCC;
1368 params.backlight_ramping_reduction = 0xCCCCCCCC;
1369 params.backlight_lut_array_size = 16;
1370 params.backlight_lut_array = linear_lut;
1372 /* Min backlight level after ABM reduction, Don't allow below 1%
1373 * 0xFFFF x 0.01 = 0x28F
1375 params.min_abm_backlight = 0x28F;
1377 /* todo will enable for navi10 */
1378 if (adev->asic_type <= CHIP_RAVEN) {
1379 ret = dmcu_load_iram(dmcu, params);
1385 return detect_mst_link_for_all_connectors(adev->ddev);
1388 static void s3_handle_mst(struct drm_device *dev, bool suspend)
1390 struct amdgpu_dm_connector *aconnector;
1391 struct drm_connector *connector;
1392 struct drm_connector_list_iter iter;
1393 struct drm_dp_mst_topology_mgr *mgr;
1395 bool need_hotplug = false;
1397 drm_connector_list_iter_begin(dev, &iter);
1398 drm_for_each_connector_iter(connector, &iter) {
1399 aconnector = to_amdgpu_dm_connector(connector);
1400 if (aconnector->dc_link->type != dc_connection_mst_branch ||
1401 aconnector->mst_port)
1404 mgr = &aconnector->mst_mgr;
1407 drm_dp_mst_topology_mgr_suspend(mgr);
1409 ret = drm_dp_mst_topology_mgr_resume(mgr, true);
1411 drm_dp_mst_topology_mgr_set_mst(mgr, false);
1412 need_hotplug = true;
1416 drm_connector_list_iter_end(&iter);
1419 drm_kms_helper_hotplug_event(dev);
1423 * dm_hw_init() - Initialize DC device
1424 * @handle: The base driver device containing the amdgpu_dm device.
1426 * Initialize the &struct amdgpu_display_manager device. This involves calling
1427 * the initializers of each DM component, then populating the struct with them.
1429 * Although the function implies hardware initialization, both hardware and
1430 * software are initialized here. Splitting them out to their relevant init
1431 * hooks is a future TODO item.
1433 * Some notable things that are initialized here:
1435 * - Display Core, both software and hardware
1436 * - DC modules that we need (freesync and color management)
1437 * - DRM software states
1438 * - Interrupt sources and handlers
1440 * - Debug FS entries, if enabled
1442 static int dm_hw_init(void *handle)
1444 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1445 /* Create DAL display manager */
1446 amdgpu_dm_init(adev);
1447 amdgpu_dm_hpd_init(adev);
1453 * dm_hw_fini() - Teardown DC device
1454 * @handle: The base driver device containing the amdgpu_dm device.
1456 * Teardown components within &struct amdgpu_display_manager that require
1457 * cleanup. This involves cleaning up the DRM device, DC, and any modules that
1458 * were loaded. Also flush IRQ workqueues and disable them.
1460 static int dm_hw_fini(void *handle)
1462 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1464 amdgpu_dm_hpd_fini(adev);
1466 amdgpu_dm_irq_fini(adev);
1467 amdgpu_dm_fini(adev);
1471 static int dm_suspend(void *handle)
1473 struct amdgpu_device *adev = handle;
1474 struct amdgpu_display_manager *dm = &adev->dm;
1477 WARN_ON(adev->dm.cached_state);
1478 adev->dm.cached_state = drm_atomic_helper_suspend(adev->ddev);
1480 s3_handle_mst(adev->ddev, true);
1482 amdgpu_dm_irq_suspend(adev);
1485 dc_set_power_state(dm->dc, DC_ACPI_CM_POWER_STATE_D3);
1490 static struct amdgpu_dm_connector *
1491 amdgpu_dm_find_first_crtc_matching_connector(struct drm_atomic_state *state,
1492 struct drm_crtc *crtc)
1495 struct drm_connector_state *new_con_state;
1496 struct drm_connector *connector;
1497 struct drm_crtc *crtc_from_state;
1499 for_each_new_connector_in_state(state, connector, new_con_state, i) {
1500 crtc_from_state = new_con_state->crtc;
1502 if (crtc_from_state == crtc)
1503 return to_amdgpu_dm_connector(connector);
1509 static void emulated_link_detect(struct dc_link *link)
1511 struct dc_sink_init_data sink_init_data = { 0 };
1512 struct display_sink_capability sink_caps = { 0 };
1513 enum dc_edid_status edid_status;
1514 struct dc_context *dc_ctx = link->ctx;
1515 struct dc_sink *sink = NULL;
1516 struct dc_sink *prev_sink = NULL;
1518 link->type = dc_connection_none;
1519 prev_sink = link->local_sink;
1521 if (prev_sink != NULL)
1522 dc_sink_retain(prev_sink);
1524 switch (link->connector_signal) {
1525 case SIGNAL_TYPE_HDMI_TYPE_A: {
1526 sink_caps.transaction_type = DDC_TRANSACTION_TYPE_I2C;
1527 sink_caps.signal = SIGNAL_TYPE_HDMI_TYPE_A;
1531 case SIGNAL_TYPE_DVI_SINGLE_LINK: {
1532 sink_caps.transaction_type = DDC_TRANSACTION_TYPE_I2C;
1533 sink_caps.signal = SIGNAL_TYPE_DVI_SINGLE_LINK;
1537 case SIGNAL_TYPE_DVI_DUAL_LINK: {
1538 sink_caps.transaction_type = DDC_TRANSACTION_TYPE_I2C;
1539 sink_caps.signal = SIGNAL_TYPE_DVI_DUAL_LINK;
1543 case SIGNAL_TYPE_LVDS: {
1544 sink_caps.transaction_type = DDC_TRANSACTION_TYPE_I2C;
1545 sink_caps.signal = SIGNAL_TYPE_LVDS;
1549 case SIGNAL_TYPE_EDP: {
1550 sink_caps.transaction_type =
1551 DDC_TRANSACTION_TYPE_I2C_OVER_AUX;
1552 sink_caps.signal = SIGNAL_TYPE_EDP;
1556 case SIGNAL_TYPE_DISPLAY_PORT: {
1557 sink_caps.transaction_type =
1558 DDC_TRANSACTION_TYPE_I2C_OVER_AUX;
1559 sink_caps.signal = SIGNAL_TYPE_VIRTUAL;
1564 DC_ERROR("Invalid connector type! signal:%d\n",
1565 link->connector_signal);
1569 sink_init_data.link = link;
1570 sink_init_data.sink_signal = sink_caps.signal;
1572 sink = dc_sink_create(&sink_init_data);
1574 DC_ERROR("Failed to create sink!\n");
1578 /* dc_sink_create returns a new reference */
1579 link->local_sink = sink;
1581 edid_status = dm_helpers_read_local_edid(
1586 if (edid_status != EDID_OK)
1587 DC_ERROR("Failed to read EDID");
1591 static int dm_resume(void *handle)
1593 struct amdgpu_device *adev = handle;
1594 struct drm_device *ddev = adev->ddev;
1595 struct amdgpu_display_manager *dm = &adev->dm;
1596 struct amdgpu_dm_connector *aconnector;
1597 struct drm_connector *connector;
1598 struct drm_connector_list_iter iter;
1599 struct drm_crtc *crtc;
1600 struct drm_crtc_state *new_crtc_state;
1601 struct dm_crtc_state *dm_new_crtc_state;
1602 struct drm_plane *plane;
1603 struct drm_plane_state *new_plane_state;
1604 struct dm_plane_state *dm_new_plane_state;
1605 struct dm_atomic_state *dm_state = to_dm_atomic_state(dm->atomic_obj.state);
1606 enum dc_connection_type new_connection_type = dc_connection_none;
1609 /* Recreate dc_state - DC invalidates it when setting power state to S3. */
1610 dc_release_state(dm_state->context);
1611 dm_state->context = dc_create_state(dm->dc);
1612 /* TODO: Remove dc_state->dccg, use dc->dccg directly. */
1613 dc_resource_state_construct(dm->dc, dm_state->context);
1615 /* Before powering on DC we need to re-initialize DMUB. */
1616 r = dm_dmub_hw_init(adev);
1618 DRM_ERROR("DMUB interface failed to initialize: status=%d\n", r);
1620 /* power on hardware */
1621 dc_set_power_state(dm->dc, DC_ACPI_CM_POWER_STATE_D0);
1623 /* program HPD filter */
1627 * early enable HPD Rx IRQ, should be done before set mode as short
1628 * pulse interrupts are used for MST
1630 amdgpu_dm_irq_resume_early(adev);
1632 /* On resume we need to rewrite the MSTM control bits to enable MST*/
1633 s3_handle_mst(ddev, false);
1636 drm_connector_list_iter_begin(ddev, &iter);
1637 drm_for_each_connector_iter(connector, &iter) {
1638 aconnector = to_amdgpu_dm_connector(connector);
1641 * this is the case when traversing through already created
1642 * MST connectors, should be skipped
1644 if (aconnector->mst_port)
1647 mutex_lock(&aconnector->hpd_lock);
1648 if (!dc_link_detect_sink(aconnector->dc_link, &new_connection_type))
1649 DRM_ERROR("KMS: Failed to detect connector\n");
1651 if (aconnector->base.force && new_connection_type == dc_connection_none)
1652 emulated_link_detect(aconnector->dc_link);
1654 dc_link_detect(aconnector->dc_link, DETECT_REASON_HPD);
1656 if (aconnector->fake_enable && aconnector->dc_link->local_sink)
1657 aconnector->fake_enable = false;
1659 if (aconnector->dc_sink)
1660 dc_sink_release(aconnector->dc_sink);
1661 aconnector->dc_sink = NULL;
1662 amdgpu_dm_update_connector_after_detect(aconnector);
1663 mutex_unlock(&aconnector->hpd_lock);
1665 drm_connector_list_iter_end(&iter);
1667 /* Force mode set in atomic commit */
1668 for_each_new_crtc_in_state(dm->cached_state, crtc, new_crtc_state, i)
1669 new_crtc_state->active_changed = true;
1672 * atomic_check is expected to create the dc states. We need to release
1673 * them here, since they were duplicated as part of the suspend
1676 for_each_new_crtc_in_state(dm->cached_state, crtc, new_crtc_state, i) {
1677 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
1678 if (dm_new_crtc_state->stream) {
1679 WARN_ON(kref_read(&dm_new_crtc_state->stream->refcount) > 1);
1680 dc_stream_release(dm_new_crtc_state->stream);
1681 dm_new_crtc_state->stream = NULL;
1685 for_each_new_plane_in_state(dm->cached_state, plane, new_plane_state, i) {
1686 dm_new_plane_state = to_dm_plane_state(new_plane_state);
1687 if (dm_new_plane_state->dc_state) {
1688 WARN_ON(kref_read(&dm_new_plane_state->dc_state->refcount) > 1);
1689 dc_plane_state_release(dm_new_plane_state->dc_state);
1690 dm_new_plane_state->dc_state = NULL;
1694 drm_atomic_helper_resume(ddev, dm->cached_state);
1696 dm->cached_state = NULL;
1698 amdgpu_dm_irq_resume_late(adev);
1706 * DM (and consequently DC) is registered in the amdgpu base driver as a IP
1707 * block. When CONFIG_DRM_AMD_DC is enabled, the DM device IP block is added to
1708 * the base driver's device list to be initialized and torn down accordingly.
1710 * The functions to do so are provided as hooks in &struct amd_ip_funcs.
1713 static const struct amd_ip_funcs amdgpu_dm_funcs = {
1715 .early_init = dm_early_init,
1716 .late_init = dm_late_init,
1717 .sw_init = dm_sw_init,
1718 .sw_fini = dm_sw_fini,
1719 .hw_init = dm_hw_init,
1720 .hw_fini = dm_hw_fini,
1721 .suspend = dm_suspend,
1722 .resume = dm_resume,
1723 .is_idle = dm_is_idle,
1724 .wait_for_idle = dm_wait_for_idle,
1725 .check_soft_reset = dm_check_soft_reset,
1726 .soft_reset = dm_soft_reset,
1727 .set_clockgating_state = dm_set_clockgating_state,
1728 .set_powergating_state = dm_set_powergating_state,
1731 const struct amdgpu_ip_block_version dm_ip_block =
1733 .type = AMD_IP_BLOCK_TYPE_DCE,
1737 .funcs = &amdgpu_dm_funcs,
1747 static const struct drm_mode_config_funcs amdgpu_dm_mode_funcs = {
1748 .fb_create = amdgpu_display_user_framebuffer_create,
1749 .output_poll_changed = drm_fb_helper_output_poll_changed,
1750 .atomic_check = amdgpu_dm_atomic_check,
1751 .atomic_commit = amdgpu_dm_atomic_commit,
1754 static struct drm_mode_config_helper_funcs amdgpu_dm_mode_config_helperfuncs = {
1755 .atomic_commit_tail = amdgpu_dm_atomic_commit_tail
1759 amdgpu_dm_update_connector_after_detect(struct amdgpu_dm_connector *aconnector)
1761 struct drm_connector *connector = &aconnector->base;
1762 struct drm_device *dev = connector->dev;
1763 struct dc_sink *sink;
1765 /* MST handled by drm_mst framework */
1766 if (aconnector->mst_mgr.mst_state == true)
1770 sink = aconnector->dc_link->local_sink;
1772 dc_sink_retain(sink);
1775 * Edid mgmt connector gets first update only in mode_valid hook and then
1776 * the connector sink is set to either fake or physical sink depends on link status.
1777 * Skip if already done during boot.
1779 if (aconnector->base.force != DRM_FORCE_UNSPECIFIED
1780 && aconnector->dc_em_sink) {
1783 * For S3 resume with headless use eml_sink to fake stream
1784 * because on resume connector->sink is set to NULL
1786 mutex_lock(&dev->mode_config.mutex);
1789 if (aconnector->dc_sink) {
1790 amdgpu_dm_update_freesync_caps(connector, NULL);
1792 * retain and release below are used to
1793 * bump up refcount for sink because the link doesn't point
1794 * to it anymore after disconnect, so on next crtc to connector
1795 * reshuffle by UMD we will get into unwanted dc_sink release
1797 dc_sink_release(aconnector->dc_sink);
1799 aconnector->dc_sink = sink;
1800 dc_sink_retain(aconnector->dc_sink);
1801 amdgpu_dm_update_freesync_caps(connector,
1804 amdgpu_dm_update_freesync_caps(connector, NULL);
1805 if (!aconnector->dc_sink) {
1806 aconnector->dc_sink = aconnector->dc_em_sink;
1807 dc_sink_retain(aconnector->dc_sink);
1811 mutex_unlock(&dev->mode_config.mutex);
1814 dc_sink_release(sink);
1819 * TODO: temporary guard to look for proper fix
1820 * if this sink is MST sink, we should not do anything
1822 if (sink && sink->sink_signal == SIGNAL_TYPE_DISPLAY_PORT_MST) {
1823 dc_sink_release(sink);
1827 if (aconnector->dc_sink == sink) {
1829 * We got a DP short pulse (Link Loss, DP CTS, etc...).
1832 DRM_DEBUG_DRIVER("DCHPD: connector_id=%d: dc_sink didn't change.\n",
1833 aconnector->connector_id);
1835 dc_sink_release(sink);
1839 DRM_DEBUG_DRIVER("DCHPD: connector_id=%d: Old sink=%p New sink=%p\n",
1840 aconnector->connector_id, aconnector->dc_sink, sink);
1842 mutex_lock(&dev->mode_config.mutex);
1845 * 1. Update status of the drm connector
1846 * 2. Send an event and let userspace tell us what to do
1850 * TODO: check if we still need the S3 mode update workaround.
1851 * If yes, put it here.
1853 if (aconnector->dc_sink)
1854 amdgpu_dm_update_freesync_caps(connector, NULL);
1856 aconnector->dc_sink = sink;
1857 dc_sink_retain(aconnector->dc_sink);
1858 if (sink->dc_edid.length == 0) {
1859 aconnector->edid = NULL;
1860 drm_dp_cec_unset_edid(&aconnector->dm_dp_aux.aux);
1863 (struct edid *) sink->dc_edid.raw_edid;
1866 drm_connector_update_edid_property(connector,
1868 drm_dp_cec_set_edid(&aconnector->dm_dp_aux.aux,
1871 amdgpu_dm_update_freesync_caps(connector, aconnector->edid);
1874 drm_dp_cec_unset_edid(&aconnector->dm_dp_aux.aux);
1875 amdgpu_dm_update_freesync_caps(connector, NULL);
1876 drm_connector_update_edid_property(connector, NULL);
1877 aconnector->num_modes = 0;
1878 dc_sink_release(aconnector->dc_sink);
1879 aconnector->dc_sink = NULL;
1880 aconnector->edid = NULL;
1881 #ifdef CONFIG_DRM_AMD_DC_HDCP
1882 /* Set CP to DESIRED if it was ENABLED, so we can re-enable it again on hotplug */
1883 if (connector->state->content_protection == DRM_MODE_CONTENT_PROTECTION_ENABLED)
1884 connector->state->content_protection = DRM_MODE_CONTENT_PROTECTION_DESIRED;
1888 mutex_unlock(&dev->mode_config.mutex);
1891 dc_sink_release(sink);
1894 static void handle_hpd_irq(void *param)
1896 struct amdgpu_dm_connector *aconnector = (struct amdgpu_dm_connector *)param;
1897 struct drm_connector *connector = &aconnector->base;
1898 struct drm_device *dev = connector->dev;
1899 enum dc_connection_type new_connection_type = dc_connection_none;
1900 #ifdef CONFIG_DRM_AMD_DC_HDCP
1901 struct amdgpu_device *adev = dev->dev_private;
1905 * In case of failure or MST no need to update connector status or notify the OS
1906 * since (for MST case) MST does this in its own context.
1908 mutex_lock(&aconnector->hpd_lock);
1910 #ifdef CONFIG_DRM_AMD_DC_HDCP
1911 if (adev->asic_type >= CHIP_RAVEN)
1912 hdcp_reset_display(adev->dm.hdcp_workqueue, aconnector->dc_link->link_index);
1914 if (aconnector->fake_enable)
1915 aconnector->fake_enable = false;
1917 if (!dc_link_detect_sink(aconnector->dc_link, &new_connection_type))
1918 DRM_ERROR("KMS: Failed to detect connector\n");
1920 if (aconnector->base.force && new_connection_type == dc_connection_none) {
1921 emulated_link_detect(aconnector->dc_link);
1924 drm_modeset_lock_all(dev);
1925 dm_restore_drm_connector_state(dev, connector);
1926 drm_modeset_unlock_all(dev);
1928 if (aconnector->base.force == DRM_FORCE_UNSPECIFIED)
1929 drm_kms_helper_hotplug_event(dev);
1931 } else if (dc_link_detect(aconnector->dc_link, DETECT_REASON_HPD)) {
1932 amdgpu_dm_update_connector_after_detect(aconnector);
1935 drm_modeset_lock_all(dev);
1936 dm_restore_drm_connector_state(dev, connector);
1937 drm_modeset_unlock_all(dev);
1939 if (aconnector->base.force == DRM_FORCE_UNSPECIFIED)
1940 drm_kms_helper_hotplug_event(dev);
1942 mutex_unlock(&aconnector->hpd_lock);
1946 static void dm_handle_hpd_rx_irq(struct amdgpu_dm_connector *aconnector)
1948 uint8_t esi[DP_PSR_ERROR_STATUS - DP_SINK_COUNT_ESI] = { 0 };
1950 bool new_irq_handled = false;
1952 int dpcd_bytes_to_read;
1954 const int max_process_count = 30;
1955 int process_count = 0;
1957 const struct dc_link_status *link_status = dc_link_get_status(aconnector->dc_link);
1959 if (link_status->dpcd_caps->dpcd_rev.raw < 0x12) {
1960 dpcd_bytes_to_read = DP_LANE0_1_STATUS - DP_SINK_COUNT;
1961 /* DPCD 0x200 - 0x201 for downstream IRQ */
1962 dpcd_addr = DP_SINK_COUNT;
1964 dpcd_bytes_to_read = DP_PSR_ERROR_STATUS - DP_SINK_COUNT_ESI;
1965 /* DPCD 0x2002 - 0x2005 for downstream IRQ */
1966 dpcd_addr = DP_SINK_COUNT_ESI;
1969 dret = drm_dp_dpcd_read(
1970 &aconnector->dm_dp_aux.aux,
1973 dpcd_bytes_to_read);
1975 while (dret == dpcd_bytes_to_read &&
1976 process_count < max_process_count) {
1982 DRM_DEBUG_DRIVER("ESI %02x %02x %02x\n", esi[0], esi[1], esi[2]);
1983 /* handle HPD short pulse irq */
1984 if (aconnector->mst_mgr.mst_state)
1986 &aconnector->mst_mgr,
1990 if (new_irq_handled) {
1991 /* ACK at DPCD to notify down stream */
1992 const int ack_dpcd_bytes_to_write =
1993 dpcd_bytes_to_read - 1;
1995 for (retry = 0; retry < 3; retry++) {
1998 wret = drm_dp_dpcd_write(
1999 &aconnector->dm_dp_aux.aux,
2002 ack_dpcd_bytes_to_write);
2003 if (wret == ack_dpcd_bytes_to_write)
2007 /* check if there is new irq to be handled */
2008 dret = drm_dp_dpcd_read(
2009 &aconnector->dm_dp_aux.aux,
2012 dpcd_bytes_to_read);
2014 new_irq_handled = false;
2020 if (process_count == max_process_count)
2021 DRM_DEBUG_DRIVER("Loop exceeded max iterations\n");
2024 static void handle_hpd_rx_irq(void *param)
2026 struct amdgpu_dm_connector *aconnector = (struct amdgpu_dm_connector *)param;
2027 struct drm_connector *connector = &aconnector->base;
2028 struct drm_device *dev = connector->dev;
2029 struct dc_link *dc_link = aconnector->dc_link;
2030 bool is_mst_root_connector = aconnector->mst_mgr.mst_state;
2031 enum dc_connection_type new_connection_type = dc_connection_none;
2032 #ifdef CONFIG_DRM_AMD_DC_HDCP
2033 union hpd_irq_data hpd_irq_data;
2034 struct amdgpu_device *adev = dev->dev_private;
2036 memset(&hpd_irq_data, 0, sizeof(hpd_irq_data));
2040 * TODO:Temporary add mutex to protect hpd interrupt not have a gpio
2041 * conflict, after implement i2c helper, this mutex should be
2044 if (dc_link->type != dc_connection_mst_branch)
2045 mutex_lock(&aconnector->hpd_lock);
2048 #ifdef CONFIG_DRM_AMD_DC_HDCP
2049 if (dc_link_handle_hpd_rx_irq(dc_link, &hpd_irq_data, NULL) &&
2051 if (dc_link_handle_hpd_rx_irq(dc_link, NULL, NULL) &&
2053 !is_mst_root_connector) {
2054 /* Downstream Port status changed. */
2055 if (!dc_link_detect_sink(dc_link, &new_connection_type))
2056 DRM_ERROR("KMS: Failed to detect connector\n");
2058 if (aconnector->base.force && new_connection_type == dc_connection_none) {
2059 emulated_link_detect(dc_link);
2061 if (aconnector->fake_enable)
2062 aconnector->fake_enable = false;
2064 amdgpu_dm_update_connector_after_detect(aconnector);
2067 drm_modeset_lock_all(dev);
2068 dm_restore_drm_connector_state(dev, connector);
2069 drm_modeset_unlock_all(dev);
2071 drm_kms_helper_hotplug_event(dev);
2072 } else if (dc_link_detect(dc_link, DETECT_REASON_HPDRX)) {
2074 if (aconnector->fake_enable)
2075 aconnector->fake_enable = false;
2077 amdgpu_dm_update_connector_after_detect(aconnector);
2080 drm_modeset_lock_all(dev);
2081 dm_restore_drm_connector_state(dev, connector);
2082 drm_modeset_unlock_all(dev);
2084 drm_kms_helper_hotplug_event(dev);
2087 #ifdef CONFIG_DRM_AMD_DC_HDCP
2088 if (hpd_irq_data.bytes.device_service_irq.bits.CP_IRQ)
2089 hdcp_handle_cpirq(adev->dm.hdcp_workqueue, aconnector->base.index);
2091 if ((dc_link->cur_link_settings.lane_count != LANE_COUNT_UNKNOWN) ||
2092 (dc_link->type == dc_connection_mst_branch))
2093 dm_handle_hpd_rx_irq(aconnector);
2095 if (dc_link->type != dc_connection_mst_branch) {
2096 drm_dp_cec_irq(&aconnector->dm_dp_aux.aux);
2097 mutex_unlock(&aconnector->hpd_lock);
2101 static void register_hpd_handlers(struct amdgpu_device *adev)
2103 struct drm_device *dev = adev->ddev;
2104 struct drm_connector *connector;
2105 struct amdgpu_dm_connector *aconnector;
2106 const struct dc_link *dc_link;
2107 struct dc_interrupt_params int_params = {0};
2109 int_params.requested_polarity = INTERRUPT_POLARITY_DEFAULT;
2110 int_params.current_polarity = INTERRUPT_POLARITY_DEFAULT;
2112 list_for_each_entry(connector,
2113 &dev->mode_config.connector_list, head) {
2115 aconnector = to_amdgpu_dm_connector(connector);
2116 dc_link = aconnector->dc_link;
2118 if (DC_IRQ_SOURCE_INVALID != dc_link->irq_source_hpd) {
2119 int_params.int_context = INTERRUPT_LOW_IRQ_CONTEXT;
2120 int_params.irq_source = dc_link->irq_source_hpd;
2122 amdgpu_dm_irq_register_interrupt(adev, &int_params,
2124 (void *) aconnector);
2127 if (DC_IRQ_SOURCE_INVALID != dc_link->irq_source_hpd_rx) {
2129 /* Also register for DP short pulse (hpd_rx). */
2130 int_params.int_context = INTERRUPT_LOW_IRQ_CONTEXT;
2131 int_params.irq_source = dc_link->irq_source_hpd_rx;
2133 amdgpu_dm_irq_register_interrupt(adev, &int_params,
2135 (void *) aconnector);
2140 /* Register IRQ sources and initialize IRQ callbacks */
2141 static int dce110_register_irq_handlers(struct amdgpu_device *adev)
2143 struct dc *dc = adev->dm.dc;
2144 struct common_irq_params *c_irq_params;
2145 struct dc_interrupt_params int_params = {0};
2148 unsigned client_id = AMDGPU_IRQ_CLIENTID_LEGACY;
2150 if (adev->asic_type >= CHIP_VEGA10)
2151 client_id = SOC15_IH_CLIENTID_DCE;
2153 int_params.requested_polarity = INTERRUPT_POLARITY_DEFAULT;
2154 int_params.current_polarity = INTERRUPT_POLARITY_DEFAULT;
2157 * Actions of amdgpu_irq_add_id():
2158 * 1. Register a set() function with base driver.
2159 * Base driver will call set() function to enable/disable an
2160 * interrupt in DC hardware.
2161 * 2. Register amdgpu_dm_irq_handler().
2162 * Base driver will call amdgpu_dm_irq_handler() for ALL interrupts
2163 * coming from DC hardware.
2164 * amdgpu_dm_irq_handler() will re-direct the interrupt to DC
2165 * for acknowledging and handling. */
2167 /* Use VBLANK interrupt */
2168 for (i = VISLANDS30_IV_SRCID_D1_VERTICAL_INTERRUPT0; i <= VISLANDS30_IV_SRCID_D6_VERTICAL_INTERRUPT0; i++) {
2169 r = amdgpu_irq_add_id(adev, client_id, i, &adev->crtc_irq);
2171 DRM_ERROR("Failed to add crtc irq id!\n");
2175 int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT;
2176 int_params.irq_source =
2177 dc_interrupt_to_irq_source(dc, i, 0);
2179 c_irq_params = &adev->dm.vblank_params[int_params.irq_source - DC_IRQ_SOURCE_VBLANK1];
2181 c_irq_params->adev = adev;
2182 c_irq_params->irq_src = int_params.irq_source;
2184 amdgpu_dm_irq_register_interrupt(adev, &int_params,
2185 dm_crtc_high_irq, c_irq_params);
2188 /* Use VUPDATE interrupt */
2189 for (i = VISLANDS30_IV_SRCID_D1_V_UPDATE_INT; i <= VISLANDS30_IV_SRCID_D6_V_UPDATE_INT; i += 2) {
2190 r = amdgpu_irq_add_id(adev, client_id, i, &adev->vupdate_irq);
2192 DRM_ERROR("Failed to add vupdate irq id!\n");
2196 int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT;
2197 int_params.irq_source =
2198 dc_interrupt_to_irq_source(dc, i, 0);
2200 c_irq_params = &adev->dm.vupdate_params[int_params.irq_source - DC_IRQ_SOURCE_VUPDATE1];
2202 c_irq_params->adev = adev;
2203 c_irq_params->irq_src = int_params.irq_source;
2205 amdgpu_dm_irq_register_interrupt(adev, &int_params,
2206 dm_vupdate_high_irq, c_irq_params);
2209 /* Use GRPH_PFLIP interrupt */
2210 for (i = VISLANDS30_IV_SRCID_D1_GRPH_PFLIP;
2211 i <= VISLANDS30_IV_SRCID_D6_GRPH_PFLIP; i += 2) {
2212 r = amdgpu_irq_add_id(adev, client_id, i, &adev->pageflip_irq);
2214 DRM_ERROR("Failed to add page flip irq id!\n");
2218 int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT;
2219 int_params.irq_source =
2220 dc_interrupt_to_irq_source(dc, i, 0);
2222 c_irq_params = &adev->dm.pflip_params[int_params.irq_source - DC_IRQ_SOURCE_PFLIP_FIRST];
2224 c_irq_params->adev = adev;
2225 c_irq_params->irq_src = int_params.irq_source;
2227 amdgpu_dm_irq_register_interrupt(adev, &int_params,
2228 dm_pflip_high_irq, c_irq_params);
2233 r = amdgpu_irq_add_id(adev, client_id,
2234 VISLANDS30_IV_SRCID_HOTPLUG_DETECT_A, &adev->hpd_irq);
2236 DRM_ERROR("Failed to add hpd irq id!\n");
2240 register_hpd_handlers(adev);
2245 #if defined(CONFIG_DRM_AMD_DC_DCN)
2246 /* Register IRQ sources and initialize IRQ callbacks */
2247 static int dcn10_register_irq_handlers(struct amdgpu_device *adev)
2249 struct dc *dc = adev->dm.dc;
2250 struct common_irq_params *c_irq_params;
2251 struct dc_interrupt_params int_params = {0};
2255 int_params.requested_polarity = INTERRUPT_POLARITY_DEFAULT;
2256 int_params.current_polarity = INTERRUPT_POLARITY_DEFAULT;
2259 * Actions of amdgpu_irq_add_id():
2260 * 1. Register a set() function with base driver.
2261 * Base driver will call set() function to enable/disable an
2262 * interrupt in DC hardware.
2263 * 2. Register amdgpu_dm_irq_handler().
2264 * Base driver will call amdgpu_dm_irq_handler() for ALL interrupts
2265 * coming from DC hardware.
2266 * amdgpu_dm_irq_handler() will re-direct the interrupt to DC
2267 * for acknowledging and handling.
2270 /* Use VSTARTUP interrupt */
2271 for (i = DCN_1_0__SRCID__DC_D1_OTG_VSTARTUP;
2272 i <= DCN_1_0__SRCID__DC_D1_OTG_VSTARTUP + adev->mode_info.num_crtc - 1;
2274 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_DCE, i, &adev->crtc_irq);
2277 DRM_ERROR("Failed to add crtc irq id!\n");
2281 int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT;
2282 int_params.irq_source =
2283 dc_interrupt_to_irq_source(dc, i, 0);
2285 c_irq_params = &adev->dm.vblank_params[int_params.irq_source - DC_IRQ_SOURCE_VBLANK1];
2287 c_irq_params->adev = adev;
2288 c_irq_params->irq_src = int_params.irq_source;
2290 amdgpu_dm_irq_register_interrupt(adev, &int_params,
2291 dm_dcn_crtc_high_irq, c_irq_params);
2294 /* Use GRPH_PFLIP interrupt */
2295 for (i = DCN_1_0__SRCID__HUBP0_FLIP_INTERRUPT;
2296 i <= DCN_1_0__SRCID__HUBP0_FLIP_INTERRUPT + adev->mode_info.num_crtc - 1;
2298 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_DCE, i, &adev->pageflip_irq);
2300 DRM_ERROR("Failed to add page flip irq id!\n");
2304 int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT;
2305 int_params.irq_source =
2306 dc_interrupt_to_irq_source(dc, i, 0);
2308 c_irq_params = &adev->dm.pflip_params[int_params.irq_source - DC_IRQ_SOURCE_PFLIP_FIRST];
2310 c_irq_params->adev = adev;
2311 c_irq_params->irq_src = int_params.irq_source;
2313 amdgpu_dm_irq_register_interrupt(adev, &int_params,
2314 dm_pflip_high_irq, c_irq_params);
2319 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_DCE, DCN_1_0__SRCID__DC_HPD1_INT,
2322 DRM_ERROR("Failed to add hpd irq id!\n");
2326 register_hpd_handlers(adev);
2333 * Acquires the lock for the atomic state object and returns
2334 * the new atomic state.
2336 * This should only be called during atomic check.
2338 static int dm_atomic_get_state(struct drm_atomic_state *state,
2339 struct dm_atomic_state **dm_state)
2341 struct drm_device *dev = state->dev;
2342 struct amdgpu_device *adev = dev->dev_private;
2343 struct amdgpu_display_manager *dm = &adev->dm;
2344 struct drm_private_state *priv_state;
2349 priv_state = drm_atomic_get_private_obj_state(state, &dm->atomic_obj);
2350 if (IS_ERR(priv_state))
2351 return PTR_ERR(priv_state);
2353 *dm_state = to_dm_atomic_state(priv_state);
2358 struct dm_atomic_state *
2359 dm_atomic_get_new_state(struct drm_atomic_state *state)
2361 struct drm_device *dev = state->dev;
2362 struct amdgpu_device *adev = dev->dev_private;
2363 struct amdgpu_display_manager *dm = &adev->dm;
2364 struct drm_private_obj *obj;
2365 struct drm_private_state *new_obj_state;
2368 for_each_new_private_obj_in_state(state, obj, new_obj_state, i) {
2369 if (obj->funcs == dm->atomic_obj.funcs)
2370 return to_dm_atomic_state(new_obj_state);
2376 struct dm_atomic_state *
2377 dm_atomic_get_old_state(struct drm_atomic_state *state)
2379 struct drm_device *dev = state->dev;
2380 struct amdgpu_device *adev = dev->dev_private;
2381 struct amdgpu_display_manager *dm = &adev->dm;
2382 struct drm_private_obj *obj;
2383 struct drm_private_state *old_obj_state;
2386 for_each_old_private_obj_in_state(state, obj, old_obj_state, i) {
2387 if (obj->funcs == dm->atomic_obj.funcs)
2388 return to_dm_atomic_state(old_obj_state);
2394 static struct drm_private_state *
2395 dm_atomic_duplicate_state(struct drm_private_obj *obj)
2397 struct dm_atomic_state *old_state, *new_state;
2399 new_state = kzalloc(sizeof(*new_state), GFP_KERNEL);
2403 __drm_atomic_helper_private_obj_duplicate_state(obj, &new_state->base);
2405 old_state = to_dm_atomic_state(obj->state);
2407 if (old_state && old_state->context)
2408 new_state->context = dc_copy_state(old_state->context);
2410 if (!new_state->context) {
2415 return &new_state->base;
2418 static void dm_atomic_destroy_state(struct drm_private_obj *obj,
2419 struct drm_private_state *state)
2421 struct dm_atomic_state *dm_state = to_dm_atomic_state(state);
2423 if (dm_state && dm_state->context)
2424 dc_release_state(dm_state->context);
2429 static struct drm_private_state_funcs dm_atomic_state_funcs = {
2430 .atomic_duplicate_state = dm_atomic_duplicate_state,
2431 .atomic_destroy_state = dm_atomic_destroy_state,
2434 static int amdgpu_dm_mode_config_init(struct amdgpu_device *adev)
2436 struct dm_atomic_state *state;
2439 adev->mode_info.mode_config_initialized = true;
2441 adev->ddev->mode_config.funcs = (void *)&amdgpu_dm_mode_funcs;
2442 adev->ddev->mode_config.helper_private = &amdgpu_dm_mode_config_helperfuncs;
2444 adev->ddev->mode_config.max_width = 16384;
2445 adev->ddev->mode_config.max_height = 16384;
2447 adev->ddev->mode_config.preferred_depth = 24;
2448 adev->ddev->mode_config.prefer_shadow = 1;
2449 /* indicates support for immediate flip */
2450 adev->ddev->mode_config.async_page_flip = true;
2452 adev->ddev->mode_config.fb_base = adev->gmc.aper_base;
2454 state = kzalloc(sizeof(*state), GFP_KERNEL);
2458 state->context = dc_create_state(adev->dm.dc);
2459 if (!state->context) {
2464 dc_resource_state_copy_construct_current(adev->dm.dc, state->context);
2466 drm_atomic_private_obj_init(adev->ddev,
2467 &adev->dm.atomic_obj,
2469 &dm_atomic_state_funcs);
2471 r = amdgpu_display_modeset_create_props(adev);
2475 r = amdgpu_dm_audio_init(adev);
2482 #define AMDGPU_DM_DEFAULT_MIN_BACKLIGHT 12
2483 #define AMDGPU_DM_DEFAULT_MAX_BACKLIGHT 255
2485 #if defined(CONFIG_BACKLIGHT_CLASS_DEVICE) ||\
2486 defined(CONFIG_BACKLIGHT_CLASS_DEVICE_MODULE)
2488 static void amdgpu_dm_update_backlight_caps(struct amdgpu_display_manager *dm)
2490 #if defined(CONFIG_ACPI)
2491 struct amdgpu_dm_backlight_caps caps;
2493 if (dm->backlight_caps.caps_valid)
2496 amdgpu_acpi_get_backlight_caps(dm->adev, &caps);
2497 if (caps.caps_valid) {
2498 dm->backlight_caps.min_input_signal = caps.min_input_signal;
2499 dm->backlight_caps.max_input_signal = caps.max_input_signal;
2500 dm->backlight_caps.caps_valid = true;
2502 dm->backlight_caps.min_input_signal =
2503 AMDGPU_DM_DEFAULT_MIN_BACKLIGHT;
2504 dm->backlight_caps.max_input_signal =
2505 AMDGPU_DM_DEFAULT_MAX_BACKLIGHT;
2508 dm->backlight_caps.min_input_signal = AMDGPU_DM_DEFAULT_MIN_BACKLIGHT;
2509 dm->backlight_caps.max_input_signal = AMDGPU_DM_DEFAULT_MAX_BACKLIGHT;
2513 static int amdgpu_dm_backlight_update_status(struct backlight_device *bd)
2515 struct amdgpu_display_manager *dm = bl_get_data(bd);
2516 struct amdgpu_dm_backlight_caps caps;
2517 uint32_t brightness = bd->props.brightness;
2519 amdgpu_dm_update_backlight_caps(dm);
2520 caps = dm->backlight_caps;
2522 * The brightness input is in the range 0-255
2523 * It needs to be rescaled to be between the
2524 * requested min and max input signal
2526 * It also needs to be scaled up by 0x101 to
2527 * match the DC interface which has a range of
2533 * (caps.max_input_signal - caps.min_input_signal)
2534 / AMDGPU_MAX_BL_LEVEL
2535 + caps.min_input_signal * 0x101;
2537 if (dc_link_set_backlight_level(dm->backlight_link,
2544 static int amdgpu_dm_backlight_get_brightness(struct backlight_device *bd)
2546 struct amdgpu_display_manager *dm = bl_get_data(bd);
2547 int ret = dc_link_get_backlight_level(dm->backlight_link);
2549 if (ret == DC_ERROR_UNEXPECTED)
2550 return bd->props.brightness;
2554 static const struct backlight_ops amdgpu_dm_backlight_ops = {
2555 .options = BL_CORE_SUSPENDRESUME,
2556 .get_brightness = amdgpu_dm_backlight_get_brightness,
2557 .update_status = amdgpu_dm_backlight_update_status,
2561 amdgpu_dm_register_backlight_device(struct amdgpu_display_manager *dm)
2564 struct backlight_properties props = { 0 };
2566 amdgpu_dm_update_backlight_caps(dm);
2568 props.max_brightness = AMDGPU_MAX_BL_LEVEL;
2569 props.brightness = AMDGPU_MAX_BL_LEVEL;
2570 props.type = BACKLIGHT_RAW;
2572 snprintf(bl_name, sizeof(bl_name), "amdgpu_bl%d",
2573 dm->adev->ddev->primary->index);
2575 dm->backlight_dev = backlight_device_register(bl_name,
2576 dm->adev->ddev->dev,
2578 &amdgpu_dm_backlight_ops,
2581 if (IS_ERR(dm->backlight_dev))
2582 DRM_ERROR("DM: Backlight registration failed!\n");
2584 DRM_DEBUG_DRIVER("DM: Registered Backlight device: %s\n", bl_name);
2589 static int initialize_plane(struct amdgpu_display_manager *dm,
2590 struct amdgpu_mode_info *mode_info, int plane_id,
2591 enum drm_plane_type plane_type,
2592 const struct dc_plane_cap *plane_cap)
2594 struct drm_plane *plane;
2595 unsigned long possible_crtcs;
2598 plane = kzalloc(sizeof(struct drm_plane), GFP_KERNEL);
2600 DRM_ERROR("KMS: Failed to allocate plane\n");
2603 plane->type = plane_type;
2606 * HACK: IGT tests expect that the primary plane for a CRTC
2607 * can only have one possible CRTC. Only expose support for
2608 * any CRTC if they're not going to be used as a primary plane
2609 * for a CRTC - like overlay or underlay planes.
2611 possible_crtcs = 1 << plane_id;
2612 if (plane_id >= dm->dc->caps.max_streams)
2613 possible_crtcs = 0xff;
2615 ret = amdgpu_dm_plane_init(dm, plane, possible_crtcs, plane_cap);
2618 DRM_ERROR("KMS: Failed to initialize plane\n");
2624 mode_info->planes[plane_id] = plane;
2630 static void register_backlight_device(struct amdgpu_display_manager *dm,
2631 struct dc_link *link)
2633 #if defined(CONFIG_BACKLIGHT_CLASS_DEVICE) ||\
2634 defined(CONFIG_BACKLIGHT_CLASS_DEVICE_MODULE)
2636 if ((link->connector_signal & (SIGNAL_TYPE_EDP | SIGNAL_TYPE_LVDS)) &&
2637 link->type != dc_connection_none) {
2639 * Event if registration failed, we should continue with
2640 * DM initialization because not having a backlight control
2641 * is better then a black screen.
2643 amdgpu_dm_register_backlight_device(dm);
2645 if (dm->backlight_dev)
2646 dm->backlight_link = link;
2653 * In this architecture, the association
2654 * connector -> encoder -> crtc
2655 * id not really requried. The crtc and connector will hold the
2656 * display_index as an abstraction to use with DAL component
2658 * Returns 0 on success
2660 static int amdgpu_dm_initialize_drm_device(struct amdgpu_device *adev)
2662 struct amdgpu_display_manager *dm = &adev->dm;
2664 struct amdgpu_dm_connector *aconnector = NULL;
2665 struct amdgpu_encoder *aencoder = NULL;
2666 struct amdgpu_mode_info *mode_info = &adev->mode_info;
2668 int32_t primary_planes;
2669 enum dc_connection_type new_connection_type = dc_connection_none;
2670 const struct dc_plane_cap *plane;
2672 link_cnt = dm->dc->caps.max_links;
2673 if (amdgpu_dm_mode_config_init(dm->adev)) {
2674 DRM_ERROR("DM: Failed to initialize mode config\n");
2678 /* There is one primary plane per CRTC */
2679 primary_planes = dm->dc->caps.max_streams;
2680 ASSERT(primary_planes <= AMDGPU_MAX_PLANES);
2683 * Initialize primary planes, implicit planes for legacy IOCTLS.
2684 * Order is reversed to match iteration order in atomic check.
2686 for (i = (primary_planes - 1); i >= 0; i--) {
2687 plane = &dm->dc->caps.planes[i];
2689 if (initialize_plane(dm, mode_info, i,
2690 DRM_PLANE_TYPE_PRIMARY, plane)) {
2691 DRM_ERROR("KMS: Failed to initialize primary plane\n");
2697 * Initialize overlay planes, index starting after primary planes.
2698 * These planes have a higher DRM index than the primary planes since
2699 * they should be considered as having a higher z-order.
2700 * Order is reversed to match iteration order in atomic check.
2702 * Only support DCN for now, and only expose one so we don't encourage
2703 * userspace to use up all the pipes.
2705 for (i = 0; i < dm->dc->caps.max_planes; ++i) {
2706 struct dc_plane_cap *plane = &dm->dc->caps.planes[i];
2708 if (plane->type != DC_PLANE_TYPE_DCN_UNIVERSAL)
2711 if (!plane->blends_with_above || !plane->blends_with_below)
2714 if (!plane->pixel_format_support.argb8888)
2717 if (initialize_plane(dm, NULL, primary_planes + i,
2718 DRM_PLANE_TYPE_OVERLAY, plane)) {
2719 DRM_ERROR("KMS: Failed to initialize overlay plane\n");
2723 /* Only create one overlay plane. */
2727 for (i = 0; i < dm->dc->caps.max_streams; i++)
2728 if (amdgpu_dm_crtc_init(dm, mode_info->planes[i], i)) {
2729 DRM_ERROR("KMS: Failed to initialize crtc\n");
2733 dm->display_indexes_num = dm->dc->caps.max_streams;
2735 /* loops over all connectors on the board */
2736 for (i = 0; i < link_cnt; i++) {
2737 struct dc_link *link = NULL;
2739 if (i > AMDGPU_DM_MAX_DISPLAY_INDEX) {
2741 "KMS: Cannot support more than %d display indexes\n",
2742 AMDGPU_DM_MAX_DISPLAY_INDEX);
2746 aconnector = kzalloc(sizeof(*aconnector), GFP_KERNEL);
2750 aencoder = kzalloc(sizeof(*aencoder), GFP_KERNEL);
2754 if (amdgpu_dm_encoder_init(dm->ddev, aencoder, i)) {
2755 DRM_ERROR("KMS: Failed to initialize encoder\n");
2759 if (amdgpu_dm_connector_init(dm, aconnector, i, aencoder)) {
2760 DRM_ERROR("KMS: Failed to initialize connector\n");
2764 link = dc_get_link_at_index(dm->dc, i);
2766 if (!dc_link_detect_sink(link, &new_connection_type))
2767 DRM_ERROR("KMS: Failed to detect connector\n");
2769 if (aconnector->base.force && new_connection_type == dc_connection_none) {
2770 emulated_link_detect(link);
2771 amdgpu_dm_update_connector_after_detect(aconnector);
2773 } else if (dc_link_detect(link, DETECT_REASON_BOOT)) {
2774 amdgpu_dm_update_connector_after_detect(aconnector);
2775 register_backlight_device(dm, link);
2776 if (amdgpu_dc_feature_mask & DC_PSR_MASK)
2777 amdgpu_dm_set_psr_caps(link);
2783 /* Software is initialized. Now we can register interrupt handlers. */
2784 switch (adev->asic_type) {
2794 case CHIP_POLARIS11:
2795 case CHIP_POLARIS10:
2796 case CHIP_POLARIS12:
2801 if (dce110_register_irq_handlers(dm->adev)) {
2802 DRM_ERROR("DM: Failed to initialize IRQ\n");
2806 #if defined(CONFIG_DRM_AMD_DC_DCN)
2812 if (dcn10_register_irq_handlers(dm->adev)) {
2813 DRM_ERROR("DM: Failed to initialize IRQ\n");
2819 DRM_ERROR("Unsupported ASIC type: 0x%X\n", adev->asic_type);
2823 if (adev->asic_type != CHIP_CARRIZO && adev->asic_type != CHIP_STONEY)
2824 dm->dc->debug.disable_stutter = amdgpu_pp_feature_mask & PP_STUTTER_MODE ? false : true;
2834 static void amdgpu_dm_destroy_drm_device(struct amdgpu_display_manager *dm)
2836 drm_mode_config_cleanup(dm->ddev);
2837 drm_atomic_private_obj_fini(&dm->atomic_obj);
2841 /******************************************************************************
2842 * amdgpu_display_funcs functions
2843 *****************************************************************************/
2846 * dm_bandwidth_update - program display watermarks
2848 * @adev: amdgpu_device pointer
2850 * Calculate and program the display watermarks and line buffer allocation.
2852 static void dm_bandwidth_update(struct amdgpu_device *adev)
2854 /* TODO: implement later */
2857 static const struct amdgpu_display_funcs dm_display_funcs = {
2858 .bandwidth_update = dm_bandwidth_update, /* called unconditionally */
2859 .vblank_get_counter = dm_vblank_get_counter,/* called unconditionally */
2860 .backlight_set_level = NULL, /* never called for DC */
2861 .backlight_get_level = NULL, /* never called for DC */
2862 .hpd_sense = NULL,/* called unconditionally */
2863 .hpd_set_polarity = NULL, /* called unconditionally */
2864 .hpd_get_gpio_reg = NULL, /* VBIOS parsing. DAL does it. */
2865 .page_flip_get_scanoutpos =
2866 dm_crtc_get_scanoutpos,/* called unconditionally */
2867 .add_encoder = NULL, /* VBIOS parsing. DAL does it. */
2868 .add_connector = NULL, /* VBIOS parsing. DAL does it. */
2871 #if defined(CONFIG_DEBUG_KERNEL_DC)
2873 static ssize_t s3_debug_store(struct device *device,
2874 struct device_attribute *attr,
2880 struct drm_device *drm_dev = dev_get_drvdata(device);
2881 struct amdgpu_device *adev = drm_dev->dev_private;
2883 ret = kstrtoint(buf, 0, &s3_state);
2888 drm_kms_helper_hotplug_event(adev->ddev);
2893 return ret == 0 ? count : 0;
2896 DEVICE_ATTR_WO(s3_debug);
2900 static int dm_early_init(void *handle)
2902 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2904 switch (adev->asic_type) {
2907 adev->mode_info.num_crtc = 6;
2908 adev->mode_info.num_hpd = 6;
2909 adev->mode_info.num_dig = 6;
2912 adev->mode_info.num_crtc = 4;
2913 adev->mode_info.num_hpd = 6;
2914 adev->mode_info.num_dig = 7;
2918 adev->mode_info.num_crtc = 2;
2919 adev->mode_info.num_hpd = 6;
2920 adev->mode_info.num_dig = 6;
2924 adev->mode_info.num_crtc = 6;
2925 adev->mode_info.num_hpd = 6;
2926 adev->mode_info.num_dig = 7;
2929 adev->mode_info.num_crtc = 3;
2930 adev->mode_info.num_hpd = 6;
2931 adev->mode_info.num_dig = 9;
2934 adev->mode_info.num_crtc = 2;
2935 adev->mode_info.num_hpd = 6;
2936 adev->mode_info.num_dig = 9;
2938 case CHIP_POLARIS11:
2939 case CHIP_POLARIS12:
2940 adev->mode_info.num_crtc = 5;
2941 adev->mode_info.num_hpd = 5;
2942 adev->mode_info.num_dig = 5;
2944 case CHIP_POLARIS10:
2946 adev->mode_info.num_crtc = 6;
2947 adev->mode_info.num_hpd = 6;
2948 adev->mode_info.num_dig = 6;
2953 adev->mode_info.num_crtc = 6;
2954 adev->mode_info.num_hpd = 6;
2955 adev->mode_info.num_dig = 6;
2957 #if defined(CONFIG_DRM_AMD_DC_DCN)
2959 adev->mode_info.num_crtc = 4;
2960 adev->mode_info.num_hpd = 4;
2961 adev->mode_info.num_dig = 4;
2966 adev->mode_info.num_crtc = 6;
2967 adev->mode_info.num_hpd = 6;
2968 adev->mode_info.num_dig = 6;
2971 adev->mode_info.num_crtc = 5;
2972 adev->mode_info.num_hpd = 5;
2973 adev->mode_info.num_dig = 5;
2976 adev->mode_info.num_crtc = 4;
2977 adev->mode_info.num_hpd = 4;
2978 adev->mode_info.num_dig = 4;
2981 DRM_ERROR("Unsupported ASIC type: 0x%X\n", adev->asic_type);
2985 amdgpu_dm_set_irq_funcs(adev);
2987 if (adev->mode_info.funcs == NULL)
2988 adev->mode_info.funcs = &dm_display_funcs;
2991 * Note: Do NOT change adev->audio_endpt_rreg and
2992 * adev->audio_endpt_wreg because they are initialised in
2993 * amdgpu_device_init()
2995 #if defined(CONFIG_DEBUG_KERNEL_DC)
2998 &dev_attr_s3_debug);
3004 static bool modeset_required(struct drm_crtc_state *crtc_state,
3005 struct dc_stream_state *new_stream,
3006 struct dc_stream_state *old_stream)
3008 if (!drm_atomic_crtc_needs_modeset(crtc_state))
3011 if (!crtc_state->enable)
3014 return crtc_state->active;
3017 static bool modereset_required(struct drm_crtc_state *crtc_state)
3019 if (!drm_atomic_crtc_needs_modeset(crtc_state))
3022 return !crtc_state->enable || !crtc_state->active;
3025 static void amdgpu_dm_encoder_destroy(struct drm_encoder *encoder)
3027 drm_encoder_cleanup(encoder);
3031 static const struct drm_encoder_funcs amdgpu_dm_encoder_funcs = {
3032 .destroy = amdgpu_dm_encoder_destroy,
3036 static int fill_dc_scaling_info(const struct drm_plane_state *state,
3037 struct dc_scaling_info *scaling_info)
3039 int scale_w, scale_h;
3041 memset(scaling_info, 0, sizeof(*scaling_info));
3043 /* Source is fixed 16.16 but we ignore mantissa for now... */
3044 scaling_info->src_rect.x = state->src_x >> 16;
3045 scaling_info->src_rect.y = state->src_y >> 16;
3047 scaling_info->src_rect.width = state->src_w >> 16;
3048 if (scaling_info->src_rect.width == 0)
3051 scaling_info->src_rect.height = state->src_h >> 16;
3052 if (scaling_info->src_rect.height == 0)
3055 scaling_info->dst_rect.x = state->crtc_x;
3056 scaling_info->dst_rect.y = state->crtc_y;
3058 if (state->crtc_w == 0)
3061 scaling_info->dst_rect.width = state->crtc_w;
3063 if (state->crtc_h == 0)
3066 scaling_info->dst_rect.height = state->crtc_h;
3068 /* DRM doesn't specify clipping on destination output. */
3069 scaling_info->clip_rect = scaling_info->dst_rect;
3071 /* TODO: Validate scaling per-format with DC plane caps */
3072 scale_w = scaling_info->dst_rect.width * 1000 /
3073 scaling_info->src_rect.width;
3075 if (scale_w < 250 || scale_w > 16000)
3078 scale_h = scaling_info->dst_rect.height * 1000 /
3079 scaling_info->src_rect.height;
3081 if (scale_h < 250 || scale_h > 16000)
3085 * The "scaling_quality" can be ignored for now, quality = 0 has DC
3086 * assume reasonable defaults based on the format.
3092 static int get_fb_info(const struct amdgpu_framebuffer *amdgpu_fb,
3093 uint64_t *tiling_flags)
3095 struct amdgpu_bo *rbo = gem_to_amdgpu_bo(amdgpu_fb->base.obj[0]);
3096 int r = amdgpu_bo_reserve(rbo, false);
3099 /* Don't show error message when returning -ERESTARTSYS */
3100 if (r != -ERESTARTSYS)
3101 DRM_ERROR("Unable to reserve buffer: %d\n", r);
3106 amdgpu_bo_get_tiling_flags(rbo, tiling_flags);
3108 amdgpu_bo_unreserve(rbo);
3113 static inline uint64_t get_dcc_address(uint64_t address, uint64_t tiling_flags)
3115 uint32_t offset = AMDGPU_TILING_GET(tiling_flags, DCC_OFFSET_256B);
3117 return offset ? (address + offset * 256) : 0;
3121 fill_plane_dcc_attributes(struct amdgpu_device *adev,
3122 const struct amdgpu_framebuffer *afb,
3123 const enum surface_pixel_format format,
3124 const enum dc_rotation_angle rotation,
3125 const struct plane_size *plane_size,
3126 const union dc_tiling_info *tiling_info,
3127 const uint64_t info,
3128 struct dc_plane_dcc_param *dcc,
3129 struct dc_plane_address *address)
3131 struct dc *dc = adev->dm.dc;
3132 struct dc_dcc_surface_param input;
3133 struct dc_surface_dcc_cap output;
3134 uint32_t offset = AMDGPU_TILING_GET(info, DCC_OFFSET_256B);
3135 uint32_t i64b = AMDGPU_TILING_GET(info, DCC_INDEPENDENT_64B) != 0;
3136 uint64_t dcc_address;
3138 memset(&input, 0, sizeof(input));
3139 memset(&output, 0, sizeof(output));
3144 if (format >= SURFACE_PIXEL_FORMAT_VIDEO_BEGIN)
3147 if (!dc->cap_funcs.get_dcc_compression_cap)
3150 input.format = format;
3151 input.surface_size.width = plane_size->surface_size.width;
3152 input.surface_size.height = plane_size->surface_size.height;
3153 input.swizzle_mode = tiling_info->gfx9.swizzle;
3155 if (rotation == ROTATION_ANGLE_0 || rotation == ROTATION_ANGLE_180)
3156 input.scan = SCAN_DIRECTION_HORIZONTAL;
3157 else if (rotation == ROTATION_ANGLE_90 || rotation == ROTATION_ANGLE_270)
3158 input.scan = SCAN_DIRECTION_VERTICAL;
3160 if (!dc->cap_funcs.get_dcc_compression_cap(dc, &input, &output))
3163 if (!output.capable)
3166 if (i64b == 0 && output.grph.rgb.independent_64b_blks != 0)
3171 AMDGPU_TILING_GET(info, DCC_PITCH_MAX) + 1;
3172 dcc->independent_64b_blks = i64b;
3174 dcc_address = get_dcc_address(afb->address, info);
3175 address->grph.meta_addr.low_part = lower_32_bits(dcc_address);
3176 address->grph.meta_addr.high_part = upper_32_bits(dcc_address);
3182 fill_plane_buffer_attributes(struct amdgpu_device *adev,
3183 const struct amdgpu_framebuffer *afb,
3184 const enum surface_pixel_format format,
3185 const enum dc_rotation_angle rotation,
3186 const uint64_t tiling_flags,
3187 union dc_tiling_info *tiling_info,
3188 struct plane_size *plane_size,
3189 struct dc_plane_dcc_param *dcc,
3190 struct dc_plane_address *address)
3192 const struct drm_framebuffer *fb = &afb->base;
3195 memset(tiling_info, 0, sizeof(*tiling_info));
3196 memset(plane_size, 0, sizeof(*plane_size));
3197 memset(dcc, 0, sizeof(*dcc));
3198 memset(address, 0, sizeof(*address));
3200 if (format < SURFACE_PIXEL_FORMAT_VIDEO_BEGIN) {
3201 plane_size->surface_size.x = 0;
3202 plane_size->surface_size.y = 0;
3203 plane_size->surface_size.width = fb->width;
3204 plane_size->surface_size.height = fb->height;
3205 plane_size->surface_pitch =
3206 fb->pitches[0] / fb->format->cpp[0];
3208 address->type = PLN_ADDR_TYPE_GRAPHICS;
3209 address->grph.addr.low_part = lower_32_bits(afb->address);
3210 address->grph.addr.high_part = upper_32_bits(afb->address);
3211 } else if (format < SURFACE_PIXEL_FORMAT_INVALID) {
3212 uint64_t chroma_addr = afb->address + fb->offsets[1];
3214 plane_size->surface_size.x = 0;
3215 plane_size->surface_size.y = 0;
3216 plane_size->surface_size.width = fb->width;
3217 plane_size->surface_size.height = fb->height;
3218 plane_size->surface_pitch =
3219 fb->pitches[0] / fb->format->cpp[0];
3221 plane_size->chroma_size.x = 0;
3222 plane_size->chroma_size.y = 0;
3223 /* TODO: set these based on surface format */
3224 plane_size->chroma_size.width = fb->width / 2;
3225 plane_size->chroma_size.height = fb->height / 2;
3227 plane_size->chroma_pitch =
3228 fb->pitches[1] / fb->format->cpp[1];
3230 address->type = PLN_ADDR_TYPE_VIDEO_PROGRESSIVE;
3231 address->video_progressive.luma_addr.low_part =
3232 lower_32_bits(afb->address);
3233 address->video_progressive.luma_addr.high_part =
3234 upper_32_bits(afb->address);
3235 address->video_progressive.chroma_addr.low_part =
3236 lower_32_bits(chroma_addr);
3237 address->video_progressive.chroma_addr.high_part =
3238 upper_32_bits(chroma_addr);
3241 /* Fill GFX8 params */
3242 if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE) == DC_ARRAY_2D_TILED_THIN1) {
3243 unsigned int bankw, bankh, mtaspect, tile_split, num_banks;
3245 bankw = AMDGPU_TILING_GET(tiling_flags, BANK_WIDTH);
3246 bankh = AMDGPU_TILING_GET(tiling_flags, BANK_HEIGHT);
3247 mtaspect = AMDGPU_TILING_GET(tiling_flags, MACRO_TILE_ASPECT);
3248 tile_split = AMDGPU_TILING_GET(tiling_flags, TILE_SPLIT);
3249 num_banks = AMDGPU_TILING_GET(tiling_flags, NUM_BANKS);
3251 /* XXX fix me for VI */
3252 tiling_info->gfx8.num_banks = num_banks;
3253 tiling_info->gfx8.array_mode =
3254 DC_ARRAY_2D_TILED_THIN1;
3255 tiling_info->gfx8.tile_split = tile_split;
3256 tiling_info->gfx8.bank_width = bankw;
3257 tiling_info->gfx8.bank_height = bankh;
3258 tiling_info->gfx8.tile_aspect = mtaspect;
3259 tiling_info->gfx8.tile_mode =
3260 DC_ADDR_SURF_MICRO_TILING_DISPLAY;
3261 } else if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE)
3262 == DC_ARRAY_1D_TILED_THIN1) {
3263 tiling_info->gfx8.array_mode = DC_ARRAY_1D_TILED_THIN1;
3266 tiling_info->gfx8.pipe_config =
3267 AMDGPU_TILING_GET(tiling_flags, PIPE_CONFIG);
3269 if (adev->asic_type == CHIP_VEGA10 ||
3270 adev->asic_type == CHIP_VEGA12 ||
3271 adev->asic_type == CHIP_VEGA20 ||
3272 adev->asic_type == CHIP_NAVI10 ||
3273 adev->asic_type == CHIP_NAVI14 ||
3274 adev->asic_type == CHIP_NAVI12 ||
3275 adev->asic_type == CHIP_RENOIR ||
3276 adev->asic_type == CHIP_RAVEN) {
3277 /* Fill GFX9 params */
3278 tiling_info->gfx9.num_pipes =
3279 adev->gfx.config.gb_addr_config_fields.num_pipes;
3280 tiling_info->gfx9.num_banks =
3281 adev->gfx.config.gb_addr_config_fields.num_banks;
3282 tiling_info->gfx9.pipe_interleave =
3283 adev->gfx.config.gb_addr_config_fields.pipe_interleave_size;
3284 tiling_info->gfx9.num_shader_engines =
3285 adev->gfx.config.gb_addr_config_fields.num_se;
3286 tiling_info->gfx9.max_compressed_frags =
3287 adev->gfx.config.gb_addr_config_fields.max_compress_frags;
3288 tiling_info->gfx9.num_rb_per_se =
3289 adev->gfx.config.gb_addr_config_fields.num_rb_per_se;
3290 tiling_info->gfx9.swizzle =
3291 AMDGPU_TILING_GET(tiling_flags, SWIZZLE_MODE);
3292 tiling_info->gfx9.shaderEnable = 1;
3294 ret = fill_plane_dcc_attributes(adev, afb, format, rotation,
3295 plane_size, tiling_info,
3296 tiling_flags, dcc, address);
3305 fill_blending_from_plane_state(const struct drm_plane_state *plane_state,
3306 bool *per_pixel_alpha, bool *global_alpha,
3307 int *global_alpha_value)
3309 *per_pixel_alpha = false;
3310 *global_alpha = false;
3311 *global_alpha_value = 0xff;
3313 if (plane_state->plane->type != DRM_PLANE_TYPE_OVERLAY)
3316 if (plane_state->pixel_blend_mode == DRM_MODE_BLEND_PREMULTI) {
3317 static const uint32_t alpha_formats[] = {
3318 DRM_FORMAT_ARGB8888,
3319 DRM_FORMAT_RGBA8888,
3320 DRM_FORMAT_ABGR8888,
3322 uint32_t format = plane_state->fb->format->format;
3325 for (i = 0; i < ARRAY_SIZE(alpha_formats); ++i) {
3326 if (format == alpha_formats[i]) {
3327 *per_pixel_alpha = true;
3333 if (plane_state->alpha < 0xffff) {
3334 *global_alpha = true;
3335 *global_alpha_value = plane_state->alpha >> 8;
3340 fill_plane_color_attributes(const struct drm_plane_state *plane_state,
3341 const enum surface_pixel_format format,
3342 enum dc_color_space *color_space)
3346 *color_space = COLOR_SPACE_SRGB;
3348 /* DRM color properties only affect non-RGB formats. */
3349 if (format < SURFACE_PIXEL_FORMAT_VIDEO_BEGIN)
3352 full_range = (plane_state->color_range == DRM_COLOR_YCBCR_FULL_RANGE);
3354 switch (plane_state->color_encoding) {
3355 case DRM_COLOR_YCBCR_BT601:
3357 *color_space = COLOR_SPACE_YCBCR601;
3359 *color_space = COLOR_SPACE_YCBCR601_LIMITED;
3362 case DRM_COLOR_YCBCR_BT709:
3364 *color_space = COLOR_SPACE_YCBCR709;
3366 *color_space = COLOR_SPACE_YCBCR709_LIMITED;
3369 case DRM_COLOR_YCBCR_BT2020:
3371 *color_space = COLOR_SPACE_2020_YCBCR;
3384 fill_dc_plane_info_and_addr(struct amdgpu_device *adev,
3385 const struct drm_plane_state *plane_state,
3386 const uint64_t tiling_flags,
3387 struct dc_plane_info *plane_info,
3388 struct dc_plane_address *address)
3390 const struct drm_framebuffer *fb = plane_state->fb;
3391 const struct amdgpu_framebuffer *afb =
3392 to_amdgpu_framebuffer(plane_state->fb);
3393 struct drm_format_name_buf format_name;
3396 memset(plane_info, 0, sizeof(*plane_info));
3398 switch (fb->format->format) {
3400 plane_info->format =
3401 SURFACE_PIXEL_FORMAT_GRPH_PALETA_256_COLORS;
3403 case DRM_FORMAT_RGB565:
3404 plane_info->format = SURFACE_PIXEL_FORMAT_GRPH_RGB565;
3406 case DRM_FORMAT_XRGB8888:
3407 case DRM_FORMAT_ARGB8888:
3408 plane_info->format = SURFACE_PIXEL_FORMAT_GRPH_ARGB8888;
3410 case DRM_FORMAT_XRGB2101010:
3411 case DRM_FORMAT_ARGB2101010:
3412 plane_info->format = SURFACE_PIXEL_FORMAT_GRPH_ARGB2101010;
3414 case DRM_FORMAT_XBGR2101010:
3415 case DRM_FORMAT_ABGR2101010:
3416 plane_info->format = SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010;
3418 case DRM_FORMAT_XBGR8888:
3419 case DRM_FORMAT_ABGR8888:
3420 plane_info->format = SURFACE_PIXEL_FORMAT_GRPH_ABGR8888;
3422 case DRM_FORMAT_NV21:
3423 plane_info->format = SURFACE_PIXEL_FORMAT_VIDEO_420_YCbCr;
3425 case DRM_FORMAT_NV12:
3426 plane_info->format = SURFACE_PIXEL_FORMAT_VIDEO_420_YCrCb;
3430 "Unsupported screen format %s\n",
3431 drm_get_format_name(fb->format->format, &format_name));
3435 switch (plane_state->rotation & DRM_MODE_ROTATE_MASK) {
3436 case DRM_MODE_ROTATE_0:
3437 plane_info->rotation = ROTATION_ANGLE_0;
3439 case DRM_MODE_ROTATE_90:
3440 plane_info->rotation = ROTATION_ANGLE_90;
3442 case DRM_MODE_ROTATE_180:
3443 plane_info->rotation = ROTATION_ANGLE_180;
3445 case DRM_MODE_ROTATE_270:
3446 plane_info->rotation = ROTATION_ANGLE_270;
3449 plane_info->rotation = ROTATION_ANGLE_0;
3453 plane_info->visible = true;
3454 plane_info->stereo_format = PLANE_STEREO_FORMAT_NONE;
3456 plane_info->layer_index = 0;
3458 ret = fill_plane_color_attributes(plane_state, plane_info->format,
3459 &plane_info->color_space);
3463 ret = fill_plane_buffer_attributes(adev, afb, plane_info->format,
3464 plane_info->rotation, tiling_flags,
3465 &plane_info->tiling_info,
3466 &plane_info->plane_size,
3467 &plane_info->dcc, address);
3471 fill_blending_from_plane_state(
3472 plane_state, &plane_info->per_pixel_alpha,
3473 &plane_info->global_alpha, &plane_info->global_alpha_value);
3478 static int fill_dc_plane_attributes(struct amdgpu_device *adev,
3479 struct dc_plane_state *dc_plane_state,
3480 struct drm_plane_state *plane_state,
3481 struct drm_crtc_state *crtc_state)
3483 struct dm_crtc_state *dm_crtc_state = to_dm_crtc_state(crtc_state);
3484 const struct amdgpu_framebuffer *amdgpu_fb =
3485 to_amdgpu_framebuffer(plane_state->fb);
3486 struct dc_scaling_info scaling_info;
3487 struct dc_plane_info plane_info;
3488 uint64_t tiling_flags;
3491 ret = fill_dc_scaling_info(plane_state, &scaling_info);
3495 dc_plane_state->src_rect = scaling_info.src_rect;
3496 dc_plane_state->dst_rect = scaling_info.dst_rect;
3497 dc_plane_state->clip_rect = scaling_info.clip_rect;
3498 dc_plane_state->scaling_quality = scaling_info.scaling_quality;
3500 ret = get_fb_info(amdgpu_fb, &tiling_flags);
3504 ret = fill_dc_plane_info_and_addr(adev, plane_state, tiling_flags,
3506 &dc_plane_state->address);
3510 dc_plane_state->format = plane_info.format;
3511 dc_plane_state->color_space = plane_info.color_space;
3512 dc_plane_state->format = plane_info.format;
3513 dc_plane_state->plane_size = plane_info.plane_size;
3514 dc_plane_state->rotation = plane_info.rotation;
3515 dc_plane_state->horizontal_mirror = plane_info.horizontal_mirror;
3516 dc_plane_state->stereo_format = plane_info.stereo_format;
3517 dc_plane_state->tiling_info = plane_info.tiling_info;
3518 dc_plane_state->visible = plane_info.visible;
3519 dc_plane_state->per_pixel_alpha = plane_info.per_pixel_alpha;
3520 dc_plane_state->global_alpha = plane_info.global_alpha;
3521 dc_plane_state->global_alpha_value = plane_info.global_alpha_value;
3522 dc_plane_state->dcc = plane_info.dcc;
3523 dc_plane_state->layer_index = plane_info.layer_index; // Always returns 0
3526 * Always set input transfer function, since plane state is refreshed
3529 ret = amdgpu_dm_update_plane_color_mgmt(dm_crtc_state, dc_plane_state);
3536 static void update_stream_scaling_settings(const struct drm_display_mode *mode,
3537 const struct dm_connector_state *dm_state,
3538 struct dc_stream_state *stream)
3540 enum amdgpu_rmx_type rmx_type;
3542 struct rect src = { 0 }; /* viewport in composition space*/
3543 struct rect dst = { 0 }; /* stream addressable area */
3545 /* no mode. nothing to be done */
3549 /* Full screen scaling by default */
3550 src.width = mode->hdisplay;
3551 src.height = mode->vdisplay;
3552 dst.width = stream->timing.h_addressable;
3553 dst.height = stream->timing.v_addressable;
3556 rmx_type = dm_state->scaling;
3557 if (rmx_type == RMX_ASPECT || rmx_type == RMX_OFF) {
3558 if (src.width * dst.height <
3559 src.height * dst.width) {
3560 /* height needs less upscaling/more downscaling */
3561 dst.width = src.width *
3562 dst.height / src.height;
3564 /* width needs less upscaling/more downscaling */
3565 dst.height = src.height *
3566 dst.width / src.width;
3568 } else if (rmx_type == RMX_CENTER) {
3572 dst.x = (stream->timing.h_addressable - dst.width) / 2;
3573 dst.y = (stream->timing.v_addressable - dst.height) / 2;
3575 if (dm_state->underscan_enable) {
3576 dst.x += dm_state->underscan_hborder / 2;
3577 dst.y += dm_state->underscan_vborder / 2;
3578 dst.width -= dm_state->underscan_hborder;
3579 dst.height -= dm_state->underscan_vborder;
3586 DRM_DEBUG_DRIVER("Destination Rectangle x:%d y:%d width:%d height:%d\n",
3587 dst.x, dst.y, dst.width, dst.height);
3591 static enum dc_color_depth
3592 convert_color_depth_from_display_info(const struct drm_connector *connector,
3593 const struct drm_connector_state *state,
3601 /* Cap display bpc based on HDMI 2.0 HF-VSDB */
3602 if (connector->display_info.hdmi.y420_dc_modes & DRM_EDID_YCBCR420_DC_48)
3604 else if (connector->display_info.hdmi.y420_dc_modes & DRM_EDID_YCBCR420_DC_36)
3606 else if (connector->display_info.hdmi.y420_dc_modes & DRM_EDID_YCBCR420_DC_30)
3609 bpc = (uint8_t)connector->display_info.bpc;
3610 /* Assume 8 bpc by default if no bpc is specified. */
3611 bpc = bpc ? bpc : 8;
3615 state = connector->state;
3619 * Cap display bpc based on the user requested value.
3621 * The value for state->max_bpc may not correctly updated
3622 * depending on when the connector gets added to the state
3623 * or if this was called outside of atomic check, so it
3624 * can't be used directly.
3626 bpc = min(bpc, state->max_requested_bpc);
3628 /* Round down to the nearest even number. */
3629 bpc = bpc - (bpc & 1);
3635 * Temporary Work around, DRM doesn't parse color depth for
3636 * EDID revision before 1.4
3637 * TODO: Fix edid parsing
3639 return COLOR_DEPTH_888;
3641 return COLOR_DEPTH_666;
3643 return COLOR_DEPTH_888;
3645 return COLOR_DEPTH_101010;
3647 return COLOR_DEPTH_121212;
3649 return COLOR_DEPTH_141414;
3651 return COLOR_DEPTH_161616;
3653 return COLOR_DEPTH_UNDEFINED;
3657 static enum dc_aspect_ratio
3658 get_aspect_ratio(const struct drm_display_mode *mode_in)
3660 /* 1-1 mapping, since both enums follow the HDMI spec. */
3661 return (enum dc_aspect_ratio) mode_in->picture_aspect_ratio;
3664 static enum dc_color_space
3665 get_output_color_space(const struct dc_crtc_timing *dc_crtc_timing)
3667 enum dc_color_space color_space = COLOR_SPACE_SRGB;
3669 switch (dc_crtc_timing->pixel_encoding) {
3670 case PIXEL_ENCODING_YCBCR422:
3671 case PIXEL_ENCODING_YCBCR444:
3672 case PIXEL_ENCODING_YCBCR420:
3675 * 27030khz is the separation point between HDTV and SDTV
3676 * according to HDMI spec, we use YCbCr709 and YCbCr601
3679 if (dc_crtc_timing->pix_clk_100hz > 270300) {
3680 if (dc_crtc_timing->flags.Y_ONLY)
3682 COLOR_SPACE_YCBCR709_LIMITED;
3684 color_space = COLOR_SPACE_YCBCR709;
3686 if (dc_crtc_timing->flags.Y_ONLY)
3688 COLOR_SPACE_YCBCR601_LIMITED;
3690 color_space = COLOR_SPACE_YCBCR601;
3695 case PIXEL_ENCODING_RGB:
3696 color_space = COLOR_SPACE_SRGB;
3707 static bool adjust_colour_depth_from_display_info(
3708 struct dc_crtc_timing *timing_out,
3709 const struct drm_display_info *info)
3711 enum dc_color_depth depth = timing_out->display_color_depth;
3714 normalized_clk = timing_out->pix_clk_100hz / 10;
3715 /* YCbCr 4:2:0 requires additional adjustment of 1/2 */
3716 if (timing_out->pixel_encoding == PIXEL_ENCODING_YCBCR420)
3717 normalized_clk /= 2;
3718 /* Adjusting pix clock following on HDMI spec based on colour depth */
3720 case COLOR_DEPTH_888:
3722 case COLOR_DEPTH_101010:
3723 normalized_clk = (normalized_clk * 30) / 24;
3725 case COLOR_DEPTH_121212:
3726 normalized_clk = (normalized_clk * 36) / 24;
3728 case COLOR_DEPTH_161616:
3729 normalized_clk = (normalized_clk * 48) / 24;
3732 /* The above depths are the only ones valid for HDMI. */
3735 if (normalized_clk <= info->max_tmds_clock) {
3736 timing_out->display_color_depth = depth;
3739 } while (--depth > COLOR_DEPTH_666);
3743 static void fill_stream_properties_from_drm_display_mode(
3744 struct dc_stream_state *stream,
3745 const struct drm_display_mode *mode_in,
3746 const struct drm_connector *connector,
3747 const struct drm_connector_state *connector_state,
3748 const struct dc_stream_state *old_stream)
3750 struct dc_crtc_timing *timing_out = &stream->timing;
3751 const struct drm_display_info *info = &connector->display_info;
3752 struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
3753 struct hdmi_vendor_infoframe hv_frame;
3754 struct hdmi_avi_infoframe avi_frame;
3756 memset(&hv_frame, 0, sizeof(hv_frame));
3757 memset(&avi_frame, 0, sizeof(avi_frame));
3759 timing_out->h_border_left = 0;
3760 timing_out->h_border_right = 0;
3761 timing_out->v_border_top = 0;
3762 timing_out->v_border_bottom = 0;
3763 /* TODO: un-hardcode */
3764 if (drm_mode_is_420_only(info, mode_in)
3765 && stream->signal == SIGNAL_TYPE_HDMI_TYPE_A)
3766 timing_out->pixel_encoding = PIXEL_ENCODING_YCBCR420;
3767 else if (drm_mode_is_420_also(info, mode_in)
3768 && aconnector->force_yuv420_output)
3769 timing_out->pixel_encoding = PIXEL_ENCODING_YCBCR420;
3770 else if ((connector->display_info.color_formats & DRM_COLOR_FORMAT_YCRCB444)
3771 && stream->signal == SIGNAL_TYPE_HDMI_TYPE_A)
3772 timing_out->pixel_encoding = PIXEL_ENCODING_YCBCR444;
3774 timing_out->pixel_encoding = PIXEL_ENCODING_RGB;
3776 timing_out->timing_3d_format = TIMING_3D_FORMAT_NONE;
3777 timing_out->display_color_depth = convert_color_depth_from_display_info(
3778 connector, connector_state,
3779 (timing_out->pixel_encoding == PIXEL_ENCODING_YCBCR420));
3780 timing_out->scan_type = SCANNING_TYPE_NODATA;
3781 timing_out->hdmi_vic = 0;
3784 timing_out->vic = old_stream->timing.vic;
3785 timing_out->flags.HSYNC_POSITIVE_POLARITY = old_stream->timing.flags.HSYNC_POSITIVE_POLARITY;
3786 timing_out->flags.VSYNC_POSITIVE_POLARITY = old_stream->timing.flags.VSYNC_POSITIVE_POLARITY;
3788 timing_out->vic = drm_match_cea_mode(mode_in);
3789 if (mode_in->flags & DRM_MODE_FLAG_PHSYNC)
3790 timing_out->flags.HSYNC_POSITIVE_POLARITY = 1;
3791 if (mode_in->flags & DRM_MODE_FLAG_PVSYNC)
3792 timing_out->flags.VSYNC_POSITIVE_POLARITY = 1;
3795 if (stream->signal == SIGNAL_TYPE_HDMI_TYPE_A) {
3796 drm_hdmi_avi_infoframe_from_display_mode(&avi_frame, (struct drm_connector *)connector, mode_in);
3797 timing_out->vic = avi_frame.video_code;
3798 drm_hdmi_vendor_infoframe_from_display_mode(&hv_frame, (struct drm_connector *)connector, mode_in);
3799 timing_out->hdmi_vic = hv_frame.vic;
3802 timing_out->h_addressable = mode_in->crtc_hdisplay;
3803 timing_out->h_total = mode_in->crtc_htotal;
3804 timing_out->h_sync_width =
3805 mode_in->crtc_hsync_end - mode_in->crtc_hsync_start;
3806 timing_out->h_front_porch =
3807 mode_in->crtc_hsync_start - mode_in->crtc_hdisplay;
3808 timing_out->v_total = mode_in->crtc_vtotal;
3809 timing_out->v_addressable = mode_in->crtc_vdisplay;
3810 timing_out->v_front_porch =
3811 mode_in->crtc_vsync_start - mode_in->crtc_vdisplay;
3812 timing_out->v_sync_width =
3813 mode_in->crtc_vsync_end - mode_in->crtc_vsync_start;
3814 timing_out->pix_clk_100hz = mode_in->crtc_clock * 10;
3815 timing_out->aspect_ratio = get_aspect_ratio(mode_in);
3817 stream->output_color_space = get_output_color_space(timing_out);
3819 stream->out_transfer_func->type = TF_TYPE_PREDEFINED;
3820 stream->out_transfer_func->tf = TRANSFER_FUNCTION_SRGB;
3821 if (stream->signal == SIGNAL_TYPE_HDMI_TYPE_A) {
3822 if (!adjust_colour_depth_from_display_info(timing_out, info) &&
3823 drm_mode_is_420_also(info, mode_in) &&
3824 timing_out->pixel_encoding != PIXEL_ENCODING_YCBCR420) {
3825 timing_out->pixel_encoding = PIXEL_ENCODING_YCBCR420;
3826 adjust_colour_depth_from_display_info(timing_out, info);
3831 static void fill_audio_info(struct audio_info *audio_info,
3832 const struct drm_connector *drm_connector,
3833 const struct dc_sink *dc_sink)
3836 int cea_revision = 0;
3837 const struct dc_edid_caps *edid_caps = &dc_sink->edid_caps;
3839 audio_info->manufacture_id = edid_caps->manufacturer_id;
3840 audio_info->product_id = edid_caps->product_id;
3842 cea_revision = drm_connector->display_info.cea_rev;
3844 strscpy(audio_info->display_name,
3845 edid_caps->display_name,
3846 AUDIO_INFO_DISPLAY_NAME_SIZE_IN_CHARS);
3848 if (cea_revision >= 3) {
3849 audio_info->mode_count = edid_caps->audio_mode_count;
3851 for (i = 0; i < audio_info->mode_count; ++i) {
3852 audio_info->modes[i].format_code =
3853 (enum audio_format_code)
3854 (edid_caps->audio_modes[i].format_code);
3855 audio_info->modes[i].channel_count =
3856 edid_caps->audio_modes[i].channel_count;
3857 audio_info->modes[i].sample_rates.all =
3858 edid_caps->audio_modes[i].sample_rate;
3859 audio_info->modes[i].sample_size =
3860 edid_caps->audio_modes[i].sample_size;
3864 audio_info->flags.all = edid_caps->speaker_flags;
3866 /* TODO: We only check for the progressive mode, check for interlace mode too */
3867 if (drm_connector->latency_present[0]) {
3868 audio_info->video_latency = drm_connector->video_latency[0];
3869 audio_info->audio_latency = drm_connector->audio_latency[0];
3872 /* TODO: For DP, video and audio latency should be calculated from DPCD caps */
3877 copy_crtc_timing_for_drm_display_mode(const struct drm_display_mode *src_mode,
3878 struct drm_display_mode *dst_mode)
3880 dst_mode->crtc_hdisplay = src_mode->crtc_hdisplay;
3881 dst_mode->crtc_vdisplay = src_mode->crtc_vdisplay;
3882 dst_mode->crtc_clock = src_mode->crtc_clock;
3883 dst_mode->crtc_hblank_start = src_mode->crtc_hblank_start;
3884 dst_mode->crtc_hblank_end = src_mode->crtc_hblank_end;
3885 dst_mode->crtc_hsync_start = src_mode->crtc_hsync_start;
3886 dst_mode->crtc_hsync_end = src_mode->crtc_hsync_end;
3887 dst_mode->crtc_htotal = src_mode->crtc_htotal;
3888 dst_mode->crtc_hskew = src_mode->crtc_hskew;
3889 dst_mode->crtc_vblank_start = src_mode->crtc_vblank_start;
3890 dst_mode->crtc_vblank_end = src_mode->crtc_vblank_end;
3891 dst_mode->crtc_vsync_start = src_mode->crtc_vsync_start;
3892 dst_mode->crtc_vsync_end = src_mode->crtc_vsync_end;
3893 dst_mode->crtc_vtotal = src_mode->crtc_vtotal;
3897 decide_crtc_timing_for_drm_display_mode(struct drm_display_mode *drm_mode,
3898 const struct drm_display_mode *native_mode,
3901 if (scale_enabled) {
3902 copy_crtc_timing_for_drm_display_mode(native_mode, drm_mode);
3903 } else if (native_mode->clock == drm_mode->clock &&
3904 native_mode->htotal == drm_mode->htotal &&
3905 native_mode->vtotal == drm_mode->vtotal) {
3906 copy_crtc_timing_for_drm_display_mode(native_mode, drm_mode);
3908 /* no scaling nor amdgpu inserted, no need to patch */
3912 static struct dc_sink *
3913 create_fake_sink(struct amdgpu_dm_connector *aconnector)
3915 struct dc_sink_init_data sink_init_data = { 0 };
3916 struct dc_sink *sink = NULL;
3917 sink_init_data.link = aconnector->dc_link;
3918 sink_init_data.sink_signal = aconnector->dc_link->connector_signal;
3920 sink = dc_sink_create(&sink_init_data);
3922 DRM_ERROR("Failed to create sink!\n");
3925 sink->sink_signal = SIGNAL_TYPE_VIRTUAL;
3930 static void set_multisync_trigger_params(
3931 struct dc_stream_state *stream)
3933 if (stream->triggered_crtc_reset.enabled) {
3934 stream->triggered_crtc_reset.event = CRTC_EVENT_VSYNC_RISING;
3935 stream->triggered_crtc_reset.delay = TRIGGER_DELAY_NEXT_LINE;
3939 static void set_master_stream(struct dc_stream_state *stream_set[],
3942 int j, highest_rfr = 0, master_stream = 0;
3944 for (j = 0; j < stream_count; j++) {
3945 if (stream_set[j] && stream_set[j]->triggered_crtc_reset.enabled) {
3946 int refresh_rate = 0;
3948 refresh_rate = (stream_set[j]->timing.pix_clk_100hz*100)/
3949 (stream_set[j]->timing.h_total*stream_set[j]->timing.v_total);
3950 if (refresh_rate > highest_rfr) {
3951 highest_rfr = refresh_rate;
3956 for (j = 0; j < stream_count; j++) {
3958 stream_set[j]->triggered_crtc_reset.event_source = stream_set[master_stream];
3962 static void dm_enable_per_frame_crtc_master_sync(struct dc_state *context)
3966 if (context->stream_count < 2)
3968 for (i = 0; i < context->stream_count ; i++) {
3969 if (!context->streams[i])
3972 * TODO: add a function to read AMD VSDB bits and set
3973 * crtc_sync_master.multi_sync_enabled flag
3974 * For now it's set to false
3976 set_multisync_trigger_params(context->streams[i]);
3978 set_master_stream(context->streams, context->stream_count);
3981 static struct dc_stream_state *
3982 create_stream_for_sink(struct amdgpu_dm_connector *aconnector,
3983 const struct drm_display_mode *drm_mode,
3984 const struct dm_connector_state *dm_state,
3985 const struct dc_stream_state *old_stream)
3987 struct drm_display_mode *preferred_mode = NULL;
3988 struct drm_connector *drm_connector;
3989 const struct drm_connector_state *con_state =
3990 dm_state ? &dm_state->base : NULL;
3991 struct dc_stream_state *stream = NULL;
3992 struct drm_display_mode mode = *drm_mode;
3993 bool native_mode_found = false;
3994 bool scale = dm_state ? (dm_state->scaling != RMX_OFF) : false;
3996 int preferred_refresh = 0;
3997 #if defined(CONFIG_DRM_AMD_DC_DCN)
3998 struct dsc_dec_dpcd_caps dsc_caps;
4000 uint32_t link_bandwidth_kbps;
4002 struct dc_sink *sink = NULL;
4003 if (aconnector == NULL) {
4004 DRM_ERROR("aconnector is NULL!\n");
4008 drm_connector = &aconnector->base;
4010 if (!aconnector->dc_sink) {
4011 sink = create_fake_sink(aconnector);
4015 sink = aconnector->dc_sink;
4016 dc_sink_retain(sink);
4019 stream = dc_create_stream_for_sink(sink);
4021 if (stream == NULL) {
4022 DRM_ERROR("Failed to create stream for sink!\n");
4026 stream->dm_stream_context = aconnector;
4028 stream->timing.flags.LTE_340MCSC_SCRAMBLE =
4029 drm_connector->display_info.hdmi.scdc.scrambling.low_rates;
4031 list_for_each_entry(preferred_mode, &aconnector->base.modes, head) {
4032 /* Search for preferred mode */
4033 if (preferred_mode->type & DRM_MODE_TYPE_PREFERRED) {
4034 native_mode_found = true;
4038 if (!native_mode_found)
4039 preferred_mode = list_first_entry_or_null(
4040 &aconnector->base.modes,
4041 struct drm_display_mode,
4044 mode_refresh = drm_mode_vrefresh(&mode);
4046 if (preferred_mode == NULL) {
4048 * This may not be an error, the use case is when we have no
4049 * usermode calls to reset and set mode upon hotplug. In this
4050 * case, we call set mode ourselves to restore the previous mode
4051 * and the modelist may not be filled in in time.
4053 DRM_DEBUG_DRIVER("No preferred mode found\n");
4055 decide_crtc_timing_for_drm_display_mode(
4056 &mode, preferred_mode,
4057 dm_state ? (dm_state->scaling != RMX_OFF) : false);
4058 preferred_refresh = drm_mode_vrefresh(preferred_mode);
4062 drm_mode_set_crtcinfo(&mode, 0);
4065 * If scaling is enabled and refresh rate didn't change
4066 * we copy the vic and polarities of the old timings
4068 if (!scale || mode_refresh != preferred_refresh)
4069 fill_stream_properties_from_drm_display_mode(stream,
4070 &mode, &aconnector->base, con_state, NULL);
4072 fill_stream_properties_from_drm_display_mode(stream,
4073 &mode, &aconnector->base, con_state, old_stream);
4075 stream->timing.flags.DSC = 0;
4077 if (aconnector->dc_link && sink->sink_signal == SIGNAL_TYPE_DISPLAY_PORT) {
4078 #if defined(CONFIG_DRM_AMD_DC_DCN)
4079 dc_dsc_parse_dsc_dpcd(aconnector->dc_link->ctx->dc,
4080 aconnector->dc_link->dpcd_caps.dsc_caps.dsc_basic_caps.raw,
4081 aconnector->dc_link->dpcd_caps.dsc_caps.dsc_ext_caps.raw,
4084 link_bandwidth_kbps = dc_link_bandwidth_kbps(aconnector->dc_link,
4085 dc_link_get_link_cap(aconnector->dc_link));
4087 #if defined(CONFIG_DRM_AMD_DC_DCN)
4088 if (dsc_caps.is_dsc_supported)
4089 if (dc_dsc_compute_config(aconnector->dc_link->ctx->dc->res_pool->dscs[0],
4091 aconnector->dc_link->ctx->dc->debug.dsc_min_slice_height_override,
4092 link_bandwidth_kbps,
4094 &stream->timing.dsc_cfg))
4095 stream->timing.flags.DSC = 1;
4099 update_stream_scaling_settings(&mode, dm_state, stream);
4102 &stream->audio_info,
4106 update_stream_signal(stream, sink);
4108 if (stream->signal == SIGNAL_TYPE_HDMI_TYPE_A)
4109 mod_build_hf_vsif_infopacket(stream, &stream->vsp_infopacket, false, false);
4110 if (stream->link->psr_feature_enabled) {
4111 struct dc *core_dc = stream->link->ctx->dc;
4113 if (dc_is_dmcu_initialized(core_dc)) {
4114 struct dmcu *dmcu = core_dc->res_pool->dmcu;
4116 stream->psr_version = dmcu->dmcu_version.psr_version;
4117 mod_build_vsc_infopacket(stream,
4118 &stream->vsc_infopacket,
4119 &stream->use_vsc_sdp_for_colorimetry);
4123 dc_sink_release(sink);
4128 static void amdgpu_dm_crtc_destroy(struct drm_crtc *crtc)
4130 drm_crtc_cleanup(crtc);
4134 static void dm_crtc_destroy_state(struct drm_crtc *crtc,
4135 struct drm_crtc_state *state)
4137 struct dm_crtc_state *cur = to_dm_crtc_state(state);
4139 /* TODO Destroy dc_stream objects are stream object is flattened */
4141 dc_stream_release(cur->stream);
4144 __drm_atomic_helper_crtc_destroy_state(state);
4150 static void dm_crtc_reset_state(struct drm_crtc *crtc)
4152 struct dm_crtc_state *state;
4155 dm_crtc_destroy_state(crtc, crtc->state);
4157 state = kzalloc(sizeof(*state), GFP_KERNEL);
4158 if (WARN_ON(!state))
4161 crtc->state = &state->base;
4162 crtc->state->crtc = crtc;
4166 static struct drm_crtc_state *
4167 dm_crtc_duplicate_state(struct drm_crtc *crtc)
4169 struct dm_crtc_state *state, *cur;
4171 cur = to_dm_crtc_state(crtc->state);
4173 if (WARN_ON(!crtc->state))
4176 state = kzalloc(sizeof(*state), GFP_KERNEL);
4180 __drm_atomic_helper_crtc_duplicate_state(crtc, &state->base);
4183 state->stream = cur->stream;
4184 dc_stream_retain(state->stream);
4187 state->active_planes = cur->active_planes;
4188 state->interrupts_enabled = cur->interrupts_enabled;
4189 state->vrr_params = cur->vrr_params;
4190 state->vrr_infopacket = cur->vrr_infopacket;
4191 state->abm_level = cur->abm_level;
4192 state->vrr_supported = cur->vrr_supported;
4193 state->freesync_config = cur->freesync_config;
4194 state->crc_src = cur->crc_src;
4195 state->cm_has_degamma = cur->cm_has_degamma;
4196 state->cm_is_degamma_srgb = cur->cm_is_degamma_srgb;
4198 /* TODO Duplicate dc_stream after objects are stream object is flattened */
4200 return &state->base;
4203 static inline int dm_set_vupdate_irq(struct drm_crtc *crtc, bool enable)
4205 enum dc_irq_source irq_source;
4206 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
4207 struct amdgpu_device *adev = crtc->dev->dev_private;
4210 /* Do not set vupdate for DCN hardware */
4211 if (adev->family > AMDGPU_FAMILY_AI)
4214 irq_source = IRQ_TYPE_VUPDATE + acrtc->otg_inst;
4216 rc = dc_interrupt_set(adev->dm.dc, irq_source, enable) ? 0 : -EBUSY;
4218 DRM_DEBUG_DRIVER("crtc %d - vupdate irq %sabling: r=%d\n",
4219 acrtc->crtc_id, enable ? "en" : "dis", rc);
4223 static inline int dm_set_vblank(struct drm_crtc *crtc, bool enable)
4225 enum dc_irq_source irq_source;
4226 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
4227 struct amdgpu_device *adev = crtc->dev->dev_private;
4228 struct dm_crtc_state *acrtc_state = to_dm_crtc_state(crtc->state);
4232 /* vblank irq on -> Only need vupdate irq in vrr mode */
4233 if (amdgpu_dm_vrr_active(acrtc_state))
4234 rc = dm_set_vupdate_irq(crtc, true);
4236 /* vblank irq off -> vupdate irq off */
4237 rc = dm_set_vupdate_irq(crtc, false);
4243 irq_source = IRQ_TYPE_VBLANK + acrtc->otg_inst;
4244 return dc_interrupt_set(adev->dm.dc, irq_source, enable) ? 0 : -EBUSY;
4247 static int dm_enable_vblank(struct drm_crtc *crtc)
4249 return dm_set_vblank(crtc, true);
4252 static void dm_disable_vblank(struct drm_crtc *crtc)
4254 dm_set_vblank(crtc, false);
4257 /* Implemented only the options currently availible for the driver */
4258 static const struct drm_crtc_funcs amdgpu_dm_crtc_funcs = {
4259 .reset = dm_crtc_reset_state,
4260 .destroy = amdgpu_dm_crtc_destroy,
4261 .gamma_set = drm_atomic_helper_legacy_gamma_set,
4262 .set_config = drm_atomic_helper_set_config,
4263 .page_flip = drm_atomic_helper_page_flip,
4264 .atomic_duplicate_state = dm_crtc_duplicate_state,
4265 .atomic_destroy_state = dm_crtc_destroy_state,
4266 .set_crc_source = amdgpu_dm_crtc_set_crc_source,
4267 .verify_crc_source = amdgpu_dm_crtc_verify_crc_source,
4268 .get_crc_sources = amdgpu_dm_crtc_get_crc_sources,
4269 .enable_vblank = dm_enable_vblank,
4270 .disable_vblank = dm_disable_vblank,
4273 static enum drm_connector_status
4274 amdgpu_dm_connector_detect(struct drm_connector *connector, bool force)
4277 struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
4281 * 1. This interface is NOT called in context of HPD irq.
4282 * 2. This interface *is called* in context of user-mode ioctl. Which
4283 * makes it a bad place for *any* MST-related activity.
4286 if (aconnector->base.force == DRM_FORCE_UNSPECIFIED &&
4287 !aconnector->fake_enable)
4288 connected = (aconnector->dc_sink != NULL);
4290 connected = (aconnector->base.force == DRM_FORCE_ON);
4292 return (connected ? connector_status_connected :
4293 connector_status_disconnected);
4296 int amdgpu_dm_connector_atomic_set_property(struct drm_connector *connector,
4297 struct drm_connector_state *connector_state,
4298 struct drm_property *property,
4301 struct drm_device *dev = connector->dev;
4302 struct amdgpu_device *adev = dev->dev_private;
4303 struct dm_connector_state *dm_old_state =
4304 to_dm_connector_state(connector->state);
4305 struct dm_connector_state *dm_new_state =
4306 to_dm_connector_state(connector_state);
4310 if (property == dev->mode_config.scaling_mode_property) {
4311 enum amdgpu_rmx_type rmx_type;
4314 case DRM_MODE_SCALE_CENTER:
4315 rmx_type = RMX_CENTER;
4317 case DRM_MODE_SCALE_ASPECT:
4318 rmx_type = RMX_ASPECT;
4320 case DRM_MODE_SCALE_FULLSCREEN:
4321 rmx_type = RMX_FULL;
4323 case DRM_MODE_SCALE_NONE:
4329 if (dm_old_state->scaling == rmx_type)
4332 dm_new_state->scaling = rmx_type;
4334 } else if (property == adev->mode_info.underscan_hborder_property) {
4335 dm_new_state->underscan_hborder = val;
4337 } else if (property == adev->mode_info.underscan_vborder_property) {
4338 dm_new_state->underscan_vborder = val;
4340 } else if (property == adev->mode_info.underscan_property) {
4341 dm_new_state->underscan_enable = val;
4343 } else if (property == adev->mode_info.abm_level_property) {
4344 dm_new_state->abm_level = val;
4351 int amdgpu_dm_connector_atomic_get_property(struct drm_connector *connector,
4352 const struct drm_connector_state *state,
4353 struct drm_property *property,
4356 struct drm_device *dev = connector->dev;
4357 struct amdgpu_device *adev = dev->dev_private;
4358 struct dm_connector_state *dm_state =
4359 to_dm_connector_state(state);
4362 if (property == dev->mode_config.scaling_mode_property) {
4363 switch (dm_state->scaling) {
4365 *val = DRM_MODE_SCALE_CENTER;
4368 *val = DRM_MODE_SCALE_ASPECT;
4371 *val = DRM_MODE_SCALE_FULLSCREEN;
4375 *val = DRM_MODE_SCALE_NONE;
4379 } else if (property == adev->mode_info.underscan_hborder_property) {
4380 *val = dm_state->underscan_hborder;
4382 } else if (property == adev->mode_info.underscan_vborder_property) {
4383 *val = dm_state->underscan_vborder;
4385 } else if (property == adev->mode_info.underscan_property) {
4386 *val = dm_state->underscan_enable;
4388 } else if (property == adev->mode_info.abm_level_property) {
4389 *val = dm_state->abm_level;
4396 static void amdgpu_dm_connector_unregister(struct drm_connector *connector)
4398 struct amdgpu_dm_connector *amdgpu_dm_connector = to_amdgpu_dm_connector(connector);
4400 drm_dp_aux_unregister(&amdgpu_dm_connector->dm_dp_aux.aux);
4403 static void amdgpu_dm_connector_destroy(struct drm_connector *connector)
4405 struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
4406 const struct dc_link *link = aconnector->dc_link;
4407 struct amdgpu_device *adev = connector->dev->dev_private;
4408 struct amdgpu_display_manager *dm = &adev->dm;
4410 #if defined(CONFIG_BACKLIGHT_CLASS_DEVICE) ||\
4411 defined(CONFIG_BACKLIGHT_CLASS_DEVICE_MODULE)
4413 if ((link->connector_signal & (SIGNAL_TYPE_EDP | SIGNAL_TYPE_LVDS)) &&
4414 link->type != dc_connection_none &&
4415 dm->backlight_dev) {
4416 backlight_device_unregister(dm->backlight_dev);
4417 dm->backlight_dev = NULL;
4421 if (aconnector->dc_em_sink)
4422 dc_sink_release(aconnector->dc_em_sink);
4423 aconnector->dc_em_sink = NULL;
4424 if (aconnector->dc_sink)
4425 dc_sink_release(aconnector->dc_sink);
4426 aconnector->dc_sink = NULL;
4428 drm_dp_cec_unregister_connector(&aconnector->dm_dp_aux.aux);
4429 drm_connector_unregister(connector);
4430 drm_connector_cleanup(connector);
4431 if (aconnector->i2c) {
4432 i2c_del_adapter(&aconnector->i2c->base);
4433 kfree(aconnector->i2c);
4439 void amdgpu_dm_connector_funcs_reset(struct drm_connector *connector)
4441 struct dm_connector_state *state =
4442 to_dm_connector_state(connector->state);
4444 if (connector->state)
4445 __drm_atomic_helper_connector_destroy_state(connector->state);
4449 state = kzalloc(sizeof(*state), GFP_KERNEL);
4452 state->scaling = RMX_OFF;
4453 state->underscan_enable = false;
4454 state->underscan_hborder = 0;
4455 state->underscan_vborder = 0;
4456 state->base.max_requested_bpc = 8;
4457 state->vcpi_slots = 0;
4459 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP)
4460 state->abm_level = amdgpu_dm_abm_level;
4462 __drm_atomic_helper_connector_reset(connector, &state->base);
4466 struct drm_connector_state *
4467 amdgpu_dm_connector_atomic_duplicate_state(struct drm_connector *connector)
4469 struct dm_connector_state *state =
4470 to_dm_connector_state(connector->state);
4472 struct dm_connector_state *new_state =
4473 kmemdup(state, sizeof(*state), GFP_KERNEL);
4478 __drm_atomic_helper_connector_duplicate_state(connector, &new_state->base);
4480 new_state->freesync_capable = state->freesync_capable;
4481 new_state->abm_level = state->abm_level;
4482 new_state->scaling = state->scaling;
4483 new_state->underscan_enable = state->underscan_enable;
4484 new_state->underscan_hborder = state->underscan_hborder;
4485 new_state->underscan_vborder = state->underscan_vborder;
4486 new_state->vcpi_slots = state->vcpi_slots;
4487 new_state->pbn = state->pbn;
4488 return &new_state->base;
4491 static const struct drm_connector_funcs amdgpu_dm_connector_funcs = {
4492 .reset = amdgpu_dm_connector_funcs_reset,
4493 .detect = amdgpu_dm_connector_detect,
4494 .fill_modes = drm_helper_probe_single_connector_modes,
4495 .destroy = amdgpu_dm_connector_destroy,
4496 .atomic_duplicate_state = amdgpu_dm_connector_atomic_duplicate_state,
4497 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
4498 .atomic_set_property = amdgpu_dm_connector_atomic_set_property,
4499 .atomic_get_property = amdgpu_dm_connector_atomic_get_property,
4500 .early_unregister = amdgpu_dm_connector_unregister
4503 static int get_modes(struct drm_connector *connector)
4505 return amdgpu_dm_connector_get_modes(connector);
4508 static void create_eml_sink(struct amdgpu_dm_connector *aconnector)
4510 struct dc_sink_init_data init_params = {
4511 .link = aconnector->dc_link,
4512 .sink_signal = SIGNAL_TYPE_VIRTUAL
4516 if (!aconnector->base.edid_blob_ptr) {
4517 DRM_ERROR("No EDID firmware found on connector: %s ,forcing to OFF!\n",
4518 aconnector->base.name);
4520 aconnector->base.force = DRM_FORCE_OFF;
4521 aconnector->base.override_edid = false;
4525 edid = (struct edid *) aconnector->base.edid_blob_ptr->data;
4527 aconnector->edid = edid;
4529 aconnector->dc_em_sink = dc_link_add_remote_sink(
4530 aconnector->dc_link,
4532 (edid->extensions + 1) * EDID_LENGTH,
4535 if (aconnector->base.force == DRM_FORCE_ON) {
4536 aconnector->dc_sink = aconnector->dc_link->local_sink ?
4537 aconnector->dc_link->local_sink :
4538 aconnector->dc_em_sink;
4539 dc_sink_retain(aconnector->dc_sink);
4543 static void handle_edid_mgmt(struct amdgpu_dm_connector *aconnector)
4545 struct dc_link *link = (struct dc_link *)aconnector->dc_link;
4548 * In case of headless boot with force on for DP managed connector
4549 * Those settings have to be != 0 to get initial modeset
4551 if (link->connector_signal == SIGNAL_TYPE_DISPLAY_PORT) {
4552 link->verified_link_cap.lane_count = LANE_COUNT_FOUR;
4553 link->verified_link_cap.link_rate = LINK_RATE_HIGH2;
4557 aconnector->base.override_edid = true;
4558 create_eml_sink(aconnector);
4561 enum drm_mode_status amdgpu_dm_connector_mode_valid(struct drm_connector *connector,
4562 struct drm_display_mode *mode)
4564 int result = MODE_ERROR;
4565 struct dc_sink *dc_sink;
4566 struct amdgpu_device *adev = connector->dev->dev_private;
4567 /* TODO: Unhardcode stream count */
4568 struct dc_stream_state *stream;
4569 struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
4570 enum dc_status dc_result = DC_OK;
4572 if ((mode->flags & DRM_MODE_FLAG_INTERLACE) ||
4573 (mode->flags & DRM_MODE_FLAG_DBLSCAN))
4577 * Only run this the first time mode_valid is called to initilialize
4580 if (aconnector->base.force != DRM_FORCE_UNSPECIFIED &&
4581 !aconnector->dc_em_sink)
4582 handle_edid_mgmt(aconnector);
4584 dc_sink = to_amdgpu_dm_connector(connector)->dc_sink;
4586 if (dc_sink == NULL) {
4587 DRM_ERROR("dc_sink is NULL!\n");
4591 stream = create_stream_for_sink(aconnector, mode, NULL, NULL);
4592 if (stream == NULL) {
4593 DRM_ERROR("Failed to create stream for sink!\n");
4597 dc_result = dc_validate_stream(adev->dm.dc, stream);
4599 if (dc_result == DC_OK)
4602 DRM_DEBUG_KMS("Mode %dx%d (clk %d) failed DC validation with error %d\n",
4608 dc_stream_release(stream);
4611 /* TODO: error handling*/
4615 static int fill_hdr_info_packet(const struct drm_connector_state *state,
4616 struct dc_info_packet *out)
4618 struct hdmi_drm_infoframe frame;
4619 unsigned char buf[30]; /* 26 + 4 */
4623 memset(out, 0, sizeof(*out));
4625 if (!state->hdr_output_metadata)
4628 ret = drm_hdmi_infoframe_set_hdr_metadata(&frame, state);
4632 len = hdmi_drm_infoframe_pack_only(&frame, buf, sizeof(buf));
4636 /* Static metadata is a fixed 26 bytes + 4 byte header. */
4640 /* Prepare the infopacket for DC. */
4641 switch (state->connector->connector_type) {
4642 case DRM_MODE_CONNECTOR_HDMIA:
4643 out->hb0 = 0x87; /* type */
4644 out->hb1 = 0x01; /* version */
4645 out->hb2 = 0x1A; /* length */
4646 out->sb[0] = buf[3]; /* checksum */
4650 case DRM_MODE_CONNECTOR_DisplayPort:
4651 case DRM_MODE_CONNECTOR_eDP:
4652 out->hb0 = 0x00; /* sdp id, zero */
4653 out->hb1 = 0x87; /* type */
4654 out->hb2 = 0x1D; /* payload len - 1 */
4655 out->hb3 = (0x13 << 2); /* sdp version */
4656 out->sb[0] = 0x01; /* version */
4657 out->sb[1] = 0x1A; /* length */
4665 memcpy(&out->sb[i], &buf[4], 26);
4668 print_hex_dump(KERN_DEBUG, "HDR SB:", DUMP_PREFIX_NONE, 16, 1, out->sb,
4669 sizeof(out->sb), false);
4675 is_hdr_metadata_different(const struct drm_connector_state *old_state,
4676 const struct drm_connector_state *new_state)
4678 struct drm_property_blob *old_blob = old_state->hdr_output_metadata;
4679 struct drm_property_blob *new_blob = new_state->hdr_output_metadata;
4681 if (old_blob != new_blob) {
4682 if (old_blob && new_blob &&
4683 old_blob->length == new_blob->length)
4684 return memcmp(old_blob->data, new_blob->data,
4694 amdgpu_dm_connector_atomic_check(struct drm_connector *conn,
4695 struct drm_atomic_state *state)
4697 struct drm_connector_state *new_con_state =
4698 drm_atomic_get_new_connector_state(state, conn);
4699 struct drm_connector_state *old_con_state =
4700 drm_atomic_get_old_connector_state(state, conn);
4701 struct drm_crtc *crtc = new_con_state->crtc;
4702 struct drm_crtc_state *new_crtc_state;
4708 if (is_hdr_metadata_different(old_con_state, new_con_state)) {
4709 struct dc_info_packet hdr_infopacket;
4711 ret = fill_hdr_info_packet(new_con_state, &hdr_infopacket);
4715 new_crtc_state = drm_atomic_get_crtc_state(state, crtc);
4716 if (IS_ERR(new_crtc_state))
4717 return PTR_ERR(new_crtc_state);
4720 * DC considers the stream backends changed if the
4721 * static metadata changes. Forcing the modeset also
4722 * gives a simple way for userspace to switch from
4723 * 8bpc to 10bpc when setting the metadata to enter
4726 * Changing the static metadata after it's been
4727 * set is permissible, however. So only force a
4728 * modeset if we're entering or exiting HDR.
4730 new_crtc_state->mode_changed =
4731 !old_con_state->hdr_output_metadata ||
4732 !new_con_state->hdr_output_metadata;
4738 static const struct drm_connector_helper_funcs
4739 amdgpu_dm_connector_helper_funcs = {
4741 * If hotplugging a second bigger display in FB Con mode, bigger resolution
4742 * modes will be filtered by drm_mode_validate_size(), and those modes
4743 * are missing after user start lightdm. So we need to renew modes list.
4744 * in get_modes call back, not just return the modes count
4746 .get_modes = get_modes,
4747 .mode_valid = amdgpu_dm_connector_mode_valid,
4748 .atomic_check = amdgpu_dm_connector_atomic_check,
4751 static void dm_crtc_helper_disable(struct drm_crtc *crtc)
4755 static bool does_crtc_have_active_cursor(struct drm_crtc_state *new_crtc_state)
4757 struct drm_device *dev = new_crtc_state->crtc->dev;
4758 struct drm_plane *plane;
4760 drm_for_each_plane_mask(plane, dev, new_crtc_state->plane_mask) {
4761 if (plane->type == DRM_PLANE_TYPE_CURSOR)
4768 static int count_crtc_active_planes(struct drm_crtc_state *new_crtc_state)
4770 struct drm_atomic_state *state = new_crtc_state->state;
4771 struct drm_plane *plane;
4774 drm_for_each_plane_mask(plane, state->dev, new_crtc_state->plane_mask) {
4775 struct drm_plane_state *new_plane_state;
4777 /* Cursor planes are "fake". */
4778 if (plane->type == DRM_PLANE_TYPE_CURSOR)
4781 new_plane_state = drm_atomic_get_new_plane_state(state, plane);
4783 if (!new_plane_state) {
4785 * The plane is enable on the CRTC and hasn't changed
4786 * state. This means that it previously passed
4787 * validation and is therefore enabled.
4793 /* We need a framebuffer to be considered enabled. */
4794 num_active += (new_plane_state->fb != NULL);
4801 * Sets whether interrupts should be enabled on a specific CRTC.
4802 * We require that the stream be enabled and that there exist active
4803 * DC planes on the stream.
4806 dm_update_crtc_interrupt_state(struct drm_crtc *crtc,
4807 struct drm_crtc_state *new_crtc_state)
4809 struct dm_crtc_state *dm_new_crtc_state =
4810 to_dm_crtc_state(new_crtc_state);
4812 dm_new_crtc_state->active_planes = 0;
4813 dm_new_crtc_state->interrupts_enabled = false;
4815 if (!dm_new_crtc_state->stream)
4818 dm_new_crtc_state->active_planes =
4819 count_crtc_active_planes(new_crtc_state);
4821 dm_new_crtc_state->interrupts_enabled =
4822 dm_new_crtc_state->active_planes > 0;
4825 static int dm_crtc_helper_atomic_check(struct drm_crtc *crtc,
4826 struct drm_crtc_state *state)
4828 struct amdgpu_device *adev = crtc->dev->dev_private;
4829 struct dc *dc = adev->dm.dc;
4830 struct dm_crtc_state *dm_crtc_state = to_dm_crtc_state(state);
4834 * Update interrupt state for the CRTC. This needs to happen whenever
4835 * the CRTC has changed or whenever any of its planes have changed.
4836 * Atomic check satisfies both of these requirements since the CRTC
4837 * is added to the state by DRM during drm_atomic_helper_check_planes.
4839 dm_update_crtc_interrupt_state(crtc, state);
4841 if (unlikely(!dm_crtc_state->stream &&
4842 modeset_required(state, NULL, dm_crtc_state->stream))) {
4847 /* In some use cases, like reset, no stream is attached */
4848 if (!dm_crtc_state->stream)
4852 * We want at least one hardware plane enabled to use
4853 * the stream with a cursor enabled.
4855 if (state->enable && state->active &&
4856 does_crtc_have_active_cursor(state) &&
4857 dm_crtc_state->active_planes == 0)
4860 if (dc_validate_stream(dc, dm_crtc_state->stream) == DC_OK)
4866 static bool dm_crtc_helper_mode_fixup(struct drm_crtc *crtc,
4867 const struct drm_display_mode *mode,
4868 struct drm_display_mode *adjusted_mode)
4873 static const struct drm_crtc_helper_funcs amdgpu_dm_crtc_helper_funcs = {
4874 .disable = dm_crtc_helper_disable,
4875 .atomic_check = dm_crtc_helper_atomic_check,
4876 .mode_fixup = dm_crtc_helper_mode_fixup
4879 static void dm_encoder_helper_disable(struct drm_encoder *encoder)
4884 static int convert_dc_color_depth_into_bpc (enum dc_color_depth display_color_depth)
4886 switch (display_color_depth) {
4887 case COLOR_DEPTH_666:
4889 case COLOR_DEPTH_888:
4891 case COLOR_DEPTH_101010:
4893 case COLOR_DEPTH_121212:
4895 case COLOR_DEPTH_141414:
4897 case COLOR_DEPTH_161616:
4905 static int dm_encoder_helper_atomic_check(struct drm_encoder *encoder,
4906 struct drm_crtc_state *crtc_state,
4907 struct drm_connector_state *conn_state)
4909 struct drm_atomic_state *state = crtc_state->state;
4910 struct drm_connector *connector = conn_state->connector;
4911 struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
4912 struct dm_connector_state *dm_new_connector_state = to_dm_connector_state(conn_state);
4913 const struct drm_display_mode *adjusted_mode = &crtc_state->adjusted_mode;
4914 struct drm_dp_mst_topology_mgr *mst_mgr;
4915 struct drm_dp_mst_port *mst_port;
4916 enum dc_color_depth color_depth;
4918 bool is_y420 = false;
4920 if (!aconnector->port || !aconnector->dc_sink)
4923 mst_port = aconnector->port;
4924 mst_mgr = &aconnector->mst_port->mst_mgr;
4926 if (!crtc_state->connectors_changed && !crtc_state->mode_changed)
4929 if (!state->duplicated) {
4930 is_y420 = drm_mode_is_420_also(&connector->display_info, adjusted_mode) &&
4931 aconnector->force_yuv420_output;
4932 color_depth = convert_color_depth_from_display_info(connector, conn_state,
4934 bpp = convert_dc_color_depth_into_bpc(color_depth) * 3;
4935 clock = adjusted_mode->clock;
4936 dm_new_connector_state->pbn = drm_dp_calc_pbn_mode(clock, bpp);
4938 dm_new_connector_state->vcpi_slots = drm_dp_atomic_find_vcpi_slots(state,
4941 dm_new_connector_state->pbn);
4942 if (dm_new_connector_state->vcpi_slots < 0) {
4943 DRM_DEBUG_ATOMIC("failed finding vcpi slots: %d\n", (int)dm_new_connector_state->vcpi_slots);
4944 return dm_new_connector_state->vcpi_slots;
4949 const struct drm_encoder_helper_funcs amdgpu_dm_encoder_helper_funcs = {
4950 .disable = dm_encoder_helper_disable,
4951 .atomic_check = dm_encoder_helper_atomic_check
4954 static void dm_drm_plane_reset(struct drm_plane *plane)
4956 struct dm_plane_state *amdgpu_state = NULL;
4959 plane->funcs->atomic_destroy_state(plane, plane->state);
4961 amdgpu_state = kzalloc(sizeof(*amdgpu_state), GFP_KERNEL);
4962 WARN_ON(amdgpu_state == NULL);
4965 __drm_atomic_helper_plane_reset(plane, &amdgpu_state->base);
4968 static struct drm_plane_state *
4969 dm_drm_plane_duplicate_state(struct drm_plane *plane)
4971 struct dm_plane_state *dm_plane_state, *old_dm_plane_state;
4973 old_dm_plane_state = to_dm_plane_state(plane->state);
4974 dm_plane_state = kzalloc(sizeof(*dm_plane_state), GFP_KERNEL);
4975 if (!dm_plane_state)
4978 __drm_atomic_helper_plane_duplicate_state(plane, &dm_plane_state->base);
4980 if (old_dm_plane_state->dc_state) {
4981 dm_plane_state->dc_state = old_dm_plane_state->dc_state;
4982 dc_plane_state_retain(dm_plane_state->dc_state);
4985 return &dm_plane_state->base;
4988 void dm_drm_plane_destroy_state(struct drm_plane *plane,
4989 struct drm_plane_state *state)
4991 struct dm_plane_state *dm_plane_state = to_dm_plane_state(state);
4993 if (dm_plane_state->dc_state)
4994 dc_plane_state_release(dm_plane_state->dc_state);
4996 drm_atomic_helper_plane_destroy_state(plane, state);
4999 static const struct drm_plane_funcs dm_plane_funcs = {
5000 .update_plane = drm_atomic_helper_update_plane,
5001 .disable_plane = drm_atomic_helper_disable_plane,
5002 .destroy = drm_primary_helper_destroy,
5003 .reset = dm_drm_plane_reset,
5004 .atomic_duplicate_state = dm_drm_plane_duplicate_state,
5005 .atomic_destroy_state = dm_drm_plane_destroy_state,
5008 static int dm_plane_helper_prepare_fb(struct drm_plane *plane,
5009 struct drm_plane_state *new_state)
5011 struct amdgpu_framebuffer *afb;
5012 struct drm_gem_object *obj;
5013 struct amdgpu_device *adev;
5014 struct amdgpu_bo *rbo;
5015 struct dm_plane_state *dm_plane_state_new, *dm_plane_state_old;
5016 struct list_head list;
5017 struct ttm_validate_buffer tv;
5018 struct ww_acquire_ctx ticket;
5019 uint64_t tiling_flags;
5023 dm_plane_state_old = to_dm_plane_state(plane->state);
5024 dm_plane_state_new = to_dm_plane_state(new_state);
5026 if (!new_state->fb) {
5027 DRM_DEBUG_DRIVER("No FB bound\n");
5031 afb = to_amdgpu_framebuffer(new_state->fb);
5032 obj = new_state->fb->obj[0];
5033 rbo = gem_to_amdgpu_bo(obj);
5034 adev = amdgpu_ttm_adev(rbo->tbo.bdev);
5035 INIT_LIST_HEAD(&list);
5039 list_add(&tv.head, &list);
5041 r = ttm_eu_reserve_buffers(&ticket, &list, false, NULL);
5043 dev_err(adev->dev, "fail to reserve bo (%d)\n", r);
5047 if (plane->type != DRM_PLANE_TYPE_CURSOR)
5048 domain = amdgpu_display_supported_domains(adev, rbo->flags);
5050 domain = AMDGPU_GEM_DOMAIN_VRAM;
5052 r = amdgpu_bo_pin(rbo, domain);
5053 if (unlikely(r != 0)) {
5054 if (r != -ERESTARTSYS)
5055 DRM_ERROR("Failed to pin framebuffer with error %d\n", r);
5056 ttm_eu_backoff_reservation(&ticket, &list);
5060 r = amdgpu_ttm_alloc_gart(&rbo->tbo);
5061 if (unlikely(r != 0)) {
5062 amdgpu_bo_unpin(rbo);
5063 ttm_eu_backoff_reservation(&ticket, &list);
5064 DRM_ERROR("%p bind failed\n", rbo);
5068 amdgpu_bo_get_tiling_flags(rbo, &tiling_flags);
5070 ttm_eu_backoff_reservation(&ticket, &list);
5072 afb->address = amdgpu_bo_gpu_offset(rbo);
5076 if (dm_plane_state_new->dc_state &&
5077 dm_plane_state_old->dc_state != dm_plane_state_new->dc_state) {
5078 struct dc_plane_state *plane_state = dm_plane_state_new->dc_state;
5080 fill_plane_buffer_attributes(
5081 adev, afb, plane_state->format, plane_state->rotation,
5082 tiling_flags, &plane_state->tiling_info,
5083 &plane_state->plane_size, &plane_state->dcc,
5084 &plane_state->address);
5090 static void dm_plane_helper_cleanup_fb(struct drm_plane *plane,
5091 struct drm_plane_state *old_state)
5093 struct amdgpu_bo *rbo;
5099 rbo = gem_to_amdgpu_bo(old_state->fb->obj[0]);
5100 r = amdgpu_bo_reserve(rbo, false);
5102 DRM_ERROR("failed to reserve rbo before unpin\n");
5106 amdgpu_bo_unpin(rbo);
5107 amdgpu_bo_unreserve(rbo);
5108 amdgpu_bo_unref(&rbo);
5111 static int dm_plane_atomic_check(struct drm_plane *plane,
5112 struct drm_plane_state *state)
5114 struct amdgpu_device *adev = plane->dev->dev_private;
5115 struct dc *dc = adev->dm.dc;
5116 struct dm_plane_state *dm_plane_state;
5117 struct dc_scaling_info scaling_info;
5120 dm_plane_state = to_dm_plane_state(state);
5122 if (!dm_plane_state->dc_state)
5125 ret = fill_dc_scaling_info(state, &scaling_info);
5129 if (dc_validate_plane(dc, dm_plane_state->dc_state) == DC_OK)
5135 static int dm_plane_atomic_async_check(struct drm_plane *plane,
5136 struct drm_plane_state *new_plane_state)
5138 /* Only support async updates on cursor planes. */
5139 if (plane->type != DRM_PLANE_TYPE_CURSOR)
5145 static void dm_plane_atomic_async_update(struct drm_plane *plane,
5146 struct drm_plane_state *new_state)
5148 struct drm_plane_state *old_state =
5149 drm_atomic_get_old_plane_state(new_state->state, plane);
5151 swap(plane->state->fb, new_state->fb);
5153 plane->state->src_x = new_state->src_x;
5154 plane->state->src_y = new_state->src_y;
5155 plane->state->src_w = new_state->src_w;
5156 plane->state->src_h = new_state->src_h;
5157 plane->state->crtc_x = new_state->crtc_x;
5158 plane->state->crtc_y = new_state->crtc_y;
5159 plane->state->crtc_w = new_state->crtc_w;
5160 plane->state->crtc_h = new_state->crtc_h;
5162 handle_cursor_update(plane, old_state);
5165 static const struct drm_plane_helper_funcs dm_plane_helper_funcs = {
5166 .prepare_fb = dm_plane_helper_prepare_fb,
5167 .cleanup_fb = dm_plane_helper_cleanup_fb,
5168 .atomic_check = dm_plane_atomic_check,
5169 .atomic_async_check = dm_plane_atomic_async_check,
5170 .atomic_async_update = dm_plane_atomic_async_update
5174 * TODO: these are currently initialized to rgb formats only.
5175 * For future use cases we should either initialize them dynamically based on
5176 * plane capabilities, or initialize this array to all formats, so internal drm
5177 * check will succeed, and let DC implement proper check
5179 static const uint32_t rgb_formats[] = {
5180 DRM_FORMAT_XRGB8888,
5181 DRM_FORMAT_ARGB8888,
5182 DRM_FORMAT_RGBA8888,
5183 DRM_FORMAT_XRGB2101010,
5184 DRM_FORMAT_XBGR2101010,
5185 DRM_FORMAT_ARGB2101010,
5186 DRM_FORMAT_ABGR2101010,
5187 DRM_FORMAT_XBGR8888,
5188 DRM_FORMAT_ABGR8888,
5192 static const uint32_t overlay_formats[] = {
5193 DRM_FORMAT_XRGB8888,
5194 DRM_FORMAT_ARGB8888,
5195 DRM_FORMAT_RGBA8888,
5196 DRM_FORMAT_XBGR8888,
5197 DRM_FORMAT_ABGR8888,
5201 static const u32 cursor_formats[] = {
5205 static int get_plane_formats(const struct drm_plane *plane,
5206 const struct dc_plane_cap *plane_cap,
5207 uint32_t *formats, int max_formats)
5209 int i, num_formats = 0;
5212 * TODO: Query support for each group of formats directly from
5213 * DC plane caps. This will require adding more formats to the
5217 switch (plane->type) {
5218 case DRM_PLANE_TYPE_PRIMARY:
5219 for (i = 0; i < ARRAY_SIZE(rgb_formats); ++i) {
5220 if (num_formats >= max_formats)
5223 formats[num_formats++] = rgb_formats[i];
5226 if (plane_cap && plane_cap->pixel_format_support.nv12)
5227 formats[num_formats++] = DRM_FORMAT_NV12;
5230 case DRM_PLANE_TYPE_OVERLAY:
5231 for (i = 0; i < ARRAY_SIZE(overlay_formats); ++i) {
5232 if (num_formats >= max_formats)
5235 formats[num_formats++] = overlay_formats[i];
5239 case DRM_PLANE_TYPE_CURSOR:
5240 for (i = 0; i < ARRAY_SIZE(cursor_formats); ++i) {
5241 if (num_formats >= max_formats)
5244 formats[num_formats++] = cursor_formats[i];
5252 static int amdgpu_dm_plane_init(struct amdgpu_display_manager *dm,
5253 struct drm_plane *plane,
5254 unsigned long possible_crtcs,
5255 const struct dc_plane_cap *plane_cap)
5257 uint32_t formats[32];
5261 num_formats = get_plane_formats(plane, plane_cap, formats,
5262 ARRAY_SIZE(formats));
5264 res = drm_universal_plane_init(dm->adev->ddev, plane, possible_crtcs,
5265 &dm_plane_funcs, formats, num_formats,
5266 NULL, plane->type, NULL);
5270 if (plane->type == DRM_PLANE_TYPE_OVERLAY &&
5271 plane_cap && plane_cap->per_pixel_alpha) {
5272 unsigned int blend_caps = BIT(DRM_MODE_BLEND_PIXEL_NONE) |
5273 BIT(DRM_MODE_BLEND_PREMULTI);
5275 drm_plane_create_alpha_property(plane);
5276 drm_plane_create_blend_mode_property(plane, blend_caps);
5279 if (plane->type == DRM_PLANE_TYPE_PRIMARY &&
5280 plane_cap && plane_cap->pixel_format_support.nv12) {
5281 /* This only affects YUV formats. */
5282 drm_plane_create_color_properties(
5284 BIT(DRM_COLOR_YCBCR_BT601) |
5285 BIT(DRM_COLOR_YCBCR_BT709),
5286 BIT(DRM_COLOR_YCBCR_LIMITED_RANGE) |
5287 BIT(DRM_COLOR_YCBCR_FULL_RANGE),
5288 DRM_COLOR_YCBCR_BT709, DRM_COLOR_YCBCR_LIMITED_RANGE);
5291 drm_plane_helper_add(plane, &dm_plane_helper_funcs);
5293 /* Create (reset) the plane state */
5294 if (plane->funcs->reset)
5295 plane->funcs->reset(plane);
5300 static int amdgpu_dm_crtc_init(struct amdgpu_display_manager *dm,
5301 struct drm_plane *plane,
5302 uint32_t crtc_index)
5304 struct amdgpu_crtc *acrtc = NULL;
5305 struct drm_plane *cursor_plane;
5309 cursor_plane = kzalloc(sizeof(*cursor_plane), GFP_KERNEL);
5313 cursor_plane->type = DRM_PLANE_TYPE_CURSOR;
5314 res = amdgpu_dm_plane_init(dm, cursor_plane, 0, NULL);
5316 acrtc = kzalloc(sizeof(struct amdgpu_crtc), GFP_KERNEL);
5320 res = drm_crtc_init_with_planes(
5325 &amdgpu_dm_crtc_funcs, NULL);
5330 drm_crtc_helper_add(&acrtc->base, &amdgpu_dm_crtc_helper_funcs);
5332 /* Create (reset) the plane state */
5333 if (acrtc->base.funcs->reset)
5334 acrtc->base.funcs->reset(&acrtc->base);
5336 acrtc->max_cursor_width = dm->adev->dm.dc->caps.max_cursor_size;
5337 acrtc->max_cursor_height = dm->adev->dm.dc->caps.max_cursor_size;
5339 acrtc->crtc_id = crtc_index;
5340 acrtc->base.enabled = false;
5341 acrtc->otg_inst = -1;
5343 dm->adev->mode_info.crtcs[crtc_index] = acrtc;
5344 drm_crtc_enable_color_mgmt(&acrtc->base, MAX_COLOR_LUT_ENTRIES,
5345 true, MAX_COLOR_LUT_ENTRIES);
5346 drm_mode_crtc_set_gamma_size(&acrtc->base, MAX_COLOR_LEGACY_LUT_ENTRIES);
5352 kfree(cursor_plane);
5357 static int to_drm_connector_type(enum signal_type st)
5360 case SIGNAL_TYPE_HDMI_TYPE_A:
5361 return DRM_MODE_CONNECTOR_HDMIA;
5362 case SIGNAL_TYPE_EDP:
5363 return DRM_MODE_CONNECTOR_eDP;
5364 case SIGNAL_TYPE_LVDS:
5365 return DRM_MODE_CONNECTOR_LVDS;
5366 case SIGNAL_TYPE_RGB:
5367 return DRM_MODE_CONNECTOR_VGA;
5368 case SIGNAL_TYPE_DISPLAY_PORT:
5369 case SIGNAL_TYPE_DISPLAY_PORT_MST:
5370 return DRM_MODE_CONNECTOR_DisplayPort;
5371 case SIGNAL_TYPE_DVI_DUAL_LINK:
5372 case SIGNAL_TYPE_DVI_SINGLE_LINK:
5373 return DRM_MODE_CONNECTOR_DVID;
5374 case SIGNAL_TYPE_VIRTUAL:
5375 return DRM_MODE_CONNECTOR_VIRTUAL;
5378 return DRM_MODE_CONNECTOR_Unknown;
5382 static struct drm_encoder *amdgpu_dm_connector_to_encoder(struct drm_connector *connector)
5384 struct drm_encoder *encoder;
5386 /* There is only one encoder per connector */
5387 drm_connector_for_each_possible_encoder(connector, encoder)
5393 static void amdgpu_dm_get_native_mode(struct drm_connector *connector)
5395 struct drm_encoder *encoder;
5396 struct amdgpu_encoder *amdgpu_encoder;
5398 encoder = amdgpu_dm_connector_to_encoder(connector);
5400 if (encoder == NULL)
5403 amdgpu_encoder = to_amdgpu_encoder(encoder);
5405 amdgpu_encoder->native_mode.clock = 0;
5407 if (!list_empty(&connector->probed_modes)) {
5408 struct drm_display_mode *preferred_mode = NULL;
5410 list_for_each_entry(preferred_mode,
5411 &connector->probed_modes,
5413 if (preferred_mode->type & DRM_MODE_TYPE_PREFERRED)
5414 amdgpu_encoder->native_mode = *preferred_mode;
5422 static struct drm_display_mode *
5423 amdgpu_dm_create_common_mode(struct drm_encoder *encoder,
5425 int hdisplay, int vdisplay)
5427 struct drm_device *dev = encoder->dev;
5428 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
5429 struct drm_display_mode *mode = NULL;
5430 struct drm_display_mode *native_mode = &amdgpu_encoder->native_mode;
5432 mode = drm_mode_duplicate(dev, native_mode);
5437 mode->hdisplay = hdisplay;
5438 mode->vdisplay = vdisplay;
5439 mode->type &= ~DRM_MODE_TYPE_PREFERRED;
5440 strscpy(mode->name, name, DRM_DISPLAY_MODE_LEN);
5446 static void amdgpu_dm_connector_add_common_modes(struct drm_encoder *encoder,
5447 struct drm_connector *connector)
5449 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
5450 struct drm_display_mode *mode = NULL;
5451 struct drm_display_mode *native_mode = &amdgpu_encoder->native_mode;
5452 struct amdgpu_dm_connector *amdgpu_dm_connector =
5453 to_amdgpu_dm_connector(connector);
5457 char name[DRM_DISPLAY_MODE_LEN];
5460 } common_modes[] = {
5461 { "640x480", 640, 480},
5462 { "800x600", 800, 600},
5463 { "1024x768", 1024, 768},
5464 { "1280x720", 1280, 720},
5465 { "1280x800", 1280, 800},
5466 {"1280x1024", 1280, 1024},
5467 { "1440x900", 1440, 900},
5468 {"1680x1050", 1680, 1050},
5469 {"1600x1200", 1600, 1200},
5470 {"1920x1080", 1920, 1080},
5471 {"1920x1200", 1920, 1200}
5474 n = ARRAY_SIZE(common_modes);
5476 for (i = 0; i < n; i++) {
5477 struct drm_display_mode *curmode = NULL;
5478 bool mode_existed = false;
5480 if (common_modes[i].w > native_mode->hdisplay ||
5481 common_modes[i].h > native_mode->vdisplay ||
5482 (common_modes[i].w == native_mode->hdisplay &&
5483 common_modes[i].h == native_mode->vdisplay))
5486 list_for_each_entry(curmode, &connector->probed_modes, head) {
5487 if (common_modes[i].w == curmode->hdisplay &&
5488 common_modes[i].h == curmode->vdisplay) {
5489 mode_existed = true;
5497 mode = amdgpu_dm_create_common_mode(encoder,
5498 common_modes[i].name, common_modes[i].w,
5500 drm_mode_probed_add(connector, mode);
5501 amdgpu_dm_connector->num_modes++;
5505 static void amdgpu_dm_connector_ddc_get_modes(struct drm_connector *connector,
5508 struct amdgpu_dm_connector *amdgpu_dm_connector =
5509 to_amdgpu_dm_connector(connector);
5512 /* empty probed_modes */
5513 INIT_LIST_HEAD(&connector->probed_modes);
5514 amdgpu_dm_connector->num_modes =
5515 drm_add_edid_modes(connector, edid);
5517 /* sorting the probed modes before calling function
5518 * amdgpu_dm_get_native_mode() since EDID can have
5519 * more than one preferred mode. The modes that are
5520 * later in the probed mode list could be of higher
5521 * and preferred resolution. For example, 3840x2160
5522 * resolution in base EDID preferred timing and 4096x2160
5523 * preferred resolution in DID extension block later.
5525 drm_mode_sort(&connector->probed_modes);
5526 amdgpu_dm_get_native_mode(connector);
5528 amdgpu_dm_connector->num_modes = 0;
5532 static int amdgpu_dm_connector_get_modes(struct drm_connector *connector)
5534 struct amdgpu_dm_connector *amdgpu_dm_connector =
5535 to_amdgpu_dm_connector(connector);
5536 struct drm_encoder *encoder;
5537 struct edid *edid = amdgpu_dm_connector->edid;
5539 encoder = amdgpu_dm_connector_to_encoder(connector);
5541 if (!edid || !drm_edid_is_valid(edid)) {
5542 amdgpu_dm_connector->num_modes =
5543 drm_add_modes_noedid(connector, 640, 480);
5545 amdgpu_dm_connector_ddc_get_modes(connector, edid);
5546 amdgpu_dm_connector_add_common_modes(encoder, connector);
5548 amdgpu_dm_fbc_init(connector);
5550 return amdgpu_dm_connector->num_modes;
5553 void amdgpu_dm_connector_init_helper(struct amdgpu_display_manager *dm,
5554 struct amdgpu_dm_connector *aconnector,
5556 struct dc_link *link,
5559 struct amdgpu_device *adev = dm->ddev->dev_private;
5562 * Some of the properties below require access to state, like bpc.
5563 * Allocate some default initial connector state with our reset helper.
5565 if (aconnector->base.funcs->reset)
5566 aconnector->base.funcs->reset(&aconnector->base);
5568 aconnector->connector_id = link_index;
5569 aconnector->dc_link = link;
5570 aconnector->base.interlace_allowed = false;
5571 aconnector->base.doublescan_allowed = false;
5572 aconnector->base.stereo_allowed = false;
5573 aconnector->base.dpms = DRM_MODE_DPMS_OFF;
5574 aconnector->hpd.hpd = AMDGPU_HPD_NONE; /* not used */
5575 aconnector->audio_inst = -1;
5576 mutex_init(&aconnector->hpd_lock);
5579 * configure support HPD hot plug connector_>polled default value is 0
5580 * which means HPD hot plug not supported
5582 switch (connector_type) {
5583 case DRM_MODE_CONNECTOR_HDMIA:
5584 aconnector->base.polled = DRM_CONNECTOR_POLL_HPD;
5585 aconnector->base.ycbcr_420_allowed =
5586 link->link_enc->features.hdmi_ycbcr420_supported ? true : false;
5588 case DRM_MODE_CONNECTOR_DisplayPort:
5589 aconnector->base.polled = DRM_CONNECTOR_POLL_HPD;
5590 aconnector->base.ycbcr_420_allowed =
5591 link->link_enc->features.dp_ycbcr420_supported ? true : false;
5593 case DRM_MODE_CONNECTOR_DVID:
5594 aconnector->base.polled = DRM_CONNECTOR_POLL_HPD;
5600 drm_object_attach_property(&aconnector->base.base,
5601 dm->ddev->mode_config.scaling_mode_property,
5602 DRM_MODE_SCALE_NONE);
5604 drm_object_attach_property(&aconnector->base.base,
5605 adev->mode_info.underscan_property,
5607 drm_object_attach_property(&aconnector->base.base,
5608 adev->mode_info.underscan_hborder_property,
5610 drm_object_attach_property(&aconnector->base.base,
5611 adev->mode_info.underscan_vborder_property,
5614 drm_connector_attach_max_bpc_property(&aconnector->base, 8, 16);
5616 /* This defaults to the max in the range, but we want 8bpc for non-edp. */
5617 aconnector->base.state->max_bpc = (connector_type == DRM_MODE_CONNECTOR_eDP) ? 16 : 8;
5618 aconnector->base.state->max_requested_bpc = aconnector->base.state->max_bpc;
5620 if (connector_type == DRM_MODE_CONNECTOR_eDP &&
5621 dc_is_dmcu_initialized(adev->dm.dc)) {
5622 drm_object_attach_property(&aconnector->base.base,
5623 adev->mode_info.abm_level_property, 0);
5626 if (connector_type == DRM_MODE_CONNECTOR_HDMIA ||
5627 connector_type == DRM_MODE_CONNECTOR_DisplayPort ||
5628 connector_type == DRM_MODE_CONNECTOR_eDP) {
5629 drm_object_attach_property(
5630 &aconnector->base.base,
5631 dm->ddev->mode_config.hdr_output_metadata_property, 0);
5633 drm_connector_attach_vrr_capable_property(
5635 #ifdef CONFIG_DRM_AMD_DC_HDCP
5636 if (adev->asic_type >= CHIP_RAVEN)
5637 drm_connector_attach_content_protection_property(&aconnector->base, true);
5642 static int amdgpu_dm_i2c_xfer(struct i2c_adapter *i2c_adap,
5643 struct i2c_msg *msgs, int num)
5645 struct amdgpu_i2c_adapter *i2c = i2c_get_adapdata(i2c_adap);
5646 struct ddc_service *ddc_service = i2c->ddc_service;
5647 struct i2c_command cmd;
5651 cmd.payloads = kcalloc(num, sizeof(struct i2c_payload), GFP_KERNEL);
5656 cmd.number_of_payloads = num;
5657 cmd.engine = I2C_COMMAND_ENGINE_DEFAULT;
5660 for (i = 0; i < num; i++) {
5661 cmd.payloads[i].write = !(msgs[i].flags & I2C_M_RD);
5662 cmd.payloads[i].address = msgs[i].addr;
5663 cmd.payloads[i].length = msgs[i].len;
5664 cmd.payloads[i].data = msgs[i].buf;
5668 ddc_service->ctx->dc,
5669 ddc_service->ddc_pin->hw_info.ddc_channel,
5673 kfree(cmd.payloads);
5677 static u32 amdgpu_dm_i2c_func(struct i2c_adapter *adap)
5679 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
5682 static const struct i2c_algorithm amdgpu_dm_i2c_algo = {
5683 .master_xfer = amdgpu_dm_i2c_xfer,
5684 .functionality = amdgpu_dm_i2c_func,
5687 static struct amdgpu_i2c_adapter *
5688 create_i2c(struct ddc_service *ddc_service,
5692 struct amdgpu_device *adev = ddc_service->ctx->driver_context;
5693 struct amdgpu_i2c_adapter *i2c;
5695 i2c = kzalloc(sizeof(struct amdgpu_i2c_adapter), GFP_KERNEL);
5698 i2c->base.owner = THIS_MODULE;
5699 i2c->base.class = I2C_CLASS_DDC;
5700 i2c->base.dev.parent = &adev->pdev->dev;
5701 i2c->base.algo = &amdgpu_dm_i2c_algo;
5702 snprintf(i2c->base.name, sizeof(i2c->base.name), "AMDGPU DM i2c hw bus %d", link_index);
5703 i2c_set_adapdata(&i2c->base, i2c);
5704 i2c->ddc_service = ddc_service;
5705 i2c->ddc_service->ddc_pin->hw_info.ddc_channel = link_index;
5712 * Note: this function assumes that dc_link_detect() was called for the
5713 * dc_link which will be represented by this aconnector.
5715 static int amdgpu_dm_connector_init(struct amdgpu_display_manager *dm,
5716 struct amdgpu_dm_connector *aconnector,
5717 uint32_t link_index,
5718 struct amdgpu_encoder *aencoder)
5722 struct dc *dc = dm->dc;
5723 struct dc_link *link = dc_get_link_at_index(dc, link_index);
5724 struct amdgpu_i2c_adapter *i2c;
5726 link->priv = aconnector;
5728 DRM_DEBUG_DRIVER("%s()\n", __func__);
5730 i2c = create_i2c(link->ddc, link->link_index, &res);
5732 DRM_ERROR("Failed to create i2c adapter data\n");
5736 aconnector->i2c = i2c;
5737 res = i2c_add_adapter(&i2c->base);
5740 DRM_ERROR("Failed to register hw i2c %d\n", link->link_index);
5744 connector_type = to_drm_connector_type(link->connector_signal);
5746 res = drm_connector_init_with_ddc(
5749 &amdgpu_dm_connector_funcs,
5754 DRM_ERROR("connector_init failed\n");
5755 aconnector->connector_id = -1;
5759 drm_connector_helper_add(
5761 &amdgpu_dm_connector_helper_funcs);
5763 amdgpu_dm_connector_init_helper(
5770 drm_connector_attach_encoder(
5771 &aconnector->base, &aencoder->base);
5773 drm_connector_register(&aconnector->base);
5774 #if defined(CONFIG_DEBUG_FS)
5775 connector_debugfs_init(aconnector);
5776 aconnector->debugfs_dpcd_address = 0;
5777 aconnector->debugfs_dpcd_size = 0;
5780 if (connector_type == DRM_MODE_CONNECTOR_DisplayPort
5781 || connector_type == DRM_MODE_CONNECTOR_eDP)
5782 amdgpu_dm_initialize_dp_connector(dm, aconnector);
5787 aconnector->i2c = NULL;
5792 int amdgpu_dm_get_encoder_crtc_mask(struct amdgpu_device *adev)
5794 switch (adev->mode_info.num_crtc) {
5811 static int amdgpu_dm_encoder_init(struct drm_device *dev,
5812 struct amdgpu_encoder *aencoder,
5813 uint32_t link_index)
5815 struct amdgpu_device *adev = dev->dev_private;
5817 int res = drm_encoder_init(dev,
5819 &amdgpu_dm_encoder_funcs,
5820 DRM_MODE_ENCODER_TMDS,
5823 aencoder->base.possible_crtcs = amdgpu_dm_get_encoder_crtc_mask(adev);
5826 aencoder->encoder_id = link_index;
5828 aencoder->encoder_id = -1;
5830 drm_encoder_helper_add(&aencoder->base, &amdgpu_dm_encoder_helper_funcs);
5835 static void manage_dm_interrupts(struct amdgpu_device *adev,
5836 struct amdgpu_crtc *acrtc,
5840 * this is not correct translation but will work as soon as VBLANK
5841 * constant is the same as PFLIP
5844 amdgpu_display_crtc_idx_to_irq_type(
5849 drm_crtc_vblank_on(&acrtc->base);
5852 &adev->pageflip_irq,
5858 &adev->pageflip_irq,
5860 drm_crtc_vblank_off(&acrtc->base);
5865 is_scaling_state_different(const struct dm_connector_state *dm_state,
5866 const struct dm_connector_state *old_dm_state)
5868 if (dm_state->scaling != old_dm_state->scaling)
5870 if (!dm_state->underscan_enable && old_dm_state->underscan_enable) {
5871 if (old_dm_state->underscan_hborder != 0 && old_dm_state->underscan_vborder != 0)
5873 } else if (dm_state->underscan_enable && !old_dm_state->underscan_enable) {
5874 if (dm_state->underscan_hborder != 0 && dm_state->underscan_vborder != 0)
5876 } else if (dm_state->underscan_hborder != old_dm_state->underscan_hborder ||
5877 dm_state->underscan_vborder != old_dm_state->underscan_vborder)
5882 #ifdef CONFIG_DRM_AMD_DC_HDCP
5883 static bool is_content_protection_different(struct drm_connector_state *state,
5884 const struct drm_connector_state *old_state,
5885 const struct drm_connector *connector, struct hdcp_workqueue *hdcp_w)
5887 struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
5889 if (old_state->hdcp_content_type != state->hdcp_content_type &&
5890 state->content_protection != DRM_MODE_CONTENT_PROTECTION_UNDESIRED) {
5891 state->content_protection = DRM_MODE_CONTENT_PROTECTION_DESIRED;
5895 /* CP is being re enabled, ignore this */
5896 if (old_state->content_protection == DRM_MODE_CONTENT_PROTECTION_ENABLED &&
5897 state->content_protection == DRM_MODE_CONTENT_PROTECTION_DESIRED) {
5898 state->content_protection = DRM_MODE_CONTENT_PROTECTION_ENABLED;
5902 /* S3 resume case, since old state will always be 0 (UNDESIRED) and the restored state will be ENABLED */
5903 if (old_state->content_protection == DRM_MODE_CONTENT_PROTECTION_UNDESIRED &&
5904 state->content_protection == DRM_MODE_CONTENT_PROTECTION_ENABLED)
5905 state->content_protection = DRM_MODE_CONTENT_PROTECTION_DESIRED;
5907 /* Check if something is connected/enabled, otherwise we start hdcp but nothing is connected/enabled
5908 * hot-plug, headless s3, dpms
5910 if (state->content_protection == DRM_MODE_CONTENT_PROTECTION_DESIRED && connector->dpms == DRM_MODE_DPMS_ON &&
5911 aconnector->dc_sink != NULL)
5914 if (old_state->content_protection == state->content_protection)
5917 if (state->content_protection == DRM_MODE_CONTENT_PROTECTION_UNDESIRED)
5924 static void remove_stream(struct amdgpu_device *adev,
5925 struct amdgpu_crtc *acrtc,
5926 struct dc_stream_state *stream)
5928 /* this is the update mode case */
5930 acrtc->otg_inst = -1;
5931 acrtc->enabled = false;
5934 static int get_cursor_position(struct drm_plane *plane, struct drm_crtc *crtc,
5935 struct dc_cursor_position *position)
5937 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
5939 int xorigin = 0, yorigin = 0;
5941 position->enable = false;
5945 if (!crtc || !plane->state->fb)
5948 if ((plane->state->crtc_w > amdgpu_crtc->max_cursor_width) ||
5949 (plane->state->crtc_h > amdgpu_crtc->max_cursor_height)) {
5950 DRM_ERROR("%s: bad cursor width or height %d x %d\n",
5952 plane->state->crtc_w,
5953 plane->state->crtc_h);
5957 x = plane->state->crtc_x;
5958 y = plane->state->crtc_y;
5960 if (x <= -amdgpu_crtc->max_cursor_width ||
5961 y <= -amdgpu_crtc->max_cursor_height)
5964 if (crtc->primary->state) {
5965 /* avivo cursor are offset into the total surface */
5966 x += crtc->primary->state->src_x >> 16;
5967 y += crtc->primary->state->src_y >> 16;
5971 xorigin = min(-x, amdgpu_crtc->max_cursor_width - 1);
5975 yorigin = min(-y, amdgpu_crtc->max_cursor_height - 1);
5978 position->enable = true;
5981 position->x_hotspot = xorigin;
5982 position->y_hotspot = yorigin;
5987 static void handle_cursor_update(struct drm_plane *plane,
5988 struct drm_plane_state *old_plane_state)
5990 struct amdgpu_device *adev = plane->dev->dev_private;
5991 struct amdgpu_framebuffer *afb = to_amdgpu_framebuffer(plane->state->fb);
5992 struct drm_crtc *crtc = afb ? plane->state->crtc : old_plane_state->crtc;
5993 struct dm_crtc_state *crtc_state = crtc ? to_dm_crtc_state(crtc->state) : NULL;
5994 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
5995 uint64_t address = afb ? afb->address : 0;
5996 struct dc_cursor_position position;
5997 struct dc_cursor_attributes attributes;
6000 if (!plane->state->fb && !old_plane_state->fb)
6003 DRM_DEBUG_DRIVER("%s: crtc_id=%d with size %d to %d\n",
6005 amdgpu_crtc->crtc_id,
6006 plane->state->crtc_w,
6007 plane->state->crtc_h);
6009 ret = get_cursor_position(plane, crtc, &position);
6013 if (!position.enable) {
6014 /* turn off cursor */
6015 if (crtc_state && crtc_state->stream) {
6016 mutex_lock(&adev->dm.dc_lock);
6017 dc_stream_set_cursor_position(crtc_state->stream,
6019 mutex_unlock(&adev->dm.dc_lock);
6024 amdgpu_crtc->cursor_width = plane->state->crtc_w;
6025 amdgpu_crtc->cursor_height = plane->state->crtc_h;
6027 memset(&attributes, 0, sizeof(attributes));
6028 attributes.address.high_part = upper_32_bits(address);
6029 attributes.address.low_part = lower_32_bits(address);
6030 attributes.width = plane->state->crtc_w;
6031 attributes.height = plane->state->crtc_h;
6032 attributes.color_format = CURSOR_MODE_COLOR_PRE_MULTIPLIED_ALPHA;
6033 attributes.rotation_angle = 0;
6034 attributes.attribute_flags.value = 0;
6036 attributes.pitch = attributes.width;
6038 if (crtc_state->stream) {
6039 mutex_lock(&adev->dm.dc_lock);
6040 if (!dc_stream_set_cursor_attributes(crtc_state->stream,
6042 DRM_ERROR("DC failed to set cursor attributes\n");
6044 if (!dc_stream_set_cursor_position(crtc_state->stream,
6046 DRM_ERROR("DC failed to set cursor position\n");
6047 mutex_unlock(&adev->dm.dc_lock);
6051 static void prepare_flip_isr(struct amdgpu_crtc *acrtc)
6054 assert_spin_locked(&acrtc->base.dev->event_lock);
6055 WARN_ON(acrtc->event);
6057 acrtc->event = acrtc->base.state->event;
6059 /* Set the flip status */
6060 acrtc->pflip_status = AMDGPU_FLIP_SUBMITTED;
6062 /* Mark this event as consumed */
6063 acrtc->base.state->event = NULL;
6065 DRM_DEBUG_DRIVER("crtc:%d, pflip_stat:AMDGPU_FLIP_SUBMITTED\n",
6069 static void update_freesync_state_on_stream(
6070 struct amdgpu_display_manager *dm,
6071 struct dm_crtc_state *new_crtc_state,
6072 struct dc_stream_state *new_stream,
6073 struct dc_plane_state *surface,
6074 u32 flip_timestamp_in_us)
6076 struct mod_vrr_params vrr_params;
6077 struct dc_info_packet vrr_infopacket = {0};
6078 struct amdgpu_device *adev = dm->adev;
6079 unsigned long flags;
6085 * TODO: Determine why min/max totals and vrefresh can be 0 here.
6086 * For now it's sufficient to just guard against these conditions.
6089 if (!new_stream->timing.h_total || !new_stream->timing.v_total)
6092 spin_lock_irqsave(&adev->ddev->event_lock, flags);
6093 vrr_params = new_crtc_state->vrr_params;
6096 mod_freesync_handle_preflip(
6097 dm->freesync_module,
6100 flip_timestamp_in_us,
6103 if (adev->family < AMDGPU_FAMILY_AI &&
6104 amdgpu_dm_vrr_active(new_crtc_state)) {
6105 mod_freesync_handle_v_update(dm->freesync_module,
6106 new_stream, &vrr_params);
6108 /* Need to call this before the frame ends. */
6109 dc_stream_adjust_vmin_vmax(dm->dc,
6110 new_crtc_state->stream,
6111 &vrr_params.adjust);
6115 mod_freesync_build_vrr_infopacket(
6116 dm->freesync_module,
6120 TRANSFER_FUNC_UNKNOWN,
6123 new_crtc_state->freesync_timing_changed |=
6124 (memcmp(&new_crtc_state->vrr_params.adjust,
6126 sizeof(vrr_params.adjust)) != 0);
6128 new_crtc_state->freesync_vrr_info_changed |=
6129 (memcmp(&new_crtc_state->vrr_infopacket,
6131 sizeof(vrr_infopacket)) != 0);
6133 new_crtc_state->vrr_params = vrr_params;
6134 new_crtc_state->vrr_infopacket = vrr_infopacket;
6136 new_stream->adjust = new_crtc_state->vrr_params.adjust;
6137 new_stream->vrr_infopacket = vrr_infopacket;
6139 if (new_crtc_state->freesync_vrr_info_changed)
6140 DRM_DEBUG_KMS("VRR packet update: crtc=%u enabled=%d state=%d",
6141 new_crtc_state->base.crtc->base.id,
6142 (int)new_crtc_state->base.vrr_enabled,
6143 (int)vrr_params.state);
6145 spin_unlock_irqrestore(&adev->ddev->event_lock, flags);
6148 static void pre_update_freesync_state_on_stream(
6149 struct amdgpu_display_manager *dm,
6150 struct dm_crtc_state *new_crtc_state)
6152 struct dc_stream_state *new_stream = new_crtc_state->stream;
6153 struct mod_vrr_params vrr_params;
6154 struct mod_freesync_config config = new_crtc_state->freesync_config;
6155 struct amdgpu_device *adev = dm->adev;
6156 unsigned long flags;
6162 * TODO: Determine why min/max totals and vrefresh can be 0 here.
6163 * For now it's sufficient to just guard against these conditions.
6165 if (!new_stream->timing.h_total || !new_stream->timing.v_total)
6168 spin_lock_irqsave(&adev->ddev->event_lock, flags);
6169 vrr_params = new_crtc_state->vrr_params;
6171 if (new_crtc_state->vrr_supported &&
6172 config.min_refresh_in_uhz &&
6173 config.max_refresh_in_uhz) {
6174 config.state = new_crtc_state->base.vrr_enabled ?
6175 VRR_STATE_ACTIVE_VARIABLE :
6178 config.state = VRR_STATE_UNSUPPORTED;
6181 mod_freesync_build_vrr_params(dm->freesync_module,
6183 &config, &vrr_params);
6185 new_crtc_state->freesync_timing_changed |=
6186 (memcmp(&new_crtc_state->vrr_params.adjust,
6188 sizeof(vrr_params.adjust)) != 0);
6190 new_crtc_state->vrr_params = vrr_params;
6191 spin_unlock_irqrestore(&adev->ddev->event_lock, flags);
6194 static void amdgpu_dm_handle_vrr_transition(struct dm_crtc_state *old_state,
6195 struct dm_crtc_state *new_state)
6197 bool old_vrr_active = amdgpu_dm_vrr_active(old_state);
6198 bool new_vrr_active = amdgpu_dm_vrr_active(new_state);
6200 if (!old_vrr_active && new_vrr_active) {
6201 /* Transition VRR inactive -> active:
6202 * While VRR is active, we must not disable vblank irq, as a
6203 * reenable after disable would compute bogus vblank/pflip
6204 * timestamps if it likely happened inside display front-porch.
6206 * We also need vupdate irq for the actual core vblank handling
6209 dm_set_vupdate_irq(new_state->base.crtc, true);
6210 drm_crtc_vblank_get(new_state->base.crtc);
6211 DRM_DEBUG_DRIVER("%s: crtc=%u VRR off->on: Get vblank ref\n",
6212 __func__, new_state->base.crtc->base.id);
6213 } else if (old_vrr_active && !new_vrr_active) {
6214 /* Transition VRR active -> inactive:
6215 * Allow vblank irq disable again for fixed refresh rate.
6217 dm_set_vupdate_irq(new_state->base.crtc, false);
6218 drm_crtc_vblank_put(new_state->base.crtc);
6219 DRM_DEBUG_DRIVER("%s: crtc=%u VRR on->off: Drop vblank ref\n",
6220 __func__, new_state->base.crtc->base.id);
6224 static void amdgpu_dm_commit_cursors(struct drm_atomic_state *state)
6226 struct drm_plane *plane;
6227 struct drm_plane_state *old_plane_state, *new_plane_state;
6231 * TODO: Make this per-stream so we don't issue redundant updates for
6232 * commits with multiple streams.
6234 for_each_oldnew_plane_in_state(state, plane, old_plane_state,
6236 if (plane->type == DRM_PLANE_TYPE_CURSOR)
6237 handle_cursor_update(plane, old_plane_state);
6240 static void amdgpu_dm_commit_planes(struct drm_atomic_state *state,
6241 struct dc_state *dc_state,
6242 struct drm_device *dev,
6243 struct amdgpu_display_manager *dm,
6244 struct drm_crtc *pcrtc,
6245 bool wait_for_vblank)
6248 uint64_t timestamp_ns;
6249 struct drm_plane *plane;
6250 struct drm_plane_state *old_plane_state, *new_plane_state;
6251 struct amdgpu_crtc *acrtc_attach = to_amdgpu_crtc(pcrtc);
6252 struct drm_crtc_state *new_pcrtc_state =
6253 drm_atomic_get_new_crtc_state(state, pcrtc);
6254 struct dm_crtc_state *acrtc_state = to_dm_crtc_state(new_pcrtc_state);
6255 struct dm_crtc_state *dm_old_crtc_state =
6256 to_dm_crtc_state(drm_atomic_get_old_crtc_state(state, pcrtc));
6257 int planes_count = 0, vpos, hpos;
6259 unsigned long flags;
6260 struct amdgpu_bo *abo;
6261 uint64_t tiling_flags;
6262 uint32_t target_vblank, last_flip_vblank;
6263 bool vrr_active = amdgpu_dm_vrr_active(acrtc_state);
6264 bool pflip_present = false;
6265 bool swizzle = true;
6267 struct dc_surface_update surface_updates[MAX_SURFACES];
6268 struct dc_plane_info plane_infos[MAX_SURFACES];
6269 struct dc_scaling_info scaling_infos[MAX_SURFACES];
6270 struct dc_flip_addrs flip_addrs[MAX_SURFACES];
6271 struct dc_stream_update stream_update;
6274 bundle = kzalloc(sizeof(*bundle), GFP_KERNEL);
6277 dm_error("Failed to allocate update bundle\n");
6282 * Disable the cursor first if we're disabling all the planes.
6283 * It'll remain on the screen after the planes are re-enabled
6286 if (acrtc_state->active_planes == 0)
6287 amdgpu_dm_commit_cursors(state);
6289 /* update planes when needed */
6290 for_each_oldnew_plane_in_state(state, plane, old_plane_state, new_plane_state, i) {
6291 struct drm_crtc *crtc = new_plane_state->crtc;
6292 struct drm_crtc_state *new_crtc_state;
6293 struct drm_framebuffer *fb = new_plane_state->fb;
6294 bool plane_needs_flip;
6295 struct dc_plane_state *dc_plane;
6296 struct dm_plane_state *dm_new_plane_state = to_dm_plane_state(new_plane_state);
6298 /* Cursor plane is handled after stream updates */
6299 if (plane->type == DRM_PLANE_TYPE_CURSOR)
6302 if (!fb || !crtc || pcrtc != crtc)
6305 new_crtc_state = drm_atomic_get_new_crtc_state(state, crtc);
6306 if (!new_crtc_state->active)
6309 dc_plane = dm_new_plane_state->dc_state;
6311 if (dc_plane && !dc_plane->tiling_info.gfx9.swizzle)
6314 bundle->surface_updates[planes_count].surface = dc_plane;
6315 if (new_pcrtc_state->color_mgmt_changed) {
6316 bundle->surface_updates[planes_count].gamma = dc_plane->gamma_correction;
6317 bundle->surface_updates[planes_count].in_transfer_func = dc_plane->in_transfer_func;
6320 fill_dc_scaling_info(new_plane_state,
6321 &bundle->scaling_infos[planes_count]);
6323 bundle->surface_updates[planes_count].scaling_info =
6324 &bundle->scaling_infos[planes_count];
6326 plane_needs_flip = old_plane_state->fb && new_plane_state->fb;
6328 pflip_present = pflip_present || plane_needs_flip;
6330 if (!plane_needs_flip) {
6335 abo = gem_to_amdgpu_bo(fb->obj[0]);
6338 * Wait for all fences on this FB. Do limited wait to avoid
6339 * deadlock during GPU reset when this fence will not signal
6340 * but we hold reservation lock for the BO.
6342 r = dma_resv_wait_timeout_rcu(abo->tbo.base.resv, true,
6344 msecs_to_jiffies(5000));
6345 if (unlikely(r <= 0))
6346 DRM_ERROR("Waiting for fences timed out!");
6349 * TODO This might fail and hence better not used, wait
6350 * explicitly on fences instead
6351 * and in general should be called for
6352 * blocking commit to as per framework helpers
6354 r = amdgpu_bo_reserve(abo, true);
6355 if (unlikely(r != 0))
6356 DRM_ERROR("failed to reserve buffer before flip\n");
6358 amdgpu_bo_get_tiling_flags(abo, &tiling_flags);
6360 amdgpu_bo_unreserve(abo);
6362 fill_dc_plane_info_and_addr(
6363 dm->adev, new_plane_state, tiling_flags,
6364 &bundle->plane_infos[planes_count],
6365 &bundle->flip_addrs[planes_count].address);
6367 bundle->surface_updates[planes_count].plane_info =
6368 &bundle->plane_infos[planes_count];
6371 * Only allow immediate flips for fast updates that don't
6372 * change FB pitch, DCC state, rotation or mirroing.
6374 bundle->flip_addrs[planes_count].flip_immediate =
6375 crtc->state->async_flip &&
6376 acrtc_state->update_type == UPDATE_TYPE_FAST;
6378 timestamp_ns = ktime_get_ns();
6379 bundle->flip_addrs[planes_count].flip_timestamp_in_us = div_u64(timestamp_ns, 1000);
6380 bundle->surface_updates[planes_count].flip_addr = &bundle->flip_addrs[planes_count];
6381 bundle->surface_updates[planes_count].surface = dc_plane;
6383 if (!bundle->surface_updates[planes_count].surface) {
6384 DRM_ERROR("No surface for CRTC: id=%d\n",
6385 acrtc_attach->crtc_id);
6389 if (plane == pcrtc->primary)
6390 update_freesync_state_on_stream(
6393 acrtc_state->stream,
6395 bundle->flip_addrs[planes_count].flip_timestamp_in_us);
6397 DRM_DEBUG_DRIVER("%s Flipping to hi: 0x%x, low: 0x%x\n",
6399 bundle->flip_addrs[planes_count].address.grph.addr.high_part,
6400 bundle->flip_addrs[planes_count].address.grph.addr.low_part);
6406 if (pflip_present) {
6408 /* Use old throttling in non-vrr fixed refresh rate mode
6409 * to keep flip scheduling based on target vblank counts
6410 * working in a backwards compatible way, e.g., for
6411 * clients using the GLX_OML_sync_control extension or
6412 * DRI3/Present extension with defined target_msc.
6414 last_flip_vblank = amdgpu_get_vblank_counter_kms(dm->ddev, acrtc_attach->crtc_id);
6417 /* For variable refresh rate mode only:
6418 * Get vblank of last completed flip to avoid > 1 vrr
6419 * flips per video frame by use of throttling, but allow
6420 * flip programming anywhere in the possibly large
6421 * variable vrr vblank interval for fine-grained flip
6422 * timing control and more opportunity to avoid stutter
6423 * on late submission of flips.
6425 spin_lock_irqsave(&pcrtc->dev->event_lock, flags);
6426 last_flip_vblank = acrtc_attach->last_flip_vblank;
6427 spin_unlock_irqrestore(&pcrtc->dev->event_lock, flags);
6430 target_vblank = last_flip_vblank + wait_for_vblank;
6433 * Wait until we're out of the vertical blank period before the one
6434 * targeted by the flip
6436 while ((acrtc_attach->enabled &&
6437 (amdgpu_display_get_crtc_scanoutpos(dm->ddev, acrtc_attach->crtc_id,
6438 0, &vpos, &hpos, NULL,
6439 NULL, &pcrtc->hwmode)
6440 & (DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_IN_VBLANK)) ==
6441 (DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_IN_VBLANK) &&
6442 (int)(target_vblank -
6443 amdgpu_get_vblank_counter_kms(dm->ddev, acrtc_attach->crtc_id)) > 0)) {
6444 usleep_range(1000, 1100);
6447 if (acrtc_attach->base.state->event) {
6448 drm_crtc_vblank_get(pcrtc);
6450 spin_lock_irqsave(&pcrtc->dev->event_lock, flags);
6452 WARN_ON(acrtc_attach->pflip_status != AMDGPU_FLIP_NONE);
6453 prepare_flip_isr(acrtc_attach);
6455 spin_unlock_irqrestore(&pcrtc->dev->event_lock, flags);
6458 if (acrtc_state->stream) {
6459 if (acrtc_state->freesync_vrr_info_changed)
6460 bundle->stream_update.vrr_infopacket =
6461 &acrtc_state->stream->vrr_infopacket;
6465 /* Update the planes if changed or disable if we don't have any. */
6466 if ((planes_count || acrtc_state->active_planes == 0) &&
6467 acrtc_state->stream) {
6468 bundle->stream_update.stream = acrtc_state->stream;
6469 if (new_pcrtc_state->mode_changed) {
6470 bundle->stream_update.src = acrtc_state->stream->src;
6471 bundle->stream_update.dst = acrtc_state->stream->dst;
6474 if (new_pcrtc_state->color_mgmt_changed) {
6476 * TODO: This isn't fully correct since we've actually
6477 * already modified the stream in place.
6479 bundle->stream_update.gamut_remap =
6480 &acrtc_state->stream->gamut_remap_matrix;
6481 bundle->stream_update.output_csc_transform =
6482 &acrtc_state->stream->csc_color_matrix;
6483 bundle->stream_update.out_transfer_func =
6484 acrtc_state->stream->out_transfer_func;
6487 acrtc_state->stream->abm_level = acrtc_state->abm_level;
6488 if (acrtc_state->abm_level != dm_old_crtc_state->abm_level)
6489 bundle->stream_update.abm_level = &acrtc_state->abm_level;
6492 * If FreeSync state on the stream has changed then we need to
6493 * re-adjust the min/max bounds now that DC doesn't handle this
6494 * as part of commit.
6496 if (amdgpu_dm_vrr_active(dm_old_crtc_state) !=
6497 amdgpu_dm_vrr_active(acrtc_state)) {
6498 spin_lock_irqsave(&pcrtc->dev->event_lock, flags);
6499 dc_stream_adjust_vmin_vmax(
6500 dm->dc, acrtc_state->stream,
6501 &acrtc_state->vrr_params.adjust);
6502 spin_unlock_irqrestore(&pcrtc->dev->event_lock, flags);
6504 mutex_lock(&dm->dc_lock);
6505 if ((acrtc_state->update_type > UPDATE_TYPE_FAST) &&
6506 acrtc_state->stream->link->psr_allow_active)
6507 amdgpu_dm_psr_disable(acrtc_state->stream);
6509 dc_commit_updates_for_stream(dm->dc,
6510 bundle->surface_updates,
6512 acrtc_state->stream,
6513 &bundle->stream_update,
6516 if ((acrtc_state->update_type > UPDATE_TYPE_FAST) &&
6517 acrtc_state->stream->psr_version &&
6518 !acrtc_state->stream->link->psr_feature_enabled)
6519 amdgpu_dm_link_setup_psr(acrtc_state->stream);
6520 else if ((acrtc_state->update_type == UPDATE_TYPE_FAST) &&
6521 acrtc_state->stream->link->psr_feature_enabled &&
6522 !acrtc_state->stream->link->psr_allow_active &&
6524 amdgpu_dm_psr_enable(acrtc_state->stream);
6527 mutex_unlock(&dm->dc_lock);
6531 * Update cursor state *after* programming all the planes.
6532 * This avoids redundant programming in the case where we're going
6533 * to be disabling a single plane - those pipes are being disabled.
6535 if (acrtc_state->active_planes)
6536 amdgpu_dm_commit_cursors(state);
6542 static void amdgpu_dm_commit_audio(struct drm_device *dev,
6543 struct drm_atomic_state *state)
6545 struct amdgpu_device *adev = dev->dev_private;
6546 struct amdgpu_dm_connector *aconnector;
6547 struct drm_connector *connector;
6548 struct drm_connector_state *old_con_state, *new_con_state;
6549 struct drm_crtc_state *new_crtc_state;
6550 struct dm_crtc_state *new_dm_crtc_state;
6551 const struct dc_stream_status *status;
6554 /* Notify device removals. */
6555 for_each_oldnew_connector_in_state(state, connector, old_con_state, new_con_state, i) {
6556 if (old_con_state->crtc != new_con_state->crtc) {
6557 /* CRTC changes require notification. */
6561 if (!new_con_state->crtc)
6564 new_crtc_state = drm_atomic_get_new_crtc_state(
6565 state, new_con_state->crtc);
6567 if (!new_crtc_state)
6570 if (!drm_atomic_crtc_needs_modeset(new_crtc_state))
6574 aconnector = to_amdgpu_dm_connector(connector);
6576 mutex_lock(&adev->dm.audio_lock);
6577 inst = aconnector->audio_inst;
6578 aconnector->audio_inst = -1;
6579 mutex_unlock(&adev->dm.audio_lock);
6581 amdgpu_dm_audio_eld_notify(adev, inst);
6584 /* Notify audio device additions. */
6585 for_each_new_connector_in_state(state, connector, new_con_state, i) {
6586 if (!new_con_state->crtc)
6589 new_crtc_state = drm_atomic_get_new_crtc_state(
6590 state, new_con_state->crtc);
6592 if (!new_crtc_state)
6595 if (!drm_atomic_crtc_needs_modeset(new_crtc_state))
6598 new_dm_crtc_state = to_dm_crtc_state(new_crtc_state);
6599 if (!new_dm_crtc_state->stream)
6602 status = dc_stream_get_status(new_dm_crtc_state->stream);
6606 aconnector = to_amdgpu_dm_connector(connector);
6608 mutex_lock(&adev->dm.audio_lock);
6609 inst = status->audio_inst;
6610 aconnector->audio_inst = inst;
6611 mutex_unlock(&adev->dm.audio_lock);
6613 amdgpu_dm_audio_eld_notify(adev, inst);
6618 * Enable interrupts on CRTCs that are newly active, undergone
6619 * a modeset, or have active planes again.
6621 * Done in two passes, based on the for_modeset flag:
6622 * Pass 1: For CRTCs going through modeset
6623 * Pass 2: For CRTCs going from 0 to n active planes
6625 * Interrupts can only be enabled after the planes are programmed,
6626 * so this requires a two-pass approach since we don't want to
6627 * just defer the interrupts until after commit planes every time.
6629 static void amdgpu_dm_enable_crtc_interrupts(struct drm_device *dev,
6630 struct drm_atomic_state *state,
6633 struct amdgpu_device *adev = dev->dev_private;
6634 struct drm_crtc *crtc;
6635 struct drm_crtc_state *old_crtc_state, *new_crtc_state;
6637 #ifdef CONFIG_DEBUG_FS
6638 enum amdgpu_dm_pipe_crc_source source;
6641 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state,
6642 new_crtc_state, i) {
6643 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
6644 struct dm_crtc_state *dm_new_crtc_state =
6645 to_dm_crtc_state(new_crtc_state);
6646 struct dm_crtc_state *dm_old_crtc_state =
6647 to_dm_crtc_state(old_crtc_state);
6648 bool modeset = drm_atomic_crtc_needs_modeset(new_crtc_state);
6651 run_pass = (for_modeset && modeset) ||
6652 (!for_modeset && !modeset &&
6653 !dm_old_crtc_state->interrupts_enabled);
6658 if (!dm_new_crtc_state->interrupts_enabled)
6661 manage_dm_interrupts(adev, acrtc, true);
6663 #ifdef CONFIG_DEBUG_FS
6664 /* The stream has changed so CRC capture needs to re-enabled. */
6665 source = dm_new_crtc_state->crc_src;
6666 if (amdgpu_dm_is_valid_crc_source(source)) {
6667 amdgpu_dm_crtc_configure_crc_source(
6668 crtc, dm_new_crtc_state,
6669 dm_new_crtc_state->crc_src);
6676 * amdgpu_dm_crtc_copy_transient_flags - copy mirrored flags from DRM to DC
6677 * @crtc_state: the DRM CRTC state
6678 * @stream_state: the DC stream state.
6680 * Copy the mirrored transient state flags from DRM, to DC. It is used to bring
6681 * a dc_stream_state's flags in sync with a drm_crtc_state's flags.
6683 static void amdgpu_dm_crtc_copy_transient_flags(struct drm_crtc_state *crtc_state,
6684 struct dc_stream_state *stream_state)
6686 stream_state->mode_changed = drm_atomic_crtc_needs_modeset(crtc_state);
6689 static int amdgpu_dm_atomic_commit(struct drm_device *dev,
6690 struct drm_atomic_state *state,
6693 struct drm_crtc *crtc;
6694 struct drm_crtc_state *old_crtc_state, *new_crtc_state;
6695 struct amdgpu_device *adev = dev->dev_private;
6699 * We evade vblank and pflip interrupts on CRTCs that are undergoing
6700 * a modeset, being disabled, or have no active planes.
6702 * It's done in atomic commit rather than commit tail for now since
6703 * some of these interrupt handlers access the current CRTC state and
6704 * potentially the stream pointer itself.
6706 * Since the atomic state is swapped within atomic commit and not within
6707 * commit tail this would leave to new state (that hasn't been committed yet)
6708 * being accesssed from within the handlers.
6710 * TODO: Fix this so we can do this in commit tail and not have to block
6713 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
6714 struct dm_crtc_state *dm_old_crtc_state = to_dm_crtc_state(old_crtc_state);
6715 struct dm_crtc_state *dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
6716 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
6718 if (dm_old_crtc_state->interrupts_enabled &&
6719 (!dm_new_crtc_state->interrupts_enabled ||
6720 drm_atomic_crtc_needs_modeset(new_crtc_state)))
6721 manage_dm_interrupts(adev, acrtc, false);
6724 * Add check here for SoC's that support hardware cursor plane, to
6725 * unset legacy_cursor_update
6728 return drm_atomic_helper_commit(dev, state, nonblock);
6730 /*TODO Handle EINTR, reenable IRQ*/
6734 * amdgpu_dm_atomic_commit_tail() - AMDgpu DM's commit tail implementation.
6735 * @state: The atomic state to commit
6737 * This will tell DC to commit the constructed DC state from atomic_check,
6738 * programming the hardware. Any failures here implies a hardware failure, since
6739 * atomic check should have filtered anything non-kosher.
6741 static void amdgpu_dm_atomic_commit_tail(struct drm_atomic_state *state)
6743 struct drm_device *dev = state->dev;
6744 struct amdgpu_device *adev = dev->dev_private;
6745 struct amdgpu_display_manager *dm = &adev->dm;
6746 struct dm_atomic_state *dm_state;
6747 struct dc_state *dc_state = NULL, *dc_state_temp = NULL;
6749 struct drm_crtc *crtc;
6750 struct drm_crtc_state *old_crtc_state, *new_crtc_state;
6751 unsigned long flags;
6752 bool wait_for_vblank = true;
6753 struct drm_connector *connector;
6754 struct drm_connector_state *old_con_state, *new_con_state;
6755 struct dm_crtc_state *dm_old_crtc_state, *dm_new_crtc_state;
6756 int crtc_disable_count = 0;
6758 drm_atomic_helper_update_legacy_modeset_state(dev, state);
6760 dm_state = dm_atomic_get_new_state(state);
6761 if (dm_state && dm_state->context) {
6762 dc_state = dm_state->context;
6764 /* No state changes, retain current state. */
6765 dc_state_temp = dc_create_state(dm->dc);
6766 ASSERT(dc_state_temp);
6767 dc_state = dc_state_temp;
6768 dc_resource_state_copy_construct_current(dm->dc, dc_state);
6771 /* update changed items */
6772 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
6773 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
6775 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
6776 dm_old_crtc_state = to_dm_crtc_state(old_crtc_state);
6779 "amdgpu_crtc id:%d crtc_state_flags: enable:%d, active:%d, "
6780 "planes_changed:%d, mode_changed:%d,active_changed:%d,"
6781 "connectors_changed:%d\n",
6783 new_crtc_state->enable,
6784 new_crtc_state->active,
6785 new_crtc_state->planes_changed,
6786 new_crtc_state->mode_changed,
6787 new_crtc_state->active_changed,
6788 new_crtc_state->connectors_changed);
6790 /* Copy all transient state flags into dc state */
6791 if (dm_new_crtc_state->stream) {
6792 amdgpu_dm_crtc_copy_transient_flags(&dm_new_crtc_state->base,
6793 dm_new_crtc_state->stream);
6796 /* handles headless hotplug case, updating new_state and
6797 * aconnector as needed
6800 if (modeset_required(new_crtc_state, dm_new_crtc_state->stream, dm_old_crtc_state->stream)) {
6802 DRM_DEBUG_DRIVER("Atomic commit: SET crtc id %d: [%p]\n", acrtc->crtc_id, acrtc);
6804 if (!dm_new_crtc_state->stream) {
6806 * this could happen because of issues with
6807 * userspace notifications delivery.
6808 * In this case userspace tries to set mode on
6809 * display which is disconnected in fact.
6810 * dc_sink is NULL in this case on aconnector.
6811 * We expect reset mode will come soon.
6813 * This can also happen when unplug is done
6814 * during resume sequence ended
6816 * In this case, we want to pretend we still
6817 * have a sink to keep the pipe running so that
6818 * hw state is consistent with the sw state
6820 DRM_DEBUG_DRIVER("%s: Failed to create new stream for crtc %d\n",
6821 __func__, acrtc->base.base.id);
6825 if (dm_old_crtc_state->stream)
6826 remove_stream(adev, acrtc, dm_old_crtc_state->stream);
6828 pm_runtime_get_noresume(dev->dev);
6830 acrtc->enabled = true;
6831 acrtc->hw_mode = new_crtc_state->mode;
6832 crtc->hwmode = new_crtc_state->mode;
6833 } else if (modereset_required(new_crtc_state)) {
6834 DRM_DEBUG_DRIVER("Atomic commit: RESET. crtc id %d:[%p]\n", acrtc->crtc_id, acrtc);
6835 /* i.e. reset mode */
6836 if (dm_old_crtc_state->stream) {
6837 if (dm_old_crtc_state->stream->link->psr_allow_active)
6838 amdgpu_dm_psr_disable(dm_old_crtc_state->stream);
6840 remove_stream(adev, acrtc, dm_old_crtc_state->stream);
6843 } /* for_each_crtc_in_state() */
6846 dm_enable_per_frame_crtc_master_sync(dc_state);
6847 mutex_lock(&dm->dc_lock);
6848 WARN_ON(!dc_commit_state(dm->dc, dc_state));
6849 mutex_unlock(&dm->dc_lock);
6852 for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) {
6853 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
6855 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
6857 if (dm_new_crtc_state->stream != NULL) {
6858 const struct dc_stream_status *status =
6859 dc_stream_get_status(dm_new_crtc_state->stream);
6862 status = dc_stream_get_status_from_state(dc_state,
6863 dm_new_crtc_state->stream);
6866 DC_ERR("got no status for stream %p on acrtc%p\n", dm_new_crtc_state->stream, acrtc);
6868 acrtc->otg_inst = status->primary_otg_inst;
6871 #ifdef CONFIG_DRM_AMD_DC_HDCP
6872 for_each_oldnew_connector_in_state(state, connector, old_con_state, new_con_state, i) {
6873 struct dm_connector_state *dm_new_con_state = to_dm_connector_state(new_con_state);
6874 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(dm_new_con_state->base.crtc);
6875 struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
6877 new_crtc_state = NULL;
6880 new_crtc_state = drm_atomic_get_new_crtc_state(state, &acrtc->base);
6882 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
6884 if (dm_new_crtc_state && dm_new_crtc_state->stream == NULL &&
6885 connector->state->content_protection == DRM_MODE_CONTENT_PROTECTION_ENABLED) {
6886 hdcp_reset_display(adev->dm.hdcp_workqueue, aconnector->dc_link->link_index);
6887 new_con_state->content_protection = DRM_MODE_CONTENT_PROTECTION_DESIRED;
6891 if (is_content_protection_different(new_con_state, old_con_state, connector, adev->dm.hdcp_workqueue))
6892 hdcp_update_display(
6893 adev->dm.hdcp_workqueue, aconnector->dc_link->link_index, aconnector,
6894 new_con_state->hdcp_content_type,
6895 new_con_state->content_protection == DRM_MODE_CONTENT_PROTECTION_DESIRED ? true
6900 /* Handle connector state changes */
6901 for_each_oldnew_connector_in_state(state, connector, old_con_state, new_con_state, i) {
6902 struct dm_connector_state *dm_new_con_state = to_dm_connector_state(new_con_state);
6903 struct dm_connector_state *dm_old_con_state = to_dm_connector_state(old_con_state);
6904 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(dm_new_con_state->base.crtc);
6905 struct dc_surface_update dummy_updates[MAX_SURFACES];
6906 struct dc_stream_update stream_update;
6907 struct dc_info_packet hdr_packet;
6908 struct dc_stream_status *status = NULL;
6909 bool abm_changed, hdr_changed, scaling_changed;
6911 memset(&dummy_updates, 0, sizeof(dummy_updates));
6912 memset(&stream_update, 0, sizeof(stream_update));
6915 new_crtc_state = drm_atomic_get_new_crtc_state(state, &acrtc->base);
6916 old_crtc_state = drm_atomic_get_old_crtc_state(state, &acrtc->base);
6919 /* Skip any modesets/resets */
6920 if (!acrtc || drm_atomic_crtc_needs_modeset(new_crtc_state))
6923 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
6924 dm_old_crtc_state = to_dm_crtc_state(old_crtc_state);
6926 scaling_changed = is_scaling_state_different(dm_new_con_state,
6929 abm_changed = dm_new_crtc_state->abm_level !=
6930 dm_old_crtc_state->abm_level;
6933 is_hdr_metadata_different(old_con_state, new_con_state);
6935 if (!scaling_changed && !abm_changed && !hdr_changed)
6938 stream_update.stream = dm_new_crtc_state->stream;
6939 if (scaling_changed) {
6940 update_stream_scaling_settings(&dm_new_con_state->base.crtc->mode,
6941 dm_new_con_state, dm_new_crtc_state->stream);
6943 stream_update.src = dm_new_crtc_state->stream->src;
6944 stream_update.dst = dm_new_crtc_state->stream->dst;
6948 dm_new_crtc_state->stream->abm_level = dm_new_crtc_state->abm_level;
6950 stream_update.abm_level = &dm_new_crtc_state->abm_level;
6954 fill_hdr_info_packet(new_con_state, &hdr_packet);
6955 stream_update.hdr_static_metadata = &hdr_packet;
6958 status = dc_stream_get_status(dm_new_crtc_state->stream);
6960 WARN_ON(!status->plane_count);
6963 * TODO: DC refuses to perform stream updates without a dc_surface_update.
6964 * Here we create an empty update on each plane.
6965 * To fix this, DC should permit updating only stream properties.
6967 for (j = 0; j < status->plane_count; j++)
6968 dummy_updates[j].surface = status->plane_states[0];
6971 mutex_lock(&dm->dc_lock);
6972 dc_commit_updates_for_stream(dm->dc,
6974 status->plane_count,
6975 dm_new_crtc_state->stream,
6978 mutex_unlock(&dm->dc_lock);
6981 /* Count number of newly disabled CRTCs for dropping PM refs later. */
6982 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state,
6983 new_crtc_state, i) {
6984 if (old_crtc_state->active && !new_crtc_state->active)
6985 crtc_disable_count++;
6987 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
6988 dm_old_crtc_state = to_dm_crtc_state(old_crtc_state);
6990 /* Update freesync active state. */
6991 pre_update_freesync_state_on_stream(dm, dm_new_crtc_state);
6993 /* Handle vrr on->off / off->on transitions */
6994 amdgpu_dm_handle_vrr_transition(dm_old_crtc_state,
6998 /* Enable interrupts for CRTCs going through a modeset. */
6999 amdgpu_dm_enable_crtc_interrupts(dev, state, true);
7001 for_each_new_crtc_in_state(state, crtc, new_crtc_state, j)
7002 if (new_crtc_state->async_flip)
7003 wait_for_vblank = false;
7005 /* update planes when needed per crtc*/
7006 for_each_new_crtc_in_state(state, crtc, new_crtc_state, j) {
7007 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
7009 if (dm_new_crtc_state->stream)
7010 amdgpu_dm_commit_planes(state, dc_state, dev,
7011 dm, crtc, wait_for_vblank);
7014 /* Enable interrupts for CRTCs going from 0 to n active planes. */
7015 amdgpu_dm_enable_crtc_interrupts(dev, state, false);
7017 /* Update audio instances for each connector. */
7018 amdgpu_dm_commit_audio(dev, state);
7021 * send vblank event on all events not handled in flip and
7022 * mark consumed event for drm_atomic_helper_commit_hw_done
7024 spin_lock_irqsave(&adev->ddev->event_lock, flags);
7025 for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) {
7027 if (new_crtc_state->event)
7028 drm_send_event_locked(dev, &new_crtc_state->event->base);
7030 new_crtc_state->event = NULL;
7032 spin_unlock_irqrestore(&adev->ddev->event_lock, flags);
7034 /* Signal HW programming completion */
7035 drm_atomic_helper_commit_hw_done(state);
7037 if (wait_for_vblank)
7038 drm_atomic_helper_wait_for_flip_done(dev, state);
7040 drm_atomic_helper_cleanup_planes(dev, state);
7043 * Finally, drop a runtime PM reference for each newly disabled CRTC,
7044 * so we can put the GPU into runtime suspend if we're not driving any
7047 for (i = 0; i < crtc_disable_count; i++)
7048 pm_runtime_put_autosuspend(dev->dev);
7049 pm_runtime_mark_last_busy(dev->dev);
7052 dc_release_state(dc_state_temp);
7056 static int dm_force_atomic_commit(struct drm_connector *connector)
7059 struct drm_device *ddev = connector->dev;
7060 struct drm_atomic_state *state = drm_atomic_state_alloc(ddev);
7061 struct amdgpu_crtc *disconnected_acrtc = to_amdgpu_crtc(connector->encoder->crtc);
7062 struct drm_plane *plane = disconnected_acrtc->base.primary;
7063 struct drm_connector_state *conn_state;
7064 struct drm_crtc_state *crtc_state;
7065 struct drm_plane_state *plane_state;
7070 state->acquire_ctx = ddev->mode_config.acquire_ctx;
7072 /* Construct an atomic state to restore previous display setting */
7075 * Attach connectors to drm_atomic_state
7077 conn_state = drm_atomic_get_connector_state(state, connector);
7079 ret = PTR_ERR_OR_ZERO(conn_state);
7083 /* Attach crtc to drm_atomic_state*/
7084 crtc_state = drm_atomic_get_crtc_state(state, &disconnected_acrtc->base);
7086 ret = PTR_ERR_OR_ZERO(crtc_state);
7090 /* force a restore */
7091 crtc_state->mode_changed = true;
7093 /* Attach plane to drm_atomic_state */
7094 plane_state = drm_atomic_get_plane_state(state, plane);
7096 ret = PTR_ERR_OR_ZERO(plane_state);
7101 /* Call commit internally with the state we just constructed */
7102 ret = drm_atomic_commit(state);
7107 DRM_ERROR("Restoring old state failed with %i\n", ret);
7108 drm_atomic_state_put(state);
7114 * This function handles all cases when set mode does not come upon hotplug.
7115 * This includes when a display is unplugged then plugged back into the
7116 * same port and when running without usermode desktop manager supprot
7118 void dm_restore_drm_connector_state(struct drm_device *dev,
7119 struct drm_connector *connector)
7121 struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
7122 struct amdgpu_crtc *disconnected_acrtc;
7123 struct dm_crtc_state *acrtc_state;
7125 if (!aconnector->dc_sink || !connector->state || !connector->encoder)
7128 disconnected_acrtc = to_amdgpu_crtc(connector->encoder->crtc);
7129 if (!disconnected_acrtc)
7132 acrtc_state = to_dm_crtc_state(disconnected_acrtc->base.state);
7133 if (!acrtc_state->stream)
7137 * If the previous sink is not released and different from the current,
7138 * we deduce we are in a state where we can not rely on usermode call
7139 * to turn on the display, so we do it here
7141 if (acrtc_state->stream->sink != aconnector->dc_sink)
7142 dm_force_atomic_commit(&aconnector->base);
7146 * Grabs all modesetting locks to serialize against any blocking commits,
7147 * Waits for completion of all non blocking commits.
7149 static int do_aquire_global_lock(struct drm_device *dev,
7150 struct drm_atomic_state *state)
7152 struct drm_crtc *crtc;
7153 struct drm_crtc_commit *commit;
7157 * Adding all modeset locks to aquire_ctx will
7158 * ensure that when the framework release it the
7159 * extra locks we are locking here will get released to
7161 ret = drm_modeset_lock_all_ctx(dev, state->acquire_ctx);
7165 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
7166 spin_lock(&crtc->commit_lock);
7167 commit = list_first_entry_or_null(&crtc->commit_list,
7168 struct drm_crtc_commit, commit_entry);
7170 drm_crtc_commit_get(commit);
7171 spin_unlock(&crtc->commit_lock);
7177 * Make sure all pending HW programming completed and
7180 ret = wait_for_completion_interruptible_timeout(&commit->hw_done, 10*HZ);
7183 ret = wait_for_completion_interruptible_timeout(
7184 &commit->flip_done, 10*HZ);
7187 DRM_ERROR("[CRTC:%d:%s] hw_done or flip_done "
7188 "timed out\n", crtc->base.id, crtc->name);
7190 drm_crtc_commit_put(commit);
7193 return ret < 0 ? ret : 0;
7196 static void get_freesync_config_for_crtc(
7197 struct dm_crtc_state *new_crtc_state,
7198 struct dm_connector_state *new_con_state)
7200 struct mod_freesync_config config = {0};
7201 struct amdgpu_dm_connector *aconnector =
7202 to_amdgpu_dm_connector(new_con_state->base.connector);
7203 struct drm_display_mode *mode = &new_crtc_state->base.mode;
7204 int vrefresh = drm_mode_vrefresh(mode);
7206 new_crtc_state->vrr_supported = new_con_state->freesync_capable &&
7207 vrefresh >= aconnector->min_vfreq &&
7208 vrefresh <= aconnector->max_vfreq;
7210 if (new_crtc_state->vrr_supported) {
7211 new_crtc_state->stream->ignore_msa_timing_param = true;
7212 config.state = new_crtc_state->base.vrr_enabled ?
7213 VRR_STATE_ACTIVE_VARIABLE :
7215 config.min_refresh_in_uhz =
7216 aconnector->min_vfreq * 1000000;
7217 config.max_refresh_in_uhz =
7218 aconnector->max_vfreq * 1000000;
7219 config.vsif_supported = true;
7223 new_crtc_state->freesync_config = config;
7226 static void reset_freesync_config_for_crtc(
7227 struct dm_crtc_state *new_crtc_state)
7229 new_crtc_state->vrr_supported = false;
7231 memset(&new_crtc_state->vrr_params, 0,
7232 sizeof(new_crtc_state->vrr_params));
7233 memset(&new_crtc_state->vrr_infopacket, 0,
7234 sizeof(new_crtc_state->vrr_infopacket));
7237 static int dm_update_crtc_state(struct amdgpu_display_manager *dm,
7238 struct drm_atomic_state *state,
7239 struct drm_crtc *crtc,
7240 struct drm_crtc_state *old_crtc_state,
7241 struct drm_crtc_state *new_crtc_state,
7243 bool *lock_and_validation_needed)
7245 struct dm_atomic_state *dm_state = NULL;
7246 struct dm_crtc_state *dm_old_crtc_state, *dm_new_crtc_state;
7247 struct dc_stream_state *new_stream;
7251 * TODO Move this code into dm_crtc_atomic_check once we get rid of dc_validation_set
7252 * update changed items
7254 struct amdgpu_crtc *acrtc = NULL;
7255 struct amdgpu_dm_connector *aconnector = NULL;
7256 struct drm_connector_state *drm_new_conn_state = NULL, *drm_old_conn_state = NULL;
7257 struct dm_connector_state *dm_new_conn_state = NULL, *dm_old_conn_state = NULL;
7261 dm_old_crtc_state = to_dm_crtc_state(old_crtc_state);
7262 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
7263 acrtc = to_amdgpu_crtc(crtc);
7264 aconnector = amdgpu_dm_find_first_crtc_matching_connector(state, crtc);
7266 /* TODO This hack should go away */
7267 if (aconnector && enable) {
7268 /* Make sure fake sink is created in plug-in scenario */
7269 drm_new_conn_state = drm_atomic_get_new_connector_state(state,
7271 drm_old_conn_state = drm_atomic_get_old_connector_state(state,
7274 if (IS_ERR(drm_new_conn_state)) {
7275 ret = PTR_ERR_OR_ZERO(drm_new_conn_state);
7279 dm_new_conn_state = to_dm_connector_state(drm_new_conn_state);
7280 dm_old_conn_state = to_dm_connector_state(drm_old_conn_state);
7282 if (!drm_atomic_crtc_needs_modeset(new_crtc_state))
7285 new_stream = create_stream_for_sink(aconnector,
7286 &new_crtc_state->mode,
7288 dm_old_crtc_state->stream);
7291 * we can have no stream on ACTION_SET if a display
7292 * was disconnected during S3, in this case it is not an
7293 * error, the OS will be updated after detection, and
7294 * will do the right thing on next atomic commit
7298 DRM_DEBUG_DRIVER("%s: Failed to create new stream for crtc %d\n",
7299 __func__, acrtc->base.base.id);
7304 dm_new_crtc_state->abm_level = dm_new_conn_state->abm_level;
7306 ret = fill_hdr_info_packet(drm_new_conn_state,
7307 &new_stream->hdr_static_metadata);
7312 * If we already removed the old stream from the context
7313 * (and set the new stream to NULL) then we can't reuse
7314 * the old stream even if the stream and scaling are unchanged.
7315 * We'll hit the BUG_ON and black screen.
7317 * TODO: Refactor this function to allow this check to work
7318 * in all conditions.
7320 if (dm_new_crtc_state->stream &&
7321 dc_is_stream_unchanged(new_stream, dm_old_crtc_state->stream) &&
7322 dc_is_stream_scaling_unchanged(new_stream, dm_old_crtc_state->stream)) {
7323 new_crtc_state->mode_changed = false;
7324 DRM_DEBUG_DRIVER("Mode change not required, setting mode_changed to %d",
7325 new_crtc_state->mode_changed);
7329 /* mode_changed flag may get updated above, need to check again */
7330 if (!drm_atomic_crtc_needs_modeset(new_crtc_state))
7334 "amdgpu_crtc id:%d crtc_state_flags: enable:%d, active:%d, "
7335 "planes_changed:%d, mode_changed:%d,active_changed:%d,"
7336 "connectors_changed:%d\n",
7338 new_crtc_state->enable,
7339 new_crtc_state->active,
7340 new_crtc_state->planes_changed,
7341 new_crtc_state->mode_changed,
7342 new_crtc_state->active_changed,
7343 new_crtc_state->connectors_changed);
7345 /* Remove stream for any changed/disabled CRTC */
7348 if (!dm_old_crtc_state->stream)
7351 ret = dm_atomic_get_state(state, &dm_state);
7355 DRM_DEBUG_DRIVER("Disabling DRM crtc: %d\n",
7358 /* i.e. reset mode */
7359 if (dc_remove_stream_from_ctx(
7362 dm_old_crtc_state->stream) != DC_OK) {
7367 dc_stream_release(dm_old_crtc_state->stream);
7368 dm_new_crtc_state->stream = NULL;
7370 reset_freesync_config_for_crtc(dm_new_crtc_state);
7372 *lock_and_validation_needed = true;
7374 } else {/* Add stream for any updated/enabled CRTC */
7376 * Quick fix to prevent NULL pointer on new_stream when
7377 * added MST connectors not found in existing crtc_state in the chained mode
7378 * TODO: need to dig out the root cause of that
7380 if (!aconnector || (!aconnector->dc_sink && aconnector->mst_port))
7383 if (modereset_required(new_crtc_state))
7386 if (modeset_required(new_crtc_state, new_stream,
7387 dm_old_crtc_state->stream)) {
7389 WARN_ON(dm_new_crtc_state->stream);
7391 ret = dm_atomic_get_state(state, &dm_state);
7395 dm_new_crtc_state->stream = new_stream;
7397 dc_stream_retain(new_stream);
7399 DRM_DEBUG_DRIVER("Enabling DRM crtc: %d\n",
7402 if (dc_add_stream_to_ctx(
7405 dm_new_crtc_state->stream) != DC_OK) {
7410 *lock_and_validation_needed = true;
7415 /* Release extra reference */
7417 dc_stream_release(new_stream);
7420 * We want to do dc stream updates that do not require a
7421 * full modeset below.
7423 if (!(enable && aconnector && new_crtc_state->enable &&
7424 new_crtc_state->active))
7427 * Given above conditions, the dc state cannot be NULL because:
7428 * 1. We're in the process of enabling CRTCs (just been added
7429 * to the dc context, or already is on the context)
7430 * 2. Has a valid connector attached, and
7431 * 3. Is currently active and enabled.
7432 * => The dc stream state currently exists.
7434 BUG_ON(dm_new_crtc_state->stream == NULL);
7436 /* Scaling or underscan settings */
7437 if (is_scaling_state_different(dm_old_conn_state, dm_new_conn_state))
7438 update_stream_scaling_settings(
7439 &new_crtc_state->mode, dm_new_conn_state, dm_new_crtc_state->stream);
7442 dm_new_crtc_state->abm_level = dm_new_conn_state->abm_level;
7445 * Color management settings. We also update color properties
7446 * when a modeset is needed, to ensure it gets reprogrammed.
7448 if (dm_new_crtc_state->base.color_mgmt_changed ||
7449 drm_atomic_crtc_needs_modeset(new_crtc_state)) {
7450 ret = amdgpu_dm_update_crtc_color_mgmt(dm_new_crtc_state);
7455 /* Update Freesync settings. */
7456 get_freesync_config_for_crtc(dm_new_crtc_state,
7463 dc_stream_release(new_stream);
7467 static bool should_reset_plane(struct drm_atomic_state *state,
7468 struct drm_plane *plane,
7469 struct drm_plane_state *old_plane_state,
7470 struct drm_plane_state *new_plane_state)
7472 struct drm_plane *other;
7473 struct drm_plane_state *old_other_state, *new_other_state;
7474 struct drm_crtc_state *new_crtc_state;
7478 * TODO: Remove this hack once the checks below are sufficient
7479 * enough to determine when we need to reset all the planes on
7482 if (state->allow_modeset)
7485 /* Exit early if we know that we're adding or removing the plane. */
7486 if (old_plane_state->crtc != new_plane_state->crtc)
7489 /* old crtc == new_crtc == NULL, plane not in context. */
7490 if (!new_plane_state->crtc)
7494 drm_atomic_get_new_crtc_state(state, new_plane_state->crtc);
7496 if (!new_crtc_state)
7499 /* CRTC Degamma changes currently require us to recreate planes. */
7500 if (new_crtc_state->color_mgmt_changed)
7503 if (drm_atomic_crtc_needs_modeset(new_crtc_state))
7507 * If there are any new primary or overlay planes being added or
7508 * removed then the z-order can potentially change. To ensure
7509 * correct z-order and pipe acquisition the current DC architecture
7510 * requires us to remove and recreate all existing planes.
7512 * TODO: Come up with a more elegant solution for this.
7514 for_each_oldnew_plane_in_state(state, other, old_other_state, new_other_state, i) {
7515 if (other->type == DRM_PLANE_TYPE_CURSOR)
7518 if (old_other_state->crtc != new_plane_state->crtc &&
7519 new_other_state->crtc != new_plane_state->crtc)
7522 if (old_other_state->crtc != new_other_state->crtc)
7525 /* TODO: Remove this once we can handle fast format changes. */
7526 if (old_other_state->fb && new_other_state->fb &&
7527 old_other_state->fb->format != new_other_state->fb->format)
7534 static int dm_update_plane_state(struct dc *dc,
7535 struct drm_atomic_state *state,
7536 struct drm_plane *plane,
7537 struct drm_plane_state *old_plane_state,
7538 struct drm_plane_state *new_plane_state,
7540 bool *lock_and_validation_needed)
7543 struct dm_atomic_state *dm_state = NULL;
7544 struct drm_crtc *new_plane_crtc, *old_plane_crtc;
7545 struct drm_crtc_state *old_crtc_state, *new_crtc_state;
7546 struct dm_crtc_state *dm_new_crtc_state, *dm_old_crtc_state;
7547 struct dm_plane_state *dm_new_plane_state, *dm_old_plane_state;
7552 new_plane_crtc = new_plane_state->crtc;
7553 old_plane_crtc = old_plane_state->crtc;
7554 dm_new_plane_state = to_dm_plane_state(new_plane_state);
7555 dm_old_plane_state = to_dm_plane_state(old_plane_state);
7557 /*TODO Implement atomic check for cursor plane */
7558 if (plane->type == DRM_PLANE_TYPE_CURSOR)
7561 needs_reset = should_reset_plane(state, plane, old_plane_state,
7564 /* Remove any changed/removed planes */
7569 if (!old_plane_crtc)
7572 old_crtc_state = drm_atomic_get_old_crtc_state(
7573 state, old_plane_crtc);
7574 dm_old_crtc_state = to_dm_crtc_state(old_crtc_state);
7576 if (!dm_old_crtc_state->stream)
7579 DRM_DEBUG_ATOMIC("Disabling DRM plane: %d on DRM crtc %d\n",
7580 plane->base.id, old_plane_crtc->base.id);
7582 ret = dm_atomic_get_state(state, &dm_state);
7586 if (!dc_remove_plane_from_context(
7588 dm_old_crtc_state->stream,
7589 dm_old_plane_state->dc_state,
7590 dm_state->context)) {
7597 dc_plane_state_release(dm_old_plane_state->dc_state);
7598 dm_new_plane_state->dc_state = NULL;
7600 *lock_and_validation_needed = true;
7602 } else { /* Add new planes */
7603 struct dc_plane_state *dc_new_plane_state;
7605 if (drm_atomic_plane_disabling(plane->state, new_plane_state))
7608 if (!new_plane_crtc)
7611 new_crtc_state = drm_atomic_get_new_crtc_state(state, new_plane_crtc);
7612 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
7614 if (!dm_new_crtc_state->stream)
7620 WARN_ON(dm_new_plane_state->dc_state);
7622 dc_new_plane_state = dc_create_plane_state(dc);
7623 if (!dc_new_plane_state)
7626 DRM_DEBUG_DRIVER("Enabling DRM plane: %d on DRM crtc %d\n",
7627 plane->base.id, new_plane_crtc->base.id);
7629 ret = fill_dc_plane_attributes(
7630 new_plane_crtc->dev->dev_private,
7635 dc_plane_state_release(dc_new_plane_state);
7639 ret = dm_atomic_get_state(state, &dm_state);
7641 dc_plane_state_release(dc_new_plane_state);
7646 * Any atomic check errors that occur after this will
7647 * not need a release. The plane state will be attached
7648 * to the stream, and therefore part of the atomic
7649 * state. It'll be released when the atomic state is
7652 if (!dc_add_plane_to_context(
7654 dm_new_crtc_state->stream,
7656 dm_state->context)) {
7658 dc_plane_state_release(dc_new_plane_state);
7662 dm_new_plane_state->dc_state = dc_new_plane_state;
7664 /* Tell DC to do a full surface update every time there
7665 * is a plane change. Inefficient, but works for now.
7667 dm_new_plane_state->dc_state->update_flags.bits.full_update = 1;
7669 *lock_and_validation_needed = true;
7677 dm_determine_update_type_for_commit(struct amdgpu_display_manager *dm,
7678 struct drm_atomic_state *state,
7679 enum surface_update_type *out_type)
7681 struct dc *dc = dm->dc;
7682 struct dm_atomic_state *dm_state = NULL, *old_dm_state = NULL;
7683 int i, j, num_plane, ret = 0;
7684 struct drm_plane_state *old_plane_state, *new_plane_state;
7685 struct dm_plane_state *new_dm_plane_state, *old_dm_plane_state;
7686 struct drm_crtc *new_plane_crtc;
7687 struct drm_plane *plane;
7689 struct drm_crtc *crtc;
7690 struct drm_crtc_state *new_crtc_state, *old_crtc_state;
7691 struct dm_crtc_state *new_dm_crtc_state, *old_dm_crtc_state;
7692 struct dc_stream_status *status = NULL;
7694 struct dc_surface_update *updates;
7695 enum surface_update_type update_type = UPDATE_TYPE_FAST;
7697 updates = kcalloc(MAX_SURFACES, sizeof(*updates), GFP_KERNEL);
7700 DRM_ERROR("Failed to allocate plane updates\n");
7701 /* Set type to FULL to avoid crashing in DC*/
7702 update_type = UPDATE_TYPE_FULL;
7706 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
7707 struct dc_scaling_info scaling_info;
7708 struct dc_stream_update stream_update;
7710 memset(&stream_update, 0, sizeof(stream_update));
7712 new_dm_crtc_state = to_dm_crtc_state(new_crtc_state);
7713 old_dm_crtc_state = to_dm_crtc_state(old_crtc_state);
7716 if (new_dm_crtc_state->stream != old_dm_crtc_state->stream) {
7717 update_type = UPDATE_TYPE_FULL;
7721 if (!new_dm_crtc_state->stream)
7724 for_each_oldnew_plane_in_state(state, plane, old_plane_state, new_plane_state, j) {
7725 const struct amdgpu_framebuffer *amdgpu_fb =
7726 to_amdgpu_framebuffer(new_plane_state->fb);
7727 struct dc_plane_info plane_info;
7728 struct dc_flip_addrs flip_addr;
7729 uint64_t tiling_flags;
7731 new_plane_crtc = new_plane_state->crtc;
7732 new_dm_plane_state = to_dm_plane_state(new_plane_state);
7733 old_dm_plane_state = to_dm_plane_state(old_plane_state);
7735 if (plane->type == DRM_PLANE_TYPE_CURSOR)
7738 if (new_dm_plane_state->dc_state != old_dm_plane_state->dc_state) {
7739 update_type = UPDATE_TYPE_FULL;
7743 if (crtc != new_plane_crtc)
7746 updates[num_plane].surface = new_dm_plane_state->dc_state;
7748 if (new_crtc_state->mode_changed) {
7749 stream_update.dst = new_dm_crtc_state->stream->dst;
7750 stream_update.src = new_dm_crtc_state->stream->src;
7753 if (new_crtc_state->color_mgmt_changed) {
7754 updates[num_plane].gamma =
7755 new_dm_plane_state->dc_state->gamma_correction;
7756 updates[num_plane].in_transfer_func =
7757 new_dm_plane_state->dc_state->in_transfer_func;
7758 stream_update.gamut_remap =
7759 &new_dm_crtc_state->stream->gamut_remap_matrix;
7760 stream_update.output_csc_transform =
7761 &new_dm_crtc_state->stream->csc_color_matrix;
7762 stream_update.out_transfer_func =
7763 new_dm_crtc_state->stream->out_transfer_func;
7766 ret = fill_dc_scaling_info(new_plane_state,
7771 updates[num_plane].scaling_info = &scaling_info;
7774 ret = get_fb_info(amdgpu_fb, &tiling_flags);
7778 memset(&flip_addr, 0, sizeof(flip_addr));
7780 ret = fill_dc_plane_info_and_addr(
7781 dm->adev, new_plane_state, tiling_flags,
7783 &flip_addr.address);
7787 updates[num_plane].plane_info = &plane_info;
7788 updates[num_plane].flip_addr = &flip_addr;
7797 ret = dm_atomic_get_state(state, &dm_state);
7801 old_dm_state = dm_atomic_get_old_state(state);
7802 if (!old_dm_state) {
7807 status = dc_stream_get_status_from_state(old_dm_state->context,
7808 new_dm_crtc_state->stream);
7809 stream_update.stream = new_dm_crtc_state->stream;
7811 * TODO: DC modifies the surface during this call so we need
7812 * to lock here - find a way to do this without locking.
7814 mutex_lock(&dm->dc_lock);
7815 update_type = dc_check_update_surfaces_for_stream(dc, updates, num_plane,
7816 &stream_update, status);
7817 mutex_unlock(&dm->dc_lock);
7819 if (update_type > UPDATE_TYPE_MED) {
7820 update_type = UPDATE_TYPE_FULL;
7828 *out_type = update_type;
7833 * amdgpu_dm_atomic_check() - Atomic check implementation for AMDgpu DM.
7834 * @dev: The DRM device
7835 * @state: The atomic state to commit
7837 * Validate that the given atomic state is programmable by DC into hardware.
7838 * This involves constructing a &struct dc_state reflecting the new hardware
7839 * state we wish to commit, then querying DC to see if it is programmable. It's
7840 * important not to modify the existing DC state. Otherwise, atomic_check
7841 * may unexpectedly commit hardware changes.
7843 * When validating the DC state, it's important that the right locks are
7844 * acquired. For full updates case which removes/adds/updates streams on one
7845 * CRTC while flipping on another CRTC, acquiring global lock will guarantee
7846 * that any such full update commit will wait for completion of any outstanding
7847 * flip using DRMs synchronization events. See
7848 * dm_determine_update_type_for_commit()
7850 * Note that DM adds the affected connectors for all CRTCs in state, when that
7851 * might not seem necessary. This is because DC stream creation requires the
7852 * DC sink, which is tied to the DRM connector state. Cleaning this up should
7853 * be possible but non-trivial - a possible TODO item.
7855 * Return: -Error code if validation failed.
7857 static int amdgpu_dm_atomic_check(struct drm_device *dev,
7858 struct drm_atomic_state *state)
7860 struct amdgpu_device *adev = dev->dev_private;
7861 struct dm_atomic_state *dm_state = NULL;
7862 struct dc *dc = adev->dm.dc;
7863 struct drm_connector *connector;
7864 struct drm_connector_state *old_con_state, *new_con_state;
7865 struct drm_crtc *crtc;
7866 struct drm_crtc_state *old_crtc_state, *new_crtc_state;
7867 struct drm_plane *plane;
7868 struct drm_plane_state *old_plane_state, *new_plane_state;
7869 enum surface_update_type update_type = UPDATE_TYPE_FAST;
7870 enum surface_update_type overall_update_type = UPDATE_TYPE_FAST;
7875 * This bool will be set for true for any modeset/reset
7876 * or plane update which implies non fast surface update.
7878 bool lock_and_validation_needed = false;
7880 ret = drm_atomic_helper_check_modeset(dev, state);
7884 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
7885 if (!drm_atomic_crtc_needs_modeset(new_crtc_state) &&
7886 !new_crtc_state->color_mgmt_changed &&
7887 old_crtc_state->vrr_enabled == new_crtc_state->vrr_enabled)
7890 if (!new_crtc_state->enable)
7893 ret = drm_atomic_add_affected_connectors(state, crtc);
7897 ret = drm_atomic_add_affected_planes(state, crtc);
7903 * Add all primary and overlay planes on the CRTC to the state
7904 * whenever a plane is enabled to maintain correct z-ordering
7905 * and to enable fast surface updates.
7907 drm_for_each_crtc(crtc, dev) {
7908 bool modified = false;
7910 for_each_oldnew_plane_in_state(state, plane, old_plane_state, new_plane_state, i) {
7911 if (plane->type == DRM_PLANE_TYPE_CURSOR)
7914 if (new_plane_state->crtc == crtc ||
7915 old_plane_state->crtc == crtc) {
7924 drm_for_each_plane_mask(plane, state->dev, crtc->state->plane_mask) {
7925 if (plane->type == DRM_PLANE_TYPE_CURSOR)
7929 drm_atomic_get_plane_state(state, plane);
7931 if (IS_ERR(new_plane_state)) {
7932 ret = PTR_ERR(new_plane_state);
7938 /* Remove exiting planes if they are modified */
7939 for_each_oldnew_plane_in_state_reverse(state, plane, old_plane_state, new_plane_state, i) {
7940 ret = dm_update_plane_state(dc, state, plane,
7944 &lock_and_validation_needed);
7949 /* Disable all crtcs which require disable */
7950 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
7951 ret = dm_update_crtc_state(&adev->dm, state, crtc,
7955 &lock_and_validation_needed);
7960 /* Enable all crtcs which require enable */
7961 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
7962 ret = dm_update_crtc_state(&adev->dm, state, crtc,
7966 &lock_and_validation_needed);
7971 /* Add new/modified planes */
7972 for_each_oldnew_plane_in_state_reverse(state, plane, old_plane_state, new_plane_state, i) {
7973 ret = dm_update_plane_state(dc, state, plane,
7977 &lock_and_validation_needed);
7982 /* Run this here since we want to validate the streams we created */
7983 ret = drm_atomic_helper_check_planes(dev, state);
7987 /* Perform validation of MST topology in the state*/
7988 ret = drm_dp_mst_atomic_check(state);
7992 if (state->legacy_cursor_update) {
7994 * This is a fast cursor update coming from the plane update
7995 * helper, check if it can be done asynchronously for better
7998 state->async_update =
7999 !drm_atomic_helper_async_check(dev, state);
8002 * Skip the remaining global validation if this is an async
8003 * update. Cursor updates can be done without affecting
8004 * state or bandwidth calcs and this avoids the performance
8005 * penalty of locking the private state object and
8006 * allocating a new dc_state.
8008 if (state->async_update)
8012 /* Check scaling and underscan changes*/
8013 /* TODO Removed scaling changes validation due to inability to commit
8014 * new stream into context w\o causing full reset. Need to
8015 * decide how to handle.
8017 for_each_oldnew_connector_in_state(state, connector, old_con_state, new_con_state, i) {
8018 struct dm_connector_state *dm_old_con_state = to_dm_connector_state(old_con_state);
8019 struct dm_connector_state *dm_new_con_state = to_dm_connector_state(new_con_state);
8020 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(dm_new_con_state->base.crtc);
8022 /* Skip any modesets/resets */
8023 if (!acrtc || drm_atomic_crtc_needs_modeset(
8024 drm_atomic_get_new_crtc_state(state, &acrtc->base)))
8027 /* Skip any thing not scale or underscan changes */
8028 if (!is_scaling_state_different(dm_new_con_state, dm_old_con_state))
8031 overall_update_type = UPDATE_TYPE_FULL;
8032 lock_and_validation_needed = true;
8035 ret = dm_determine_update_type_for_commit(&adev->dm, state, &update_type);
8039 if (overall_update_type < update_type)
8040 overall_update_type = update_type;
8043 * lock_and_validation_needed was an old way to determine if we need to set
8044 * the global lock. Leaving it in to check if we broke any corner cases
8045 * lock_and_validation_needed true = UPDATE_TYPE_FULL or UPDATE_TYPE_MED
8046 * lock_and_validation_needed false = UPDATE_TYPE_FAST
8048 if (lock_and_validation_needed && overall_update_type <= UPDATE_TYPE_FAST)
8049 WARN(1, "Global lock should be Set, overall_update_type should be UPDATE_TYPE_MED or UPDATE_TYPE_FULL");
8051 if (overall_update_type > UPDATE_TYPE_FAST) {
8052 ret = dm_atomic_get_state(state, &dm_state);
8056 ret = do_aquire_global_lock(dev, state);
8060 if (dc_validate_global_state(dc, dm_state->context, false) != DC_OK) {
8066 * The commit is a fast update. Fast updates shouldn't change
8067 * the DC context, affect global validation, and can have their
8068 * commit work done in parallel with other commits not touching
8069 * the same resource. If we have a new DC context as part of
8070 * the DM atomic state from validation we need to free it and
8071 * retain the existing one instead.
8073 struct dm_atomic_state *new_dm_state, *old_dm_state;
8075 new_dm_state = dm_atomic_get_new_state(state);
8076 old_dm_state = dm_atomic_get_old_state(state);
8078 if (new_dm_state && old_dm_state) {
8079 if (new_dm_state->context)
8080 dc_release_state(new_dm_state->context);
8082 new_dm_state->context = old_dm_state->context;
8084 if (old_dm_state->context)
8085 dc_retain_state(old_dm_state->context);
8089 /* Store the overall update type for use later in atomic check. */
8090 for_each_new_crtc_in_state (state, crtc, new_crtc_state, i) {
8091 struct dm_crtc_state *dm_new_crtc_state =
8092 to_dm_crtc_state(new_crtc_state);
8094 dm_new_crtc_state->update_type = (int)overall_update_type;
8097 /* Must be success */
8102 if (ret == -EDEADLK)
8103 DRM_DEBUG_DRIVER("Atomic check stopped to avoid deadlock.\n");
8104 else if (ret == -EINTR || ret == -EAGAIN || ret == -ERESTARTSYS)
8105 DRM_DEBUG_DRIVER("Atomic check stopped due to signal.\n");
8107 DRM_DEBUG_DRIVER("Atomic check failed with err: %d \n", ret);
8112 static bool is_dp_capable_without_timing_msa(struct dc *dc,
8113 struct amdgpu_dm_connector *amdgpu_dm_connector)
8116 bool capable = false;
8118 if (amdgpu_dm_connector->dc_link &&
8119 dm_helpers_dp_read_dpcd(
8121 amdgpu_dm_connector->dc_link,
8122 DP_DOWN_STREAM_PORT_COUNT,
8124 sizeof(dpcd_data))) {
8125 capable = (dpcd_data & DP_MSA_TIMING_PAR_IGNORED) ? true:false;
8130 void amdgpu_dm_update_freesync_caps(struct drm_connector *connector,
8134 bool edid_check_required;
8135 struct detailed_timing *timing;
8136 struct detailed_non_pixel *data;
8137 struct detailed_data_monitor_range *range;
8138 struct amdgpu_dm_connector *amdgpu_dm_connector =
8139 to_amdgpu_dm_connector(connector);
8140 struct dm_connector_state *dm_con_state = NULL;
8142 struct drm_device *dev = connector->dev;
8143 struct amdgpu_device *adev = dev->dev_private;
8144 bool freesync_capable = false;
8146 if (!connector->state) {
8147 DRM_ERROR("%s - Connector has no state", __func__);
8152 dm_con_state = to_dm_connector_state(connector->state);
8154 amdgpu_dm_connector->min_vfreq = 0;
8155 amdgpu_dm_connector->max_vfreq = 0;
8156 amdgpu_dm_connector->pixel_clock_mhz = 0;
8161 dm_con_state = to_dm_connector_state(connector->state);
8163 edid_check_required = false;
8164 if (!amdgpu_dm_connector->dc_sink) {
8165 DRM_ERROR("dc_sink NULL, could not add free_sync module.\n");
8168 if (!adev->dm.freesync_module)
8171 * if edid non zero restrict freesync only for dp and edp
8174 if (amdgpu_dm_connector->dc_sink->sink_signal == SIGNAL_TYPE_DISPLAY_PORT
8175 || amdgpu_dm_connector->dc_sink->sink_signal == SIGNAL_TYPE_EDP) {
8176 edid_check_required = is_dp_capable_without_timing_msa(
8178 amdgpu_dm_connector);
8181 if (edid_check_required == true && (edid->version > 1 ||
8182 (edid->version == 1 && edid->revision > 1))) {
8183 for (i = 0; i < 4; i++) {
8185 timing = &edid->detailed_timings[i];
8186 data = &timing->data.other_data;
8187 range = &data->data.range;
8189 * Check if monitor has continuous frequency mode
8191 if (data->type != EDID_DETAIL_MONITOR_RANGE)
8194 * Check for flag range limits only. If flag == 1 then
8195 * no additional timing information provided.
8196 * Default GTF, GTF Secondary curve and CVT are not
8199 if (range->flags != 1)
8202 amdgpu_dm_connector->min_vfreq = range->min_vfreq;
8203 amdgpu_dm_connector->max_vfreq = range->max_vfreq;
8204 amdgpu_dm_connector->pixel_clock_mhz =
8205 range->pixel_clock_mhz * 10;
8209 if (amdgpu_dm_connector->max_vfreq -
8210 amdgpu_dm_connector->min_vfreq > 10) {
8212 freesync_capable = true;
8218 dm_con_state->freesync_capable = freesync_capable;
8220 if (connector->vrr_capable_property)
8221 drm_connector_set_vrr_capable_property(connector,
8225 static void amdgpu_dm_set_psr_caps(struct dc_link *link)
8227 uint8_t dpcd_data[EDP_PSR_RECEIVER_CAP_SIZE];
8229 if (!(link->connector_signal & SIGNAL_TYPE_EDP))
8231 if (link->type == dc_connection_none)
8233 if (dm_helpers_dp_read_dpcd(NULL, link, DP_PSR_SUPPORT,
8234 dpcd_data, sizeof(dpcd_data))) {
8235 link->psr_feature_enabled = dpcd_data[0] ? true:false;
8236 DRM_INFO("PSR support:%d\n", link->psr_feature_enabled);
8241 * amdgpu_dm_link_setup_psr() - configure psr link
8242 * @stream: stream state
8244 * Return: true if success
8246 static bool amdgpu_dm_link_setup_psr(struct dc_stream_state *stream)
8248 struct dc_link *link = NULL;
8249 struct psr_config psr_config = {0};
8250 struct psr_context psr_context = {0};
8251 struct dc *dc = NULL;
8257 link = stream->link;
8260 psr_config.psr_version = dc->res_pool->dmcu->dmcu_version.psr_version;
8262 if (psr_config.psr_version > 0) {
8263 psr_config.psr_exit_link_training_required = 0x1;
8264 psr_config.psr_frame_capture_indication_req = 0;
8265 psr_config.psr_rfb_setup_time = 0x37;
8266 psr_config.psr_sdp_transmit_line_num_deadline = 0x20;
8267 psr_config.allow_smu_optimizations = 0x0;
8269 ret = dc_link_setup_psr(link, stream, &psr_config, &psr_context);
8272 DRM_DEBUG_DRIVER("PSR link: %d\n", link->psr_feature_enabled);
8278 * amdgpu_dm_psr_enable() - enable psr f/w
8279 * @stream: stream state
8281 * Return: true if success
8283 bool amdgpu_dm_psr_enable(struct dc_stream_state *stream)
8285 struct dc_link *link = stream->link;
8286 struct dc_static_screen_events triggers = {0};
8288 DRM_DEBUG_DRIVER("Enabling psr...\n");
8290 triggers.cursor_update = true;
8291 triggers.overlay_update = true;
8292 triggers.surface_update = true;
8294 dc_stream_set_static_screen_events(link->ctx->dc,
8298 return dc_link_set_psr_allow_active(link, true, false);
8302 * amdgpu_dm_psr_disable() - disable psr f/w
8303 * @stream: stream state
8305 * Return: true if success
8307 static bool amdgpu_dm_psr_disable(struct dc_stream_state *stream)
8310 DRM_DEBUG_DRIVER("Disabling psr...\n");
8312 return dc_link_set_psr_allow_active(stream->link, false, true);