drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

   1 /*
   2  * Copyright 2015 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: AMD
  23  *
  24  */
  25
  26 #include "dm_services_types.h"
  27 #include "dc.h"
  28 #include "dc/inc/core_types.h"
  29
  30 #include "vid.h"
  31 #include "amdgpu.h"
  32 #include "amdgpu_display.h"
  33 #include "atom.h"
  34 #include "amdgpu_dm.h"
  35 #include "amdgpu_pm.h"
  36
  37 #include "amd_shared.h"
  38 #include "amdgpu_dm_irq.h"
  39 #include "dm_helpers.h"
  40 #include "dm_services_types.h"
  41 #include "amdgpu_dm_mst_types.h"
  42 #if defined(CONFIG_DEBUG_FS)
  43 #include "amdgpu_dm_debugfs.h"
  44 #endif
  45
  46 #include "ivsrcid/ivsrcid_vislands30.h"
  47
  48 #include <linux/module.h>
  49 #include <linux/moduleparam.h>
  50 #include <linux/version.h>
  51 #include <linux/types.h>
  52 #include <linux/pm_runtime.h>
  53
  54 #include <drm/drmP.h>
  55 #include <drm/drm_atomic.h>
  56 #include <drm/drm_atomic_helper.h>
  57 #include <drm/drm_dp_mst_helper.h>
  58 #include <drm/drm_fb_helper.h>
  59 #include <drm/drm_edid.h>
  60
  61 #include "modules/inc/mod_freesync.h"
  62
  63 #ifdef CONFIG_X86
  64 #include "ivsrcid/irqsrcs_dcn_1_0.h"
  65
  66 #include "dcn/dcn_1_0_offset.h"
  67 #include "dcn/dcn_1_0_sh_mask.h"
  68 #include "soc15_hw_ip.h"
  69 #include "vega10_ip_offset.h"
  70
  71 #include "soc15_common.h"
  72 #endif
  73
  74 #include "modules/inc/mod_freesync.h"
  75
  76 #include "i2caux_interface.h"
  77
  78 /* basic init/fini API */
  79 static int amdgpu_dm_init(struct amdgpu_device *adev);
  80 static void amdgpu_dm_fini(struct amdgpu_device *adev);
  81
  82 /* initializes drm_device display related structures, based on the information
  83  * provided by DAL. The drm strcutures are: drm_crtc, drm_connector,
  84  * drm_encoder, drm_mode_config
  85  *
  86  * Returns 0 on success
  87  */
  88 static int amdgpu_dm_initialize_drm_device(struct amdgpu_device *adev);
  89 /* removes and deallocates the drm structures, created by the above function */
  90 static void amdgpu_dm_destroy_drm_device(struct amdgpu_display_manager *dm);
  91
  92 static void
  93 amdgpu_dm_update_connector_after_detect(struct amdgpu_dm_connector *aconnector);
  94
  95 static int amdgpu_dm_plane_init(struct amdgpu_display_manager *dm,
  96                                 struct amdgpu_plane *aplane,
  97                                 unsigned long possible_crtcs);
  98 static int amdgpu_dm_crtc_init(struct amdgpu_display_manager *dm,
  99                                struct drm_plane *plane,
 100                                uint32_t link_index);
 101 static int amdgpu_dm_connector_init(struct amdgpu_display_manager *dm,
 102                                     struct amdgpu_dm_connector *amdgpu_dm_connector,
 103                                     uint32_t link_index,
 104                                     struct amdgpu_encoder *amdgpu_encoder);
 105 static int amdgpu_dm_encoder_init(struct drm_device *dev,
 106                                   struct amdgpu_encoder *aencoder,
 107                                   uint32_t link_index);
 108
 109 static int amdgpu_dm_connector_get_modes(struct drm_connector *connector);
 110
 111 static int amdgpu_dm_atomic_commit(struct drm_device *dev,
 112                                    struct drm_atomic_state *state,
 113                                    bool nonblock);
 114
 115 static void amdgpu_dm_atomic_commit_tail(struct drm_atomic_state *state);
 116
 117 static int amdgpu_dm_atomic_check(struct drm_device *dev,
 118                                   struct drm_atomic_state *state);
 119
 120
 121
 122
 123 static const enum drm_plane_type dm_plane_type_default[AMDGPU_MAX_PLANES] = {
 124         DRM_PLANE_TYPE_PRIMARY,
 125         DRM_PLANE_TYPE_PRIMARY,
 126         DRM_PLANE_TYPE_PRIMARY,
 127         DRM_PLANE_TYPE_PRIMARY,
 128         DRM_PLANE_TYPE_PRIMARY,
 129         DRM_PLANE_TYPE_PRIMARY,
 130 };
 131
 132 static const enum drm_plane_type dm_plane_type_carizzo[AMDGPU_MAX_PLANES] = {
 133         DRM_PLANE_TYPE_PRIMARY,
 134         DRM_PLANE_TYPE_PRIMARY,
 135         DRM_PLANE_TYPE_PRIMARY,
 136         DRM_PLANE_TYPE_OVERLAY,/* YUV Capable Underlay */
 137 };
 138
 139 static const enum drm_plane_type dm_plane_type_stoney[AMDGPU_MAX_PLANES] = {
 140         DRM_PLANE_TYPE_PRIMARY,
 141         DRM_PLANE_TYPE_PRIMARY,
 142         DRM_PLANE_TYPE_OVERLAY, /* YUV Capable Underlay */
 143 };
 144
 145 /*
 146  * dm_vblank_get_counter
 147  *
 148  * @brief
 149  * Get counter for number of vertical blanks
 150  *
 151  * @param
 152  * struct amdgpu_device *adev - [in] desired amdgpu device
 153  * int disp_idx - [in] which CRTC to get the counter from
 154  *
 155  * @return
 156  * Counter for vertical blanks
 157  */
 158 static u32 dm_vblank_get_counter(struct amdgpu_device *adev, int crtc)
 159 {
 160         if (crtc >= adev->mode_info.num_crtc)
 161                 return 0;
 162         else {
 163                 struct amdgpu_crtc *acrtc = adev->mode_info.crtcs[crtc];
 164                 struct dm_crtc_state *acrtc_state = to_dm_crtc_state(
 165                                 acrtc->base.state);
 166
 167
 168                 if (acrtc_state->stream == NULL) {
 169                         DRM_ERROR("dc_stream_state is NULL for crtc '%d'!\n",
 170                                   crtc);
 171                         return 0;
 172                 }
 173
 174                 return dc_stream_get_vblank_counter(acrtc_state->stream);
 175         }
 176 }
 177
 178 static int dm_crtc_get_scanoutpos(struct amdgpu_device *adev, int crtc,
 179                                   u32 *vbl, u32 *position)
 180 {
 181         uint32_t v_blank_start, v_blank_end, h_position, v_position;
 182
 183         if ((crtc < 0) || (crtc >= adev->mode_info.num_crtc))
 184                 return -EINVAL;
 185         else {
 186                 struct amdgpu_crtc *acrtc = adev->mode_info.crtcs[crtc];
 187                 struct dm_crtc_state *acrtc_state = to_dm_crtc_state(
 188                                                 acrtc->base.state);
 189
 190                 if (acrtc_state->stream ==  NULL) {
 191                         DRM_ERROR("dc_stream_state is NULL for crtc '%d'!\n",
 192                                   crtc);
 193                         return 0;
 194                 }
 195
 196                 /*
 197                  * TODO rework base driver to use values directly.
 198                  * for now parse it back into reg-format
 199                  */
 200                 dc_stream_get_scanoutpos(acrtc_state->stream,
 201                                          &v_blank_start,
 202                                          &v_blank_end,
 203                                          &h_position,
 204                                          &v_position);
 205
 206                 *position = v_position | (h_position << 16);
 207                 *vbl = v_blank_start | (v_blank_end << 16);
 208         }
 209
 210         return 0;
 211 }
 212
 213 static bool dm_is_idle(void *handle)
 214 {
 215         /* XXX todo */
 216         return true;
 217 }
 218
 219 static int dm_wait_for_idle(void *handle)
 220 {
 221         /* XXX todo */
 222         return 0;
 223 }
 224
 225 static bool dm_check_soft_reset(void *handle)
 226 {
 227         return false;
 228 }
 229
 230 static int dm_soft_reset(void *handle)
 231 {
 232         /* XXX todo */
 233         return 0;
 234 }
 235
 236 static struct amdgpu_crtc *
 237 get_crtc_by_otg_inst(struct amdgpu_device *adev,
 238                      int otg_inst)
 239 {
 240         struct drm_device *dev = adev->ddev;
 241         struct drm_crtc *crtc;
 242         struct amdgpu_crtc *amdgpu_crtc;
 243
 244         /*
 245          * following if is check inherited from both functions where this one is
 246          * used now. Need to be checked why it could happen.
 247          */
 248         if (otg_inst == -1) {
 249                 WARN_ON(1);
 250                 return adev->mode_info.crtcs[0];
 251         }
 252
 253         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
 254                 amdgpu_crtc = to_amdgpu_crtc(crtc);
 255
 256                 if (amdgpu_crtc->otg_inst == otg_inst)
 257                         return amdgpu_crtc;
 258         }
 259
 260         return NULL;
 261 }
 262
 263 static void dm_pflip_high_irq(void *interrupt_params)
 264 {
 265         struct amdgpu_crtc *amdgpu_crtc;
 266         struct common_irq_params *irq_params = interrupt_params;
 267         struct amdgpu_device *adev = irq_params->adev;
 268         unsigned long flags;
 269
 270         amdgpu_crtc = get_crtc_by_otg_inst(adev, irq_params->irq_src - IRQ_TYPE_PFLIP);
 271
 272         /* IRQ could occur when in initial stage */
 273         /*TODO work and BO cleanup */
 274         if (amdgpu_crtc == NULL) {
 275                 DRM_DEBUG_DRIVER("CRTC is null, returning.\n");
 276                 return;
 277         }
 278
 279         spin_lock_irqsave(&adev->ddev->event_lock, flags);
 280
 281         if (amdgpu_crtc->pflip_status != AMDGPU_FLIP_SUBMITTED){
 282                 DRM_DEBUG_DRIVER("amdgpu_crtc->pflip_status = %d !=AMDGPU_FLIP_SUBMITTED(%d) on crtc:%d[%p] \n",
 283                                                  amdgpu_crtc->pflip_status,
 284                                                  AMDGPU_FLIP_SUBMITTED,
 285                                                  amdgpu_crtc->crtc_id,
 286                                                  amdgpu_crtc);
 287                 spin_unlock_irqrestore(&adev->ddev->event_lock, flags);
 288                 return;
 289         }
 290
 291
 292         /* wakeup usersapce */
 293         if (amdgpu_crtc->event) {
 294                 /* Update to correct count/ts if racing with vblank irq */
 295                 drm_crtc_accurate_vblank_count(&amdgpu_crtc->base);
 296
 297                 drm_crtc_send_vblank_event(&amdgpu_crtc->base, amdgpu_crtc->event);
 298
 299                 /* page flip completed. clean up */
 300                 amdgpu_crtc->event = NULL;
 301
 302         } else
 303                 WARN_ON(1);
 304
 305         amdgpu_crtc->pflip_status = AMDGPU_FLIP_NONE;
 306         spin_unlock_irqrestore(&adev->ddev->event_lock, flags);
 307
 308         DRM_DEBUG_DRIVER("%s - crtc :%d[%p], pflip_stat:AMDGPU_FLIP_NONE\n",
 309                                         __func__, amdgpu_crtc->crtc_id, amdgpu_crtc);
 310
 311         drm_crtc_vblank_put(&amdgpu_crtc->base);
 312 }
 313
 314 static void dm_crtc_high_irq(void *interrupt_params)
 315 {
 316         struct common_irq_params *irq_params = interrupt_params;
 317         struct amdgpu_device *adev = irq_params->adev;
 318         uint8_t crtc_index = 0;
 319         struct amdgpu_crtc *acrtc;
 320
 321         acrtc = get_crtc_by_otg_inst(adev, irq_params->irq_src - IRQ_TYPE_VBLANK);
 322
 323         if (acrtc)
 324                 crtc_index = acrtc->crtc_id;
 325
 326         drm_handle_vblank(adev->ddev, crtc_index);
 327         amdgpu_dm_crtc_handle_crc_irq(&acrtc->base);
 328 }
 329
 330 static int dm_set_clockgating_state(void *handle,
 331                   enum amd_clockgating_state state)
 332 {
 333         return 0;
 334 }
 335
 336 static int dm_set_powergating_state(void *handle,
 337                   enum amd_powergating_state state)
 338 {
 339         return 0;
 340 }
 341
 342 /* Prototypes of private functions */
 343 static int dm_early_init(void* handle);
 344
 345 static void hotplug_notify_work_func(struct work_struct *work)
 346 {
 347         struct amdgpu_display_manager *dm = container_of(work, struct amdgpu_display_manager, mst_hotplug_work);
 348         struct drm_device *dev = dm->ddev;
 349
 350         drm_kms_helper_hotplug_event(dev);
 351 }
 352
 353 /* Allocate memory for FBC compressed data  */
 354 static void amdgpu_dm_fbc_init(struct drm_connector *connector)
 355 {
 356         struct drm_device *dev = connector->dev;
 357         struct amdgpu_device *adev = dev->dev_private;
 358         struct dm_comressor_info *compressor = &adev->dm.compressor;
 359         struct amdgpu_dm_connector *aconn = to_amdgpu_dm_connector(connector);
 360         struct drm_display_mode *mode;
 361         unsigned long max_size = 0;
 362
 363         if (adev->dm.dc->fbc_compressor == NULL)
 364                 return;
 365
 366         if (aconn->dc_link->connector_signal != SIGNAL_TYPE_EDP)
 367                 return;
 368
 369         if (compressor->bo_ptr)
 370                 return;
 371
 372
 373         list_for_each_entry(mode, &connector->modes, head) {
 374                 if (max_size < mode->htotal * mode->vtotal)
 375                         max_size = mode->htotal * mode->vtotal;
 376         }
 377
 378         if (max_size) {
 379                 int r = amdgpu_bo_create_kernel(adev, max_size * 4, PAGE_SIZE,
 380                             AMDGPU_GEM_DOMAIN_GTT, &compressor->bo_ptr,
 381                             &compressor->gpu_addr, &compressor->cpu_addr);
 382
 383                 if (r)
 384                         DRM_ERROR("DM: Failed to initialize FBC\n");
 385                 else {
 386                         adev->dm.dc->ctx->fbc_gpu_addr = compressor->gpu_addr;
 387                         DRM_INFO("DM: FBC alloc %lu\n", max_size*4);
 388                 }
 389
 390         }
 391
 392 }
 393
 394
 395 /* Init display KMS
 396  *
 397  * Returns 0 on success
 398  */
 399 static int amdgpu_dm_init(struct amdgpu_device *adev)
 400 {
 401         struct dc_init_data init_data;
 402         adev->dm.ddev = adev->ddev;
 403         adev->dm.adev = adev;
 404
 405         /* Zero all the fields */
 406         memset(&init_data, 0, sizeof(init_data));
 407
 408         if(amdgpu_dm_irq_init(adev)) {
 409                 DRM_ERROR("amdgpu: failed to initialize DM IRQ support.\n");
 410                 goto error;
 411         }
 412
 413         init_data.asic_id.chip_family = adev->family;
 414
 415         init_data.asic_id.pci_revision_id = adev->rev_id;
 416         init_data.asic_id.hw_internal_rev = adev->external_rev_id;
 417
 418         init_data.asic_id.vram_width = adev->gmc.vram_width;
 419         /* TODO: initialize init_data.asic_id.vram_type here!!!! */
 420         init_data.asic_id.atombios_base_address =
 421                 adev->mode_info.atom_context->bios;
 422
 423         init_data.driver = adev;
 424
 425         adev->dm.cgs_device = amdgpu_cgs_create_device(adev);
 426
 427         if (!adev->dm.cgs_device) {
 428                 DRM_ERROR("amdgpu: failed to create cgs device.\n");
 429                 goto error;
 430         }
 431
 432         init_data.cgs_device = adev->dm.cgs_device;
 433
 434         adev->dm.dal = NULL;
 435
 436         init_data.dce_environment = DCE_ENV_PRODUCTION_DRV;
 437
 438         /*
 439          * TODO debug why this doesn't work on Raven
 440          */
 441         if (adev->flags & AMD_IS_APU &&
 442             adev->asic_type >= CHIP_CARRIZO &&
 443             adev->asic_type < CHIP_RAVEN)
 444                 init_data.flags.gpu_vm_support = true;
 445
 446         /* Display Core create. */
 447         adev->dm.dc = dc_create(&init_data);
 448
 449         if (adev->dm.dc) {
 450                 DRM_INFO("Display Core initialized with v%s!\n", DC_VER);
 451         } else {
 452                 DRM_INFO("Display Core failed to initialize with v%s!\n", DC_VER);
 453                 goto error;
 454         }
 455
 456         INIT_WORK(&adev->dm.mst_hotplug_work, hotplug_notify_work_func);
 457
 458         adev->dm.freesync_module = mod_freesync_create(adev->dm.dc);
 459         if (!adev->dm.freesync_module) {
 460                 DRM_ERROR(
 461                 "amdgpu: failed to initialize freesync_module.\n");
 462         } else
 463                 DRM_DEBUG_DRIVER("amdgpu: freesync_module init done %p.\n",
 464                                 adev->dm.freesync_module);
 465
 466         amdgpu_dm_init_color_mod();
 467
 468         if (amdgpu_dm_initialize_drm_device(adev)) {
 469                 DRM_ERROR(
 470                 "amdgpu: failed to initialize sw for display support.\n");
 471                 goto error;
 472         }
 473
 474         /* Update the actual used number of crtc */
 475         adev->mode_info.num_crtc = adev->dm.display_indexes_num;
 476
 477         /* TODO: Add_display_info? */
 478
 479         /* TODO use dynamic cursor width */
 480         adev->ddev->mode_config.cursor_width = adev->dm.dc->caps.max_cursor_size;
 481         adev->ddev->mode_config.cursor_height = adev->dm.dc->caps.max_cursor_size;
 482
 483         if (drm_vblank_init(adev->ddev, adev->dm.display_indexes_num)) {
 484                 DRM_ERROR(
 485                 "amdgpu: failed to initialize sw for display support.\n");
 486                 goto error;
 487         }
 488
 489         DRM_DEBUG_DRIVER("KMS initialized.\n");
 490
 491         return 0;
 492 error:
 493         amdgpu_dm_fini(adev);
 494
 495         return -1;
 496 }
 497
 498 static void amdgpu_dm_fini(struct amdgpu_device *adev)
 499 {
 500         amdgpu_dm_destroy_drm_device(&adev->dm);
 501         /*
 502          * TODO: pageflip, vlank interrupt
 503          *
 504          * amdgpu_dm_irq_fini(adev);
 505          */
 506
 507         if (adev->dm.cgs_device) {
 508                 amdgpu_cgs_destroy_device(adev->dm.cgs_device);
 509                 adev->dm.cgs_device = NULL;
 510         }
 511         if (adev->dm.freesync_module) {
 512                 mod_freesync_destroy(adev->dm.freesync_module);
 513                 adev->dm.freesync_module = NULL;
 514         }
 515         /* DC Destroy TODO: Replace destroy DAL */
 516         if (adev->dm.dc)
 517                 dc_destroy(&adev->dm.dc);
 518         return;
 519 }
 520
 521 static int dm_sw_init(void *handle)
 522 {
 523         return 0;
 524 }
 525
 526 static int dm_sw_fini(void *handle)
 527 {
 528         return 0;
 529 }
 530
 531 static int detect_mst_link_for_all_connectors(struct drm_device *dev)
 532 {
 533         struct amdgpu_dm_connector *aconnector;
 534         struct drm_connector *connector;
 535         int ret = 0;
 536
 537         drm_modeset_lock(&dev->mode_config.connection_mutex, NULL);
 538
 539         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
 540                 aconnector = to_amdgpu_dm_connector(connector);
 541                 if (aconnector->dc_link->type == dc_connection_mst_branch &&
 542                     aconnector->mst_mgr.aux) {
 543                         DRM_DEBUG_DRIVER("DM_MST: starting TM on aconnector: %p [id: %d]\n",
 544                                         aconnector, aconnector->base.base.id);
 545
 546                         ret = drm_dp_mst_topology_mgr_set_mst(&aconnector->mst_mgr, true);
 547                         if (ret < 0) {
 548                                 DRM_ERROR("DM_MST: Failed to start MST\n");
 549                                 ((struct dc_link *)aconnector->dc_link)->type = dc_connection_single;
 550                                 return ret;
 551                                 }
 552                         }
 553         }
 554
 555         drm_modeset_unlock(&dev->mode_config.connection_mutex);
 556         return ret;
 557 }
 558
 559 static int dm_late_init(void *handle)
 560 {
 561         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 562
 563         return detect_mst_link_for_all_connectors(adev->ddev);
 564 }
 565
 566 static void s3_handle_mst(struct drm_device *dev, bool suspend)
 567 {
 568         struct amdgpu_dm_connector *aconnector;
 569         struct drm_connector *connector;
 570
 571         drm_modeset_lock(&dev->mode_config.connection_mutex, NULL);
 572
 573         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
 574                    aconnector = to_amdgpu_dm_connector(connector);
 575                    if (aconnector->dc_link->type == dc_connection_mst_branch &&
 576                                    !aconnector->mst_port) {
 577
 578                            if (suspend)
 579                                    drm_dp_mst_topology_mgr_suspend(&aconnector->mst_mgr);
 580                            else
 581                                    drm_dp_mst_topology_mgr_resume(&aconnector->mst_mgr);
 582                    }
 583         }
 584
 585         drm_modeset_unlock(&dev->mode_config.connection_mutex);
 586 }
 587
 588 static int dm_hw_init(void *handle)
 589 {
 590         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 591         /* Create DAL display manager */
 592         amdgpu_dm_init(adev);
 593         amdgpu_dm_hpd_init(adev);
 594
 595         return 0;
 596 }
 597
 598 static int dm_hw_fini(void *handle)
 599 {
 600         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 601
 602         amdgpu_dm_hpd_fini(adev);
 603
 604         amdgpu_dm_irq_fini(adev);
 605         amdgpu_dm_fini(adev);
 606         return 0;
 607 }
 608
 609 static int dm_suspend(void *handle)
 610 {
 611         struct amdgpu_device *adev = handle;
 612         struct amdgpu_display_manager *dm = &adev->dm;
 613         int ret = 0;
 614
 615         s3_handle_mst(adev->ddev, true);
 616
 617         amdgpu_dm_irq_suspend(adev);
 618
 619         WARN_ON(adev->dm.cached_state);
 620         adev->dm.cached_state = drm_atomic_helper_suspend(adev->ddev);
 621
 622         dc_set_power_state(dm->dc, DC_ACPI_CM_POWER_STATE_D3);
 623
 624         return ret;
 625 }
 626
 627 static struct amdgpu_dm_connector *
 628 amdgpu_dm_find_first_crtc_matching_connector(struct drm_atomic_state *state,
 629                                              struct drm_crtc *crtc)
 630 {
 631         uint32_t i;
 632         struct drm_connector_state *new_con_state;
 633         struct drm_connector *connector;
 634         struct drm_crtc *crtc_from_state;
 635
 636         for_each_new_connector_in_state(state, connector, new_con_state, i) {
 637                 crtc_from_state = new_con_state->crtc;
 638
 639                 if (crtc_from_state == crtc)
 640                         return to_amdgpu_dm_connector(connector);
 641         }
 642
 643         return NULL;
 644 }
 645
 646 static int dm_resume(void *handle)
 647 {
 648         struct amdgpu_device *adev = handle;
 649         struct drm_device *ddev = adev->ddev;
 650         struct amdgpu_display_manager *dm = &adev->dm;
 651         struct amdgpu_dm_connector *aconnector;
 652         struct drm_connector *connector;
 653         struct drm_crtc *crtc;
 654         struct drm_crtc_state *new_crtc_state;
 655         struct dm_crtc_state *dm_new_crtc_state;
 656         struct drm_plane *plane;
 657         struct drm_plane_state *new_plane_state;
 658         struct dm_plane_state *dm_new_plane_state;
 659         int ret;
 660         int i;
 661
 662         /* power on hardware */
 663         dc_set_power_state(dm->dc, DC_ACPI_CM_POWER_STATE_D0);
 664
 665         /* program HPD filter */
 666         dc_resume(dm->dc);
 667
 668         /* On resume we need to  rewrite the MSTM control bits to enamble MST*/
 669         s3_handle_mst(ddev, false);
 670
 671         /*
 672          * early enable HPD Rx IRQ, should be done before set mode as short
 673          * pulse interrupts are used for MST
 674          */
 675         amdgpu_dm_irq_resume_early(adev);
 676
 677         /* Do detection*/
 678         list_for_each_entry(connector, &ddev->mode_config.connector_list, head) {
 679                 aconnector = to_amdgpu_dm_connector(connector);
 680
 681                 /*
 682                  * this is the case when traversing through already created
 683                  * MST connectors, should be skipped
 684                  */
 685                 if (aconnector->mst_port)
 686                         continue;
 687
 688                 mutex_lock(&aconnector->hpd_lock);
 689                 dc_link_detect(aconnector->dc_link, DETECT_REASON_HPD);
 690
 691                 if (aconnector->fake_enable && aconnector->dc_link->local_sink)
 692                         aconnector->fake_enable = false;
 693
 694                 aconnector->dc_sink = NULL;
 695                 amdgpu_dm_update_connector_after_detect(aconnector);
 696                 mutex_unlock(&aconnector->hpd_lock);
 697         }
 698
 699         /* Force mode set in atomic comit */
 700         for_each_new_crtc_in_state(dm->cached_state, crtc, new_crtc_state, i)
 701                 new_crtc_state->active_changed = true;
 702
 703         /*
 704          * atomic_check is expected to create the dc states. We need to release
 705          * them here, since they were duplicated as part of the suspend
 706          * procedure.
 707          */
 708         for_each_new_crtc_in_state(dm->cached_state, crtc, new_crtc_state, i) {
 709                 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
 710                 if (dm_new_crtc_state->stream) {
 711                         WARN_ON(kref_read(&dm_new_crtc_state->stream->refcount) > 1);
 712                         dc_stream_release(dm_new_crtc_state->stream);
 713                         dm_new_crtc_state->stream = NULL;
 714                 }
 715         }
 716
 717         for_each_new_plane_in_state(dm->cached_state, plane, new_plane_state, i) {
 718                 dm_new_plane_state = to_dm_plane_state(new_plane_state);
 719                 if (dm_new_plane_state->dc_state) {
 720                         WARN_ON(kref_read(&dm_new_plane_state->dc_state->refcount) > 1);
 721                         dc_plane_state_release(dm_new_plane_state->dc_state);
 722                         dm_new_plane_state->dc_state = NULL;
 723                 }
 724         }
 725
 726         ret = drm_atomic_helper_resume(ddev, dm->cached_state);
 727
 728         dm->cached_state = NULL;
 729
 730         amdgpu_dm_irq_resume_late(adev);
 731
 732         return ret;
 733 }
 734
 735 static const struct amd_ip_funcs amdgpu_dm_funcs = {
 736         .name = "dm",
 737         .early_init = dm_early_init,
 738         .late_init = dm_late_init,
 739         .sw_init = dm_sw_init,
 740         .sw_fini = dm_sw_fini,
 741         .hw_init = dm_hw_init,
 742         .hw_fini = dm_hw_fini,
 743         .suspend = dm_suspend,
 744         .resume = dm_resume,
 745         .is_idle = dm_is_idle,
 746         .wait_for_idle = dm_wait_for_idle,
 747         .check_soft_reset = dm_check_soft_reset,
 748         .soft_reset = dm_soft_reset,
 749         .set_clockgating_state = dm_set_clockgating_state,
 750         .set_powergating_state = dm_set_powergating_state,
 751 };
 752
 753 const struct amdgpu_ip_block_version dm_ip_block =
 754 {
 755         .type = AMD_IP_BLOCK_TYPE_DCE,
 756         .major = 1,
 757         .minor = 0,
 758         .rev = 0,
 759         .funcs = &amdgpu_dm_funcs,
 760 };
 761
 762
 763 static struct drm_atomic_state *
 764 dm_atomic_state_alloc(struct drm_device *dev)
 765 {
 766         struct dm_atomic_state *state = kzalloc(sizeof(*state), GFP_KERNEL);
 767
 768         if (!state)
 769                 return NULL;
 770
 771         if (drm_atomic_state_init(dev, &state->base) < 0)
 772                 goto fail;
 773
 774         return &state->base;
 775
 776 fail:
 777         kfree(state);
 778         return NULL;
 779 }
 780
 781 static void
 782 dm_atomic_state_clear(struct drm_atomic_state *state)
 783 {
 784         struct dm_atomic_state *dm_state = to_dm_atomic_state(state);
 785
 786         if (dm_state->context) {
 787                 dc_release_state(dm_state->context);
 788                 dm_state->context = NULL;
 789         }
 790
 791         drm_atomic_state_default_clear(state);
 792 }
 793
 794 static void
 795 dm_atomic_state_alloc_free(struct drm_atomic_state *state)
 796 {
 797         struct dm_atomic_state *dm_state = to_dm_atomic_state(state);
 798         drm_atomic_state_default_release(state);
 799         kfree(dm_state);
 800 }
 801
 802 static const struct drm_mode_config_funcs amdgpu_dm_mode_funcs = {
 803         .fb_create = amdgpu_display_user_framebuffer_create,
 804         .output_poll_changed = drm_fb_helper_output_poll_changed,
 805         .atomic_check = amdgpu_dm_atomic_check,
 806         .atomic_commit = amdgpu_dm_atomic_commit,
 807         .atomic_state_alloc = dm_atomic_state_alloc,
 808         .atomic_state_clear = dm_atomic_state_clear,
 809         .atomic_state_free = dm_atomic_state_alloc_free
 810 };
 811
 812 static struct drm_mode_config_helper_funcs amdgpu_dm_mode_config_helperfuncs = {
 813         .atomic_commit_tail = amdgpu_dm_atomic_commit_tail
 814 };
 815
 816 static void
 817 amdgpu_dm_update_connector_after_detect(struct amdgpu_dm_connector *aconnector)
 818 {
 819         struct drm_connector *connector = &aconnector->base;
 820         struct drm_device *dev = connector->dev;
 821         struct dc_sink *sink;
 822
 823         /* MST handled by drm_mst framework */
 824         if (aconnector->mst_mgr.mst_state == true)
 825                 return;
 826
 827
 828         sink = aconnector->dc_link->local_sink;
 829
 830         /* Edid mgmt connector gets first update only in mode_valid hook and then
 831          * the connector sink is set to either fake or physical sink depends on link status.
 832          * don't do it here if u are during boot
 833          */
 834         if (aconnector->base.force != DRM_FORCE_UNSPECIFIED
 835                         && aconnector->dc_em_sink) {
 836
 837                 /* For S3 resume with headless use eml_sink to fake stream
 838                  * because on resume connecotr->sink is set ti NULL
 839                  */
 840                 mutex_lock(&dev->mode_config.mutex);
 841
 842                 if (sink) {
 843                         if (aconnector->dc_sink) {
 844                                 amdgpu_dm_remove_sink_from_freesync_module(
 845                                                                 connector);
 846                                 /* retain and release bellow are used for
 847                                  * bump up refcount for sink because the link don't point
 848                                  * to it anymore after disconnect so on next crtc to connector
 849                                  * reshuffle by UMD we will get into unwanted dc_sink release
 850                                  */
 851                                 if (aconnector->dc_sink != aconnector->dc_em_sink)
 852                                         dc_sink_release(aconnector->dc_sink);
 853                         }
 854                         aconnector->dc_sink = sink;
 855                         amdgpu_dm_add_sink_to_freesync_module(
 856                                                 connector, aconnector->edid);
 857                 } else {
 858                         amdgpu_dm_remove_sink_from_freesync_module(connector);
 859                         if (!aconnector->dc_sink)
 860                                 aconnector->dc_sink = aconnector->dc_em_sink;
 861                         else if (aconnector->dc_sink != aconnector->dc_em_sink)
 862                                 dc_sink_retain(aconnector->dc_sink);
 863                 }
 864
 865                 mutex_unlock(&dev->mode_config.mutex);
 866                 return;
 867         }
 868
 869         /*
 870          * TODO: temporary guard to look for proper fix
 871          * if this sink is MST sink, we should not do anything
 872          */
 873         if (sink && sink->sink_signal == SIGNAL_TYPE_DISPLAY_PORT_MST)
 874                 return;
 875
 876         if (aconnector->dc_sink == sink) {
 877                 /* We got a DP short pulse (Link Loss, DP CTS, etc...).
 878                  * Do nothing!! */
 879                 DRM_DEBUG_DRIVER("DCHPD: connector_id=%d: dc_sink didn't change.\n",
 880                                 aconnector->connector_id);
 881                 return;
 882         }
 883
 884         DRM_DEBUG_DRIVER("DCHPD: connector_id=%d: Old sink=%p New sink=%p\n",
 885                 aconnector->connector_id, aconnector->dc_sink, sink);
 886
 887         mutex_lock(&dev->mode_config.mutex);
 888
 889         /* 1. Update status of the drm connector
 890          * 2. Send an event and let userspace tell us what to do */
 891         if (sink) {
 892                 /* TODO: check if we still need the S3 mode update workaround.
 893                  * If yes, put it here. */
 894                 if (aconnector->dc_sink)
 895                         amdgpu_dm_remove_sink_from_freesync_module(
 896                                                         connector);
 897
 898                 aconnector->dc_sink = sink;
 899                 if (sink->dc_edid.length == 0) {
 900                         aconnector->edid = NULL;
 901                 } else {
 902                         aconnector->edid =
 903                                 (struct edid *) sink->dc_edid.raw_edid;
 904
 905
 906                         drm_connector_update_edid_property(connector,
 907                                         aconnector->edid);
 908                 }
 909                 amdgpu_dm_add_sink_to_freesync_module(connector, aconnector->edid);
 910
 911         } else {
 912                 amdgpu_dm_remove_sink_from_freesync_module(connector);
 913                 drm_connector_update_edid_property(connector, NULL);
 914                 aconnector->num_modes = 0;
 915                 aconnector->dc_sink = NULL;
 916                 aconnector->edid = NULL;
 917         }
 918
 919         mutex_unlock(&dev->mode_config.mutex);
 920 }
 921
 922 static void handle_hpd_irq(void *param)
 923 {
 924         struct amdgpu_dm_connector *aconnector = (struct amdgpu_dm_connector *)param;
 925         struct drm_connector *connector = &aconnector->base;
 926         struct drm_device *dev = connector->dev;
 927
 928         /* In case of failure or MST no need to update connector status or notify the OS
 929          * since (for MST case) MST does this in it's own context.
 930          */
 931         mutex_lock(&aconnector->hpd_lock);
 932
 933         if (aconnector->fake_enable)
 934                 aconnector->fake_enable = false;
 935
 936         if (dc_link_detect(aconnector->dc_link, DETECT_REASON_HPD)) {
 937                 amdgpu_dm_update_connector_after_detect(aconnector);
 938
 939
 940                 drm_modeset_lock_all(dev);
 941                 dm_restore_drm_connector_state(dev, connector);
 942                 drm_modeset_unlock_all(dev);
 943
 944                 if (aconnector->base.force == DRM_FORCE_UNSPECIFIED)
 945                         drm_kms_helper_hotplug_event(dev);
 946         }
 947         mutex_unlock(&aconnector->hpd_lock);
 948
 949 }
 950
 951 static void dm_handle_hpd_rx_irq(struct amdgpu_dm_connector *aconnector)
 952 {
 953         uint8_t esi[DP_PSR_ERROR_STATUS - DP_SINK_COUNT_ESI] = { 0 };
 954         uint8_t dret;
 955         bool new_irq_handled = false;
 956         int dpcd_addr;
 957         int dpcd_bytes_to_read;
 958
 959         const int max_process_count = 30;
 960         int process_count = 0;
 961
 962         const struct dc_link_status *link_status = dc_link_get_status(aconnector->dc_link);
 963
 964         if (link_status->dpcd_caps->dpcd_rev.raw < 0x12) {
 965                 dpcd_bytes_to_read = DP_LANE0_1_STATUS - DP_SINK_COUNT;
 966                 /* DPCD 0x200 - 0x201 for downstream IRQ */
 967                 dpcd_addr = DP_SINK_COUNT;
 968         } else {
 969                 dpcd_bytes_to_read = DP_PSR_ERROR_STATUS - DP_SINK_COUNT_ESI;
 970                 /* DPCD 0x2002 - 0x2005 for downstream IRQ */
 971                 dpcd_addr = DP_SINK_COUNT_ESI;
 972         }
 973
 974         dret = drm_dp_dpcd_read(
 975                 &aconnector->dm_dp_aux.aux,
 976                 dpcd_addr,
 977                 esi,
 978                 dpcd_bytes_to_read);
 979
 980         while (dret == dpcd_bytes_to_read &&
 981                 process_count < max_process_count) {
 982                 uint8_t retry;
 983                 dret = 0;
 984
 985                 process_count++;
 986
 987                 DRM_DEBUG_DRIVER("ESI %02x %02x %02x\n", esi[0], esi[1], esi[2]);
 988                 /* handle HPD short pulse irq */
 989                 if (aconnector->mst_mgr.mst_state)
 990                         drm_dp_mst_hpd_irq(
 991                                 &aconnector->mst_mgr,
 992                                 esi,
 993                                 &new_irq_handled);
 994
 995                 if (new_irq_handled) {
 996                         /* ACK at DPCD to notify down stream */
 997                         const int ack_dpcd_bytes_to_write =
 998                                 dpcd_bytes_to_read - 1;
 999
1000                         for (retry = 0; retry < 3; retry++) {
1001                                 uint8_t wret;
1002
1003                                 wret = drm_dp_dpcd_write(
1004                                         &aconnector->dm_dp_aux.aux,
1005                                         dpcd_addr + 1,
1006                                         &esi[1],
1007                                         ack_dpcd_bytes_to_write);
1008                                 if (wret == ack_dpcd_bytes_to_write)
1009                                         break;
1010                         }
1011
1012                         /* check if there is new irq to be handle */
1013                         dret = drm_dp_dpcd_read(
1014                                 &aconnector->dm_dp_aux.aux,
1015                                 dpcd_addr,
1016                                 esi,
1017                                 dpcd_bytes_to_read);
1018
1019                         new_irq_handled = false;
1020                 } else {
1021                         break;
1022                 }
1023         }
1024
1025         if (process_count == max_process_count)
1026                 DRM_DEBUG_DRIVER("Loop exceeded max iterations\n");
1027 }
1028
1029 static void handle_hpd_rx_irq(void *param)
1030 {
1031         struct amdgpu_dm_connector *aconnector = (struct amdgpu_dm_connector *)param;
1032         struct drm_connector *connector = &aconnector->base;
1033         struct drm_device *dev = connector->dev;
1034         struct dc_link *dc_link = aconnector->dc_link;
1035         bool is_mst_root_connector = aconnector->mst_mgr.mst_state;
1036
1037         /* TODO:Temporary add mutex to protect hpd interrupt not have a gpio
1038          * conflict, after implement i2c helper, this mutex should be
1039          * retired.
1040          */
1041         if (dc_link->type != dc_connection_mst_branch)
1042                 mutex_lock(&aconnector->hpd_lock);
1043
1044         if (dc_link_handle_hpd_rx_irq(dc_link, NULL, NULL) &&
1045                         !is_mst_root_connector) {
1046                 /* Downstream Port status changed. */
1047                 if (dc_link_detect(dc_link, DETECT_REASON_HPDRX)) {
1048
1049                         if (aconnector->fake_enable)
1050                                 aconnector->fake_enable = false;
1051
1052                         amdgpu_dm_update_connector_after_detect(aconnector);
1053
1054
1055                         drm_modeset_lock_all(dev);
1056                         dm_restore_drm_connector_state(dev, connector);
1057                         drm_modeset_unlock_all(dev);
1058
1059                         drm_kms_helper_hotplug_event(dev);
1060                 }
1061         }
1062         if ((dc_link->cur_link_settings.lane_count != LANE_COUNT_UNKNOWN) ||
1063             (dc_link->type == dc_connection_mst_branch))
1064                 dm_handle_hpd_rx_irq(aconnector);
1065
1066         if (dc_link->type != dc_connection_mst_branch)
1067                 mutex_unlock(&aconnector->hpd_lock);
1068 }
1069
1070 static void register_hpd_handlers(struct amdgpu_device *adev)
1071 {
1072         struct drm_device *dev = adev->ddev;
1073         struct drm_connector *connector;
1074         struct amdgpu_dm_connector *aconnector;
1075         const struct dc_link *dc_link;
1076         struct dc_interrupt_params int_params = {0};
1077
1078         int_params.requested_polarity = INTERRUPT_POLARITY_DEFAULT;
1079         int_params.current_polarity = INTERRUPT_POLARITY_DEFAULT;
1080
1081         list_for_each_entry(connector,
1082                         &dev->mode_config.connector_list, head) {
1083
1084                 aconnector = to_amdgpu_dm_connector(connector);
1085                 dc_link = aconnector->dc_link;
1086
1087                 if (DC_IRQ_SOURCE_INVALID != dc_link->irq_source_hpd) {
1088                         int_params.int_context = INTERRUPT_LOW_IRQ_CONTEXT;
1089                         int_params.irq_source = dc_link->irq_source_hpd;
1090
1091                         amdgpu_dm_irq_register_interrupt(adev, &int_params,
1092                                         handle_hpd_irq,
1093                                         (void *) aconnector);
1094                 }
1095
1096                 if (DC_IRQ_SOURCE_INVALID != dc_link->irq_source_hpd_rx) {
1097
1098                         /* Also register for DP short pulse (hpd_rx). */
1099                         int_params.int_context = INTERRUPT_LOW_IRQ_CONTEXT;
1100                         int_params.irq_source = dc_link->irq_source_hpd_rx;
1101
1102                         amdgpu_dm_irq_register_interrupt(adev, &int_params,
1103                                         handle_hpd_rx_irq,
1104                                         (void *) aconnector);
1105                 }
1106         }
1107 }
1108
1109 /* Register IRQ sources and initialize IRQ callbacks */
1110 static int dce110_register_irq_handlers(struct amdgpu_device *adev)
1111 {
1112         struct dc *dc = adev->dm.dc;
1113         struct common_irq_params *c_irq_params;
1114         struct dc_interrupt_params int_params = {0};
1115         int r;
1116         int i;
1117         unsigned client_id = AMDGPU_IH_CLIENTID_LEGACY;
1118
1119         if (adev->asic_type == CHIP_VEGA10 ||
1120             adev->asic_type == CHIP_VEGA12 ||
1121             adev->asic_type == CHIP_VEGA20 ||
1122             adev->asic_type == CHIP_RAVEN)
1123                 client_id = SOC15_IH_CLIENTID_DCE;
1124
1125         int_params.requested_polarity = INTERRUPT_POLARITY_DEFAULT;
1126         int_params.current_polarity = INTERRUPT_POLARITY_DEFAULT;
1127
1128         /* Actions of amdgpu_irq_add_id():
1129          * 1. Register a set() function with base driver.
1130          *    Base driver will call set() function to enable/disable an
1131          *    interrupt in DC hardware.
1132          * 2. Register amdgpu_dm_irq_handler().
1133          *    Base driver will call amdgpu_dm_irq_handler() for ALL interrupts
1134          *    coming from DC hardware.
1135          *    amdgpu_dm_irq_handler() will re-direct the interrupt to DC
1136          *    for acknowledging and handling. */
1137
1138         /* Use VBLANK interrupt */
1139         for (i = VISLANDS30_IV_SRCID_D1_VERTICAL_INTERRUPT0; i <= VISLANDS30_IV_SRCID_D6_VERTICAL_INTERRUPT0; i++) {
1140                 r = amdgpu_irq_add_id(adev, client_id, i, &adev->crtc_irq);
1141                 if (r) {
1142                         DRM_ERROR("Failed to add crtc irq id!\n");
1143                         return r;
1144                 }
1145
1146                 int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT;
1147                 int_params.irq_source =
1148                         dc_interrupt_to_irq_source(dc, i, 0);
1149
1150                 c_irq_params = &adev->dm.vblank_params[int_params.irq_source - DC_IRQ_SOURCE_VBLANK1];
1151
1152                 c_irq_params->adev = adev;
1153                 c_irq_params->irq_src = int_params.irq_source;
1154
1155                 amdgpu_dm_irq_register_interrupt(adev, &int_params,
1156                                 dm_crtc_high_irq, c_irq_params);
1157         }
1158
1159         /* Use GRPH_PFLIP interrupt */
1160         for (i = VISLANDS30_IV_SRCID_D1_GRPH_PFLIP;
1161                         i <= VISLANDS30_IV_SRCID_D6_GRPH_PFLIP; i += 2) {
1162                 r = amdgpu_irq_add_id(adev, client_id, i, &adev->pageflip_irq);
1163                 if (r) {
1164                         DRM_ERROR("Failed to add page flip irq id!\n");
1165                         return r;
1166                 }
1167
1168                 int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT;
1169                 int_params.irq_source =
1170                         dc_interrupt_to_irq_source(dc, i, 0);
1171
1172                 c_irq_params = &adev->dm.pflip_params[int_params.irq_source - DC_IRQ_SOURCE_PFLIP_FIRST];
1173
1174                 c_irq_params->adev = adev;
1175                 c_irq_params->irq_src = int_params.irq_source;
1176
1177                 amdgpu_dm_irq_register_interrupt(adev, &int_params,
1178                                 dm_pflip_high_irq, c_irq_params);
1179
1180         }
1181
1182         /* HPD */
1183         r = amdgpu_irq_add_id(adev, client_id,
1184                         VISLANDS30_IV_SRCID_HOTPLUG_DETECT_A, &adev->hpd_irq);
1185         if (r) {
1186                 DRM_ERROR("Failed to add hpd irq id!\n");
1187                 return r;
1188         }
1189
1190         register_hpd_handlers(adev);
1191
1192         return 0;
1193 }
1194
1195 #ifdef CONFIG_X86
1196 /* Register IRQ sources and initialize IRQ callbacks */
1197 static int dcn10_register_irq_handlers(struct amdgpu_device *adev)
1198 {
1199         struct dc *dc = adev->dm.dc;
1200         struct common_irq_params *c_irq_params;
1201         struct dc_interrupt_params int_params = {0};
1202         int r;
1203         int i;
1204
1205         int_params.requested_polarity = INTERRUPT_POLARITY_DEFAULT;
1206         int_params.current_polarity = INTERRUPT_POLARITY_DEFAULT;
1207
1208         /* Actions of amdgpu_irq_add_id():
1209          * 1. Register a set() function with base driver.
1210          *    Base driver will call set() function to enable/disable an
1211          *    interrupt in DC hardware.
1212          * 2. Register amdgpu_dm_irq_handler().
1213          *    Base driver will call amdgpu_dm_irq_handler() for ALL interrupts
1214          *    coming from DC hardware.
1215          *    amdgpu_dm_irq_handler() will re-direct the interrupt to DC
1216          *    for acknowledging and handling.
1217          * */
1218
1219         /* Use VSTARTUP interrupt */
1220         for (i = DCN_1_0__SRCID__DC_D1_OTG_VSTARTUP;
1221                         i <= DCN_1_0__SRCID__DC_D1_OTG_VSTARTUP + adev->mode_info.num_crtc - 1;
1222                         i++) {
1223                 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_DCE, i, &adev->crtc_irq);
1224
1225                 if (r) {
1226                         DRM_ERROR("Failed to add crtc irq id!\n");
1227                         return r;
1228                 }
1229
1230                 int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT;
1231                 int_params.irq_source =
1232                         dc_interrupt_to_irq_source(dc, i, 0);
1233
1234                 c_irq_params = &adev->dm.vblank_params[int_params.irq_source - DC_IRQ_SOURCE_VBLANK1];
1235
1236                 c_irq_params->adev = adev;
1237                 c_irq_params->irq_src = int_params.irq_source;
1238
1239                 amdgpu_dm_irq_register_interrupt(adev, &int_params,
1240                                 dm_crtc_high_irq, c_irq_params);
1241         }
1242
1243         /* Use GRPH_PFLIP interrupt */
1244         for (i = DCN_1_0__SRCID__HUBP0_FLIP_INTERRUPT;
1245                         i <= DCN_1_0__SRCID__HUBP0_FLIP_INTERRUPT + adev->mode_info.num_crtc - 1;
1246                         i++) {
1247                 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_DCE, i, &adev->pageflip_irq);
1248                 if (r) {
1249                         DRM_ERROR("Failed to add page flip irq id!\n");
1250                         return r;
1251                 }
1252
1253                 int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT;
1254                 int_params.irq_source =
1255                         dc_interrupt_to_irq_source(dc, i, 0);
1256
1257                 c_irq_params = &adev->dm.pflip_params[int_params.irq_source - DC_IRQ_SOURCE_PFLIP_FIRST];
1258
1259                 c_irq_params->adev = adev;
1260                 c_irq_params->irq_src = int_params.irq_source;
1261
1262                 amdgpu_dm_irq_register_interrupt(adev, &int_params,
1263                                 dm_pflip_high_irq, c_irq_params);
1264
1265         }
1266
1267         /* HPD */
1268         r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_DCE, DCN_1_0__SRCID__DC_HPD1_INT,
1269                         &adev->hpd_irq);
1270         if (r) {
1271                 DRM_ERROR("Failed to add hpd irq id!\n");
1272                 return r;
1273         }
1274
1275         register_hpd_handlers(adev);
1276
1277         return 0;
1278 }
1279 #endif
1280
1281 static int amdgpu_dm_mode_config_init(struct amdgpu_device *adev)
1282 {
1283         int r;
1284
1285         adev->mode_info.mode_config_initialized = true;
1286
1287         adev->ddev->mode_config.funcs = (void *)&amdgpu_dm_mode_funcs;
1288         adev->ddev->mode_config.helper_private = &amdgpu_dm_mode_config_helperfuncs;
1289
1290         adev->ddev->mode_config.max_width = 16384;
1291         adev->ddev->mode_config.max_height = 16384;
1292
1293         adev->ddev->mode_config.preferred_depth = 24;
1294         adev->ddev->mode_config.prefer_shadow = 1;
1295         /* indicate support of immediate flip */
1296         adev->ddev->mode_config.async_page_flip = true;
1297
1298         adev->ddev->mode_config.fb_base = adev->gmc.aper_base;
1299
1300         r = amdgpu_display_modeset_create_props(adev);
1301         if (r)
1302                 return r;
1303
1304         return 0;
1305 }
1306
1307 #if defined(CONFIG_BACKLIGHT_CLASS_DEVICE) ||\
1308         defined(CONFIG_BACKLIGHT_CLASS_DEVICE_MODULE)
1309
1310 static int amdgpu_dm_backlight_update_status(struct backlight_device *bd)
1311 {
1312         struct amdgpu_display_manager *dm = bl_get_data(bd);
1313
1314         if (dc_link_set_backlight_level(dm->backlight_link,
1315                         bd->props.brightness, 0, 0))
1316                 return 0;
1317         else
1318                 return 1;
1319 }
1320
1321 static int amdgpu_dm_backlight_get_brightness(struct backlight_device *bd)
1322 {
1323         struct amdgpu_display_manager *dm = bl_get_data(bd);
1324         int ret = dc_link_get_backlight_level(dm->backlight_link);
1325
1326         if (ret == DC_ERROR_UNEXPECTED)
1327                 return bd->props.brightness;
1328         return ret;
1329 }
1330
1331 static const struct backlight_ops amdgpu_dm_backlight_ops = {
1332         .get_brightness = amdgpu_dm_backlight_get_brightness,
1333         .update_status  = amdgpu_dm_backlight_update_status,
1334 };
1335
1336 static void
1337 amdgpu_dm_register_backlight_device(struct amdgpu_display_manager *dm)
1338 {
1339         char bl_name[16];
1340         struct backlight_properties props = { 0 };
1341
1342         props.max_brightness = AMDGPU_MAX_BL_LEVEL;
1343         props.brightness = AMDGPU_MAX_BL_LEVEL;
1344         props.type = BACKLIGHT_RAW;
1345
1346         snprintf(bl_name, sizeof(bl_name), "amdgpu_bl%d",
1347                         dm->adev->ddev->primary->index);
1348
1349         dm->backlight_dev = backlight_device_register(bl_name,
1350                         dm->adev->ddev->dev,
1351                         dm,
1352                         &amdgpu_dm_backlight_ops,
1353                         &props);
1354
1355         if (IS_ERR(dm->backlight_dev))
1356                 DRM_ERROR("DM: Backlight registration failed!\n");
1357         else
1358                 DRM_DEBUG_DRIVER("DM: Registered Backlight device: %s\n", bl_name);
1359 }
1360
1361 #endif
1362
1363 static int initialize_plane(struct amdgpu_display_manager *dm,
1364                              struct amdgpu_mode_info *mode_info,
1365                              int plane_id)
1366 {
1367         struct amdgpu_plane *plane;
1368         unsigned long possible_crtcs;
1369         int ret = 0;
1370
1371         plane = kzalloc(sizeof(struct amdgpu_plane), GFP_KERNEL);
1372         mode_info->planes[plane_id] = plane;
1373
1374         if (!plane) {
1375                 DRM_ERROR("KMS: Failed to allocate plane\n");
1376                 return -ENOMEM;
1377         }
1378         plane->base.type = mode_info->plane_type[plane_id];
1379
1380         /*
1381          * HACK: IGT tests expect that each plane can only have one
1382          * one possible CRTC. For now, set one CRTC for each
1383          * plane that is not an underlay, but still allow multiple
1384          * CRTCs for underlay planes.
1385          */
1386         possible_crtcs = 1 << plane_id;
1387         if (plane_id >= dm->dc->caps.max_streams)
1388                 possible_crtcs = 0xff;
1389
1390         ret = amdgpu_dm_plane_init(dm, mode_info->planes[plane_id], possible_crtcs);
1391
1392         if (ret) {
1393                 DRM_ERROR("KMS: Failed to initialize plane\n");
1394                 return ret;
1395         }
1396
1397         return ret;
1398 }
1399
1400
1401 static void register_backlight_device(struct amdgpu_display_manager *dm,
1402                                       struct dc_link *link)
1403 {
1404 #if defined(CONFIG_BACKLIGHT_CLASS_DEVICE) ||\
1405         defined(CONFIG_BACKLIGHT_CLASS_DEVICE_MODULE)
1406
1407         if ((link->connector_signal & (SIGNAL_TYPE_EDP | SIGNAL_TYPE_LVDS)) &&
1408             link->type != dc_connection_none) {
1409                 /* Event if registration failed, we should continue with
1410                  * DM initialization because not having a backlight control
1411                  * is better then a black screen.
1412                  */
1413                 amdgpu_dm_register_backlight_device(dm);
1414
1415                 if (dm->backlight_dev)
1416                         dm->backlight_link = link;
1417         }
1418 #endif
1419 }
1420
1421
1422 /* In this architecture, the association
1423  * connector -> encoder -> crtc
1424  * id not really requried. The crtc and connector will hold the
1425  * display_index as an abstraction to use with DAL component
1426  *
1427  * Returns 0 on success
1428  */
1429 static int amdgpu_dm_initialize_drm_device(struct amdgpu_device *adev)
1430 {
1431         struct amdgpu_display_manager *dm = &adev->dm;
1432         int32_t i;
1433         struct amdgpu_dm_connector *aconnector = NULL;
1434         struct amdgpu_encoder *aencoder = NULL;
1435         struct amdgpu_mode_info *mode_info = &adev->mode_info;
1436         uint32_t link_cnt;
1437         int32_t total_overlay_planes, total_primary_planes;
1438
1439         link_cnt = dm->dc->caps.max_links;
1440         if (amdgpu_dm_mode_config_init(dm->adev)) {
1441                 DRM_ERROR("DM: Failed to initialize mode config\n");
1442                 return -1;
1443         }
1444
1445         /* Identify the number of planes to be initialized */
1446         total_overlay_planes = dm->dc->caps.max_slave_planes;
1447         total_primary_planes = dm->dc->caps.max_planes - dm->dc->caps.max_slave_planes;
1448
1449         /* First initialize overlay planes, index starting after primary planes */
1450         for (i = (total_overlay_planes - 1); i >= 0; i--) {
1451                 if (initialize_plane(dm, mode_info, (total_primary_planes + i))) {
1452                         DRM_ERROR("KMS: Failed to initialize overlay plane\n");
1453                         goto fail;
1454                 }
1455         }
1456
1457         /* Initialize primary planes */
1458         for (i = (total_primary_planes - 1); i >= 0; i--) {
1459                 if (initialize_plane(dm, mode_info, i)) {
1460                         DRM_ERROR("KMS: Failed to initialize primary plane\n");
1461                         goto fail;
1462                 }
1463         }
1464
1465         for (i = 0; i < dm->dc->caps.max_streams; i++)
1466                 if (amdgpu_dm_crtc_init(dm, &mode_info->planes[i]->base, i)) {
1467                         DRM_ERROR("KMS: Failed to initialize crtc\n");
1468                         goto fail;
1469                 }
1470
1471         dm->display_indexes_num = dm->dc->caps.max_streams;
1472
1473         /* loops over all connectors on the board */
1474         for (i = 0; i < link_cnt; i++) {
1475                 struct dc_link *link = NULL;
1476
1477                 if (i > AMDGPU_DM_MAX_DISPLAY_INDEX) {
1478                         DRM_ERROR(
1479                                 "KMS: Cannot support more than %d display indexes\n",
1480                                         AMDGPU_DM_MAX_DISPLAY_INDEX);
1481                         continue;
1482                 }
1483
1484                 aconnector = kzalloc(sizeof(*aconnector), GFP_KERNEL);
1485                 if (!aconnector)
1486                         goto fail;
1487
1488                 aencoder = kzalloc(sizeof(*aencoder), GFP_KERNEL);
1489                 if (!aencoder)
1490                         goto fail;
1491
1492                 if (amdgpu_dm_encoder_init(dm->ddev, aencoder, i)) {
1493                         DRM_ERROR("KMS: Failed to initialize encoder\n");
1494                         goto fail;
1495                 }
1496
1497                 if (amdgpu_dm_connector_init(dm, aconnector, i, aencoder)) {
1498                         DRM_ERROR("KMS: Failed to initialize connector\n");
1499                         goto fail;
1500                 }
1501
1502                 link = dc_get_link_at_index(dm->dc, i);
1503
1504                 if (dc_link_detect(link, DETECT_REASON_BOOT)) {
1505                         amdgpu_dm_update_connector_after_detect(aconnector);
1506                         register_backlight_device(dm, link);
1507                 }
1508
1509
1510         }
1511
1512         /* Software is initialized. Now we can register interrupt handlers. */
1513         switch (adev->asic_type) {
1514         case CHIP_BONAIRE:
1515         case CHIP_HAWAII:
1516         case CHIP_KAVERI:
1517         case CHIP_KABINI:
1518         case CHIP_MULLINS:
1519         case CHIP_TONGA:
1520         case CHIP_FIJI:
1521         case CHIP_CARRIZO:
1522         case CHIP_STONEY:
1523         case CHIP_POLARIS11:
1524         case CHIP_POLARIS10:
1525         case CHIP_POLARIS12:
1526         case CHIP_VEGAM:
1527         case CHIP_VEGA10:
1528         case CHIP_VEGA12:
1529         case CHIP_VEGA20:
1530                 if (dce110_register_irq_handlers(dm->adev)) {
1531                         DRM_ERROR("DM: Failed to initialize IRQ\n");
1532                         goto fail;
1533                 }
1534                 break;
1535 #ifdef CONFIG_X86
1536         case CHIP_RAVEN:
1537                 if (dcn10_register_irq_handlers(dm->adev)) {
1538                         DRM_ERROR("DM: Failed to initialize IRQ\n");
1539                         goto fail;
1540                 }
1541                 break;
1542 #endif
1543         default:
1544                 DRM_ERROR("Unsupported ASIC type: 0x%X\n", adev->asic_type);
1545                 goto fail;
1546         }
1547
1548         if (adev->asic_type != CHIP_CARRIZO && adev->asic_type != CHIP_STONEY)
1549                 dm->dc->debug.disable_stutter = amdgpu_pp_feature_mask & PP_STUTTER_MODE ? false : true;
1550
1551         return 0;
1552 fail:
1553         kfree(aencoder);
1554         kfree(aconnector);
1555         for (i = 0; i < dm->dc->caps.max_planes; i++)
1556                 kfree(mode_info->planes[i]);
1557         return -1;
1558 }
1559
1560 static void amdgpu_dm_destroy_drm_device(struct amdgpu_display_manager *dm)
1561 {
1562         drm_mode_config_cleanup(dm->ddev);
1563         return;
1564 }
1565
1566 /******************************************************************************
1567  * amdgpu_display_funcs functions
1568  *****************************************************************************/
1569
1570 /**
1571  * dm_bandwidth_update - program display watermarks
1572  *
1573  * @adev: amdgpu_device pointer
1574  *
1575  * Calculate and program the display watermarks and line buffer allocation.
1576  */
1577 static void dm_bandwidth_update(struct amdgpu_device *adev)
1578 {
1579         /* TODO: implement later */
1580 }
1581
1582 static int amdgpu_notify_freesync(struct drm_device *dev, void *data,
1583                                 struct drm_file *filp)
1584 {
1585         struct mod_freesync_params freesync_params;
1586         uint8_t num_streams;
1587         uint8_t i;
1588
1589         struct amdgpu_device *adev = dev->dev_private;
1590         int r = 0;
1591
1592         /* Get freesync enable flag from DRM */
1593
1594         num_streams = dc_get_current_stream_count(adev->dm.dc);
1595
1596         for (i = 0; i < num_streams; i++) {
1597                 struct dc_stream_state *stream;
1598                 stream = dc_get_stream_at_index(adev->dm.dc, i);
1599
1600                 mod_freesync_update_state(adev->dm.freesync_module,
1601                                           &stream, 1, &freesync_params);
1602         }
1603
1604         return r;
1605 }
1606
1607 static const struct amdgpu_display_funcs dm_display_funcs = {
1608         .bandwidth_update = dm_bandwidth_update, /* called unconditionally */
1609         .vblank_get_counter = dm_vblank_get_counter,/* called unconditionally */
1610         .backlight_set_level = NULL, /* never called for DC */
1611         .backlight_get_level = NULL, /* never called for DC */
1612         .hpd_sense = NULL,/* called unconditionally */
1613         .hpd_set_polarity = NULL, /* called unconditionally */
1614         .hpd_get_gpio_reg = NULL, /* VBIOS parsing. DAL does it. */
1615         .page_flip_get_scanoutpos =
1616                 dm_crtc_get_scanoutpos,/* called unconditionally */
1617         .add_encoder = NULL, /* VBIOS parsing. DAL does it. */
1618         .add_connector = NULL, /* VBIOS parsing. DAL does it. */
1619         .notify_freesync = amdgpu_notify_freesync,
1620
1621 };
1622
1623 #if defined(CONFIG_DEBUG_KERNEL_DC)
1624
1625 static ssize_t s3_debug_store(struct device *device,
1626                               struct device_attribute *attr,
1627                               const char *buf,
1628                               size_t count)
1629 {
1630         int ret;
1631         int s3_state;
1632         struct pci_dev *pdev = to_pci_dev(device);
1633         struct drm_device *drm_dev = pci_get_drvdata(pdev);
1634         struct amdgpu_device *adev = drm_dev->dev_private;
1635
1636         ret = kstrtoint(buf, 0, &s3_state);
1637
1638         if (ret == 0) {
1639                 if (s3_state) {
1640                         dm_resume(adev);
1641                         drm_kms_helper_hotplug_event(adev->ddev);
1642                 } else
1643                         dm_suspend(adev);
1644         }
1645
1646         return ret == 0 ? count : 0;
1647 }
1648
1649 DEVICE_ATTR_WO(s3_debug);
1650
1651 #endif
1652
1653 static int dm_early_init(void *handle)
1654 {
1655         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1656
1657         switch (adev->asic_type) {
1658         case CHIP_BONAIRE:
1659         case CHIP_HAWAII:
1660                 adev->mode_info.num_crtc = 6;
1661                 adev->mode_info.num_hpd = 6;
1662                 adev->mode_info.num_dig = 6;
1663                 adev->mode_info.plane_type = dm_plane_type_default;
1664                 break;
1665         case CHIP_KAVERI:
1666                 adev->mode_info.num_crtc = 4;
1667                 adev->mode_info.num_hpd = 6;
1668                 adev->mode_info.num_dig = 7;
1669                 adev->mode_info.plane_type = dm_plane_type_default;
1670                 break;
1671         case CHIP_KABINI:
1672         case CHIP_MULLINS:
1673                 adev->mode_info.num_crtc = 2;
1674                 adev->mode_info.num_hpd = 6;
1675                 adev->mode_info.num_dig = 6;
1676                 adev->mode_info.plane_type = dm_plane_type_default;
1677                 break;
1678         case CHIP_FIJI:
1679         case CHIP_TONGA:
1680                 adev->mode_info.num_crtc = 6;
1681                 adev->mode_info.num_hpd = 6;
1682                 adev->mode_info.num_dig = 7;
1683                 adev->mode_info.plane_type = dm_plane_type_default;
1684                 break;
1685         case CHIP_CARRIZO:
1686                 adev->mode_info.num_crtc = 3;
1687                 adev->mode_info.num_hpd = 6;
1688                 adev->mode_info.num_dig = 9;
1689                 adev->mode_info.plane_type = dm_plane_type_carizzo;
1690                 break;
1691         case CHIP_STONEY:
1692                 adev->mode_info.num_crtc = 2;
1693                 adev->mode_info.num_hpd = 6;
1694                 adev->mode_info.num_dig = 9;
1695                 adev->mode_info.plane_type = dm_plane_type_stoney;
1696                 break;
1697         case CHIP_POLARIS11:
1698         case CHIP_POLARIS12:
1699                 adev->mode_info.num_crtc = 5;
1700                 adev->mode_info.num_hpd = 5;
1701                 adev->mode_info.num_dig = 5;
1702                 adev->mode_info.plane_type = dm_plane_type_default;
1703                 break;
1704         case CHIP_POLARIS10:
1705         case CHIP_VEGAM:
1706                 adev->mode_info.num_crtc = 6;
1707                 adev->mode_info.num_hpd = 6;
1708                 adev->mode_info.num_dig = 6;
1709                 adev->mode_info.plane_type = dm_plane_type_default;
1710                 break;
1711         case CHIP_VEGA10:
1712         case CHIP_VEGA12:
1713         case CHIP_VEGA20:
1714                 adev->mode_info.num_crtc = 6;
1715                 adev->mode_info.num_hpd = 6;
1716                 adev->mode_info.num_dig = 6;
1717                 adev->mode_info.plane_type = dm_plane_type_default;
1718                 break;
1719 #ifdef CONFIG_X86
1720         case CHIP_RAVEN:
1721                 adev->mode_info.num_crtc = 4;
1722                 adev->mode_info.num_hpd = 4;
1723                 adev->mode_info.num_dig = 4;
1724                 adev->mode_info.plane_type = dm_plane_type_default;
1725                 break;
1726 #endif
1727         default:
1728                 DRM_ERROR("Unsupported ASIC type: 0x%X\n", adev->asic_type);
1729                 return -EINVAL;
1730         }
1731
1732         amdgpu_dm_set_irq_funcs(adev);
1733
1734         if (adev->mode_info.funcs == NULL)
1735                 adev->mode_info.funcs = &dm_display_funcs;
1736
1737         /* Note: Do NOT change adev->audio_endpt_rreg and
1738          * adev->audio_endpt_wreg because they are initialised in
1739          * amdgpu_device_init() */
1740 #if defined(CONFIG_DEBUG_KERNEL_DC)
1741         device_create_file(
1742                 adev->ddev->dev,
1743                 &dev_attr_s3_debug);
1744 #endif
1745
1746         return 0;
1747 }
1748
1749 static bool modeset_required(struct drm_crtc_state *crtc_state,
1750                              struct dc_stream_state *new_stream,
1751                              struct dc_stream_state *old_stream)
1752 {
1753         if (!drm_atomic_crtc_needs_modeset(crtc_state))
1754                 return false;
1755
1756         if (!crtc_state->enable)
1757                 return false;
1758
1759         return crtc_state->active;
1760 }
1761
1762 static bool modereset_required(struct drm_crtc_state *crtc_state)
1763 {
1764         if (!drm_atomic_crtc_needs_modeset(crtc_state))
1765                 return false;
1766
1767         return !crtc_state->enable || !crtc_state->active;
1768 }
1769
1770 static void amdgpu_dm_encoder_destroy(struct drm_encoder *encoder)
1771 {
1772         drm_encoder_cleanup(encoder);
1773         kfree(encoder);
1774 }
1775
1776 static const struct drm_encoder_funcs amdgpu_dm_encoder_funcs = {
1777         .destroy = amdgpu_dm_encoder_destroy,
1778 };
1779
1780 static bool fill_rects_from_plane_state(const struct drm_plane_state *state,
1781                                         struct dc_plane_state *plane_state)
1782 {
1783         plane_state->src_rect.x = state->src_x >> 16;
1784         plane_state->src_rect.y = state->src_y >> 16;
1785         /*we ignore for now mantissa and do not to deal with floating pixels :(*/
1786         plane_state->src_rect.width = state->src_w >> 16;
1787
1788         if (plane_state->src_rect.width == 0)
1789                 return false;
1790
1791         plane_state->src_rect.height = state->src_h >> 16;
1792         if (plane_state->src_rect.height == 0)
1793                 return false;
1794
1795         plane_state->dst_rect.x = state->crtc_x;
1796         plane_state->dst_rect.y = state->crtc_y;
1797
1798         if (state->crtc_w == 0)
1799                 return false;
1800
1801         plane_state->dst_rect.width = state->crtc_w;
1802
1803         if (state->crtc_h == 0)
1804                 return false;
1805
1806         plane_state->dst_rect.height = state->crtc_h;
1807
1808         plane_state->clip_rect = plane_state->dst_rect;
1809
1810         switch (state->rotation & DRM_MODE_ROTATE_MASK) {
1811         case DRM_MODE_ROTATE_0:
1812                 plane_state->rotation = ROTATION_ANGLE_0;
1813                 break;
1814         case DRM_MODE_ROTATE_90:
1815                 plane_state->rotation = ROTATION_ANGLE_90;
1816                 break;
1817         case DRM_MODE_ROTATE_180:
1818                 plane_state->rotation = ROTATION_ANGLE_180;
1819                 break;
1820         case DRM_MODE_ROTATE_270:
1821                 plane_state->rotation = ROTATION_ANGLE_270;
1822                 break;
1823         default:
1824                 plane_state->rotation = ROTATION_ANGLE_0;
1825                 break;
1826         }
1827
1828         return true;
1829 }
1830 static int get_fb_info(const struct amdgpu_framebuffer *amdgpu_fb,
1831                        uint64_t *tiling_flags)
1832 {
1833         struct amdgpu_bo *rbo = gem_to_amdgpu_bo(amdgpu_fb->base.obj[0]);
1834         int r = amdgpu_bo_reserve(rbo, false);
1835
1836         if (unlikely(r)) {
1837                 // Don't show error msg. when return -ERESTARTSYS
1838                 if (r != -ERESTARTSYS)
1839                         DRM_ERROR("Unable to reserve buffer: %d\n", r);
1840                 return r;
1841         }
1842
1843         if (tiling_flags)
1844                 amdgpu_bo_get_tiling_flags(rbo, tiling_flags);
1845
1846         amdgpu_bo_unreserve(rbo);
1847
1848         return r;
1849 }
1850
1851 static int fill_plane_attributes_from_fb(struct amdgpu_device *adev,
1852                                          struct dc_plane_state *plane_state,
1853                                          const struct amdgpu_framebuffer *amdgpu_fb)
1854 {
1855         uint64_t tiling_flags;
1856         unsigned int awidth;
1857         const struct drm_framebuffer *fb = &amdgpu_fb->base;
1858         int ret = 0;
1859         struct drm_format_name_buf format_name;
1860
1861         ret = get_fb_info(
1862                 amdgpu_fb,
1863                 &tiling_flags);
1864
1865         if (ret)
1866                 return ret;
1867
1868         switch (fb->format->format) {
1869         case DRM_FORMAT_C8:
1870                 plane_state->format = SURFACE_PIXEL_FORMAT_GRPH_PALETA_256_COLORS;
1871                 break;
1872         case DRM_FORMAT_RGB565:
1873                 plane_state->format = SURFACE_PIXEL_FORMAT_GRPH_RGB565;
1874                 break;
1875         case DRM_FORMAT_XRGB8888:
1876         case DRM_FORMAT_ARGB8888:
1877                 plane_state->format = SURFACE_PIXEL_FORMAT_GRPH_ARGB8888;
1878                 break;
1879         case DRM_FORMAT_XRGB2101010:
1880         case DRM_FORMAT_ARGB2101010:
1881                 plane_state->format = SURFACE_PIXEL_FORMAT_GRPH_ARGB2101010;
1882                 break;
1883         case DRM_FORMAT_XBGR2101010:
1884         case DRM_FORMAT_ABGR2101010:
1885                 plane_state->format = SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010;
1886                 break;
1887         case DRM_FORMAT_NV21:
1888                 plane_state->format = SURFACE_PIXEL_FORMAT_VIDEO_420_YCbCr;
1889                 break;
1890         case DRM_FORMAT_NV12:
1891                 plane_state->format = SURFACE_PIXEL_FORMAT_VIDEO_420_YCrCb;
1892                 break;
1893         default:
1894                 DRM_ERROR("Unsupported screen format %s\n",
1895                           drm_get_format_name(fb->format->format, &format_name));
1896                 return -EINVAL;
1897         }
1898
1899         if (plane_state->format < SURFACE_PIXEL_FORMAT_VIDEO_BEGIN) {
1900                 plane_state->address.type = PLN_ADDR_TYPE_GRAPHICS;
1901                 plane_state->plane_size.grph.surface_size.x = 0;
1902                 plane_state->plane_size.grph.surface_size.y = 0;
1903                 plane_state->plane_size.grph.surface_size.width = fb->width;
1904                 plane_state->plane_size.grph.surface_size.height = fb->height;
1905                 plane_state->plane_size.grph.surface_pitch =
1906                                 fb->pitches[0] / fb->format->cpp[0];
1907                 /* TODO: unhardcode */
1908                 plane_state->color_space = COLOR_SPACE_SRGB;
1909
1910         } else {
1911                 awidth = ALIGN(fb->width, 64);
1912                 plane_state->address.type = PLN_ADDR_TYPE_VIDEO_PROGRESSIVE;
1913                 plane_state->plane_size.video.luma_size.x = 0;
1914                 plane_state->plane_size.video.luma_size.y = 0;
1915                 plane_state->plane_size.video.luma_size.width = awidth;
1916                 plane_state->plane_size.video.luma_size.height = fb->height;
1917                 /* TODO: unhardcode */
1918                 plane_state->plane_size.video.luma_pitch = awidth;
1919
1920                 plane_state->plane_size.video.chroma_size.x = 0;
1921                 plane_state->plane_size.video.chroma_size.y = 0;
1922                 plane_state->plane_size.video.chroma_size.width = awidth;
1923                 plane_state->plane_size.video.chroma_size.height = fb->height;
1924                 plane_state->plane_size.video.chroma_pitch = awidth / 2;
1925
1926                 /* TODO: unhardcode */
1927                 plane_state->color_space = COLOR_SPACE_YCBCR709;
1928         }
1929
1930         memset(&plane_state->tiling_info, 0, sizeof(plane_state->tiling_info));
1931
1932         /* Fill GFX8 params */
1933         if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE) == DC_ARRAY_2D_TILED_THIN1) {
1934                 unsigned int bankw, bankh, mtaspect, tile_split, num_banks;
1935
1936                 bankw = AMDGPU_TILING_GET(tiling_flags, BANK_WIDTH);
1937                 bankh = AMDGPU_TILING_GET(tiling_flags, BANK_HEIGHT);
1938                 mtaspect = AMDGPU_TILING_GET(tiling_flags, MACRO_TILE_ASPECT);
1939                 tile_split = AMDGPU_TILING_GET(tiling_flags, TILE_SPLIT);
1940                 num_banks = AMDGPU_TILING_GET(tiling_flags, NUM_BANKS);
1941
1942                 /* XXX fix me for VI */
1943                 plane_state->tiling_info.gfx8.num_banks = num_banks;
1944                 plane_state->tiling_info.gfx8.array_mode =
1945                                 DC_ARRAY_2D_TILED_THIN1;
1946                 plane_state->tiling_info.gfx8.tile_split = tile_split;
1947                 plane_state->tiling_info.gfx8.bank_width = bankw;
1948                 plane_state->tiling_info.gfx8.bank_height = bankh;
1949                 plane_state->tiling_info.gfx8.tile_aspect = mtaspect;
1950                 plane_state->tiling_info.gfx8.tile_mode =
1951                                 DC_ADDR_SURF_MICRO_TILING_DISPLAY;
1952         } else if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE)
1953                         == DC_ARRAY_1D_TILED_THIN1) {
1954                 plane_state->tiling_info.gfx8.array_mode = DC_ARRAY_1D_TILED_THIN1;
1955         }
1956
1957         plane_state->tiling_info.gfx8.pipe_config =
1958                         AMDGPU_TILING_GET(tiling_flags, PIPE_CONFIG);
1959
1960         if (adev->asic_type == CHIP_VEGA10 ||
1961             adev->asic_type == CHIP_VEGA12 ||
1962             adev->asic_type == CHIP_VEGA20 ||
1963             adev->asic_type == CHIP_RAVEN) {
1964                 /* Fill GFX9 params */
1965                 plane_state->tiling_info.gfx9.num_pipes =
1966                         adev->gfx.config.gb_addr_config_fields.num_pipes;
1967                 plane_state->tiling_info.gfx9.num_banks =
1968                         adev->gfx.config.gb_addr_config_fields.num_banks;
1969                 plane_state->tiling_info.gfx9.pipe_interleave =
1970                         adev->gfx.config.gb_addr_config_fields.pipe_interleave_size;
1971                 plane_state->tiling_info.gfx9.num_shader_engines =
1972                         adev->gfx.config.gb_addr_config_fields.num_se;
1973                 plane_state->tiling_info.gfx9.max_compressed_frags =
1974                         adev->gfx.config.gb_addr_config_fields.max_compress_frags;
1975                 plane_state->tiling_info.gfx9.num_rb_per_se =
1976                         adev->gfx.config.gb_addr_config_fields.num_rb_per_se;
1977                 plane_state->tiling_info.gfx9.swizzle =
1978                         AMDGPU_TILING_GET(tiling_flags, SWIZZLE_MODE);
1979                 plane_state->tiling_info.gfx9.shaderEnable = 1;
1980         }
1981
1982         plane_state->visible = true;
1983         plane_state->scaling_quality.h_taps_c = 0;
1984         plane_state->scaling_quality.v_taps_c = 0;
1985
1986         /* is this needed? is plane_state zeroed at allocation? */
1987         plane_state->scaling_quality.h_taps = 0;
1988         plane_state->scaling_quality.v_taps = 0;
1989         plane_state->stereo_format = PLANE_STEREO_FORMAT_NONE;
1990
1991         return ret;
1992
1993 }
1994
1995 static int fill_plane_attributes(struct amdgpu_device *adev,
1996                                  struct dc_plane_state *dc_plane_state,
1997                                  struct drm_plane_state *plane_state,
1998                                  struct drm_crtc_state *crtc_state)
1999 {
2000         const struct amdgpu_framebuffer *amdgpu_fb =
2001                 to_amdgpu_framebuffer(plane_state->fb);
2002         const struct drm_crtc *crtc = plane_state->crtc;
2003         int ret = 0;
2004
2005         if (!fill_rects_from_plane_state(plane_state, dc_plane_state))
2006                 return -EINVAL;
2007
2008         ret = fill_plane_attributes_from_fb(
2009                 crtc->dev->dev_private,
2010                 dc_plane_state,
2011                 amdgpu_fb);
2012
2013         if (ret)
2014                 return ret;
2015
2016         /*
2017          * Always set input transfer function, since plane state is refreshed
2018          * every time.
2019          */
2020         ret = amdgpu_dm_set_degamma_lut(crtc_state, dc_plane_state);
2021         if (ret) {
2022                 dc_transfer_func_release(dc_plane_state->in_transfer_func);
2023                 dc_plane_state->in_transfer_func = NULL;
2024         }
2025
2026         return ret;
2027 }
2028
2029 /*****************************************************************************/
2030
2031 static void update_stream_scaling_settings(const struct drm_display_mode *mode,
2032                                            const struct dm_connector_state *dm_state,
2033                                            struct dc_stream_state *stream)
2034 {
2035         enum amdgpu_rmx_type rmx_type;
2036
2037         struct rect src = { 0 }; /* viewport in composition space*/
2038         struct rect dst = { 0 }; /* stream addressable area */
2039
2040         /* no mode. nothing to be done */
2041         if (!mode)
2042                 return;
2043
2044         /* Full screen scaling by default */
2045         src.width = mode->hdisplay;
2046         src.height = mode->vdisplay;
2047         dst.width = stream->timing.h_addressable;
2048         dst.height = stream->timing.v_addressable;
2049
2050         if (dm_state) {
2051                 rmx_type = dm_state->scaling;
2052                 if (rmx_type == RMX_ASPECT || rmx_type == RMX_OFF) {
2053                         if (src.width * dst.height <
2054                                         src.height * dst.width) {
2055                                 /* height needs less upscaling/more downscaling */
2056                                 dst.width = src.width *
2057                                                 dst.height / src.height;
2058                         } else {
2059                                 /* width needs less upscaling/more downscaling */
2060                                 dst.height = src.height *
2061                                                 dst.width / src.width;
2062                         }
2063                 } else if (rmx_type == RMX_CENTER) {
2064                         dst = src;
2065                 }
2066
2067                 dst.x = (stream->timing.h_addressable - dst.width) / 2;
2068                 dst.y = (stream->timing.v_addressable - dst.height) / 2;
2069
2070                 if (dm_state->underscan_enable) {
2071                         dst.x += dm_state->underscan_hborder / 2;
2072                         dst.y += dm_state->underscan_vborder / 2;
2073                         dst.width -= dm_state->underscan_hborder;
2074                         dst.height -= dm_state->underscan_vborder;
2075                 }
2076         }
2077
2078         stream->src = src;
2079         stream->dst = dst;
2080
2081         DRM_DEBUG_DRIVER("Destination Rectangle x:%d  y:%d  width:%d  height:%d\n",
2082                         dst.x, dst.y, dst.width, dst.height);
2083
2084 }
2085
2086 static enum dc_color_depth
2087 convert_color_depth_from_display_info(const struct drm_connector *connector)
2088 {
2089         uint32_t bpc = connector->display_info.bpc;
2090
2091         switch (bpc) {
2092         case 0:
2093                 /* Temporary Work around, DRM don't parse color depth for
2094                  * EDID revision before 1.4
2095                  * TODO: Fix edid parsing
2096                  */
2097                 return COLOR_DEPTH_888;
2098         case 6:
2099                 return COLOR_DEPTH_666;
2100         case 8:
2101                 return COLOR_DEPTH_888;
2102         case 10:
2103                 return COLOR_DEPTH_101010;
2104         case 12:
2105                 return COLOR_DEPTH_121212;
2106         case 14:
2107                 return COLOR_DEPTH_141414;
2108         case 16:
2109                 return COLOR_DEPTH_161616;
2110         default:
2111                 return COLOR_DEPTH_UNDEFINED;
2112         }
2113 }
2114
2115 static enum dc_aspect_ratio
2116 get_aspect_ratio(const struct drm_display_mode *mode_in)
2117 {
2118         /* 1-1 mapping, since both enums follow the HDMI spec. */
2119         return (enum dc_aspect_ratio) mode_in->picture_aspect_ratio;
2120 }
2121
2122 static enum dc_color_space
2123 get_output_color_space(const struct dc_crtc_timing *dc_crtc_timing)
2124 {
2125         enum dc_color_space color_space = COLOR_SPACE_SRGB;
2126
2127         switch (dc_crtc_timing->pixel_encoding) {
2128         case PIXEL_ENCODING_YCBCR422:
2129         case PIXEL_ENCODING_YCBCR444:
2130         case PIXEL_ENCODING_YCBCR420:
2131         {
2132                 /*
2133                  * 27030khz is the separation point between HDTV and SDTV
2134                  * according to HDMI spec, we use YCbCr709 and YCbCr601
2135                  * respectively
2136                  */
2137                 if (dc_crtc_timing->pix_clk_khz > 27030) {
2138                         if (dc_crtc_timing->flags.Y_ONLY)
2139                                 color_space =
2140                                         COLOR_SPACE_YCBCR709_LIMITED;
2141                         else
2142                                 color_space = COLOR_SPACE_YCBCR709;
2143                 } else {
2144                         if (dc_crtc_timing->flags.Y_ONLY)
2145                                 color_space =
2146                                         COLOR_SPACE_YCBCR601_LIMITED;
2147                         else
2148                                 color_space = COLOR_SPACE_YCBCR601;
2149                 }
2150
2151         }
2152         break;
2153         case PIXEL_ENCODING_RGB:
2154                 color_space = COLOR_SPACE_SRGB;
2155                 break;
2156
2157         default:
2158                 WARN_ON(1);
2159                 break;
2160         }
2161
2162         return color_space;
2163 }
2164
2165 static void reduce_mode_colour_depth(struct dc_crtc_timing *timing_out)
2166 {
2167         if (timing_out->display_color_depth <= COLOR_DEPTH_888)
2168                 return;
2169
2170         timing_out->display_color_depth--;
2171 }
2172
2173 static void adjust_colour_depth_from_display_info(struct dc_crtc_timing *timing_out,
2174                                                 const struct drm_display_info *info)
2175 {
2176         int normalized_clk;
2177         if (timing_out->display_color_depth <= COLOR_DEPTH_888)
2178                 return;
2179         do {
2180                 normalized_clk = timing_out->pix_clk_khz;
2181                 /* YCbCr 4:2:0 requires additional adjustment of 1/2 */
2182                 if (timing_out->pixel_encoding == PIXEL_ENCODING_YCBCR420)
2183                         normalized_clk /= 2;
2184                 /* Adjusting pix clock following on HDMI spec based on colour depth */
2185                 switch (timing_out->display_color_depth) {
2186                 case COLOR_DEPTH_101010:
2187                         normalized_clk = (normalized_clk * 30) / 24;
2188                         break;
2189                 case COLOR_DEPTH_121212:
2190                         normalized_clk = (normalized_clk * 36) / 24;
2191                         break;
2192                 case COLOR_DEPTH_161616:
2193                         normalized_clk = (normalized_clk * 48) / 24;
2194                         break;
2195                 default:
2196                         return;
2197                 }
2198                 if (normalized_clk <= info->max_tmds_clock)
2199                         return;
2200                 reduce_mode_colour_depth(timing_out);
2201
2202         } while (timing_out->display_color_depth > COLOR_DEPTH_888);
2203
2204 }
2205 /*****************************************************************************/
2206
2207 static void
2208 fill_stream_properties_from_drm_display_mode(struct dc_stream_state *stream,
2209                                              const struct drm_display_mode *mode_in,
2210                                              const struct drm_connector *connector)
2211 {
2212         struct dc_crtc_timing *timing_out = &stream->timing;
2213         const struct drm_display_info *info = &connector->display_info;
2214
2215         memset(timing_out, 0, sizeof(struct dc_crtc_timing));
2216
2217         timing_out->h_border_left = 0;
2218         timing_out->h_border_right = 0;
2219         timing_out->v_border_top = 0;
2220         timing_out->v_border_bottom = 0;
2221         /* TODO: un-hardcode */
2222         if (drm_mode_is_420_only(info, mode_in)
2223                         && stream->sink->sink_signal == SIGNAL_TYPE_HDMI_TYPE_A)
2224                 timing_out->pixel_encoding = PIXEL_ENCODING_YCBCR420;
2225         else if ((connector->display_info.color_formats & DRM_COLOR_FORMAT_YCRCB444)
2226                         && stream->sink->sink_signal == SIGNAL_TYPE_HDMI_TYPE_A)
2227                 timing_out->pixel_encoding = PIXEL_ENCODING_YCBCR444;
2228         else
2229                 timing_out->pixel_encoding = PIXEL_ENCODING_RGB;
2230
2231         timing_out->timing_3d_format = TIMING_3D_FORMAT_NONE;
2232         timing_out->display_color_depth = convert_color_depth_from_display_info(
2233                         connector);
2234         timing_out->scan_type = SCANNING_TYPE_NODATA;
2235         timing_out->hdmi_vic = 0;
2236         timing_out->vic = drm_match_cea_mode(mode_in);
2237
2238         timing_out->h_addressable = mode_in->crtc_hdisplay;
2239         timing_out->h_total = mode_in->crtc_htotal;
2240         timing_out->h_sync_width =
2241                 mode_in->crtc_hsync_end - mode_in->crtc_hsync_start;
2242         timing_out->h_front_porch =
2243                 mode_in->crtc_hsync_start - mode_in->crtc_hdisplay;
2244         timing_out->v_total = mode_in->crtc_vtotal;
2245         timing_out->v_addressable = mode_in->crtc_vdisplay;
2246         timing_out->v_front_porch =
2247                 mode_in->crtc_vsync_start - mode_in->crtc_vdisplay;
2248         timing_out->v_sync_width =
2249                 mode_in->crtc_vsync_end - mode_in->crtc_vsync_start;
2250         timing_out->pix_clk_khz = mode_in->crtc_clock;
2251         timing_out->aspect_ratio = get_aspect_ratio(mode_in);
2252         if (mode_in->flags & DRM_MODE_FLAG_PHSYNC)
2253                 timing_out->flags.HSYNC_POSITIVE_POLARITY = 1;
2254         if (mode_in->flags & DRM_MODE_FLAG_PVSYNC)
2255                 timing_out->flags.VSYNC_POSITIVE_POLARITY = 1;
2256
2257         stream->output_color_space = get_output_color_space(timing_out);
2258
2259         stream->out_transfer_func->type = TF_TYPE_PREDEFINED;
2260         stream->out_transfer_func->tf = TRANSFER_FUNCTION_SRGB;
2261         if (stream->sink->sink_signal == SIGNAL_TYPE_HDMI_TYPE_A)
2262                 adjust_colour_depth_from_display_info(timing_out, info);
2263 }
2264
2265 static void fill_audio_info(struct audio_info *audio_info,
2266                             const struct drm_connector *drm_connector,
2267                             const struct dc_sink *dc_sink)
2268 {
2269         int i = 0;
2270         int cea_revision = 0;
2271         const struct dc_edid_caps *edid_caps = &dc_sink->edid_caps;
2272
2273         audio_info->manufacture_id = edid_caps->manufacturer_id;
2274         audio_info->product_id = edid_caps->product_id;
2275
2276         cea_revision = drm_connector->display_info.cea_rev;
2277
2278         strncpy(audio_info->display_name,
2279                 edid_caps->display_name,
2280                 AUDIO_INFO_DISPLAY_NAME_SIZE_IN_CHARS - 1);
2281
2282         if (cea_revision >= 3) {
2283                 audio_info->mode_count = edid_caps->audio_mode_count;
2284
2285                 for (i = 0; i < audio_info->mode_count; ++i) {
2286                         audio_info->modes[i].format_code =
2287                                         (enum audio_format_code)
2288                                         (edid_caps->audio_modes[i].format_code);
2289                         audio_info->modes[i].channel_count =
2290                                         edid_caps->audio_modes[i].channel_count;
2291                         audio_info->modes[i].sample_rates.all =
2292                                         edid_caps->audio_modes[i].sample_rate;
2293                         audio_info->modes[i].sample_size =
2294                                         edid_caps->audio_modes[i].sample_size;
2295                 }
2296         }
2297
2298         audio_info->flags.all = edid_caps->speaker_flags;
2299
2300         /* TODO: We only check for the progressive mode, check for interlace mode too */
2301         if (drm_connector->latency_present[0]) {
2302                 audio_info->video_latency = drm_connector->video_latency[0];
2303                 audio_info->audio_latency = drm_connector->audio_latency[0];
2304         }
2305
2306         /* TODO: For DP, video and audio latency should be calculated from DPCD caps */
2307
2308 }
2309
2310 static void
2311 copy_crtc_timing_for_drm_display_mode(const struct drm_display_mode *src_mode,
2312                                       struct drm_display_mode *dst_mode)
2313 {
2314         dst_mode->crtc_hdisplay = src_mode->crtc_hdisplay;
2315         dst_mode->crtc_vdisplay = src_mode->crtc_vdisplay;
2316         dst_mode->crtc_clock = src_mode->crtc_clock;
2317         dst_mode->crtc_hblank_start = src_mode->crtc_hblank_start;
2318         dst_mode->crtc_hblank_end = src_mode->crtc_hblank_end;
2319         dst_mode->crtc_hsync_start =  src_mode->crtc_hsync_start;
2320         dst_mode->crtc_hsync_end = src_mode->crtc_hsync_end;
2321         dst_mode->crtc_htotal = src_mode->crtc_htotal;
2322         dst_mode->crtc_hskew = src_mode->crtc_hskew;
2323         dst_mode->crtc_vblank_start = src_mode->crtc_vblank_start;
2324         dst_mode->crtc_vblank_end = src_mode->crtc_vblank_end;
2325         dst_mode->crtc_vsync_start = src_mode->crtc_vsync_start;
2326         dst_mode->crtc_vsync_end = src_mode->crtc_vsync_end;
2327         dst_mode->crtc_vtotal = src_mode->crtc_vtotal;
2328 }
2329
2330 static void
2331 decide_crtc_timing_for_drm_display_mode(struct drm_display_mode *drm_mode,
2332                                         const struct drm_display_mode *native_mode,
2333                                         bool scale_enabled)
2334 {
2335         if (scale_enabled) {
2336                 copy_crtc_timing_for_drm_display_mode(native_mode, drm_mode);
2337         } else if (native_mode->clock == drm_mode->clock &&
2338                         native_mode->htotal == drm_mode->htotal &&
2339                         native_mode->vtotal == drm_mode->vtotal) {
2340                 copy_crtc_timing_for_drm_display_mode(native_mode, drm_mode);
2341         } else {
2342                 /* no scaling nor amdgpu inserted, no need to patch */
2343         }
2344 }
2345
2346 static struct dc_sink *
2347 create_fake_sink(struct amdgpu_dm_connector *aconnector)
2348 {
2349         struct dc_sink_init_data sink_init_data = { 0 };
2350         struct dc_sink *sink = NULL;
2351         sink_init_data.link = aconnector->dc_link;
2352         sink_init_data.sink_signal = aconnector->dc_link->connector_signal;
2353
2354         sink = dc_sink_create(&sink_init_data);
2355         if (!sink) {
2356                 DRM_ERROR("Failed to create sink!\n");
2357                 return NULL;
2358         }
2359         sink->sink_signal = SIGNAL_TYPE_VIRTUAL;
2360
2361         return sink;
2362 }
2363
2364 static void set_multisync_trigger_params(
2365                 struct dc_stream_state *stream)
2366 {
2367         if (stream->triggered_crtc_reset.enabled) {
2368                 stream->triggered_crtc_reset.event = CRTC_EVENT_VSYNC_RISING;
2369                 stream->triggered_crtc_reset.delay = TRIGGER_DELAY_NEXT_LINE;
2370         }
2371 }
2372
2373 static void set_master_stream(struct dc_stream_state *stream_set[],
2374                               int stream_count)
2375 {
2376         int j, highest_rfr = 0, master_stream = 0;
2377
2378         for (j = 0;  j < stream_count; j++) {
2379                 if (stream_set[j] && stream_set[j]->triggered_crtc_reset.enabled) {
2380                         int refresh_rate = 0;
2381
2382                         refresh_rate = (stream_set[j]->timing.pix_clk_khz*1000)/
2383                                 (stream_set[j]->timing.h_total*stream_set[j]->timing.v_total);
2384                         if (refresh_rate > highest_rfr) {
2385                                 highest_rfr = refresh_rate;
2386                                 master_stream = j;
2387                         }
2388                 }
2389         }
2390         for (j = 0;  j < stream_count; j++) {
2391                 if (stream_set[j])
2392                         stream_set[j]->triggered_crtc_reset.event_source = stream_set[master_stream];
2393         }
2394 }
2395
2396 static void dm_enable_per_frame_crtc_master_sync(struct dc_state *context)
2397 {
2398         int i = 0;
2399
2400         if (context->stream_count < 2)
2401                 return;
2402         for (i = 0; i < context->stream_count ; i++) {
2403                 if (!context->streams[i])
2404                         continue;
2405                 /* TODO: add a function to read AMD VSDB bits and will set
2406                  * crtc_sync_master.multi_sync_enabled flag
2407                  * For now its set to false
2408                  */
2409                 set_multisync_trigger_params(context->streams[i]);
2410         }
2411         set_master_stream(context->streams, context->stream_count);
2412 }
2413
2414 static struct dc_stream_state *
2415 create_stream_for_sink(struct amdgpu_dm_connector *aconnector,
2416                        const struct drm_display_mode *drm_mode,
2417                        const struct dm_connector_state *dm_state)
2418 {
2419         struct drm_display_mode *preferred_mode = NULL;
2420         struct drm_connector *drm_connector;
2421         struct dc_stream_state *stream = NULL;
2422         struct drm_display_mode mode = *drm_mode;
2423         bool native_mode_found = false;
2424         struct dc_sink *sink = NULL;
2425         if (aconnector == NULL) {
2426                 DRM_ERROR("aconnector is NULL!\n");
2427                 return stream;
2428         }
2429
2430         drm_connector = &aconnector->base;
2431
2432         if (!aconnector->dc_sink) {
2433                 /*
2434                  * Create dc_sink when necessary to MST
2435                  * Don't apply fake_sink to MST
2436                  */
2437                 if (aconnector->mst_port) {
2438                         dm_dp_mst_dc_sink_create(drm_connector);
2439                         return stream;
2440                 }
2441
2442                 sink = create_fake_sink(aconnector);
2443                 if (!sink)
2444                         return stream;
2445         } else {
2446                 sink = aconnector->dc_sink;
2447         }
2448
2449         stream = dc_create_stream_for_sink(sink);
2450
2451         if (stream == NULL) {
2452                 DRM_ERROR("Failed to create stream for sink!\n");
2453                 goto finish;
2454         }
2455
2456         list_for_each_entry(preferred_mode, &aconnector->base.modes, head) {
2457                 /* Search for preferred mode */
2458                 if (preferred_mode->type & DRM_MODE_TYPE_PREFERRED) {
2459                         native_mode_found = true;
2460                         break;
2461                 }
2462         }
2463         if (!native_mode_found)
2464                 preferred_mode = list_first_entry_or_null(
2465                                 &aconnector->base.modes,
2466                                 struct drm_display_mode,
2467                                 head);
2468
2469         if (preferred_mode == NULL) {
2470                 /* This may not be an error, the use case is when we we have no
2471                  * usermode calls to reset and set mode upon hotplug. In this
2472                  * case, we call set mode ourselves to restore the previous mode
2473                  * and the modelist may not be filled in in time.
2474                  */
2475                 DRM_DEBUG_DRIVER("No preferred mode found\n");
2476         } else {
2477                 decide_crtc_timing_for_drm_display_mode(
2478                                 &mode, preferred_mode,
2479                                 dm_state ? (dm_state->scaling != RMX_OFF) : false);
2480         }
2481
2482         if (!dm_state)
2483                 drm_mode_set_crtcinfo(&mode, 0);
2484
2485         fill_stream_properties_from_drm_display_mode(stream,
2486                         &mode, &aconnector->base);
2487         update_stream_scaling_settings(&mode, dm_state, stream);
2488
2489         fill_audio_info(
2490                 &stream->audio_info,
2491                 drm_connector,
2492                 sink);
2493
2494         update_stream_signal(stream);
2495
2496         if (dm_state && dm_state->freesync_capable)
2497                 stream->ignore_msa_timing_param = true;
2498 finish:
2499         if (sink && sink->sink_signal == SIGNAL_TYPE_VIRTUAL)
2500                 dc_sink_release(sink);
2501
2502         return stream;
2503 }
2504
2505 static void amdgpu_dm_crtc_destroy(struct drm_crtc *crtc)
2506 {
2507         drm_crtc_cleanup(crtc);
2508         kfree(crtc);
2509 }
2510
2511 static void dm_crtc_destroy_state(struct drm_crtc *crtc,
2512                                   struct drm_crtc_state *state)
2513 {
2514         struct dm_crtc_state *cur = to_dm_crtc_state(state);
2515
2516         /* TODO Destroy dc_stream objects are stream object is flattened */
2517         if (cur->stream)
2518                 dc_stream_release(cur->stream);
2519
2520
2521         __drm_atomic_helper_crtc_destroy_state(state);
2522
2523
2524         kfree(state);
2525 }
2526
2527 static void dm_crtc_reset_state(struct drm_crtc *crtc)
2528 {
2529         struct dm_crtc_state *state;
2530
2531         if (crtc->state)
2532                 dm_crtc_destroy_state(crtc, crtc->state);
2533
2534         state = kzalloc(sizeof(*state), GFP_KERNEL);
2535         if (WARN_ON(!state))
2536                 return;
2537
2538         crtc->state = &state->base;
2539         crtc->state->crtc = crtc;
2540
2541 }
2542
2543 static struct drm_crtc_state *
2544 dm_crtc_duplicate_state(struct drm_crtc *crtc)
2545 {
2546         struct dm_crtc_state *state, *cur;
2547
2548         cur = to_dm_crtc_state(crtc->state);
2549
2550         if (WARN_ON(!crtc->state))
2551                 return NULL;
2552
2553         state = kzalloc(sizeof(*state), GFP_KERNEL);
2554         if (!state)
2555                 return NULL;
2556
2557         __drm_atomic_helper_crtc_duplicate_state(crtc, &state->base);
2558
2559         if (cur->stream) {
2560                 state->stream = cur->stream;
2561                 dc_stream_retain(state->stream);
2562         }
2563
2564         /* TODO Duplicate dc_stream after objects are stream object is flattened */
2565
2566         return &state->base;
2567 }
2568
2569
2570 static inline int dm_set_vblank(struct drm_crtc *crtc, bool enable)
2571 {
2572         enum dc_irq_source irq_source;
2573         struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
2574         struct amdgpu_device *adev = crtc->dev->dev_private;
2575
2576         irq_source = IRQ_TYPE_VBLANK + acrtc->otg_inst;
2577         return dc_interrupt_set(adev->dm.dc, irq_source, enable) ? 0 : -EBUSY;
2578 }
2579
2580 static int dm_enable_vblank(struct drm_crtc *crtc)
2581 {
2582         return dm_set_vblank(crtc, true);
2583 }
2584
2585 static void dm_disable_vblank(struct drm_crtc *crtc)
2586 {
2587         dm_set_vblank(crtc, false);
2588 }
2589
2590 /* Implemented only the options currently availible for the driver */
2591 static const struct drm_crtc_funcs amdgpu_dm_crtc_funcs = {
2592         .reset = dm_crtc_reset_state,
2593         .destroy = amdgpu_dm_crtc_destroy,
2594         .gamma_set = drm_atomic_helper_legacy_gamma_set,
2595         .set_config = drm_atomic_helper_set_config,
2596         .page_flip = drm_atomic_helper_page_flip,
2597         .atomic_duplicate_state = dm_crtc_duplicate_state,
2598         .atomic_destroy_state = dm_crtc_destroy_state,
2599         .set_crc_source = amdgpu_dm_crtc_set_crc_source,
2600         .enable_vblank = dm_enable_vblank,
2601         .disable_vblank = dm_disable_vblank,
2602 };
2603
2604 static enum drm_connector_status
2605 amdgpu_dm_connector_detect(struct drm_connector *connector, bool force)
2606 {
2607         bool connected;
2608         struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
2609
2610         /* Notes:
2611          * 1. This interface is NOT called in context of HPD irq.
2612          * 2. This interface *is called* in context of user-mode ioctl. Which
2613          * makes it a bad place for *any* MST-related activit. */
2614
2615         if (aconnector->base.force == DRM_FORCE_UNSPECIFIED &&
2616             !aconnector->fake_enable)
2617                 connected = (aconnector->dc_sink != NULL);
2618         else
2619                 connected = (aconnector->base.force == DRM_FORCE_ON);
2620
2621         return (connected ? connector_status_connected :
2622                         connector_status_disconnected);
2623 }
2624
2625 int amdgpu_dm_connector_atomic_set_property(struct drm_connector *connector,
2626                                             struct drm_connector_state *connector_state,
2627                                             struct drm_property *property,
2628                                             uint64_t val)
2629 {
2630         struct drm_device *dev = connector->dev;
2631         struct amdgpu_device *adev = dev->dev_private;
2632         struct dm_connector_state *dm_old_state =
2633                 to_dm_connector_state(connector->state);
2634         struct dm_connector_state *dm_new_state =
2635                 to_dm_connector_state(connector_state);
2636
2637         int ret = -EINVAL;
2638
2639         if (property == dev->mode_config.scaling_mode_property) {
2640                 enum amdgpu_rmx_type rmx_type;
2641
2642                 switch (val) {
2643                 case DRM_MODE_SCALE_CENTER:
2644                         rmx_type = RMX_CENTER;
2645                         break;
2646                 case DRM_MODE_SCALE_ASPECT:
2647                         rmx_type = RMX_ASPECT;
2648                         break;
2649                 case DRM_MODE_SCALE_FULLSCREEN:
2650                         rmx_type = RMX_FULL;
2651                         break;
2652                 case DRM_MODE_SCALE_NONE:
2653                 default:
2654                         rmx_type = RMX_OFF;
2655                         break;
2656                 }
2657
2658                 if (dm_old_state->scaling == rmx_type)
2659                         return 0;
2660
2661                 dm_new_state->scaling = rmx_type;
2662                 ret = 0;
2663         } else if (property == adev->mode_info.underscan_hborder_property) {
2664                 dm_new_state->underscan_hborder = val;
2665                 ret = 0;
2666         } else if (property == adev->mode_info.underscan_vborder_property) {
2667                 dm_new_state->underscan_vborder = val;
2668                 ret = 0;
2669         } else if (property == adev->mode_info.underscan_property) {
2670                 dm_new_state->underscan_enable = val;
2671                 ret = 0;
2672         }
2673
2674         return ret;
2675 }
2676
2677 int amdgpu_dm_connector_atomic_get_property(struct drm_connector *connector,
2678                                             const struct drm_connector_state *state,
2679                                             struct drm_property *property,
2680                                             uint64_t *val)
2681 {
2682         struct drm_device *dev = connector->dev;
2683         struct amdgpu_device *adev = dev->dev_private;
2684         struct dm_connector_state *dm_state =
2685                 to_dm_connector_state(state);
2686         int ret = -EINVAL;
2687
2688         if (property == dev->mode_config.scaling_mode_property) {
2689                 switch (dm_state->scaling) {
2690                 case RMX_CENTER:
2691                         *val = DRM_MODE_SCALE_CENTER;
2692                         break;
2693                 case RMX_ASPECT:
2694                         *val = DRM_MODE_SCALE_ASPECT;
2695                         break;
2696                 case RMX_FULL:
2697                         *val = DRM_MODE_SCALE_FULLSCREEN;
2698                         break;
2699                 case RMX_OFF:
2700                 default:
2701                         *val = DRM_MODE_SCALE_NONE;
2702                         break;
2703                 }
2704                 ret = 0;
2705         } else if (property == adev->mode_info.underscan_hborder_property) {
2706                 *val = dm_state->underscan_hborder;
2707                 ret = 0;
2708         } else if (property == adev->mode_info.underscan_vborder_property) {
2709                 *val = dm_state->underscan_vborder;
2710                 ret = 0;
2711         } else if (property == adev->mode_info.underscan_property) {
2712                 *val = dm_state->underscan_enable;
2713                 ret = 0;
2714         }
2715         return ret;
2716 }
2717
2718 static void amdgpu_dm_connector_destroy(struct drm_connector *connector)
2719 {
2720         struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
2721         const struct dc_link *link = aconnector->dc_link;
2722         struct amdgpu_device *adev = connector->dev->dev_private;
2723         struct amdgpu_display_manager *dm = &adev->dm;
2724
2725 #if defined(CONFIG_BACKLIGHT_CLASS_DEVICE) ||\
2726         defined(CONFIG_BACKLIGHT_CLASS_DEVICE_MODULE)
2727
2728         if ((link->connector_signal & (SIGNAL_TYPE_EDP | SIGNAL_TYPE_LVDS)) &&
2729             link->type != dc_connection_none &&
2730             dm->backlight_dev) {
2731                 backlight_device_unregister(dm->backlight_dev);
2732                 dm->backlight_dev = NULL;
2733         }
2734 #endif
2735         drm_connector_unregister(connector);
2736         drm_connector_cleanup(connector);
2737         kfree(connector);
2738 }
2739
2740 void amdgpu_dm_connector_funcs_reset(struct drm_connector *connector)
2741 {
2742         struct dm_connector_state *state =
2743                 to_dm_connector_state(connector->state);
2744
2745         if (connector->state)
2746                 __drm_atomic_helper_connector_destroy_state(connector->state);
2747
2748         kfree(state);
2749
2750         state = kzalloc(sizeof(*state), GFP_KERNEL);
2751
2752         if (state) {
2753                 state->scaling = RMX_OFF;
2754                 state->underscan_enable = false;
2755                 state->underscan_hborder = 0;
2756                 state->underscan_vborder = 0;
2757
2758                 __drm_atomic_helper_connector_reset(connector, &state->base);
2759         }
2760 }
2761
2762 struct drm_connector_state *
2763 amdgpu_dm_connector_atomic_duplicate_state(struct drm_connector *connector)
2764 {
2765         struct dm_connector_state *state =
2766                 to_dm_connector_state(connector->state);
2767
2768         struct dm_connector_state *new_state =
2769                         kmemdup(state, sizeof(*state), GFP_KERNEL);
2770
2771         if (new_state) {
2772                 __drm_atomic_helper_connector_duplicate_state(connector,
2773                                                               &new_state->base);
2774                 return &new_state->base;
2775         }
2776
2777         return NULL;
2778 }
2779
2780 static const struct drm_connector_funcs amdgpu_dm_connector_funcs = {
2781         .reset = amdgpu_dm_connector_funcs_reset,
2782         .detect = amdgpu_dm_connector_detect,
2783         .fill_modes = drm_helper_probe_single_connector_modes,
2784         .destroy = amdgpu_dm_connector_destroy,
2785         .atomic_duplicate_state = amdgpu_dm_connector_atomic_duplicate_state,
2786         .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
2787         .atomic_set_property = amdgpu_dm_connector_atomic_set_property,
2788         .atomic_get_property = amdgpu_dm_connector_atomic_get_property
2789 };
2790
2791 static struct drm_encoder *best_encoder(struct drm_connector *connector)
2792 {
2793         int enc_id = connector->encoder_ids[0];
2794         struct drm_mode_object *obj;
2795         struct drm_encoder *encoder;
2796
2797         DRM_DEBUG_DRIVER("Finding the best encoder\n");
2798
2799         /* pick the encoder ids */
2800         if (enc_id) {
2801                 obj = drm_mode_object_find(connector->dev, NULL, enc_id, DRM_MODE_OBJECT_ENCODER);
2802                 if (!obj) {
2803                         DRM_ERROR("Couldn't find a matching encoder for our connector\n");
2804                         return NULL;
2805                 }
2806                 encoder = obj_to_encoder(obj);
2807                 return encoder;
2808         }
2809         DRM_ERROR("No encoder id\n");
2810         return NULL;
2811 }
2812
2813 static int get_modes(struct drm_connector *connector)
2814 {
2815         return amdgpu_dm_connector_get_modes(connector);
2816 }
2817
2818 static void create_eml_sink(struct amdgpu_dm_connector *aconnector)
2819 {
2820         struct dc_sink_init_data init_params = {
2821                         .link = aconnector->dc_link,
2822                         .sink_signal = SIGNAL_TYPE_VIRTUAL
2823         };
2824         struct edid *edid;
2825
2826         if (!aconnector->base.edid_blob_ptr) {
2827                 DRM_ERROR("No EDID firmware found on connector: %s ,forcing to OFF!\n",
2828                                 aconnector->base.name);
2829
2830                 aconnector->base.force = DRM_FORCE_OFF;
2831                 aconnector->base.override_edid = false;
2832                 return;
2833         }
2834
2835         edid = (struct edid *) aconnector->base.edid_blob_ptr->data;
2836
2837         aconnector->edid = edid;
2838
2839         aconnector->dc_em_sink = dc_link_add_remote_sink(
2840                 aconnector->dc_link,
2841                 (uint8_t *)edid,
2842                 (edid->extensions + 1) * EDID_LENGTH,
2843                 &init_params);
2844
2845         if (aconnector->base.force == DRM_FORCE_ON)
2846                 aconnector->dc_sink = aconnector->dc_link->local_sink ?
2847                 aconnector->dc_link->local_sink :
2848                 aconnector->dc_em_sink;
2849 }
2850
2851 static void handle_edid_mgmt(struct amdgpu_dm_connector *aconnector)
2852 {
2853         struct dc_link *link = (struct dc_link *)aconnector->dc_link;
2854
2855         /* In case of headless boot with force on for DP managed connector
2856          * Those settings have to be != 0 to get initial modeset
2857          */
2858         if (link->connector_signal == SIGNAL_TYPE_DISPLAY_PORT) {
2859                 link->verified_link_cap.lane_count = LANE_COUNT_FOUR;
2860                 link->verified_link_cap.link_rate = LINK_RATE_HIGH2;
2861         }
2862
2863
2864         aconnector->base.override_edid = true;
2865         create_eml_sink(aconnector);
2866 }
2867
2868 enum drm_mode_status amdgpu_dm_connector_mode_valid(struct drm_connector *connector,
2869                                    struct drm_display_mode *mode)
2870 {
2871         int result = MODE_ERROR;
2872         struct dc_sink *dc_sink;
2873         struct amdgpu_device *adev = connector->dev->dev_private;
2874         /* TODO: Unhardcode stream count */
2875         struct dc_stream_state *stream;
2876         struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
2877         enum dc_status dc_result = DC_OK;
2878
2879         if ((mode->flags & DRM_MODE_FLAG_INTERLACE) ||
2880                         (mode->flags & DRM_MODE_FLAG_DBLSCAN))
2881                 return result;
2882
2883         /* Only run this the first time mode_valid is called to initilialize
2884          * EDID mgmt
2885          */
2886         if (aconnector->base.force != DRM_FORCE_UNSPECIFIED &&
2887                 !aconnector->dc_em_sink)
2888                 handle_edid_mgmt(aconnector);
2889
2890         dc_sink = to_amdgpu_dm_connector(connector)->dc_sink;
2891
2892         if (dc_sink == NULL) {
2893                 DRM_ERROR("dc_sink is NULL!\n");
2894                 goto fail;
2895         }
2896
2897         stream = create_stream_for_sink(aconnector, mode, NULL);
2898         if (stream == NULL) {
2899                 DRM_ERROR("Failed to create stream for sink!\n");
2900                 goto fail;
2901         }
2902
2903         dc_result = dc_validate_stream(adev->dm.dc, stream);
2904
2905         if (dc_result == DC_OK)
2906                 result = MODE_OK;
2907         else
2908                 DRM_DEBUG_KMS("Mode %dx%d (clk %d) failed DC validation with error %d\n",
2909                               mode->vdisplay,
2910                               mode->hdisplay,
2911                               mode->clock,
2912                               dc_result);
2913
2914         dc_stream_release(stream);
2915
2916 fail:
2917         /* TODO: error handling*/
2918         return result;
2919 }
2920
2921 static const struct drm_connector_helper_funcs
2922 amdgpu_dm_connector_helper_funcs = {
2923         /*
2924          * If hotplug a second bigger display in FB Con mode, bigger resolution
2925          * modes will be filtered by drm_mode_validate_size(), and those modes
2926          * is missing after user start lightdm. So we need to renew modes list.
2927          * in get_modes call back, not just return the modes count
2928          */
2929         .get_modes = get_modes,
2930         .mode_valid = amdgpu_dm_connector_mode_valid,
2931         .best_encoder = best_encoder
2932 };
2933
2934 static void dm_crtc_helper_disable(struct drm_crtc *crtc)
2935 {
2936 }
2937
2938 static int dm_crtc_helper_atomic_check(struct drm_crtc *crtc,
2939                                        struct drm_crtc_state *state)
2940 {
2941         struct amdgpu_device *adev = crtc->dev->dev_private;
2942         struct dc *dc = adev->dm.dc;
2943         struct dm_crtc_state *dm_crtc_state = to_dm_crtc_state(state);
2944         int ret = -EINVAL;
2945
2946         if (unlikely(!dm_crtc_state->stream &&
2947                      modeset_required(state, NULL, dm_crtc_state->stream))) {
2948                 WARN_ON(1);
2949                 return ret;
2950         }
2951
2952         /* In some use cases, like reset, no stream  is attached */
2953         if (!dm_crtc_state->stream)
2954                 return 0;
2955
2956         if (dc_validate_stream(dc, dm_crtc_state->stream) == DC_OK)
2957                 return 0;
2958
2959         return ret;
2960 }
2961
2962 static bool dm_crtc_helper_mode_fixup(struct drm_crtc *crtc,
2963                                       const struct drm_display_mode *mode,
2964                                       struct drm_display_mode *adjusted_mode)
2965 {
2966         return true;
2967 }
2968
2969 static const struct drm_crtc_helper_funcs amdgpu_dm_crtc_helper_funcs = {
2970         .disable = dm_crtc_helper_disable,
2971         .atomic_check = dm_crtc_helper_atomic_check,
2972         .mode_fixup = dm_crtc_helper_mode_fixup
2973 };
2974
2975 static void dm_encoder_helper_disable(struct drm_encoder *encoder)
2976 {
2977
2978 }
2979
2980 static int dm_encoder_helper_atomic_check(struct drm_encoder *encoder,
2981                                           struct drm_crtc_state *crtc_state,
2982                                           struct drm_connector_state *conn_state)
2983 {
2984         return 0;
2985 }
2986
2987 const struct drm_encoder_helper_funcs amdgpu_dm_encoder_helper_funcs = {
2988         .disable = dm_encoder_helper_disable,
2989         .atomic_check = dm_encoder_helper_atomic_check
2990 };
2991
2992 static void dm_drm_plane_reset(struct drm_plane *plane)
2993 {
2994         struct dm_plane_state *amdgpu_state = NULL;
2995
2996         if (plane->state)
2997                 plane->funcs->atomic_destroy_state(plane, plane->state);
2998
2999         amdgpu_state = kzalloc(sizeof(*amdgpu_state), GFP_KERNEL);
3000         WARN_ON(amdgpu_state == NULL);
3001
3002         if (amdgpu_state) {
3003                 plane->state = &amdgpu_state->base;
3004                 plane->state->plane = plane;
3005                 plane->state->rotation = DRM_MODE_ROTATE_0;
3006         }
3007 }
3008
3009 static struct drm_plane_state *
3010 dm_drm_plane_duplicate_state(struct drm_plane *plane)
3011 {
3012         struct dm_plane_state *dm_plane_state, *old_dm_plane_state;
3013
3014         old_dm_plane_state = to_dm_plane_state(plane->state);
3015         dm_plane_state = kzalloc(sizeof(*dm_plane_state), GFP_KERNEL);
3016         if (!dm_plane_state)
3017                 return NULL;
3018
3019         __drm_atomic_helper_plane_duplicate_state(plane, &dm_plane_state->base);
3020
3021         if (old_dm_plane_state->dc_state) {
3022                 dm_plane_state->dc_state = old_dm_plane_state->dc_state;
3023                 dc_plane_state_retain(dm_plane_state->dc_state);
3024         }
3025
3026         return &dm_plane_state->base;
3027 }
3028
3029 void dm_drm_plane_destroy_state(struct drm_plane *plane,
3030                                 struct drm_plane_state *state)
3031 {
3032         struct dm_plane_state *dm_plane_state = to_dm_plane_state(state);
3033
3034         if (dm_plane_state->dc_state)
3035                 dc_plane_state_release(dm_plane_state->dc_state);
3036
3037         drm_atomic_helper_plane_destroy_state(plane, state);
3038 }
3039
3040 static const struct drm_plane_funcs dm_plane_funcs = {
3041         .update_plane   = drm_atomic_helper_update_plane,
3042         .disable_plane  = drm_atomic_helper_disable_plane,
3043         .destroy        = drm_plane_cleanup,
3044         .reset = dm_drm_plane_reset,
3045         .atomic_duplicate_state = dm_drm_plane_duplicate_state,
3046         .atomic_destroy_state = dm_drm_plane_destroy_state,
3047 };
3048
3049 static int dm_plane_helper_prepare_fb(struct drm_plane *plane,
3050                                       struct drm_plane_state *new_state)
3051 {
3052         struct amdgpu_framebuffer *afb;
3053         struct drm_gem_object *obj;
3054         struct amdgpu_device *adev;
3055         struct amdgpu_bo *rbo;
3056         uint64_t chroma_addr = 0;
3057         struct dm_plane_state *dm_plane_state_new, *dm_plane_state_old;
3058         unsigned int awidth;
3059         uint32_t domain;
3060         int r;
3061
3062         dm_plane_state_old = to_dm_plane_state(plane->state);
3063         dm_plane_state_new = to_dm_plane_state(new_state);
3064
3065         if (!new_state->fb) {
3066                 DRM_DEBUG_DRIVER("No FB bound\n");
3067                 return 0;
3068         }
3069
3070         afb = to_amdgpu_framebuffer(new_state->fb);
3071         obj = new_state->fb->obj[0];
3072         rbo = gem_to_amdgpu_bo(obj);
3073         adev = amdgpu_ttm_adev(rbo->tbo.bdev);
3074         r = amdgpu_bo_reserve(rbo, false);
3075         if (unlikely(r != 0))
3076                 return r;
3077
3078         if (plane->type != DRM_PLANE_TYPE_CURSOR)
3079                 domain = amdgpu_display_supported_domains(adev);
3080         else
3081                 domain = AMDGPU_GEM_DOMAIN_VRAM;
3082
3083         r = amdgpu_bo_pin(rbo, domain);
3084         if (unlikely(r != 0)) {
3085                 if (r != -ERESTARTSYS)
3086                         DRM_ERROR("Failed to pin framebuffer with error %d\n", r);
3087                 amdgpu_bo_unreserve(rbo);
3088                 return r;
3089         }
3090
3091         r = amdgpu_ttm_alloc_gart(&rbo->tbo);
3092         if (unlikely(r != 0)) {
3093                 amdgpu_bo_unpin(rbo);
3094                 amdgpu_bo_unreserve(rbo);
3095                 DRM_ERROR("%p bind failed\n", rbo);
3096                 return r;
3097         }
3098         amdgpu_bo_unreserve(rbo);
3099
3100         afb->address = amdgpu_bo_gpu_offset(rbo);
3101
3102         amdgpu_bo_ref(rbo);
3103
3104         if (dm_plane_state_new->dc_state &&
3105                         dm_plane_state_old->dc_state != dm_plane_state_new->dc_state) {
3106                 struct dc_plane_state *plane_state = dm_plane_state_new->dc_state;
3107
3108                 if (plane_state->format < SURFACE_PIXEL_FORMAT_VIDEO_BEGIN) {
3109                         plane_state->address.grph.addr.low_part = lower_32_bits(afb->address);
3110                         plane_state->address.grph.addr.high_part = upper_32_bits(afb->address);
3111                 } else {
3112                         awidth = ALIGN(new_state->fb->width, 64);
3113                         plane_state->address.type = PLN_ADDR_TYPE_VIDEO_PROGRESSIVE;
3114                         plane_state->address.video_progressive.luma_addr.low_part
3115                                                         = lower_32_bits(afb->address);
3116                         plane_state->address.video_progressive.luma_addr.high_part
3117                                                         = upper_32_bits(afb->address);
3118                         chroma_addr = afb->address + (u64)awidth * new_state->fb->height;
3119                         plane_state->address.video_progressive.chroma_addr.low_part
3120                                                         = lower_32_bits(chroma_addr);
3121                         plane_state->address.video_progressive.chroma_addr.high_part
3122                                                         = upper_32_bits(chroma_addr);
3123                 }
3124         }
3125
3126         return 0;
3127 }
3128
3129 static void dm_plane_helper_cleanup_fb(struct drm_plane *plane,
3130                                        struct drm_plane_state *old_state)
3131 {
3132         struct amdgpu_bo *rbo;
3133         int r;
3134
3135         if (!old_state->fb)
3136                 return;
3137
3138         rbo = gem_to_amdgpu_bo(old_state->fb->obj[0]);
3139         r = amdgpu_bo_reserve(rbo, false);
3140         if (unlikely(r)) {
3141                 DRM_ERROR("failed to reserve rbo before unpin\n");
3142                 return;
3143         }
3144
3145         amdgpu_bo_unpin(rbo);
3146         amdgpu_bo_unreserve(rbo);
3147         amdgpu_bo_unref(&rbo);
3148 }
3149
3150 static int dm_plane_atomic_check(struct drm_plane *plane,
3151                                  struct drm_plane_state *state)
3152 {
3153         struct amdgpu_device *adev = plane->dev->dev_private;
3154         struct dc *dc = adev->dm.dc;
3155         struct dm_plane_state *dm_plane_state = to_dm_plane_state(state);
3156
3157         if (!dm_plane_state->dc_state)
3158                 return 0;
3159
3160         if (!fill_rects_from_plane_state(state, dm_plane_state->dc_state))
3161                 return -EINVAL;
3162
3163         if (dc_validate_plane(dc, dm_plane_state->dc_state) == DC_OK)
3164                 return 0;
3165
3166         return -EINVAL;
3167 }
3168
3169 static const struct drm_plane_helper_funcs dm_plane_helper_funcs = {
3170         .prepare_fb = dm_plane_helper_prepare_fb,
3171         .cleanup_fb = dm_plane_helper_cleanup_fb,
3172         .atomic_check = dm_plane_atomic_check,
3173 };
3174
3175 /*
3176  * TODO: these are currently initialized to rgb formats only.
3177  * For future use cases we should either initialize them dynamically based on
3178  * plane capabilities, or initialize this array to all formats, so internal drm
3179  * check will succeed, and let DC to implement proper check
3180  */
3181 static const uint32_t rgb_formats[] = {
3182         DRM_FORMAT_RGB888,
3183         DRM_FORMAT_XRGB8888,
3184         DRM_FORMAT_ARGB8888,
3185         DRM_FORMAT_RGBA8888,
3186         DRM_FORMAT_XRGB2101010,
3187         DRM_FORMAT_XBGR2101010,
3188         DRM_FORMAT_ARGB2101010,
3189         DRM_FORMAT_ABGR2101010,
3190 };
3191
3192 static const uint32_t yuv_formats[] = {
3193         DRM_FORMAT_NV12,
3194         DRM_FORMAT_NV21,
3195 };
3196
3197 static const u32 cursor_formats[] = {
3198         DRM_FORMAT_ARGB8888
3199 };
3200
3201 static int amdgpu_dm_plane_init(struct amdgpu_display_manager *dm,
3202                                 struct amdgpu_plane *aplane,
3203                                 unsigned long possible_crtcs)
3204 {
3205         int res = -EPERM;
3206
3207         switch (aplane->base.type) {
3208         case DRM_PLANE_TYPE_PRIMARY:
3209                 res = drm_universal_plane_init(
3210                                 dm->adev->ddev,
3211                                 &aplane->base,
3212                                 possible_crtcs,
3213                                 &dm_plane_funcs,
3214                                 rgb_formats,
3215                                 ARRAY_SIZE(rgb_formats),
3216                                 NULL, aplane->base.type, NULL);
3217                 break;
3218         case DRM_PLANE_TYPE_OVERLAY:
3219                 res = drm_universal_plane_init(
3220                                 dm->adev->ddev,
3221                                 &aplane->base,
3222                                 possible_crtcs,
3223                                 &dm_plane_funcs,
3224                                 yuv_formats,
3225                                 ARRAY_SIZE(yuv_formats),
3226                                 NULL, aplane->base.type, NULL);
3227                 break;
3228         case DRM_PLANE_TYPE_CURSOR:
3229                 res = drm_universal_plane_init(
3230                                 dm->adev->ddev,
3231                                 &aplane->base,
3232                                 possible_crtcs,
3233                                 &dm_plane_funcs,
3234                                 cursor_formats,
3235                                 ARRAY_SIZE(cursor_formats),
3236                                 NULL, aplane->base.type, NULL);
3237                 break;
3238         }
3239
3240         drm_plane_helper_add(&aplane->base, &dm_plane_helper_funcs);
3241
3242         /* Create (reset) the plane state */
3243         if (aplane->base.funcs->reset)
3244                 aplane->base.funcs->reset(&aplane->base);
3245
3246
3247         return res;
3248 }
3249
3250 static int amdgpu_dm_crtc_init(struct amdgpu_display_manager *dm,
3251                                struct drm_plane *plane,
3252                                uint32_t crtc_index)
3253 {
3254         struct amdgpu_crtc *acrtc = NULL;
3255         struct amdgpu_plane *cursor_plane;
3256
3257         int res = -ENOMEM;
3258
3259         cursor_plane = kzalloc(sizeof(*cursor_plane), GFP_KERNEL);
3260         if (!cursor_plane)
3261                 goto fail;
3262
3263         cursor_plane->base.type = DRM_PLANE_TYPE_CURSOR;
3264         res = amdgpu_dm_plane_init(dm, cursor_plane, 0);
3265
3266         acrtc = kzalloc(sizeof(struct amdgpu_crtc), GFP_KERNEL);
3267         if (!acrtc)
3268                 goto fail;
3269
3270         res = drm_crtc_init_with_planes(
3271                         dm->ddev,
3272                         &acrtc->base,
3273                         plane,
3274                         &cursor_plane->base,
3275                         &amdgpu_dm_crtc_funcs, NULL);
3276
3277         if (res)
3278                 goto fail;
3279
3280         drm_crtc_helper_add(&acrtc->base, &amdgpu_dm_crtc_helper_funcs);
3281
3282         /* Create (reset) the plane state */
3283         if (acrtc->base.funcs->reset)
3284                 acrtc->base.funcs->reset(&acrtc->base);
3285
3286         acrtc->max_cursor_width = dm->adev->dm.dc->caps.max_cursor_size;
3287         acrtc->max_cursor_height = dm->adev->dm.dc->caps.max_cursor_size;
3288
3289         acrtc->crtc_id = crtc_index;
3290         acrtc->base.enabled = false;
3291
3292         dm->adev->mode_info.crtcs[crtc_index] = acrtc;
3293         drm_crtc_enable_color_mgmt(&acrtc->base, MAX_COLOR_LUT_ENTRIES,
3294                                    true, MAX_COLOR_LUT_ENTRIES);
3295         drm_mode_crtc_set_gamma_size(&acrtc->base, MAX_COLOR_LEGACY_LUT_ENTRIES);
3296
3297         return 0;
3298
3299 fail:
3300         kfree(acrtc);
3301         kfree(cursor_plane);
3302         return res;
3303 }
3304
3305
3306 static int to_drm_connector_type(enum signal_type st)
3307 {
3308         switch (st) {
3309         case SIGNAL_TYPE_HDMI_TYPE_A:
3310                 return DRM_MODE_CONNECTOR_HDMIA;
3311         case SIGNAL_TYPE_EDP:
3312                 return DRM_MODE_CONNECTOR_eDP;
3313         case SIGNAL_TYPE_RGB:
3314                 return DRM_MODE_CONNECTOR_VGA;
3315         case SIGNAL_TYPE_DISPLAY_PORT:
3316         case SIGNAL_TYPE_DISPLAY_PORT_MST:
3317                 return DRM_MODE_CONNECTOR_DisplayPort;
3318         case SIGNAL_TYPE_DVI_DUAL_LINK:
3319         case SIGNAL_TYPE_DVI_SINGLE_LINK:
3320                 return DRM_MODE_CONNECTOR_DVID;
3321         case SIGNAL_TYPE_VIRTUAL:
3322                 return DRM_MODE_CONNECTOR_VIRTUAL;
3323
3324         default:
3325                 return DRM_MODE_CONNECTOR_Unknown;
3326         }
3327 }
3328
3329 static void amdgpu_dm_get_native_mode(struct drm_connector *connector)
3330 {
3331         const struct drm_connector_helper_funcs *helper =
3332                 connector->helper_private;
3333         struct drm_encoder *encoder;
3334         struct amdgpu_encoder *amdgpu_encoder;
3335
3336         encoder = helper->best_encoder(connector);
3337
3338         if (encoder == NULL)
3339                 return;
3340
3341         amdgpu_encoder = to_amdgpu_encoder(encoder);
3342
3343         amdgpu_encoder->native_mode.clock = 0;
3344
3345         if (!list_empty(&connector->probed_modes)) {
3346                 struct drm_display_mode *preferred_mode = NULL;
3347
3348                 list_for_each_entry(preferred_mode,
3349                                     &connector->probed_modes,
3350                                     head) {
3351                         if (preferred_mode->type & DRM_MODE_TYPE_PREFERRED)
3352                                 amdgpu_encoder->native_mode = *preferred_mode;
3353
3354                         break;
3355                 }
3356
3357         }
3358 }
3359
3360 static struct drm_display_mode *
3361 amdgpu_dm_create_common_mode(struct drm_encoder *encoder,
3362                              char *name,
3363                              int hdisplay, int vdisplay)
3364 {
3365         struct drm_device *dev = encoder->dev;
3366         struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
3367         struct drm_display_mode *mode = NULL;
3368         struct drm_display_mode *native_mode = &amdgpu_encoder->native_mode;
3369
3370         mode = drm_mode_duplicate(dev, native_mode);
3371
3372         if (mode == NULL)
3373                 return NULL;
3374
3375         mode->hdisplay = hdisplay;
3376         mode->vdisplay = vdisplay;
3377         mode->type &= ~DRM_MODE_TYPE_PREFERRED;
3378         strncpy(mode->name, name, DRM_DISPLAY_MODE_LEN);
3379
3380         return mode;
3381
3382 }
3383
3384 static void amdgpu_dm_connector_add_common_modes(struct drm_encoder *encoder,
3385                                                  struct drm_connector *connector)
3386 {
3387         struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
3388         struct drm_display_mode *mode = NULL;
3389         struct drm_display_mode *native_mode = &amdgpu_encoder->native_mode;
3390         struct amdgpu_dm_connector *amdgpu_dm_connector =
3391                                 to_amdgpu_dm_connector(connector);
3392         int i;
3393         int n;
3394         struct mode_size {
3395                 char name[DRM_DISPLAY_MODE_LEN];
3396                 int w;
3397                 int h;
3398         } common_modes[] = {
3399                 {  "640x480",  640,  480},
3400                 {  "800x600",  800,  600},
3401                 { "1024x768", 1024,  768},
3402                 { "1280x720", 1280,  720},
3403                 { "1280x800", 1280,  800},
3404                 {"1280x1024", 1280, 1024},
3405                 { "1440x900", 1440,  900},
3406                 {"1680x1050", 1680, 1050},
3407                 {"1600x1200", 1600, 1200},
3408                 {"1920x1080", 1920, 1080},
3409                 {"1920x1200", 1920, 1200}
3410         };
3411
3412         n = ARRAY_SIZE(common_modes);
3413
3414         for (i = 0; i < n; i++) {
3415                 struct drm_display_mode *curmode = NULL;
3416                 bool mode_existed = false;
3417
3418                 if (common_modes[i].w > native_mode->hdisplay ||
3419                     common_modes[i].h > native_mode->vdisplay ||
3420                    (common_modes[i].w == native_mode->hdisplay &&
3421                     common_modes[i].h == native_mode->vdisplay))
3422                         continue;
3423
3424                 list_for_each_entry(curmode, &connector->probed_modes, head) {
3425                         if (common_modes[i].w == curmode->hdisplay &&
3426                             common_modes[i].h == curmode->vdisplay) {
3427                                 mode_existed = true;
3428                                 break;
3429                         }
3430                 }
3431
3432                 if (mode_existed)
3433                         continue;
3434
3435                 mode = amdgpu_dm_create_common_mode(encoder,
3436                                 common_modes[i].name, common_modes[i].w,
3437                                 common_modes[i].h);
3438                 drm_mode_probed_add(connector, mode);
3439                 amdgpu_dm_connector->num_modes++;
3440         }
3441 }
3442
3443 static void amdgpu_dm_connector_ddc_get_modes(struct drm_connector *connector,
3444                                               struct edid *edid)
3445 {
3446         struct amdgpu_dm_connector *amdgpu_dm_connector =
3447                         to_amdgpu_dm_connector(connector);
3448
3449         if (edid) {
3450                 /* empty probed_modes */
3451                 INIT_LIST_HEAD(&connector->probed_modes);
3452                 amdgpu_dm_connector->num_modes =
3453                                 drm_add_edid_modes(connector, edid);
3454
3455                 amdgpu_dm_get_native_mode(connector);
3456         } else {
3457                 amdgpu_dm_connector->num_modes = 0;
3458         }
3459 }
3460
3461 static int amdgpu_dm_connector_get_modes(struct drm_connector *connector)
3462 {
3463         const struct drm_connector_helper_funcs *helper =
3464                         connector->helper_private;
3465         struct amdgpu_dm_connector *amdgpu_dm_connector =
3466                         to_amdgpu_dm_connector(connector);
3467         struct drm_encoder *encoder;
3468         struct edid *edid = amdgpu_dm_connector->edid;
3469
3470         encoder = helper->best_encoder(connector);
3471
3472         if (!edid || !drm_edid_is_valid(edid)) {
3473                 drm_add_modes_noedid(connector, 640, 480);
3474         } else {
3475                 amdgpu_dm_connector_ddc_get_modes(connector, edid);
3476                 amdgpu_dm_connector_add_common_modes(encoder, connector);
3477         }
3478         amdgpu_dm_fbc_init(connector);
3479
3480         return amdgpu_dm_connector->num_modes;
3481 }
3482
3483 void amdgpu_dm_connector_init_helper(struct amdgpu_display_manager *dm,
3484                                      struct amdgpu_dm_connector *aconnector,
3485                                      int connector_type,
3486                                      struct dc_link *link,
3487                                      int link_index)
3488 {
3489         struct amdgpu_device *adev = dm->ddev->dev_private;
3490
3491         aconnector->connector_id = link_index;
3492         aconnector->dc_link = link;
3493         aconnector->base.interlace_allowed = false;
3494         aconnector->base.doublescan_allowed = false;
3495         aconnector->base.stereo_allowed = false;
3496         aconnector->base.dpms = DRM_MODE_DPMS_OFF;
3497         aconnector->hpd.hpd = AMDGPU_HPD_NONE; /* not used */
3498         mutex_init(&aconnector->hpd_lock);
3499
3500         /* configure support HPD hot plug connector_>polled default value is 0
3501          * which means HPD hot plug not supported
3502          */
3503         switch (connector_type) {
3504         case DRM_MODE_CONNECTOR_HDMIA:
3505                 aconnector->base.polled = DRM_CONNECTOR_POLL_HPD;
3506                 aconnector->base.ycbcr_420_allowed =
3507                         link->link_enc->features.ycbcr420_supported ? true : false;
3508                 break;
3509         case DRM_MODE_CONNECTOR_DisplayPort:
3510                 aconnector->base.polled = DRM_CONNECTOR_POLL_HPD;
3511                 aconnector->base.ycbcr_420_allowed =
3512                         link->link_enc->features.ycbcr420_supported ? true : false;
3513                 break;
3514         case DRM_MODE_CONNECTOR_DVID:
3515                 aconnector->base.polled = DRM_CONNECTOR_POLL_HPD;
3516                 break;
3517         default:
3518                 break;
3519         }
3520
3521         drm_object_attach_property(&aconnector->base.base,
3522                                 dm->ddev->mode_config.scaling_mode_property,
3523                                 DRM_MODE_SCALE_NONE);
3524
3525         drm_object_attach_property(&aconnector->base.base,
3526                                 adev->mode_info.underscan_property,
3527                                 UNDERSCAN_OFF);
3528         drm_object_attach_property(&aconnector->base.base,
3529                                 adev->mode_info.underscan_hborder_property,
3530                                 0);
3531         drm_object_attach_property(&aconnector->base.base,
3532                                 adev->mode_info.underscan_vborder_property,
3533                                 0);
3534
3535 }
3536
3537 static int amdgpu_dm_i2c_xfer(struct i2c_adapter *i2c_adap,
3538                               struct i2c_msg *msgs, int num)
3539 {
3540         struct amdgpu_i2c_adapter *i2c = i2c_get_adapdata(i2c_adap);
3541         struct ddc_service *ddc_service = i2c->ddc_service;
3542         struct i2c_command cmd;
3543         int i;
3544         int result = -EIO;
3545
3546         cmd.payloads = kcalloc(num, sizeof(struct i2c_payload), GFP_KERNEL);
3547
3548         if (!cmd.payloads)
3549                 return result;
3550
3551         cmd.number_of_payloads = num;
3552         cmd.engine = I2C_COMMAND_ENGINE_DEFAULT;
3553         cmd.speed = 100;
3554
3555         for (i = 0; i < num; i++) {
3556                 cmd.payloads[i].write = !(msgs[i].flags & I2C_M_RD);
3557                 cmd.payloads[i].address = msgs[i].addr;
3558                 cmd.payloads[i].length = msgs[i].len;
3559                 cmd.payloads[i].data = msgs[i].buf;
3560         }
3561
3562         if (dal_i2caux_submit_i2c_command(
3563                         ddc_service->ctx->i2caux,
3564                         ddc_service->ddc_pin,
3565                         &cmd))
3566                 result = num;
3567
3568         kfree(cmd.payloads);
3569         return result;
3570 }
3571
3572 static u32 amdgpu_dm_i2c_func(struct i2c_adapter *adap)
3573 {
3574         return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
3575 }
3576
3577 static const struct i2c_algorithm amdgpu_dm_i2c_algo = {
3578         .master_xfer = amdgpu_dm_i2c_xfer,
3579         .functionality = amdgpu_dm_i2c_func,
3580 };
3581
3582 static struct amdgpu_i2c_adapter *
3583 create_i2c(struct ddc_service *ddc_service,
3584            int link_index,
3585            int *res)
3586 {
3587         struct amdgpu_device *adev = ddc_service->ctx->driver_context;
3588         struct amdgpu_i2c_adapter *i2c;
3589
3590         i2c = kzalloc(sizeof(struct amdgpu_i2c_adapter), GFP_KERNEL);
3591         if (!i2c)
3592                 return NULL;
3593         i2c->base.owner = THIS_MODULE;
3594         i2c->base.class = I2C_CLASS_DDC;
3595         i2c->base.dev.parent = &adev->pdev->dev;
3596         i2c->base.algo = &amdgpu_dm_i2c_algo;
3597         snprintf(i2c->base.name, sizeof(i2c->base.name), "AMDGPU DM i2c hw bus %d", link_index);
3598         i2c_set_adapdata(&i2c->base, i2c);
3599         i2c->ddc_service = ddc_service;
3600
3601         return i2c;
3602 }
3603
3604
3605 /* Note: this function assumes that dc_link_detect() was called for the
3606  * dc_link which will be represented by this aconnector.
3607  */
3608 static int amdgpu_dm_connector_init(struct amdgpu_display_manager *dm,
3609                                     struct amdgpu_dm_connector *aconnector,
3610                                     uint32_t link_index,
3611                                     struct amdgpu_encoder *aencoder)
3612 {
3613         int res = 0;
3614         int connector_type;
3615         struct dc *dc = dm->dc;
3616         struct dc_link *link = dc_get_link_at_index(dc, link_index);
3617         struct amdgpu_i2c_adapter *i2c;
3618
3619         link->priv = aconnector;
3620
3621         DRM_DEBUG_DRIVER("%s()\n", __func__);
3622
3623         i2c = create_i2c(link->ddc, link->link_index, &res);
3624         if (!i2c) {
3625                 DRM_ERROR("Failed to create i2c adapter data\n");
3626                 return -ENOMEM;
3627         }
3628
3629         aconnector->i2c = i2c;
3630         res = i2c_add_adapter(&i2c->base);
3631
3632         if (res) {
3633                 DRM_ERROR("Failed to register hw i2c %d\n", link->link_index);
3634                 goto out_free;
3635         }
3636
3637         connector_type = to_drm_connector_type(link->connector_signal);
3638
3639         res = drm_connector_init(
3640                         dm->ddev,
3641                         &aconnector->base,
3642                         &amdgpu_dm_connector_funcs,
3643                         connector_type);
3644
3645         if (res) {
3646                 DRM_ERROR("connector_init failed\n");
3647                 aconnector->connector_id = -1;
3648                 goto out_free;
3649         }
3650
3651         drm_connector_helper_add(
3652                         &aconnector->base,
3653                         &amdgpu_dm_connector_helper_funcs);
3654
3655         if (aconnector->base.funcs->reset)
3656                 aconnector->base.funcs->reset(&aconnector->base);
3657
3658         amdgpu_dm_connector_init_helper(
3659                 dm,
3660                 aconnector,
3661                 connector_type,
3662                 link,
3663                 link_index);
3664
3665         drm_connector_attach_encoder(
3666                 &aconnector->base, &aencoder->base);
3667
3668         drm_connector_register(&aconnector->base);
3669 #if defined(CONFIG_DEBUG_FS)
3670         res = connector_debugfs_init(aconnector);
3671         if (res) {
3672                 DRM_ERROR("Failed to create debugfs for connector");
3673                 goto out_free;
3674         }
3675 #endif
3676
3677         if (connector_type == DRM_MODE_CONNECTOR_DisplayPort
3678                 || connector_type == DRM_MODE_CONNECTOR_eDP)
3679                 amdgpu_dm_initialize_dp_connector(dm, aconnector);
3680
3681 out_free:
3682         if (res) {
3683                 kfree(i2c);
3684                 aconnector->i2c = NULL;
3685         }
3686         return res;
3687 }
3688
3689 int amdgpu_dm_get_encoder_crtc_mask(struct amdgpu_device *adev)
3690 {
3691         switch (adev->mode_info.num_crtc) {
3692         case 1:
3693                 return 0x1;
3694         case 2:
3695                 return 0x3;
3696         case 3:
3697                 return 0x7;
3698         case 4:
3699                 return 0xf;
3700         case 5:
3701                 return 0x1f;
3702         case 6:
3703         default:
3704                 return 0x3f;
3705         }
3706 }
3707
3708 static int amdgpu_dm_encoder_init(struct drm_device *dev,
3709                                   struct amdgpu_encoder *aencoder,
3710                                   uint32_t link_index)
3711 {
3712         struct amdgpu_device *adev = dev->dev_private;
3713
3714         int res = drm_encoder_init(dev,
3715                                    &aencoder->base,
3716                                    &amdgpu_dm_encoder_funcs,
3717                                    DRM_MODE_ENCODER_TMDS,
3718                                    NULL);
3719
3720         aencoder->base.possible_crtcs = amdgpu_dm_get_encoder_crtc_mask(adev);
3721
3722         if (!res)
3723                 aencoder->encoder_id = link_index;
3724         else
3725                 aencoder->encoder_id = -1;
3726
3727         drm_encoder_helper_add(&aencoder->base, &amdgpu_dm_encoder_helper_funcs);
3728
3729         return res;
3730 }
3731
3732 static void manage_dm_interrupts(struct amdgpu_device *adev,
3733                                  struct amdgpu_crtc *acrtc,
3734                                  bool enable)
3735 {
3736         /*
3737          * this is not correct translation but will work as soon as VBLANK
3738          * constant is the same as PFLIP
3739          */
3740         int irq_type =
3741                 amdgpu_display_crtc_idx_to_irq_type(
3742                         adev,
3743                         acrtc->crtc_id);
3744
3745         if (enable) {
3746                 drm_crtc_vblank_on(&acrtc->base);
3747                 amdgpu_irq_get(
3748                         adev,
3749                         &adev->pageflip_irq,
3750                         irq_type);
3751         } else {
3752
3753                 amdgpu_irq_put(
3754                         adev,
3755                         &adev->pageflip_irq,
3756                         irq_type);
3757                 drm_crtc_vblank_off(&acrtc->base);
3758         }
3759 }
3760
3761 static bool
3762 is_scaling_state_different(const struct dm_connector_state *dm_state,
3763                            const struct dm_connector_state *old_dm_state)
3764 {
3765         if (dm_state->scaling != old_dm_state->scaling)
3766                 return true;
3767         if (!dm_state->underscan_enable && old_dm_state->underscan_enable) {
3768                 if (old_dm_state->underscan_hborder != 0 && old_dm_state->underscan_vborder != 0)
3769                         return true;
3770         } else  if (dm_state->underscan_enable && !old_dm_state->underscan_enable) {
3771                 if (dm_state->underscan_hborder != 0 && dm_state->underscan_vborder != 0)
3772                         return true;
3773         } else if (dm_state->underscan_hborder != old_dm_state->underscan_hborder ||
3774                    dm_state->underscan_vborder != old_dm_state->underscan_vborder)
3775                 return true;
3776         return false;
3777 }
3778
3779 static void remove_stream(struct amdgpu_device *adev,
3780                           struct amdgpu_crtc *acrtc,
3781                           struct dc_stream_state *stream)
3782 {
3783         /* this is the update mode case */
3784         if (adev->dm.freesync_module)
3785                 mod_freesync_remove_stream(adev->dm.freesync_module, stream);
3786
3787         acrtc->otg_inst = -1;
3788         acrtc->enabled = false;
3789 }
3790
3791 static int get_cursor_position(struct drm_plane *plane, struct drm_crtc *crtc,
3792                                struct dc_cursor_position *position)
3793 {
3794         struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
3795         int x, y;
3796         int xorigin = 0, yorigin = 0;
3797
3798         if (!crtc || !plane->state->fb) {
3799                 position->enable = false;
3800                 position->x = 0;
3801                 position->y = 0;
3802                 return 0;
3803         }
3804
3805         if ((plane->state->crtc_w > amdgpu_crtc->max_cursor_width) ||
3806             (plane->state->crtc_h > amdgpu_crtc->max_cursor_height)) {
3807                 DRM_ERROR("%s: bad cursor width or height %d x %d\n",
3808                           __func__,
3809                           plane->state->crtc_w,
3810                           plane->state->crtc_h);
3811                 return -EINVAL;
3812         }
3813
3814         x = plane->state->crtc_x;
3815         y = plane->state->crtc_y;
3816         /* avivo cursor are offset into the total surface */
3817         x += crtc->primary->state->src_x >> 16;
3818         y += crtc->primary->state->src_y >> 16;
3819         if (x < 0) {
3820                 xorigin = min(-x, amdgpu_crtc->max_cursor_width - 1);
3821                 x = 0;
3822         }
3823         if (y < 0) {
3824                 yorigin = min(-y, amdgpu_crtc->max_cursor_height - 1);
3825                 y = 0;
3826         }
3827         position->enable = true;
3828         position->x = x;
3829         position->y = y;
3830         position->x_hotspot = xorigin;
3831         position->y_hotspot = yorigin;
3832
3833         return 0;
3834 }
3835
3836 static void handle_cursor_update(struct drm_plane *plane,
3837                                  struct drm_plane_state *old_plane_state)
3838 {
3839         struct amdgpu_framebuffer *afb = to_amdgpu_framebuffer(plane->state->fb);
3840         struct drm_crtc *crtc = afb ? plane->state->crtc : old_plane_state->crtc;
3841         struct dm_crtc_state *crtc_state = crtc ? to_dm_crtc_state(crtc->state) : NULL;
3842         struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
3843         uint64_t address = afb ? afb->address : 0;
3844         struct dc_cursor_position position;
3845         struct dc_cursor_attributes attributes;
3846         int ret;
3847
3848         if (!plane->state->fb && !old_plane_state->fb)
3849                 return;
3850
3851         DRM_DEBUG_DRIVER("%s: crtc_id=%d with size %d to %d\n",
3852                          __func__,
3853                          amdgpu_crtc->crtc_id,
3854                          plane->state->crtc_w,
3855                          plane->state->crtc_h);
3856
3857         ret = get_cursor_position(plane, crtc, &position);
3858         if (ret)
3859                 return;
3860
3861         if (!position.enable) {
3862                 /* turn off cursor */
3863                 if (crtc_state && crtc_state->stream)
3864                         dc_stream_set_cursor_position(crtc_state->stream,
3865                                                       &position);
3866                 return;
3867         }
3868
3869         amdgpu_crtc->cursor_width = plane->state->crtc_w;
3870         amdgpu_crtc->cursor_height = plane->state->crtc_h;
3871
3872         attributes.address.high_part = upper_32_bits(address);
3873         attributes.address.low_part  = lower_32_bits(address);
3874         attributes.width             = plane->state->crtc_w;
3875         attributes.height            = plane->state->crtc_h;
3876         attributes.color_format      = CURSOR_MODE_COLOR_PRE_MULTIPLIED_ALPHA;
3877         attributes.rotation_angle    = 0;
3878         attributes.attribute_flags.value = 0;
3879
3880         attributes.pitch = attributes.width;
3881
3882         if (crtc_state->stream) {
3883                 if (!dc_stream_set_cursor_attributes(crtc_state->stream,
3884                                                          &attributes))
3885                         DRM_ERROR("DC failed to set cursor attributes\n");
3886
3887                 if (!dc_stream_set_cursor_position(crtc_state->stream,
3888                                                    &position))
3889                         DRM_ERROR("DC failed to set cursor position\n");
3890         }
3891 }
3892
3893 static void prepare_flip_isr(struct amdgpu_crtc *acrtc)
3894 {
3895
3896         assert_spin_locked(&acrtc->base.dev->event_lock);
3897         WARN_ON(acrtc->event);
3898
3899         acrtc->event = acrtc->base.state->event;
3900
3901         /* Set the flip status */
3902         acrtc->pflip_status = AMDGPU_FLIP_SUBMITTED;
3903
3904         /* Mark this event as consumed */
3905         acrtc->base.state->event = NULL;
3906
3907         DRM_DEBUG_DRIVER("crtc:%d, pflip_stat:AMDGPU_FLIP_SUBMITTED\n",
3908                                                  acrtc->crtc_id);
3909 }
3910
3911 /*
3912  * Executes flip
3913  *
3914  * Waits on all BO's fences and for proper vblank count
3915  */
3916 static void amdgpu_dm_do_flip(struct drm_crtc *crtc,
3917                               struct drm_framebuffer *fb,
3918                               uint32_t target,
3919                               struct dc_state *state)
3920 {
3921         unsigned long flags;
3922         uint32_t target_vblank;
3923         int r, vpos, hpos;
3924         struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
3925         struct amdgpu_framebuffer *afb = to_amdgpu_framebuffer(fb);
3926         struct amdgpu_bo *abo = gem_to_amdgpu_bo(fb->obj[0]);
3927         struct amdgpu_device *adev = crtc->dev->dev_private;
3928         bool async_flip = (crtc->state->pageflip_flags & DRM_MODE_PAGE_FLIP_ASYNC) != 0;
3929         struct dc_flip_addrs addr = { {0} };
3930         /* TODO eliminate or rename surface_update */
3931         struct dc_surface_update surface_updates[1] = { {0} };
3932         struct dm_crtc_state *acrtc_state = to_dm_crtc_state(crtc->state);
3933
3934
3935         /* Prepare wait for target vblank early - before the fence-waits */
3936         target_vblank = target - (uint32_t)drm_crtc_vblank_count(crtc) +
3937                         amdgpu_get_vblank_counter_kms(crtc->dev, acrtc->crtc_id);
3938
3939         /* TODO This might fail and hence better not used, wait
3940          * explicitly on fences instead
3941          * and in general should be called for
3942          * blocking commit to as per framework helpers
3943          */
3944         r = amdgpu_bo_reserve(abo, true);
3945         if (unlikely(r != 0)) {
3946                 DRM_ERROR("failed to reserve buffer before flip\n");
3947                 WARN_ON(1);
3948         }
3949
3950         /* Wait for all fences on this FB */
3951         WARN_ON(reservation_object_wait_timeout_rcu(abo->tbo.resv, true, false,
3952                                                                     MAX_SCHEDULE_TIMEOUT) < 0);
3953
3954         amdgpu_bo_unreserve(abo);
3955
3956         /* Wait until we're out of the vertical blank period before the one
3957          * targeted by the flip
3958          */
3959         while ((acrtc->enabled &&
3960                 (amdgpu_display_get_crtc_scanoutpos(adev->ddev, acrtc->crtc_id,
3961                                                     0, &vpos, &hpos, NULL,
3962                                                     NULL, &crtc->hwmode)
3963                  & (DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_IN_VBLANK)) ==
3964                 (DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_IN_VBLANK) &&
3965                 (int)(target_vblank -
3966                   amdgpu_get_vblank_counter_kms(adev->ddev, acrtc->crtc_id)) > 0)) {
3967                 usleep_range(1000, 1100);
3968         }
3969
3970         /* Flip */
3971         spin_lock_irqsave(&crtc->dev->event_lock, flags);
3972
3973         WARN_ON(acrtc->pflip_status != AMDGPU_FLIP_NONE);
3974         WARN_ON(!acrtc_state->stream);
3975
3976         addr.address.grph.addr.low_part = lower_32_bits(afb->address);
3977         addr.address.grph.addr.high_part = upper_32_bits(afb->address);
3978         addr.flip_immediate = async_flip;
3979
3980
3981         if (acrtc->base.state->event)
3982                 prepare_flip_isr(acrtc);
3983
3984         spin_unlock_irqrestore(&crtc->dev->event_lock, flags);
3985
3986         surface_updates->surface = dc_stream_get_status(acrtc_state->stream)->plane_states[0];
3987         surface_updates->flip_addr = &addr;
3988
3989         dc_commit_updates_for_stream(adev->dm.dc,
3990                                              surface_updates,
3991                                              1,
3992                                              acrtc_state->stream,
3993                                              NULL,
3994                                              &surface_updates->surface,
3995                                              state);
3996
3997         DRM_DEBUG_DRIVER("%s Flipping to hi: 0x%x, low: 0x%x \n",
3998                          __func__,
3999                          addr.address.grph.addr.high_part,
4000                          addr.address.grph.addr.low_part);
4001 }
4002
4003 /*
4004  * TODO this whole function needs to go
4005  *
4006  * dc_surface_update is needlessly complex. See if we can just replace this
4007  * with a dc_plane_state and follow the atomic model a bit more closely here.
4008  */
4009 static bool commit_planes_to_stream(
4010                 struct dc *dc,
4011                 struct dc_plane_state **plane_states,
4012                 uint8_t new_plane_count,
4013                 struct dm_crtc_state *dm_new_crtc_state,
4014                 struct dm_crtc_state *dm_old_crtc_state,
4015                 struct dc_state *state)
4016 {
4017         /* no need to dynamically allocate this. it's pretty small */
4018         struct dc_surface_update updates[MAX_SURFACES];
4019         struct dc_flip_addrs *flip_addr;
4020         struct dc_plane_info *plane_info;
4021         struct dc_scaling_info *scaling_info;
4022         int i;
4023         struct dc_stream_state *dc_stream = dm_new_crtc_state->stream;
4024         struct dc_stream_update *stream_update =
4025                         kzalloc(sizeof(struct dc_stream_update), GFP_KERNEL);
4026
4027         if (!stream_update) {
4028                 BREAK_TO_DEBUGGER();
4029                 return false;
4030         }
4031
4032         flip_addr = kcalloc(MAX_SURFACES, sizeof(struct dc_flip_addrs),
4033                             GFP_KERNEL);
4034         plane_info = kcalloc(MAX_SURFACES, sizeof(struct dc_plane_info),
4035                              GFP_KERNEL);
4036         scaling_info = kcalloc(MAX_SURFACES, sizeof(struct dc_scaling_info),
4037                                GFP_KERNEL);
4038
4039         if (!flip_addr || !plane_info || !scaling_info) {
4040                 kfree(flip_addr);
4041                 kfree(plane_info);
4042                 kfree(scaling_info);
4043                 kfree(stream_update);
4044                 return false;
4045         }
4046
4047         memset(updates, 0, sizeof(updates));
4048
4049         stream_update->src = dc_stream->src;
4050         stream_update->dst = dc_stream->dst;
4051         stream_update->out_transfer_func = dc_stream->out_transfer_func;
4052
4053         for (i = 0; i < new_plane_count; i++) {
4054                 updates[i].surface = plane_states[i];
4055                 updates[i].gamma =
4056                         (struct dc_gamma *)plane_states[i]->gamma_correction;
4057                 updates[i].in_transfer_func = plane_states[i]->in_transfer_func;
4058                 flip_addr[i].address = plane_states[i]->address;
4059                 flip_addr[i].flip_immediate = plane_states[i]->flip_immediate;
4060                 plane_info[i].color_space = plane_states[i]->color_space;
4061                 plane_info[i].format = plane_states[i]->format;
4062                 plane_info[i].plane_size = plane_states[i]->plane_size;
4063                 plane_info[i].rotation = plane_states[i]->rotation;
4064                 plane_info[i].horizontal_mirror = plane_states[i]->horizontal_mirror;
4065                 plane_info[i].stereo_format = plane_states[i]->stereo_format;
4066                 plane_info[i].tiling_info = plane_states[i]->tiling_info;
4067                 plane_info[i].visible = plane_states[i]->visible;
4068                 plane_info[i].per_pixel_alpha = plane_states[i]->per_pixel_alpha;
4069                 plane_info[i].dcc = plane_states[i]->dcc;
4070                 scaling_info[i].scaling_quality = plane_states[i]->scaling_quality;
4071                 scaling_info[i].src_rect = plane_states[i]->src_rect;
4072                 scaling_info[i].dst_rect = plane_states[i]->dst_rect;
4073                 scaling_info[i].clip_rect = plane_states[i]->clip_rect;
4074
4075                 updates[i].flip_addr = &flip_addr[i];
4076                 updates[i].plane_info = &plane_info[i];
4077                 updates[i].scaling_info = &scaling_info[i];
4078         }
4079
4080         dc_commit_updates_for_stream(
4081                         dc,
4082                         updates,
4083                         new_plane_count,
4084                         dc_stream, stream_update, plane_states, state);
4085
4086         kfree(flip_addr);
4087         kfree(plane_info);
4088         kfree(scaling_info);
4089         kfree(stream_update);
4090         return true;
4091 }
4092
4093 static void amdgpu_dm_commit_planes(struct drm_atomic_state *state,
4094                                     struct drm_device *dev,
4095                                     struct amdgpu_display_manager *dm,
4096                                     struct drm_crtc *pcrtc,
4097                                     bool *wait_for_vblank)
4098 {
4099         uint32_t i;
4100         struct drm_plane *plane;
4101         struct drm_plane_state *old_plane_state, *new_plane_state;
4102         struct dc_stream_state *dc_stream_attach;
4103         struct dc_plane_state *plane_states_constructed[MAX_SURFACES];
4104         struct amdgpu_crtc *acrtc_attach = to_amdgpu_crtc(pcrtc);
4105         struct drm_crtc_state *new_pcrtc_state =
4106                         drm_atomic_get_new_crtc_state(state, pcrtc);
4107         struct dm_crtc_state *acrtc_state = to_dm_crtc_state(new_pcrtc_state);
4108         struct dm_crtc_state *dm_old_crtc_state =
4109                         to_dm_crtc_state(drm_atomic_get_old_crtc_state(state, pcrtc));
4110         struct dm_atomic_state *dm_state = to_dm_atomic_state(state);
4111         int planes_count = 0;
4112         unsigned long flags;
4113
4114         /* update planes when needed */
4115         for_each_oldnew_plane_in_state(state, plane, old_plane_state, new_plane_state, i) {
4116                 struct drm_crtc *crtc = new_plane_state->crtc;
4117                 struct drm_crtc_state *new_crtc_state;
4118                 struct drm_framebuffer *fb = new_plane_state->fb;
4119                 bool pflip_needed;
4120                 struct dm_plane_state *dm_new_plane_state = to_dm_plane_state(new_plane_state);
4121
4122                 if (plane->type == DRM_PLANE_TYPE_CURSOR) {
4123                         handle_cursor_update(plane, old_plane_state);
4124                         continue;
4125                 }
4126
4127                 if (!fb || !crtc || pcrtc != crtc)
4128                         continue;
4129
4130                 new_crtc_state = drm_atomic_get_new_crtc_state(state, crtc);
4131                 if (!new_crtc_state->active)
4132                         continue;
4133
4134                 pflip_needed = !state->allow_modeset;
4135
4136                 spin_lock_irqsave(&crtc->dev->event_lock, flags);
4137                 if (acrtc_attach->pflip_status != AMDGPU_FLIP_NONE) {
4138                         DRM_ERROR("%s: acrtc %d, already busy\n",
4139                                   __func__,
4140                                   acrtc_attach->crtc_id);
4141                         /* In commit tail framework this cannot happen */
4142                         WARN_ON(1);
4143                 }
4144                 spin_unlock_irqrestore(&crtc->dev->event_lock, flags);
4145
4146                 if (!pflip_needed || plane->type == DRM_PLANE_TYPE_OVERLAY) {
4147                         WARN_ON(!dm_new_plane_state->dc_state);
4148
4149                         plane_states_constructed[planes_count] = dm_new_plane_state->dc_state;
4150
4151                         dc_stream_attach = acrtc_state->stream;
4152                         planes_count++;
4153
4154                 } else if (new_crtc_state->planes_changed) {
4155                         /* Assume even ONE crtc with immediate flip means
4156                          * entire can't wait for VBLANK
4157                          * TODO Check if it's correct
4158                          */
4159                         *wait_for_vblank =
4160                                         new_pcrtc_state->pageflip_flags & DRM_MODE_PAGE_FLIP_ASYNC ?
4161                                 false : true;
4162
4163                         /* TODO: Needs rework for multiplane flip */
4164                         if (plane->type == DRM_PLANE_TYPE_PRIMARY)
4165                                 drm_crtc_vblank_get(crtc);
4166
4167                         amdgpu_dm_do_flip(
4168                                 crtc,
4169                                 fb,
4170                                 (uint32_t)drm_crtc_vblank_count(crtc) + *wait_for_vblank,
4171                                 dm_state->context);
4172                 }
4173
4174         }
4175
4176         if (planes_count) {
4177                 unsigned long flags;
4178
4179                 if (new_pcrtc_state->event) {
4180
4181                         drm_crtc_vblank_get(pcrtc);
4182
4183                         spin_lock_irqsave(&pcrtc->dev->event_lock, flags);
4184                         prepare_flip_isr(acrtc_attach);
4185                         spin_unlock_irqrestore(&pcrtc->dev->event_lock, flags);
4186                 }
4187
4188
4189                 if (false == commit_planes_to_stream(dm->dc,
4190                                                         plane_states_constructed,
4191                                                         planes_count,
4192                                                         acrtc_state,
4193                                                         dm_old_crtc_state,
4194                                                         dm_state->context))
4195                         dm_error("%s: Failed to attach plane!\n", __func__);
4196         } else {
4197                 /*TODO BUG Here should go disable planes on CRTC. */
4198         }
4199 }
4200
4201 /**
4202  * amdgpu_dm_crtc_copy_transient_flags - copy mirrored flags from DRM to DC
4203  * @crtc_state: the DRM CRTC state
4204  * @stream_state: the DC stream state.
4205  *
4206  * Copy the mirrored transient state flags from DRM, to DC. It is used to bring
4207  * a dc_stream_state's flags in sync with a drm_crtc_state's flags.
4208  */
4209 static void amdgpu_dm_crtc_copy_transient_flags(struct drm_crtc_state *crtc_state,
4210                                                 struct dc_stream_state *stream_state)
4211 {
4212         stream_state->mode_changed = crtc_state->mode_changed;
4213 }
4214
4215 static int amdgpu_dm_atomic_commit(struct drm_device *dev,
4216                                    struct drm_atomic_state *state,
4217                                    bool nonblock)
4218 {
4219         struct drm_crtc *crtc;
4220         struct drm_crtc_state *old_crtc_state, *new_crtc_state;
4221         struct amdgpu_device *adev = dev->dev_private;
4222         int i;
4223
4224         /*
4225          * We evade vblanks and pflips on crtc that
4226          * should be changed. We do it here to flush & disable
4227          * interrupts before drm_swap_state is called in drm_atomic_helper_commit
4228          * it will update crtc->dm_crtc_state->stream pointer which is used in
4229          * the ISRs.
4230          */
4231         for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
4232                 struct dm_crtc_state *dm_old_crtc_state = to_dm_crtc_state(old_crtc_state);
4233                 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
4234
4235                 if (drm_atomic_crtc_needs_modeset(new_crtc_state) && dm_old_crtc_state->stream)
4236                         manage_dm_interrupts(adev, acrtc, false);
4237         }
4238         /* Add check here for SoC's that support hardware cursor plane, to
4239          * unset legacy_cursor_update */
4240
4241         return drm_atomic_helper_commit(dev, state, nonblock);
4242
4243         /*TODO Handle EINTR, reenable IRQ*/
4244 }
4245
4246 static void amdgpu_dm_atomic_commit_tail(struct drm_atomic_state *state)
4247 {
4248         struct drm_device *dev = state->dev;
4249         struct amdgpu_device *adev = dev->dev_private;
4250         struct amdgpu_display_manager *dm = &adev->dm;
4251         struct dm_atomic_state *dm_state;
4252         uint32_t i, j;
4253         struct drm_crtc *crtc;
4254         struct drm_crtc_state *old_crtc_state, *new_crtc_state;
4255         unsigned long flags;
4256         bool wait_for_vblank = true;
4257         struct drm_connector *connector;
4258         struct drm_connector_state *old_con_state, *new_con_state;
4259         struct dm_crtc_state *dm_old_crtc_state, *dm_new_crtc_state;
4260         int crtc_disable_count = 0;
4261
4262         drm_atomic_helper_update_legacy_modeset_state(dev, state);
4263
4264         dm_state = to_dm_atomic_state(state);
4265
4266         /* update changed items */
4267         for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
4268                 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
4269
4270                 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
4271                 dm_old_crtc_state = to_dm_crtc_state(old_crtc_state);
4272
4273                 DRM_DEBUG_DRIVER(
4274                         "amdgpu_crtc id:%d crtc_state_flags: enable:%d, active:%d, "
4275                         "planes_changed:%d, mode_changed:%d,active_changed:%d,"
4276                         "connectors_changed:%d\n",
4277                         acrtc->crtc_id,
4278                         new_crtc_state->enable,
4279                         new_crtc_state->active,
4280                         new_crtc_state->planes_changed,
4281                         new_crtc_state->mode_changed,
4282                         new_crtc_state->active_changed,
4283                         new_crtc_state->connectors_changed);
4284
4285                 /* Copy all transient state flags into dc state */
4286                 if (dm_new_crtc_state->stream) {
4287                         amdgpu_dm_crtc_copy_transient_flags(&dm_new_crtc_state->base,
4288                                                             dm_new_crtc_state->stream);
4289                 }
4290
4291                 /* handles headless hotplug case, updating new_state and
4292                  * aconnector as needed
4293                  */
4294
4295                 if (modeset_required(new_crtc_state, dm_new_crtc_state->stream, dm_old_crtc_state->stream)) {
4296
4297                         DRM_DEBUG_DRIVER("Atomic commit: SET crtc id %d: [%p]\n", acrtc->crtc_id, acrtc);
4298
4299                         if (!dm_new_crtc_state->stream) {
4300                                 /*
4301                                  * this could happen because of issues with
4302                                  * userspace notifications delivery.
4303                                  * In this case userspace tries to set mode on
4304                                  * display which is disconnect in fact.
4305                                  * dc_sink in NULL in this case on aconnector.
4306                                  * We expect reset mode will come soon.
4307                                  *
4308                                  * This can also happen when unplug is done
4309                                  * during resume sequence ended
4310                                  *
4311                                  * In this case, we want to pretend we still
4312                                  * have a sink to keep the pipe running so that
4313                                  * hw state is consistent with the sw state
4314                                  */
4315                                 DRM_DEBUG_DRIVER("%s: Failed to create new stream for crtc %d\n",
4316                                                 __func__, acrtc->base.base.id);
4317                                 continue;
4318                         }
4319
4320                         if (dm_old_crtc_state->stream)
4321                                 remove_stream(adev, acrtc, dm_old_crtc_state->stream);
4322
4323                         pm_runtime_get_noresume(dev->dev);
4324
4325                         acrtc->enabled = true;
4326                         acrtc->hw_mode = new_crtc_state->mode;
4327                         crtc->hwmode = new_crtc_state->mode;
4328                 } else if (modereset_required(new_crtc_state)) {
4329                         DRM_DEBUG_DRIVER("Atomic commit: RESET. crtc id %d:[%p]\n", acrtc->crtc_id, acrtc);
4330
4331                         /* i.e. reset mode */
4332                         if (dm_old_crtc_state->stream)
4333                                 remove_stream(adev, acrtc, dm_old_crtc_state->stream);
4334                 }
4335         } /* for_each_crtc_in_state() */
4336
4337         /*
4338          * Add streams after required streams from new and replaced streams
4339          * are removed from freesync module
4340          */
4341         if (adev->dm.freesync_module) {
4342                 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state,
4343                                               new_crtc_state, i) {
4344                         struct amdgpu_dm_connector *aconnector = NULL;
4345                         struct dm_connector_state *dm_new_con_state = NULL;
4346                         struct amdgpu_crtc *acrtc = NULL;
4347                         bool modeset_needed;
4348
4349                         dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
4350                         dm_old_crtc_state = to_dm_crtc_state(old_crtc_state);
4351                         modeset_needed = modeset_required(
4352                                         new_crtc_state,
4353                                         dm_new_crtc_state->stream,
4354                                         dm_old_crtc_state->stream);
4355                         /* We add stream to freesync if:
4356                          * 1. Said stream is not null, and
4357                          * 2. A modeset is requested. This means that the
4358                          *    stream was removed previously, and needs to be
4359                          *    replaced.
4360                          */
4361                         if (dm_new_crtc_state->stream == NULL ||
4362                                         !modeset_needed)
4363                                 continue;
4364
4365                         acrtc = to_amdgpu_crtc(crtc);
4366
4367                         aconnector =
4368                                 amdgpu_dm_find_first_crtc_matching_connector(
4369                                         state, crtc);
4370                         if (!aconnector) {
4371                                 DRM_DEBUG_DRIVER("Atomic commit: Failed to "
4372                                                  "find connector for acrtc "
4373                                                  "id:%d skipping freesync "
4374                                                  "init\n",
4375                                                  acrtc->crtc_id);
4376                                 continue;
4377                         }
4378
4379                         mod_freesync_add_stream(adev->dm.freesync_module,
4380                                                 dm_new_crtc_state->stream,
4381                                                 &aconnector->caps);
4382                         new_con_state = drm_atomic_get_new_connector_state(
4383                                         state, &aconnector->base);
4384                         dm_new_con_state = to_dm_connector_state(new_con_state);
4385
4386                         mod_freesync_set_user_enable(adev->dm.freesync_module,
4387                                                      &dm_new_crtc_state->stream,
4388                                                      1,
4389                                                      &dm_new_con_state->user_enable);
4390                 }
4391         }
4392
4393         if (dm_state->context) {
4394                 dm_enable_per_frame_crtc_master_sync(dm_state->context);
4395                 WARN_ON(!dc_commit_state(dm->dc, dm_state->context));
4396         }
4397
4398         for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) {
4399                 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
4400
4401                 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
4402
4403                 if (dm_new_crtc_state->stream != NULL) {
4404                         const struct dc_stream_status *status =
4405                                         dc_stream_get_status(dm_new_crtc_state->stream);
4406
4407                         if (!status)
4408                                 DC_ERR("got no status for stream %p on acrtc%p\n", dm_new_crtc_state->stream, acrtc);
4409                         else
4410                                 acrtc->otg_inst = status->primary_otg_inst;
4411                 }
4412         }
4413
4414         /* Handle scaling and underscan changes*/
4415         for_each_oldnew_connector_in_state(state, connector, old_con_state, new_con_state, i) {
4416                 struct dm_connector_state *dm_new_con_state = to_dm_connector_state(new_con_state);
4417                 struct dm_connector_state *dm_old_con_state = to_dm_connector_state(old_con_state);
4418                 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(dm_new_con_state->base.crtc);
4419                 struct dc_stream_status *status = NULL;
4420
4421                 if (acrtc) {
4422                         new_crtc_state = drm_atomic_get_new_crtc_state(state, &acrtc->base);
4423                         old_crtc_state = drm_atomic_get_old_crtc_state(state, &acrtc->base);
4424                 }
4425
4426                 /* Skip any modesets/resets */
4427                 if (!acrtc || drm_atomic_crtc_needs_modeset(new_crtc_state))
4428                         continue;
4429
4430                 /* Skip any thing not scale or underscan changes */
4431                 if (!is_scaling_state_different(dm_new_con_state, dm_old_con_state))
4432                         continue;
4433
4434                 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
4435
4436                 update_stream_scaling_settings(&dm_new_con_state->base.crtc->mode,
4437                                 dm_new_con_state, (struct dc_stream_state *)dm_new_crtc_state->stream);
4438
4439                 if (!dm_new_crtc_state->stream)
4440                         continue;
4441
4442                 status = dc_stream_get_status(dm_new_crtc_state->stream);
4443                 WARN_ON(!status);
4444                 WARN_ON(!status->plane_count);
4445
4446                 /*TODO How it works with MPO ?*/
4447                 if (!commit_planes_to_stream(
4448                                 dm->dc,
4449                                 status->plane_states,
4450                                 status->plane_count,
4451                                 dm_new_crtc_state,
4452                                 to_dm_crtc_state(old_crtc_state),
4453                                 dm_state->context))
4454                         dm_error("%s: Failed to update stream scaling!\n", __func__);
4455         }
4456
4457         for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state,
4458                         new_crtc_state, i) {
4459                 /*
4460                  * loop to enable interrupts on newly arrived crtc
4461                  */
4462                 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
4463                 bool modeset_needed;
4464
4465                 if (old_crtc_state->active && !new_crtc_state->active)
4466                         crtc_disable_count++;
4467
4468                 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
4469                 dm_old_crtc_state = to_dm_crtc_state(old_crtc_state);
4470                 modeset_needed = modeset_required(
4471                                 new_crtc_state,
4472                                 dm_new_crtc_state->stream,
4473                                 dm_old_crtc_state->stream);
4474
4475                 if (dm_new_crtc_state->stream == NULL || !modeset_needed)
4476                         continue;
4477
4478                 if (adev->dm.freesync_module)
4479                         mod_freesync_notify_mode_change(
4480                                 adev->dm.freesync_module,
4481                                 &dm_new_crtc_state->stream, 1);
4482
4483                 manage_dm_interrupts(adev, acrtc, true);
4484         }
4485
4486         /* update planes when needed per crtc*/
4487         for_each_new_crtc_in_state(state, crtc, new_crtc_state, j) {
4488                 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
4489
4490                 if (dm_new_crtc_state->stream)
4491                         amdgpu_dm_commit_planes(state, dev, dm, crtc, &wait_for_vblank);
4492         }
4493
4494
4495         /*
4496          * send vblank event on all events not handled in flip and
4497          * mark consumed event for drm_atomic_helper_commit_hw_done
4498          */
4499         spin_lock_irqsave(&adev->ddev->event_lock, flags);
4500         for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) {
4501
4502                 if (new_crtc_state->event)
4503                         drm_send_event_locked(dev, &new_crtc_state->event->base);
4504
4505                 new_crtc_state->event = NULL;
4506         }
4507         spin_unlock_irqrestore(&adev->ddev->event_lock, flags);
4508
4509         /* Signal HW programming completion */
4510         drm_atomic_helper_commit_hw_done(state);
4511
4512         if (wait_for_vblank)
4513                 drm_atomic_helper_wait_for_flip_done(dev, state);
4514
4515         drm_atomic_helper_cleanup_planes(dev, state);
4516
4517         /* Finally, drop a runtime PM reference for each newly disabled CRTC,
4518          * so we can put the GPU into runtime suspend if we're not driving any
4519          * displays anymore
4520          */
4521         for (i = 0; i < crtc_disable_count; i++)
4522                 pm_runtime_put_autosuspend(dev->dev);
4523         pm_runtime_mark_last_busy(dev->dev);
4524 }
4525
4526
4527 static int dm_force_atomic_commit(struct drm_connector *connector)
4528 {
4529         int ret = 0;
4530         struct drm_device *ddev = connector->dev;
4531         struct drm_atomic_state *state = drm_atomic_state_alloc(ddev);
4532         struct amdgpu_crtc *disconnected_acrtc = to_amdgpu_crtc(connector->encoder->crtc);
4533         struct drm_plane *plane = disconnected_acrtc->base.primary;
4534         struct drm_connector_state *conn_state;
4535         struct drm_crtc_state *crtc_state;
4536         struct drm_plane_state *plane_state;
4537
4538         if (!state)
4539                 return -ENOMEM;
4540
4541         state->acquire_ctx = ddev->mode_config.acquire_ctx;
4542
4543         /* Construct an atomic state to restore previous display setting */
4544
4545         /*
4546          * Attach connectors to drm_atomic_state
4547          */
4548         conn_state = drm_atomic_get_connector_state(state, connector);
4549
4550         ret = PTR_ERR_OR_ZERO(conn_state);
4551         if (ret)
4552                 goto err;
4553
4554         /* Attach crtc to drm_atomic_state*/
4555         crtc_state = drm_atomic_get_crtc_state(state, &disconnected_acrtc->base);
4556
4557         ret = PTR_ERR_OR_ZERO(crtc_state);
4558         if (ret)
4559                 goto err;
4560
4561         /* force a restore */
4562         crtc_state->mode_changed = true;
4563
4564         /* Attach plane to drm_atomic_state */
4565         plane_state = drm_atomic_get_plane_state(state, plane);
4566
4567         ret = PTR_ERR_OR_ZERO(plane_state);
4568         if (ret)
4569                 goto err;
4570
4571
4572         /* Call commit internally with the state we just constructed */
4573         ret = drm_atomic_commit(state);
4574         if (!ret)
4575                 return 0;
4576
4577 err:
4578         DRM_ERROR("Restoring old state failed with %i\n", ret);
4579         drm_atomic_state_put(state);
4580
4581         return ret;
4582 }
4583
4584 /*
4585  * This functions handle all cases when set mode does not come upon hotplug.
4586  * This include when the same display is unplugged then plugged back into the
4587  * same port and when we are running without usermode desktop manager supprot
4588  */
4589 void dm_restore_drm_connector_state(struct drm_device *dev,
4590                                     struct drm_connector *connector)
4591 {
4592         struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
4593         struct amdgpu_crtc *disconnected_acrtc;
4594         struct dm_crtc_state *acrtc_state;
4595
4596         if (!aconnector->dc_sink || !connector->state || !connector->encoder)
4597                 return;
4598
4599         disconnected_acrtc = to_amdgpu_crtc(connector->encoder->crtc);
4600         if (!disconnected_acrtc)
4601                 return;
4602
4603         acrtc_state = to_dm_crtc_state(disconnected_acrtc->base.state);
4604         if (!acrtc_state->stream)
4605                 return;
4606
4607         /*
4608          * If the previous sink is not released and different from the current,
4609          * we deduce we are in a state where we can not rely on usermode call
4610          * to turn on the display, so we do it here
4611          */
4612         if (acrtc_state->stream->sink != aconnector->dc_sink)
4613                 dm_force_atomic_commit(&aconnector->base);
4614 }
4615
4616 /*`
4617  * Grabs all modesetting locks to serialize against any blocking commits,
4618  * Waits for completion of all non blocking commits.
4619  */
4620 static int do_aquire_global_lock(struct drm_device *dev,
4621                                  struct drm_atomic_state *state)
4622 {
4623         struct drm_crtc *crtc;
4624         struct drm_crtc_commit *commit;
4625         long ret;
4626
4627         /* Adding all modeset locks to aquire_ctx will
4628          * ensure that when the framework release it the
4629          * extra locks we are locking here will get released to
4630          */
4631         ret = drm_modeset_lock_all_ctx(dev, state->acquire_ctx);
4632         if (ret)
4633                 return ret;
4634
4635         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
4636                 spin_lock(&crtc->commit_lock);
4637                 commit = list_first_entry_or_null(&crtc->commit_list,
4638                                 struct drm_crtc_commit, commit_entry);
4639                 if (commit)
4640                         drm_crtc_commit_get(commit);
4641                 spin_unlock(&crtc->commit_lock);
4642
4643                 if (!commit)
4644                         continue;
4645
4646                 /* Make sure all pending HW programming completed and
4647                  * page flips done
4648                  */
4649                 ret = wait_for_completion_interruptible_timeout(&commit->hw_done, 10*HZ);
4650
4651                 if (ret > 0)
4652                         ret = wait_for_completion_interruptible_timeout(
4653                                         &commit->flip_done, 10*HZ);
4654
4655                 if (ret == 0)
4656                         DRM_ERROR("[CRTC:%d:%s] hw_done or flip_done "
4657                                   "timed out\n", crtc->base.id, crtc->name);
4658
4659                 drm_crtc_commit_put(commit);
4660         }
4661
4662         return ret < 0 ? ret : 0;
4663 }
4664
4665 static int dm_update_crtcs_state(struct dc *dc,
4666                                  struct drm_atomic_state *state,
4667                                  bool enable,
4668                                  bool *lock_and_validation_needed)
4669 {
4670         struct drm_crtc *crtc;
4671         struct drm_crtc_state *old_crtc_state, *new_crtc_state;
4672         int i;
4673         struct dm_crtc_state *dm_old_crtc_state, *dm_new_crtc_state;
4674         struct dm_atomic_state *dm_state = to_dm_atomic_state(state);
4675         struct dc_stream_state *new_stream;
4676         int ret = 0;
4677
4678         /*TODO Move this code into dm_crtc_atomic_check once we get rid of dc_validation_set */
4679         /* update changed items */
4680         for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
4681                 struct amdgpu_crtc *acrtc = NULL;
4682                 struct amdgpu_dm_connector *aconnector = NULL;
4683                 struct drm_connector_state *drm_new_conn_state = NULL, *drm_old_conn_state = NULL;
4684                 struct dm_connector_state *dm_new_conn_state = NULL, *dm_old_conn_state = NULL;
4685                 struct drm_plane_state *new_plane_state = NULL;
4686
4687                 new_stream = NULL;
4688
4689                 dm_old_crtc_state = to_dm_crtc_state(old_crtc_state);
4690                 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
4691                 acrtc = to_amdgpu_crtc(crtc);
4692
4693                 new_plane_state = drm_atomic_get_new_plane_state(state, new_crtc_state->crtc->primary);
4694
4695                 if (new_crtc_state->enable && new_plane_state && !new_plane_state->fb) {
4696                         ret = -EINVAL;
4697                         goto fail;
4698                 }
4699
4700                 aconnector = amdgpu_dm_find_first_crtc_matching_connector(state, crtc);
4701
4702                 /* TODO This hack should go away */
4703                 if (aconnector && enable) {
4704                         // Make sure fake sink is created in plug-in scenario
4705                         drm_new_conn_state = drm_atomic_get_new_connector_state(state,
4706                                                                     &aconnector->base);
4707                         drm_old_conn_state = drm_atomic_get_old_connector_state(state,
4708                                                                     &aconnector->base);
4709
4710                         if (IS_ERR(drm_new_conn_state)) {
4711                                 ret = PTR_ERR_OR_ZERO(drm_new_conn_state);
4712                                 break;
4713                         }
4714
4715                         dm_new_conn_state = to_dm_connector_state(drm_new_conn_state);
4716                         dm_old_conn_state = to_dm_connector_state(drm_old_conn_state);
4717
4718                         new_stream = create_stream_for_sink(aconnector,
4719                                                              &new_crtc_state->mode,
4720                                                             dm_new_conn_state);
4721
4722                         /*
4723                          * we can have no stream on ACTION_SET if a display
4724                          * was disconnected during S3, in this case it not and
4725                          * error, the OS will be updated after detection, and
4726                          * do the right thing on next atomic commit
4727                          */
4728
4729                         if (!new_stream) {
4730                                 DRM_DEBUG_DRIVER("%s: Failed to create new stream for crtc %d\n",
4731                                                 __func__, acrtc->base.base.id);
4732                                 break;
4733                         }
4734
4735                         if (dc_is_stream_unchanged(new_stream, dm_old_crtc_state->stream) &&
4736                             dc_is_stream_scaling_unchanged(new_stream, dm_old_crtc_state->stream)) {
4737                                 new_crtc_state->mode_changed = false;
4738                                 DRM_DEBUG_DRIVER("Mode change not required, setting mode_changed to %d",
4739                                                  new_crtc_state->mode_changed);
4740                         }
4741                 }
4742
4743                 if (!drm_atomic_crtc_needs_modeset(new_crtc_state))
4744                         goto next_crtc;
4745
4746                 DRM_DEBUG_DRIVER(
4747                         "amdgpu_crtc id:%d crtc_state_flags: enable:%d, active:%d, "
4748                         "planes_changed:%d, mode_changed:%d,active_changed:%d,"
4749                         "connectors_changed:%d\n",
4750                         acrtc->crtc_id,
4751                         new_crtc_state->enable,
4752                         new_crtc_state->active,
4753                         new_crtc_state->planes_changed,
4754                         new_crtc_state->mode_changed,
4755                         new_crtc_state->active_changed,
4756                         new_crtc_state->connectors_changed);
4757
4758                 /* Remove stream for any changed/disabled CRTC */
4759                 if (!enable) {
4760
4761                         if (!dm_old_crtc_state->stream)
4762                                 goto next_crtc;
4763
4764                         DRM_DEBUG_DRIVER("Disabling DRM crtc: %d\n",
4765                                         crtc->base.id);
4766
4767                         /* i.e. reset mode */
4768                         if (dc_remove_stream_from_ctx(
4769                                         dc,
4770                                         dm_state->context,
4771                                         dm_old_crtc_state->stream) != DC_OK) {
4772                                 ret = -EINVAL;
4773                                 goto fail;
4774                         }
4775
4776                         dc_stream_release(dm_old_crtc_state->stream);
4777                         dm_new_crtc_state->stream = NULL;
4778
4779                         *lock_and_validation_needed = true;
4780
4781                 } else {/* Add stream for any updated/enabled CRTC */
4782                         /*
4783                          * Quick fix to prevent NULL pointer on new_stream when
4784                          * added MST connectors not found in existing crtc_state in the chained mode
4785                          * TODO: need to dig out the root cause of that
4786                          */
4787                         if (!aconnector || (!aconnector->dc_sink && aconnector->mst_port))
4788                                 goto next_crtc;
4789
4790                         if (modereset_required(new_crtc_state))
4791                                 goto next_crtc;
4792
4793                         if (modeset_required(new_crtc_state, new_stream,
4794                                              dm_old_crtc_state->stream)) {
4795
4796                                 WARN_ON(dm_new_crtc_state->stream);
4797
4798                                 dm_new_crtc_state->stream = new_stream;
4799
4800                                 dc_stream_retain(new_stream);
4801
4802                                 DRM_DEBUG_DRIVER("Enabling DRM crtc: %d\n",
4803                                                         crtc->base.id);
4804
4805                                 if (dc_add_stream_to_ctx(
4806                                                 dc,
4807                                                 dm_state->context,
4808                                                 dm_new_crtc_state->stream) != DC_OK) {
4809                                         ret = -EINVAL;
4810                                         goto fail;
4811                                 }
4812
4813                                 *lock_and_validation_needed = true;
4814                         }
4815                 }
4816
4817 next_crtc:
4818                 /* Release extra reference */
4819                 if (new_stream)
4820                          dc_stream_release(new_stream);
4821
4822                 /*
4823                  * We want to do dc stream updates that do not require a
4824                  * full modeset below.
4825                  */
4826                 if (!(enable && aconnector && new_crtc_state->enable &&
4827                       new_crtc_state->active))
4828                         continue;
4829                 /*
4830                  * Given above conditions, the dc state cannot be NULL because:
4831                  * 1. We're in the process of enabling CRTCs (just been added
4832                  *    to the dc context, or already is on the context)
4833                  * 2. Has a valid connector attached, and
4834                  * 3. Is currently active and enabled.
4835                  * => The dc stream state currently exists.
4836                  */
4837                 BUG_ON(dm_new_crtc_state->stream == NULL);
4838
4839                 /* Scaling or underscan settings */
4840                 if (is_scaling_state_different(dm_old_conn_state, dm_new_conn_state))
4841                         update_stream_scaling_settings(
4842                                 &new_crtc_state->mode, dm_new_conn_state, dm_new_crtc_state->stream);
4843
4844                 /*
4845                  * Color management settings. We also update color properties
4846                  * when a modeset is needed, to ensure it gets reprogrammed.
4847                  */
4848                 if (dm_new_crtc_state->base.color_mgmt_changed ||
4849                     drm_atomic_crtc_needs_modeset(new_crtc_state)) {
4850                         ret = amdgpu_dm_set_regamma_lut(dm_new_crtc_state);
4851                         if (ret)
4852                                 goto fail;
4853                         amdgpu_dm_set_ctm(dm_new_crtc_state);
4854                 }
4855         }
4856
4857         return ret;
4858
4859 fail:
4860         if (new_stream)
4861                 dc_stream_release(new_stream);
4862         return ret;
4863 }
4864
4865 static int dm_update_planes_state(struct dc *dc,
4866                                   struct drm_atomic_state *state,
4867                                   bool enable,
4868                                   bool *lock_and_validation_needed)
4869 {
4870         struct drm_crtc *new_plane_crtc, *old_plane_crtc;
4871         struct drm_crtc_state *old_crtc_state, *new_crtc_state;
4872         struct drm_plane *plane;
4873         struct drm_plane_state *old_plane_state, *new_plane_state;
4874         struct dm_crtc_state *dm_new_crtc_state, *dm_old_crtc_state;
4875         struct dm_atomic_state *dm_state = to_dm_atomic_state(state);
4876         struct dm_plane_state *dm_new_plane_state, *dm_old_plane_state;
4877         int i ;
4878         /* TODO return page_flip_needed() function */
4879         bool pflip_needed  = !state->allow_modeset;
4880         int ret = 0;
4881
4882
4883         /* Add new planes, in reverse order as DC expectation */
4884         for_each_oldnew_plane_in_state_reverse(state, plane, old_plane_state, new_plane_state, i) {
4885                 new_plane_crtc = new_plane_state->crtc;
4886                 old_plane_crtc = old_plane_state->crtc;
4887                 dm_new_plane_state = to_dm_plane_state(new_plane_state);
4888                 dm_old_plane_state = to_dm_plane_state(old_plane_state);
4889
4890                 /*TODO Implement atomic check for cursor plane */
4891                 if (plane->type == DRM_PLANE_TYPE_CURSOR)
4892                         continue;
4893
4894                 /* Remove any changed/removed planes */
4895                 if (!enable) {
4896                         if (pflip_needed &&
4897                             plane->type != DRM_PLANE_TYPE_OVERLAY)
4898                                 continue;
4899
4900                         if (!old_plane_crtc)
4901                                 continue;
4902
4903                         old_crtc_state = drm_atomic_get_old_crtc_state(
4904                                         state, old_plane_crtc);
4905                         dm_old_crtc_state = to_dm_crtc_state(old_crtc_state);
4906
4907                         if (!dm_old_crtc_state->stream)
4908                                 continue;
4909
4910                         DRM_DEBUG_ATOMIC("Disabling DRM plane: %d on DRM crtc %d\n",
4911                                         plane->base.id, old_plane_crtc->base.id);
4912
4913                         if (!dc_remove_plane_from_context(
4914                                         dc,
4915                                         dm_old_crtc_state->stream,
4916                                         dm_old_plane_state->dc_state,
4917                                         dm_state->context)) {
4918
4919                                 ret = EINVAL;
4920                                 return ret;
4921                         }
4922
4923
4924                         dc_plane_state_release(dm_old_plane_state->dc_state);
4925                         dm_new_plane_state->dc_state = NULL;
4926
4927                         *lock_and_validation_needed = true;
4928
4929                 } else { /* Add new planes */
4930                         struct dc_plane_state *dc_new_plane_state;
4931
4932                         if (drm_atomic_plane_disabling(plane->state, new_plane_state))
4933                                 continue;
4934
4935                         if (!new_plane_crtc)
4936                                 continue;
4937
4938                         new_crtc_state = drm_atomic_get_new_crtc_state(state, new_plane_crtc);
4939                         dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
4940
4941                         if (!dm_new_crtc_state->stream)
4942                                 continue;
4943
4944                         if (pflip_needed &&
4945                             plane->type != DRM_PLANE_TYPE_OVERLAY)
4946                                 continue;
4947
4948                         WARN_ON(dm_new_plane_state->dc_state);
4949
4950                         dc_new_plane_state = dc_create_plane_state(dc);
4951                         if (!dc_new_plane_state)
4952                                 return -ENOMEM;
4953
4954                         DRM_DEBUG_DRIVER("Enabling DRM plane: %d on DRM crtc %d\n",
4955                                         plane->base.id, new_plane_crtc->base.id);
4956
4957                         ret = fill_plane_attributes(
4958                                 new_plane_crtc->dev->dev_private,
4959                                 dc_new_plane_state,
4960                                 new_plane_state,
4961                                 new_crtc_state);
4962                         if (ret) {
4963                                 dc_plane_state_release(dc_new_plane_state);
4964                                 return ret;
4965                         }
4966
4967                         /*
4968                          * Any atomic check errors that occur after this will
4969                          * not need a release. The plane state will be attached
4970                          * to the stream, and therefore part of the atomic
4971                          * state. It'll be released when the atomic state is
4972                          * cleaned.
4973                          */
4974                         if (!dc_add_plane_to_context(
4975                                         dc,
4976                                         dm_new_crtc_state->stream,
4977                                         dc_new_plane_state,
4978                                         dm_state->context)) {
4979
4980                                 dc_plane_state_release(dc_new_plane_state);
4981                                 return -EINVAL;
4982                         }
4983
4984                         dm_new_plane_state->dc_state = dc_new_plane_state;
4985
4986                         /* Tell DC to do a full surface update every time there
4987                          * is a plane change. Inefficient, but works for now.
4988                          */
4989                         dm_new_plane_state->dc_state->update_flags.bits.full_update = 1;
4990
4991                         *lock_and_validation_needed = true;
4992                 }
4993         }
4994
4995
4996         return ret;
4997 }
4998
4999 static int amdgpu_dm_atomic_check(struct drm_device *dev,
5000                                   struct drm_atomic_state *state)
5001 {
5002         struct amdgpu_device *adev = dev->dev_private;
5003         struct dc *dc = adev->dm.dc;
5004         struct dm_atomic_state *dm_state = to_dm_atomic_state(state);
5005         struct drm_connector *connector;
5006         struct drm_connector_state *old_con_state, *new_con_state;
5007         struct drm_crtc *crtc;
5008         struct drm_crtc_state *old_crtc_state, *new_crtc_state;
5009         int ret, i;
5010
5011         /*
5012          * This bool will be set for true for any modeset/reset
5013          * or plane update which implies non fast surface update.
5014          */
5015         bool lock_and_validation_needed = false;
5016
5017         ret = drm_atomic_helper_check_modeset(dev, state);
5018         if (ret)
5019                 goto fail;
5020
5021         for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
5022                 if (!drm_atomic_crtc_needs_modeset(new_crtc_state) &&
5023                     !new_crtc_state->color_mgmt_changed)
5024                         continue;
5025
5026                 if (!new_crtc_state->enable)
5027                         continue;
5028
5029                 ret = drm_atomic_add_affected_connectors(state, crtc);
5030                 if (ret)
5031                         return ret;
5032
5033                 ret = drm_atomic_add_affected_planes(state, crtc);
5034                 if (ret)
5035                         goto fail;
5036         }
5037
5038         dm_state->context = dc_create_state();
5039         ASSERT(dm_state->context);
5040         dc_resource_state_copy_construct_current(dc, dm_state->context);
5041
5042         /* Remove exiting planes if they are modified */
5043         ret = dm_update_planes_state(dc, state, false, &lock_and_validation_needed);
5044         if (ret) {
5045                 goto fail;
5046         }
5047
5048         /* Disable all crtcs which require disable */
5049         ret = dm_update_crtcs_state(dc, state, false, &lock_and_validation_needed);
5050         if (ret) {
5051                 goto fail;
5052         }
5053
5054         /* Enable all crtcs which require enable */
5055         ret = dm_update_crtcs_state(dc, state, true, &lock_and_validation_needed);
5056         if (ret) {
5057                 goto fail;
5058         }
5059
5060         /* Add new/modified planes */
5061         ret = dm_update_planes_state(dc, state, true, &lock_and_validation_needed);
5062         if (ret) {
5063                 goto fail;
5064         }
5065
5066         /* Run this here since we want to validate the streams we created */
5067         ret = drm_atomic_helper_check_planes(dev, state);
5068         if (ret)
5069                 goto fail;
5070
5071         /* Check scaling and underscan changes*/
5072         /*TODO Removed scaling changes validation due to inability to commit
5073          * new stream into context w\o causing full reset. Need to
5074          * decide how to handle.
5075          */
5076         for_each_oldnew_connector_in_state(state, connector, old_con_state, new_con_state, i) {
5077                 struct dm_connector_state *dm_old_con_state = to_dm_connector_state(old_con_state);
5078                 struct dm_connector_state *dm_new_con_state = to_dm_connector_state(new_con_state);
5079                 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(dm_new_con_state->base.crtc);
5080
5081                 /* Skip any modesets/resets */
5082                 if (!acrtc || drm_atomic_crtc_needs_modeset(
5083                                 drm_atomic_get_new_crtc_state(state, &acrtc->base)))
5084                         continue;
5085
5086                 /* Skip any thing not scale or underscan changes */
5087                 if (!is_scaling_state_different(dm_new_con_state, dm_old_con_state))
5088                         continue;
5089
5090                 lock_and_validation_needed = true;
5091         }
5092
5093         /*
5094          * For full updates case when
5095          * removing/adding/updating  streams on once CRTC while flipping
5096          * on another CRTC,
5097          * acquiring global lock  will guarantee that any such full
5098          * update commit
5099          * will wait for completion of any outstanding flip using DRMs
5100          * synchronization events.
5101          */
5102
5103         if (lock_and_validation_needed) {
5104
5105                 ret = do_aquire_global_lock(dev, state);
5106                 if (ret)
5107                         goto fail;
5108
5109                 if (dc_validate_global_state(dc, dm_state->context) != DC_OK) {
5110                         ret = -EINVAL;
5111                         goto fail;
5112                 }
5113         }
5114
5115         /* Must be success */
5116         WARN_ON(ret);
5117         return ret;
5118
5119 fail:
5120         if (ret == -EDEADLK)
5121                 DRM_DEBUG_DRIVER("Atomic check stopped to avoid deadlock.\n");
5122         else if (ret == -EINTR || ret == -EAGAIN || ret == -ERESTARTSYS)
5123                 DRM_DEBUG_DRIVER("Atomic check stopped due to signal.\n");
5124         else
5125                 DRM_DEBUG_DRIVER("Atomic check failed with err: %d \n", ret);
5126
5127         return ret;
5128 }
5129
5130 static bool is_dp_capable_without_timing_msa(struct dc *dc,
5131                                              struct amdgpu_dm_connector *amdgpu_dm_connector)
5132 {
5133         uint8_t dpcd_data;
5134         bool capable = false;
5135
5136         if (amdgpu_dm_connector->dc_link &&
5137                 dm_helpers_dp_read_dpcd(
5138                                 NULL,
5139                                 amdgpu_dm_connector->dc_link,
5140                                 DP_DOWN_STREAM_PORT_COUNT,
5141                                 &dpcd_data,
5142                                 sizeof(dpcd_data))) {
5143                 capable = (dpcd_data & DP_MSA_TIMING_PAR_IGNORED) ? true:false;
5144         }
5145
5146         return capable;
5147 }
5148 void amdgpu_dm_add_sink_to_freesync_module(struct drm_connector *connector,
5149                                            struct edid *edid)
5150 {
5151         int i;
5152         bool edid_check_required;
5153         struct detailed_timing *timing;
5154         struct detailed_non_pixel *data;
5155         struct detailed_data_monitor_range *range;
5156         struct amdgpu_dm_connector *amdgpu_dm_connector =
5157                         to_amdgpu_dm_connector(connector);
5158         struct dm_connector_state *dm_con_state;
5159
5160         struct drm_device *dev = connector->dev;
5161         struct amdgpu_device *adev = dev->dev_private;
5162
5163         if (!connector->state) {
5164                 DRM_ERROR("%s - Connector has no state", __func__);
5165                 return;
5166         }
5167
5168         dm_con_state = to_dm_connector_state(connector->state);
5169
5170         edid_check_required = false;
5171         if (!amdgpu_dm_connector->dc_sink) {
5172                 DRM_ERROR("dc_sink NULL, could not add free_sync module.\n");
5173                 return;
5174         }
5175         if (!adev->dm.freesync_module)
5176                 return;
5177         /*
5178          * if edid non zero restrict freesync only for dp and edp
5179          */
5180         if (edid) {
5181                 if (amdgpu_dm_connector->dc_sink->sink_signal == SIGNAL_TYPE_DISPLAY_PORT
5182                         || amdgpu_dm_connector->dc_sink->sink_signal == SIGNAL_TYPE_EDP) {
5183                         edid_check_required = is_dp_capable_without_timing_msa(
5184                                                 adev->dm.dc,
5185                                                 amdgpu_dm_connector);
5186                 }
5187         }
5188         dm_con_state->freesync_capable = false;
5189         if (edid_check_required == true && (edid->version > 1 ||
5190            (edid->version == 1 && edid->revision > 1))) {
5191                 for (i = 0; i < 4; i++) {
5192
5193                         timing  = &edid->detailed_timings[i];
5194                         data    = &timing->data.other_data;
5195                         range   = &data->data.range;
5196                         /*
5197                          * Check if monitor has continuous frequency mode
5198                          */
5199                         if (data->type != EDID_DETAIL_MONITOR_RANGE)
5200                                 continue;
5201                         /*
5202                          * Check for flag range limits only. If flag == 1 then
5203                          * no additional timing information provided.
5204                          * Default GTF, GTF Secondary curve and CVT are not
5205                          * supported
5206                          */
5207                         if (range->flags != 1)
5208                                 continue;
5209
5210                         amdgpu_dm_connector->min_vfreq = range->min_vfreq;
5211                         amdgpu_dm_connector->max_vfreq = range->max_vfreq;
5212                         amdgpu_dm_connector->pixel_clock_mhz =
5213                                 range->pixel_clock_mhz * 10;
5214                         break;
5215                 }
5216
5217                 if (amdgpu_dm_connector->max_vfreq -
5218                                 amdgpu_dm_connector->min_vfreq > 10) {
5219                         amdgpu_dm_connector->caps.supported = true;
5220                         amdgpu_dm_connector->caps.min_refresh_in_micro_hz =
5221                                         amdgpu_dm_connector->min_vfreq * 1000000;
5222                         amdgpu_dm_connector->caps.max_refresh_in_micro_hz =
5223                                         amdgpu_dm_connector->max_vfreq * 1000000;
5224                         dm_con_state->freesync_capable = true;
5225                 }
5226         }
5227
5228         /*
5229          * TODO figure out how to notify user-mode or DRM of freesync caps
5230          * once we figure out how to deal with freesync in an upstreamable
5231          * fashion
5232          */
5233
5234 }
5235
5236 void amdgpu_dm_remove_sink_from_freesync_module(struct drm_connector *connector)
5237 {
5238         /*
5239          * TODO fill in once we figure out how to deal with freesync in
5240          * an upstreamable fashion
5241          */
5242 }