2 * Copyright 2015 Advanced Micro Devices, Inc.
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9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
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26 #ifndef __AMDGPU_DM_H__
27 #define __AMDGPU_DM_H__
29 #include <drm/drm_atomic.h>
30 #include <drm/drm_connector.h>
31 #include <drm/drm_crtc.h>
32 #include <drm/drm_dp_mst_helper.h>
33 #include <drm/drm_plane.h>
36 * This file contains the definition for amdgpu_display_manager
37 * and its API for amdgpu driver's use.
38 * This component provides all the display related functionality
39 * and this is the only component that calls DAL API.
40 * The API contained here intended for amdgpu driver use.
41 * The API that is called directly from KMS framework is located
42 * in amdgpu_dm_kms.h file
45 #define AMDGPU_DM_MAX_DISPLAY_INDEX 31
47 #include "include/amdgpu_dal_power_if.h"
48 #include "amdgpu_dm_irq.h"
51 #include "irq_types.h"
52 #include "signal_types.h"
54 /* Forward declarations */
57 struct amdgpu_dm_irq_handler_data;
60 struct common_irq_params {
61 struct amdgpu_device *adev;
62 enum dc_irq_source irq_src;
66 * struct irq_list_head - Linked-list for low context IRQ handlers.
68 * @head: The list_head within &struct handler_data
69 * @work: A work_struct containing the deferred handler work
71 struct irq_list_head {
72 struct list_head head;
73 /* In case this interrupt needs post-processing, 'work' will be queued*/
74 struct work_struct work;
78 * struct dm_compressor_info - Buffer info used by frame buffer compression
79 * @cpu_addr: MMIO cpu addr
80 * @bo_ptr: Pointer to the buffer object
81 * @gpu_addr: MMIO gpu addr
83 struct dm_comressor_info {
85 struct amdgpu_bo *bo_ptr;
90 * struct amdgpu_dm_backlight_caps - Usable range of backlight values from ACPI
91 * @min_input_signal: minimum possible input in range 0-255
92 * @max_input_signal: maximum possible input in range 0-255
93 * @caps_valid: true if these values are from the ACPI interface
95 struct amdgpu_dm_backlight_caps {
102 * struct amdgpu_display_manager - Central amdgpu display manager device
104 * @dc: Display Core control structure
105 * @adev: AMDGPU base driver structure
106 * @ddev: DRM base driver structure
107 * @display_indexes_num: Max number of display streams supported
108 * @irq_handler_list_table_lock: Synchronizes access to IRQ tables
109 * @backlight_dev: Backlight control device
110 * @cached_state: Caches device atomic state for suspend/resume
111 * @compressor: Frame buffer compression buffer. See &struct dm_comressor_info
113 struct amdgpu_display_manager {
120 * The Common Graphics Services device. It provides an interface for
121 * accessing registers.
123 struct cgs_device *cgs_device;
125 struct amdgpu_device *adev;
126 struct drm_device *ddev;
127 u16 display_indexes_num;
132 * In combination with &dm_atomic_state it helps manage
133 * global atomic state that doesn't map cleanly into existing
134 * drm resources, like &dc_context.
136 struct drm_private_obj atomic_obj;
141 * Guards access to DC functions that can issue register write
144 struct mutex dc_lock;
147 * @irq_handler_list_low_tab:
149 * Low priority IRQ handler table.
151 * It is a n*m table consisting of n IRQ sources, and m handlers per IRQ
152 * source. Low priority IRQ handlers are deferred to a workqueue to be
153 * processed. Hence, they can sleep.
155 * Note that handlers are called in the same order as they were
158 struct irq_list_head irq_handler_list_low_tab[DAL_IRQ_SOURCES_NUMBER];
161 * @irq_handler_list_high_tab:
163 * High priority IRQ handler table.
165 * It is a n*m table, same as &irq_handler_list_low_tab. However,
166 * handlers in this table are not deferred and are called immediately.
168 struct list_head irq_handler_list_high_tab[DAL_IRQ_SOURCES_NUMBER];
173 * Page flip IRQ parameters, passed to registered handlers when
176 struct common_irq_params
177 pflip_params[DC_IRQ_SOURCE_PFLIP_LAST - DC_IRQ_SOURCE_PFLIP_FIRST + 1];
182 * Vertical blanking IRQ parameters, passed to registered handlers when
185 struct common_irq_params
186 vblank_params[DC_IRQ_SOURCE_VBLANK6 - DC_IRQ_SOURCE_VBLANK1 + 1];
191 * Vertical update IRQ parameters, passed to registered handlers when
194 struct common_irq_params
195 vupdate_params[DC_IRQ_SOURCE_VUPDATE6 - DC_IRQ_SOURCE_VUPDATE1 + 1];
197 spinlock_t irq_handler_list_table_lock;
199 struct backlight_device *backlight_dev;
201 const struct dc_link *backlight_link;
202 struct amdgpu_dm_backlight_caps backlight_caps;
204 struct mod_freesync *freesync_module;
206 struct drm_atomic_state *cached_state;
208 struct dm_comressor_info compressor;
210 const struct firmware *fw_dmcu;
211 uint32_t dmcu_fw_version;
212 #ifdef CONFIG_DRM_AMD_DC_DCN2_0
214 * gpu_info FW provided soc bounding box struct or 0 if not
217 const struct gpu_info_soc_bounding_box_v1_0 *soc_bounding_box;
221 struct amdgpu_dm_connector {
223 struct drm_connector base;
224 uint32_t connector_id;
226 /* we need to mind the EDID between detect
227 and get modes due to analog/digital/tvencoder */
230 /* shared with amdgpu */
231 struct amdgpu_hpd hpd;
233 /* number of modes generated from EDID at 'dc_sink' */
236 /* The 'old' sink - before an HPD.
237 * The 'current' sink is in dc_link->sink. */
238 struct dc_sink *dc_sink;
239 struct dc_link *dc_link;
240 struct dc_sink *dc_em_sink;
243 struct drm_dp_mst_topology_mgr mst_mgr;
244 struct amdgpu_dm_dp_aux dm_dp_aux;
245 struct drm_dp_mst_port *port;
246 struct amdgpu_dm_connector *mst_port;
247 struct amdgpu_encoder *mst_encoder;
249 /* TODO see if we can merge with ddc_bus or make a dm_connector */
250 struct amdgpu_i2c_adapter *i2c;
252 /* Monitor range limits */
257 struct mutex hpd_lock;
260 #ifdef CONFIG_DEBUG_FS
261 uint32_t debugfs_dpcd_address;
262 uint32_t debugfs_dpcd_size;
266 #define to_amdgpu_dm_connector(x) container_of(x, struct amdgpu_dm_connector, base)
268 extern const struct amdgpu_ip_block_version dm_ip_block;
270 struct amdgpu_framebuffer;
271 struct amdgpu_display_manager;
272 struct dc_validation_set;
273 struct dc_plane_state;
275 struct dm_plane_state {
276 struct drm_plane_state base;
277 struct dc_plane_state *dc_state;
280 struct dm_crtc_state {
281 struct drm_crtc_state base;
282 struct dc_stream_state *stream;
285 bool cm_is_degamma_srgb;
288 bool interrupts_enabled;
293 bool freesync_timing_changed;
294 bool freesync_vrr_info_changed;
297 struct mod_freesync_config freesync_config;
298 struct mod_vrr_params vrr_params;
299 struct dc_info_packet vrr_infopacket;
304 #define to_dm_crtc_state(x) container_of(x, struct dm_crtc_state, base)
306 struct dm_atomic_state {
307 struct drm_private_state base;
309 struct dc_state *context;
312 #define to_dm_atomic_state(x) container_of(x, struct dm_atomic_state, base)
314 struct dm_connector_state {
315 struct drm_connector_state base;
317 enum amdgpu_rmx_type scaling;
318 uint8_t underscan_vborder;
319 uint8_t underscan_hborder;
320 bool underscan_enable;
321 bool freesync_capable;
325 #define to_dm_connector_state(x)\
326 container_of((x), struct dm_connector_state, base)
328 void amdgpu_dm_connector_funcs_reset(struct drm_connector *connector);
329 struct drm_connector_state *
330 amdgpu_dm_connector_atomic_duplicate_state(struct drm_connector *connector);
331 int amdgpu_dm_connector_atomic_set_property(struct drm_connector *connector,
332 struct drm_connector_state *state,
333 struct drm_property *property,
336 int amdgpu_dm_connector_atomic_get_property(struct drm_connector *connector,
337 const struct drm_connector_state *state,
338 struct drm_property *property,
341 int amdgpu_dm_get_encoder_crtc_mask(struct amdgpu_device *adev);
343 void amdgpu_dm_connector_init_helper(struct amdgpu_display_manager *dm,
344 struct amdgpu_dm_connector *aconnector,
346 struct dc_link *link,
349 enum drm_mode_status amdgpu_dm_connector_mode_valid(struct drm_connector *connector,
350 struct drm_display_mode *mode);
352 void dm_restore_drm_connector_state(struct drm_device *dev,
353 struct drm_connector *connector);
355 void amdgpu_dm_update_freesync_caps(struct drm_connector *connector,
358 /* amdgpu_dm_crc.c */
359 #ifdef CONFIG_DEBUG_FS
360 int amdgpu_dm_crtc_set_crc_source(struct drm_crtc *crtc, const char *src_name);
361 int amdgpu_dm_crtc_verify_crc_source(struct drm_crtc *crtc,
362 const char *src_name,
364 void amdgpu_dm_crtc_handle_crc_irq(struct drm_crtc *crtc);
366 #define amdgpu_dm_crtc_set_crc_source NULL
367 #define amdgpu_dm_crtc_verify_crc_source NULL
368 #define amdgpu_dm_crtc_handle_crc_irq(x)
371 #define MAX_COLOR_LUT_ENTRIES 4096
372 /* Legacy gamm LUT users such as X doesn't like large LUT sizes */
373 #define MAX_COLOR_LEGACY_LUT_ENTRIES 256
375 void amdgpu_dm_init_color_mod(void);
376 int amdgpu_dm_update_crtc_color_mgmt(struct dm_crtc_state *crtc);
377 int amdgpu_dm_update_plane_color_mgmt(struct dm_crtc_state *crtc,
378 struct dc_plane_state *dc_plane_state);
380 extern const struct drm_encoder_helper_funcs amdgpu_dm_encoder_helper_funcs;
382 #endif /* __AMDGPU_DM_H__ */