2 * Copyright 2015 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
26 #include <linux/string.h>
27 #include <linux/acpi.h>
28 #include <linux/version.h>
29 #include <linux/i2c.h>
32 #include <drm/drm_crtc_helper.h>
33 #include <drm/amdgpu_drm.h>
34 #include <drm/drm_edid.h>
36 #include "dm_services.h"
39 #include "amdgpu_dm.h"
40 #include "amdgpu_dm_irq.h"
42 #include "dm_helpers.h"
44 /* dm_helpers_parse_edid_caps
48 * @edid: [in] pointer to edid
49 * edid_caps: [in] pointer to edid caps
53 enum dc_edid_status dm_helpers_parse_edid_caps(
54 struct dc_context *ctx,
55 const struct dc_edid *edid,
56 struct dc_edid_caps *edid_caps)
58 struct edid *edid_buf = (struct edid *) edid->raw_edid;
66 enum dc_edid_status result = EDID_OK;
68 if (!edid_caps || !edid)
69 return EDID_BAD_INPUT;
71 if (!drm_edid_is_valid(edid_buf))
72 result = EDID_BAD_CHECKSUM;
74 edid_caps->manufacturer_id = (uint16_t) edid_buf->mfg_id[0] |
75 ((uint16_t) edid_buf->mfg_id[1])<<8;
76 edid_caps->product_id = (uint16_t) edid_buf->prod_code[0] |
77 ((uint16_t) edid_buf->prod_code[1])<<8;
78 edid_caps->serial_number = edid_buf->serial;
79 edid_caps->manufacture_week = edid_buf->mfg_week;
80 edid_caps->manufacture_year = edid_buf->mfg_year;
82 /* One of the four detailed_timings stores the monitor name. It's
83 * stored in an array of length 13. */
84 for (i = 0; i < 4; i++) {
85 if (edid_buf->detailed_timings[i].data.other_data.type == 0xfc) {
86 while (j < 13 && edid_buf->detailed_timings[i].data.other_data.data.str.str[j]) {
87 if (edid_buf->detailed_timings[i].data.other_data.data.str.str[j] == '\n')
90 edid_caps->display_name[j] =
91 edid_buf->detailed_timings[i].data.other_data.data.str.str[j];
97 edid_caps->edid_hdmi = drm_detect_hdmi_monitor(
98 (struct edid *) edid->raw_edid);
100 sad_count = drm_edid_to_sad((struct edid *) edid->raw_edid, &sads);
101 if (sad_count <= 0) {
102 DRM_INFO("SADs count is: %d, don't need to read it\n",
107 edid_caps->audio_mode_count = sad_count < DC_MAX_AUDIO_DESC_COUNT ? sad_count : DC_MAX_AUDIO_DESC_COUNT;
108 for (i = 0; i < edid_caps->audio_mode_count; ++i) {
109 struct cea_sad *sad = &sads[i];
111 edid_caps->audio_modes[i].format_code = sad->format;
112 edid_caps->audio_modes[i].channel_count = sad->channels + 1;
113 edid_caps->audio_modes[i].sample_rate = sad->freq;
114 edid_caps->audio_modes[i].sample_size = sad->byte2;
117 sadb_count = drm_edid_to_speaker_allocation((struct edid *) edid->raw_edid, &sadb);
119 if (sadb_count < 0) {
120 DRM_ERROR("Couldn't read Speaker Allocation Data Block: %d\n", sadb_count);
125 edid_caps->speaker_flags = sadb[0];
127 edid_caps->speaker_flags = DEFAULT_SPEAKER_LOCATION;
135 static void get_payload_table(
136 struct amdgpu_dm_connector *aconnector,
137 struct dp_mst_stream_allocation_table *proposed_table)
140 struct drm_dp_mst_topology_mgr *mst_mgr =
141 &aconnector->mst_port->mst_mgr;
143 mutex_lock(&mst_mgr->payload_lock);
145 proposed_table->stream_count = 0;
147 /* number of active streams */
148 for (i = 0; i < mst_mgr->max_payloads; i++) {
149 if (mst_mgr->payloads[i].num_slots == 0)
150 break; /* end of vcp_id table */
152 ASSERT(mst_mgr->payloads[i].payload_state !=
153 DP_PAYLOAD_DELETE_LOCAL);
155 if (mst_mgr->payloads[i].payload_state == DP_PAYLOAD_LOCAL ||
156 mst_mgr->payloads[i].payload_state ==
159 struct dp_mst_stream_allocation *sa =
160 &proposed_table->stream_allocations[
161 proposed_table->stream_count];
163 sa->slot_count = mst_mgr->payloads[i].num_slots;
164 sa->vcp_id = mst_mgr->proposed_vcpis[i]->vcpi;
165 proposed_table->stream_count++;
169 mutex_unlock(&mst_mgr->payload_lock);
172 void dm_helpers_dp_update_branch_info(
173 struct dc_context *ctx,
174 const struct dc_link *link)
178 * Writes payload allocation table in immediate downstream device.
180 bool dm_helpers_dp_mst_write_payload_allocation_table(
181 struct dc_context *ctx,
182 const struct dc_stream_state *stream,
183 struct dp_mst_stream_allocation_table *proposed_table,
186 struct amdgpu_dm_connector *aconnector;
187 struct drm_dp_mst_topology_mgr *mst_mgr;
188 struct drm_dp_mst_port *mst_port;
195 aconnector = stream->sink->priv;
197 if (!aconnector || !aconnector->mst_port)
200 mst_mgr = &aconnector->mst_port->mst_mgr;
202 if (!mst_mgr->mst_state)
205 mst_port = aconnector->port;
208 clock = stream->timing.pix_clk_khz;
210 switch (stream->timing.display_color_depth) {
212 case COLOR_DEPTH_666:
215 case COLOR_DEPTH_888:
218 case COLOR_DEPTH_101010:
221 case COLOR_DEPTH_121212:
224 case COLOR_DEPTH_141414:
227 case COLOR_DEPTH_161616:
237 /* TODO need to know link rate */
239 pbn = drm_dp_calc_pbn_mode(clock, bpp);
241 slots = drm_dp_find_vcpi_slots(mst_mgr, pbn);
242 ret = drm_dp_mst_allocate_vcpi(mst_mgr, mst_port, pbn, slots);
248 drm_dp_mst_reset_vcpi_slots(mst_mgr, mst_port);
251 ret = drm_dp_update_payload_part1(mst_mgr);
253 /* mst_mgr->->payloads are VC payload notify MST branch using DPCD or
254 * AUX message. The sequence is slot 1-63 allocated sequence for each
255 * stream. AMD ASIC stream slot allocation should follow the same
256 * sequence. copy DRM MST allocation to dc */
258 get_payload_table(aconnector, proposed_table);
268 * Clear payload allocation table before enable MST DP link.
270 void dm_helpers_dp_mst_clear_payload_allocation_table(
271 struct dc_context *ctx,
272 const struct dc_link *link)
276 * Polls for ACT (allocation change trigger) handled and sends
277 * ALLOCATE_PAYLOAD message.
279 bool dm_helpers_dp_mst_poll_for_allocation_change_trigger(
280 struct dc_context *ctx,
281 const struct dc_stream_state *stream)
283 struct amdgpu_dm_connector *aconnector;
284 struct drm_dp_mst_topology_mgr *mst_mgr;
287 aconnector = stream->sink->priv;
289 if (!aconnector || !aconnector->mst_port)
292 mst_mgr = &aconnector->mst_port->mst_mgr;
294 if (!mst_mgr->mst_state)
297 ret = drm_dp_check_act_status(mst_mgr);
305 bool dm_helpers_dp_mst_send_payload_allocation(
306 struct dc_context *ctx,
307 const struct dc_stream_state *stream,
310 struct amdgpu_dm_connector *aconnector;
311 struct drm_dp_mst_topology_mgr *mst_mgr;
312 struct drm_dp_mst_port *mst_port;
315 aconnector = stream->sink->priv;
317 if (!aconnector || !aconnector->mst_port)
320 mst_port = aconnector->port;
322 mst_mgr = &aconnector->mst_port->mst_mgr;
324 if (!mst_mgr->mst_state)
327 ret = drm_dp_update_payload_part2(mst_mgr);
333 drm_dp_mst_deallocate_vcpi(mst_mgr, mst_port);
338 void dm_dtn_log_begin(struct dc_context *ctx)
341 void dm_dtn_log_append_v(struct dc_context *ctx,
342 const char *pMsg, ...)
345 void dm_dtn_log_end(struct dc_context *ctx)
348 bool dm_helpers_dp_mst_start_top_mgr(
349 struct dc_context *ctx,
350 const struct dc_link *link,
353 struct amdgpu_dm_connector *aconnector = link->priv;
356 DRM_ERROR("Failed to found connector for link!");
361 DRM_INFO("DM_MST: Differing MST start on aconnector: %p [id: %d]\n",
362 aconnector, aconnector->base.base.id);
366 DRM_INFO("DM_MST: starting TM on aconnector: %p [id: %d]\n",
367 aconnector, aconnector->base.base.id);
369 return (drm_dp_mst_topology_mgr_set_mst(&aconnector->mst_mgr, true) == 0);
372 void dm_helpers_dp_mst_stop_top_mgr(
373 struct dc_context *ctx,
374 const struct dc_link *link)
376 struct amdgpu_dm_connector *aconnector = link->priv;
379 DRM_ERROR("Failed to found connector for link!");
383 DRM_INFO("DM_MST: stopping TM on aconnector: %p [id: %d]\n",
384 aconnector, aconnector->base.base.id);
386 if (aconnector->mst_mgr.mst_state == true)
387 drm_dp_mst_topology_mgr_set_mst(&aconnector->mst_mgr, false);
390 bool dm_helpers_dp_read_dpcd(
391 struct dc_context *ctx,
392 const struct dc_link *link,
398 struct amdgpu_dm_connector *aconnector = link->priv;
401 DRM_ERROR("Failed to found connector for link!");
405 return drm_dp_dpcd_read(&aconnector->dm_dp_aux.aux, address,
409 bool dm_helpers_dp_write_dpcd(
410 struct dc_context *ctx,
411 const struct dc_link *link,
416 struct amdgpu_dm_connector *aconnector = link->priv;
419 DRM_ERROR("Failed to found connector for link!");
423 return drm_dp_dpcd_write(&aconnector->dm_dp_aux.aux,
424 address, (uint8_t *)data, size) > 0;
427 bool dm_helpers_submit_i2c(
428 struct dc_context *ctx,
429 const struct dc_link *link,
430 struct i2c_command *cmd)
432 struct amdgpu_dm_connector *aconnector = link->priv;
433 struct i2c_msg *msgs;
435 int num = cmd->number_of_payloads;
439 DRM_ERROR("Failed to found connector for link!");
443 msgs = kcalloc(num, sizeof(struct i2c_msg), GFP_KERNEL);
448 for (i = 0; i < num; i++) {
449 msgs[i].flags = cmd->payloads[i].write ? 0 : I2C_M_RD;
450 msgs[i].addr = cmd->payloads[i].address;
451 msgs[i].len = cmd->payloads[i].length;
452 msgs[i].buf = cmd->payloads[i].data;
455 result = i2c_transfer(&aconnector->i2c->base, msgs, num) == num;
462 bool dm_helpers_is_dp_sink_present(struct dc_link *link)
464 bool dp_sink_present;
465 struct amdgpu_dm_connector *aconnector = link->priv;
468 BUG_ON("Failed to found connector for link!");
472 mutex_lock(&aconnector->dm_dp_aux.aux.hw_mutex);
473 dp_sink_present = dc_link_is_dp_sink_present(link);
474 mutex_unlock(&aconnector->dm_dp_aux.aux.hw_mutex);
475 return dp_sink_present;
478 enum dc_edid_status dm_helpers_read_local_edid(
479 struct dc_context *ctx,
480 struct dc_link *link,
481 struct dc_sink *sink)
483 struct amdgpu_dm_connector *aconnector = link->priv;
484 struct i2c_adapter *ddc;
486 enum dc_edid_status edid_status;
490 ddc = &aconnector->dm_dp_aux.aux.ddc;
492 ddc = &aconnector->i2c->base;
494 /* some dongles read edid incorrectly the first time,
495 * do check sum and retry to make sure read correct edid.
499 edid = drm_get_edid(&aconnector->base, ddc);
502 return EDID_NO_RESPONSE;
504 sink->dc_edid.length = EDID_LENGTH * (edid->extensions + 1);
505 memmove(sink->dc_edid.raw_edid, (uint8_t *)edid, sink->dc_edid.length);
507 /* We don't need the original edid anymore */
510 edid_status = dm_helpers_parse_edid_caps(
515 } while (edid_status == EDID_BAD_CHECKSUM && --retry > 0);
517 if (edid_status != EDID_OK)
518 DRM_ERROR("EDID err: %d, on connector: %s",
520 aconnector->base.name);
521 if (link->aux_mode) {
522 union test_request test_request = { {0} };
523 union test_response test_response = { {0} };
525 dm_helpers_dp_read_dpcd(ctx,
529 sizeof(union test_request));
531 if (!test_request.bits.EDID_READ)
534 test_response.bits.EDID_CHECKSUM_WRITE = 1;
536 dm_helpers_dp_write_dpcd(ctx,
538 DP_TEST_EDID_CHECKSUM,
539 &sink->dc_edid.raw_edid[sink->dc_edid.length-1],
542 dm_helpers_dp_write_dpcd(ctx,
546 sizeof(test_response));
553 void dm_set_dcn_clocks(struct dc_context *ctx, struct dc_clocks *clks)
555 /* TODO: something */