drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c

   1 /*
   2  * Copyright 2012-15 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: AMD
  23  *
  24  */
  25
  26 #include <linux/version.h>
  27 #include <drm/drm_atomic_helper.h>
  28 #include <drm/drm_dp_mst_helper.h>
  29 #include "dm_services.h"
  30 #include "amdgpu.h"
  31 #include "amdgpu_dm.h"
  32 #include "amdgpu_dm_mst_types.h"
  33
  34 #include "dc.h"
  35 #include "dm_helpers.h"
  36
  37 #include "dc_link_ddc.h"
  38
  39 #include "i2caux_interface.h"
  40 #if defined(CONFIG_DEBUG_FS)
  41 #include "amdgpu_dm_debugfs.h"
  42 #endif
  43
  44
  45 #include "dc/dcn20/dcn20_resource.h"
  46
  47 /* #define TRACE_DPCD */
  48
  49 #ifdef TRACE_DPCD
  50 #define SIDE_BAND_MSG(address) (address >= DP_SIDEBAND_MSG_DOWN_REQ_BASE && address < DP_SINK_COUNT_ESI)
  51
  52 static inline char *side_band_msg_type_to_str(uint32_t address)
  53 {
  54         static char str[10] = {0};
  55
  56         if (address < DP_SIDEBAND_MSG_UP_REP_BASE)
  57                 strcpy(str, "DOWN_REQ");
  58         else if (address < DP_SIDEBAND_MSG_DOWN_REP_BASE)
  59                 strcpy(str, "UP_REP");
  60         else if (address < DP_SIDEBAND_MSG_UP_REQ_BASE)
  61                 strcpy(str, "DOWN_REP");
  62         else
  63                 strcpy(str, "UP_REQ");
  64
  65         return str;
  66 }
  67
  68 static void log_dpcd(uint8_t type,
  69                      uint32_t address,
  70                      uint8_t *data,
  71                      uint32_t size,
  72                      bool res)
  73 {
  74         DRM_DEBUG_KMS("Op: %s, addr: %04x, SideBand Msg: %s, Op res: %s\n",
  75                         (type == DP_AUX_NATIVE_READ) ||
  76                         (type == DP_AUX_I2C_READ) ?
  77                                         "Read" : "Write",
  78                         address,
  79                         SIDE_BAND_MSG(address) ?
  80                                         side_band_msg_type_to_str(address) : "Nop",
  81                         res ? "OK" : "Fail");
  82
  83         if (res) {
  84                 print_hex_dump(KERN_INFO, "Body: ", DUMP_PREFIX_NONE, 16, 1, data, size, false);
  85         }
  86 }
  87 #endif
  88
  89 static ssize_t dm_dp_aux_transfer(struct drm_dp_aux *aux,
  90                                   struct drm_dp_aux_msg *msg)
  91 {
  92         ssize_t result = 0;
  93         struct aux_payload payload;
  94         enum aux_channel_operation_result operation_result;
  95
  96         if (WARN_ON(msg->size > 16))
  97                 return -E2BIG;
  98
  99         payload.address = msg->address;
 100         payload.data = msg->buffer;
 101         payload.length = msg->size;
 102         payload.reply = &msg->reply;
 103         payload.i2c_over_aux = (msg->request & DP_AUX_NATIVE_WRITE) == 0;
 104         payload.write = (msg->request & DP_AUX_I2C_READ) == 0;
 105         payload.mot = (msg->request & DP_AUX_I2C_MOT) != 0;
 106         payload.defer_delay = 0;
 107
 108         result = dc_link_aux_transfer_raw(TO_DM_AUX(aux)->ddc_service, &payload,
 109                                       &operation_result);
 110
 111         if (payload.write)
 112                 result = msg->size;
 113
 114         if (result < 0)
 115                 switch (operation_result) {
 116                 case AUX_CHANNEL_OPERATION_SUCCEEDED:
 117                         break;
 118                 case AUX_CHANNEL_OPERATION_FAILED_HPD_DISCON:
 119                 case AUX_CHANNEL_OPERATION_FAILED_REASON_UNKNOWN:
 120                         result = -EIO;
 121                         break;
 122                 case AUX_CHANNEL_OPERATION_FAILED_INVALID_REPLY:
 123                 case AUX_CHANNEL_OPERATION_FAILED_ENGINE_ACQUIRE:
 124                         result = -EBUSY;
 125                         break;
 126                 case AUX_CHANNEL_OPERATION_FAILED_TIMEOUT:
 127                         result = -ETIMEDOUT;
 128                         break;
 129                 }
 130
 131         return result;
 132 }
 133
 134 static void
 135 dm_dp_mst_connector_destroy(struct drm_connector *connector)
 136 {
 137         struct amdgpu_dm_connector *amdgpu_dm_connector = to_amdgpu_dm_connector(connector);
 138         struct amdgpu_encoder *amdgpu_encoder = amdgpu_dm_connector->mst_encoder;
 139
 140         kfree(amdgpu_dm_connector->edid);
 141         amdgpu_dm_connector->edid = NULL;
 142
 143         drm_encoder_cleanup(&amdgpu_encoder->base);
 144         kfree(amdgpu_encoder);
 145         drm_connector_cleanup(connector);
 146         drm_dp_mst_put_port_malloc(amdgpu_dm_connector->port);
 147         kfree(amdgpu_dm_connector);
 148 }
 149
 150 static int
 151 amdgpu_dm_mst_connector_late_register(struct drm_connector *connector)
 152 {
 153         struct amdgpu_dm_connector *amdgpu_dm_connector =
 154                 to_amdgpu_dm_connector(connector);
 155         struct drm_dp_mst_port *port = amdgpu_dm_connector->port;
 156
 157 #if defined(CONFIG_DEBUG_FS)
 158         connector_debugfs_init(amdgpu_dm_connector);
 159         amdgpu_dm_connector->debugfs_dpcd_address = 0;
 160         amdgpu_dm_connector->debugfs_dpcd_size = 0;
 161 #endif
 162
 163         return drm_dp_mst_connector_late_register(connector, port);
 164 }
 165
 166 static void
 167 amdgpu_dm_mst_connector_early_unregister(struct drm_connector *connector)
 168 {
 169         struct amdgpu_dm_connector *amdgpu_dm_connector =
 170                 to_amdgpu_dm_connector(connector);
 171         struct drm_dp_mst_port *port = amdgpu_dm_connector->port;
 172
 173         drm_dp_mst_connector_early_unregister(connector, port);
 174 }
 175
 176 static const struct drm_connector_funcs dm_dp_mst_connector_funcs = {
 177         .fill_modes = drm_helper_probe_single_connector_modes,
 178         .destroy = dm_dp_mst_connector_destroy,
 179         .reset = amdgpu_dm_connector_funcs_reset,
 180         .atomic_duplicate_state = amdgpu_dm_connector_atomic_duplicate_state,
 181         .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
 182         .atomic_set_property = amdgpu_dm_connector_atomic_set_property,
 183         .atomic_get_property = amdgpu_dm_connector_atomic_get_property,
 184         .late_register = amdgpu_dm_mst_connector_late_register,
 185         .early_unregister = amdgpu_dm_mst_connector_early_unregister,
 186 };
 187
 188 static bool validate_dsc_caps_on_connector(struct amdgpu_dm_connector *aconnector)
 189 {
 190         struct dc_sink *dc_sink = aconnector->dc_sink;
 191         struct drm_dp_mst_port *port = aconnector->port;
 192         u8 dsc_caps[16] = { 0 };
 193
 194         aconnector->dsc_aux = drm_dp_mst_dsc_aux_for_port(port);
 195
 196         if (!aconnector->dsc_aux)
 197                 return false;
 198
 199         if (drm_dp_dpcd_read(aconnector->dsc_aux, DP_DSC_SUPPORT, dsc_caps, 16) < 0)
 200                 return false;
 201
 202         if (!dc_dsc_parse_dsc_dpcd(aconnector->dc_link->ctx->dc,
 203                                    dsc_caps, NULL,
 204                                    &dc_sink->sink_dsc_caps.dsc_dec_caps))
 205                 return false;
 206
 207         return true;
 208 }
 209
 210 static int dm_dp_mst_get_modes(struct drm_connector *connector)
 211 {
 212         struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
 213         int ret = 0;
 214
 215         if (!aconnector)
 216                 return drm_add_edid_modes(connector, NULL);
 217
 218         if (!aconnector->edid) {
 219                 struct edid *edid;
 220                 edid = drm_dp_mst_get_edid(connector, &aconnector->mst_port->mst_mgr, aconnector->port);
 221
 222                 if (!edid) {
 223                         drm_connector_update_edid_property(
 224                                 &aconnector->base,
 225                                 NULL);
 226                         return ret;
 227                 }
 228
 229                 aconnector->edid = edid;
 230         }
 231
 232         if (aconnector->dc_sink && aconnector->dc_sink->sink_signal == SIGNAL_TYPE_VIRTUAL) {
 233                 dc_sink_release(aconnector->dc_sink);
 234                 aconnector->dc_sink = NULL;
 235         }
 236
 237         if (!aconnector->dc_sink) {
 238                 struct dc_sink *dc_sink;
 239                 struct dc_sink_init_data init_params = {
 240                                 .link = aconnector->dc_link,
 241                                 .sink_signal = SIGNAL_TYPE_DISPLAY_PORT_MST };
 242                 dc_sink = dc_link_add_remote_sink(
 243                         aconnector->dc_link,
 244                         (uint8_t *)aconnector->edid,
 245                         (aconnector->edid->extensions + 1) * EDID_LENGTH,
 246                         &init_params);
 247
 248                 dc_sink->priv = aconnector;
 249                 /* dc_link_add_remote_sink returns a new reference */
 250                 aconnector->dc_sink = dc_sink;
 251
 252                 if (aconnector->dc_sink) {
 253                         amdgpu_dm_update_freesync_caps(
 254                                         connector, aconnector->edid);
 255
 256                         if (!validate_dsc_caps_on_connector(aconnector))
 257                                 memset(&aconnector->dc_sink->sink_dsc_caps,
 258                                        0, sizeof(aconnector->dc_sink->sink_dsc_caps));
 259                 }
 260         }
 261
 262         drm_connector_update_edid_property(
 263                                         &aconnector->base, aconnector->edid);
 264
 265         ret = drm_add_edid_modes(connector, aconnector->edid);
 266
 267         return ret;
 268 }
 269
 270 static struct drm_encoder *
 271 dm_mst_atomic_best_encoder(struct drm_connector *connector,
 272                            struct drm_connector_state *connector_state)
 273 {
 274         return &to_amdgpu_dm_connector(connector)->mst_encoder->base;
 275 }
 276
 277 static int
 278 dm_dp_mst_detect(struct drm_connector *connector,
 279                  struct drm_modeset_acquire_ctx *ctx, bool force)
 280 {
 281         struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
 282         struct amdgpu_dm_connector *master = aconnector->mst_port;
 283
 284         return drm_dp_mst_detect_port(connector, ctx, &master->mst_mgr,
 285                                       aconnector->port);
 286 }
 287
 288 static int dm_dp_mst_atomic_check(struct drm_connector *connector,
 289                                 struct drm_atomic_state *state)
 290 {
 291         struct drm_connector_state *new_conn_state =
 292                         drm_atomic_get_new_connector_state(state, connector);
 293         struct drm_connector_state *old_conn_state =
 294                         drm_atomic_get_old_connector_state(state, connector);
 295         struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
 296         struct drm_crtc_state *new_crtc_state;
 297         struct drm_dp_mst_topology_mgr *mst_mgr;
 298         struct drm_dp_mst_port *mst_port;
 299
 300         mst_port = aconnector->port;
 301         mst_mgr = &aconnector->mst_port->mst_mgr;
 302
 303         if (!old_conn_state->crtc)
 304                 return 0;
 305
 306         if (new_conn_state->crtc) {
 307                 new_crtc_state = drm_atomic_get_new_crtc_state(state, new_conn_state->crtc);
 308                 if (!new_crtc_state ||
 309                     !drm_atomic_crtc_needs_modeset(new_crtc_state) ||
 310                     new_crtc_state->enable)
 311                         return 0;
 312                 }
 313
 314         return drm_dp_atomic_release_vcpi_slots(state,
 315                                                 mst_mgr,
 316                                                 mst_port);
 317 }
 318
 319 static const struct drm_connector_helper_funcs dm_dp_mst_connector_helper_funcs = {
 320         .get_modes = dm_dp_mst_get_modes,
 321         .mode_valid = amdgpu_dm_connector_mode_valid,
 322         .atomic_best_encoder = dm_mst_atomic_best_encoder,
 323         .detect_ctx = dm_dp_mst_detect,
 324         .atomic_check = dm_dp_mst_atomic_check,
 325 };
 326
 327 static void amdgpu_dm_encoder_destroy(struct drm_encoder *encoder)
 328 {
 329         drm_encoder_cleanup(encoder);
 330         kfree(encoder);
 331 }
 332
 333 static const struct drm_encoder_funcs amdgpu_dm_encoder_funcs = {
 334         .destroy = amdgpu_dm_encoder_destroy,
 335 };
 336
 337 static struct amdgpu_encoder *
 338 dm_dp_create_fake_mst_encoder(struct amdgpu_dm_connector *connector)
 339 {
 340         struct drm_device *dev = connector->base.dev;
 341         struct amdgpu_device *adev = dev->dev_private;
 342         struct amdgpu_encoder *amdgpu_encoder;
 343         struct drm_encoder *encoder;
 344
 345         amdgpu_encoder = kzalloc(sizeof(*amdgpu_encoder), GFP_KERNEL);
 346         if (!amdgpu_encoder)
 347                 return NULL;
 348
 349         encoder = &amdgpu_encoder->base;
 350         encoder->possible_crtcs = amdgpu_dm_get_encoder_crtc_mask(adev);
 351
 352         drm_encoder_init(
 353                 dev,
 354                 &amdgpu_encoder->base,
 355                 &amdgpu_dm_encoder_funcs,
 356                 DRM_MODE_ENCODER_DPMST,
 357                 NULL);
 358
 359         drm_encoder_helper_add(encoder, &amdgpu_dm_encoder_helper_funcs);
 360
 361         return amdgpu_encoder;
 362 }
 363
 364 static struct drm_connector *
 365 dm_dp_add_mst_connector(struct drm_dp_mst_topology_mgr *mgr,
 366                         struct drm_dp_mst_port *port,
 367                         const char *pathprop)
 368 {
 369         struct amdgpu_dm_connector *master = container_of(mgr, struct amdgpu_dm_connector, mst_mgr);
 370         struct drm_device *dev = master->base.dev;
 371         struct amdgpu_device *adev = dev->dev_private;
 372         struct amdgpu_dm_connector *aconnector;
 373         struct drm_connector *connector;
 374
 375         aconnector = kzalloc(sizeof(*aconnector), GFP_KERNEL);
 376         if (!aconnector)
 377                 return NULL;
 378
 379         connector = &aconnector->base;
 380         aconnector->port = port;
 381         aconnector->mst_port = master;
 382
 383         if (drm_connector_init(
 384                 dev,
 385                 connector,
 386                 &dm_dp_mst_connector_funcs,
 387                 DRM_MODE_CONNECTOR_DisplayPort)) {
 388                 kfree(aconnector);
 389                 return NULL;
 390         }
 391         drm_connector_helper_add(connector, &dm_dp_mst_connector_helper_funcs);
 392
 393         amdgpu_dm_connector_init_helper(
 394                 &adev->dm,
 395                 aconnector,
 396                 DRM_MODE_CONNECTOR_DisplayPort,
 397                 master->dc_link,
 398                 master->connector_id);
 399
 400         aconnector->mst_encoder = dm_dp_create_fake_mst_encoder(master);
 401         drm_connector_attach_encoder(&aconnector->base,
 402                                      &aconnector->mst_encoder->base);
 403
 404         drm_object_attach_property(
 405                 &connector->base,
 406                 dev->mode_config.path_property,
 407                 0);
 408         drm_object_attach_property(
 409                 &connector->base,
 410                 dev->mode_config.tile_property,
 411                 0);
 412
 413         drm_connector_set_path_property(connector, pathprop);
 414
 415         /*
 416          * Initialize connector state before adding the connectror to drm and
 417          * framebuffer lists
 418          */
 419         amdgpu_dm_connector_funcs_reset(connector);
 420
 421         DRM_INFO("DM_MST: added connector: %p [id: %d] [master: %p]\n",
 422                  aconnector, connector->base.id, aconnector->mst_port);
 423
 424         drm_dp_mst_get_port_malloc(port);
 425
 426         DRM_DEBUG_KMS(":%d\n", connector->base.id);
 427
 428         return connector;
 429 }
 430
 431 static void dm_dp_destroy_mst_connector(struct drm_dp_mst_topology_mgr *mgr,
 432                                         struct drm_connector *connector)
 433 {
 434         struct amdgpu_dm_connector *master = container_of(mgr, struct amdgpu_dm_connector, mst_mgr);
 435         struct drm_device *dev = master->base.dev;
 436         struct amdgpu_device *adev = dev->dev_private;
 437         struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
 438
 439         DRM_INFO("DM_MST: Disabling connector: %p [id: %d] [master: %p]\n",
 440                  aconnector, connector->base.id, aconnector->mst_port);
 441
 442         if (aconnector->dc_sink) {
 443                 amdgpu_dm_update_freesync_caps(connector, NULL);
 444                 dc_link_remove_remote_sink(aconnector->dc_link,
 445                                            aconnector->dc_sink);
 446                 dc_sink_release(aconnector->dc_sink);
 447                 aconnector->dc_sink = NULL;
 448         }
 449
 450         drm_connector_unregister(connector);
 451         if (adev->mode_info.rfbdev)
 452                 drm_fb_helper_remove_one_connector(&adev->mode_info.rfbdev->helper, connector);
 453         drm_connector_put(connector);
 454 }
 455
 456 static void dm_dp_mst_register_connector(struct drm_connector *connector)
 457 {
 458         struct drm_device *dev = connector->dev;
 459         struct amdgpu_device *adev = dev->dev_private;
 460
 461         if (adev->mode_info.rfbdev)
 462                 drm_fb_helper_add_one_connector(&adev->mode_info.rfbdev->helper, connector);
 463         else
 464                 DRM_ERROR("adev->mode_info.rfbdev is NULL\n");
 465
 466         drm_connector_register(connector);
 467 }
 468
 469 static const struct drm_dp_mst_topology_cbs dm_mst_cbs = {
 470         .add_connector = dm_dp_add_mst_connector,
 471         .destroy_connector = dm_dp_destroy_mst_connector,
 472         .register_connector = dm_dp_mst_register_connector
 473 };
 474
 475 void amdgpu_dm_initialize_dp_connector(struct amdgpu_display_manager *dm,
 476                                        struct amdgpu_dm_connector *aconnector)
 477 {
 478         aconnector->dm_dp_aux.aux.name = "dmdc";
 479         aconnector->dm_dp_aux.aux.dev = aconnector->base.kdev;
 480         aconnector->dm_dp_aux.aux.transfer = dm_dp_aux_transfer;
 481         aconnector->dm_dp_aux.ddc_service = aconnector->dc_link->ddc;
 482
 483         drm_dp_aux_register(&aconnector->dm_dp_aux.aux);
 484         drm_dp_cec_register_connector(&aconnector->dm_dp_aux.aux,
 485                                       &aconnector->base);
 486
 487         if (aconnector->base.connector_type == DRM_MODE_CONNECTOR_eDP)
 488                 return;
 489
 490         aconnector->mst_mgr.cbs = &dm_mst_cbs;
 491         drm_dp_mst_topology_mgr_init(
 492                 &aconnector->mst_mgr,
 493                 dm->adev->ddev,
 494                 &aconnector->dm_dp_aux.aux,
 495                 16,
 496                 4,
 497                 aconnector->connector_id);
 498 }
 499
 500 int dm_mst_get_pbn_divider(struct dc_link *link)
 501 {
 502         if (!link)
 503                 return 0;
 504
 505         return dc_link_bandwidth_kbps(link,
 506                         dc_link_get_link_cap(link)) / (8 * 1000 * 54);
 507 }
 508
 509 struct dsc_mst_fairness_params {
 510         struct dc_crtc_timing *timing;
 511         struct dc_sink *sink;
 512         struct dc_dsc_bw_range bw_range;
 513         bool compression_possible;
 514         struct drm_dp_mst_port *port;
 515 };
 516
 517 struct dsc_mst_fairness_vars {
 518         int pbn;
 519         bool dsc_enabled;
 520         int bpp_x16;
 521 };
 522
 523 static int kbps_to_peak_pbn(int kbps)
 524 {
 525         u64 peak_kbps = kbps;
 526
 527         peak_kbps *= 1006;
 528         peak_kbps /= 1000;
 529         return (int) DIV_ROUND_UP(peak_kbps * 64, (54 * 8 * 1000));
 530 }
 531
 532 static void set_dsc_configs_from_fairness_vars(struct dsc_mst_fairness_params *params,
 533                 struct dsc_mst_fairness_vars *vars,
 534                 int count)
 535 {
 536         int i;
 537
 538         for (i = 0; i < count; i++) {
 539                 memset(&params[i].timing->dsc_cfg, 0, sizeof(params[i].timing->dsc_cfg));
 540                 if (vars[i].dsc_enabled && dc_dsc_compute_config(
 541                                         params[i].sink->ctx->dc->res_pool->dscs[0],
 542                                         &params[i].sink->sink_dsc_caps.dsc_dec_caps,
 543                                         params[i].sink->ctx->dc->debug.dsc_min_slice_height_override,
 544                                         0,
 545                                         params[i].timing,
 546                                         &params[i].timing->dsc_cfg)) {
 547                         params[i].timing->flags.DSC = 1;
 548                         params[i].timing->dsc_cfg.bits_per_pixel = vars[i].bpp_x16;
 549                 } else {
 550                         params[i].timing->flags.DSC = 0;
 551                 }
 552         }
 553 }
 554
 555 static int bpp_x16_from_pbn(struct dsc_mst_fairness_params param, int pbn)
 556 {
 557         struct dc_dsc_config dsc_config;
 558         u64 kbps;
 559
 560         kbps = (u64)pbn * 994 * 8 * 54 / 64;
 561         dc_dsc_compute_config(
 562                         param.sink->ctx->dc->res_pool->dscs[0],
 563                         &param.sink->sink_dsc_caps.dsc_dec_caps,
 564                         param.sink->ctx->dc->debug.dsc_min_slice_height_override,
 565                         (int) kbps, param.timing, &dsc_config);
 566
 567         return dsc_config.bits_per_pixel;
 568 }
 569
 570 static void increase_dsc_bpp(struct drm_atomic_state *state,
 571                              struct dc_link *dc_link,
 572                              struct dsc_mst_fairness_params *params,
 573                              struct dsc_mst_fairness_vars *vars,
 574                              int count)
 575 {
 576         int i;
 577         bool bpp_increased[MAX_PIPES];
 578         int initial_slack[MAX_PIPES];
 579         int min_initial_slack;
 580         int next_index;
 581         int remaining_to_increase = 0;
 582         int pbn_per_timeslot;
 583         int link_timeslots_used;
 584         int fair_pbn_alloc;
 585
 586         for (i = 0; i < count; i++) {
 587                 if (vars[i].dsc_enabled) {
 588                         initial_slack[i] = kbps_to_peak_pbn(params[i].bw_range.max_kbps) - vars[i].pbn;
 589                         bpp_increased[i] = false;
 590                         remaining_to_increase += 1;
 591                 } else {
 592                         initial_slack[i] = 0;
 593                         bpp_increased[i] = true;
 594                 }
 595         }
 596
 597         pbn_per_timeslot = dc_link_bandwidth_kbps(dc_link,
 598                         dc_link_get_link_cap(dc_link)) / (8 * 1000 * 54);
 599
 600         while (remaining_to_increase) {
 601                 next_index = -1;
 602                 min_initial_slack = -1;
 603                 for (i = 0; i < count; i++) {
 604                         if (!bpp_increased[i]) {
 605                                 if (min_initial_slack == -1 || min_initial_slack > initial_slack[i]) {
 606                                         min_initial_slack = initial_slack[i];
 607                                         next_index = i;
 608                                 }
 609                         }
 610                 }
 611
 612                 if (next_index == -1)
 613                         break;
 614
 615                 link_timeslots_used = 0;
 616
 617                 for (i = 0; i < count; i++)
 618                         link_timeslots_used += DIV_ROUND_UP(vars[i].pbn, pbn_per_timeslot);
 619
 620                 fair_pbn_alloc = (63 - link_timeslots_used) / remaining_to_increase * pbn_per_timeslot;
 621
 622                 if (initial_slack[next_index] > fair_pbn_alloc) {
 623                         vars[next_index].pbn += fair_pbn_alloc;
 624                         drm_dp_atomic_find_vcpi_slots(state,
 625                                                       params[next_index].port->mgr,
 626                                                       params[next_index].port,
 627                                                       vars[next_index].pbn,
 628                                                       dm_mst_get_pbn_divider(dc_link));
 629                         if (!drm_dp_mst_atomic_check(state)) {
 630                                 vars[next_index].bpp_x16 = bpp_x16_from_pbn(params[next_index], vars[next_index].pbn);
 631                         } else {
 632                                 vars[next_index].pbn -= fair_pbn_alloc;
 633                                 drm_dp_atomic_find_vcpi_slots(state,
 634                                                       params[next_index].port->mgr,
 635                                                       params[next_index].port,
 636                                                       vars[next_index].pbn,
 637                                                       dm_mst_get_pbn_divider(dc_link));
 638                         }
 639                 } else {
 640                         vars[next_index].pbn += initial_slack[next_index];
 641                         drm_dp_atomic_find_vcpi_slots(state,
 642                                                       params[next_index].port->mgr,
 643                                                       params[next_index].port,
 644                                                       vars[next_index].pbn,
 645                                                       dm_mst_get_pbn_divider(dc_link));
 646                         if (!drm_dp_mst_atomic_check(state)) {
 647                                 vars[next_index].bpp_x16 = params[next_index].bw_range.max_target_bpp_x16;
 648                         } else {
 649                                 vars[next_index].pbn -= initial_slack[next_index];
 650                                 drm_dp_atomic_find_vcpi_slots(state,
 651                                                       params[next_index].port->mgr,
 652                                                       params[next_index].port,
 653                                                       vars[next_index].pbn,
 654                                                       dm_mst_get_pbn_divider(dc_link));
 655                         }
 656                 }
 657
 658                 bpp_increased[next_index] = true;
 659                 remaining_to_increase--;
 660         }
 661 }
 662
 663 static void try_disable_dsc(struct drm_atomic_state *state,
 664                             struct dc_link *dc_link,
 665                             struct dsc_mst_fairness_params *params,
 666                             struct dsc_mst_fairness_vars *vars,
 667                             int count)
 668 {
 669         int i;
 670         bool tried[MAX_PIPES];
 671         int kbps_increase[MAX_PIPES];
 672         int max_kbps_increase;
 673         int next_index;
 674         int remaining_to_try = 0;
 675
 676         for (i = 0; i < count; i++) {
 677                 if (vars[i].dsc_enabled && vars[i].bpp_x16 == params[i].bw_range.max_target_bpp_x16) {
 678                         kbps_increase[i] = params[i].bw_range.stream_kbps - params[i].bw_range.max_kbps;
 679                         tried[i] = false;
 680                         remaining_to_try += 1;
 681                 } else {
 682                         kbps_increase[i] = 0;
 683                         tried[i] = true;
 684                 }
 685         }
 686
 687         while (remaining_to_try) {
 688                 next_index = -1;
 689                 max_kbps_increase = -1;
 690                 for (i = 0; i < count; i++) {
 691                         if (!tried[i]) {
 692                                 if (max_kbps_increase == -1 || max_kbps_increase < kbps_increase[i]) {
 693                                         max_kbps_increase = kbps_increase[i];
 694                                         next_index = i;
 695                                 }
 696                         }
 697                 }
 698
 699                 if (next_index == -1)
 700                         break;
 701
 702                 vars[next_index].pbn = kbps_to_peak_pbn(params[next_index].bw_range.stream_kbps);
 703                 drm_dp_atomic_find_vcpi_slots(state,
 704                                               params[next_index].port->mgr,
 705                                               params[next_index].port,
 706                                               vars[next_index].pbn,
 707                                               0);
 708
 709                 if (!drm_dp_mst_atomic_check(state)) {
 710                         vars[next_index].dsc_enabled = false;
 711                         vars[next_index].bpp_x16 = 0;
 712                 } else {
 713                         vars[next_index].pbn = kbps_to_peak_pbn(params[next_index].bw_range.max_kbps);
 714                         drm_dp_atomic_find_vcpi_slots(state,
 715                                               params[next_index].port->mgr,
 716                                               params[next_index].port,
 717                                               vars[next_index].pbn,
 718                                               dm_mst_get_pbn_divider(dc_link));
 719                 }
 720
 721                 tried[next_index] = true;
 722                 remaining_to_try--;
 723         }
 724 }
 725
 726 static bool compute_mst_dsc_configs_for_link(struct drm_atomic_state *state,
 727                                              struct dc_state *dc_state,
 728                                              struct dc_link *dc_link)
 729 {
 730         int i;
 731         struct dc_stream_state *stream;
 732         struct dsc_mst_fairness_params params[MAX_PIPES];
 733         struct dsc_mst_fairness_vars vars[MAX_PIPES];
 734         struct amdgpu_dm_connector *aconnector;
 735         int count = 0;
 736
 737         memset(params, 0, sizeof(params));
 738
 739         /* Set up params */
 740         for (i = 0; i < dc_state->stream_count; i++) {
 741                 struct dc_dsc_policy dsc_policy = {0};
 742
 743                 stream = dc_state->streams[i];
 744
 745                 if (stream->link != dc_link)
 746                         continue;
 747
 748                 stream->timing.flags.DSC = 0;
 749
 750                 params[count].timing = &stream->timing;
 751                 params[count].sink = stream->sink;
 752                 aconnector = (struct amdgpu_dm_connector *)stream->dm_stream_context;
 753                 params[count].port = aconnector->port;
 754                 params[count].compression_possible = stream->sink->sink_dsc_caps.dsc_dec_caps.is_dsc_supported;
 755                 dc_dsc_get_policy_for_timing(params[count].timing, &dsc_policy);
 756                 if (!dc_dsc_compute_bandwidth_range(
 757                                 stream->sink->ctx->dc->res_pool->dscs[0],
 758                                 stream->sink->ctx->dc->debug.dsc_min_slice_height_override,
 759                                 dsc_policy.min_target_bpp,
 760                                 dsc_policy.max_target_bpp,
 761                                 &stream->sink->sink_dsc_caps.dsc_dec_caps,
 762                                 &stream->timing, &params[count].bw_range))
 763                         params[count].bw_range.stream_kbps = dc_bandwidth_in_kbps_from_timing(&stream->timing);
 764
 765                 count++;
 766         }
 767         /* Try no compression */
 768         for (i = 0; i < count; i++) {
 769                 vars[i].pbn = kbps_to_peak_pbn(params[i].bw_range.stream_kbps);
 770                 vars[i].dsc_enabled = false;
 771                 vars[i].bpp_x16 = 0;
 772                 drm_dp_atomic_find_vcpi_slots(state,
 773                                               params[i].port->mgr,
 774                                               params[i].port,
 775                                               vars[i].pbn,
 776                                               0);
 777         }
 778         if (!drm_dp_mst_atomic_check(state)) {
 779                 set_dsc_configs_from_fairness_vars(params, vars, count);
 780                 return true;
 781         }
 782
 783         /* Try max compression */
 784         for (i = 0; i < count; i++) {
 785                 if (params[i].compression_possible) {
 786                         vars[i].pbn = kbps_to_peak_pbn(params[i].bw_range.min_kbps);
 787                         vars[i].dsc_enabled = true;
 788                         vars[i].bpp_x16 = params[i].bw_range.min_target_bpp_x16;
 789                         drm_dp_atomic_find_vcpi_slots(state,
 790                                               params[i].port->mgr,
 791                                               params[i].port,
 792                                               vars[i].pbn,
 793                                               dm_mst_get_pbn_divider(dc_link));
 794                 } else {
 795                         vars[i].pbn = kbps_to_peak_pbn(params[i].bw_range.stream_kbps);
 796                         vars[i].dsc_enabled = false;
 797                         vars[i].bpp_x16 = 0;
 798                         drm_dp_atomic_find_vcpi_slots(state,
 799                                               params[i].port->mgr,
 800                                               params[i].port,
 801                                               vars[i].pbn,
 802                                               0);
 803                 }
 804         }
 805         if (drm_dp_mst_atomic_check(state))
 806                 return false;
 807
 808         /* Optimize degree of compression */
 809         increase_dsc_bpp(state, dc_link, params, vars, count);
 810
 811         try_disable_dsc(state, dc_link, params, vars, count);
 812
 813         set_dsc_configs_from_fairness_vars(params, vars, count);
 814
 815         return true;
 816 }
 817
 818 bool compute_mst_dsc_configs_for_state(struct drm_atomic_state *state,
 819                                        struct dc_state *dc_state)
 820 {
 821         int i, j;
 822         struct dc_stream_state *stream;
 823         bool computed_streams[MAX_PIPES];
 824         struct amdgpu_dm_connector *aconnector;
 825
 826         for (i = 0; i < dc_state->stream_count; i++)
 827                 computed_streams[i] = false;
 828
 829         for (i = 0; i < dc_state->stream_count; i++) {
 830                 stream = dc_state->streams[i];
 831
 832                 if (stream->signal != SIGNAL_TYPE_DISPLAY_PORT_MST)
 833                         continue;
 834
 835                 aconnector = (struct amdgpu_dm_connector *)stream->dm_stream_context;
 836
 837                 if (!aconnector || !aconnector->dc_sink)
 838                         continue;
 839
 840                 if (!aconnector->dc_sink->sink_dsc_caps.dsc_dec_caps.is_dsc_supported)
 841                         continue;
 842
 843                 if (computed_streams[i])
 844                         continue;
 845
 846                 mutex_lock(&aconnector->mst_mgr.lock);
 847                 if (!compute_mst_dsc_configs_for_link(state, dc_state, stream->link)) {
 848                         mutex_unlock(&aconnector->mst_mgr.lock);
 849                         return false;
 850                 }
 851                 mutex_unlock(&aconnector->mst_mgr.lock);
 852
 853                 for (j = 0; j < dc_state->stream_count; j++) {
 854                         if (dc_state->streams[j]->link == stream->link)
 855                                 computed_streams[j] = true;
 856                 }
 857         }
 858
 859         for (i = 0; i < dc_state->stream_count; i++) {
 860                 stream = dc_state->streams[i];
 861
 862                 if (stream->timing.flags.DSC == 1)
 863                         dcn20_add_dsc_to_stream_resource(stream->ctx->dc, dc_state, stream);
 864         }
 865
 866         return true;
 867 }