2 * Copyright 2012-15 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
26 #include <linux/version.h>
27 #include <drm/drm_atomic_helper.h>
28 #include <drm/drm_dp_mst_helper.h>
29 #include "dm_services.h"
31 #include "amdgpu_dm.h"
32 #include "amdgpu_dm_mst_types.h"
35 #include "dm_helpers.h"
37 #include "dc_link_ddc.h"
39 #include "i2caux_interface.h"
40 #if defined(CONFIG_DEBUG_FS)
41 #include "amdgpu_dm_debugfs.h"
43 /* #define TRACE_DPCD */
46 #define SIDE_BAND_MSG(address) (address >= DP_SIDEBAND_MSG_DOWN_REQ_BASE && address < DP_SINK_COUNT_ESI)
48 static inline char *side_band_msg_type_to_str(uint32_t address)
50 static char str[10] = {0};
52 if (address < DP_SIDEBAND_MSG_UP_REP_BASE)
53 strcpy(str, "DOWN_REQ");
54 else if (address < DP_SIDEBAND_MSG_DOWN_REP_BASE)
55 strcpy(str, "UP_REP");
56 else if (address < DP_SIDEBAND_MSG_UP_REQ_BASE)
57 strcpy(str, "DOWN_REP");
59 strcpy(str, "UP_REQ");
64 static void log_dpcd(uint8_t type,
70 DRM_DEBUG_KMS("Op: %s, addr: %04x, SideBand Msg: %s, Op res: %s\n",
71 (type == DP_AUX_NATIVE_READ) ||
72 (type == DP_AUX_I2C_READ) ?
75 SIDE_BAND_MSG(address) ?
76 side_band_msg_type_to_str(address) : "Nop",
80 print_hex_dump(KERN_INFO, "Body: ", DUMP_PREFIX_NONE, 16, 1, data, size, false);
85 static ssize_t dm_dp_aux_transfer(struct drm_dp_aux *aux,
86 struct drm_dp_aux_msg *msg)
89 struct aux_payload payload;
90 enum aux_channel_operation_result operation_result;
92 if (WARN_ON(msg->size > 16))
95 payload.address = msg->address;
96 payload.data = msg->buffer;
97 payload.length = msg->size;
98 payload.reply = &msg->reply;
99 payload.i2c_over_aux = (msg->request & DP_AUX_NATIVE_WRITE) == 0;
100 payload.write = (msg->request & DP_AUX_I2C_READ) == 0;
101 payload.mot = (msg->request & DP_AUX_I2C_MOT) != 0;
102 payload.defer_delay = 0;
104 result = dc_link_aux_transfer_raw(TO_DM_AUX(aux)->ddc_service, &payload,
111 switch (operation_result) {
112 case AUX_CHANNEL_OPERATION_SUCCEEDED:
114 case AUX_CHANNEL_OPERATION_FAILED_HPD_DISCON:
115 case AUX_CHANNEL_OPERATION_FAILED_REASON_UNKNOWN:
118 case AUX_CHANNEL_OPERATION_FAILED_INVALID_REPLY:
119 case AUX_CHANNEL_OPERATION_FAILED_ENGINE_ACQUIRE:
122 case AUX_CHANNEL_OPERATION_FAILED_TIMEOUT:
131 dm_dp_mst_connector_destroy(struct drm_connector *connector)
133 struct amdgpu_dm_connector *amdgpu_dm_connector = to_amdgpu_dm_connector(connector);
134 struct amdgpu_encoder *amdgpu_encoder = amdgpu_dm_connector->mst_encoder;
136 kfree(amdgpu_dm_connector->edid);
137 amdgpu_dm_connector->edid = NULL;
139 drm_encoder_cleanup(&amdgpu_encoder->base);
140 kfree(amdgpu_encoder);
141 drm_connector_cleanup(connector);
142 drm_dp_mst_put_port_malloc(amdgpu_dm_connector->port);
143 kfree(amdgpu_dm_connector);
147 amdgpu_dm_mst_connector_late_register(struct drm_connector *connector)
149 struct amdgpu_dm_connector *amdgpu_dm_connector =
150 to_amdgpu_dm_connector(connector);
151 struct drm_dp_mst_port *port = amdgpu_dm_connector->port;
153 #if defined(CONFIG_DEBUG_FS)
154 connector_debugfs_init(amdgpu_dm_connector);
155 amdgpu_dm_connector->debugfs_dpcd_address = 0;
156 amdgpu_dm_connector->debugfs_dpcd_size = 0;
159 return drm_dp_mst_connector_late_register(connector, port);
163 amdgpu_dm_mst_connector_early_unregister(struct drm_connector *connector)
165 struct amdgpu_dm_connector *amdgpu_dm_connector =
166 to_amdgpu_dm_connector(connector);
167 struct drm_dp_mst_port *port = amdgpu_dm_connector->port;
169 drm_dp_mst_connector_early_unregister(connector, port);
172 static const struct drm_connector_funcs dm_dp_mst_connector_funcs = {
173 .fill_modes = drm_helper_probe_single_connector_modes,
174 .destroy = dm_dp_mst_connector_destroy,
175 .reset = amdgpu_dm_connector_funcs_reset,
176 .atomic_duplicate_state = amdgpu_dm_connector_atomic_duplicate_state,
177 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
178 .atomic_set_property = amdgpu_dm_connector_atomic_set_property,
179 .atomic_get_property = amdgpu_dm_connector_atomic_get_property,
180 .late_register = amdgpu_dm_mst_connector_late_register,
181 .early_unregister = amdgpu_dm_mst_connector_early_unregister,
184 static bool validate_dsc_caps_on_connector(struct amdgpu_dm_connector *aconnector)
186 struct dc_sink *dc_sink = aconnector->dc_sink;
187 struct drm_dp_mst_port *port = aconnector->port;
188 u8 dsc_caps[16] = { 0 };
190 aconnector->dsc_aux = drm_dp_mst_dsc_aux_for_port(port);
192 if (!aconnector->dsc_aux)
195 if (drm_dp_dpcd_read(aconnector->dsc_aux, DP_DSC_SUPPORT, dsc_caps, 16) < 0)
198 if (!dc_dsc_parse_dsc_dpcd(aconnector->dc_link->ctx->dc,
200 &dc_sink->sink_dsc_caps.dsc_dec_caps))
206 static int dm_dp_mst_get_modes(struct drm_connector *connector)
208 struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
212 return drm_add_edid_modes(connector, NULL);
214 if (!aconnector->edid) {
216 edid = drm_dp_mst_get_edid(connector, &aconnector->mst_port->mst_mgr, aconnector->port);
219 drm_connector_update_edid_property(
225 aconnector->edid = edid;
228 if (aconnector->dc_sink && aconnector->dc_sink->sink_signal == SIGNAL_TYPE_VIRTUAL) {
229 dc_sink_release(aconnector->dc_sink);
230 aconnector->dc_sink = NULL;
233 if (!aconnector->dc_sink) {
234 struct dc_sink *dc_sink;
235 struct dc_sink_init_data init_params = {
236 .link = aconnector->dc_link,
237 .sink_signal = SIGNAL_TYPE_DISPLAY_PORT_MST };
238 dc_sink = dc_link_add_remote_sink(
240 (uint8_t *)aconnector->edid,
241 (aconnector->edid->extensions + 1) * EDID_LENGTH,
244 dc_sink->priv = aconnector;
245 /* dc_link_add_remote_sink returns a new reference */
246 aconnector->dc_sink = dc_sink;
248 if (aconnector->dc_sink) {
249 amdgpu_dm_update_freesync_caps(
250 connector, aconnector->edid);
252 if (!validate_dsc_caps_on_connector(aconnector))
253 memset(&aconnector->dc_sink->sink_dsc_caps,
254 0, sizeof(aconnector->dc_sink->sink_dsc_caps));
258 drm_connector_update_edid_property(
259 &aconnector->base, aconnector->edid);
261 ret = drm_add_edid_modes(connector, aconnector->edid);
266 static struct drm_encoder *
267 dm_mst_atomic_best_encoder(struct drm_connector *connector,
268 struct drm_connector_state *connector_state)
270 return &to_amdgpu_dm_connector(connector)->mst_encoder->base;
274 dm_dp_mst_detect(struct drm_connector *connector,
275 struct drm_modeset_acquire_ctx *ctx, bool force)
277 struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
278 struct amdgpu_dm_connector *master = aconnector->mst_port;
280 return drm_dp_mst_detect_port(connector, ctx, &master->mst_mgr,
284 static int dm_dp_mst_atomic_check(struct drm_connector *connector,
285 struct drm_atomic_state *state)
287 struct drm_connector_state *new_conn_state =
288 drm_atomic_get_new_connector_state(state, connector);
289 struct drm_connector_state *old_conn_state =
290 drm_atomic_get_old_connector_state(state, connector);
291 struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
292 struct drm_crtc_state *new_crtc_state;
293 struct drm_dp_mst_topology_mgr *mst_mgr;
294 struct drm_dp_mst_port *mst_port;
296 mst_port = aconnector->port;
297 mst_mgr = &aconnector->mst_port->mst_mgr;
299 if (!old_conn_state->crtc)
302 if (new_conn_state->crtc) {
303 new_crtc_state = drm_atomic_get_new_crtc_state(state, new_conn_state->crtc);
304 if (!new_crtc_state ||
305 !drm_atomic_crtc_needs_modeset(new_crtc_state) ||
306 new_crtc_state->enable)
310 return drm_dp_atomic_release_vcpi_slots(state,
315 static const struct drm_connector_helper_funcs dm_dp_mst_connector_helper_funcs = {
316 .get_modes = dm_dp_mst_get_modes,
317 .mode_valid = amdgpu_dm_connector_mode_valid,
318 .atomic_best_encoder = dm_mst_atomic_best_encoder,
319 .detect_ctx = dm_dp_mst_detect,
320 .atomic_check = dm_dp_mst_atomic_check,
323 static void amdgpu_dm_encoder_destroy(struct drm_encoder *encoder)
325 drm_encoder_cleanup(encoder);
329 static const struct drm_encoder_funcs amdgpu_dm_encoder_funcs = {
330 .destroy = amdgpu_dm_encoder_destroy,
333 static struct amdgpu_encoder *
334 dm_dp_create_fake_mst_encoder(struct amdgpu_dm_connector *connector)
336 struct drm_device *dev = connector->base.dev;
337 struct amdgpu_device *adev = dev->dev_private;
338 struct amdgpu_encoder *amdgpu_encoder;
339 struct drm_encoder *encoder;
341 amdgpu_encoder = kzalloc(sizeof(*amdgpu_encoder), GFP_KERNEL);
345 encoder = &amdgpu_encoder->base;
346 encoder->possible_crtcs = amdgpu_dm_get_encoder_crtc_mask(adev);
350 &amdgpu_encoder->base,
351 &amdgpu_dm_encoder_funcs,
352 DRM_MODE_ENCODER_DPMST,
355 drm_encoder_helper_add(encoder, &amdgpu_dm_encoder_helper_funcs);
357 return amdgpu_encoder;
360 static struct drm_connector *
361 dm_dp_add_mst_connector(struct drm_dp_mst_topology_mgr *mgr,
362 struct drm_dp_mst_port *port,
363 const char *pathprop)
365 struct amdgpu_dm_connector *master = container_of(mgr, struct amdgpu_dm_connector, mst_mgr);
366 struct drm_device *dev = master->base.dev;
367 struct amdgpu_device *adev = dev->dev_private;
368 struct amdgpu_dm_connector *aconnector;
369 struct drm_connector *connector;
371 aconnector = kzalloc(sizeof(*aconnector), GFP_KERNEL);
375 connector = &aconnector->base;
376 aconnector->port = port;
377 aconnector->mst_port = master;
379 if (drm_connector_init(
382 &dm_dp_mst_connector_funcs,
383 DRM_MODE_CONNECTOR_DisplayPort)) {
387 drm_connector_helper_add(connector, &dm_dp_mst_connector_helper_funcs);
389 amdgpu_dm_connector_init_helper(
392 DRM_MODE_CONNECTOR_DisplayPort,
394 master->connector_id);
396 aconnector->mst_encoder = dm_dp_create_fake_mst_encoder(master);
397 drm_connector_attach_encoder(&aconnector->base,
398 &aconnector->mst_encoder->base);
400 drm_object_attach_property(
402 dev->mode_config.path_property,
404 drm_object_attach_property(
406 dev->mode_config.tile_property,
409 drm_connector_set_path_property(connector, pathprop);
412 * Initialize connector state before adding the connectror to drm and
415 amdgpu_dm_connector_funcs_reset(connector);
417 DRM_INFO("DM_MST: added connector: %p [id: %d] [master: %p]\n",
418 aconnector, connector->base.id, aconnector->mst_port);
420 drm_dp_mst_get_port_malloc(port);
422 DRM_DEBUG_KMS(":%d\n", connector->base.id);
427 static void dm_dp_destroy_mst_connector(struct drm_dp_mst_topology_mgr *mgr,
428 struct drm_connector *connector)
430 struct amdgpu_dm_connector *master = container_of(mgr, struct amdgpu_dm_connector, mst_mgr);
431 struct drm_device *dev = master->base.dev;
432 struct amdgpu_device *adev = dev->dev_private;
433 struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
435 DRM_INFO("DM_MST: Disabling connector: %p [id: %d] [master: %p]\n",
436 aconnector, connector->base.id, aconnector->mst_port);
438 if (aconnector->dc_sink) {
439 amdgpu_dm_update_freesync_caps(connector, NULL);
440 dc_link_remove_remote_sink(aconnector->dc_link,
441 aconnector->dc_sink);
442 dc_sink_release(aconnector->dc_sink);
443 aconnector->dc_sink = NULL;
446 drm_connector_unregister(connector);
447 if (adev->mode_info.rfbdev)
448 drm_fb_helper_remove_one_connector(&adev->mode_info.rfbdev->helper, connector);
449 drm_connector_put(connector);
452 static void dm_dp_mst_register_connector(struct drm_connector *connector)
454 struct drm_device *dev = connector->dev;
455 struct amdgpu_device *adev = dev->dev_private;
457 if (adev->mode_info.rfbdev)
458 drm_fb_helper_add_one_connector(&adev->mode_info.rfbdev->helper, connector);
460 DRM_ERROR("adev->mode_info.rfbdev is NULL\n");
462 drm_connector_register(connector);
465 static const struct drm_dp_mst_topology_cbs dm_mst_cbs = {
466 .add_connector = dm_dp_add_mst_connector,
467 .destroy_connector = dm_dp_destroy_mst_connector,
468 .register_connector = dm_dp_mst_register_connector
471 void amdgpu_dm_initialize_dp_connector(struct amdgpu_display_manager *dm,
472 struct amdgpu_dm_connector *aconnector)
474 aconnector->dm_dp_aux.aux.name = "dmdc";
475 aconnector->dm_dp_aux.aux.dev = aconnector->base.kdev;
476 aconnector->dm_dp_aux.aux.transfer = dm_dp_aux_transfer;
477 aconnector->dm_dp_aux.ddc_service = aconnector->dc_link->ddc;
479 drm_dp_aux_register(&aconnector->dm_dp_aux.aux);
480 drm_dp_cec_register_connector(&aconnector->dm_dp_aux.aux,
483 if (aconnector->base.connector_type == DRM_MODE_CONNECTOR_eDP)
486 aconnector->mst_mgr.cbs = &dm_mst_cbs;
487 drm_dp_mst_topology_mgr_init(
488 &aconnector->mst_mgr,
490 &aconnector->dm_dp_aux.aux,
493 aconnector->connector_id);