2 * Copyright 2015 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
26 #include <linux/string.h>
27 #include <linux/acpi.h>
30 #include <drm/drm_crtc_helper.h>
31 #include <drm/amdgpu_drm.h>
32 #include "dm_services.h"
34 #include "amdgpu_dm.h"
35 #include "amdgpu_dm_irq.h"
36 #include "amdgpu_pm.h"
38 unsigned long long dm_get_timestamp(struct dc_context *ctx)
40 struct timespec64 time;
42 getrawmonotonic64(&time);
43 return timespec64_to_ns(&time);
46 unsigned long long dm_get_elapse_time_in_ns(struct dc_context *ctx,
47 unsigned long long current_time_stamp,
48 unsigned long long last_time_stamp)
50 return current_time_stamp - last_time_stamp;
53 void dm_perf_trace_timestamp(const char *func_name, unsigned int line)
57 bool dm_write_persistent_data(struct dc_context *ctx,
58 const struct dc_sink *sink,
59 const char *module_name,
63 struct persistent_data_flag *flag)
69 bool dm_read_persistent_data(struct dc_context *ctx,
70 const struct dc_sink *sink,
71 const char *module_name,
75 struct persistent_data_flag *flag)
81 /**** power component interfaces ****/
83 bool dm_pp_apply_display_requirements(
84 const struct dc_context *ctx,
85 const struct dm_pp_display_configuration *pp_display_cfg)
87 struct amdgpu_device *adev = ctx->driver_context;
89 if (adev->pm.dpm_enabled) {
91 memset(&adev->pm.pm_display_cfg, 0,
92 sizeof(adev->pm.pm_display_cfg));
94 adev->pm.pm_display_cfg.cpu_cc6_disable =
95 pp_display_cfg->cpu_cc6_disable;
97 adev->pm.pm_display_cfg.cpu_pstate_disable =
98 pp_display_cfg->cpu_pstate_disable;
100 adev->pm.pm_display_cfg.cpu_pstate_separation_time =
101 pp_display_cfg->cpu_pstate_separation_time;
103 adev->pm.pm_display_cfg.nb_pstate_switch_disable =
104 pp_display_cfg->nb_pstate_switch_disable;
106 adev->pm.pm_display_cfg.num_display =
107 pp_display_cfg->display_count;
108 adev->pm.pm_display_cfg.num_path_including_non_display =
109 pp_display_cfg->display_count;
111 adev->pm.pm_display_cfg.min_core_set_clock =
112 pp_display_cfg->min_engine_clock_khz/10;
113 adev->pm.pm_display_cfg.min_core_set_clock_in_sr =
114 pp_display_cfg->min_engine_clock_deep_sleep_khz/10;
115 adev->pm.pm_display_cfg.min_mem_set_clock =
116 pp_display_cfg->min_memory_clock_khz/10;
118 adev->pm.pm_display_cfg.multi_monitor_in_sync =
119 pp_display_cfg->all_displays_in_sync;
120 adev->pm.pm_display_cfg.min_vblank_time =
121 pp_display_cfg->avail_mclk_switch_time_us;
123 adev->pm.pm_display_cfg.display_clk =
124 pp_display_cfg->disp_clk_khz/10;
126 adev->pm.pm_display_cfg.dce_tolerable_mclk_in_active_latency =
127 pp_display_cfg->avail_mclk_switch_time_in_disp_active_us;
129 adev->pm.pm_display_cfg.crtc_index = pp_display_cfg->crtc_index;
130 adev->pm.pm_display_cfg.line_time_in_us =
131 pp_display_cfg->line_time_in_us;
133 adev->pm.pm_display_cfg.vrefresh = pp_display_cfg->disp_configs[0].v_refresh;
134 adev->pm.pm_display_cfg.crossfire_display_index = -1;
135 adev->pm.pm_display_cfg.min_bus_bandwidth = 0;
137 /* TODO: complete implementation of
138 * pp_display_configuration_change().
140 * PHM_StoreDALConfigurationData - powerplay\hwmgr\hardwaremanager.c
141 * PP_IRI_DisplayConfigurationChange - powerplay\eventmgr\iri.c */
142 if (adev->powerplay.pp_funcs->display_configuration_change)
143 adev->powerplay.pp_funcs->display_configuration_change(
144 adev->powerplay.pp_handle,
145 &adev->pm.pm_display_cfg);
147 /* TODO: replace by a separate call to 'apply display cfg'? */
148 amdgpu_pm_compute_clocks(adev);
154 static void get_default_clock_levels(
155 enum dm_pp_clock_type clk_type,
156 struct dm_pp_clock_levels *clks)
158 uint32_t disp_clks_in_khz[6] = {
159 300000, 400000, 496560, 626090, 685720, 757900 };
160 uint32_t sclks_in_khz[6] = {
161 300000, 360000, 423530, 514290, 626090, 720000 };
162 uint32_t mclks_in_khz[2] = { 333000, 800000 };
165 case DM_PP_CLOCK_TYPE_DISPLAY_CLK:
166 clks->num_levels = 6;
167 memmove(clks->clocks_in_khz, disp_clks_in_khz,
168 sizeof(disp_clks_in_khz));
170 case DM_PP_CLOCK_TYPE_ENGINE_CLK:
171 clks->num_levels = 6;
172 memmove(clks->clocks_in_khz, sclks_in_khz,
173 sizeof(sclks_in_khz));
175 case DM_PP_CLOCK_TYPE_MEMORY_CLK:
176 clks->num_levels = 2;
177 memmove(clks->clocks_in_khz, mclks_in_khz,
178 sizeof(mclks_in_khz));
181 clks->num_levels = 0;
186 static enum amd_pp_clock_type dc_to_pp_clock_type(
187 enum dm_pp_clock_type dm_pp_clk_type)
189 enum amd_pp_clock_type amd_pp_clk_type = 0;
191 switch (dm_pp_clk_type) {
192 case DM_PP_CLOCK_TYPE_DISPLAY_CLK:
193 amd_pp_clk_type = amd_pp_disp_clock;
195 case DM_PP_CLOCK_TYPE_ENGINE_CLK:
196 amd_pp_clk_type = amd_pp_sys_clock;
198 case DM_PP_CLOCK_TYPE_MEMORY_CLK:
199 amd_pp_clk_type = amd_pp_mem_clock;
202 DRM_ERROR("DM_PPLIB: invalid clock type: %d!\n",
207 return amd_pp_clk_type;
210 static void pp_to_dc_clock_levels(
211 const struct amd_pp_clocks *pp_clks,
212 struct dm_pp_clock_levels *dc_clks,
213 enum dm_pp_clock_type dc_clk_type)
217 if (pp_clks->count > DM_PP_MAX_CLOCK_LEVELS) {
218 DRM_INFO("DM_PPLIB: Warning: %s clock: number of levels %d exceeds maximum of %d!\n",
219 DC_DECODE_PP_CLOCK_TYPE(dc_clk_type),
221 DM_PP_MAX_CLOCK_LEVELS);
223 dc_clks->num_levels = DM_PP_MAX_CLOCK_LEVELS;
225 dc_clks->num_levels = pp_clks->count;
227 DRM_INFO("DM_PPLIB: values for %s clock\n",
228 DC_DECODE_PP_CLOCK_TYPE(dc_clk_type));
230 for (i = 0; i < dc_clks->num_levels; i++) {
231 DRM_INFO("DM_PPLIB:\t %d\n", pp_clks->clock[i]);
232 /* translate 10kHz to kHz */
233 dc_clks->clocks_in_khz[i] = pp_clks->clock[i] * 10;
237 static void pp_to_dc_clock_levels_with_latency(
238 const struct pp_clock_levels_with_latency *pp_clks,
239 struct dm_pp_clock_levels_with_latency *clk_level_info,
240 enum dm_pp_clock_type dc_clk_type)
244 if (pp_clks->num_levels > DM_PP_MAX_CLOCK_LEVELS) {
245 DRM_INFO("DM_PPLIB: Warning: %s clock: number of levels %d exceeds maximum of %d!\n",
246 DC_DECODE_PP_CLOCK_TYPE(dc_clk_type),
248 DM_PP_MAX_CLOCK_LEVELS);
250 clk_level_info->num_levels = DM_PP_MAX_CLOCK_LEVELS;
252 clk_level_info->num_levels = pp_clks->num_levels;
254 DRM_DEBUG("DM_PPLIB: values for %s clock\n",
255 DC_DECODE_PP_CLOCK_TYPE(dc_clk_type));
257 for (i = 0; i < clk_level_info->num_levels; i++) {
258 DRM_DEBUG("DM_PPLIB:\t %d\n", pp_clks->data[i].clocks_in_khz);
259 clk_level_info->data[i].clocks_in_khz = pp_clks->data[i].clocks_in_khz;
260 clk_level_info->data[i].latency_in_us = pp_clks->data[i].latency_in_us;
264 bool dm_pp_get_clock_levels_by_type(
265 const struct dc_context *ctx,
266 enum dm_pp_clock_type clk_type,
267 struct dm_pp_clock_levels *dc_clks)
269 struct amdgpu_device *adev = ctx->driver_context;
270 void *pp_handle = adev->powerplay.pp_handle;
271 struct amd_pp_clocks pp_clks = { 0 };
272 struct amd_pp_simple_clock_info validation_clks = { 0 };
275 if (adev->powerplay.pp_funcs->get_clock_by_type) {
276 if (adev->powerplay.pp_funcs->get_clock_by_type(pp_handle,
277 dc_to_pp_clock_type(clk_type), &pp_clks)) {
278 /* Error in pplib. Provide default values. */
279 get_default_clock_levels(clk_type, dc_clks);
284 pp_to_dc_clock_levels(&pp_clks, dc_clks, clk_type);
286 if (adev->powerplay.pp_funcs->get_display_mode_validation_clocks) {
287 if (adev->powerplay.pp_funcs->get_display_mode_validation_clocks(
288 pp_handle, &validation_clks)) {
289 /* Error in pplib. Provide default values. */
290 DRM_INFO("DM_PPLIB: Warning: using default validation clocks!\n");
291 validation_clks.engine_max_clock = 72000;
292 validation_clks.memory_max_clock = 80000;
293 validation_clks.level = 0;
297 DRM_INFO("DM_PPLIB: Validation clocks:\n");
298 DRM_INFO("DM_PPLIB: engine_max_clock: %d\n",
299 validation_clks.engine_max_clock);
300 DRM_INFO("DM_PPLIB: memory_max_clock: %d\n",
301 validation_clks.memory_max_clock);
302 DRM_INFO("DM_PPLIB: level : %d\n",
303 validation_clks.level);
305 /* Translate 10 kHz to kHz. */
306 validation_clks.engine_max_clock *= 10;
307 validation_clks.memory_max_clock *= 10;
309 /* Determine the highest non-boosted level from the Validation Clocks */
310 if (clk_type == DM_PP_CLOCK_TYPE_ENGINE_CLK) {
311 for (i = 0; i < dc_clks->num_levels; i++) {
312 if (dc_clks->clocks_in_khz[i] > validation_clks.engine_max_clock) {
313 /* This clock is higher the validation clock.
314 * Than means the previous one is the highest
315 * non-boosted one. */
316 DRM_INFO("DM_PPLIB: reducing engine clock level from %d to %d\n",
317 dc_clks->num_levels, i);
318 dc_clks->num_levels = i > 0 ? i : 1;
322 } else if (clk_type == DM_PP_CLOCK_TYPE_MEMORY_CLK) {
323 for (i = 0; i < dc_clks->num_levels; i++) {
324 if (dc_clks->clocks_in_khz[i] > validation_clks.memory_max_clock) {
325 DRM_INFO("DM_PPLIB: reducing memory clock level from %d to %d\n",
326 dc_clks->num_levels, i);
327 dc_clks->num_levels = i > 0 ? i : 1;
336 bool dm_pp_get_clock_levels_by_type_with_latency(
337 const struct dc_context *ctx,
338 enum dm_pp_clock_type clk_type,
339 struct dm_pp_clock_levels_with_latency *clk_level_info)
341 struct amdgpu_device *adev = ctx->driver_context;
342 void *pp_handle = adev->powerplay.pp_handle;
343 struct pp_clock_levels_with_latency pp_clks = { 0 };
344 const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs;
346 if (!pp_funcs || !pp_funcs->get_clock_by_type_with_latency)
349 if (pp_funcs->get_clock_by_type_with_latency(pp_handle,
350 dc_to_pp_clock_type(clk_type),
354 pp_to_dc_clock_levels_with_latency(&pp_clks, clk_level_info, clk_type);
359 bool dm_pp_get_clock_levels_by_type_with_voltage(
360 const struct dc_context *ctx,
361 enum dm_pp_clock_type clk_type,
362 struct dm_pp_clock_levels_with_voltage *clk_level_info)
364 /* TODO: to be implemented */
368 bool dm_pp_notify_wm_clock_changes(
369 const struct dc_context *ctx,
370 struct dm_pp_wm_sets_with_clock_ranges *wm_with_clock_ranges)
372 /* TODO: to be implemented */
376 bool dm_pp_apply_power_level_change_request(
377 const struct dc_context *ctx,
378 struct dm_pp_power_level_change_request *level_change_req)
380 /* TODO: to be implemented */
384 bool dm_pp_apply_clock_for_voltage_request(
385 const struct dc_context *ctx,
386 struct dm_pp_clock_for_voltage_req *clock_for_voltage_req)
388 /* TODO: to be implemented */
392 bool dm_pp_get_static_clocks(
393 const struct dc_context *ctx,
394 struct dm_pp_static_clock_info *static_clk_info)
396 /* TODO: to be implemented */
400 void dm_pp_get_funcs_rv(
401 struct dc_context *ctx,
402 struct pp_smu_funcs_rv *funcs)
405 /**** end of power component interfaces ****/