drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c

   1 /*
   2  * Copyright 2017 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: AMD
  23  *
  24  */
  25
  26 #include "dm_services.h"
  27 #include "dcn_calcs.h"
  28 #include "dcn_calc_auto.h"
  29 #include "dc.h"
  30 #include "dal_asic_id.h"
  31
  32 #include "resource.h"
  33 #include "dcn10/dcn10_resource.h"
  34 #include "dcn_calc_math.h"
  35
  36 #define DC_LOGGER \
  37         dc->ctx->logger
  38 /*
  39  * NOTE:
  40  *   This file is gcc-parseable HW gospel, coming straight from HW engineers.
  41  *
  42  * It doesn't adhere to Linux kernel style and sometimes will do things in odd
  43  * ways. Unless there is something clearly wrong with it the code should
  44  * remain as-is as it provides us with a guarantee from HW that it is correct.
  45  */
  46
  47 /* Defaults from spreadsheet rev#247 */
  48 const struct dcn_soc_bounding_box dcn10_soc_defaults = {
  49                 /* latencies */
  50                 .sr_exit_time = 17, /*us*/
  51                 .sr_enter_plus_exit_time = 19, /*us*/
  52                 .urgent_latency = 4, /*us*/
  53                 .dram_clock_change_latency = 17, /*us*/
  54                 .write_back_latency = 12, /*us*/
  55                 .percent_of_ideal_drambw_received_after_urg_latency = 80, /*%*/
  56
  57                 /* below default clocks derived from STA target base on
  58                  * slow-slow corner + 10% margin with voltages aligned to FCLK.
  59                  *
  60                  * Use these value if fused value doesn't make sense as earlier
  61                  * part don't have correct value fused */
  62                 /* default DCF CLK DPM on RV*/
  63                 .dcfclkv_max0p9 = 655,  /* MHz, = 3600/5.5 */
  64                 .dcfclkv_nom0p8 = 626,  /* MHz, = 3600/5.75 */
  65                 .dcfclkv_mid0p72 = 600, /* MHz, = 3600/6, bypass */
  66                 .dcfclkv_min0p65 = 300, /* MHz, = 3600/12, bypass */
  67
  68                 /* default DISP CLK voltage state on RV */
  69                 .max_dispclk_vmax0p9 = 1108,    /* MHz, = 3600/3.25 */
  70                 .max_dispclk_vnom0p8 = 1029,    /* MHz, = 3600/3.5 */
  71                 .max_dispclk_vmid0p72 = 960,    /* MHz, = 3600/3.75 */
  72                 .max_dispclk_vmin0p65 = 626,    /* MHz, = 3600/5.75 */
  73
  74                 /* default DPP CLK voltage state on RV */
  75                 .max_dppclk_vmax0p9 = 720,      /* MHz, = 3600/5 */
  76                 .max_dppclk_vnom0p8 = 686,      /* MHz, = 3600/5.25 */
  77                 .max_dppclk_vmid0p72 = 626,     /* MHz, = 3600/5.75 */
  78                 .max_dppclk_vmin0p65 = 400,     /* MHz, = 3600/9 */
  79
  80                 /* default PHY CLK voltage state on RV */
  81                 .phyclkv_max0p9 = 900, /*MHz*/
  82                 .phyclkv_nom0p8 = 847, /*MHz*/
  83                 .phyclkv_mid0p72 = 800, /*MHz*/
  84                 .phyclkv_min0p65 = 600, /*MHz*/
  85
  86                 /* BW depend on FCLK, MCLK, # of channels */
  87                 /* dual channel BW */
  88                 .fabric_and_dram_bandwidth_vmax0p9 = 38.4f, /*GB/s*/
  89                 .fabric_and_dram_bandwidth_vnom0p8 = 34.133f, /*GB/s*/
  90                 .fabric_and_dram_bandwidth_vmid0p72 = 29.866f, /*GB/s*/
  91                 .fabric_and_dram_bandwidth_vmin0p65 = 12.8f, /*GB/s*/
  92                 /* single channel BW
  93                 .fabric_and_dram_bandwidth_vmax0p9 = 19.2f,
  94                 .fabric_and_dram_bandwidth_vnom0p8 = 17.066f,
  95                 .fabric_and_dram_bandwidth_vmid0p72 = 14.933f,
  96                 .fabric_and_dram_bandwidth_vmin0p65 = 12.8f,
  97                 */
  98
  99                 .number_of_channels = 2,
 100
 101                 .socclk = 208, /*MHz*/
 102                 .downspreading = 0.5f, /*%*/
 103                 .round_trip_ping_latency_cycles = 128, /*DCFCLK Cycles*/
 104                 .urgent_out_of_order_return_per_channel = 256, /*bytes*/
 105                 .vmm_page_size = 4096, /*bytes*/
 106                 .return_bus_width = 64, /*bytes*/
 107                 .max_request_size = 256, /*bytes*/
 108
 109                 /* Depends on user class (client vs embedded, workstation, etc) */
 110                 .percent_disp_bw_limit = 0.3f /*%*/
 111 };
 112
 113 const struct dcn_ip_params dcn10_ip_defaults = {
 114                 .rob_buffer_size_in_kbyte = 64,
 115                 .det_buffer_size_in_kbyte = 164,
 116                 .dpp_output_buffer_pixels = 2560,
 117                 .opp_output_buffer_lines = 1,
 118                 .pixel_chunk_size_in_kbyte = 8,
 119                 .pte_enable = dcn_bw_yes,
 120                 .pte_chunk_size = 2, /*kbytes*/
 121                 .meta_chunk_size = 2, /*kbytes*/
 122                 .writeback_chunk_size = 2, /*kbytes*/
 123                 .odm_capability = dcn_bw_no,
 124                 .dsc_capability = dcn_bw_no,
 125                 .line_buffer_size = 589824, /*bit*/
 126                 .max_line_buffer_lines = 12,
 127                 .is_line_buffer_bpp_fixed = dcn_bw_no,
 128                 .line_buffer_fixed_bpp = dcn_bw_na,
 129                 .writeback_luma_buffer_size = 12, /*kbytes*/
 130                 .writeback_chroma_buffer_size = 8, /*kbytes*/
 131                 .max_num_dpp = 4,
 132                 .max_num_writeback = 2,
 133                 .max_dchub_topscl_throughput = 4, /*pixels/dppclk*/
 134                 .max_pscl_tolb_throughput = 2, /*pixels/dppclk*/
 135                 .max_lb_tovscl_throughput = 4, /*pixels/dppclk*/
 136                 .max_vscl_tohscl_throughput = 4, /*pixels/dppclk*/
 137                 .max_hscl_ratio = 4,
 138                 .max_vscl_ratio = 4,
 139                 .max_hscl_taps = 8,
 140                 .max_vscl_taps = 8,
 141                 .pte_buffer_size_in_requests = 42,
 142                 .dispclk_ramping_margin = 1, /*%*/
 143                 .under_scan_factor = 1.11f,
 144                 .max_inter_dcn_tile_repeaters = 8,
 145                 .can_vstartup_lines_exceed_vsync_plus_back_porch_lines_minus_one = dcn_bw_no,
 146                 .bug_forcing_luma_and_chroma_request_to_same_size_fixed = dcn_bw_no,
 147                 .dcfclk_cstate_latency = 10 /*TODO clone of something else? sr_enter_plus_exit_time?*/
 148 };
 149
 150 static enum dcn_bw_defs tl_sw_mode_to_bw_defs(enum swizzle_mode_values sw_mode)
 151 {
 152         switch (sw_mode) {
 153         case DC_SW_LINEAR:
 154                 return dcn_bw_sw_linear;
 155         case DC_SW_4KB_S:
 156                 return dcn_bw_sw_4_kb_s;
 157         case DC_SW_4KB_D:
 158                 return dcn_bw_sw_4_kb_d;
 159         case DC_SW_64KB_S:
 160                 return dcn_bw_sw_64_kb_s;
 161         case DC_SW_64KB_D:
 162                 return dcn_bw_sw_64_kb_d;
 163         case DC_SW_VAR_S:
 164                 return dcn_bw_sw_var_s;
 165         case DC_SW_VAR_D:
 166                 return dcn_bw_sw_var_d;
 167         case DC_SW_64KB_S_T:
 168                 return dcn_bw_sw_64_kb_s_t;
 169         case DC_SW_64KB_D_T:
 170                 return dcn_bw_sw_64_kb_d_t;
 171         case DC_SW_4KB_S_X:
 172                 return dcn_bw_sw_4_kb_s_x;
 173         case DC_SW_4KB_D_X:
 174                 return dcn_bw_sw_4_kb_d_x;
 175         case DC_SW_64KB_S_X:
 176                 return dcn_bw_sw_64_kb_s_x;
 177         case DC_SW_64KB_D_X:
 178                 return dcn_bw_sw_64_kb_d_x;
 179         case DC_SW_VAR_S_X:
 180                 return dcn_bw_sw_var_s_x;
 181         case DC_SW_VAR_D_X:
 182                 return dcn_bw_sw_var_d_x;
 183         case DC_SW_256B_S:
 184         case DC_SW_256_D:
 185         case DC_SW_256_R:
 186         case DC_SW_4KB_R:
 187         case DC_SW_64KB_R:
 188         case DC_SW_VAR_R:
 189         case DC_SW_4KB_R_X:
 190         case DC_SW_64KB_R_X:
 191         case DC_SW_VAR_R_X:
 192         default:
 193                 BREAK_TO_DEBUGGER(); /*not in formula*/
 194                 return dcn_bw_sw_4_kb_s;
 195         }
 196 }
 197
 198 static int tl_lb_bpp_to_int(enum lb_pixel_depth depth)
 199 {
 200         switch (depth) {
 201         case LB_PIXEL_DEPTH_18BPP:
 202                 return 18;
 203         case LB_PIXEL_DEPTH_24BPP:
 204                 return 24;
 205         case LB_PIXEL_DEPTH_30BPP:
 206                 return 30;
 207         case LB_PIXEL_DEPTH_36BPP:
 208                 return 36;
 209         default:
 210                 return 30;
 211         }
 212 }
 213
 214 static enum dcn_bw_defs tl_pixel_format_to_bw_defs(enum surface_pixel_format format)
 215 {
 216         switch (format) {
 217         case SURFACE_PIXEL_FORMAT_GRPH_ARGB1555:
 218         case SURFACE_PIXEL_FORMAT_GRPH_RGB565:
 219                 return dcn_bw_rgb_sub_16;
 220         case SURFACE_PIXEL_FORMAT_GRPH_ARGB8888:
 221         case SURFACE_PIXEL_FORMAT_GRPH_ABGR8888:
 222         case SURFACE_PIXEL_FORMAT_GRPH_ARGB2101010:
 223         case SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010:
 224         case SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010_XR_BIAS:
 225                 return dcn_bw_rgb_sub_32;
 226         case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616:
 227         case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616F:
 228         case SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616F:
 229                 return dcn_bw_rgb_sub_64;
 230         case SURFACE_PIXEL_FORMAT_VIDEO_420_YCbCr:
 231         case SURFACE_PIXEL_FORMAT_VIDEO_420_YCrCb:
 232                 return dcn_bw_yuv420_sub_8;
 233         case SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCbCr:
 234         case SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCrCb:
 235                 return dcn_bw_yuv420_sub_10;
 236         default:
 237                 return dcn_bw_rgb_sub_32;
 238         }
 239 }
 240
 241 static void pipe_ctx_to_e2e_pipe_params (
 242                 const struct pipe_ctx *pipe,
 243                 struct _vcs_dpi_display_pipe_params_st *input)
 244 {
 245         input->src.is_hsplit = false;
 246         if (pipe->top_pipe != NULL && pipe->top_pipe->plane_state == pipe->plane_state)
 247                 input->src.is_hsplit = true;
 248         else if (pipe->bottom_pipe != NULL && pipe->bottom_pipe->plane_state == pipe->plane_state)
 249                 input->src.is_hsplit = true;
 250
 251         input->src.dcc                 = pipe->plane_state->dcc.enable;
 252         input->src.dcc_rate            = 1;
 253         input->src.meta_pitch          = pipe->plane_state->dcc.grph.meta_pitch;
 254         input->src.source_scan         = dm_horz;
 255         input->src.sw_mode             = pipe->plane_state->tiling_info.gfx9.swizzle;
 256
 257         input->src.viewport_width      = pipe->plane_res.scl_data.viewport.width;
 258         input->src.viewport_height     = pipe->plane_res.scl_data.viewport.height;
 259         input->src.data_pitch          = pipe->plane_res.scl_data.viewport.width;
 260         input->src.data_pitch_c        = pipe->plane_res.scl_data.viewport.width;
 261         input->src.cur0_src_width      = 128; /* TODO: Cursor calcs, not curently stored */
 262         input->src.cur0_bpp            = 32;
 263
 264         switch (pipe->plane_state->tiling_info.gfx9.swizzle) {
 265         /* for 4/8/16 high tiles */
 266         case DC_SW_LINEAR:
 267                 input->src.is_display_sw = 1;
 268                 input->src.macro_tile_size = dm_4k_tile;
 269                 break;
 270         case DC_SW_4KB_S:
 271         case DC_SW_4KB_S_X:
 272                 input->src.is_display_sw = 0;
 273                 input->src.macro_tile_size = dm_4k_tile;
 274                 break;
 275         case DC_SW_64KB_S:
 276         case DC_SW_64KB_S_X:
 277         case DC_SW_64KB_S_T:
 278                 input->src.is_display_sw = 0;
 279                 input->src.macro_tile_size = dm_64k_tile;
 280                 break;
 281         case DC_SW_VAR_S:
 282         case DC_SW_VAR_S_X:
 283                 input->src.is_display_sw = 0;
 284                 input->src.macro_tile_size = dm_256k_tile;
 285                 break;
 286
 287         /* For 64bpp 2 high tiles */
 288         case DC_SW_4KB_D:
 289         case DC_SW_4KB_D_X:
 290                 input->src.is_display_sw = 1;
 291                 input->src.macro_tile_size = dm_4k_tile;
 292                 break;
 293         case DC_SW_64KB_D:
 294         case DC_SW_64KB_D_X:
 295         case DC_SW_64KB_D_T:
 296                 input->src.is_display_sw = 1;
 297                 input->src.macro_tile_size = dm_64k_tile;
 298                 break;
 299         case DC_SW_VAR_D:
 300         case DC_SW_VAR_D_X:
 301                 input->src.is_display_sw = 1;
 302                 input->src.macro_tile_size = dm_256k_tile;
 303                 break;
 304
 305         /* Unsupported swizzle modes for dcn */
 306         case DC_SW_256B_S:
 307         default:
 308                 ASSERT(0); /* Not supported */
 309                 break;
 310         }
 311
 312         switch (pipe->plane_state->rotation) {
 313         case ROTATION_ANGLE_0:
 314         case ROTATION_ANGLE_180:
 315                 input->src.source_scan = dm_horz;
 316                 break;
 317         case ROTATION_ANGLE_90:
 318         case ROTATION_ANGLE_270:
 319                 input->src.source_scan = dm_vert;
 320                 break;
 321         default:
 322                 ASSERT(0); /* Not supported */
 323                 break;
 324         }
 325
 326         /* TODO: Fix pixel format mappings */
 327         switch (pipe->plane_state->format) {
 328         case SURFACE_PIXEL_FORMAT_VIDEO_420_YCbCr:
 329         case SURFACE_PIXEL_FORMAT_VIDEO_420_YCrCb:
 330                 input->src.source_format = dm_420_8;
 331                 input->src.viewport_width_c    = input->src.viewport_width / 2;
 332                 input->src.viewport_height_c   = input->src.viewport_height / 2;
 333                 break;
 334         case SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCbCr:
 335         case SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCrCb:
 336                 input->src.source_format = dm_420_10;
 337                 input->src.viewport_width_c    = input->src.viewport_width / 2;
 338                 input->src.viewport_height_c   = input->src.viewport_height / 2;
 339                 break;
 340         case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616:
 341         case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616F:
 342         case SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616F:
 343                 input->src.source_format = dm_444_64;
 344                 input->src.viewport_width_c    = input->src.viewport_width;
 345                 input->src.viewport_height_c   = input->src.viewport_height;
 346                 break;
 347         default:
 348                 input->src.source_format = dm_444_32;
 349                 input->src.viewport_width_c    = input->src.viewport_width;
 350                 input->src.viewport_height_c   = input->src.viewport_height;
 351                 break;
 352         }
 353
 354         input->scale_taps.htaps                = pipe->plane_res.scl_data.taps.h_taps;
 355         input->scale_ratio_depth.hscl_ratio    = pipe->plane_res.scl_data.ratios.horz.value/4294967296.0;
 356         input->scale_ratio_depth.vscl_ratio    = pipe->plane_res.scl_data.ratios.vert.value/4294967296.0;
 357         input->scale_ratio_depth.vinit =  pipe->plane_res.scl_data.inits.v.value/4294967296.0;
 358         if (input->scale_ratio_depth.vinit < 1.0)
 359                         input->scale_ratio_depth.vinit = 1;
 360         input->scale_taps.vtaps = pipe->plane_res.scl_data.taps.v_taps;
 361         input->scale_taps.vtaps_c = pipe->plane_res.scl_data.taps.v_taps_c;
 362         input->scale_taps.htaps_c              = pipe->plane_res.scl_data.taps.h_taps_c;
 363         input->scale_ratio_depth.hscl_ratio_c  = pipe->plane_res.scl_data.ratios.horz_c.value/4294967296.0;
 364         input->scale_ratio_depth.vscl_ratio_c  = pipe->plane_res.scl_data.ratios.vert_c.value/4294967296.0;
 365         input->scale_ratio_depth.vinit_c       = pipe->plane_res.scl_data.inits.v_c.value/4294967296.0;
 366         if (input->scale_ratio_depth.vinit_c < 1.0)
 367                         input->scale_ratio_depth.vinit_c = 1;
 368         switch (pipe->plane_res.scl_data.lb_params.depth) {
 369         case LB_PIXEL_DEPTH_30BPP:
 370                 input->scale_ratio_depth.lb_depth = 30; break;
 371         case LB_PIXEL_DEPTH_36BPP:
 372                 input->scale_ratio_depth.lb_depth = 36; break;
 373         default:
 374                 input->scale_ratio_depth.lb_depth = 24; break;
 375         }
 376
 377
 378         input->dest.vactive        = pipe->stream->timing.v_addressable + pipe->stream->timing.v_border_top
 379                         + pipe->stream->timing.v_border_bottom;
 380
 381         input->dest.recout_width   = pipe->plane_res.scl_data.recout.width;
 382         input->dest.recout_height  = pipe->plane_res.scl_data.recout.height;
 383
 384         input->dest.full_recout_width   = pipe->plane_res.scl_data.recout.width;
 385         input->dest.full_recout_height  = pipe->plane_res.scl_data.recout.height;
 386
 387         input->dest.htotal         = pipe->stream->timing.h_total;
 388         input->dest.hblank_start   = input->dest.htotal - pipe->stream->timing.h_front_porch;
 389         input->dest.hblank_end     = input->dest.hblank_start
 390                         - pipe->stream->timing.h_addressable
 391                         - pipe->stream->timing.h_border_left
 392                         - pipe->stream->timing.h_border_right;
 393
 394         input->dest.vtotal         = pipe->stream->timing.v_total;
 395         input->dest.vblank_start   = input->dest.vtotal - pipe->stream->timing.v_front_porch;
 396         input->dest.vblank_end     = input->dest.vblank_start
 397                         - pipe->stream->timing.v_addressable
 398                         - pipe->stream->timing.v_border_bottom
 399                         - pipe->stream->timing.v_border_top;
 400         input->dest.pixel_rate_mhz = pipe->stream->timing.pix_clk_khz/1000.0;
 401         input->dest.vstartup_start = pipe->pipe_dlg_param.vstartup_start;
 402         input->dest.vupdate_offset = pipe->pipe_dlg_param.vupdate_offset;
 403         input->dest.vupdate_offset = pipe->pipe_dlg_param.vupdate_offset;
 404         input->dest.vupdate_width = pipe->pipe_dlg_param.vupdate_width;
 405
 406 }
 407
 408 static void dcn_bw_calc_rq_dlg_ttu(
 409                 const struct dc *dc,
 410                 const struct dcn_bw_internal_vars *v,
 411                 struct pipe_ctx *pipe,
 412                 int in_idx)
 413 {
 414         struct display_mode_lib *dml = (struct display_mode_lib *)(&dc->dml);
 415         struct _vcs_dpi_display_dlg_regs_st *dlg_regs = &pipe->dlg_regs;
 416         struct _vcs_dpi_display_ttu_regs_st *ttu_regs = &pipe->ttu_regs;
 417         struct _vcs_dpi_display_rq_regs_st *rq_regs = &pipe->rq_regs;
 418         struct _vcs_dpi_display_rq_params_st rq_param = {0};
 419         struct _vcs_dpi_display_dlg_sys_params_st dlg_sys_param = {0};
 420         struct _vcs_dpi_display_e2e_pipe_params_st input = { { { 0 } } };
 421         float total_active_bw = 0;
 422         float total_prefetch_bw = 0;
 423         int total_flip_bytes = 0;
 424         int i;
 425
 426         for (i = 0; i < number_of_planes; i++) {
 427                 total_active_bw += v->read_bandwidth[i];
 428                 total_prefetch_bw += v->prefetch_bandwidth[i];
 429                 total_flip_bytes += v->total_immediate_flip_bytes[i];
 430         }
 431         dlg_sys_param.total_flip_bw = v->return_bw - dcn_bw_max2(total_active_bw, total_prefetch_bw);
 432         if (dlg_sys_param.total_flip_bw < 0.0)
 433                 dlg_sys_param.total_flip_bw = 0;
 434
 435         dlg_sys_param.t_mclk_wm_us = v->dram_clock_change_watermark;
 436         dlg_sys_param.t_sr_wm_us = v->stutter_enter_plus_exit_watermark;
 437         dlg_sys_param.t_urg_wm_us = v->urgent_watermark;
 438         dlg_sys_param.t_extra_us = v->urgent_extra_latency;
 439         dlg_sys_param.deepsleep_dcfclk_mhz = v->dcf_clk_deep_sleep;
 440         dlg_sys_param.total_flip_bytes = total_flip_bytes;
 441
 442         pipe_ctx_to_e2e_pipe_params(pipe, &input.pipe);
 443         input.clks_cfg.dcfclk_mhz = v->dcfclk;
 444         input.clks_cfg.dispclk_mhz = v->dispclk;
 445         input.clks_cfg.dppclk_mhz = v->dppclk;
 446         input.clks_cfg.refclk_mhz = dc->res_pool->ref_clock_inKhz / 1000.0;
 447         input.clks_cfg.socclk_mhz = v->socclk;
 448         input.clks_cfg.voltage = v->voltage_level;
 449 //      dc->dml.logger = pool->base.logger;
 450         input.dout.output_format = (v->output_format[in_idx] == dcn_bw_420) ? dm_420 : dm_444;
 451         input.dout.output_type  = (v->output[in_idx] == dcn_bw_hdmi) ? dm_hdmi : dm_dp;
 452         //input[in_idx].dout.output_standard;
 453
 454         /*todo: soc->sr_enter_plus_exit_time??*/
 455         dlg_sys_param.t_srx_delay_us = dc->dcn_ip->dcfclk_cstate_latency / v->dcf_clk_deep_sleep;
 456
 457         dml1_rq_dlg_get_rq_params(dml, &rq_param, input.pipe.src);
 458         dml1_extract_rq_regs(dml, rq_regs, rq_param);
 459         dml1_rq_dlg_get_dlg_params(
 460                         dml,
 461                         dlg_regs,
 462                         ttu_regs,
 463                         rq_param.dlg,
 464                         dlg_sys_param,
 465                         input,
 466                         true,
 467                         true,
 468                         v->pte_enable == dcn_bw_yes,
 469                         pipe->plane_state->flip_immediate);
 470 }
 471
 472 static void split_stream_across_pipes(
 473                 struct resource_context *res_ctx,
 474                 const struct resource_pool *pool,
 475                 struct pipe_ctx *primary_pipe,
 476                 struct pipe_ctx *secondary_pipe)
 477 {
 478         int pipe_idx = secondary_pipe->pipe_idx;
 479
 480         if (!primary_pipe->plane_state)
 481                 return;
 482
 483         *secondary_pipe = *primary_pipe;
 484
 485         secondary_pipe->pipe_idx = pipe_idx;
 486         secondary_pipe->plane_res.mi = pool->mis[secondary_pipe->pipe_idx];
 487         secondary_pipe->plane_res.hubp = pool->hubps[secondary_pipe->pipe_idx];
 488         secondary_pipe->plane_res.ipp = pool->ipps[secondary_pipe->pipe_idx];
 489         secondary_pipe->plane_res.xfm = pool->transforms[secondary_pipe->pipe_idx];
 490         secondary_pipe->plane_res.dpp = pool->dpps[secondary_pipe->pipe_idx];
 491         secondary_pipe->plane_res.mpcc_inst = pool->dpps[secondary_pipe->pipe_idx]->inst;
 492         if (primary_pipe->bottom_pipe) {
 493                 ASSERT(primary_pipe->bottom_pipe != secondary_pipe);
 494                 secondary_pipe->bottom_pipe = primary_pipe->bottom_pipe;
 495                 secondary_pipe->bottom_pipe->top_pipe = secondary_pipe;
 496         }
 497         primary_pipe->bottom_pipe = secondary_pipe;
 498         secondary_pipe->top_pipe = primary_pipe;
 499
 500         resource_build_scaling_params(primary_pipe);
 501         resource_build_scaling_params(secondary_pipe);
 502 }
 503
 504 static void calc_wm_sets_and_perf_params(
 505                 struct dc_state *context,
 506                 struct dcn_bw_internal_vars *v)
 507 {
 508         /* Calculate set A last to keep internal var state consistent for required config */
 509         if (v->voltage_level < 2) {
 510                 v->fabric_and_dram_bandwidth_per_state[1] = v->fabric_and_dram_bandwidth_vnom0p8;
 511                 v->fabric_and_dram_bandwidth_per_state[0] = v->fabric_and_dram_bandwidth_vnom0p8;
 512                 v->fabric_and_dram_bandwidth = v->fabric_and_dram_bandwidth_vnom0p8;
 513                 dispclkdppclkdcfclk_deep_sleep_prefetch_parameters_watermarks_and_performance_calculation(v);
 514
 515                 context->bw.dcn.watermarks.b.cstate_pstate.cstate_exit_ns =
 516                         v->stutter_exit_watermark * 1000;
 517                 context->bw.dcn.watermarks.b.cstate_pstate.cstate_enter_plus_exit_ns =
 518                                 v->stutter_enter_plus_exit_watermark * 1000;
 519                 context->bw.dcn.watermarks.b.cstate_pstate.pstate_change_ns =
 520                                 v->dram_clock_change_watermark * 1000;
 521                 context->bw.dcn.watermarks.b.pte_meta_urgent_ns = v->ptemeta_urgent_watermark * 1000;
 522                 context->bw.dcn.watermarks.b.urgent_ns = v->urgent_watermark * 1000;
 523
 524                 v->dcfclk_per_state[1] = v->dcfclkv_nom0p8;
 525                 v->dcfclk_per_state[0] = v->dcfclkv_nom0p8;
 526                 v->dcfclk = v->dcfclkv_nom0p8;
 527                 dispclkdppclkdcfclk_deep_sleep_prefetch_parameters_watermarks_and_performance_calculation(v);
 528
 529                 context->bw.dcn.watermarks.c.cstate_pstate.cstate_exit_ns =
 530                         v->stutter_exit_watermark * 1000;
 531                 context->bw.dcn.watermarks.c.cstate_pstate.cstate_enter_plus_exit_ns =
 532                                 v->stutter_enter_plus_exit_watermark * 1000;
 533                 context->bw.dcn.watermarks.c.cstate_pstate.pstate_change_ns =
 534                                 v->dram_clock_change_watermark * 1000;
 535                 context->bw.dcn.watermarks.c.pte_meta_urgent_ns = v->ptemeta_urgent_watermark * 1000;
 536                 context->bw.dcn.watermarks.c.urgent_ns = v->urgent_watermark * 1000;
 537         }
 538
 539         if (v->voltage_level < 3) {
 540                 v->fabric_and_dram_bandwidth_per_state[2] = v->fabric_and_dram_bandwidth_vmax0p9;
 541                 v->fabric_and_dram_bandwidth_per_state[1] = v->fabric_and_dram_bandwidth_vmax0p9;
 542                 v->fabric_and_dram_bandwidth_per_state[0] = v->fabric_and_dram_bandwidth_vmax0p9;
 543                 v->fabric_and_dram_bandwidth = v->fabric_and_dram_bandwidth_vmax0p9;
 544                 v->dcfclk_per_state[2] = v->dcfclkv_max0p9;
 545                 v->dcfclk_per_state[1] = v->dcfclkv_max0p9;
 546                 v->dcfclk_per_state[0] = v->dcfclkv_max0p9;
 547                 v->dcfclk = v->dcfclkv_max0p9;
 548                 dispclkdppclkdcfclk_deep_sleep_prefetch_parameters_watermarks_and_performance_calculation(v);
 549
 550                 context->bw.dcn.watermarks.d.cstate_pstate.cstate_exit_ns =
 551                         v->stutter_exit_watermark * 1000;
 552                 context->bw.dcn.watermarks.d.cstate_pstate.cstate_enter_plus_exit_ns =
 553                                 v->stutter_enter_plus_exit_watermark * 1000;
 554                 context->bw.dcn.watermarks.d.cstate_pstate.pstate_change_ns =
 555                                 v->dram_clock_change_watermark * 1000;
 556                 context->bw.dcn.watermarks.d.pte_meta_urgent_ns = v->ptemeta_urgent_watermark * 1000;
 557                 context->bw.dcn.watermarks.d.urgent_ns = v->urgent_watermark * 1000;
 558         }
 559
 560         v->fabric_and_dram_bandwidth_per_state[2] = v->fabric_and_dram_bandwidth_vnom0p8;
 561         v->fabric_and_dram_bandwidth_per_state[1] = v->fabric_and_dram_bandwidth_vmid0p72;
 562         v->fabric_and_dram_bandwidth_per_state[0] = v->fabric_and_dram_bandwidth_vmin0p65;
 563         v->fabric_and_dram_bandwidth = v->fabric_and_dram_bandwidth_per_state[v->voltage_level];
 564         v->dcfclk_per_state[2] = v->dcfclkv_nom0p8;
 565         v->dcfclk_per_state[1] = v->dcfclkv_mid0p72;
 566         v->dcfclk_per_state[0] = v->dcfclkv_min0p65;
 567         v->dcfclk = v->dcfclk_per_state[v->voltage_level];
 568         dispclkdppclkdcfclk_deep_sleep_prefetch_parameters_watermarks_and_performance_calculation(v);
 569
 570         context->bw.dcn.watermarks.a.cstate_pstate.cstate_exit_ns =
 571                 v->stutter_exit_watermark * 1000;
 572         context->bw.dcn.watermarks.a.cstate_pstate.cstate_enter_plus_exit_ns =
 573                         v->stutter_enter_plus_exit_watermark * 1000;
 574         context->bw.dcn.watermarks.a.cstate_pstate.pstate_change_ns =
 575                         v->dram_clock_change_watermark * 1000;
 576         context->bw.dcn.watermarks.a.pte_meta_urgent_ns = v->ptemeta_urgent_watermark * 1000;
 577         context->bw.dcn.watermarks.a.urgent_ns = v->urgent_watermark * 1000;
 578         if (v->voltage_level >= 2) {
 579                 context->bw.dcn.watermarks.b = context->bw.dcn.watermarks.a;
 580                 context->bw.dcn.watermarks.c = context->bw.dcn.watermarks.a;
 581         }
 582         if (v->voltage_level >= 3)
 583                 context->bw.dcn.watermarks.d = context->bw.dcn.watermarks.a;
 584 }
 585
 586 static bool dcn_bw_apply_registry_override(struct dc *dc)
 587 {
 588         bool updated = false;
 589
 590         kernel_fpu_begin();
 591         if ((int)(dc->dcn_soc->sr_exit_time * 1000) != dc->debug.sr_exit_time_ns
 592                         && dc->debug.sr_exit_time_ns) {
 593                 updated = true;
 594                 dc->dcn_soc->sr_exit_time = dc->debug.sr_exit_time_ns / 1000.0;
 595         }
 596
 597         if ((int)(dc->dcn_soc->sr_enter_plus_exit_time * 1000)
 598                                 != dc->debug.sr_enter_plus_exit_time_ns
 599                         && dc->debug.sr_enter_plus_exit_time_ns) {
 600                 updated = true;
 601                 dc->dcn_soc->sr_enter_plus_exit_time =
 602                                 dc->debug.sr_enter_plus_exit_time_ns / 1000.0;
 603         }
 604
 605         if ((int)(dc->dcn_soc->urgent_latency * 1000) != dc->debug.urgent_latency_ns
 606                         && dc->debug.urgent_latency_ns) {
 607                 updated = true;
 608                 dc->dcn_soc->urgent_latency = dc->debug.urgent_latency_ns / 1000.0;
 609         }
 610
 611         if ((int)(dc->dcn_soc->percent_of_ideal_drambw_received_after_urg_latency * 1000)
 612                                 != dc->debug.percent_of_ideal_drambw
 613                         && dc->debug.percent_of_ideal_drambw) {
 614                 updated = true;
 615                 dc->dcn_soc->percent_of_ideal_drambw_received_after_urg_latency =
 616                                 dc->debug.percent_of_ideal_drambw;
 617         }
 618
 619         if ((int)(dc->dcn_soc->dram_clock_change_latency * 1000)
 620                                 != dc->debug.dram_clock_change_latency_ns
 621                         && dc->debug.dram_clock_change_latency_ns) {
 622                 updated = true;
 623                 dc->dcn_soc->dram_clock_change_latency =
 624                                 dc->debug.dram_clock_change_latency_ns / 1000.0;
 625         }
 626         kernel_fpu_end();
 627
 628         return updated;
 629 }
 630
 631 static void hack_disable_optional_pipe_split(struct dcn_bw_internal_vars *v)
 632 {
 633         /*
 634          * disable optional pipe split by lower dispclk bounding box
 635          * at DPM0
 636          */
 637         v->max_dispclk[0] = v->max_dppclk_vmin0p65;
 638 }
 639
 640 static void hack_force_pipe_split(struct dcn_bw_internal_vars *v,
 641                 unsigned int pixel_rate_khz)
 642 {
 643         float pixel_rate_mhz = pixel_rate_khz / 1000;
 644
 645         /*
 646          * force enabling pipe split by lower dpp clock for DPM0 to just
 647          * below the specify pixel_rate, so bw calc would split pipe.
 648          */
 649         if (pixel_rate_mhz < v->max_dppclk[0])
 650                 v->max_dppclk[0] = pixel_rate_mhz;
 651 }
 652
 653 static void hack_bounding_box(struct dcn_bw_internal_vars *v,
 654                 struct dc_debug *dbg,
 655                 struct dc_state *context)
 656 {
 657         if (dbg->pipe_split_policy == MPC_SPLIT_AVOID)
 658                 hack_disable_optional_pipe_split(v);
 659
 660         if (dbg->pipe_split_policy == MPC_SPLIT_AVOID_MULT_DISP &&
 661                 context->stream_count >= 2)
 662                 hack_disable_optional_pipe_split(v);
 663
 664         if (context->stream_count == 1 &&
 665                         dbg->force_single_disp_pipe_split)
 666                 hack_force_pipe_split(v, context->streams[0]->timing.pix_clk_khz);
 667 }
 668
 669 bool dcn_validate_bandwidth(
 670                 struct dc *dc,
 671                 struct dc_state *context)
 672 {
 673         const struct resource_pool *pool = dc->res_pool;
 674         struct dcn_bw_internal_vars *v = &context->dcn_bw_vars;
 675         int i, input_idx;
 676         int vesa_sync_start, asic_blank_end, asic_blank_start;
 677         bool bw_limit_pass;
 678         float bw_limit;
 679
 680         PERFORMANCE_TRACE_START();
 681         if (dcn_bw_apply_registry_override(dc))
 682                 dcn_bw_sync_calcs_and_dml(dc);
 683
 684         memset(v, 0, sizeof(*v));
 685         kernel_fpu_begin();
 686         v->sr_exit_time = dc->dcn_soc->sr_exit_time;
 687         v->sr_enter_plus_exit_time = dc->dcn_soc->sr_enter_plus_exit_time;
 688         v->urgent_latency = dc->dcn_soc->urgent_latency;
 689         v->write_back_latency = dc->dcn_soc->write_back_latency;
 690         v->percent_of_ideal_drambw_received_after_urg_latency =
 691                         dc->dcn_soc->percent_of_ideal_drambw_received_after_urg_latency;
 692
 693         v->dcfclkv_min0p65 = dc->dcn_soc->dcfclkv_min0p65;
 694         v->dcfclkv_mid0p72 = dc->dcn_soc->dcfclkv_mid0p72;
 695         v->dcfclkv_nom0p8 = dc->dcn_soc->dcfclkv_nom0p8;
 696         v->dcfclkv_max0p9 = dc->dcn_soc->dcfclkv_max0p9;
 697
 698         v->max_dispclk_vmin0p65 = dc->dcn_soc->max_dispclk_vmin0p65;
 699         v->max_dispclk_vmid0p72 = dc->dcn_soc->max_dispclk_vmid0p72;
 700         v->max_dispclk_vnom0p8 = dc->dcn_soc->max_dispclk_vnom0p8;
 701         v->max_dispclk_vmax0p9 = dc->dcn_soc->max_dispclk_vmax0p9;
 702
 703         v->max_dppclk_vmin0p65 = dc->dcn_soc->max_dppclk_vmin0p65;
 704         v->max_dppclk_vmid0p72 = dc->dcn_soc->max_dppclk_vmid0p72;
 705         v->max_dppclk_vnom0p8 = dc->dcn_soc->max_dppclk_vnom0p8;
 706         v->max_dppclk_vmax0p9 = dc->dcn_soc->max_dppclk_vmax0p9;
 707
 708         v->socclk = dc->dcn_soc->socclk;
 709
 710         v->fabric_and_dram_bandwidth_vmin0p65 = dc->dcn_soc->fabric_and_dram_bandwidth_vmin0p65;
 711         v->fabric_and_dram_bandwidth_vmid0p72 = dc->dcn_soc->fabric_and_dram_bandwidth_vmid0p72;
 712         v->fabric_and_dram_bandwidth_vnom0p8 = dc->dcn_soc->fabric_and_dram_bandwidth_vnom0p8;
 713         v->fabric_and_dram_bandwidth_vmax0p9 = dc->dcn_soc->fabric_and_dram_bandwidth_vmax0p9;
 714
 715         v->phyclkv_min0p65 = dc->dcn_soc->phyclkv_min0p65;
 716         v->phyclkv_mid0p72 = dc->dcn_soc->phyclkv_mid0p72;
 717         v->phyclkv_nom0p8 = dc->dcn_soc->phyclkv_nom0p8;
 718         v->phyclkv_max0p9 = dc->dcn_soc->phyclkv_max0p9;
 719
 720         v->downspreading = dc->dcn_soc->downspreading;
 721         v->round_trip_ping_latency_cycles = dc->dcn_soc->round_trip_ping_latency_cycles;
 722         v->urgent_out_of_order_return_per_channel = dc->dcn_soc->urgent_out_of_order_return_per_channel;
 723         v->number_of_channels = dc->dcn_soc->number_of_channels;
 724         v->vmm_page_size = dc->dcn_soc->vmm_page_size;
 725         v->dram_clock_change_latency = dc->dcn_soc->dram_clock_change_latency;
 726         v->return_bus_width = dc->dcn_soc->return_bus_width;
 727
 728         v->rob_buffer_size_in_kbyte = dc->dcn_ip->rob_buffer_size_in_kbyte;
 729         v->det_buffer_size_in_kbyte = dc->dcn_ip->det_buffer_size_in_kbyte;
 730         v->dpp_output_buffer_pixels = dc->dcn_ip->dpp_output_buffer_pixels;
 731         v->opp_output_buffer_lines = dc->dcn_ip->opp_output_buffer_lines;
 732         v->pixel_chunk_size_in_kbyte = dc->dcn_ip->pixel_chunk_size_in_kbyte;
 733         v->pte_enable = dc->dcn_ip->pte_enable;
 734         v->pte_chunk_size = dc->dcn_ip->pte_chunk_size;
 735         v->meta_chunk_size = dc->dcn_ip->meta_chunk_size;
 736         v->writeback_chunk_size = dc->dcn_ip->writeback_chunk_size;
 737         v->odm_capability = dc->dcn_ip->odm_capability;
 738         v->dsc_capability = dc->dcn_ip->dsc_capability;
 739         v->line_buffer_size = dc->dcn_ip->line_buffer_size;
 740         v->is_line_buffer_bpp_fixed = dc->dcn_ip->is_line_buffer_bpp_fixed;
 741         v->line_buffer_fixed_bpp = dc->dcn_ip->line_buffer_fixed_bpp;
 742         v->max_line_buffer_lines = dc->dcn_ip->max_line_buffer_lines;
 743         v->writeback_luma_buffer_size = dc->dcn_ip->writeback_luma_buffer_size;
 744         v->writeback_chroma_buffer_size = dc->dcn_ip->writeback_chroma_buffer_size;
 745         v->max_num_dpp = dc->dcn_ip->max_num_dpp;
 746         v->max_num_writeback = dc->dcn_ip->max_num_writeback;
 747         v->max_dchub_topscl_throughput = dc->dcn_ip->max_dchub_topscl_throughput;
 748         v->max_pscl_tolb_throughput = dc->dcn_ip->max_pscl_tolb_throughput;
 749         v->max_lb_tovscl_throughput = dc->dcn_ip->max_lb_tovscl_throughput;
 750         v->max_vscl_tohscl_throughput = dc->dcn_ip->max_vscl_tohscl_throughput;
 751         v->max_hscl_ratio = dc->dcn_ip->max_hscl_ratio;
 752         v->max_vscl_ratio = dc->dcn_ip->max_vscl_ratio;
 753         v->max_hscl_taps = dc->dcn_ip->max_hscl_taps;
 754         v->max_vscl_taps = dc->dcn_ip->max_vscl_taps;
 755         v->under_scan_factor = dc->dcn_ip->under_scan_factor;
 756         v->pte_buffer_size_in_requests = dc->dcn_ip->pte_buffer_size_in_requests;
 757         v->dispclk_ramping_margin = dc->dcn_ip->dispclk_ramping_margin;
 758         v->max_inter_dcn_tile_repeaters = dc->dcn_ip->max_inter_dcn_tile_repeaters;
 759         v->can_vstartup_lines_exceed_vsync_plus_back_porch_lines_minus_one =
 760                         dc->dcn_ip->can_vstartup_lines_exceed_vsync_plus_back_porch_lines_minus_one;
 761         v->bug_forcing_luma_and_chroma_request_to_same_size_fixed =
 762                         dc->dcn_ip->bug_forcing_luma_and_chroma_request_to_same_size_fixed;
 763
 764         v->voltage[5] = dcn_bw_no_support;
 765         v->voltage[4] = dcn_bw_v_max0p9;
 766         v->voltage[3] = dcn_bw_v_max0p9;
 767         v->voltage[2] = dcn_bw_v_nom0p8;
 768         v->voltage[1] = dcn_bw_v_mid0p72;
 769         v->voltage[0] = dcn_bw_v_min0p65;
 770         v->fabric_and_dram_bandwidth_per_state[5] = v->fabric_and_dram_bandwidth_vmax0p9;
 771         v->fabric_and_dram_bandwidth_per_state[4] = v->fabric_and_dram_bandwidth_vmax0p9;
 772         v->fabric_and_dram_bandwidth_per_state[3] = v->fabric_and_dram_bandwidth_vmax0p9;
 773         v->fabric_and_dram_bandwidth_per_state[2] = v->fabric_and_dram_bandwidth_vnom0p8;
 774         v->fabric_and_dram_bandwidth_per_state[1] = v->fabric_and_dram_bandwidth_vmid0p72;
 775         v->fabric_and_dram_bandwidth_per_state[0] = v->fabric_and_dram_bandwidth_vmin0p65;
 776         v->dcfclk_per_state[5] = v->dcfclkv_max0p9;
 777         v->dcfclk_per_state[4] = v->dcfclkv_max0p9;
 778         v->dcfclk_per_state[3] = v->dcfclkv_max0p9;
 779         v->dcfclk_per_state[2] = v->dcfclkv_nom0p8;
 780         v->dcfclk_per_state[1] = v->dcfclkv_mid0p72;
 781         v->dcfclk_per_state[0] = v->dcfclkv_min0p65;
 782         v->max_dispclk[5] = v->max_dispclk_vmax0p9;
 783         v->max_dispclk[4] = v->max_dispclk_vmax0p9;
 784         v->max_dispclk[3] = v->max_dispclk_vmax0p9;
 785         v->max_dispclk[2] = v->max_dispclk_vnom0p8;
 786         v->max_dispclk[1] = v->max_dispclk_vmid0p72;
 787         v->max_dispclk[0] = v->max_dispclk_vmin0p65;
 788         v->max_dppclk[5] = v->max_dppclk_vmax0p9;
 789         v->max_dppclk[4] = v->max_dppclk_vmax0p9;
 790         v->max_dppclk[3] = v->max_dppclk_vmax0p9;
 791         v->max_dppclk[2] = v->max_dppclk_vnom0p8;
 792         v->max_dppclk[1] = v->max_dppclk_vmid0p72;
 793         v->max_dppclk[0] = v->max_dppclk_vmin0p65;
 794         v->phyclk_per_state[5] = v->phyclkv_max0p9;
 795         v->phyclk_per_state[4] = v->phyclkv_max0p9;
 796         v->phyclk_per_state[3] = v->phyclkv_max0p9;
 797         v->phyclk_per_state[2] = v->phyclkv_nom0p8;
 798         v->phyclk_per_state[1] = v->phyclkv_mid0p72;
 799         v->phyclk_per_state[0] = v->phyclkv_min0p65;
 800         v->synchronized_vblank = dcn_bw_no;
 801         v->ta_pscalculation = dcn_bw_override;
 802         v->allow_different_hratio_vratio = dcn_bw_yes;
 803
 804         for (i = 0, input_idx = 0; i < pool->pipe_count; i++) {
 805                 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];
 806
 807                 if (!pipe->stream)
 808                         continue;
 809                 /* skip all but first of split pipes */
 810                 if (pipe->top_pipe && pipe->top_pipe->plane_state == pipe->plane_state)
 811                         continue;
 812
 813                 v->underscan_output[input_idx] = false; /* taken care of in recout already*/
 814                 v->interlace_output[input_idx] = false;
 815
 816                 v->htotal[input_idx] = pipe->stream->timing.h_total;
 817                 v->vtotal[input_idx] = pipe->stream->timing.v_total;
 818                 v->vactive[input_idx] = pipe->stream->timing.v_addressable +
 819                                 pipe->stream->timing.v_border_top + pipe->stream->timing.v_border_bottom;
 820                 v->v_sync_plus_back_porch[input_idx] = pipe->stream->timing.v_total
 821                                 - v->vactive[input_idx]
 822                                 - pipe->stream->timing.v_front_porch;
 823                 v->pixel_clock[input_idx] = pipe->stream->timing.pix_clk_khz / 1000.0f;
 824
 825                 if (!pipe->plane_state) {
 826                         v->dcc_enable[input_idx] = dcn_bw_yes;
 827                         v->source_pixel_format[input_idx] = dcn_bw_rgb_sub_32;
 828                         v->source_surface_mode[input_idx] = dcn_bw_sw_4_kb_s;
 829                         v->lb_bit_per_pixel[input_idx] = 30;
 830                         v->viewport_width[input_idx] = pipe->stream->timing.h_addressable;
 831                         v->viewport_height[input_idx] = pipe->stream->timing.v_addressable;
 832                         v->scaler_rec_out_width[input_idx] = pipe->stream->timing.h_addressable;
 833                         v->scaler_recout_height[input_idx] = pipe->stream->timing.v_addressable;
 834                         v->override_hta_ps[input_idx] = 1;
 835                         v->override_vta_ps[input_idx] = 1;
 836                         v->override_hta_pschroma[input_idx] = 1;
 837                         v->override_vta_pschroma[input_idx] = 1;
 838                         v->source_scan[input_idx] = dcn_bw_hor;
 839
 840                 } else {
 841                         v->viewport_height[input_idx] =  pipe->plane_res.scl_data.viewport.height;
 842                         v->viewport_width[input_idx] = pipe->plane_res.scl_data.viewport.width;
 843                         v->scaler_rec_out_width[input_idx] = pipe->plane_res.scl_data.recout.width;
 844                         v->scaler_recout_height[input_idx] = pipe->plane_res.scl_data.recout.height;
 845                         if (pipe->bottom_pipe && pipe->bottom_pipe->plane_state == pipe->plane_state) {
 846                                 if (pipe->plane_state->rotation % 2 == 0) {
 847                                         int viewport_end = pipe->plane_res.scl_data.viewport.width
 848                                                         + pipe->plane_res.scl_data.viewport.x;
 849                                         int viewport_b_end = pipe->bottom_pipe->plane_res.scl_data.viewport.width
 850                                                         + pipe->bottom_pipe->plane_res.scl_data.viewport.x;
 851
 852                                         if (viewport_end > viewport_b_end)
 853                                                 v->viewport_width[input_idx] = viewport_end
 854                                                         - pipe->bottom_pipe->plane_res.scl_data.viewport.x;
 855                                         else
 856                                                 v->viewport_width[input_idx] = viewport_b_end
 857                                                                         - pipe->plane_res.scl_data.viewport.x;
 858                                 } else  {
 859                                         int viewport_end = pipe->plane_res.scl_data.viewport.height
 860                                                 + pipe->plane_res.scl_data.viewport.y;
 861                                         int viewport_b_end = pipe->bottom_pipe->plane_res.scl_data.viewport.height
 862                                                 + pipe->bottom_pipe->plane_res.scl_data.viewport.y;
 863
 864                                         if (viewport_end > viewport_b_end)
 865                                                 v->viewport_height[input_idx] = viewport_end
 866                                                         - pipe->bottom_pipe->plane_res.scl_data.viewport.y;
 867                                         else
 868                                                 v->viewport_height[input_idx] = viewport_b_end
 869                                                                         - pipe->plane_res.scl_data.viewport.y;
 870                                 }
 871                                 v->scaler_rec_out_width[input_idx] = pipe->plane_res.scl_data.recout.width
 872                                                 + pipe->bottom_pipe->plane_res.scl_data.recout.width;
 873                         }
 874
 875                         if (pipe->plane_state->rotation % 2 == 0) {
 876                                 ASSERT(pipe->plane_res.scl_data.ratios.horz.value != dal_fixed31_32_one.value
 877                                         || v->scaler_rec_out_width[input_idx] == v->viewport_width[input_idx]);
 878                                 ASSERT(pipe->plane_res.scl_data.ratios.vert.value != dal_fixed31_32_one.value
 879                                         || v->scaler_recout_height[input_idx] == v->viewport_height[input_idx]);
 880                         } else {
 881                                 ASSERT(pipe->plane_res.scl_data.ratios.horz.value != dal_fixed31_32_one.value
 882                                         || v->scaler_recout_height[input_idx] == v->viewport_width[input_idx]);
 883                                 ASSERT(pipe->plane_res.scl_data.ratios.vert.value != dal_fixed31_32_one.value
 884                                         || v->scaler_rec_out_width[input_idx] == v->viewport_height[input_idx]);
 885                         }
 886                         v->dcc_enable[input_idx] = pipe->plane_state->dcc.enable ? dcn_bw_yes : dcn_bw_no;
 887                         v->source_pixel_format[input_idx] = tl_pixel_format_to_bw_defs(
 888                                         pipe->plane_state->format);
 889                         v->source_surface_mode[input_idx] = tl_sw_mode_to_bw_defs(
 890                                         pipe->plane_state->tiling_info.gfx9.swizzle);
 891                         v->lb_bit_per_pixel[input_idx] = tl_lb_bpp_to_int(pipe->plane_res.scl_data.lb_params.depth);
 892                         v->override_hta_ps[input_idx] = pipe->plane_res.scl_data.taps.h_taps;
 893                         v->override_vta_ps[input_idx] = pipe->plane_res.scl_data.taps.v_taps;
 894                         v->override_hta_pschroma[input_idx] = pipe->plane_res.scl_data.taps.h_taps_c;
 895                         v->override_vta_pschroma[input_idx] = pipe->plane_res.scl_data.taps.v_taps_c;
 896                         /*
 897                          * Spreadsheet doesn't handle taps_c is one properly,
 898                          * need to force Chroma to always be scaled to pass
 899                          * bandwidth validation.
 900                          */
 901                         if (v->override_hta_pschroma[input_idx] == 1)
 902                                 v->override_hta_pschroma[input_idx] = 2;
 903                         if (v->override_vta_pschroma[input_idx] == 1)
 904                                 v->override_vta_pschroma[input_idx] = 2;
 905                         v->source_scan[input_idx] = (pipe->plane_state->rotation % 2) ? dcn_bw_vert : dcn_bw_hor;
 906                 }
 907                 if (v->is_line_buffer_bpp_fixed == dcn_bw_yes)
 908                         v->lb_bit_per_pixel[input_idx] = v->line_buffer_fixed_bpp;
 909                 v->dcc_rate[input_idx] = 1; /*TODO: Worst case? does this change?*/
 910                 v->output_format[input_idx] = pipe->stream->timing.pixel_encoding ==
 911                                 PIXEL_ENCODING_YCBCR420 ? dcn_bw_420 : dcn_bw_444;
 912                 v->output[input_idx] = pipe->stream->sink->sink_signal ==
 913                                 SIGNAL_TYPE_HDMI_TYPE_A ? dcn_bw_hdmi : dcn_bw_dp;
 914                 v->output_deep_color[input_idx] = dcn_bw_encoder_8bpc;
 915                 if (v->output[input_idx] == dcn_bw_hdmi) {
 916                         switch (pipe->stream->timing.display_color_depth) {
 917                         case COLOR_DEPTH_101010:
 918                                 v->output_deep_color[input_idx] = dcn_bw_encoder_10bpc;
 919                                 break;
 920                         case COLOR_DEPTH_121212:
 921                                 v->output_deep_color[input_idx]  = dcn_bw_encoder_12bpc;
 922                                 break;
 923                         case COLOR_DEPTH_161616:
 924                                 v->output_deep_color[input_idx]  = dcn_bw_encoder_16bpc;
 925                                 break;
 926                         default:
 927                                 break;
 928                         }
 929                 }
 930
 931                 input_idx++;
 932         }
 933         v->number_of_active_planes = input_idx;
 934
 935         scaler_settings_calculation(v);
 936
 937         hack_bounding_box(v, &dc->debug, context);
 938
 939         mode_support_and_system_configuration(v);
 940
 941         /* Unhack dppclk: dont bother with trying to pipe split if we cannot maintain dpm0 */
 942         if (v->voltage_level != 0
 943                         && context->stream_count == 1
 944                         && dc->debug.force_single_disp_pipe_split) {
 945                 v->max_dppclk[0] = v->max_dppclk_vmin0p65;
 946                 mode_support_and_system_configuration(v);
 947         }
 948
 949         if (v->voltage_level == 0 &&
 950                         (dc->debug.sr_exit_time_dpm0_ns
 951                                 || dc->debug.sr_enter_plus_exit_time_dpm0_ns)) {
 952
 953                 if (dc->debug.sr_enter_plus_exit_time_dpm0_ns)
 954                         v->sr_enter_plus_exit_time =
 955                                 dc->debug.sr_enter_plus_exit_time_dpm0_ns / 1000.0f;
 956                 if (dc->debug.sr_exit_time_dpm0_ns)
 957                         v->sr_exit_time =  dc->debug.sr_exit_time_dpm0_ns / 1000.0f;
 958                 dc->dml.soc.sr_enter_plus_exit_time_us = v->sr_enter_plus_exit_time;
 959                 dc->dml.soc.sr_exit_time_us = v->sr_exit_time;
 960                 mode_support_and_system_configuration(v);
 961         }
 962
 963         if (v->voltage_level != 5) {
 964                 float bw_consumed = v->total_bandwidth_consumed_gbyte_per_second;
 965                 if (bw_consumed < v->fabric_and_dram_bandwidth_vmin0p65)
 966                         bw_consumed = v->fabric_and_dram_bandwidth_vmin0p65;
 967                 else if (bw_consumed < v->fabric_and_dram_bandwidth_vmid0p72)
 968                         bw_consumed = v->fabric_and_dram_bandwidth_vmid0p72;
 969                 else if (bw_consumed < v->fabric_and_dram_bandwidth_vnom0p8)
 970                         bw_consumed = v->fabric_and_dram_bandwidth_vnom0p8;
 971                 else
 972                         bw_consumed = v->fabric_and_dram_bandwidth_vmax0p9;
 973
 974                 if (bw_consumed < v->fabric_and_dram_bandwidth)
 975                         if (dc->debug.voltage_align_fclk)
 976                                 bw_consumed = v->fabric_and_dram_bandwidth;
 977
 978                 display_pipe_configuration(v);
 979                 calc_wm_sets_and_perf_params(context, v);
 980                 context->bw.dcn.calc_clk.fclk_khz = (int)(bw_consumed * 1000000 /
 981                                 (ddr4_dram_factor_single_Channel * v->number_of_channels));
 982                 if (bw_consumed == v->fabric_and_dram_bandwidth_vmin0p65) {
 983                         context->bw.dcn.calc_clk.fclk_khz = (int)(bw_consumed * 1000000 / 32);
 984                 }
 985
 986                 context->bw.dcn.calc_clk.dram_ccm_us = (int)(v->dram_clock_change_margin);
 987                 context->bw.dcn.calc_clk.min_active_dram_ccm_us = (int)(v->min_active_dram_clock_change_margin);
 988                 context->bw.dcn.calc_clk.dcfclk_deep_sleep_khz = (int)(v->dcf_clk_deep_sleep * 1000);
 989                 context->bw.dcn.calc_clk.dcfclk_khz = (int)(v->dcfclk * 1000);
 990
 991                 context->bw.dcn.calc_clk.dispclk_khz = (int)(v->dispclk * 1000);
 992                 if (dc->debug.max_disp_clk == true)
 993                         context->bw.dcn.calc_clk.dispclk_khz = (int)(dc->dcn_soc->max_dispclk_vmax0p9 * 1000);
 994
 995                 if (context->bw.dcn.calc_clk.dispclk_khz <
 996                                 dc->debug.min_disp_clk_khz) {
 997                         context->bw.dcn.calc_clk.dispclk_khz =
 998                                         dc->debug.min_disp_clk_khz;
 999                 }
1000
1001                 context->bw.dcn.calc_clk.max_dppclk_khz = (int)(v->dppclk * 1000);
1002
1003                 for (i = 0, input_idx = 0; i < pool->pipe_count; i++) {
1004                         struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];
1005
1006                         /* skip inactive pipe */
1007                         if (!pipe->stream)
1008                                 continue;
1009                         /* skip all but first of split pipes */
1010                         if (pipe->top_pipe && pipe->top_pipe->plane_state == pipe->plane_state)
1011                                 continue;
1012
1013                         pipe->pipe_dlg_param.vupdate_width = v->v_update_width[input_idx][v->dpp_per_plane[input_idx] == 2 ? 1 : 0];
1014                         pipe->pipe_dlg_param.vupdate_offset = v->v_update_offset[input_idx][v->dpp_per_plane[input_idx] == 2 ? 1 : 0];
1015                         pipe->pipe_dlg_param.vready_offset = v->v_ready_offset[input_idx][v->dpp_per_plane[input_idx] == 2 ? 1 : 0];
1016                         pipe->pipe_dlg_param.vstartup_start = v->v_startup[input_idx];
1017
1018                         pipe->pipe_dlg_param.htotal = pipe->stream->timing.h_total;
1019                         pipe->pipe_dlg_param.vtotal = pipe->stream->timing.v_total;
1020                         vesa_sync_start = pipe->stream->timing.v_addressable +
1021                                                 pipe->stream->timing.v_border_bottom +
1022                                                 pipe->stream->timing.v_front_porch;
1023
1024                         asic_blank_end = (pipe->stream->timing.v_total -
1025                                                 vesa_sync_start -
1026                                                 pipe->stream->timing.v_border_top)
1027                         * (pipe->stream->timing.flags.INTERLACE ? 1 : 0);
1028
1029                         asic_blank_start = asic_blank_end +
1030                                                 (pipe->stream->timing.v_border_top +
1031                                                 pipe->stream->timing.v_addressable +
1032                                                 pipe->stream->timing.v_border_bottom)
1033                         * (pipe->stream->timing.flags.INTERLACE ? 1 : 0);
1034
1035                         pipe->pipe_dlg_param.vblank_start = asic_blank_start;
1036                         pipe->pipe_dlg_param.vblank_end = asic_blank_end;
1037
1038                         if (pipe->plane_state) {
1039                                 struct pipe_ctx *hsplit_pipe = pipe->bottom_pipe;
1040
1041                                 pipe->plane_state->update_flags.bits.full_update = 1;
1042
1043                                 if (v->dpp_per_plane[input_idx] == 2 ||
1044                                         ((pipe->stream->view_format ==
1045                                           VIEW_3D_FORMAT_SIDE_BY_SIDE ||
1046                                           pipe->stream->view_format ==
1047                                           VIEW_3D_FORMAT_TOP_AND_BOTTOM) &&
1048                                         (pipe->stream->timing.timing_3d_format ==
1049                                          TIMING_3D_FORMAT_TOP_AND_BOTTOM ||
1050                                          pipe->stream->timing.timing_3d_format ==
1051                                          TIMING_3D_FORMAT_SIDE_BY_SIDE))) {
1052                                         if (hsplit_pipe && hsplit_pipe->plane_state == pipe->plane_state) {
1053                                                 /* update previously split pipe */
1054                                                 hsplit_pipe->pipe_dlg_param.vupdate_width = v->v_update_width[input_idx][v->dpp_per_plane[input_idx] == 2 ? 1 : 0];
1055                                                 hsplit_pipe->pipe_dlg_param.vupdate_offset = v->v_update_offset[input_idx][v->dpp_per_plane[input_idx] == 2 ? 1 : 0];
1056                                                 hsplit_pipe->pipe_dlg_param.vready_offset = v->v_ready_offset[input_idx][v->dpp_per_plane[input_idx] == 2 ? 1 : 0];
1057                                                 hsplit_pipe->pipe_dlg_param.vstartup_start = v->v_startup[input_idx];
1058
1059                                                 hsplit_pipe->pipe_dlg_param.htotal = pipe->stream->timing.h_total;
1060                                                 hsplit_pipe->pipe_dlg_param.vtotal = pipe->stream->timing.v_total;
1061                                                 hsplit_pipe->pipe_dlg_param.vblank_start = pipe->pipe_dlg_param.vblank_start;
1062                                                 hsplit_pipe->pipe_dlg_param.vblank_end = pipe->pipe_dlg_param.vblank_end;
1063                                         } else {
1064                                                 /* pipe not split previously needs split */
1065                                                 hsplit_pipe = find_idle_secondary_pipe(&context->res_ctx, pool);
1066                                                 ASSERT(hsplit_pipe);
1067                                                 split_stream_across_pipes(
1068                                                         &context->res_ctx, pool,
1069                                                         pipe, hsplit_pipe);
1070                                         }
1071
1072                                         dcn_bw_calc_rq_dlg_ttu(dc, v, hsplit_pipe, input_idx);
1073                                 } else if (hsplit_pipe && hsplit_pipe->plane_state == pipe->plane_state) {
1074                                         /* merge previously split pipe */
1075                                         pipe->bottom_pipe = hsplit_pipe->bottom_pipe;
1076                                         if (hsplit_pipe->bottom_pipe)
1077                                                 hsplit_pipe->bottom_pipe->top_pipe = pipe;
1078                                         hsplit_pipe->plane_state = NULL;
1079                                         hsplit_pipe->stream = NULL;
1080                                         hsplit_pipe->top_pipe = NULL;
1081                                         hsplit_pipe->bottom_pipe = NULL;
1082                                         /* Clear plane_res and stream_res */
1083                                         memset(&hsplit_pipe->plane_res, 0, sizeof(hsplit_pipe->plane_res));
1084                                         memset(&hsplit_pipe->stream_res, 0, sizeof(hsplit_pipe->stream_res));
1085                                         resource_build_scaling_params(pipe);
1086                                 }
1087                                 /* for now important to do this after pipe split for building e2e params */
1088                                 dcn_bw_calc_rq_dlg_ttu(dc, v, pipe, input_idx);
1089                         }
1090
1091                         input_idx++;
1092                 }
1093         }
1094
1095         if (v->voltage_level == 0) {
1096
1097                 dc->dml.soc.sr_enter_plus_exit_time_us =
1098                                 dc->dcn_soc->sr_enter_plus_exit_time;
1099                 dc->dml.soc.sr_exit_time_us = dc->dcn_soc->sr_exit_time;
1100         }
1101
1102         /*
1103          * BW limit is set to prevent display from impacting other system functions
1104          */
1105
1106         bw_limit = dc->dcn_soc->percent_disp_bw_limit * v->fabric_and_dram_bandwidth_vmax0p9;
1107         bw_limit_pass = (v->total_data_read_bandwidth / 1000.0) < bw_limit;
1108
1109         kernel_fpu_end();
1110
1111         PERFORMANCE_TRACE_END();
1112
1113         if (bw_limit_pass && v->voltage_level != 5)
1114                 return true;
1115         else
1116                 return false;
1117 }
1118
1119 static unsigned int dcn_find_normalized_clock_vdd_Level(
1120         const struct dc *dc,
1121         enum dm_pp_clock_type clocks_type,
1122         int clocks_in_khz)
1123 {
1124         int vdd_level = dcn_bw_v_min0p65;
1125
1126         if (clocks_in_khz == 0)/*todo some clock not in the considerations*/
1127                 return vdd_level;
1128
1129         switch (clocks_type) {
1130         case DM_PP_CLOCK_TYPE_DISPLAY_CLK:
1131                 if (clocks_in_khz > dc->dcn_soc->max_dispclk_vmax0p9*1000) {
1132                         vdd_level = dcn_bw_v_max0p91;
1133                         BREAK_TO_DEBUGGER();
1134                 } else if (clocks_in_khz > dc->dcn_soc->max_dispclk_vnom0p8*1000) {
1135                         vdd_level = dcn_bw_v_max0p9;
1136                 } else if (clocks_in_khz > dc->dcn_soc->max_dispclk_vmid0p72*1000) {
1137                         vdd_level = dcn_bw_v_nom0p8;
1138                 } else if (clocks_in_khz > dc->dcn_soc->max_dispclk_vmin0p65*1000) {
1139                         vdd_level = dcn_bw_v_mid0p72;
1140                 } else
1141                         vdd_level = dcn_bw_v_min0p65;
1142                 break;
1143         case DM_PP_CLOCK_TYPE_DISPLAYPHYCLK:
1144                 if (clocks_in_khz > dc->dcn_soc->phyclkv_max0p9*1000) {
1145                         vdd_level = dcn_bw_v_max0p91;
1146                         BREAK_TO_DEBUGGER();
1147                 } else if (clocks_in_khz > dc->dcn_soc->phyclkv_nom0p8*1000) {
1148                         vdd_level = dcn_bw_v_max0p9;
1149                 } else if (clocks_in_khz > dc->dcn_soc->phyclkv_mid0p72*1000) {
1150                         vdd_level = dcn_bw_v_nom0p8;
1151                 } else if (clocks_in_khz > dc->dcn_soc->phyclkv_min0p65*1000) {
1152                         vdd_level = dcn_bw_v_mid0p72;
1153                 } else
1154                         vdd_level = dcn_bw_v_min0p65;
1155                 break;
1156
1157         case DM_PP_CLOCK_TYPE_DPPCLK:
1158                 if (clocks_in_khz > dc->dcn_soc->max_dppclk_vmax0p9*1000) {
1159                         vdd_level = dcn_bw_v_max0p91;
1160                         BREAK_TO_DEBUGGER();
1161                 } else if (clocks_in_khz > dc->dcn_soc->max_dppclk_vnom0p8*1000) {
1162                         vdd_level = dcn_bw_v_max0p9;
1163                 } else if (clocks_in_khz > dc->dcn_soc->max_dppclk_vmid0p72*1000) {
1164                         vdd_level = dcn_bw_v_nom0p8;
1165                 } else if (clocks_in_khz > dc->dcn_soc->max_dppclk_vmin0p65*1000) {
1166                         vdd_level = dcn_bw_v_mid0p72;
1167                 } else
1168                         vdd_level = dcn_bw_v_min0p65;
1169                 break;
1170
1171         case DM_PP_CLOCK_TYPE_MEMORY_CLK:
1172                 {
1173                         unsigned factor = (ddr4_dram_factor_single_Channel * dc->dcn_soc->number_of_channels);
1174
1175                         if (clocks_in_khz > dc->dcn_soc->fabric_and_dram_bandwidth_vmax0p9*1000000/factor) {
1176                                 vdd_level = dcn_bw_v_max0p91;
1177                                 BREAK_TO_DEBUGGER();
1178                         } else if (clocks_in_khz > dc->dcn_soc->fabric_and_dram_bandwidth_vnom0p8*1000000/factor) {
1179                                 vdd_level = dcn_bw_v_max0p9;
1180                         } else if (clocks_in_khz > dc->dcn_soc->fabric_and_dram_bandwidth_vmid0p72*1000000/factor) {
1181                                 vdd_level = dcn_bw_v_nom0p8;
1182                         } else if (clocks_in_khz > dc->dcn_soc->fabric_and_dram_bandwidth_vmin0p65*1000000/factor) {
1183                                 vdd_level = dcn_bw_v_mid0p72;
1184                         } else
1185                                 vdd_level = dcn_bw_v_min0p65;
1186                 }
1187                 break;
1188
1189         case DM_PP_CLOCK_TYPE_DCFCLK:
1190                 if (clocks_in_khz > dc->dcn_soc->dcfclkv_max0p9*1000) {
1191                         vdd_level = dcn_bw_v_max0p91;
1192                         BREAK_TO_DEBUGGER();
1193                 } else if (clocks_in_khz > dc->dcn_soc->dcfclkv_nom0p8*1000) {
1194                         vdd_level = dcn_bw_v_max0p9;
1195                 } else if (clocks_in_khz > dc->dcn_soc->dcfclkv_mid0p72*1000) {
1196                         vdd_level = dcn_bw_v_nom0p8;
1197                 } else if (clocks_in_khz > dc->dcn_soc->dcfclkv_min0p65*1000) {
1198                         vdd_level = dcn_bw_v_mid0p72;
1199                 } else
1200                         vdd_level = dcn_bw_v_min0p65;
1201                 break;
1202
1203         default:
1204                  break;
1205         }
1206         return vdd_level;
1207 }
1208
1209 unsigned int dcn_find_dcfclk_suits_all(
1210         const struct dc *dc,
1211         struct clocks_value *clocks)
1212 {
1213         unsigned vdd_level, vdd_level_temp;
1214         unsigned dcf_clk;
1215
1216         /*find a common supported voltage level*/
1217         vdd_level = dcn_find_normalized_clock_vdd_Level(
1218                 dc, DM_PP_CLOCK_TYPE_DISPLAY_CLK, clocks->dispclk_in_khz);
1219         vdd_level_temp = dcn_find_normalized_clock_vdd_Level(
1220                 dc, DM_PP_CLOCK_TYPE_DISPLAYPHYCLK, clocks->phyclk_in_khz);
1221
1222         vdd_level = dcn_bw_max(vdd_level, vdd_level_temp);
1223         vdd_level_temp = dcn_find_normalized_clock_vdd_Level(
1224                 dc, DM_PP_CLOCK_TYPE_DPPCLK, clocks->dppclk_in_khz);
1225         vdd_level = dcn_bw_max(vdd_level, vdd_level_temp);
1226
1227         vdd_level_temp = dcn_find_normalized_clock_vdd_Level(
1228                 dc, DM_PP_CLOCK_TYPE_MEMORY_CLK, clocks->dcfclock_in_khz);
1229         vdd_level = dcn_bw_max(vdd_level, vdd_level_temp);
1230         vdd_level_temp = dcn_find_normalized_clock_vdd_Level(
1231                 dc, DM_PP_CLOCK_TYPE_DCFCLK, clocks->dcfclock_in_khz);
1232
1233         /*find that level conresponding dcfclk*/
1234         vdd_level = dcn_bw_max(vdd_level, vdd_level_temp);
1235         if (vdd_level == dcn_bw_v_max0p91) {
1236                 BREAK_TO_DEBUGGER();
1237                 dcf_clk = dc->dcn_soc->dcfclkv_max0p9*1000;
1238         } else if (vdd_level == dcn_bw_v_max0p9)
1239                 dcf_clk =  dc->dcn_soc->dcfclkv_max0p9*1000;
1240         else if (vdd_level == dcn_bw_v_nom0p8)
1241                 dcf_clk =  dc->dcn_soc->dcfclkv_nom0p8*1000;
1242         else if (vdd_level == dcn_bw_v_mid0p72)
1243                 dcf_clk =  dc->dcn_soc->dcfclkv_mid0p72*1000;
1244         else
1245                 dcf_clk =  dc->dcn_soc->dcfclkv_min0p65*1000;
1246
1247         DC_LOG_BANDWIDTH_CALCS("\tdcf_clk for voltage = %d\n", dcf_clk);
1248         return dcf_clk;
1249 }
1250
1251 static bool verify_clock_values(struct dm_pp_clock_levels_with_voltage *clks)
1252 {
1253         int i;
1254
1255         if (clks->num_levels == 0)
1256                 return false;
1257
1258         for (i = 0; i < clks->num_levels; i++)
1259                 /* Ensure that the result is sane */
1260                 if (clks->data[i].clocks_in_khz == 0)
1261                         return false;
1262
1263         return true;
1264 }
1265
1266 void dcn_bw_update_from_pplib(struct dc *dc)
1267 {
1268         struct dc_context *ctx = dc->ctx;
1269         struct dm_pp_clock_levels_with_voltage fclks = {0}, dcfclks = {0};
1270         bool res;
1271
1272         kernel_fpu_begin();
1273
1274         /* TODO: This is not the proper way to obtain fabric_and_dram_bandwidth, should be min(fclk, memclk) */
1275         res = dm_pp_get_clock_levels_by_type_with_voltage(
1276                         ctx, DM_PP_CLOCK_TYPE_FCLK, &fclks);
1277
1278         if (res)
1279                 res = verify_clock_values(&fclks);
1280
1281         if (res) {
1282                 ASSERT(fclks.num_levels >= 3);
1283                 dc->dcn_soc->fabric_and_dram_bandwidth_vmin0p65 = 32 * (fclks.data[0].clocks_in_khz / 1000.0) / 1000.0;
1284                 dc->dcn_soc->fabric_and_dram_bandwidth_vmid0p72 = dc->dcn_soc->number_of_channels *
1285                                 (fclks.data[fclks.num_levels - (fclks.num_levels > 2 ? 3 : 2)].clocks_in_khz / 1000.0)
1286                                 * ddr4_dram_factor_single_Channel / 1000.0;
1287                 dc->dcn_soc->fabric_and_dram_bandwidth_vnom0p8 = dc->dcn_soc->number_of_channels *
1288                                 (fclks.data[fclks.num_levels - 2].clocks_in_khz / 1000.0)
1289                                 * ddr4_dram_factor_single_Channel / 1000.0;
1290                 dc->dcn_soc->fabric_and_dram_bandwidth_vmax0p9 = dc->dcn_soc->number_of_channels *
1291                                 (fclks.data[fclks.num_levels - 1].clocks_in_khz / 1000.0)
1292                                 * ddr4_dram_factor_single_Channel / 1000.0;
1293         } else
1294                 BREAK_TO_DEBUGGER();
1295
1296         res = dm_pp_get_clock_levels_by_type_with_voltage(
1297                         ctx, DM_PP_CLOCK_TYPE_DCFCLK, &dcfclks);
1298
1299         if (res)
1300                 res = verify_clock_values(&dcfclks);
1301
1302         if (res && dcfclks.num_levels >= 3) {
1303                 dc->dcn_soc->dcfclkv_min0p65 = dcfclks.data[0].clocks_in_khz / 1000.0;
1304                 dc->dcn_soc->dcfclkv_mid0p72 = dcfclks.data[dcfclks.num_levels - 3].clocks_in_khz / 1000.0;
1305                 dc->dcn_soc->dcfclkv_nom0p8 = dcfclks.data[dcfclks.num_levels - 2].clocks_in_khz / 1000.0;
1306                 dc->dcn_soc->dcfclkv_max0p9 = dcfclks.data[dcfclks.num_levels - 1].clocks_in_khz / 1000.0;
1307         } else
1308                 BREAK_TO_DEBUGGER();
1309
1310         kernel_fpu_end();
1311 }
1312
1313 void dcn_bw_notify_pplib_of_wm_ranges(struct dc *dc)
1314 {
1315         struct pp_smu_funcs_rv *pp = dc->res_pool->pp_smu;
1316         struct pp_smu_wm_range_sets ranges = {0};
1317         int max_fclk_khz, nom_fclk_khz, mid_fclk_khz, min_fclk_khz;
1318         int max_dcfclk_khz, min_dcfclk_khz;
1319         int socclk_khz;
1320         const int overdrive = 5000000; /* 5 GHz to cover Overdrive */
1321         unsigned factor = (ddr4_dram_factor_single_Channel * dc->dcn_soc->number_of_channels);
1322
1323         if (!pp->set_wm_ranges)
1324                 return;
1325
1326         kernel_fpu_begin();
1327         max_fclk_khz = dc->dcn_soc->fabric_and_dram_bandwidth_vmax0p9 * 1000000 / factor;
1328         nom_fclk_khz = dc->dcn_soc->fabric_and_dram_bandwidth_vnom0p8 * 1000000 / factor;
1329         mid_fclk_khz = dc->dcn_soc->fabric_and_dram_bandwidth_vmid0p72 * 1000000 / factor;
1330         min_fclk_khz = dc->dcn_soc->fabric_and_dram_bandwidth_vmin0p65 * 1000000 / 32;
1331         max_dcfclk_khz = dc->dcn_soc->dcfclkv_max0p9 * 1000;
1332         min_dcfclk_khz = dc->dcn_soc->dcfclkv_min0p65 * 1000;
1333         socclk_khz = dc->dcn_soc->socclk * 1000;
1334         kernel_fpu_end();
1335
1336         /* Now notify PPLib/SMU about which Watermarks sets they should select
1337          * depending on DPM state they are in. And update BW MGR GFX Engine and
1338          * Memory clock member variables for Watermarks calculations for each
1339          * Watermark Set
1340          */
1341         /* SOCCLK does not affect anytihng but writeback for DCN so for now we dont
1342          * care what the value is, hence min to overdrive level
1343          */
1344         ranges.num_reader_wm_sets = WM_COUNT;
1345         ranges.num_writer_wm_sets = WM_COUNT;
1346         ranges.reader_wm_sets[0].wm_inst = WM_A;
1347         ranges.reader_wm_sets[0].min_drain_clk_khz = min_dcfclk_khz;
1348         ranges.reader_wm_sets[0].max_drain_clk_khz = max_dcfclk_khz;
1349         ranges.reader_wm_sets[0].min_fill_clk_khz = min_fclk_khz;
1350         ranges.reader_wm_sets[0].max_fill_clk_khz = min_fclk_khz;
1351         ranges.writer_wm_sets[0].wm_inst = WM_A;
1352         ranges.writer_wm_sets[0].min_fill_clk_khz = socclk_khz;
1353         ranges.writer_wm_sets[0].max_fill_clk_khz = overdrive;
1354         ranges.writer_wm_sets[0].min_drain_clk_khz = min_fclk_khz;
1355         ranges.writer_wm_sets[0].max_drain_clk_khz = min_fclk_khz;
1356
1357         ranges.reader_wm_sets[1].wm_inst = WM_B;
1358         ranges.reader_wm_sets[1].min_drain_clk_khz = min_fclk_khz;
1359         ranges.reader_wm_sets[1].max_drain_clk_khz = max_dcfclk_khz;
1360         ranges.reader_wm_sets[1].min_fill_clk_khz = mid_fclk_khz;
1361         ranges.reader_wm_sets[1].max_fill_clk_khz = mid_fclk_khz;
1362         ranges.writer_wm_sets[1].wm_inst = WM_B;
1363         ranges.writer_wm_sets[1].min_fill_clk_khz = socclk_khz;
1364         ranges.writer_wm_sets[1].max_fill_clk_khz = overdrive;
1365         ranges.writer_wm_sets[1].min_drain_clk_khz = mid_fclk_khz;
1366         ranges.writer_wm_sets[1].max_drain_clk_khz = mid_fclk_khz;
1367
1368
1369         ranges.reader_wm_sets[2].wm_inst = WM_C;
1370         ranges.reader_wm_sets[2].min_drain_clk_khz = min_fclk_khz;
1371         ranges.reader_wm_sets[2].max_drain_clk_khz = max_dcfclk_khz;
1372         ranges.reader_wm_sets[2].min_fill_clk_khz = nom_fclk_khz;
1373         ranges.reader_wm_sets[2].max_fill_clk_khz = nom_fclk_khz;
1374         ranges.writer_wm_sets[2].wm_inst = WM_C;
1375         ranges.writer_wm_sets[2].min_fill_clk_khz = socclk_khz;
1376         ranges.writer_wm_sets[2].max_fill_clk_khz = overdrive;
1377         ranges.writer_wm_sets[2].min_drain_clk_khz = nom_fclk_khz;
1378         ranges.writer_wm_sets[2].max_drain_clk_khz = nom_fclk_khz;
1379
1380         ranges.reader_wm_sets[3].wm_inst = WM_D;
1381         ranges.reader_wm_sets[3].min_drain_clk_khz = min_fclk_khz;
1382         ranges.reader_wm_sets[3].max_drain_clk_khz = max_dcfclk_khz;
1383         ranges.reader_wm_sets[3].min_fill_clk_khz = max_fclk_khz;
1384         ranges.reader_wm_sets[3].max_fill_clk_khz = max_fclk_khz;
1385         ranges.writer_wm_sets[3].wm_inst = WM_D;
1386         ranges.writer_wm_sets[3].min_fill_clk_khz = socclk_khz;
1387         ranges.writer_wm_sets[3].max_fill_clk_khz = overdrive;
1388         ranges.writer_wm_sets[3].min_drain_clk_khz = max_fclk_khz;
1389         ranges.writer_wm_sets[3].max_drain_clk_khz = max_fclk_khz;
1390
1391         if (dc->debug.pplib_wm_report_mode == WM_REPORT_OVERRIDE) {
1392                 ranges.reader_wm_sets[0].wm_inst = WM_A;
1393                 ranges.reader_wm_sets[0].min_drain_clk_khz = 300000;
1394                 ranges.reader_wm_sets[0].max_drain_clk_khz = 654000;
1395                 ranges.reader_wm_sets[0].min_fill_clk_khz = 800000;
1396                 ranges.reader_wm_sets[0].max_fill_clk_khz = 800000;
1397                 ranges.writer_wm_sets[0].wm_inst = WM_A;
1398                 ranges.writer_wm_sets[0].min_fill_clk_khz = 200000;
1399                 ranges.writer_wm_sets[0].max_fill_clk_khz = 757000;
1400                 ranges.writer_wm_sets[0].min_drain_clk_khz = 800000;
1401                 ranges.writer_wm_sets[0].max_drain_clk_khz = 800000;
1402
1403                 ranges.reader_wm_sets[1].wm_inst = WM_B;
1404                 ranges.reader_wm_sets[1].min_drain_clk_khz = 300000;
1405                 ranges.reader_wm_sets[1].max_drain_clk_khz = 654000;
1406                 ranges.reader_wm_sets[1].min_fill_clk_khz = 933000;
1407                 ranges.reader_wm_sets[1].max_fill_clk_khz = 933000;
1408                 ranges.writer_wm_sets[1].wm_inst = WM_B;
1409                 ranges.writer_wm_sets[1].min_fill_clk_khz = 200000;
1410                 ranges.writer_wm_sets[1].max_fill_clk_khz = 757000;
1411                 ranges.writer_wm_sets[1].min_drain_clk_khz = 933000;
1412                 ranges.writer_wm_sets[1].max_drain_clk_khz = 933000;
1413
1414
1415                 ranges.reader_wm_sets[2].wm_inst = WM_C;
1416                 ranges.reader_wm_sets[2].min_drain_clk_khz = 300000;
1417                 ranges.reader_wm_sets[2].max_drain_clk_khz = 654000;
1418                 ranges.reader_wm_sets[2].min_fill_clk_khz = 1067000;
1419                 ranges.reader_wm_sets[2].max_fill_clk_khz = 1067000;
1420                 ranges.writer_wm_sets[2].wm_inst = WM_C;
1421                 ranges.writer_wm_sets[2].min_fill_clk_khz = 200000;
1422                 ranges.writer_wm_sets[2].max_fill_clk_khz = 757000;
1423                 ranges.writer_wm_sets[2].min_drain_clk_khz = 1067000;
1424                 ranges.writer_wm_sets[2].max_drain_clk_khz = 1067000;
1425
1426                 ranges.reader_wm_sets[3].wm_inst = WM_D;
1427                 ranges.reader_wm_sets[3].min_drain_clk_khz = 300000;
1428                 ranges.reader_wm_sets[3].max_drain_clk_khz = 654000;
1429                 ranges.reader_wm_sets[3].min_fill_clk_khz = 1200000;
1430                 ranges.reader_wm_sets[3].max_fill_clk_khz = 1200000;
1431                 ranges.writer_wm_sets[3].wm_inst = WM_D;
1432                 ranges.writer_wm_sets[3].min_fill_clk_khz = 200000;
1433                 ranges.writer_wm_sets[3].max_fill_clk_khz = 757000;
1434                 ranges.writer_wm_sets[3].min_drain_clk_khz = 1200000;
1435                 ranges.writer_wm_sets[3].max_drain_clk_khz = 1200000;
1436         }
1437
1438         /* Notify PP Lib/SMU which Watermarks to use for which clock ranges */
1439         pp->set_wm_ranges(&pp->pp_smu, &ranges);
1440 }
1441
1442 void dcn_bw_sync_calcs_and_dml(struct dc *dc)
1443 {
1444         kernel_fpu_begin();
1445         DC_LOG_BANDWIDTH_CALCS("sr_exit_time: %d ns\n"
1446                         "sr_enter_plus_exit_time: %d ns\n"
1447                         "urgent_latency: %d ns\n"
1448                         "write_back_latency: %d ns\n"
1449                         "percent_of_ideal_drambw_received_after_urg_latency: %d %\n"
1450                         "max_request_size: %d bytes\n"
1451                         "dcfclkv_max0p9: %d kHz\n"
1452                         "dcfclkv_nom0p8: %d kHz\n"
1453                         "dcfclkv_mid0p72: %d kHz\n"
1454                         "dcfclkv_min0p65: %d kHz\n"
1455                         "max_dispclk_vmax0p9: %d kHz\n"
1456                         "max_dispclk_vnom0p8: %d kHz\n"
1457                         "max_dispclk_vmid0p72: %d kHz\n"
1458                         "max_dispclk_vmin0p65: %d kHz\n"
1459                         "max_dppclk_vmax0p9: %d kHz\n"
1460                         "max_dppclk_vnom0p8: %d kHz\n"
1461                         "max_dppclk_vmid0p72: %d kHz\n"
1462                         "max_dppclk_vmin0p65: %d kHz\n"
1463                         "socclk: %d kHz\n"
1464                         "fabric_and_dram_bandwidth_vmax0p9: %d MB/s\n"
1465                         "fabric_and_dram_bandwidth_vnom0p8: %d MB/s\n"
1466                         "fabric_and_dram_bandwidth_vmid0p72: %d MB/s\n"
1467                         "fabric_and_dram_bandwidth_vmin0p65: %d MB/s\n"
1468                         "phyclkv_max0p9: %d kHz\n"
1469                         "phyclkv_nom0p8: %d kHz\n"
1470                         "phyclkv_mid0p72: %d kHz\n"
1471                         "phyclkv_min0p65: %d kHz\n"
1472                         "downspreading: %d %\n"
1473                         "round_trip_ping_latency_cycles: %d DCFCLK Cycles\n"
1474                         "urgent_out_of_order_return_per_channel: %d Bytes\n"
1475                         "number_of_channels: %d\n"
1476                         "vmm_page_size: %d Bytes\n"
1477                         "dram_clock_change_latency: %d ns\n"
1478                         "return_bus_width: %d Bytes\n",
1479                         dc->dcn_soc->sr_exit_time * 1000,
1480                         dc->dcn_soc->sr_enter_plus_exit_time * 1000,
1481                         dc->dcn_soc->urgent_latency * 1000,
1482                         dc->dcn_soc->write_back_latency * 1000,
1483                         dc->dcn_soc->percent_of_ideal_drambw_received_after_urg_latency,
1484                         dc->dcn_soc->max_request_size,
1485                         dc->dcn_soc->dcfclkv_max0p9 * 1000,
1486                         dc->dcn_soc->dcfclkv_nom0p8 * 1000,
1487                         dc->dcn_soc->dcfclkv_mid0p72 * 1000,
1488                         dc->dcn_soc->dcfclkv_min0p65 * 1000,
1489                         dc->dcn_soc->max_dispclk_vmax0p9 * 1000,
1490                         dc->dcn_soc->max_dispclk_vnom0p8 * 1000,
1491                         dc->dcn_soc->max_dispclk_vmid0p72 * 1000,
1492                         dc->dcn_soc->max_dispclk_vmin0p65 * 1000,
1493                         dc->dcn_soc->max_dppclk_vmax0p9 * 1000,
1494                         dc->dcn_soc->max_dppclk_vnom0p8 * 1000,
1495                         dc->dcn_soc->max_dppclk_vmid0p72 * 1000,
1496                         dc->dcn_soc->max_dppclk_vmin0p65 * 1000,
1497                         dc->dcn_soc->socclk * 1000,
1498                         dc->dcn_soc->fabric_and_dram_bandwidth_vmax0p9 * 1000,
1499                         dc->dcn_soc->fabric_and_dram_bandwidth_vnom0p8 * 1000,
1500                         dc->dcn_soc->fabric_and_dram_bandwidth_vmid0p72 * 1000,
1501                         dc->dcn_soc->fabric_and_dram_bandwidth_vmin0p65 * 1000,
1502                         dc->dcn_soc->phyclkv_max0p9 * 1000,
1503                         dc->dcn_soc->phyclkv_nom0p8 * 1000,
1504                         dc->dcn_soc->phyclkv_mid0p72 * 1000,
1505                         dc->dcn_soc->phyclkv_min0p65 * 1000,
1506                         dc->dcn_soc->downspreading * 100,
1507                         dc->dcn_soc->round_trip_ping_latency_cycles,
1508                         dc->dcn_soc->urgent_out_of_order_return_per_channel,
1509                         dc->dcn_soc->number_of_channels,
1510                         dc->dcn_soc->vmm_page_size,
1511                         dc->dcn_soc->dram_clock_change_latency * 1000,
1512                         dc->dcn_soc->return_bus_width);
1513         DC_LOG_BANDWIDTH_CALCS("rob_buffer_size_in_kbyte: %d\n"
1514                         "det_buffer_size_in_kbyte: %d\n"
1515                         "dpp_output_buffer_pixels: %d\n"
1516                         "opp_output_buffer_lines: %d\n"
1517                         "pixel_chunk_size_in_kbyte: %d\n"
1518                         "pte_enable: %d\n"
1519                         "pte_chunk_size: %d kbytes\n"
1520                         "meta_chunk_size: %d kbytes\n"
1521                         "writeback_chunk_size: %d kbytes\n"
1522                         "odm_capability: %d\n"
1523                         "dsc_capability: %d\n"
1524                         "line_buffer_size: %d bits\n"
1525                         "max_line_buffer_lines: %d\n"
1526                         "is_line_buffer_bpp_fixed: %d\n"
1527                         "line_buffer_fixed_bpp: %d\n"
1528                         "writeback_luma_buffer_size: %d kbytes\n"
1529                         "writeback_chroma_buffer_size: %d kbytes\n"
1530                         "max_num_dpp: %d\n"
1531                         "max_num_writeback: %d\n"
1532                         "max_dchub_topscl_throughput: %d pixels/dppclk\n"
1533                         "max_pscl_tolb_throughput: %d pixels/dppclk\n"
1534                         "max_lb_tovscl_throughput: %d pixels/dppclk\n"
1535                         "max_vscl_tohscl_throughput: %d pixels/dppclk\n"
1536                         "max_hscl_ratio: %d\n"
1537                         "max_vscl_ratio: %d\n"
1538                         "max_hscl_taps: %d\n"
1539                         "max_vscl_taps: %d\n"
1540                         "pte_buffer_size_in_requests: %d\n"
1541                         "dispclk_ramping_margin: %d %\n"
1542                         "under_scan_factor: %d %\n"
1543                         "max_inter_dcn_tile_repeaters: %d\n"
1544                         "can_vstartup_lines_exceed_vsync_plus_back_porch_lines_minus_one: %d\n"
1545                         "bug_forcing_luma_and_chroma_request_to_same_size_fixed: %d\n"
1546                         "dcfclk_cstate_latency: %d\n",
1547                         dc->dcn_ip->rob_buffer_size_in_kbyte,
1548                         dc->dcn_ip->det_buffer_size_in_kbyte,
1549                         dc->dcn_ip->dpp_output_buffer_pixels,
1550                         dc->dcn_ip->opp_output_buffer_lines,
1551                         dc->dcn_ip->pixel_chunk_size_in_kbyte,
1552                         dc->dcn_ip->pte_enable,
1553                         dc->dcn_ip->pte_chunk_size,
1554                         dc->dcn_ip->meta_chunk_size,
1555                         dc->dcn_ip->writeback_chunk_size,
1556                         dc->dcn_ip->odm_capability,
1557                         dc->dcn_ip->dsc_capability,
1558                         dc->dcn_ip->line_buffer_size,
1559                         dc->dcn_ip->max_line_buffer_lines,
1560                         dc->dcn_ip->is_line_buffer_bpp_fixed,
1561                         dc->dcn_ip->line_buffer_fixed_bpp,
1562                         dc->dcn_ip->writeback_luma_buffer_size,
1563                         dc->dcn_ip->writeback_chroma_buffer_size,
1564                         dc->dcn_ip->max_num_dpp,
1565                         dc->dcn_ip->max_num_writeback,
1566                         dc->dcn_ip->max_dchub_topscl_throughput,
1567                         dc->dcn_ip->max_pscl_tolb_throughput,
1568                         dc->dcn_ip->max_lb_tovscl_throughput,
1569                         dc->dcn_ip->max_vscl_tohscl_throughput,
1570                         dc->dcn_ip->max_hscl_ratio,
1571                         dc->dcn_ip->max_vscl_ratio,
1572                         dc->dcn_ip->max_hscl_taps,
1573                         dc->dcn_ip->max_vscl_taps,
1574                         dc->dcn_ip->pte_buffer_size_in_requests,
1575                         dc->dcn_ip->dispclk_ramping_margin,
1576                         dc->dcn_ip->under_scan_factor * 100,
1577                         dc->dcn_ip->max_inter_dcn_tile_repeaters,
1578                         dc->dcn_ip->can_vstartup_lines_exceed_vsync_plus_back_porch_lines_minus_one,
1579                         dc->dcn_ip->bug_forcing_luma_and_chroma_request_to_same_size_fixed,
1580                         dc->dcn_ip->dcfclk_cstate_latency);
1581
1582         dc->dml.soc.sr_exit_time_us = dc->dcn_soc->sr_exit_time;
1583         dc->dml.soc.sr_enter_plus_exit_time_us = dc->dcn_soc->sr_enter_plus_exit_time;
1584         dc->dml.soc.urgent_latency_us = dc->dcn_soc->urgent_latency;
1585         dc->dml.soc.writeback_latency_us = dc->dcn_soc->write_back_latency;
1586         dc->dml.soc.ideal_dram_bw_after_urgent_percent =
1587                         dc->dcn_soc->percent_of_ideal_drambw_received_after_urg_latency;
1588         dc->dml.soc.max_request_size_bytes = dc->dcn_soc->max_request_size;
1589         dc->dml.soc.downspread_percent = dc->dcn_soc->downspreading;
1590         dc->dml.soc.round_trip_ping_latency_dcfclk_cycles =
1591                         dc->dcn_soc->round_trip_ping_latency_cycles;
1592         dc->dml.soc.urgent_out_of_order_return_per_channel_bytes =
1593                         dc->dcn_soc->urgent_out_of_order_return_per_channel;
1594         dc->dml.soc.num_chans = dc->dcn_soc->number_of_channels;
1595         dc->dml.soc.vmm_page_size_bytes = dc->dcn_soc->vmm_page_size;
1596         dc->dml.soc.dram_clock_change_latency_us = dc->dcn_soc->dram_clock_change_latency;
1597         dc->dml.soc.return_bus_width_bytes = dc->dcn_soc->return_bus_width;
1598
1599         dc->dml.ip.rob_buffer_size_kbytes = dc->dcn_ip->rob_buffer_size_in_kbyte;
1600         dc->dml.ip.det_buffer_size_kbytes = dc->dcn_ip->det_buffer_size_in_kbyte;
1601         dc->dml.ip.dpp_output_buffer_pixels = dc->dcn_ip->dpp_output_buffer_pixels;
1602         dc->dml.ip.opp_output_buffer_lines = dc->dcn_ip->opp_output_buffer_lines;
1603         dc->dml.ip.pixel_chunk_size_kbytes = dc->dcn_ip->pixel_chunk_size_in_kbyte;
1604         dc->dml.ip.pte_enable = dc->dcn_ip->pte_enable == dcn_bw_yes;
1605         dc->dml.ip.pte_chunk_size_kbytes = dc->dcn_ip->pte_chunk_size;
1606         dc->dml.ip.meta_chunk_size_kbytes = dc->dcn_ip->meta_chunk_size;
1607         dc->dml.ip.writeback_chunk_size_kbytes = dc->dcn_ip->writeback_chunk_size;
1608         dc->dml.ip.line_buffer_size_bits = dc->dcn_ip->line_buffer_size;
1609         dc->dml.ip.max_line_buffer_lines = dc->dcn_ip->max_line_buffer_lines;
1610         dc->dml.ip.IsLineBufferBppFixed = dc->dcn_ip->is_line_buffer_bpp_fixed == dcn_bw_yes;
1611         dc->dml.ip.LineBufferFixedBpp = dc->dcn_ip->line_buffer_fixed_bpp;
1612         dc->dml.ip.writeback_luma_buffer_size_kbytes = dc->dcn_ip->writeback_luma_buffer_size;
1613         dc->dml.ip.writeback_chroma_buffer_size_kbytes = dc->dcn_ip->writeback_chroma_buffer_size;
1614         dc->dml.ip.max_num_dpp = dc->dcn_ip->max_num_dpp;
1615         dc->dml.ip.max_num_wb = dc->dcn_ip->max_num_writeback;
1616         dc->dml.ip.max_dchub_pscl_bw_pix_per_clk = dc->dcn_ip->max_dchub_topscl_throughput;
1617         dc->dml.ip.max_pscl_lb_bw_pix_per_clk = dc->dcn_ip->max_pscl_tolb_throughput;
1618         dc->dml.ip.max_lb_vscl_bw_pix_per_clk = dc->dcn_ip->max_lb_tovscl_throughput;
1619         dc->dml.ip.max_vscl_hscl_bw_pix_per_clk = dc->dcn_ip->max_vscl_tohscl_throughput;
1620         dc->dml.ip.max_hscl_ratio = dc->dcn_ip->max_hscl_ratio;
1621         dc->dml.ip.max_vscl_ratio = dc->dcn_ip->max_vscl_ratio;
1622         dc->dml.ip.max_hscl_taps = dc->dcn_ip->max_hscl_taps;
1623         dc->dml.ip.max_vscl_taps = dc->dcn_ip->max_vscl_taps;
1624         /*pte_buffer_size_in_requests missing in dml*/
1625         dc->dml.ip.dispclk_ramp_margin_percent = dc->dcn_ip->dispclk_ramping_margin;
1626         dc->dml.ip.underscan_factor = dc->dcn_ip->under_scan_factor;
1627         dc->dml.ip.max_inter_dcn_tile_repeaters = dc->dcn_ip->max_inter_dcn_tile_repeaters;
1628         dc->dml.ip.can_vstartup_lines_exceed_vsync_plus_back_porch_lines_minus_one =
1629                 dc->dcn_ip->can_vstartup_lines_exceed_vsync_plus_back_porch_lines_minus_one == dcn_bw_yes;
1630         dc->dml.ip.bug_forcing_LC_req_same_size_fixed =
1631                 dc->dcn_ip->bug_forcing_luma_and_chroma_request_to_same_size_fixed == dcn_bw_yes;
1632         dc->dml.ip.dcfclk_cstate_latency = dc->dcn_ip->dcfclk_cstate_latency;
1633         kernel_fpu_end();
1634 }