2 * Copyright 2018 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
27 #include "clk_mgr_internal.h"
29 #include "dce100/dce_clk_mgr.h"
30 #include "reg_helper.h"
31 #include "core_types.h"
32 #include "dm_helpers.h"
34 #include "navi10_ip_offset.h"
35 #include "dcn/dcn_2_0_0_offset.h"
36 #include "dcn/dcn_2_0_0_sh_mask.h"
37 #include "clk/clk_11_0_0_offset.h"
38 #include "clk/clk_11_0_0_sh_mask.h"
41 #define FN(reg_name, field_name) \
42 clk_mgr->clk_mgr_shift->field_name, clk_mgr->clk_mgr_mask->field_name
47 #define BASE_INNER(seg) DCN_BASE__INST0_SEG ## seg
49 #define BASE(seg) BASE_INNER(seg)
52 .reg_name = BASE(mm ## reg_name ## _BASE_IDX) + \
55 #define CLK_BASE_INNER(seg) \
56 CLK_BASE__INST0_SEG ## seg
59 static const struct clk_mgr_registers clk_mgr_regs = {
63 static const struct clk_mgr_shift clk_mgr_shift = {
64 CLK_MASK_SH_LIST_NV10(__SHIFT)
67 static const struct clk_mgr_mask clk_mgr_mask = {
68 CLK_MASK_SH_LIST_NV10(_MASK)
71 uint32_t dentist_get_did_from_divider(int divider)
75 /* we want to floor here to get higher clock than required rather than lower */
76 if (divider < DENTIST_DIVIDER_RANGE_2_START) {
77 if (divider < DENTIST_DIVIDER_RANGE_1_START)
78 divider_id = DENTIST_BASE_DID_1;
80 divider_id = DENTIST_BASE_DID_1
81 + (divider - DENTIST_DIVIDER_RANGE_1_START)
82 / DENTIST_DIVIDER_RANGE_1_STEP;
83 } else if (divider < DENTIST_DIVIDER_RANGE_3_START) {
84 divider_id = DENTIST_BASE_DID_2
85 + (divider - DENTIST_DIVIDER_RANGE_2_START)
86 / DENTIST_DIVIDER_RANGE_2_STEP;
87 } else if (divider < DENTIST_DIVIDER_RANGE_4_START) {
88 divider_id = DENTIST_BASE_DID_3
89 + (divider - DENTIST_DIVIDER_RANGE_3_START)
90 / DENTIST_DIVIDER_RANGE_3_STEP;
92 divider_id = DENTIST_BASE_DID_4
93 + (divider - DENTIST_DIVIDER_RANGE_4_START)
94 / DENTIST_DIVIDER_RANGE_4_STEP;
95 if (divider_id > DENTIST_MAX_DID)
96 divider_id = DENTIST_MAX_DID;
102 void dcn20_update_clocks_update_dpp_dto(struct clk_mgr_internal *clk_mgr,
103 struct dc_state *context)
107 for (i = 0; i < clk_mgr->base.ctx->dc->res_pool->pipe_count; i++) {
108 int dpp_inst, dppclk_khz;
110 if (!context->res_ctx.pipe_ctx[i].plane_state)
113 dpp_inst = context->res_ctx.pipe_ctx[i].plane_res.dpp->inst;
114 dppclk_khz = context->res_ctx.pipe_ctx[i].plane_res.bw.dppclk_khz;
115 clk_mgr->dccg->funcs->update_dpp_dto(
116 clk_mgr->dccg, dpp_inst, dppclk_khz, false);
120 static void update_global_dpp_clk(struct clk_mgr_internal *clk_mgr, unsigned int khz)
122 int dpp_divider = DENTIST_DIVIDER_RANGE_SCALE_FACTOR
123 * clk_mgr->dentist_vco_freq_khz / khz;
125 uint32_t dppclk_wdivider = dentist_get_did_from_divider(dpp_divider);
127 REG_UPDATE(DENTIST_DISPCLK_CNTL,
128 DENTIST_DPPCLK_WDIVIDER, dppclk_wdivider);
129 REG_WAIT(DENTIST_DISPCLK_CNTL, DENTIST_DPPCLK_CHG_DONE, 1, 5, 100);
132 static void update_display_clk(struct clk_mgr_internal *clk_mgr, unsigned int khz)
134 int disp_divider = DENTIST_DIVIDER_RANGE_SCALE_FACTOR
135 * clk_mgr->dentist_vco_freq_khz / khz;
137 uint32_t dispclk_wdivider = dentist_get_did_from_divider(disp_divider);
139 REG_UPDATE(DENTIST_DISPCLK_CNTL,
140 DENTIST_DISPCLK_WDIVIDER, dispclk_wdivider);
143 static void request_voltage_and_program_disp_clk(struct clk_mgr *clk_mgr_base, unsigned int khz)
145 struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);
146 struct dc *dc = clk_mgr_base->ctx->dc;
147 struct pp_smu_funcs_nv *pp_smu = NULL;
148 bool going_up = clk_mgr->base.clks.dispclk_khz < khz;
150 if (dc->res_pool->pp_smu)
151 pp_smu = &dc->res_pool->pp_smu->nv_funcs;
153 clk_mgr->base.clks.dispclk_khz = khz;
155 if (going_up && pp_smu && pp_smu->set_voltage_by_freq)
156 pp_smu->set_voltage_by_freq(&pp_smu->pp_smu, PP_SMU_NV_DISPCLK, clk_mgr_base->clks.dispclk_khz / 1000);
158 update_display_clk(clk_mgr, khz);
160 if (!going_up && pp_smu && pp_smu->set_voltage_by_freq)
161 pp_smu->set_voltage_by_freq(&pp_smu->pp_smu, PP_SMU_NV_DISPCLK, clk_mgr_base->clks.dispclk_khz / 1000);
164 static void request_voltage_and_program_global_dpp_clk(struct clk_mgr *clk_mgr_base, unsigned int khz)
166 struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);
167 struct dc *dc = clk_mgr_base->ctx->dc;
168 struct pp_smu_funcs_nv *pp_smu = NULL;
169 bool going_up = clk_mgr->base.clks.dppclk_khz < khz;
171 if (dc->res_pool->pp_smu)
172 pp_smu = &dc->res_pool->pp_smu->nv_funcs;
174 clk_mgr->base.clks.dppclk_khz = khz;
175 clk_mgr->dccg->ref_dppclk = khz;
177 if (going_up && pp_smu && pp_smu->set_voltage_by_freq)
178 pp_smu->set_voltage_by_freq(&pp_smu->pp_smu, PP_SMU_NV_PIXELCLK, clk_mgr_base->clks.dppclk_khz / 1000);
180 update_global_dpp_clk(clk_mgr, khz);
182 if (!going_up && pp_smu && pp_smu->set_voltage_by_freq)
183 pp_smu->set_voltage_by_freq(&pp_smu->pp_smu, PP_SMU_NV_PIXELCLK, clk_mgr_base->clks.dppclk_khz / 1000);
186 void dcn2_update_clocks(struct clk_mgr *clk_mgr_base,
187 struct dc_state *context,
190 struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);
191 struct dc_clocks *new_clocks = &context->bw_ctx.bw.dcn.clk;
192 struct dc *dc = clk_mgr_base->ctx->dc;
193 struct pp_smu_funcs_nv *pp_smu = NULL;
195 bool update_dispclk = false;
196 bool enter_display_off = false;
197 struct dmcu *dmcu = clk_mgr_base->ctx->dc->res_pool->dmcu;
198 bool force_reset = false;
201 if (dc->work_arounds.skip_clock_update)
204 if (clk_mgr_base->clks.dispclk_khz == 0 ||
205 dc->debug.force_clock_mode & 0x1) {
206 //this is from resume or boot up, if forced_clock cfg option used, we bypass program dispclk and DPPCLK, but need set them for S3.
208 //force_clock_mode 0x1: force reset the clock even it is the same clock as long as it is in Passive level.
210 display_count = clk_mgr_helper_get_active_display_cnt(dc, context);
211 if (dc->res_pool->pp_smu)
212 pp_smu = &dc->res_pool->pp_smu->nv_funcs;
214 if (display_count == 0)
215 enter_display_off = true;
217 if (enter_display_off == safe_to_lower) {
218 if (pp_smu && pp_smu->set_display_count)
219 pp_smu->set_display_count(&pp_smu->pp_smu, display_count);
222 if (should_set_clock(safe_to_lower, new_clocks->phyclk_khz, clk_mgr_base->clks.phyclk_khz)) {
223 clk_mgr_base->clks.phyclk_khz = new_clocks->phyclk_khz;
224 if (pp_smu && pp_smu->set_voltage_by_freq)
225 pp_smu->set_voltage_by_freq(&pp_smu->pp_smu, PP_SMU_NV_PHYCLK, clk_mgr_base->clks.phyclk_khz / 1000);
229 if (dc->debug.force_min_dcfclk_mhz > 0)
230 new_clocks->dcfclk_khz = (new_clocks->dcfclk_khz > (dc->debug.force_min_dcfclk_mhz * 1000)) ?
231 new_clocks->dcfclk_khz : (dc->debug.force_min_dcfclk_mhz * 1000);
233 if (should_set_clock(safe_to_lower, new_clocks->dcfclk_khz, clk_mgr_base->clks.dcfclk_khz)) {
234 clk_mgr_base->clks.dcfclk_khz = new_clocks->dcfclk_khz;
235 if (pp_smu && pp_smu->set_hard_min_dcfclk_by_freq)
236 pp_smu->set_hard_min_dcfclk_by_freq(&pp_smu->pp_smu, clk_mgr_base->clks.dcfclk_khz / 1000);
239 if (should_set_clock(safe_to_lower,
240 new_clocks->dcfclk_deep_sleep_khz, clk_mgr_base->clks.dcfclk_deep_sleep_khz)) {
241 clk_mgr_base->clks.dcfclk_deep_sleep_khz = new_clocks->dcfclk_deep_sleep_khz;
242 if (pp_smu && pp_smu->set_min_deep_sleep_dcfclk)
243 pp_smu->set_min_deep_sleep_dcfclk(&pp_smu->pp_smu, clk_mgr_base->clks.dcfclk_deep_sleep_khz / 1000);
246 if (should_set_clock(safe_to_lower, new_clocks->socclk_khz, clk_mgr_base->clks.socclk_khz)) {
247 clk_mgr_base->clks.socclk_khz = new_clocks->socclk_khz;
248 if (pp_smu && pp_smu->set_hard_min_socclk_by_freq)
249 pp_smu->set_hard_min_socclk_by_freq(&pp_smu->pp_smu, clk_mgr_base->clks.socclk_khz / 1000);
252 if (should_update_pstate_support(safe_to_lower, new_clocks->p_state_change_support, clk_mgr_base->clks.p_state_change_support)) {
253 clk_mgr_base->clks.prev_p_state_change_support = clk_mgr_base->clks.p_state_change_support;
255 clk_mgr_base->clks.p_state_change_support = new_clocks->p_state_change_support;
256 if (pp_smu && pp_smu->set_pstate_handshake_support)
257 pp_smu->set_pstate_handshake_support(&pp_smu->pp_smu, clk_mgr_base->clks.p_state_change_support);
259 clk_mgr_base->clks.prev_p_state_change_support = clk_mgr_base->clks.p_state_change_support;
261 if (should_set_clock(safe_to_lower, new_clocks->dramclk_khz, clk_mgr_base->clks.dramclk_khz)) {
262 clk_mgr_base->clks.dramclk_khz = new_clocks->dramclk_khz;
263 if (pp_smu && pp_smu->set_hard_min_uclk_by_freq)
264 pp_smu->set_hard_min_uclk_by_freq(&pp_smu->pp_smu, clk_mgr_base->clks.dramclk_khz / 1000);
267 if (dc->config.forced_clocks == false) {
268 // First update display clock
269 if (should_set_clock(safe_to_lower, new_clocks->dispclk_khz, clk_mgr_base->clks.dispclk_khz))
270 request_voltage_and_program_disp_clk(clk_mgr_base, new_clocks->dispclk_khz);
272 // Updating DPP clock requires some more logic
273 if (!safe_to_lower) {
274 // For pre-programming, we need to make sure any DPP clock that will go up has to go up
276 // First raise the global reference if needed
277 if (new_clocks->dppclk_khz > clk_mgr_base->clks.dppclk_khz)
278 request_voltage_and_program_global_dpp_clk(clk_mgr_base, new_clocks->dppclk_khz);
280 // Then raise any dividers that need raising
281 for (i = 0; i < clk_mgr->base.ctx->dc->res_pool->pipe_count; i++) {
282 int dpp_inst, dppclk_khz;
284 if (!context->res_ctx.pipe_ctx[i].plane_state)
287 dpp_inst = context->res_ctx.pipe_ctx[i].plane_res.dpp->inst;
288 dppclk_khz = context->res_ctx.pipe_ctx[i].plane_res.bw.dppclk_khz;
290 clk_mgr->dccg->funcs->update_dpp_dto(clk_mgr->dccg, dpp_inst, dppclk_khz, true);
293 // For post-programming, we can lower ref clk if needed, and unconditionally set all the DTOs
295 if (new_clocks->dppclk_khz < clk_mgr_base->clks.dppclk_khz)
296 request_voltage_and_program_global_dpp_clk(clk_mgr_base, new_clocks->dppclk_khz);
298 for (i = 0; i < clk_mgr->base.ctx->dc->res_pool->pipe_count; i++) {
299 int dpp_inst, dppclk_khz;
301 if (!context->res_ctx.pipe_ctx[i].plane_state)
304 dpp_inst = context->res_ctx.pipe_ctx[i].plane_res.dpp->inst;
305 dppclk_khz = context->res_ctx.pipe_ctx[i].plane_res.bw.dppclk_khz;
307 clk_mgr->dccg->funcs->update_dpp_dto(clk_mgr->dccg, dpp_inst, dppclk_khz, false);
311 if (update_dispclk &&
312 dmcu && dmcu->funcs->is_dmcu_initialized(dmcu)) {
313 /*update dmcu for wait_loop count*/
314 dmcu->funcs->set_psr_wait_loop(dmcu,
315 clk_mgr_base->clks.dispclk_khz / 1000 / 7);
319 void dcn2_update_clocks_fpga(struct clk_mgr *clk_mgr,
320 struct dc_state *context,
323 struct dc_clocks *new_clocks = &context->bw_ctx.bw.dcn.clk;
324 /* Min fclk = 1.2GHz since all the extra scemi logic seems to run off of it */
325 int fclk_adj = new_clocks->fclk_khz > 1200000 ? new_clocks->fclk_khz : 1200000;
327 if (should_set_clock(safe_to_lower, new_clocks->phyclk_khz, clk_mgr->clks.phyclk_khz)) {
328 clk_mgr->clks.phyclk_khz = new_clocks->phyclk_khz;
331 if (should_set_clock(safe_to_lower, new_clocks->dcfclk_khz, clk_mgr->clks.dcfclk_khz)) {
332 clk_mgr->clks.dcfclk_khz = new_clocks->dcfclk_khz;
335 if (should_set_clock(safe_to_lower,
336 new_clocks->dcfclk_deep_sleep_khz, clk_mgr->clks.dcfclk_deep_sleep_khz)) {
337 clk_mgr->clks.dcfclk_deep_sleep_khz = new_clocks->dcfclk_deep_sleep_khz;
340 if (should_set_clock(safe_to_lower, new_clocks->socclk_khz, clk_mgr->clks.socclk_khz)) {
341 clk_mgr->clks.socclk_khz = new_clocks->socclk_khz;
344 if (should_set_clock(safe_to_lower, new_clocks->dramclk_khz, clk_mgr->clks.dramclk_khz)) {
345 clk_mgr->clks.dramclk_khz = new_clocks->dramclk_khz;
348 if (should_set_clock(safe_to_lower, new_clocks->dppclk_khz, clk_mgr->clks.dppclk_khz)) {
349 clk_mgr->clks.dppclk_khz = new_clocks->dppclk_khz;
352 if (should_set_clock(safe_to_lower, fclk_adj, clk_mgr->clks.fclk_khz)) {
353 clk_mgr->clks.fclk_khz = fclk_adj;
356 if (should_set_clock(safe_to_lower, new_clocks->dispclk_khz, clk_mgr->clks.dispclk_khz)) {
357 clk_mgr->clks.dispclk_khz = new_clocks->dispclk_khz;
360 /* Both fclk and dppclk ref are run on the same scemi clock so we
361 * need to keep the same value for both
363 if (clk_mgr->clks.fclk_khz > clk_mgr->clks.dppclk_khz)
364 clk_mgr->clks.dppclk_khz = clk_mgr->clks.fclk_khz;
365 if (clk_mgr->clks.dppclk_khz > clk_mgr->clks.fclk_khz)
366 clk_mgr->clks.fclk_khz = clk_mgr->clks.dppclk_khz;
368 dm_set_dcn_clocks(clk_mgr->ctx, &clk_mgr->clks);
371 void dcn2_init_clocks(struct clk_mgr *clk_mgr)
373 memset(&(clk_mgr->clks), 0, sizeof(struct dc_clocks));
374 // Assumption is that boot state always supports pstate
375 clk_mgr->clks.p_state_change_support = true;
376 clk_mgr->clks.prev_p_state_change_support = true;
379 void dcn2_enable_pme_wa(struct clk_mgr *clk_mgr_base)
381 struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);
382 struct pp_smu_funcs_nv *pp_smu = NULL;
384 if (clk_mgr->pp_smu) {
385 pp_smu = &clk_mgr->pp_smu->nv_funcs;
387 if (pp_smu->set_pme_wa_enable)
388 pp_smu->set_pme_wa_enable(&pp_smu->pp_smu);
392 void dcn2_get_clock(struct clk_mgr *clk_mgr,
393 struct dc_state *context,
394 enum dc_clock_type clock_type,
395 struct dc_clock_config *clock_cfg)
398 if (clock_type == DC_CLOCK_TYPE_DISPCLK) {
399 clock_cfg->max_clock_khz = context->bw_ctx.bw.dcn.clk.max_supported_dispclk_khz;
400 clock_cfg->min_clock_khz = DCN_MINIMUM_DISPCLK_Khz;
401 clock_cfg->current_clock_khz = clk_mgr->clks.dispclk_khz;
402 clock_cfg->bw_requirequired_clock_khz = context->bw_ctx.bw.dcn.clk.bw_dispclk_khz;
404 if (clock_type == DC_CLOCK_TYPE_DPPCLK) {
405 clock_cfg->max_clock_khz = context->bw_ctx.bw.dcn.clk.max_supported_dppclk_khz;
406 clock_cfg->min_clock_khz = DCN_MINIMUM_DPPCLK_Khz;
407 clock_cfg->current_clock_khz = clk_mgr->clks.dppclk_khz;
408 clock_cfg->bw_requirequired_clock_khz = context->bw_ctx.bw.dcn.clk.bw_dppclk_khz;
412 static struct clk_mgr_funcs dcn2_funcs = {
413 .get_dp_ref_clk_frequency = dce12_get_dp_ref_freq_khz,
414 .update_clocks = dcn2_update_clocks,
415 .init_clocks = dcn2_init_clocks,
416 .enable_pme_wa = dcn2_enable_pme_wa,
417 .get_clock = dcn2_get_clock,
421 void dcn20_clk_mgr_construct(
422 struct dc_context *ctx,
423 struct clk_mgr_internal *clk_mgr,
424 struct pp_smu_funcs *pp_smu,
427 clk_mgr->base.ctx = ctx;
428 clk_mgr->pp_smu = pp_smu;
429 clk_mgr->base.funcs = &dcn2_funcs;
430 clk_mgr->regs = &clk_mgr_regs;
431 clk_mgr->clk_mgr_shift = &clk_mgr_shift;
432 clk_mgr->clk_mgr_mask = &clk_mgr_mask;
434 clk_mgr->dccg = dccg;
435 clk_mgr->dfs_bypass_disp_clk = 0;
437 clk_mgr->dprefclk_ss_percentage = 0;
438 clk_mgr->dprefclk_ss_divider = 1000;
439 clk_mgr->ss_on_dprefclk = false;
441 clk_mgr->base.dprefclk_khz = 700000; // 700 MHz planned if VCO is 3.85 GHz, will be retrieved
443 if (IS_FPGA_MAXIMUS_DC(ctx->dce_environment)) {
444 dcn2_funcs.update_clocks = dcn2_update_clocks_fpga;
445 clk_mgr->dentist_vco_freq_khz = 3850000;
448 /* DFS Slice 2 should be used for DPREFCLK */
449 int dprefclk_did = REG_READ(CLK3_CLK2_DFS_CNTL);
450 /* Convert DPREFCLK DFS Slice DID to actual divider*/
451 int target_div = dentist_get_divider_from_did(dprefclk_did);
453 /* get FbMult value */
454 uint32_t pll_req_reg = REG_READ(CLK3_CLK_PLL_REQ);
455 struct fixed31_32 pll_req;
457 /* set up a fixed-point number
458 * this works because the int part is on the right edge of the register
459 * and the frac part is on the left edge
462 pll_req = dc_fixpt_from_int(pll_req_reg & clk_mgr->clk_mgr_mask->FbMult_int);
463 pll_req.value |= pll_req_reg & clk_mgr->clk_mgr_mask->FbMult_frac;
465 /* multiply by REFCLK period */
466 pll_req = dc_fixpt_mul_int(pll_req, 100000);
468 /* integer part is now VCO frequency in kHz */
469 clk_mgr->dentist_vco_freq_khz = dc_fixpt_floor(pll_req);
471 /* in case we don't get a value from the register, use default */
472 if (clk_mgr->dentist_vco_freq_khz == 0)
473 clk_mgr->dentist_vco_freq_khz = 3850000;
475 /* Calculate the DPREFCLK in kHz.*/
476 clk_mgr->base.dprefclk_khz = (DENTIST_DIVIDER_RANGE_SCALE_FACTOR
477 * clk_mgr->dentist_vco_freq_khz) / target_div;
479 //Integrated_info table does not exist on dGPU projects so should not be referenced
480 //anywhere in code for dGPUs.
481 //Also there is no plan for now that DFS BYPASS will be used on NV10/12/14.
482 clk_mgr->dfs_bypass_enabled = false;
484 dce_clock_read_ss_info(clk_mgr);