drivers/gpu/drm/amd/display/dc/core/dc.c

   1 /*
   2  * Copyright 2015 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: AMD
  23  */
  24
  25 #include "dm_services.h"
  26
  27 #include "dc.h"
  28
  29 #include "core_status.h"
  30 #include "core_types.h"
  31 #include "hw_sequencer.h"
  32 #include "dce/dce_hwseq.h"
  33
  34 #include "resource.h"
  35
  36 #include "clock_source.h"
  37 #include "dc_bios_types.h"
  38
  39 #include "bios_parser_interface.h"
  40 #include "include/irq_service_interface.h"
  41 #include "transform.h"
  42 #include "dmcu.h"
  43 #include "dpp.h"
  44 #include "timing_generator.h"
  45 #include "abm.h"
  46 #include "virtual/virtual_link_encoder.h"
  47
  48 #include "link_hwss.h"
  49 #include "link_encoder.h"
  50
  51 #include "dc_link_ddc.h"
  52 #include "dm_helpers.h"
  53 #include "mem_input.h"
  54 #include "hubp.h"
  55
  56 #include "dc_link_dp.h"
  57
  58 #include "dce/dce_i2c.h"
  59
  60 #define DC_LOGGER \
  61         dc->ctx->logger
  62
  63 const static char DC_BUILD_ID[] = "production-build";
  64
  65 /**
  66  * DOC: Overview
  67  *
  68  * DC is the OS-agnostic component of the amdgpu DC driver.
  69  *
  70  * DC maintains and validates a set of structs representing the state of the
  71  * driver and writes that state to AMD hardware
  72  *
  73  * Main DC HW structs:
  74  *
  75  * struct dc - The central struct.  One per driver.  Created on driver load,
  76  * destroyed on driver unload.
  77  *
  78  * struct dc_context - One per driver.
  79  * Used as a backpointer by most other structs in dc.
  80  *
  81  * struct dc_link - One per connector (the physical DP, HDMI, miniDP, or eDP
  82  * plugpoints).  Created on driver load, destroyed on driver unload.
  83  *
  84  * struct dc_sink - One per display.  Created on boot or hotplug.
  85  * Destroyed on shutdown or hotunplug.  A dc_link can have a local sink
  86  * (the display directly attached).  It may also have one or more remote
  87  * sinks (in the Multi-Stream Transport case)
  88  *
  89  * struct resource_pool - One per driver.  Represents the hw blocks not in the
  90  * main pipeline.  Not directly accessible by dm.
  91  *
  92  * Main dc state structs:
  93  *
  94  * These structs can be created and destroyed as needed.  There is a full set of
  95  * these structs in dc->current_state representing the currently programmed state.
  96  *
  97  * struct dc_state - The global DC state to track global state information,
  98  * such as bandwidth values.
  99  *
 100  * struct dc_stream_state - Represents the hw configuration for the pipeline from
 101  * a framebuffer to a display.  Maps one-to-one with dc_sink.
 102  *
 103  * struct dc_plane_state - Represents a framebuffer.  Each stream has at least one,
 104  * and may have more in the Multi-Plane Overlay case.
 105  *
 106  * struct resource_context - Represents the programmable state of everything in
 107  * the resource_pool.  Not directly accessible by dm.
 108  *
 109  * struct pipe_ctx - A member of struct resource_context.  Represents the
 110  * internal hardware pipeline components.  Each dc_plane_state has either
 111  * one or two (in the pipe-split case).
 112  */
 113
 114 /*******************************************************************************
 115  * Private functions
 116  ******************************************************************************/
 117
 118 static inline void elevate_update_type(enum surface_update_type *original, enum surface_update_type new)
 119 {
 120         if (new > *original)
 121                 *original = new;
 122 }
 123
 124 static void destroy_links(struct dc *dc)
 125 {
 126         uint32_t i;
 127
 128         for (i = 0; i < dc->link_count; i++) {
 129                 if (NULL != dc->links[i])
 130                         link_destroy(&dc->links[i]);
 131         }
 132 }
 133
 134 static bool create_links(
 135                 struct dc *dc,
 136                 uint32_t num_virtual_links)
 137 {
 138         int i;
 139         int connectors_num;
 140         struct dc_bios *bios = dc->ctx->dc_bios;
 141
 142         dc->link_count = 0;
 143
 144         connectors_num = bios->funcs->get_connectors_number(bios);
 145
 146         if (connectors_num > ENUM_ID_COUNT) {
 147                 dm_error(
 148                         "DC: Number of connectors %d exceeds maximum of %d!\n",
 149                         connectors_num,
 150                         ENUM_ID_COUNT);
 151                 return false;
 152         }
 153
 154         dm_output_to_console(
 155                 "DC: %s: connectors_num: physical:%d, virtual:%d\n",
 156                 __func__,
 157                 connectors_num,
 158                 num_virtual_links);
 159
 160         for (i = 0; i < connectors_num; i++) {
 161                 struct link_init_data link_init_params = {0};
 162                 struct dc_link *link;
 163
 164                 link_init_params.ctx = dc->ctx;
 165                 /* next BIOS object table connector */
 166                 link_init_params.connector_index = i;
 167                 link_init_params.link_index = dc->link_count;
 168                 link_init_params.dc = dc;
 169                 link = link_create(&link_init_params);
 170
 171                 if (link) {
 172                         dc->links[dc->link_count] = link;
 173                         link->dc = dc;
 174                         ++dc->link_count;
 175                 }
 176         }
 177
 178         for (i = 0; i < num_virtual_links; i++) {
 179                 struct dc_link *link = kzalloc(sizeof(*link), GFP_KERNEL);
 180                 struct encoder_init_data enc_init = {0};
 181
 182                 if (link == NULL) {
 183                         BREAK_TO_DEBUGGER();
 184                         goto failed_alloc;
 185                 }
 186
 187                 link->link_index = dc->link_count;
 188                 dc->links[dc->link_count] = link;
 189                 dc->link_count++;
 190
 191                 link->ctx = dc->ctx;
 192                 link->dc = dc;
 193                 link->connector_signal = SIGNAL_TYPE_VIRTUAL;
 194                 link->link_id.type = OBJECT_TYPE_CONNECTOR;
 195                 link->link_id.id = CONNECTOR_ID_VIRTUAL;
 196                 link->link_id.enum_id = ENUM_ID_1;
 197                 link->link_enc = kzalloc(sizeof(*link->link_enc), GFP_KERNEL);
 198
 199                 if (!link->link_enc) {
 200                         BREAK_TO_DEBUGGER();
 201                         goto failed_alloc;
 202                 }
 203
 204                 link->link_status.dpcd_caps = &link->dpcd_caps;
 205
 206                 enc_init.ctx = dc->ctx;
 207                 enc_init.channel = CHANNEL_ID_UNKNOWN;
 208                 enc_init.hpd_source = HPD_SOURCEID_UNKNOWN;
 209                 enc_init.transmitter = TRANSMITTER_UNKNOWN;
 210                 enc_init.connector = link->link_id;
 211                 enc_init.encoder.type = OBJECT_TYPE_ENCODER;
 212                 enc_init.encoder.id = ENCODER_ID_INTERNAL_VIRTUAL;
 213                 enc_init.encoder.enum_id = ENUM_ID_1;
 214                 virtual_link_encoder_construct(link->link_enc, &enc_init);
 215         }
 216
 217         return true;
 218
 219 failed_alloc:
 220         return false;
 221 }
 222
 223 static struct dc_perf_trace *dc_perf_trace_create(void)
 224 {
 225         return kzalloc(sizeof(struct dc_perf_trace), GFP_KERNEL);
 226 }
 227
 228 static void dc_perf_trace_destroy(struct dc_perf_trace **perf_trace)
 229 {
 230         kfree(*perf_trace);
 231         *perf_trace = NULL;
 232 }
 233
 234 /**
 235  *****************************************************************************
 236  *  Function: dc_stream_adjust_vmin_vmax
 237  *
 238  *  @brief
 239  *     Looks up the pipe context of dc_stream_state and updates the
 240  *     vertical_total_min and vertical_total_max of the DRR, Dynamic Refresh
 241  *     Rate, which is a power-saving feature that targets reducing panel
 242  *     refresh rate while the screen is static
 243  *
 244  *  @param [in] dc: dc reference
 245  *  @param [in] stream: Initial dc stream state
 246  *  @param [in] adjust: Updated parameters for vertical_total_min and
 247  *  vertical_total_max
 248  *****************************************************************************
 249  */
 250 bool dc_stream_adjust_vmin_vmax(struct dc *dc,
 251                 struct dc_stream_state *stream,
 252                 struct dc_crtc_timing_adjust *adjust)
 253 {
 254         int i = 0;
 255         bool ret = false;
 256
 257         for (i = 0; i < MAX_PIPES; i++) {
 258                 struct pipe_ctx *pipe = &dc->current_state->res_ctx.pipe_ctx[i];
 259
 260                 if (pipe->stream == stream && pipe->stream_res.stream_enc) {
 261                         pipe->stream->adjust = *adjust;
 262                         dc->hwss.set_drr(&pipe,
 263                                         1,
 264                                         adjust->v_total_min,
 265                                         adjust->v_total_max);
 266
 267                         ret = true;
 268                 }
 269         }
 270         return ret;
 271 }
 272
 273 bool dc_stream_get_crtc_position(struct dc *dc,
 274                 struct dc_stream_state **streams, int num_streams,
 275                 unsigned int *v_pos, unsigned int *nom_v_pos)
 276 {
 277         /* TODO: Support multiple streams */
 278         const struct dc_stream_state *stream = streams[0];
 279         int i = 0;
 280         bool ret = false;
 281         struct crtc_position position;
 282
 283         for (i = 0; i < MAX_PIPES; i++) {
 284                 struct pipe_ctx *pipe =
 285                                 &dc->current_state->res_ctx.pipe_ctx[i];
 286
 287                 if (pipe->stream == stream && pipe->stream_res.stream_enc) {
 288                         dc->hwss.get_position(&pipe, 1, &position);
 289
 290                         *v_pos = position.vertical_count;
 291                         *nom_v_pos = position.nominal_vcount;
 292                         ret = true;
 293                 }
 294         }
 295         return ret;
 296 }
 297
 298 /**
 299  * dc_stream_configure_crc() - Configure CRC capture for the given stream.
 300  * @dc: DC Object
 301  * @stream: The stream to configure CRC on.
 302  * @enable: Enable CRC if true, disable otherwise.
 303  * @continuous: Capture CRC on every frame if true. Otherwise, only capture
 304  *              once.
 305  *
 306  * By default, only CRC0 is configured, and the entire frame is used to
 307  * calculate the crc.
 308  */
 309 bool dc_stream_configure_crc(struct dc *dc, struct dc_stream_state *stream,
 310                              bool enable, bool continuous)
 311 {
 312         int i;
 313         struct pipe_ctx *pipe;
 314         struct crc_params param;
 315         struct timing_generator *tg;
 316
 317         for (i = 0; i < MAX_PIPES; i++) {
 318                 pipe = &dc->current_state->res_ctx.pipe_ctx[i];
 319                 if (pipe->stream == stream)
 320                         break;
 321         }
 322         /* Stream not found */
 323         if (i == MAX_PIPES)
 324                 return false;
 325
 326         /* Always capture the full frame */
 327         param.windowa_x_start = 0;
 328         param.windowa_y_start = 0;
 329         param.windowa_x_end = pipe->stream->timing.h_addressable;
 330         param.windowa_y_end = pipe->stream->timing.v_addressable;
 331         param.windowb_x_start = 0;
 332         param.windowb_y_start = 0;
 333         param.windowb_x_end = pipe->stream->timing.h_addressable;
 334         param.windowb_y_end = pipe->stream->timing.v_addressable;
 335
 336         /* Default to the union of both windows */
 337         param.selection = UNION_WINDOW_A_B;
 338         param.continuous_mode = continuous;
 339         param.enable = enable;
 340
 341         tg = pipe->stream_res.tg;
 342
 343         /* Only call if supported */
 344         if (tg->funcs->configure_crc)
 345                 return tg->funcs->configure_crc(tg, &param);
 346         DC_LOG_WARNING("CRC capture not supported.");
 347         return false;
 348 }
 349
 350 /**
 351  * dc_stream_get_crc() - Get CRC values for the given stream.
 352  * @dc: DC object
 353  * @stream: The DC stream state of the stream to get CRCs from.
 354  * @r_cr, g_y, b_cb: CRC values for the three channels are stored here.
 355  *
 356  * dc_stream_configure_crc needs to be called beforehand to enable CRCs.
 357  * Return false if stream is not found, or if CRCs are not enabled.
 358  */
 359 bool dc_stream_get_crc(struct dc *dc, struct dc_stream_state *stream,
 360                        uint32_t *r_cr, uint32_t *g_y, uint32_t *b_cb)
 361 {
 362         int i;
 363         struct pipe_ctx *pipe;
 364         struct timing_generator *tg;
 365
 366         for (i = 0; i < MAX_PIPES; i++) {
 367                 pipe = &dc->current_state->res_ctx.pipe_ctx[i];
 368                 if (pipe->stream == stream)
 369                         break;
 370         }
 371         /* Stream not found */
 372         if (i == MAX_PIPES)
 373                 return false;
 374
 375         tg = pipe->stream_res.tg;
 376
 377         if (tg->funcs->get_crc)
 378                 return tg->funcs->get_crc(tg, r_cr, g_y, b_cb);
 379         DC_LOG_WARNING("CRC capture not supported.");
 380         return false;
 381 }
 382
 383 void dc_stream_set_dither_option(struct dc_stream_state *stream,
 384                 enum dc_dither_option option)
 385 {
 386         struct bit_depth_reduction_params params;
 387         struct dc_link *link = stream->link;
 388         struct pipe_ctx *pipes = NULL;
 389         int i;
 390
 391         for (i = 0; i < MAX_PIPES; i++) {
 392                 if (link->dc->current_state->res_ctx.pipe_ctx[i].stream ==
 393                                 stream) {
 394                         pipes = &link->dc->current_state->res_ctx.pipe_ctx[i];
 395                         break;
 396                 }
 397         }
 398
 399         if (!pipes)
 400                 return;
 401         if (option > DITHER_OPTION_MAX)
 402                 return;
 403
 404         stream->dither_option = option;
 405
 406         memset(&params, 0, sizeof(params));
 407         resource_build_bit_depth_reduction_params(stream, &params);
 408         stream->bit_depth_params = params;
 409
 410         if (pipes->plane_res.xfm &&
 411             pipes->plane_res.xfm->funcs->transform_set_pixel_storage_depth) {
 412                 pipes->plane_res.xfm->funcs->transform_set_pixel_storage_depth(
 413                         pipes->plane_res.xfm,
 414                         pipes->plane_res.scl_data.lb_params.depth,
 415                         &stream->bit_depth_params);
 416         }
 417
 418         pipes->stream_res.opp->funcs->
 419                 opp_program_bit_depth_reduction(pipes->stream_res.opp, &params);
 420 }
 421
 422 bool dc_stream_set_gamut_remap(struct dc *dc, const struct dc_stream_state *stream)
 423 {
 424         int i = 0;
 425         bool ret = false;
 426         struct pipe_ctx *pipes;
 427
 428         for (i = 0; i < MAX_PIPES; i++) {
 429                 if (dc->current_state->res_ctx.pipe_ctx[i].stream == stream) {
 430                         pipes = &dc->current_state->res_ctx.pipe_ctx[i];
 431                         dc->hwss.program_gamut_remap(pipes);
 432                         ret = true;
 433                 }
 434         }
 435
 436         return ret;
 437 }
 438
 439 bool dc_stream_program_csc_matrix(struct dc *dc, struct dc_stream_state *stream)
 440 {
 441         int i = 0;
 442         bool ret = false;
 443         struct pipe_ctx *pipes;
 444
 445         for (i = 0; i < MAX_PIPES; i++) {
 446                 if (dc->current_state->res_ctx.pipe_ctx[i].stream
 447                                 == stream) {
 448
 449                         pipes = &dc->current_state->res_ctx.pipe_ctx[i];
 450                         dc->hwss.program_output_csc(dc,
 451                                         pipes,
 452                                         stream->output_color_space,
 453                                         stream->csc_color_matrix.matrix,
 454                                         pipes->plane_res.hubp ? pipes->plane_res.hubp->opp_id : 0);
 455                         ret = true;
 456                 }
 457         }
 458
 459         return ret;
 460 }
 461
 462 void dc_stream_set_static_screen_events(struct dc *dc,
 463                 struct dc_stream_state **streams,
 464                 int num_streams,
 465                 const struct dc_static_screen_events *events)
 466 {
 467         int i = 0;
 468         int j = 0;
 469         struct pipe_ctx *pipes_affected[MAX_PIPES];
 470         int num_pipes_affected = 0;
 471
 472         for (i = 0; i < num_streams; i++) {
 473                 struct dc_stream_state *stream = streams[i];
 474
 475                 for (j = 0; j < MAX_PIPES; j++) {
 476                         if (dc->current_state->res_ctx.pipe_ctx[j].stream
 477                                         == stream) {
 478                                 pipes_affected[num_pipes_affected++] =
 479                                                 &dc->current_state->res_ctx.pipe_ctx[j];
 480                         }
 481                 }
 482         }
 483
 484         dc->hwss.set_static_screen_control(pipes_affected, num_pipes_affected, events);
 485 }
 486
 487 void dc_link_set_drive_settings(struct dc *dc,
 488                                 struct link_training_settings *lt_settings,
 489                                 const struct dc_link *link)
 490 {
 491
 492         int i;
 493
 494         for (i = 0; i < dc->link_count; i++) {
 495                 if (dc->links[i] == link)
 496                         break;
 497         }
 498
 499         if (i >= dc->link_count)
 500                 ASSERT_CRITICAL(false);
 501
 502         dc_link_dp_set_drive_settings(dc->links[i], lt_settings);
 503 }
 504
 505 void dc_link_perform_link_training(struct dc *dc,
 506                                    struct dc_link_settings *link_setting,
 507                                    bool skip_video_pattern)
 508 {
 509         int i;
 510
 511         for (i = 0; i < dc->link_count; i++)
 512                 dc_link_dp_perform_link_training(
 513                         dc->links[i],
 514                         link_setting,
 515                         skip_video_pattern);
 516 }
 517
 518 void dc_link_set_preferred_link_settings(struct dc *dc,
 519                                          struct dc_link_settings *link_setting,
 520                                          struct dc_link *link)
 521 {
 522         int i;
 523         struct pipe_ctx *pipe;
 524         struct dc_stream_state *link_stream;
 525         struct dc_link_settings store_settings = *link_setting;
 526
 527         link->preferred_link_setting = store_settings;
 528
 529         /* Retrain with preferred link settings only relevant for
 530          * DP signal type
 531          */
 532         if (!dc_is_dp_signal(link->connector_signal))
 533                 return;
 534
 535         for (i = 0; i < MAX_PIPES; i++) {
 536                 pipe = &dc->current_state->res_ctx.pipe_ctx[i];
 537                 if (pipe->stream && pipe->stream->link) {
 538                         if (pipe->stream->link == link)
 539                                 break;
 540                 }
 541         }
 542
 543         /* Stream not found */
 544         if (i == MAX_PIPES)
 545                 return;
 546
 547         link_stream = link->dc->current_state->res_ctx.pipe_ctx[i].stream;
 548
 549         /* Cannot retrain link if backend is off */
 550         if (link_stream->dpms_off)
 551                 return;
 552
 553         if (link_stream)
 554                 decide_link_settings(link_stream, &store_settings);
 555
 556         if ((store_settings.lane_count != LANE_COUNT_UNKNOWN) &&
 557                 (store_settings.link_rate != LINK_RATE_UNKNOWN))
 558                 dp_retrain_link_dp_test(link, &store_settings, false);
 559 }
 560
 561 void dc_link_enable_hpd(const struct dc_link *link)
 562 {
 563         dc_link_dp_enable_hpd(link);
 564 }
 565
 566 void dc_link_disable_hpd(const struct dc_link *link)
 567 {
 568         dc_link_dp_disable_hpd(link);
 569 }
 570
 571
 572 void dc_link_set_test_pattern(struct dc_link *link,
 573                               enum dp_test_pattern test_pattern,
 574                               const struct link_training_settings *p_link_settings,
 575                               const unsigned char *p_custom_pattern,
 576                               unsigned int cust_pattern_size)
 577 {
 578         if (link != NULL)
 579                 dc_link_dp_set_test_pattern(
 580                         link,
 581                         test_pattern,
 582                         p_link_settings,
 583                         p_custom_pattern,
 584                         cust_pattern_size);
 585 }
 586
 587 static void destruct(struct dc *dc)
 588 {
 589         dc_release_state(dc->current_state);
 590         dc->current_state = NULL;
 591
 592         destroy_links(dc);
 593
 594         dc_destroy_resource_pool(dc);
 595
 596         if (dc->ctx->gpio_service)
 597                 dal_gpio_service_destroy(&dc->ctx->gpio_service);
 598
 599         if (dc->ctx->created_bios)
 600                 dal_bios_parser_destroy(&dc->ctx->dc_bios);
 601
 602         dc_perf_trace_destroy(&dc->ctx->perf_trace);
 603
 604         kfree(dc->ctx);
 605         dc->ctx = NULL;
 606
 607         kfree(dc->bw_vbios);
 608         dc->bw_vbios = NULL;
 609
 610         kfree(dc->bw_dceip);
 611         dc->bw_dceip = NULL;
 612
 613 #ifdef CONFIG_DRM_AMD_DC_DCN1_0
 614         kfree(dc->dcn_soc);
 615         dc->dcn_soc = NULL;
 616
 617         kfree(dc->dcn_ip);
 618         dc->dcn_ip = NULL;
 619
 620 #endif
 621 }
 622
 623 static bool construct(struct dc *dc,
 624                 const struct dc_init_data *init_params)
 625 {
 626         struct dc_context *dc_ctx;
 627         struct bw_calcs_dceip *dc_dceip;
 628         struct bw_calcs_vbios *dc_vbios;
 629 #ifdef CONFIG_DRM_AMD_DC_DCN1_0
 630         struct dcn_soc_bounding_box *dcn_soc;
 631         struct dcn_ip_params *dcn_ip;
 632 #endif
 633
 634         enum dce_version dc_version = DCE_VERSION_UNKNOWN;
 635         memcpy(&dc->bb_overrides, &init_params->bb_overrides, sizeof(dc->bb_overrides));
 636
 637         dc_dceip = kzalloc(sizeof(*dc_dceip), GFP_KERNEL);
 638         if (!dc_dceip) {
 639                 dm_error("%s: failed to create dceip\n", __func__);
 640                 goto fail;
 641         }
 642
 643         dc->bw_dceip = dc_dceip;
 644
 645         dc_vbios = kzalloc(sizeof(*dc_vbios), GFP_KERNEL);
 646         if (!dc_vbios) {
 647                 dm_error("%s: failed to create vbios\n", __func__);
 648                 goto fail;
 649         }
 650
 651         dc->bw_vbios = dc_vbios;
 652 #ifdef CONFIG_DRM_AMD_DC_DCN1_0
 653         dcn_soc = kzalloc(sizeof(*dcn_soc), GFP_KERNEL);
 654         if (!dcn_soc) {
 655                 dm_error("%s: failed to create dcn_soc\n", __func__);
 656                 goto fail;
 657         }
 658
 659         dc->dcn_soc = dcn_soc;
 660
 661         dcn_ip = kzalloc(sizeof(*dcn_ip), GFP_KERNEL);
 662         if (!dcn_ip) {
 663                 dm_error("%s: failed to create dcn_ip\n", __func__);
 664                 goto fail;
 665         }
 666
 667         dc->dcn_ip = dcn_ip;
 668 #endif
 669
 670         dc_ctx = kzalloc(sizeof(*dc_ctx), GFP_KERNEL);
 671         if (!dc_ctx) {
 672                 dm_error("%s: failed to create ctx\n", __func__);
 673                 goto fail;
 674         }
 675
 676         dc_ctx->cgs_device = init_params->cgs_device;
 677         dc_ctx->driver_context = init_params->driver;
 678         dc_ctx->dc = dc;
 679         dc_ctx->asic_id = init_params->asic_id;
 680         dc_ctx->dc_sink_id_count = 0;
 681         dc_ctx->dc_stream_id_count = 0;
 682         dc->ctx = dc_ctx;
 683
 684         dc->current_state = dc_create_state();
 685
 686         if (!dc->current_state) {
 687                 dm_error("%s: failed to create validate ctx\n", __func__);
 688                 goto fail;
 689         }
 690
 691         /* Create logger */
 692
 693         dc_ctx->dce_environment = init_params->dce_environment;
 694
 695         dc_version = resource_parse_asic_id(init_params->asic_id);
 696         dc_ctx->dce_version = dc_version;
 697
 698         /* Resource should construct all asic specific resources.
 699          * This should be the only place where we need to parse the asic id
 700          */
 701         if (init_params->vbios_override)
 702                 dc_ctx->dc_bios = init_params->vbios_override;
 703         else {
 704                 /* Create BIOS parser */
 705                 struct bp_init_data bp_init_data;
 706
 707                 bp_init_data.ctx = dc_ctx;
 708                 bp_init_data.bios = init_params->asic_id.atombios_base_address;
 709
 710                 dc_ctx->dc_bios = dal_bios_parser_create(
 711                                 &bp_init_data, dc_version);
 712
 713                 if (!dc_ctx->dc_bios) {
 714                         ASSERT_CRITICAL(false);
 715                         goto fail;
 716                 }
 717
 718                 dc_ctx->created_bios = true;
 719                 }
 720
 721         dc_ctx->perf_trace = dc_perf_trace_create();
 722         if (!dc_ctx->perf_trace) {
 723                 ASSERT_CRITICAL(false);
 724                 goto fail;
 725         }
 726
 727         /* Create GPIO service */
 728         dc_ctx->gpio_service = dal_gpio_service_create(
 729                         dc_version,
 730                         dc_ctx->dce_environment,
 731                         dc_ctx);
 732
 733         if (!dc_ctx->gpio_service) {
 734                 ASSERT_CRITICAL(false);
 735                 goto fail;
 736         }
 737
 738         dc->res_pool = dc_create_resource_pool(dc, init_params, dc_version);
 739         if (!dc->res_pool)
 740                 goto fail;
 741
 742         dc_resource_state_construct(dc, dc->current_state);
 743
 744         if (!create_links(dc, init_params->num_virtual_links))
 745                 goto fail;
 746
 747         return true;
 748
 749 fail:
 750
 751         destruct(dc);
 752         return false;
 753 }
 754
 755 static void disable_dangling_plane(struct dc *dc, struct dc_state *context)
 756 {
 757         int i, j;
 758         struct dc_state *dangling_context = dc_create_state();
 759         struct dc_state *current_ctx;
 760
 761         if (dangling_context == NULL)
 762                 return;
 763
 764         dc_resource_state_copy_construct(dc->current_state, dangling_context);
 765
 766         for (i = 0; i < dc->res_pool->pipe_count; i++) {
 767                 struct dc_stream_state *old_stream =
 768                                 dc->current_state->res_ctx.pipe_ctx[i].stream;
 769                 bool should_disable = true;
 770
 771                 for (j = 0; j < context->stream_count; j++) {
 772                         if (old_stream == context->streams[j]) {
 773                                 should_disable = false;
 774                                 break;
 775                         }
 776                 }
 777                 if (should_disable && old_stream) {
 778                         dc_rem_all_planes_for_stream(dc, old_stream, dangling_context);
 779                         dc->hwss.apply_ctx_for_surface(dc, old_stream, 0, dangling_context);
 780                 }
 781         }
 782
 783         current_ctx = dc->current_state;
 784         dc->current_state = dangling_context;
 785         dc_release_state(current_ctx);
 786 }
 787
 788 /*******************************************************************************
 789  * Public functions
 790  ******************************************************************************/
 791
 792 struct dc *dc_create(const struct dc_init_data *init_params)
 793 {
 794         struct dc *dc = kzalloc(sizeof(*dc), GFP_KERNEL);
 795         unsigned int full_pipe_count;
 796
 797         if (NULL == dc)
 798                 goto alloc_fail;
 799
 800         if (false == construct(dc, init_params))
 801                 goto construct_fail;
 802
 803         /*TODO: separate HW and SW initialization*/
 804         dc->hwss.init_hw(dc);
 805
 806         full_pipe_count = dc->res_pool->pipe_count;
 807         if (dc->res_pool->underlay_pipe_index != NO_UNDERLAY_PIPE)
 808                 full_pipe_count--;
 809         dc->caps.max_streams = min(
 810                         full_pipe_count,
 811                         dc->res_pool->stream_enc_count);
 812
 813         dc->caps.max_links = dc->link_count;
 814         dc->caps.max_audios = dc->res_pool->audio_count;
 815         dc->caps.linear_pitch_alignment = 64;
 816
 817         /* Populate versioning information */
 818         dc->versions.dc_ver = DC_VER;
 819
 820         if (dc->res_pool->dmcu != NULL)
 821                 dc->versions.dmcu_version = dc->res_pool->dmcu->dmcu_version;
 822
 823         dc->config = init_params->flags;
 824
 825         dc->build_id = DC_BUILD_ID;
 826
 827         DC_LOG_DC("Display Core initialized\n");
 828
 829
 830
 831         return dc;
 832
 833 construct_fail:
 834         kfree(dc);
 835
 836 alloc_fail:
 837         return NULL;
 838 }
 839
 840 void dc_init_callbacks(struct dc *dc,
 841                 const struct dc_callback_init *init_params)
 842 {
 843 }
 844
 845 void dc_destroy(struct dc **dc)
 846 {
 847         destruct(*dc);
 848         kfree(*dc);
 849         *dc = NULL;
 850 }
 851
 852 static void enable_timing_multisync(
 853                 struct dc *dc,
 854                 struct dc_state *ctx)
 855 {
 856         int i = 0, multisync_count = 0;
 857         int pipe_count = dc->res_pool->pipe_count;
 858         struct pipe_ctx *multisync_pipes[MAX_PIPES] = { NULL };
 859
 860         for (i = 0; i < pipe_count; i++) {
 861                 if (!ctx->res_ctx.pipe_ctx[i].stream ||
 862                                 !ctx->res_ctx.pipe_ctx[i].stream->triggered_crtc_reset.enabled)
 863                         continue;
 864                 if (ctx->res_ctx.pipe_ctx[i].stream == ctx->res_ctx.pipe_ctx[i].stream->triggered_crtc_reset.event_source)
 865                         continue;
 866                 multisync_pipes[multisync_count] = &ctx->res_ctx.pipe_ctx[i];
 867                 multisync_count++;
 868         }
 869
 870         if (multisync_count > 0) {
 871                 dc->hwss.enable_per_frame_crtc_position_reset(
 872                         dc, multisync_count, multisync_pipes);
 873         }
 874 }
 875
 876 static void program_timing_sync(
 877                 struct dc *dc,
 878                 struct dc_state *ctx)
 879 {
 880         int i, j, k;
 881         int group_index = 0;
 882         int num_group = 0;
 883         int pipe_count = dc->res_pool->pipe_count;
 884         struct pipe_ctx *unsynced_pipes[MAX_PIPES] = { NULL };
 885
 886         for (i = 0; i < pipe_count; i++) {
 887                 if (!ctx->res_ctx.pipe_ctx[i].stream || ctx->res_ctx.pipe_ctx[i].top_pipe)
 888                         continue;
 889
 890                 unsynced_pipes[i] = &ctx->res_ctx.pipe_ctx[i];
 891         }
 892
 893         for (i = 0; i < pipe_count; i++) {
 894                 int group_size = 1;
 895                 struct pipe_ctx *pipe_set[MAX_PIPES];
 896
 897                 if (!unsynced_pipes[i])
 898                         continue;
 899
 900                 pipe_set[0] = unsynced_pipes[i];
 901                 unsynced_pipes[i] = NULL;
 902
 903                 /* Add tg to the set, search rest of the tg's for ones with
 904                  * same timing, add all tgs with same timing to the group
 905                  */
 906                 for (j = i + 1; j < pipe_count; j++) {
 907                         if (!unsynced_pipes[j])
 908                                 continue;
 909
 910                         if (resource_are_streams_timing_synchronizable(
 911                                         unsynced_pipes[j]->stream,
 912                                         pipe_set[0]->stream)) {
 913                                 pipe_set[group_size] = unsynced_pipes[j];
 914                                 unsynced_pipes[j] = NULL;
 915                                 group_size++;
 916                         }
 917                 }
 918
 919                 /* set first pipe with plane as master */
 920                 for (j = 0; j < group_size; j++) {
 921                         struct pipe_ctx *temp;
 922
 923                         if (pipe_set[j]->plane_state) {
 924                                 if (j == 0)
 925                                         break;
 926
 927                                 temp = pipe_set[0];
 928                                 pipe_set[0] = pipe_set[j];
 929                                 pipe_set[j] = temp;
 930                                 break;
 931                         }
 932                 }
 933
 934
 935                 for (k = 0; k < group_size; k++) {
 936                         struct dc_stream_status *status = dc_stream_get_status_from_state(ctx, pipe_set[k]->stream);
 937
 938                         status->timing_sync_info.group_id = num_group;
 939                         status->timing_sync_info.group_size = group_size;
 940                         if (k == 0)
 941                                 status->timing_sync_info.master = true;
 942                         else
 943                                 status->timing_sync_info.master = false;
 944
 945                 }
 946                 /* remove any other pipes with plane as they have already been synced */
 947                 for (j = j + 1; j < group_size; j++) {
 948                         if (pipe_set[j]->plane_state) {
 949                                 group_size--;
 950                                 pipe_set[j] = pipe_set[group_size];
 951                                 j--;
 952                         }
 953                 }
 954
 955                 if (group_size > 1) {
 956                         dc->hwss.enable_timing_synchronization(
 957                                 dc, group_index, group_size, pipe_set);
 958                         group_index++;
 959                 }
 960                 num_group++;
 961         }
 962 }
 963
 964 static bool context_changed(
 965                 struct dc *dc,
 966                 struct dc_state *context)
 967 {
 968         uint8_t i;
 969
 970         if (context->stream_count != dc->current_state->stream_count)
 971                 return true;
 972
 973         for (i = 0; i < dc->current_state->stream_count; i++) {
 974                 if (dc->current_state->streams[i] != context->streams[i])
 975                         return true;
 976         }
 977
 978         return false;
 979 }
 980
 981 bool dc_validate_seamless_boot_timing(const struct dc *dc,
 982                                 const struct dc_sink *sink,
 983                                 struct dc_crtc_timing *crtc_timing)
 984 {
 985         struct timing_generator *tg;
 986         struct dc_link *link = sink->link;
 987         unsigned int inst;
 988
 989         /* Check for enabled DIG to identify enabled display */
 990         if (!link->link_enc->funcs->is_dig_enabled(link->link_enc))
 991                 return false;
 992
 993         /* Check for which front end is used by this encoder.
 994          * Note the inst is 1 indexed, where 0 is undefined.
 995          * Note that DIG_FE can source from different OTG but our
 996          * current implementation always map 1-to-1, so this code makes
 997          * the same assumption and doesn't check OTG source.
 998          */
 999         inst = link->link_enc->funcs->get_dig_frontend(link->link_enc) - 1;
1000
1001         /* Instance should be within the range of the pool */
1002         if (inst >= dc->res_pool->pipe_count)
1003                 return false;
1004
1005         tg = dc->res_pool->timing_generators[inst];
1006
1007         if (!tg->funcs->is_matching_timing)
1008                 return false;
1009
1010         if (!tg->funcs->is_matching_timing(tg, crtc_timing))
1011                 return false;
1012
1013         if (dc_is_dp_signal(link->connector_signal)) {
1014                 unsigned int pix_clk_100hz;
1015
1016                 dc->res_pool->dp_clock_source->funcs->get_pixel_clk_frequency_100hz(
1017                         dc->res_pool->dp_clock_source,
1018                         inst, &pix_clk_100hz);
1019
1020                 if (crtc_timing->pix_clk_100hz != pix_clk_100hz)
1021                         return false;
1022         }
1023
1024         return true;
1025 }
1026
1027 bool dc_enable_stereo(
1028         struct dc *dc,
1029         struct dc_state *context,
1030         struct dc_stream_state *streams[],
1031         uint8_t stream_count)
1032 {
1033         bool ret = true;
1034         int i, j;
1035         struct pipe_ctx *pipe;
1036
1037         for (i = 0; i < MAX_PIPES; i++) {
1038                 if (context != NULL)
1039                         pipe = &context->res_ctx.pipe_ctx[i];
1040                 else
1041                         pipe = &dc->current_state->res_ctx.pipe_ctx[i];
1042                 for (j = 0 ; pipe && j < stream_count; j++)  {
1043                         if (streams[j] && streams[j] == pipe->stream &&
1044                                 dc->hwss.setup_stereo)
1045                                 dc->hwss.setup_stereo(pipe, dc);
1046                 }
1047         }
1048
1049         return ret;
1050 }
1051
1052 /*
1053  * Applies given context to HW and copy it into current context.
1054  * It's up to the user to release the src context afterwards.
1055  */
1056 static enum dc_status dc_commit_state_no_check(struct dc *dc, struct dc_state *context)
1057 {
1058         struct dc_bios *dcb = dc->ctx->dc_bios;
1059         enum dc_status result = DC_ERROR_UNEXPECTED;
1060         struct pipe_ctx *pipe;
1061         int i, k, l;
1062         struct dc_stream_state *dc_streams[MAX_STREAMS] = {0};
1063
1064         disable_dangling_plane(dc, context);
1065
1066         for (i = 0; i < context->stream_count; i++)
1067                 dc_streams[i] =  context->streams[i];
1068
1069         if (!dcb->funcs->is_accelerated_mode(dcb))
1070                 dc->hwss.enable_accelerated_mode(dc, context);
1071
1072         for (i = 0; i < context->stream_count; i++) {
1073                 if (context->streams[i]->apply_seamless_boot_optimization)
1074                         dc->optimize_seamless_boot = true;
1075         }
1076
1077         if (!dc->optimize_seamless_boot)
1078                 dc->hwss.prepare_bandwidth(dc, context);
1079
1080         /* re-program planes for existing stream, in case we need to
1081          * free up plane resource for later use
1082          */
1083         for (i = 0; i < context->stream_count; i++) {
1084                 if (context->streams[i]->mode_changed)
1085                         continue;
1086
1087                 dc->hwss.apply_ctx_for_surface(
1088                         dc, context->streams[i],
1089                         context->stream_status[i].plane_count,
1090                         context); /* use new pipe config in new context */
1091         }
1092
1093         /* Program hardware */
1094         for (i = 0; i < dc->res_pool->pipe_count; i++) {
1095                 pipe = &context->res_ctx.pipe_ctx[i];
1096                 dc->hwss.wait_for_mpcc_disconnect(dc, dc->res_pool, pipe);
1097         }
1098
1099         result = dc->hwss.apply_ctx_to_hw(dc, context);
1100
1101         if (result != DC_OK)
1102                 return result;
1103
1104         if (context->stream_count > 1) {
1105                 enable_timing_multisync(dc, context);
1106                 program_timing_sync(dc, context);
1107         }
1108
1109         /* Program all planes within new context*/
1110         for (i = 0; i < context->stream_count; i++) {
1111                 const struct dc_link *link = context->streams[i]->link;
1112                 struct dc_stream_status *status;
1113
1114                 if (context->streams[i]->apply_seamless_boot_optimization)
1115                         context->streams[i]->apply_seamless_boot_optimization = false;
1116
1117                 if (!context->streams[i]->mode_changed)
1118                         continue;
1119
1120                 dc->hwss.apply_ctx_for_surface(
1121                                 dc, context->streams[i],
1122                                 context->stream_status[i].plane_count,
1123                                 context);
1124
1125                 /*
1126                  * enable stereo
1127                  * TODO rework dc_enable_stereo call to work with validation sets?
1128                  */
1129                 for (k = 0; k < MAX_PIPES; k++) {
1130                         pipe = &context->res_ctx.pipe_ctx[k];
1131
1132                         for (l = 0 ; pipe && l < context->stream_count; l++)  {
1133                                 if (context->streams[l] &&
1134                                         context->streams[l] == pipe->stream &&
1135                                         dc->hwss.setup_stereo)
1136                                         dc->hwss.setup_stereo(pipe, dc);
1137                         }
1138                 }
1139
1140                 status = dc_stream_get_status_from_state(context, context->streams[i]);
1141                 context->streams[i]->out.otg_offset = status->primary_otg_inst;
1142
1143                 CONN_MSG_MODE(link, "{%dx%d, %dx%d@%dKhz}",
1144                                 context->streams[i]->timing.h_addressable,
1145                                 context->streams[i]->timing.v_addressable,
1146                                 context->streams[i]->timing.h_total,
1147                                 context->streams[i]->timing.v_total,
1148                                 context->streams[i]->timing.pix_clk_100hz / 10);
1149         }
1150
1151         dc_enable_stereo(dc, context, dc_streams, context->stream_count);
1152
1153         if (!dc->optimize_seamless_boot)
1154                 /* pplib is notified if disp_num changed */
1155                 dc->hwss.optimize_bandwidth(dc, context);
1156
1157         for (i = 0; i < context->stream_count; i++)
1158                 context->streams[i]->mode_changed = false;
1159
1160         memset(&context->commit_hints, 0, sizeof(context->commit_hints));
1161
1162         dc_release_state(dc->current_state);
1163
1164         dc->current_state = context;
1165
1166         dc_retain_state(dc->current_state);
1167
1168         return result;
1169 }
1170
1171 bool dc_commit_state(struct dc *dc, struct dc_state *context)
1172 {
1173         enum dc_status result = DC_ERROR_UNEXPECTED;
1174         int i;
1175
1176         if (false == context_changed(dc, context))
1177                 return DC_OK;
1178
1179         DC_LOG_DC("%s: %d streams\n",
1180                                 __func__, context->stream_count);
1181
1182         for (i = 0; i < context->stream_count; i++) {
1183                 struct dc_stream_state *stream = context->streams[i];
1184
1185                 dc_stream_log(dc, stream);
1186         }
1187
1188         result = dc_commit_state_no_check(dc, context);
1189
1190         return (result == DC_OK);
1191 }
1192
1193 bool dc_post_update_surfaces_to_stream(struct dc *dc)
1194 {
1195         int i;
1196         struct dc_state *context = dc->current_state;
1197
1198         if (!dc->optimized_required || dc->optimize_seamless_boot)
1199                 return true;
1200
1201         post_surface_trace(dc);
1202
1203         for (i = 0; i < dc->res_pool->pipe_count; i++)
1204                 if (context->res_ctx.pipe_ctx[i].stream == NULL ||
1205                     context->res_ctx.pipe_ctx[i].plane_state == NULL) {
1206                         context->res_ctx.pipe_ctx[i].pipe_idx = i;
1207                         dc->hwss.disable_plane(dc, &context->res_ctx.pipe_ctx[i]);
1208                 }
1209
1210         dc->optimized_required = false;
1211
1212         dc->hwss.optimize_bandwidth(dc, context);
1213         return true;
1214 }
1215
1216 struct dc_state *dc_create_state(void)
1217 {
1218         struct dc_state *context = kzalloc(sizeof(struct dc_state),
1219                                            GFP_KERNEL);
1220
1221         if (!context)
1222                 return NULL;
1223
1224         kref_init(&context->refcount);
1225         return context;
1226 }
1227
1228 void dc_retain_state(struct dc_state *context)
1229 {
1230         kref_get(&context->refcount);
1231 }
1232
1233 static void dc_state_free(struct kref *kref)
1234 {
1235         struct dc_state *context = container_of(kref, struct dc_state, refcount);
1236         dc_resource_state_destruct(context);
1237         kfree(context);
1238 }
1239
1240 void dc_release_state(struct dc_state *context)
1241 {
1242         kref_put(&context->refcount, dc_state_free);
1243 }
1244
1245 static bool is_surface_in_context(
1246                 const struct dc_state *context,
1247                 const struct dc_plane_state *plane_state)
1248 {
1249         int j;
1250
1251         for (j = 0; j < MAX_PIPES; j++) {
1252                 const struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[j];
1253
1254                 if (plane_state == pipe_ctx->plane_state) {
1255                         return true;
1256                 }
1257         }
1258
1259         return false;
1260 }
1261
1262 static enum surface_update_type get_plane_info_update_type(const struct dc_surface_update *u)
1263 {
1264         union surface_update_flags *update_flags = &u->surface->update_flags;
1265
1266         if (!u->plane_info)
1267                 return UPDATE_TYPE_FAST;
1268
1269         if (u->plane_info->color_space != u->surface->color_space)
1270                 update_flags->bits.color_space_change = 1;
1271
1272         if (u->plane_info->horizontal_mirror != u->surface->horizontal_mirror)
1273                 update_flags->bits.horizontal_mirror_change = 1;
1274
1275         if (u->plane_info->rotation != u->surface->rotation)
1276                 update_flags->bits.rotation_change = 1;
1277
1278         if (u->plane_info->format != u->surface->format)
1279                 update_flags->bits.pixel_format_change = 1;
1280
1281         if (u->plane_info->stereo_format != u->surface->stereo_format)
1282                 update_flags->bits.stereo_format_change = 1;
1283
1284         if (u->plane_info->per_pixel_alpha != u->surface->per_pixel_alpha)
1285                 update_flags->bits.per_pixel_alpha_change = 1;
1286
1287         if (u->plane_info->global_alpha_value != u->surface->global_alpha_value)
1288                 update_flags->bits.global_alpha_change = 1;
1289
1290         if (u->plane_info->dcc.enable != u->surface->dcc.enable
1291                         || u->plane_info->dcc.grph.independent_64b_blks != u->surface->dcc.grph.independent_64b_blks
1292                         || u->plane_info->dcc.grph.meta_pitch != u->surface->dcc.grph.meta_pitch)
1293                 update_flags->bits.dcc_change = 1;
1294
1295         if (resource_pixel_format_to_bpp(u->plane_info->format) !=
1296                         resource_pixel_format_to_bpp(u->surface->format))
1297                 /* different bytes per element will require full bandwidth
1298                  * and DML calculation
1299                  */
1300                 update_flags->bits.bpp_change = 1;
1301
1302         if (u->plane_info->plane_size.grph.surface_pitch != u->surface->plane_size.grph.surface_pitch
1303                         || u->plane_info->plane_size.video.luma_pitch != u->surface->plane_size.video.luma_pitch
1304                         || u->plane_info->plane_size.video.chroma_pitch != u->surface->plane_size.video.chroma_pitch)
1305                 update_flags->bits.plane_size_change = 1;
1306
1307
1308         if (memcmp(&u->plane_info->tiling_info, &u->surface->tiling_info,
1309                         sizeof(union dc_tiling_info)) != 0) {
1310                 update_flags->bits.swizzle_change = 1;
1311                 /* todo: below are HW dependent, we should add a hook to
1312                  * DCE/N resource and validated there.
1313                  */
1314                 if (u->plane_info->tiling_info.gfx9.swizzle != DC_SW_LINEAR)
1315                         /* swizzled mode requires RQ to be setup properly,
1316                          * thus need to run DML to calculate RQ settings
1317                          */
1318                         update_flags->bits.bandwidth_change = 1;
1319         }
1320
1321         if (update_flags->bits.rotation_change
1322                         || update_flags->bits.stereo_format_change
1323                         || update_flags->bits.pixel_format_change
1324                         || update_flags->bits.bpp_change
1325                         || update_flags->bits.bandwidth_change
1326                         || update_flags->bits.output_tf_change)
1327                 return UPDATE_TYPE_FULL;
1328
1329         return update_flags->raw ? UPDATE_TYPE_MED : UPDATE_TYPE_FAST;
1330 }
1331
1332 static enum surface_update_type get_scaling_info_update_type(
1333                 const struct dc_surface_update *u)
1334 {
1335         union surface_update_flags *update_flags = &u->surface->update_flags;
1336
1337         if (!u->scaling_info)
1338                 return UPDATE_TYPE_FAST;
1339
1340         if (u->scaling_info->clip_rect.width != u->surface->clip_rect.width
1341                         || u->scaling_info->clip_rect.height != u->surface->clip_rect.height
1342                         || u->scaling_info->dst_rect.width != u->surface->dst_rect.width
1343                         || u->scaling_info->dst_rect.height != u->surface->dst_rect.height) {
1344                 update_flags->bits.scaling_change = 1;
1345
1346                 if ((u->scaling_info->dst_rect.width < u->surface->dst_rect.width
1347                         || u->scaling_info->dst_rect.height < u->surface->dst_rect.height)
1348                                 && (u->scaling_info->dst_rect.width < u->surface->src_rect.width
1349                                         || u->scaling_info->dst_rect.height < u->surface->src_rect.height))
1350                         /* Making dst rect smaller requires a bandwidth change */
1351                         update_flags->bits.bandwidth_change = 1;
1352         }
1353
1354         if (u->scaling_info->src_rect.width != u->surface->src_rect.width
1355                 || u->scaling_info->src_rect.height != u->surface->src_rect.height) {
1356
1357                 update_flags->bits.scaling_change = 1;
1358                 if (u->scaling_info->src_rect.width > u->surface->src_rect.width
1359                                 && u->scaling_info->src_rect.height > u->surface->src_rect.height)
1360                         /* Making src rect bigger requires a bandwidth change */
1361                         update_flags->bits.clock_change = 1;
1362         }
1363
1364         if (u->scaling_info->src_rect.x != u->surface->src_rect.x
1365                         || u->scaling_info->src_rect.y != u->surface->src_rect.y
1366                         || u->scaling_info->clip_rect.x != u->surface->clip_rect.x
1367                         || u->scaling_info->clip_rect.y != u->surface->clip_rect.y
1368                         || u->scaling_info->dst_rect.x != u->surface->dst_rect.x
1369                         || u->scaling_info->dst_rect.y != u->surface->dst_rect.y)
1370                 update_flags->bits.position_change = 1;
1371
1372         if (update_flags->bits.clock_change
1373                         || update_flags->bits.bandwidth_change)
1374                 return UPDATE_TYPE_FULL;
1375
1376         if (update_flags->bits.scaling_change
1377                         || update_flags->bits.position_change)
1378                 return UPDATE_TYPE_MED;
1379
1380         return UPDATE_TYPE_FAST;
1381 }
1382
1383 static enum surface_update_type det_surface_update(const struct dc *dc,
1384                 const struct dc_surface_update *u)
1385 {
1386         const struct dc_state *context = dc->current_state;
1387         enum surface_update_type type;
1388         enum surface_update_type overall_type = UPDATE_TYPE_FAST;
1389         union surface_update_flags *update_flags = &u->surface->update_flags;
1390
1391         update_flags->raw = 0; // Reset all flags
1392
1393         if (!is_surface_in_context(context, u->surface)) {
1394                 update_flags->bits.new_plane = 1;
1395                 return UPDATE_TYPE_FULL;
1396         }
1397
1398         type = get_plane_info_update_type(u);
1399         elevate_update_type(&overall_type, type);
1400
1401         type = get_scaling_info_update_type(u);
1402         elevate_update_type(&overall_type, type);
1403
1404         if (u->in_transfer_func)
1405                 update_flags->bits.in_transfer_func_change = 1;
1406
1407         if (u->input_csc_color_matrix)
1408                 update_flags->bits.input_csc_change = 1;
1409
1410         if (u->coeff_reduction_factor)
1411                 update_flags->bits.coeff_reduction_change = 1;
1412
1413         if (u->gamma) {
1414                 enum surface_pixel_format format = SURFACE_PIXEL_FORMAT_GRPH_BEGIN;
1415
1416                 if (u->plane_info)
1417                         format = u->plane_info->format;
1418                 else if (u->surface)
1419                         format = u->surface->format;
1420
1421                 if (dce_use_lut(format))
1422                         update_flags->bits.gamma_change = 1;
1423         }
1424
1425         if (update_flags->bits.in_transfer_func_change) {
1426                 type = UPDATE_TYPE_MED;
1427                 elevate_update_type(&overall_type, type);
1428         }
1429
1430         if (update_flags->bits.input_csc_change
1431                         || update_flags->bits.coeff_reduction_change
1432                         || update_flags->bits.gamma_change) {
1433                 type = UPDATE_TYPE_FULL;
1434                 elevate_update_type(&overall_type, type);
1435         }
1436
1437         return overall_type;
1438 }
1439
1440 static enum surface_update_type check_update_surfaces_for_stream(
1441                 struct dc *dc,
1442                 struct dc_surface_update *updates,
1443                 int surface_count,
1444                 struct dc_stream_update *stream_update,
1445                 const struct dc_stream_status *stream_status)
1446 {
1447         int i;
1448         enum surface_update_type overall_type = UPDATE_TYPE_FAST;
1449
1450         if (stream_status == NULL || stream_status->plane_count != surface_count)
1451                 return UPDATE_TYPE_FULL;
1452
1453         /* some stream updates require passive update */
1454         if (stream_update) {
1455                 if ((stream_update->src.height != 0) &&
1456                                 (stream_update->src.width != 0))
1457                         return UPDATE_TYPE_FULL;
1458
1459                 if ((stream_update->dst.height != 0) &&
1460                                 (stream_update->dst.width != 0))
1461                         return UPDATE_TYPE_FULL;
1462
1463                 if (stream_update->out_transfer_func)
1464                         return UPDATE_TYPE_FULL;
1465
1466                 if (stream_update->abm_level)
1467                         return UPDATE_TYPE_FULL;
1468
1469                 if (stream_update->dpms_off)
1470                         return UPDATE_TYPE_FULL;
1471         }
1472
1473         for (i = 0 ; i < surface_count; i++) {
1474                 enum surface_update_type type =
1475                                 det_surface_update(dc, &updates[i]);
1476
1477                 if (type == UPDATE_TYPE_FULL)
1478                         return type;
1479
1480                 elevate_update_type(&overall_type, type);
1481         }
1482
1483         return overall_type;
1484 }
1485
1486 /**
1487  * dc_check_update_surfaces_for_stream() - Determine update type (fast, med, or full)
1488  *
1489  * See :c:type:`enum surface_update_type <surface_update_type>` for explanation of update types
1490  */
1491 enum surface_update_type dc_check_update_surfaces_for_stream(
1492                 struct dc *dc,
1493                 struct dc_surface_update *updates,
1494                 int surface_count,
1495                 struct dc_stream_update *stream_update,
1496                 const struct dc_stream_status *stream_status)
1497 {
1498         int i;
1499         enum surface_update_type type;
1500
1501         for (i = 0; i < surface_count; i++)
1502                 updates[i].surface->update_flags.raw = 0;
1503
1504         type = check_update_surfaces_for_stream(dc, updates, surface_count, stream_update, stream_status);
1505         if (type == UPDATE_TYPE_FULL)
1506                 for (i = 0; i < surface_count; i++)
1507                         updates[i].surface->update_flags.raw = 0xFFFFFFFF;
1508
1509         return type;
1510 }
1511
1512 static struct dc_stream_status *stream_get_status(
1513         struct dc_state *ctx,
1514         struct dc_stream_state *stream)
1515 {
1516         uint8_t i;
1517
1518         for (i = 0; i < ctx->stream_count; i++) {
1519                 if (stream == ctx->streams[i]) {
1520                         return &ctx->stream_status[i];
1521                 }
1522         }
1523
1524         return NULL;
1525 }
1526
1527 static const enum surface_update_type update_surface_trace_level = UPDATE_TYPE_FULL;
1528
1529 static void copy_surface_update_to_plane(
1530                 struct dc_plane_state *surface,
1531                 struct dc_surface_update *srf_update)
1532 {
1533         if (srf_update->flip_addr) {
1534                 surface->address = srf_update->flip_addr->address;
1535                 surface->flip_immediate =
1536                         srf_update->flip_addr->flip_immediate;
1537                 surface->time.time_elapsed_in_us[surface->time.index] =
1538                         srf_update->flip_addr->flip_timestamp_in_us -
1539                                 surface->time.prev_update_time_in_us;
1540                 surface->time.prev_update_time_in_us =
1541                         srf_update->flip_addr->flip_timestamp_in_us;
1542                 surface->time.index++;
1543                 if (surface->time.index >= DC_PLANE_UPDATE_TIMES_MAX)
1544                         surface->time.index = 0;
1545         }
1546
1547         if (srf_update->scaling_info) {
1548                 surface->scaling_quality =
1549                                 srf_update->scaling_info->scaling_quality;
1550                 surface->dst_rect =
1551                                 srf_update->scaling_info->dst_rect;
1552                 surface->src_rect =
1553                                 srf_update->scaling_info->src_rect;
1554                 surface->clip_rect =
1555                                 srf_update->scaling_info->clip_rect;
1556         }
1557
1558         if (srf_update->plane_info) {
1559                 surface->color_space =
1560                                 srf_update->plane_info->color_space;
1561                 surface->format =
1562                                 srf_update->plane_info->format;
1563                 surface->plane_size =
1564                                 srf_update->plane_info->plane_size;
1565                 surface->rotation =
1566                                 srf_update->plane_info->rotation;
1567                 surface->horizontal_mirror =
1568                                 srf_update->plane_info->horizontal_mirror;
1569                 surface->stereo_format =
1570                                 srf_update->plane_info->stereo_format;
1571                 surface->tiling_info =
1572                                 srf_update->plane_info->tiling_info;
1573                 surface->visible =
1574                                 srf_update->plane_info->visible;
1575                 surface->per_pixel_alpha =
1576                                 srf_update->plane_info->per_pixel_alpha;
1577                 surface->global_alpha =
1578                                 srf_update->plane_info->global_alpha;
1579                 surface->global_alpha_value =
1580                                 srf_update->plane_info->global_alpha_value;
1581                 surface->dcc =
1582                                 srf_update->plane_info->dcc;
1583                 surface->sdr_white_level =
1584                                 srf_update->plane_info->sdr_white_level;
1585         }
1586
1587         if (srf_update->gamma &&
1588                         (surface->gamma_correction !=
1589                                         srf_update->gamma)) {
1590                 memcpy(&surface->gamma_correction->entries,
1591                         &srf_update->gamma->entries,
1592                         sizeof(struct dc_gamma_entries));
1593                 surface->gamma_correction->is_identity =
1594                         srf_update->gamma->is_identity;
1595                 surface->gamma_correction->num_entries =
1596                         srf_update->gamma->num_entries;
1597                 surface->gamma_correction->type =
1598                         srf_update->gamma->type;
1599         }
1600
1601         if (srf_update->in_transfer_func &&
1602                         (surface->in_transfer_func !=
1603                                 srf_update->in_transfer_func)) {
1604                 surface->in_transfer_func->sdr_ref_white_level =
1605                         srf_update->in_transfer_func->sdr_ref_white_level;
1606                 surface->in_transfer_func->tf =
1607                         srf_update->in_transfer_func->tf;
1608                 surface->in_transfer_func->type =
1609                         srf_update->in_transfer_func->type;
1610                 memcpy(&surface->in_transfer_func->tf_pts,
1611                         &srf_update->in_transfer_func->tf_pts,
1612                         sizeof(struct dc_transfer_func_distributed_points));
1613         }
1614
1615         if (srf_update->input_csc_color_matrix)
1616                 surface->input_csc_color_matrix =
1617                         *srf_update->input_csc_color_matrix;
1618
1619         if (srf_update->coeff_reduction_factor)
1620                 surface->coeff_reduction_factor =
1621                         *srf_update->coeff_reduction_factor;
1622 }
1623
1624 static void commit_planes_do_stream_update(struct dc *dc,
1625                 struct dc_stream_state *stream,
1626                 struct dc_stream_update *stream_update,
1627                 enum surface_update_type update_type,
1628                 struct dc_state *context)
1629 {
1630         int j;
1631
1632         // Stream updates
1633         for (j = 0; j < dc->res_pool->pipe_count; j++) {
1634                 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[j];
1635
1636                 if (!pipe_ctx->top_pipe &&
1637                         pipe_ctx->stream &&
1638                         pipe_ctx->stream == stream) {
1639
1640                         /* Fast update*/
1641                         // VRR program can be done as part of FAST UPDATE
1642                         if (stream_update->adjust)
1643                                 dc->hwss.set_drr(&pipe_ctx, 1,
1644                                         stream_update->adjust->v_total_min,
1645                                         stream_update->adjust->v_total_max);
1646
1647                         if (stream_update->periodic_interrupt0 &&
1648                                         dc->hwss.setup_periodic_interrupt)
1649                                 dc->hwss.setup_periodic_interrupt(pipe_ctx, VLINE0);
1650
1651                         if (stream_update->periodic_interrupt1 &&
1652                                         dc->hwss.setup_periodic_interrupt)
1653                                 dc->hwss.setup_periodic_interrupt(pipe_ctx, VLINE1);
1654
1655                         if ((stream_update->hdr_static_metadata && !stream->use_dynamic_meta) ||
1656                                         stream_update->vrr_infopacket ||
1657                                         stream_update->vsc_infopacket ||
1658                                         stream_update->vsp_infopacket) {
1659                                 resource_build_info_frame(pipe_ctx);
1660                                 dc->hwss.update_info_frame(pipe_ctx);
1661                         }
1662
1663                         if (stream_update->gamut_remap)
1664                                 dc_stream_set_gamut_remap(dc, stream);
1665
1666                         if (stream_update->output_csc_transform)
1667                                 dc_stream_program_csc_matrix(dc, stream);
1668
1669                         if (stream_update->dither_option) {
1670                                 resource_build_bit_depth_reduction_params(pipe_ctx->stream,
1671                                                                         &pipe_ctx->stream->bit_depth_params);
1672                                 pipe_ctx->stream_res.opp->funcs->opp_program_fmt(pipe_ctx->stream_res.opp,
1673                                                 &stream->bit_depth_params,
1674                                                 &stream->clamping);
1675                         }
1676
1677                         /* Full fe update*/
1678                         if (update_type == UPDATE_TYPE_FAST)
1679                                 continue;
1680
1681                         if (stream_update->dpms_off) {
1682                                 dc->hwss.pipe_control_lock(dc, pipe_ctx, true);
1683                                 if (*stream_update->dpms_off) {
1684                                         core_link_disable_stream(pipe_ctx, KEEP_ACQUIRED_RESOURCE);
1685                                         dc->hwss.optimize_bandwidth(dc, dc->current_state);
1686                                 } else {
1687                                         dc->hwss.prepare_bandwidth(dc, dc->current_state);
1688                                         core_link_enable_stream(dc->current_state, pipe_ctx);
1689                                 }
1690                                 dc->hwss.pipe_control_lock(dc, pipe_ctx, false);
1691                         }
1692
1693                         if (stream_update->abm_level && pipe_ctx->stream_res.abm) {
1694                                 if (pipe_ctx->stream_res.tg->funcs->is_blanked) {
1695                                         // if otg funcs defined check if blanked before programming
1696                                         if (!pipe_ctx->stream_res.tg->funcs->is_blanked(pipe_ctx->stream_res.tg))
1697                                                 pipe_ctx->stream_res.abm->funcs->set_abm_level(
1698                                                         pipe_ctx->stream_res.abm, stream->abm_level);
1699                                 } else
1700                                         pipe_ctx->stream_res.abm->funcs->set_abm_level(
1701                                                 pipe_ctx->stream_res.abm, stream->abm_level);
1702                         }
1703                 }
1704         }
1705 }
1706
1707 static void commit_planes_for_stream(struct dc *dc,
1708                 struct dc_surface_update *srf_updates,
1709                 int surface_count,
1710                 struct dc_stream_state *stream,
1711                 struct dc_stream_update *stream_update,
1712                 enum surface_update_type update_type,
1713                 struct dc_state *context)
1714 {
1715         int i, j;
1716         struct pipe_ctx *top_pipe_to_program = NULL;
1717
1718         if (dc->optimize_seamless_boot && surface_count > 0) {
1719                 /* Optimize seamless boot flag keeps clocks and watermarks high until
1720                  * first flip. After first flip, optimization is required to lower
1721                  * bandwidth.
1722                  */
1723                 dc->optimize_seamless_boot = false;
1724                 dc->optimized_required = true;
1725         }
1726
1727         if (update_type == UPDATE_TYPE_FULL && !dc->optimize_seamless_boot) {
1728                 dc->hwss.prepare_bandwidth(dc, context);
1729                 context_clock_trace(dc, context);
1730         }
1731
1732         // Stream updates
1733         if (stream_update)
1734                 commit_planes_do_stream_update(dc, stream, stream_update, update_type, context);
1735
1736         if (surface_count == 0) {
1737                 /*
1738                  * In case of turning off screen, no need to program front end a second time.
1739                  * just return after program blank.
1740                  */
1741                 dc->hwss.apply_ctx_for_surface(dc, stream, 0, context);
1742                 return;
1743         }
1744
1745         // Update Type FULL, Surface updates
1746         for (j = 0; j < dc->res_pool->pipe_count; j++) {
1747                 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[j];
1748
1749                 if (!pipe_ctx->top_pipe &&
1750                         pipe_ctx->stream &&
1751                         pipe_ctx->stream == stream) {
1752                         struct dc_stream_status *stream_status = NULL;
1753
1754                         top_pipe_to_program = pipe_ctx;
1755
1756                         if (!pipe_ctx->plane_state)
1757                                 continue;
1758
1759                         /* Full fe update*/
1760                         if (update_type == UPDATE_TYPE_FAST)
1761                                 continue;
1762
1763                         stream_status =
1764                                 stream_get_status(context, pipe_ctx->stream);
1765
1766                         dc->hwss.apply_ctx_for_surface(
1767                                         dc, pipe_ctx->stream, stream_status->plane_count, context);
1768                 }
1769         }
1770
1771         // Update Type FAST, Surface updates
1772         if (update_type == UPDATE_TYPE_FAST) {
1773                 /* Lock the top pipe while updating plane addrs, since freesync requires
1774                  *  plane addr update event triggers to be synchronized.
1775                  *  top_pipe_to_program is expected to never be NULL
1776                  */
1777                 dc->hwss.pipe_control_lock(dc, top_pipe_to_program, true);
1778
1779                 /* Perform requested Updates */
1780                 for (i = 0; i < surface_count; i++) {
1781                         struct dc_plane_state *plane_state = srf_updates[i].surface;
1782
1783                         for (j = 0; j < dc->res_pool->pipe_count; j++) {
1784                                 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[j];
1785
1786                                 if (pipe_ctx->stream != stream)
1787                                         continue;
1788
1789                                 if (pipe_ctx->plane_state != plane_state)
1790                                         continue;
1791
1792                                 if (srf_updates[i].flip_addr)
1793                                         dc->hwss.update_plane_addr(dc, pipe_ctx);
1794                         }
1795                 }
1796
1797                 dc->hwss.pipe_control_lock(dc, top_pipe_to_program, false);
1798         }
1799 }
1800
1801 void dc_commit_updates_for_stream(struct dc *dc,
1802                 struct dc_surface_update *srf_updates,
1803                 int surface_count,
1804                 struct dc_stream_state *stream,
1805                 struct dc_stream_update *stream_update,
1806                 struct dc_state *state)
1807 {
1808         const struct dc_stream_status *stream_status;
1809         enum surface_update_type update_type;
1810         struct dc_state *context;
1811         struct dc_context *dc_ctx = dc->ctx;
1812         int i, j;
1813
1814         stream_status = dc_stream_get_status(stream);
1815         context = dc->current_state;
1816
1817         update_type = dc_check_update_surfaces_for_stream(
1818                                 dc, srf_updates, surface_count, stream_update, stream_status);
1819
1820         if (update_type >= update_surface_trace_level)
1821                 update_surface_trace(dc, srf_updates, surface_count);
1822
1823
1824         if (update_type >= UPDATE_TYPE_FULL) {
1825
1826                 /* initialize scratch memory for building context */
1827                 context = dc_create_state();
1828                 if (context == NULL) {
1829                         DC_ERROR("Failed to allocate new validate context!\n");
1830                         return;
1831                 }
1832
1833                 dc_resource_state_copy_construct(state, context);
1834         }
1835
1836
1837         for (i = 0; i < surface_count; i++) {
1838                 struct dc_plane_state *surface = srf_updates[i].surface;
1839
1840                 copy_surface_update_to_plane(surface, &srf_updates[i]);
1841
1842                 if (update_type >= UPDATE_TYPE_MED) {
1843                         for (j = 0; j < dc->res_pool->pipe_count; j++) {
1844                                 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[j];
1845
1846                                 if (pipe_ctx->plane_state != surface)
1847                                         continue;
1848
1849                                 resource_build_scaling_params(pipe_ctx);
1850                         }
1851                 }
1852         }
1853
1854         commit_planes_for_stream(
1855                                 dc,
1856                                 srf_updates,
1857                                 surface_count,
1858                                 stream,
1859                                 stream_update,
1860                                 update_type,
1861                                 context);
1862         /*update current_State*/
1863         if (dc->current_state != context) {
1864
1865                 struct dc_state *old = dc->current_state;
1866
1867                 dc->current_state = context;
1868                 dc_release_state(old);
1869
1870         }
1871         /*let's use current_state to update watermark etc*/
1872         if (update_type >= UPDATE_TYPE_FULL)
1873                 dc_post_update_surfaces_to_stream(dc);
1874
1875         return;
1876
1877 }
1878
1879 uint8_t dc_get_current_stream_count(struct dc *dc)
1880 {
1881         return dc->current_state->stream_count;
1882 }
1883
1884 struct dc_stream_state *dc_get_stream_at_index(struct dc *dc, uint8_t i)
1885 {
1886         if (i < dc->current_state->stream_count)
1887                 return dc->current_state->streams[i];
1888         return NULL;
1889 }
1890
1891 enum dc_irq_source dc_interrupt_to_irq_source(
1892                 struct dc *dc,
1893                 uint32_t src_id,
1894                 uint32_t ext_id)
1895 {
1896         return dal_irq_service_to_irq_source(dc->res_pool->irqs, src_id, ext_id);
1897 }
1898
1899 /**
1900  * dc_interrupt_set() - Enable/disable an AMD hw interrupt source
1901  */
1902 bool dc_interrupt_set(struct dc *dc, enum dc_irq_source src, bool enable)
1903 {
1904
1905         if (dc == NULL)
1906                 return false;
1907
1908         return dal_irq_service_set(dc->res_pool->irqs, src, enable);
1909 }
1910
1911 void dc_interrupt_ack(struct dc *dc, enum dc_irq_source src)
1912 {
1913         dal_irq_service_ack(dc->res_pool->irqs, src);
1914 }
1915
1916 void dc_set_power_state(
1917         struct dc *dc,
1918         enum dc_acpi_cm_power_state power_state)
1919 {
1920         struct kref refcount;
1921
1922         switch (power_state) {
1923         case DC_ACPI_CM_POWER_STATE_D0:
1924                 dc_resource_state_construct(dc, dc->current_state);
1925
1926                 dc->hwss.init_hw(dc);
1927                 break;
1928         default:
1929                 ASSERT(dc->current_state->stream_count == 0);
1930                 /* Zero out the current context so that on resume we start with
1931                  * clean state, and dc hw programming optimizations will not
1932                  * cause any trouble.
1933                  */
1934
1935                 /* Preserve refcount */
1936                 refcount = dc->current_state->refcount;
1937                 dc_resource_state_destruct(dc->current_state);
1938                 memset(dc->current_state, 0,
1939                                 sizeof(*dc->current_state));
1940
1941                 dc->current_state->refcount = refcount;
1942
1943                 break;
1944         }
1945
1946 }
1947
1948 void dc_resume(struct dc *dc)
1949 {
1950
1951         uint32_t i;
1952
1953         for (i = 0; i < dc->link_count; i++)
1954                 core_link_resume(dc->links[i]);
1955 }
1956
1957 unsigned int dc_get_current_backlight_pwm(struct dc *dc)
1958 {
1959         struct abm *abm = dc->res_pool->abm;
1960
1961         if (abm)
1962                 return abm->funcs->get_current_backlight(abm);
1963
1964         return 0;
1965 }
1966
1967 unsigned int dc_get_target_backlight_pwm(struct dc *dc)
1968 {
1969         struct abm *abm = dc->res_pool->abm;
1970
1971         if (abm)
1972                 return abm->funcs->get_target_backlight(abm);
1973
1974         return 0;
1975 }
1976
1977 bool dc_is_dmcu_initialized(struct dc *dc)
1978 {
1979         struct dmcu *dmcu = dc->res_pool->dmcu;
1980
1981         if (dmcu)
1982                 return dmcu->funcs->is_dmcu_initialized(dmcu);
1983         return false;
1984 }
1985
1986 bool dc_submit_i2c(
1987                 struct dc *dc,
1988                 uint32_t link_index,
1989                 struct i2c_command *cmd)
1990 {
1991
1992         struct dc_link *link = dc->links[link_index];
1993         struct ddc_service *ddc = link->ddc;
1994         return dce_i2c_submit_command(
1995                 dc->res_pool,
1996                 ddc->ddc_pin,
1997                 cmd);
1998 }
1999
2000 static bool link_add_remote_sink_helper(struct dc_link *dc_link, struct dc_sink *sink)
2001 {
2002         if (dc_link->sink_count >= MAX_SINKS_PER_LINK) {
2003                 BREAK_TO_DEBUGGER();
2004                 return false;
2005         }
2006
2007         dc_sink_retain(sink);
2008
2009         dc_link->remote_sinks[dc_link->sink_count] = sink;
2010         dc_link->sink_count++;
2011
2012         return true;
2013 }
2014
2015 /**
2016  * dc_link_add_remote_sink() - Create a sink and attach it to an existing link
2017  *
2018  * EDID length is in bytes
2019  */
2020 struct dc_sink *dc_link_add_remote_sink(
2021                 struct dc_link *link,
2022                 const uint8_t *edid,
2023                 int len,
2024                 struct dc_sink_init_data *init_data)
2025 {
2026         struct dc_sink *dc_sink;
2027         enum dc_edid_status edid_status;
2028
2029         if (len > DC_MAX_EDID_BUFFER_SIZE) {
2030                 dm_error("Max EDID buffer size breached!\n");
2031                 return NULL;
2032         }
2033
2034         if (!init_data) {
2035                 BREAK_TO_DEBUGGER();
2036                 return NULL;
2037         }
2038
2039         if (!init_data->link) {
2040                 BREAK_TO_DEBUGGER();
2041                 return NULL;
2042         }
2043
2044         dc_sink = dc_sink_create(init_data);
2045
2046         if (!dc_sink)
2047                 return NULL;
2048
2049         memmove(dc_sink->dc_edid.raw_edid, edid, len);
2050         dc_sink->dc_edid.length = len;
2051
2052         if (!link_add_remote_sink_helper(
2053                         link,
2054                         dc_sink))
2055                 goto fail_add_sink;
2056
2057         edid_status = dm_helpers_parse_edid_caps(
2058                         link->ctx,
2059                         &dc_sink->dc_edid,
2060                         &dc_sink->edid_caps);
2061
2062         /*
2063          * Treat device as no EDID device if EDID
2064          * parsing fails
2065          */
2066         if (edid_status != EDID_OK) {
2067                 dc_sink->dc_edid.length = 0;
2068                 dm_error("Bad EDID, status%d!\n", edid_status);
2069         }
2070
2071         return dc_sink;
2072
2073 fail_add_sink:
2074         dc_sink_release(dc_sink);
2075         return NULL;
2076 }
2077
2078 /**
2079  * dc_link_remove_remote_sink() - Remove a remote sink from a dc_link
2080  *
2081  * Note that this just removes the struct dc_sink - it doesn't
2082  * program hardware or alter other members of dc_link
2083  */
2084 void dc_link_remove_remote_sink(struct dc_link *link, struct dc_sink *sink)
2085 {
2086         int i;
2087
2088         if (!link->sink_count) {
2089                 BREAK_TO_DEBUGGER();
2090                 return;
2091         }
2092
2093         for (i = 0; i < link->sink_count; i++) {
2094                 if (link->remote_sinks[i] == sink) {
2095                         dc_sink_release(sink);
2096                         link->remote_sinks[i] = NULL;
2097
2098                         /* shrink array to remove empty place */
2099                         while (i < link->sink_count - 1) {
2100                                 link->remote_sinks[i] = link->remote_sinks[i+1];
2101                                 i++;
2102                         }
2103                         link->remote_sinks[i] = NULL;
2104                         link->sink_count--;
2105                         return;
2106                 }
2107         }
2108 }
2109
2110 void get_clock_requirements_for_state(struct dc_state *state, struct AsicStateEx *info)
2111 {
2112         info->displayClock                              = (unsigned int)state->bw.dcn.clk.dispclk_khz;
2113         info->engineClock                               = (unsigned int)state->bw.dcn.clk.dcfclk_khz;
2114         info->memoryClock                               = (unsigned int)state->bw.dcn.clk.dramclk_khz;
2115         info->maxSupportedDppClock              = (unsigned int)state->bw.dcn.clk.max_supported_dppclk_khz;
2116         info->dppClock                                  = (unsigned int)state->bw.dcn.clk.dppclk_khz;
2117         info->socClock                                  = (unsigned int)state->bw.dcn.clk.socclk_khz;
2118         info->dcfClockDeepSleep                 = (unsigned int)state->bw.dcn.clk.dcfclk_deep_sleep_khz;
2119         info->fClock                                    = (unsigned int)state->bw.dcn.clk.fclk_khz;
2120         info->phyClock                                  = (unsigned int)state->bw.dcn.clk.phyclk_khz;
2121 }