drivers/gpu/drm/amd/display/dc/core/dc_link.c

   1 /*
   2  * Copyright 2012-15 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: AMD
  23  *
  24  */
  25
  26 #include "dm_services.h"
  27 #include "atom.h"
  28 #include "dm_helpers.h"
  29 #include "dc.h"
  30 #include "grph_object_id.h"
  31 #include "gpio_service_interface.h"
  32 #include "core_status.h"
  33 #include "dc_link_dp.h"
  34 #include "dc_link_ddc.h"
  35 #include "link_hwss.h"
  36 #include "opp.h"
  37
  38 #include "link_encoder.h"
  39 #include "hw_sequencer.h"
  40 #include "resource.h"
  41 #include "abm.h"
  42 #include "fixed31_32.h"
  43 #include "dpcd_defs.h"
  44 #include "dmcu.h"
  45
  46 #define DC_LOGGER_INIT(logger)
  47
  48
  49 #define LINK_INFO(...) \
  50         DC_LOG_HW_HOTPLUG(  \
  51                 __VA_ARGS__)
  52
  53 #define RETIMER_REDRIVER_INFO(...) \
  54         DC_LOG_RETIMER_REDRIVER(  \
  55                 __VA_ARGS__)
  56 /*******************************************************************************
  57  * Private structures
  58  ******************************************************************************/
  59
  60 enum {
  61         LINK_RATE_REF_FREQ_IN_MHZ = 27,
  62         PEAK_FACTOR_X1000 = 1006,
  63         /*
  64         * Some receivers fail to train on first try and are good
  65         * on subsequent tries. 2 retries should be plenty. If we
  66         * don't have a successful training then we don't expect to
  67         * ever get one.
  68         */
  69         LINK_TRAINING_MAX_VERIFY_RETRY = 2
  70 };
  71
  72 /*******************************************************************************
  73  * Private functions
  74  ******************************************************************************/
  75 static void destruct(struct dc_link *link)
  76 {
  77         int i;
  78
  79         if (link->hpd_gpio != NULL) {
  80                 dal_gpio_close(link->hpd_gpio);
  81                 dal_gpio_destroy_irq(&link->hpd_gpio);
  82                 link->hpd_gpio = NULL;
  83         }
  84
  85         if (link->ddc)
  86                 dal_ddc_service_destroy(&link->ddc);
  87
  88         if(link->link_enc)
  89                 link->link_enc->funcs->destroy(&link->link_enc);
  90
  91         if (link->local_sink)
  92                 dc_sink_release(link->local_sink);
  93
  94         for (i = 0; i < link->sink_count; ++i)
  95                 dc_sink_release(link->remote_sinks[i]);
  96 }
  97
  98 struct gpio *get_hpd_gpio(struct dc_bios *dcb,
  99                 struct graphics_object_id link_id,
 100                 struct gpio_service *gpio_service)
 101 {
 102         enum bp_result bp_result;
 103         struct graphics_object_hpd_info hpd_info;
 104         struct gpio_pin_info pin_info;
 105
 106         if (dcb->funcs->get_hpd_info(dcb, link_id, &hpd_info) != BP_RESULT_OK)
 107                 return NULL;
 108
 109         bp_result = dcb->funcs->get_gpio_pin_info(dcb,
 110                 hpd_info.hpd_int_gpio_uid, &pin_info);
 111
 112         if (bp_result != BP_RESULT_OK) {
 113                 ASSERT(bp_result == BP_RESULT_NORECORD);
 114                 return NULL;
 115         }
 116
 117         return dal_gpio_service_create_irq(
 118                 gpio_service,
 119                 pin_info.offset,
 120                 pin_info.mask);
 121 }
 122
 123 /*
 124  *  Function: program_hpd_filter
 125  *
 126  *  @brief
 127  *     Programs HPD filter on associated HPD line
 128  *
 129  *  @param [in] delay_on_connect_in_ms: Connect filter timeout
 130  *  @param [in] delay_on_disconnect_in_ms: Disconnect filter timeout
 131  *
 132  *  @return
 133  *     true on success, false otherwise
 134  */
 135 static bool program_hpd_filter(
 136         const struct dc_link *link)
 137 {
 138         bool result = false;
 139
 140         struct gpio *hpd;
 141
 142         int delay_on_connect_in_ms = 0;
 143         int delay_on_disconnect_in_ms = 0;
 144
 145         if (link->is_hpd_filter_disabled)
 146                 return false;
 147         /* Verify feature is supported */
 148         switch (link->connector_signal) {
 149         case SIGNAL_TYPE_DVI_SINGLE_LINK:
 150         case SIGNAL_TYPE_DVI_DUAL_LINK:
 151         case SIGNAL_TYPE_HDMI_TYPE_A:
 152                 /* Program hpd filter */
 153                 delay_on_connect_in_ms = 500;
 154                 delay_on_disconnect_in_ms = 100;
 155                 break;
 156         case SIGNAL_TYPE_DISPLAY_PORT:
 157         case SIGNAL_TYPE_DISPLAY_PORT_MST:
 158                 /* Program hpd filter to allow DP signal to settle */
 159                 /* 500: not able to detect MST <-> SST switch as HPD is low for
 160                  *      only 100ms on DELL U2413
 161                  * 0:   some passive dongle still show aux mode instead of i2c
 162                  * 20-50:not enough to hide bouncing HPD with passive dongle.
 163                  *      also see intermittent i2c read issues.
 164                  */
 165                 delay_on_connect_in_ms = 80;
 166                 delay_on_disconnect_in_ms = 0;
 167                 break;
 168         case SIGNAL_TYPE_LVDS:
 169         case SIGNAL_TYPE_EDP:
 170         default:
 171                 /* Don't program hpd filter */
 172                 return false;
 173         }
 174
 175         /* Obtain HPD handle */
 176         hpd = get_hpd_gpio(link->ctx->dc_bios, link->link_id, link->ctx->gpio_service);
 177
 178         if (!hpd)
 179                 return result;
 180
 181         /* Setup HPD filtering */
 182         if (dal_gpio_open(hpd, GPIO_MODE_INTERRUPT) == GPIO_RESULT_OK) {
 183                 struct gpio_hpd_config config;
 184
 185                 config.delay_on_connect = delay_on_connect_in_ms;
 186                 config.delay_on_disconnect = delay_on_disconnect_in_ms;
 187
 188                 dal_irq_setup_hpd_filter(hpd, &config);
 189
 190                 dal_gpio_close(hpd);
 191
 192                 result = true;
 193         } else {
 194                 ASSERT_CRITICAL(false);
 195         }
 196
 197         /* Release HPD handle */
 198         dal_gpio_destroy_irq(&hpd);
 199
 200         return result;
 201 }
 202
 203 /**
 204  * dc_link_detect_sink() - Determine if there is a sink connected
 205  *
 206  * @type: Returned connection type
 207  * Does not detect downstream devices, such as MST sinks
 208  * or display connected through active dongles
 209  */
 210 bool dc_link_detect_sink(struct dc_link *link, enum dc_connection_type *type)
 211 {
 212         uint32_t is_hpd_high = 0;
 213         struct gpio *hpd_pin;
 214
 215         if (link->connector_signal == SIGNAL_TYPE_LVDS) {
 216                 *type = dc_connection_single;
 217                 return true;
 218         }
 219
 220         if (link->connector_signal == SIGNAL_TYPE_EDP)
 221                 link->dc->hwss.edp_wait_for_hpd_ready(link, true);
 222
 223         /* todo: may need to lock gpio access */
 224         hpd_pin = get_hpd_gpio(link->ctx->dc_bios, link->link_id, link->ctx->gpio_service);
 225         if (hpd_pin == NULL)
 226                 goto hpd_gpio_failure;
 227
 228         dal_gpio_open(hpd_pin, GPIO_MODE_INTERRUPT);
 229         dal_gpio_get_value(hpd_pin, &is_hpd_high);
 230         dal_gpio_close(hpd_pin);
 231         dal_gpio_destroy_irq(&hpd_pin);
 232
 233         if (is_hpd_high) {
 234                 *type = dc_connection_single;
 235                 /* TODO: need to do the actual detection */
 236         } else {
 237                 *type = dc_connection_none;
 238         }
 239
 240         return true;
 241
 242 hpd_gpio_failure:
 243         return false;
 244 }
 245
 246 static enum ddc_transaction_type get_ddc_transaction_type(
 247                 enum signal_type sink_signal)
 248 {
 249         enum ddc_transaction_type transaction_type = DDC_TRANSACTION_TYPE_NONE;
 250
 251         switch (sink_signal) {
 252         case SIGNAL_TYPE_DVI_SINGLE_LINK:
 253         case SIGNAL_TYPE_DVI_DUAL_LINK:
 254         case SIGNAL_TYPE_HDMI_TYPE_A:
 255         case SIGNAL_TYPE_LVDS:
 256         case SIGNAL_TYPE_RGB:
 257                 transaction_type = DDC_TRANSACTION_TYPE_I2C;
 258                 break;
 259
 260         case SIGNAL_TYPE_DISPLAY_PORT:
 261         case SIGNAL_TYPE_EDP:
 262                 transaction_type = DDC_TRANSACTION_TYPE_I2C_OVER_AUX;
 263                 break;
 264
 265         case SIGNAL_TYPE_DISPLAY_PORT_MST:
 266                 /* MST does not use I2COverAux, but there is the
 267                  * SPECIAL use case for "immediate dwnstrm device
 268                  * access" (EPR#370830). */
 269                 transaction_type = DDC_TRANSACTION_TYPE_I2C_OVER_AUX;
 270                 break;
 271
 272         default:
 273                 break;
 274         }
 275
 276         return transaction_type;
 277 }
 278
 279 static enum signal_type get_basic_signal_type(
 280         struct graphics_object_id encoder,
 281         struct graphics_object_id downstream)
 282 {
 283         if (downstream.type == OBJECT_TYPE_CONNECTOR) {
 284                 switch (downstream.id) {
 285                 case CONNECTOR_ID_SINGLE_LINK_DVII:
 286                         switch (encoder.id) {
 287                         case ENCODER_ID_INTERNAL_DAC1:
 288                         case ENCODER_ID_INTERNAL_KLDSCP_DAC1:
 289                         case ENCODER_ID_INTERNAL_DAC2:
 290                         case ENCODER_ID_INTERNAL_KLDSCP_DAC2:
 291                                 return SIGNAL_TYPE_RGB;
 292                         default:
 293                                 return SIGNAL_TYPE_DVI_SINGLE_LINK;
 294                         }
 295                 break;
 296                 case CONNECTOR_ID_DUAL_LINK_DVII:
 297                 {
 298                         switch (encoder.id) {
 299                         case ENCODER_ID_INTERNAL_DAC1:
 300                         case ENCODER_ID_INTERNAL_KLDSCP_DAC1:
 301                         case ENCODER_ID_INTERNAL_DAC2:
 302                         case ENCODER_ID_INTERNAL_KLDSCP_DAC2:
 303                                 return SIGNAL_TYPE_RGB;
 304                         default:
 305                                 return SIGNAL_TYPE_DVI_DUAL_LINK;
 306                         }
 307                 }
 308                 break;
 309                 case CONNECTOR_ID_SINGLE_LINK_DVID:
 310                         return SIGNAL_TYPE_DVI_SINGLE_LINK;
 311                 case CONNECTOR_ID_DUAL_LINK_DVID:
 312                         return SIGNAL_TYPE_DVI_DUAL_LINK;
 313                 case CONNECTOR_ID_VGA:
 314                         return SIGNAL_TYPE_RGB;
 315                 case CONNECTOR_ID_HDMI_TYPE_A:
 316                         return SIGNAL_TYPE_HDMI_TYPE_A;
 317                 case CONNECTOR_ID_LVDS:
 318                         return SIGNAL_TYPE_LVDS;
 319                 case CONNECTOR_ID_DISPLAY_PORT:
 320                         return SIGNAL_TYPE_DISPLAY_PORT;
 321                 case CONNECTOR_ID_EDP:
 322                         return SIGNAL_TYPE_EDP;
 323                 default:
 324                         return SIGNAL_TYPE_NONE;
 325                 }
 326         } else if (downstream.type == OBJECT_TYPE_ENCODER) {
 327                 switch (downstream.id) {
 328                 case ENCODER_ID_EXTERNAL_NUTMEG:
 329                 case ENCODER_ID_EXTERNAL_TRAVIS:
 330                         return SIGNAL_TYPE_DISPLAY_PORT;
 331                 default:
 332                         return SIGNAL_TYPE_NONE;
 333                 }
 334         }
 335
 336         return SIGNAL_TYPE_NONE;
 337 }
 338
 339 /**
 340  * dc_link_is_dp_sink_present() - Check if there is a native DP
 341  * or passive DP-HDMI dongle connected
 342  */
 343 bool dc_link_is_dp_sink_present(struct dc_link *link)
 344 {
 345         enum gpio_result gpio_result;
 346         uint32_t clock_pin = 0;
 347         uint8_t retry = 0;
 348         struct ddc *ddc;
 349
 350         enum connector_id connector_id =
 351                 dal_graphics_object_id_get_connector_id(link->link_id);
 352
 353         bool present =
 354                 ((connector_id == CONNECTOR_ID_DISPLAY_PORT) ||
 355                 (connector_id == CONNECTOR_ID_EDP));
 356
 357         ddc = dal_ddc_service_get_ddc_pin(link->ddc);
 358
 359         if (!ddc) {
 360                 BREAK_TO_DEBUGGER();
 361                 return present;
 362         }
 363
 364         /* Open GPIO and set it to I2C mode */
 365         /* Note: this GpioMode_Input will be converted
 366          * to GpioConfigType_I2cAuxDualMode in GPIO component,
 367          * which indicates we need additional delay */
 368
 369         if (GPIO_RESULT_OK != dal_ddc_open(
 370                 ddc, GPIO_MODE_INPUT, GPIO_DDC_CONFIG_TYPE_MODE_I2C)) {
 371                 dal_gpio_destroy_ddc(&ddc);
 372
 373                 return present;
 374         }
 375
 376         /*
 377          * Read GPIO: DP sink is present if both clock and data pins are zero
 378          *
 379          * [W/A] plug-unplug DP cable, sometimes customer board has
 380          * one short pulse on clk_pin(1V, < 1ms). DP will be config to HDMI/DVI
 381          * then monitor can't br light up. Add retry 3 times
 382          * But in real passive dongle, it need additional 3ms to detect
 383          */
 384         do {
 385                 gpio_result = dal_gpio_get_value(ddc->pin_clock, &clock_pin);
 386                 ASSERT(gpio_result == GPIO_RESULT_OK);
 387                 if (clock_pin)
 388                         udelay(1000);
 389                 else
 390                         break;
 391         } while (retry++ < 3);
 392
 393         present = (gpio_result == GPIO_RESULT_OK) && !clock_pin;
 394
 395         dal_ddc_close(ddc);
 396
 397         return present;
 398 }
 399
 400 /*
 401  * @brief
 402  * Detect output sink type
 403  */
 404 static enum signal_type link_detect_sink(
 405         struct dc_link *link,
 406         enum dc_detect_reason reason)
 407 {
 408         enum signal_type result = get_basic_signal_type(
 409                 link->link_enc->id, link->link_id);
 410
 411         /* Internal digital encoder will detect only dongles
 412          * that require digital signal */
 413
 414         /* Detection mechanism is different
 415          * for different native connectors.
 416          * LVDS connector supports only LVDS signal;
 417          * PCIE is a bus slot, the actual connector needs to be detected first;
 418          * eDP connector supports only eDP signal;
 419          * HDMI should check straps for audio */
 420
 421         /* PCIE detects the actual connector on add-on board */
 422
 423         if (link->link_id.id == CONNECTOR_ID_PCIE) {
 424                 /* ZAZTODO implement PCIE add-on card detection */
 425         }
 426
 427         switch (link->link_id.id) {
 428         case CONNECTOR_ID_HDMI_TYPE_A: {
 429                 /* check audio support:
 430                  * if native HDMI is not supported, switch to DVI */
 431                 struct audio_support *aud_support = &link->dc->res_pool->audio_support;
 432
 433                 if (!aud_support->hdmi_audio_native)
 434                         if (link->link_id.id == CONNECTOR_ID_HDMI_TYPE_A)
 435                                 result = SIGNAL_TYPE_DVI_SINGLE_LINK;
 436         }
 437         break;
 438         case CONNECTOR_ID_DISPLAY_PORT: {
 439                 /* DP HPD short pulse. Passive DP dongle will not
 440                  * have short pulse
 441                  */
 442                 if (reason != DETECT_REASON_HPDRX) {
 443                         /* Check whether DP signal detected: if not -
 444                          * we assume signal is DVI; it could be corrected
 445                          * to HDMI after dongle detection
 446                          */
 447                         if (!dm_helpers_is_dp_sink_present(link))
 448                                 result = SIGNAL_TYPE_DVI_SINGLE_LINK;
 449                 }
 450         }
 451         break;
 452         default:
 453         break;
 454         }
 455
 456         return result;
 457 }
 458
 459 static enum signal_type decide_signal_from_strap_and_dongle_type(
 460                 enum display_dongle_type dongle_type,
 461                 struct audio_support *audio_support)
 462 {
 463         enum signal_type signal = SIGNAL_TYPE_NONE;
 464
 465         switch (dongle_type) {
 466         case DISPLAY_DONGLE_DP_HDMI_DONGLE:
 467                 if (audio_support->hdmi_audio_on_dongle)
 468                         signal =  SIGNAL_TYPE_HDMI_TYPE_A;
 469                 else
 470                         signal = SIGNAL_TYPE_DVI_SINGLE_LINK;
 471                 break;
 472         case DISPLAY_DONGLE_DP_DVI_DONGLE:
 473                 signal = SIGNAL_TYPE_DVI_SINGLE_LINK;
 474                 break;
 475         case DISPLAY_DONGLE_DP_HDMI_MISMATCHED_DONGLE:
 476                 if (audio_support->hdmi_audio_native)
 477                         signal =  SIGNAL_TYPE_HDMI_TYPE_A;
 478                 else
 479                         signal = SIGNAL_TYPE_DVI_SINGLE_LINK;
 480                 break;
 481         default:
 482                 signal = SIGNAL_TYPE_NONE;
 483                 break;
 484         }
 485
 486         return signal;
 487 }
 488
 489 static enum signal_type dp_passive_dongle_detection(
 490                 struct ddc_service *ddc,
 491                 struct display_sink_capability *sink_cap,
 492                 struct audio_support *audio_support)
 493 {
 494         dal_ddc_service_i2c_query_dp_dual_mode_adaptor(
 495                                                 ddc, sink_cap);
 496         return decide_signal_from_strap_and_dongle_type(
 497                         sink_cap->dongle_type,
 498                         audio_support);
 499 }
 500
 501 static void link_disconnect_sink(struct dc_link *link)
 502 {
 503         if (link->local_sink) {
 504                 dc_sink_release(link->local_sink);
 505                 link->local_sink = NULL;
 506         }
 507
 508         link->dpcd_sink_count = 0;
 509 }
 510
 511 static void link_disconnect_remap(struct dc_sink *prev_sink, struct dc_link *link)
 512 {
 513         dc_sink_release(link->local_sink);
 514         link->local_sink = prev_sink;
 515 }
 516
 517
 518 static bool detect_dp(
 519         struct dc_link *link,
 520         struct display_sink_capability *sink_caps,
 521         bool *converter_disable_audio,
 522         struct audio_support *audio_support,
 523         enum dc_detect_reason reason)
 524 {
 525         bool boot = false;
 526         sink_caps->signal = link_detect_sink(link, reason);
 527         sink_caps->transaction_type =
 528                 get_ddc_transaction_type(sink_caps->signal);
 529
 530         if (sink_caps->transaction_type == DDC_TRANSACTION_TYPE_I2C_OVER_AUX) {
 531                 sink_caps->signal = SIGNAL_TYPE_DISPLAY_PORT;
 532                 if (!detect_dp_sink_caps(link))
 533                         return false;
 534
 535                 if (is_mst_supported(link)) {
 536                         sink_caps->signal = SIGNAL_TYPE_DISPLAY_PORT_MST;
 537                         link->type = dc_connection_mst_branch;
 538
 539                         dal_ddc_service_set_transaction_type(
 540                                                         link->ddc,
 541                                                         sink_caps->transaction_type);
 542
 543                         /*
 544                          * This call will initiate MST topology discovery. Which
 545                          * will detect MST ports and add new DRM connector DRM
 546                          * framework. Then read EDID via remote i2c over aux. In
 547                          * the end, will notify DRM detect result and save EDID
 548                          * into DRM framework.
 549                          *
 550                          * .detect is called by .fill_modes.
 551                          * .fill_modes is called by user mode ioctl
 552                          * DRM_IOCTL_MODE_GETCONNECTOR.
 553                          *
 554                          * .get_modes is called by .fill_modes.
 555                          *
 556                          * call .get_modes, AMDGPU DM implementation will create
 557                          * new dc_sink and add to dc_link. For long HPD plug
 558                          * in/out, MST has its own handle.
 559                          *
 560                          * Therefore, just after dc_create, link->sink is not
 561                          * created for MST until user mode app calls
 562                          * DRM_IOCTL_MODE_GETCONNECTOR.
 563                          *
 564                          * Need check ->sink usages in case ->sink = NULL
 565                          * TODO: s3 resume check
 566                          */
 567                         if (reason == DETECT_REASON_BOOT)
 568                                 boot = true;
 569
 570                         dm_helpers_dp_update_branch_info(
 571                                 link->ctx,
 572                                 link);
 573
 574                         if (!dm_helpers_dp_mst_start_top_mgr(
 575                                 link->ctx,
 576                                 link, boot)) {
 577                                 /* MST not supported */
 578                                 link->type = dc_connection_single;
 579                                 sink_caps->signal = SIGNAL_TYPE_DISPLAY_PORT;
 580                         }
 581                 }
 582
 583                 if (link->type != dc_connection_mst_branch &&
 584                         is_dp_active_dongle(link)) {
 585                         /* DP active dongles */
 586                         link->type = dc_connection_active_dongle;
 587                         if (!link->dpcd_caps.sink_count.bits.SINK_COUNT) {
 588                                 /*
 589                                  * active dongle unplug processing for short irq
 590                                  */
 591                                 link_disconnect_sink(link);
 592                                 return true;
 593                         }
 594
 595                         if (link->dpcd_caps.dongle_type != DISPLAY_DONGLE_DP_HDMI_CONVERTER)
 596                                 *converter_disable_audio = true;
 597                 }
 598         } else {
 599                 /* DP passive dongles */
 600                 sink_caps->signal = dp_passive_dongle_detection(link->ddc,
 601                                 sink_caps,
 602                                 audio_support);
 603         }
 604
 605         return true;
 606 }
 607
 608 static bool is_same_edid(struct dc_edid *old_edid, struct dc_edid *new_edid)
 609 {
 610         if (old_edid->length != new_edid->length)
 611                 return false;
 612
 613         if (new_edid->length == 0)
 614                 return false;
 615
 616         return (memcmp(old_edid->raw_edid, new_edid->raw_edid, new_edid->length) == 0);
 617 }
 618
 619 /**
 620  * dc_link_detect() - Detect if a sink is attached to a given link
 621  *
 622  * link->local_sink is created or destroyed as needed.
 623  *
 624  * This does not create remote sinks but will trigger DM
 625  * to start MST detection if a branch is detected.
 626  */
 627 bool dc_link_detect(struct dc_link *link, enum dc_detect_reason reason)
 628 {
 629         struct dc_sink_init_data sink_init_data = { 0 };
 630         struct display_sink_capability sink_caps = { 0 };
 631         uint8_t i;
 632         bool converter_disable_audio = false;
 633         struct audio_support *aud_support = &link->dc->res_pool->audio_support;
 634         bool same_edid = false;
 635         enum dc_edid_status edid_status;
 636         struct dc_context *dc_ctx = link->ctx;
 637         struct dc_sink *sink = NULL;
 638         struct dc_sink *prev_sink = NULL;
 639         struct dpcd_caps prev_dpcd_caps;
 640         bool same_dpcd = true;
 641         enum dc_connection_type new_connection_type = dc_connection_none;
 642         DC_LOGGER_INIT(link->ctx->logger);
 643         if (link->connector_signal == SIGNAL_TYPE_VIRTUAL)
 644                 return false;
 645
 646         if (false == dc_link_detect_sink(link, &new_connection_type)) {
 647                 BREAK_TO_DEBUGGER();
 648                 return false;
 649         }
 650
 651         if (link->connector_signal == SIGNAL_TYPE_EDP &&
 652                         link->local_sink)
 653                 return true;
 654
 655         if (link->connector_signal == SIGNAL_TYPE_LVDS &&
 656                         link->local_sink)
 657                 return true;
 658
 659         prev_sink = link->local_sink;
 660         if (prev_sink != NULL) {
 661                 dc_sink_retain(prev_sink);
 662                 memcpy(&prev_dpcd_caps, &link->dpcd_caps, sizeof(struct dpcd_caps));
 663         }
 664         link_disconnect_sink(link);
 665
 666         if (new_connection_type != dc_connection_none) {
 667                 link->type = new_connection_type;
 668
 669                 /* From Disconnected-to-Connected. */
 670                 switch (link->connector_signal) {
 671                 case SIGNAL_TYPE_HDMI_TYPE_A: {
 672                         sink_caps.transaction_type = DDC_TRANSACTION_TYPE_I2C;
 673                         if (aud_support->hdmi_audio_native)
 674                                 sink_caps.signal = SIGNAL_TYPE_HDMI_TYPE_A;
 675                         else
 676                                 sink_caps.signal = SIGNAL_TYPE_DVI_SINGLE_LINK;
 677                         break;
 678                 }
 679
 680                 case SIGNAL_TYPE_DVI_SINGLE_LINK: {
 681                         sink_caps.transaction_type = DDC_TRANSACTION_TYPE_I2C;
 682                         sink_caps.signal = SIGNAL_TYPE_DVI_SINGLE_LINK;
 683                         break;
 684                 }
 685
 686                 case SIGNAL_TYPE_DVI_DUAL_LINK: {
 687                         sink_caps.transaction_type = DDC_TRANSACTION_TYPE_I2C;
 688                         sink_caps.signal = SIGNAL_TYPE_DVI_DUAL_LINK;
 689                         break;
 690                 }
 691
 692                 case SIGNAL_TYPE_LVDS: {
 693                         sink_caps.transaction_type = DDC_TRANSACTION_TYPE_I2C;
 694                         sink_caps.signal = SIGNAL_TYPE_LVDS;
 695                         break;
 696                 }
 697
 698                 case SIGNAL_TYPE_EDP: {
 699                         detect_edp_sink_caps(link);
 700                         sink_caps.transaction_type =
 701                                 DDC_TRANSACTION_TYPE_I2C_OVER_AUX;
 702                         sink_caps.signal = SIGNAL_TYPE_EDP;
 703                         break;
 704                 }
 705
 706                 case SIGNAL_TYPE_DISPLAY_PORT: {
 707                         if (!detect_dp(
 708                                 link,
 709                                 &sink_caps,
 710                                 &converter_disable_audio,
 711                                 aud_support, reason)) {
 712                                 if (prev_sink != NULL)
 713                                         dc_sink_release(prev_sink);
 714                                 return false;
 715                         }
 716
 717                         // Check if dpcp block is the same
 718                         if (prev_sink != NULL) {
 719                                 if (memcmp(&link->dpcd_caps, &prev_dpcd_caps, sizeof(struct dpcd_caps)))
 720                                         same_dpcd = false;
 721                         }
 722                         /* Active dongle plug in without display or downstream unplug*/
 723                         if (link->type == dc_connection_active_dongle &&
 724                                 link->dpcd_caps.sink_count.bits.SINK_COUNT == 0) {
 725                                 if (prev_sink != NULL) {
 726                                         /* Downstream unplug */
 727                                         dc_sink_release(prev_sink);
 728                                 } else {
 729                                         /* Empty dongle plug in */
 730                                         for (i = 0; i < LINK_TRAINING_MAX_VERIFY_RETRY; i++) {
 731                                                 int fail_count = 0;
 732
 733                                                 dp_verify_link_cap(link,
 734                                                                   &link->reported_link_cap,
 735                                                                   &fail_count);
 736
 737                                                 if (fail_count == 0)
 738                                                         break;
 739                                         }
 740                                 }
 741                                 return true;
 742                         }
 743
 744                         if (link->type == dc_connection_mst_branch) {
 745                                 LINK_INFO("link=%d, mst branch is now Connected\n",
 746                                         link->link_index);
 747                                 /* Need to setup mst link_cap struct here
 748                                  * otherwise dc_link_detect() will leave mst link_cap
 749                                  * empty which leads to allocate_mst_payload() has "0"
 750                                  * pbn_per_slot value leading to exception on dc_fixpt_div()
 751                                  */
 752                                 link->verified_link_cap = link->reported_link_cap;
 753                                 if (prev_sink != NULL)
 754                                         dc_sink_release(prev_sink);
 755                                 return false;
 756                         }
 757
 758                         break;
 759                 }
 760
 761                 default:
 762                         DC_ERROR("Invalid connector type! signal:%d\n",
 763                                 link->connector_signal);
 764                         if (prev_sink != NULL)
 765                                 dc_sink_release(prev_sink);
 766                         return false;
 767                 } /* switch() */
 768
 769                 if (link->dpcd_caps.sink_count.bits.SINK_COUNT)
 770                         link->dpcd_sink_count = link->dpcd_caps.sink_count.
 771                                         bits.SINK_COUNT;
 772                 else
 773                         link->dpcd_sink_count = 1;
 774
 775                 dal_ddc_service_set_transaction_type(
 776                                                 link->ddc,
 777                                                 sink_caps.transaction_type);
 778
 779                 link->aux_mode = dal_ddc_service_is_in_aux_transaction_mode(
 780                                 link->ddc);
 781
 782                 sink_init_data.link = link;
 783                 sink_init_data.sink_signal = sink_caps.signal;
 784
 785                 sink = dc_sink_create(&sink_init_data);
 786                 if (!sink) {
 787                         DC_ERROR("Failed to create sink!\n");
 788                         if (prev_sink != NULL)
 789                                 dc_sink_release(prev_sink);
 790                         return false;
 791                 }
 792
 793                 sink->link->dongle_max_pix_clk = sink_caps.max_hdmi_pixel_clock;
 794                 sink->converter_disable_audio = converter_disable_audio;
 795
 796                 /* dc_sink_create returns a new reference */
 797                 link->local_sink = sink;
 798
 799                 edid_status = dm_helpers_read_local_edid(
 800                                 link->ctx,
 801                                 link,
 802                                 sink);
 803
 804                 switch (edid_status) {
 805                 case EDID_BAD_CHECKSUM:
 806                         DC_LOG_ERROR("EDID checksum invalid.\n");
 807                         break;
 808                 case EDID_NO_RESPONSE:
 809                         DC_LOG_ERROR("No EDID read.\n");
 810
 811                         /*
 812                          * Abort detection for non-DP connectors if we have
 813                          * no EDID
 814                          *
 815                          * DP needs to report as connected if HDP is high
 816                          * even if we have no EDID in order to go to
 817                          * fail-safe mode
 818                          */
 819                         if (dc_is_hdmi_signal(link->connector_signal) ||
 820                             dc_is_dvi_signal(link->connector_signal)) {
 821                                 if (prev_sink != NULL)
 822                                         dc_sink_release(prev_sink);
 823
 824                                 return false;
 825                         }
 826                 default:
 827                         break;
 828                 }
 829
 830                 // Check if edid is the same
 831                 if ((prev_sink != NULL) && ((edid_status == EDID_THE_SAME) || (edid_status == EDID_OK)))
 832                         same_edid = is_same_edid(&prev_sink->dc_edid, &sink->dc_edid);
 833
 834                 if (link->connector_signal == SIGNAL_TYPE_DISPLAY_PORT &&
 835                         sink_caps.transaction_type == DDC_TRANSACTION_TYPE_I2C_OVER_AUX &&
 836                         reason != DETECT_REASON_HPDRX) {
 837                         /*
 838                          * TODO debug why Dell 2413 doesn't like
 839                          *  two link trainings
 840                          */
 841
 842                         /* deal with non-mst cases */
 843                         for (i = 0; i < LINK_TRAINING_MAX_VERIFY_RETRY; i++) {
 844                                 int fail_count = 0;
 845
 846                                 dp_verify_link_cap(link,
 847                                                   &link->reported_link_cap,
 848                                                   &fail_count);
 849
 850                                 if (fail_count == 0)
 851                                         break;
 852                         }
 853
 854                 } else {
 855                         // If edid is the same, then discard new sink and revert back to original sink
 856                         if (same_edid) {
 857                                 link_disconnect_remap(prev_sink, link);
 858                                 sink = prev_sink;
 859                                 prev_sink = NULL;
 860
 861                         }
 862                 }
 863
 864                 /* HDMI-DVI Dongle */
 865                 if (sink->sink_signal == SIGNAL_TYPE_HDMI_TYPE_A &&
 866                                 !sink->edid_caps.edid_hdmi)
 867                         sink->sink_signal = SIGNAL_TYPE_DVI_SINGLE_LINK;
 868
 869                 /* Connectivity log: detection */
 870                 for (i = 0; i < sink->dc_edid.length / EDID_BLOCK_SIZE; i++) {
 871                         CONN_DATA_DETECT(link,
 872                                         &sink->dc_edid.raw_edid[i * EDID_BLOCK_SIZE],
 873                                         EDID_BLOCK_SIZE,
 874                                         "%s: [Block %d] ", sink->edid_caps.display_name, i);
 875                 }
 876
 877                 DC_LOG_DETECTION_EDID_PARSER("%s: "
 878                         "manufacturer_id = %X, "
 879                         "product_id = %X, "
 880                         "serial_number = %X, "
 881                         "manufacture_week = %d, "
 882                         "manufacture_year = %d, "
 883                         "display_name = %s, "
 884                         "speaker_flag = %d, "
 885                         "audio_mode_count = %d\n",
 886                         __func__,
 887                         sink->edid_caps.manufacturer_id,
 888                         sink->edid_caps.product_id,
 889                         sink->edid_caps.serial_number,
 890                         sink->edid_caps.manufacture_week,
 891                         sink->edid_caps.manufacture_year,
 892                         sink->edid_caps.display_name,
 893                         sink->edid_caps.speaker_flags,
 894                         sink->edid_caps.audio_mode_count);
 895
 896                 for (i = 0; i < sink->edid_caps.audio_mode_count; i++) {
 897                         DC_LOG_DETECTION_EDID_PARSER("%s: mode number = %d, "
 898                                 "format_code = %d, "
 899                                 "channel_count = %d, "
 900                                 "sample_rate = %d, "
 901                                 "sample_size = %d\n",
 902                                 __func__,
 903                                 i,
 904                                 sink->edid_caps.audio_modes[i].format_code,
 905                                 sink->edid_caps.audio_modes[i].channel_count,
 906                                 sink->edid_caps.audio_modes[i].sample_rate,
 907                                 sink->edid_caps.audio_modes[i].sample_size);
 908                 }
 909
 910         } else {
 911                 /* From Connected-to-Disconnected. */
 912                 if (link->type == dc_connection_mst_branch) {
 913                         LINK_INFO("link=%d, mst branch is now Disconnected\n",
 914                                 link->link_index);
 915
 916                         dm_helpers_dp_mst_stop_top_mgr(link->ctx, link);
 917
 918                         link->mst_stream_alloc_table.stream_count = 0;
 919                         memset(link->mst_stream_alloc_table.stream_allocations, 0, sizeof(link->mst_stream_alloc_table.stream_allocations));
 920                 }
 921
 922                 link->type = dc_connection_none;
 923                 sink_caps.signal = SIGNAL_TYPE_NONE;
 924         }
 925
 926         LINK_INFO("link=%d, dc_sink_in=%p is now %s prev_sink=%p dpcd same=%d edid same=%d\n",
 927                 link->link_index, sink,
 928                 (sink_caps.signal == SIGNAL_TYPE_NONE ?
 929                         "Disconnected":"Connected"), prev_sink,
 930                         same_dpcd, same_edid);
 931
 932         if (prev_sink != NULL)
 933                 dc_sink_release(prev_sink);
 934
 935         return true;
 936 }
 937
 938 bool dc_link_get_hpd_state(struct dc_link *dc_link)
 939 {
 940         uint32_t state;
 941
 942         dal_gpio_lock_pin(dc_link->hpd_gpio);
 943         dal_gpio_get_value(dc_link->hpd_gpio, &state);
 944         dal_gpio_unlock_pin(dc_link->hpd_gpio);
 945
 946         return state;
 947 }
 948
 949 static enum hpd_source_id get_hpd_line(
 950                 struct dc_link *link)
 951 {
 952         struct gpio *hpd;
 953         enum hpd_source_id hpd_id = HPD_SOURCEID_UNKNOWN;
 954
 955         hpd = get_hpd_gpio(link->ctx->dc_bios, link->link_id, link->ctx->gpio_service);
 956
 957         if (hpd) {
 958                 switch (dal_irq_get_source(hpd)) {
 959                 case DC_IRQ_SOURCE_HPD1:
 960                         hpd_id = HPD_SOURCEID1;
 961                 break;
 962                 case DC_IRQ_SOURCE_HPD2:
 963                         hpd_id = HPD_SOURCEID2;
 964                 break;
 965                 case DC_IRQ_SOURCE_HPD3:
 966                         hpd_id = HPD_SOURCEID3;
 967                 break;
 968                 case DC_IRQ_SOURCE_HPD4:
 969                         hpd_id = HPD_SOURCEID4;
 970                 break;
 971                 case DC_IRQ_SOURCE_HPD5:
 972                         hpd_id = HPD_SOURCEID5;
 973                 break;
 974                 case DC_IRQ_SOURCE_HPD6:
 975                         hpd_id = HPD_SOURCEID6;
 976                 break;
 977                 default:
 978                         BREAK_TO_DEBUGGER();
 979                 break;
 980                 }
 981
 982                 dal_gpio_destroy_irq(&hpd);
 983         }
 984
 985         return hpd_id;
 986 }
 987
 988 static enum channel_id get_ddc_line(struct dc_link *link)
 989 {
 990         struct ddc *ddc;
 991         enum channel_id channel = CHANNEL_ID_UNKNOWN;
 992
 993         ddc = dal_ddc_service_get_ddc_pin(link->ddc);
 994
 995         if (ddc) {
 996                 switch (dal_ddc_get_line(ddc)) {
 997                 case GPIO_DDC_LINE_DDC1:
 998                         channel = CHANNEL_ID_DDC1;
 999                         break;
1000                 case GPIO_DDC_LINE_DDC2:
1001                         channel = CHANNEL_ID_DDC2;
1002                         break;
1003                 case GPIO_DDC_LINE_DDC3:
1004                         channel = CHANNEL_ID_DDC3;
1005                         break;
1006                 case GPIO_DDC_LINE_DDC4:
1007                         channel = CHANNEL_ID_DDC4;
1008                         break;
1009                 case GPIO_DDC_LINE_DDC5:
1010                         channel = CHANNEL_ID_DDC5;
1011                         break;
1012                 case GPIO_DDC_LINE_DDC6:
1013                         channel = CHANNEL_ID_DDC6;
1014                         break;
1015                 case GPIO_DDC_LINE_DDC_VGA:
1016                         channel = CHANNEL_ID_DDC_VGA;
1017                         break;
1018                 case GPIO_DDC_LINE_I2C_PAD:
1019                         channel = CHANNEL_ID_I2C_PAD;
1020                         break;
1021                 default:
1022                         BREAK_TO_DEBUGGER();
1023                         break;
1024                 }
1025         }
1026
1027         return channel;
1028 }
1029
1030 static enum transmitter translate_encoder_to_transmitter(
1031         struct graphics_object_id encoder)
1032 {
1033         switch (encoder.id) {
1034         case ENCODER_ID_INTERNAL_UNIPHY:
1035                 switch (encoder.enum_id) {
1036                 case ENUM_ID_1:
1037                         return TRANSMITTER_UNIPHY_A;
1038                 case ENUM_ID_2:
1039                         return TRANSMITTER_UNIPHY_B;
1040                 default:
1041                         return TRANSMITTER_UNKNOWN;
1042                 }
1043         break;
1044         case ENCODER_ID_INTERNAL_UNIPHY1:
1045                 switch (encoder.enum_id) {
1046                 case ENUM_ID_1:
1047                         return TRANSMITTER_UNIPHY_C;
1048                 case ENUM_ID_2:
1049                         return TRANSMITTER_UNIPHY_D;
1050                 default:
1051                         return TRANSMITTER_UNKNOWN;
1052                 }
1053         break;
1054         case ENCODER_ID_INTERNAL_UNIPHY2:
1055                 switch (encoder.enum_id) {
1056                 case ENUM_ID_1:
1057                         return TRANSMITTER_UNIPHY_E;
1058                 case ENUM_ID_2:
1059                         return TRANSMITTER_UNIPHY_F;
1060                 default:
1061                         return TRANSMITTER_UNKNOWN;
1062                 }
1063         break;
1064         case ENCODER_ID_INTERNAL_UNIPHY3:
1065                 switch (encoder.enum_id) {
1066                 case ENUM_ID_1:
1067                         return TRANSMITTER_UNIPHY_G;
1068                 default:
1069                         return TRANSMITTER_UNKNOWN;
1070                 }
1071         break;
1072         case ENCODER_ID_EXTERNAL_NUTMEG:
1073                 switch (encoder.enum_id) {
1074                 case ENUM_ID_1:
1075                         return TRANSMITTER_NUTMEG_CRT;
1076                 default:
1077                         return TRANSMITTER_UNKNOWN;
1078                 }
1079         break;
1080         case ENCODER_ID_EXTERNAL_TRAVIS:
1081                 switch (encoder.enum_id) {
1082                 case ENUM_ID_1:
1083                         return TRANSMITTER_TRAVIS_CRT;
1084                 case ENUM_ID_2:
1085                         return TRANSMITTER_TRAVIS_LCD;
1086                 default:
1087                         return TRANSMITTER_UNKNOWN;
1088                 }
1089         break;
1090         default:
1091                 return TRANSMITTER_UNKNOWN;
1092         }
1093 }
1094
1095 static bool construct(
1096         struct dc_link *link,
1097         const struct link_init_data *init_params)
1098 {
1099         uint8_t i;
1100         struct ddc_service_init_data ddc_service_init_data = { { 0 } };
1101         struct dc_context *dc_ctx = init_params->ctx;
1102         struct encoder_init_data enc_init_data = { 0 };
1103         struct integrated_info info = {{{ 0 }}};
1104         struct dc_bios *bios = init_params->dc->ctx->dc_bios;
1105         const struct dc_vbios_funcs *bp_funcs = bios->funcs;
1106         DC_LOGGER_INIT(dc_ctx->logger);
1107
1108         link->irq_source_hpd = DC_IRQ_SOURCE_INVALID;
1109         link->irq_source_hpd_rx = DC_IRQ_SOURCE_INVALID;
1110
1111         link->link_status.dpcd_caps = &link->dpcd_caps;
1112
1113         link->dc = init_params->dc;
1114         link->ctx = dc_ctx;
1115         link->link_index = init_params->link_index;
1116
1117         link->link_id = bios->funcs->get_connector_id(bios, init_params->connector_index);
1118
1119         if (link->link_id.type != OBJECT_TYPE_CONNECTOR) {
1120                 dm_error("%s: Invalid Connector ObjectID from Adapter Service for connector index:%d! type %d expected %d\n",
1121                          __func__, init_params->connector_index,
1122                          link->link_id.type, OBJECT_TYPE_CONNECTOR);
1123                 goto create_fail;
1124         }
1125
1126         if (link->dc->res_pool->funcs->link_init)
1127                 link->dc->res_pool->funcs->link_init(link);
1128
1129         link->hpd_gpio = get_hpd_gpio(link->ctx->dc_bios, link->link_id, link->ctx->gpio_service);
1130         if (link->hpd_gpio != NULL) {
1131                 dal_gpio_open(link->hpd_gpio, GPIO_MODE_INTERRUPT);
1132                 dal_gpio_unlock_pin(link->hpd_gpio);
1133                 link->irq_source_hpd = dal_irq_get_source(link->hpd_gpio);
1134         }
1135
1136         switch (link->link_id.id) {
1137         case CONNECTOR_ID_HDMI_TYPE_A:
1138                 link->connector_signal = SIGNAL_TYPE_HDMI_TYPE_A;
1139
1140                 break;
1141         case CONNECTOR_ID_SINGLE_LINK_DVID:
1142         case CONNECTOR_ID_SINGLE_LINK_DVII:
1143                 link->connector_signal = SIGNAL_TYPE_DVI_SINGLE_LINK;
1144                 break;
1145         case CONNECTOR_ID_DUAL_LINK_DVID:
1146         case CONNECTOR_ID_DUAL_LINK_DVII:
1147                 link->connector_signal = SIGNAL_TYPE_DVI_DUAL_LINK;
1148                 break;
1149         case CONNECTOR_ID_DISPLAY_PORT:
1150                 link->connector_signal =        SIGNAL_TYPE_DISPLAY_PORT;
1151
1152                 if (link->hpd_gpio != NULL)
1153                         link->irq_source_hpd_rx =
1154                                         dal_irq_get_rx_source(link->hpd_gpio);
1155
1156                 break;
1157         case CONNECTOR_ID_EDP:
1158                 link->connector_signal = SIGNAL_TYPE_EDP;
1159
1160                 if (link->hpd_gpio != NULL) {
1161                         link->irq_source_hpd = DC_IRQ_SOURCE_INVALID;
1162                         link->irq_source_hpd_rx =
1163                                         dal_irq_get_rx_source(link->hpd_gpio);
1164                 }
1165                 break;
1166         case CONNECTOR_ID_LVDS:
1167                 link->connector_signal = SIGNAL_TYPE_LVDS;
1168                 break;
1169         default:
1170                 DC_LOG_WARNING("Unsupported Connector type:%d!\n", link->link_id.id);
1171                 goto create_fail;
1172         }
1173
1174
1175
1176         /* TODO: #DAL3 Implement id to str function.*/
1177         LINK_INFO("Connector[%d] description:"
1178                         "signal %d\n",
1179                         init_params->connector_index,
1180                         link->connector_signal);
1181
1182         ddc_service_init_data.ctx = link->ctx;
1183         ddc_service_init_data.id = link->link_id;
1184         ddc_service_init_data.link = link;
1185         link->ddc = dal_ddc_service_create(&ddc_service_init_data);
1186
1187         if (link->ddc == NULL) {
1188                 DC_ERROR("Failed to create ddc_service!\n");
1189                 goto ddc_create_fail;
1190         }
1191
1192         link->ddc_hw_inst =
1193                 dal_ddc_get_line(
1194                         dal_ddc_service_get_ddc_pin(link->ddc));
1195
1196         enc_init_data.ctx = dc_ctx;
1197         bp_funcs->get_src_obj(dc_ctx->dc_bios, link->link_id, 0, &enc_init_data.encoder);
1198         enc_init_data.connector = link->link_id;
1199         enc_init_data.channel = get_ddc_line(link);
1200         enc_init_data.hpd_source = get_hpd_line(link);
1201
1202         link->hpd_src = enc_init_data.hpd_source;
1203
1204         enc_init_data.transmitter =
1205                         translate_encoder_to_transmitter(enc_init_data.encoder);
1206         link->link_enc = link->dc->res_pool->funcs->link_enc_create(
1207                                                                 &enc_init_data);
1208
1209         if (link->link_enc == NULL) {
1210                 DC_ERROR("Failed to create link encoder!\n");
1211                 goto link_enc_create_fail;
1212         }
1213
1214         link->link_enc_hw_inst = link->link_enc->transmitter;
1215
1216         for (i = 0; i < 4; i++) {
1217                 if (BP_RESULT_OK !=
1218                                 bp_funcs->get_device_tag(dc_ctx->dc_bios, link->link_id, i, &link->device_tag)) {
1219                         DC_ERROR("Failed to find device tag!\n");
1220                         goto device_tag_fail;
1221                 }
1222
1223                 /* Look for device tag that matches connector signal,
1224                  * CRT for rgb, LCD for other supported signal tyes
1225                  */
1226                 if (!bp_funcs->is_device_id_supported(dc_ctx->dc_bios, link->device_tag.dev_id))
1227                         continue;
1228                 if (link->device_tag.dev_id.device_type == DEVICE_TYPE_CRT
1229                         && link->connector_signal != SIGNAL_TYPE_RGB)
1230                         continue;
1231                 if (link->device_tag.dev_id.device_type == DEVICE_TYPE_LCD
1232                         && link->connector_signal == SIGNAL_TYPE_RGB)
1233                         continue;
1234                 break;
1235         }
1236
1237         if (bios->integrated_info)
1238                 info = *bios->integrated_info;
1239
1240         /* Look for channel mapping corresponding to connector and device tag */
1241         for (i = 0; i < MAX_NUMBER_OF_EXT_DISPLAY_PATH; i++) {
1242                 struct external_display_path *path =
1243                         &info.ext_disp_conn_info.path[i];
1244                 if (path->device_connector_id.enum_id == link->link_id.enum_id
1245                         && path->device_connector_id.id == link->link_id.id
1246                         && path->device_connector_id.type == link->link_id.type) {
1247
1248                         if (link->device_tag.acpi_device != 0
1249                                 && path->device_acpi_enum == link->device_tag.acpi_device) {
1250                                 link->ddi_channel_mapping = path->channel_mapping;
1251                                 link->chip_caps = path->caps;
1252                         } else if (path->device_tag ==
1253                                         link->device_tag.dev_id.raw_device_tag) {
1254                                 link->ddi_channel_mapping = path->channel_mapping;
1255                                 link->chip_caps = path->caps;
1256                         }
1257                         break;
1258                 }
1259         }
1260
1261         /*
1262          * TODO check if GPIO programmed correctly
1263          *
1264          * If GPIO isn't programmed correctly HPD might not rise or drain
1265          * fast enough, leading to bounces.
1266          */
1267         program_hpd_filter(link);
1268
1269         return true;
1270 device_tag_fail:
1271         link->link_enc->funcs->destroy(&link->link_enc);
1272 link_enc_create_fail:
1273         dal_ddc_service_destroy(&link->ddc);
1274 ddc_create_fail:
1275 create_fail:
1276
1277         if (link->hpd_gpio != NULL) {
1278                 dal_gpio_destroy_irq(&link->hpd_gpio);
1279                 link->hpd_gpio = NULL;
1280         }
1281
1282         return false;
1283 }
1284
1285 /*******************************************************************************
1286  * Public functions
1287  ******************************************************************************/
1288 struct dc_link *link_create(const struct link_init_data *init_params)
1289 {
1290         struct dc_link *link =
1291                         kzalloc(sizeof(*link), GFP_KERNEL);
1292
1293         if (NULL == link)
1294                 goto alloc_fail;
1295
1296         if (false == construct(link, init_params))
1297                 goto construct_fail;
1298
1299         return link;
1300
1301 construct_fail:
1302         kfree(link);
1303
1304 alloc_fail:
1305         return NULL;
1306 }
1307
1308 void link_destroy(struct dc_link **link)
1309 {
1310         destruct(*link);
1311         kfree(*link);
1312         *link = NULL;
1313 }
1314
1315 static void dpcd_configure_panel_mode(
1316         struct dc_link *link,
1317         enum dp_panel_mode panel_mode)
1318 {
1319         union dpcd_edp_config edp_config_set;
1320         bool panel_mode_edp = false;
1321         DC_LOGGER_INIT(link->ctx->logger);
1322
1323         memset(&edp_config_set, '\0', sizeof(union dpcd_edp_config));
1324
1325         if (DP_PANEL_MODE_DEFAULT != panel_mode) {
1326
1327                 switch (panel_mode) {
1328                 case DP_PANEL_MODE_EDP:
1329                 case DP_PANEL_MODE_SPECIAL:
1330                         panel_mode_edp = true;
1331                         break;
1332
1333                 default:
1334                         break;
1335                 }
1336
1337                 /*set edp panel mode in receiver*/
1338                 core_link_read_dpcd(
1339                         link,
1340                         DP_EDP_CONFIGURATION_SET,
1341                         &edp_config_set.raw,
1342                         sizeof(edp_config_set.raw));
1343
1344                 if (edp_config_set.bits.PANEL_MODE_EDP
1345                         != panel_mode_edp) {
1346                         enum ddc_result result = DDC_RESULT_UNKNOWN;
1347
1348                         edp_config_set.bits.PANEL_MODE_EDP =
1349                         panel_mode_edp;
1350                         result = core_link_write_dpcd(
1351                                 link,
1352                                 DP_EDP_CONFIGURATION_SET,
1353                                 &edp_config_set.raw,
1354                                 sizeof(edp_config_set.raw));
1355
1356                         ASSERT(result == DDC_RESULT_SUCESSFULL);
1357                 }
1358         }
1359         DC_LOG_DETECTION_DP_CAPS("Link: %d eDP panel mode supported: %d "
1360                         "eDP panel mode enabled: %d \n",
1361                         link->link_index,
1362                         link->dpcd_caps.panel_mode_edp,
1363                         panel_mode_edp);
1364 }
1365
1366 static void enable_stream_features(struct pipe_ctx *pipe_ctx)
1367 {
1368         struct dc_stream_state *stream = pipe_ctx->stream;
1369         struct dc_link *link = stream->link;
1370         union down_spread_ctrl old_downspread;
1371         union down_spread_ctrl new_downspread;
1372
1373         core_link_read_dpcd(link, DP_DOWNSPREAD_CTRL,
1374                         &old_downspread.raw, sizeof(old_downspread));
1375
1376         new_downspread.raw = old_downspread.raw;
1377
1378         new_downspread.bits.IGNORE_MSA_TIMING_PARAM =
1379                         (stream->ignore_msa_timing_param) ? 1 : 0;
1380
1381         if (new_downspread.raw != old_downspread.raw) {
1382                 core_link_write_dpcd(link, DP_DOWNSPREAD_CTRL,
1383                         &new_downspread.raw, sizeof(new_downspread));
1384         }
1385 }
1386
1387 static enum dc_status enable_link_dp(
1388                 struct dc_state *state,
1389                 struct pipe_ctx *pipe_ctx)
1390 {
1391         struct dc_stream_state *stream = pipe_ctx->stream;
1392         enum dc_status status;
1393         bool skip_video_pattern;
1394         struct dc_link *link = stream->link;
1395         struct dc_link_settings link_settings = {0};
1396         enum dp_panel_mode panel_mode;
1397
1398         /* get link settings for video mode timing */
1399         decide_link_settings(stream, &link_settings);
1400
1401         pipe_ctx->stream_res.pix_clk_params.requested_sym_clk =
1402                         link_settings.link_rate * LINK_RATE_REF_FREQ_IN_KHZ;
1403         state->dccg->funcs->update_clocks(state->dccg, state, false);
1404
1405         dp_enable_link_phy(
1406                 link,
1407                 pipe_ctx->stream->signal,
1408                 pipe_ctx->clock_source->id,
1409                 &link_settings);
1410
1411         if (stream->sink_patches.dppowerup_delay > 0) {
1412                 int delay_dp_power_up_in_ms = stream->sink_patches.dppowerup_delay;
1413
1414                 msleep(delay_dp_power_up_in_ms);
1415         }
1416
1417         panel_mode = dp_get_panel_mode(link);
1418         dpcd_configure_panel_mode(link, panel_mode);
1419
1420         skip_video_pattern = true;
1421
1422         if (link_settings.link_rate == LINK_RATE_LOW)
1423                         skip_video_pattern = false;
1424
1425         if (perform_link_training_with_retries(
1426                         link,
1427                         &link_settings,
1428                         skip_video_pattern,
1429                         LINK_TRAINING_ATTEMPTS)) {
1430                 link->cur_link_settings = link_settings;
1431                 status = DC_OK;
1432         }
1433         else
1434                 status = DC_FAIL_DP_LINK_TRAINING;
1435
1436         return status;
1437 }
1438
1439 static enum dc_status enable_link_edp(
1440                 struct dc_state *state,
1441                 struct pipe_ctx *pipe_ctx)
1442 {
1443         enum dc_status status;
1444         struct dc_stream_state *stream = pipe_ctx->stream;
1445         struct dc_link *link = stream->link;
1446         /*in case it is not on*/
1447         link->dc->hwss.edp_power_control(link, true);
1448         link->dc->hwss.edp_wait_for_hpd_ready(link, true);
1449
1450         status = enable_link_dp(state, pipe_ctx);
1451
1452
1453         return status;
1454 }
1455
1456 static enum dc_status enable_link_dp_mst(
1457                 struct dc_state *state,
1458                 struct pipe_ctx *pipe_ctx)
1459 {
1460         struct dc_link *link = pipe_ctx->stream->link;
1461
1462         /* sink signal type after MST branch is MST. Multiple MST sinks
1463          * share one link. Link DP PHY is enable or training only once.
1464          */
1465         if (link->cur_link_settings.lane_count != LANE_COUNT_UNKNOWN)
1466                 return DC_OK;
1467
1468         /* clear payload table */
1469         dm_helpers_dp_mst_clear_payload_allocation_table(link->ctx, link);
1470
1471         /* to make sure the pending down rep can be processed
1472          * before enabling the link
1473          */
1474         dm_helpers_dp_mst_poll_pending_down_reply(link->ctx, link);
1475
1476         /* set the sink to MST mode before enabling the link */
1477         dp_enable_mst_on_sink(link, true);
1478
1479         return enable_link_dp(state, pipe_ctx);
1480 }
1481
1482 static bool get_ext_hdmi_settings(struct pipe_ctx *pipe_ctx,
1483                 enum engine_id eng_id,
1484                 struct ext_hdmi_settings *settings)
1485 {
1486         bool result = false;
1487         int i = 0;
1488         struct integrated_info *integrated_info =
1489                         pipe_ctx->stream->ctx->dc_bios->integrated_info;
1490
1491         if (integrated_info == NULL)
1492                 return false;
1493
1494         /*
1495          * Get retimer settings from sbios for passing SI eye test for DCE11
1496          * The setting values are varied based on board revision and port id
1497          * Therefore the setting values of each ports is passed by sbios.
1498          */
1499
1500         // Check if current bios contains ext Hdmi settings
1501         if (integrated_info->gpu_cap_info & 0x20) {
1502                 switch (eng_id) {
1503                 case ENGINE_ID_DIGA:
1504                         settings->slv_addr = integrated_info->dp0_ext_hdmi_slv_addr;
1505                         settings->reg_num = integrated_info->dp0_ext_hdmi_6g_reg_num;
1506                         settings->reg_num_6g = integrated_info->dp0_ext_hdmi_6g_reg_num;
1507                         memmove(settings->reg_settings,
1508                                         integrated_info->dp0_ext_hdmi_reg_settings,
1509                                         sizeof(integrated_info->dp0_ext_hdmi_reg_settings));
1510                         memmove(settings->reg_settings_6g,
1511                                         integrated_info->dp0_ext_hdmi_6g_reg_settings,
1512                                         sizeof(integrated_info->dp0_ext_hdmi_6g_reg_settings));
1513                         result = true;
1514                         break;
1515                 case ENGINE_ID_DIGB:
1516                         settings->slv_addr = integrated_info->dp1_ext_hdmi_slv_addr;
1517                         settings->reg_num = integrated_info->dp1_ext_hdmi_6g_reg_num;
1518                         settings->reg_num_6g = integrated_info->dp1_ext_hdmi_6g_reg_num;
1519                         memmove(settings->reg_settings,
1520                                         integrated_info->dp1_ext_hdmi_reg_settings,
1521                                         sizeof(integrated_info->dp1_ext_hdmi_reg_settings));
1522                         memmove(settings->reg_settings_6g,
1523                                         integrated_info->dp1_ext_hdmi_6g_reg_settings,
1524                                         sizeof(integrated_info->dp1_ext_hdmi_6g_reg_settings));
1525                         result = true;
1526                         break;
1527                 case ENGINE_ID_DIGC:
1528                         settings->slv_addr = integrated_info->dp2_ext_hdmi_slv_addr;
1529                         settings->reg_num = integrated_info->dp2_ext_hdmi_6g_reg_num;
1530                         settings->reg_num_6g = integrated_info->dp2_ext_hdmi_6g_reg_num;
1531                         memmove(settings->reg_settings,
1532                                         integrated_info->dp2_ext_hdmi_reg_settings,
1533                                         sizeof(integrated_info->dp2_ext_hdmi_reg_settings));
1534                         memmove(settings->reg_settings_6g,
1535                                         integrated_info->dp2_ext_hdmi_6g_reg_settings,
1536                                         sizeof(integrated_info->dp2_ext_hdmi_6g_reg_settings));
1537                         result = true;
1538                         break;
1539                 case ENGINE_ID_DIGD:
1540                         settings->slv_addr = integrated_info->dp3_ext_hdmi_slv_addr;
1541                         settings->reg_num = integrated_info->dp3_ext_hdmi_6g_reg_num;
1542                         settings->reg_num_6g = integrated_info->dp3_ext_hdmi_6g_reg_num;
1543                         memmove(settings->reg_settings,
1544                                         integrated_info->dp3_ext_hdmi_reg_settings,
1545                                         sizeof(integrated_info->dp3_ext_hdmi_reg_settings));
1546                         memmove(settings->reg_settings_6g,
1547                                         integrated_info->dp3_ext_hdmi_6g_reg_settings,
1548                                         sizeof(integrated_info->dp3_ext_hdmi_6g_reg_settings));
1549                         result = true;
1550                         break;
1551                 default:
1552                         break;
1553                 }
1554
1555                 if (result == true) {
1556                         // Validate settings from bios integrated info table
1557                         if (settings->slv_addr == 0)
1558                                 return false;
1559                         if (settings->reg_num > 9)
1560                                 return false;
1561                         if (settings->reg_num_6g > 3)
1562                                 return false;
1563
1564                         for (i = 0; i < settings->reg_num; i++) {
1565                                 if (settings->reg_settings[i].i2c_reg_index > 0x20)
1566                                         return false;
1567                         }
1568
1569                         for (i = 0; i < settings->reg_num_6g; i++) {
1570                                 if (settings->reg_settings_6g[i].i2c_reg_index > 0x20)
1571                                         return false;
1572                         }
1573                 }
1574         }
1575
1576         return result;
1577 }
1578
1579 static bool i2c_write(struct pipe_ctx *pipe_ctx,
1580                 uint8_t address, uint8_t *buffer, uint32_t length)
1581 {
1582         struct i2c_command cmd = {0};
1583         struct i2c_payload payload = {0};
1584
1585         memset(&payload, 0, sizeof(payload));
1586         memset(&cmd, 0, sizeof(cmd));
1587
1588         cmd.number_of_payloads = 1;
1589         cmd.engine = I2C_COMMAND_ENGINE_DEFAULT;
1590         cmd.speed = pipe_ctx->stream->ctx->dc->caps.i2c_speed_in_khz;
1591
1592         payload.address = address;
1593         payload.data = buffer;
1594         payload.length = length;
1595         payload.write = true;
1596         cmd.payloads = &payload;
1597
1598         if (dm_helpers_submit_i2c(pipe_ctx->stream->ctx,
1599                         pipe_ctx->stream->link, &cmd))
1600                 return true;
1601
1602         return false;
1603 }
1604
1605 static void write_i2c_retimer_setting(
1606                 struct pipe_ctx *pipe_ctx,
1607                 bool is_vga_mode,
1608                 bool is_over_340mhz,
1609                 struct ext_hdmi_settings *settings)
1610 {
1611         uint8_t slave_address = (settings->slv_addr >> 1);
1612         uint8_t buffer[2];
1613         const uint8_t apply_rx_tx_change = 0x4;
1614         uint8_t offset = 0xA;
1615         uint8_t value = 0;
1616         int i = 0;
1617         bool i2c_success = false;
1618         DC_LOGGER_INIT(pipe_ctx->stream->ctx->logger);
1619
1620         memset(&buffer, 0, sizeof(buffer));
1621
1622         /* Start Ext-Hdmi programming*/
1623
1624         for (i = 0; i < settings->reg_num; i++) {
1625                 /* Apply 3G settings */
1626                 if (settings->reg_settings[i].i2c_reg_index <= 0x20) {
1627
1628                         buffer[0] = settings->reg_settings[i].i2c_reg_index;
1629                         buffer[1] = settings->reg_settings[i].i2c_reg_val;
1630                         i2c_success = i2c_write(pipe_ctx, slave_address,
1631                                                 buffer, sizeof(buffer));
1632                         RETIMER_REDRIVER_INFO("retimer write to slave_address = 0x%x,\
1633                                 offset = 0x%x, reg_val= 0x%x, i2c_success = %d\n",
1634                                 slave_address, buffer[0], buffer[1], i2c_success?1:0);
1635
1636                         if (!i2c_success)
1637                                 /* Write failure */
1638                                 ASSERT(i2c_success);
1639
1640                         /* Based on DP159 specs, APPLY_RX_TX_CHANGE bit in 0x0A
1641                          * needs to be set to 1 on every 0xA-0xC write.
1642                          */
1643                         if (settings->reg_settings[i].i2c_reg_index == 0xA ||
1644                                 settings->reg_settings[i].i2c_reg_index == 0xB ||
1645                                 settings->reg_settings[i].i2c_reg_index == 0xC) {
1646
1647                                 /* Query current value from offset 0xA */
1648                                 if (settings->reg_settings[i].i2c_reg_index == 0xA)
1649                                         value = settings->reg_settings[i].i2c_reg_val;
1650                                 else {
1651                                         i2c_success =
1652                                                 dal_ddc_service_query_ddc_data(
1653                                                 pipe_ctx->stream->link->ddc,
1654                                                 slave_address, &offset, 1, &value, 1);
1655                                         if (!i2c_success)
1656                                                 /* Write failure */
1657                                                 ASSERT(i2c_success);
1658                                 }
1659
1660                                 buffer[0] = offset;
1661                                 /* Set APPLY_RX_TX_CHANGE bit to 1 */
1662                                 buffer[1] = value | apply_rx_tx_change;
1663                                 i2c_success = i2c_write(pipe_ctx, slave_address,
1664                                                 buffer, sizeof(buffer));
1665                                 RETIMER_REDRIVER_INFO("retimer write to slave_address = 0x%x,\
1666                                         offset = 0x%x, reg_val = 0x%x, i2c_success = %d\n",
1667                                         slave_address, buffer[0], buffer[1], i2c_success?1:0);
1668                                 if (!i2c_success)
1669                                         /* Write failure */
1670                                         ASSERT(i2c_success);
1671                         }
1672                 }
1673         }
1674
1675         /* Apply 3G settings */
1676         if (is_over_340mhz) {
1677                 for (i = 0; i < settings->reg_num_6g; i++) {
1678                         /* Apply 3G settings */
1679                         if (settings->reg_settings[i].i2c_reg_index <= 0x20) {
1680
1681                                 buffer[0] = settings->reg_settings_6g[i].i2c_reg_index;
1682                                 buffer[1] = settings->reg_settings_6g[i].i2c_reg_val;
1683                                 i2c_success = i2c_write(pipe_ctx, slave_address,
1684                                                         buffer, sizeof(buffer));
1685                                 RETIMER_REDRIVER_INFO("above 340Mhz: retimer write to slave_address = 0x%x,\
1686                                         offset = 0x%x, reg_val = 0x%x, i2c_success = %d\n",
1687                                         slave_address, buffer[0], buffer[1], i2c_success?1:0);
1688
1689                                 if (!i2c_success)
1690                                         /* Write failure */
1691                                         ASSERT(i2c_success);
1692
1693                                 /* Based on DP159 specs, APPLY_RX_TX_CHANGE bit in 0x0A
1694                                  * needs to be set to 1 on every 0xA-0xC write.
1695                                  */
1696                                 if (settings->reg_settings_6g[i].i2c_reg_index == 0xA ||
1697                                         settings->reg_settings_6g[i].i2c_reg_index == 0xB ||
1698                                         settings->reg_settings_6g[i].i2c_reg_index == 0xC) {
1699
1700                                         /* Query current value from offset 0xA */
1701                                         if (settings->reg_settings_6g[i].i2c_reg_index == 0xA)
1702                                                 value = settings->reg_settings_6g[i].i2c_reg_val;
1703                                         else {
1704                                                 i2c_success =
1705                                                                 dal_ddc_service_query_ddc_data(
1706                                                                 pipe_ctx->stream->link->ddc,
1707                                                                 slave_address, &offset, 1, &value, 1);
1708                                                 if (!i2c_success)
1709                                                         /* Write failure */
1710                                                         ASSERT(i2c_success);
1711                                         }
1712
1713                                         buffer[0] = offset;
1714                                         /* Set APPLY_RX_TX_CHANGE bit to 1 */
1715                                         buffer[1] = value | apply_rx_tx_change;
1716                                         i2c_success = i2c_write(pipe_ctx, slave_address,
1717                                                         buffer, sizeof(buffer));
1718                                         RETIMER_REDRIVER_INFO("retimer write to slave_address = 0x%x,\
1719                                                 offset = 0x%x, reg_val = 0x%x, i2c_success = %d\n",
1720                                                 slave_address, buffer[0], buffer[1], i2c_success?1:0);
1721                                         if (!i2c_success)
1722                                                 /* Write failure */
1723                                                 ASSERT(i2c_success);
1724                                 }
1725                         }
1726                 }
1727         }
1728
1729         if (is_vga_mode) {
1730                 /* Program additional settings if using 640x480 resolution */
1731
1732                 /* Write offset 0xFF to 0x01 */
1733                 buffer[0] = 0xff;
1734                 buffer[1] = 0x01;
1735                 i2c_success = i2c_write(pipe_ctx, slave_address,
1736                                 buffer, sizeof(buffer));
1737                 RETIMER_REDRIVER_INFO("retimer write to slave_address = 0x%x,\
1738                                 offset = 0x%x, reg_val = 0x%x, i2c_success = %d\n",
1739                                 slave_address, buffer[0], buffer[1], i2c_success?1:0);
1740                 if (!i2c_success)
1741                         /* Write failure */
1742                         ASSERT(i2c_success);
1743
1744                 /* Write offset 0x00 to 0x23 */
1745                 buffer[0] = 0x00;
1746                 buffer[1] = 0x23;
1747                 i2c_success = i2c_write(pipe_ctx, slave_address,
1748                                 buffer, sizeof(buffer));
1749                 RETIMER_REDRIVER_INFO("retimer write to slave_address = 0x%x,\
1750                         offset = 0x%x, reg_val = 0x%x, i2c_success = %d\n",
1751                         slave_address, buffer[0], buffer[1], i2c_success?1:0);
1752                 if (!i2c_success)
1753                         /* Write failure */
1754                         ASSERT(i2c_success);
1755
1756                 /* Write offset 0xff to 0x00 */
1757                 buffer[0] = 0xff;
1758                 buffer[1] = 0x00;
1759                 i2c_success = i2c_write(pipe_ctx, slave_address,
1760                                 buffer, sizeof(buffer));
1761                 RETIMER_REDRIVER_INFO("retimer write to slave_address = 0x%x,\
1762                         offset = 0x%x, reg_val = 0x%x, i2c_success = %d\n",
1763                         slave_address, buffer[0], buffer[1], i2c_success?1:0);
1764                 if (!i2c_success)
1765                         /* Write failure */
1766                         ASSERT(i2c_success);
1767
1768         }
1769 }
1770
1771 static void write_i2c_default_retimer_setting(
1772                 struct pipe_ctx *pipe_ctx,
1773                 bool is_vga_mode,
1774                 bool is_over_340mhz)
1775 {
1776         uint8_t slave_address = (0xBA >> 1);
1777         uint8_t buffer[2];
1778         bool i2c_success = false;
1779         DC_LOGGER_INIT(pipe_ctx->stream->ctx->logger);
1780
1781         memset(&buffer, 0, sizeof(buffer));
1782
1783         /* Program Slave Address for tuning single integrity */
1784         /* Write offset 0x0A to 0x13 */
1785         buffer[0] = 0x0A;
1786         buffer[1] = 0x13;
1787         i2c_success = i2c_write(pipe_ctx, slave_address,
1788                         buffer, sizeof(buffer));
1789         RETIMER_REDRIVER_INFO("retimer writes default setting to slave_address = 0x%x,\
1790                 offset = 0x%x, reg_val = 0x%x, i2c_success = %d\n",
1791                 slave_address, buffer[0], buffer[1], i2c_success?1:0);
1792         if (!i2c_success)
1793                 /* Write failure */
1794                 ASSERT(i2c_success);
1795
1796         /* Write offset 0x0A to 0x17 */
1797         buffer[0] = 0x0A;
1798         buffer[1] = 0x17;
1799         i2c_success = i2c_write(pipe_ctx, slave_address,
1800                         buffer, sizeof(buffer));
1801         RETIMER_REDRIVER_INFO("retimer write to slave_addr = 0x%x,\
1802                 offset = 0x%x, reg_val = 0x%x, i2c_success = %d\n",
1803                 slave_address, buffer[0], buffer[1], i2c_success?1:0);
1804         if (!i2c_success)
1805                 /* Write failure */
1806                 ASSERT(i2c_success);
1807
1808         /* Write offset 0x0B to 0xDA or 0xD8 */
1809         buffer[0] = 0x0B;
1810         buffer[1] = is_over_340mhz ? 0xDA : 0xD8;
1811         i2c_success = i2c_write(pipe_ctx, slave_address,
1812                         buffer, sizeof(buffer));
1813         RETIMER_REDRIVER_INFO("retimer write to slave_addr = 0x%x,\
1814                 offset = 0x%x, reg_val = 0x%x, i2c_success = %d\n",
1815                 slave_address, buffer[0], buffer[1], i2c_success?1:0);
1816         if (!i2c_success)
1817                 /* Write failure */
1818                 ASSERT(i2c_success);
1819
1820         /* Write offset 0x0A to 0x17 */
1821         buffer[0] = 0x0A;
1822         buffer[1] = 0x17;
1823         i2c_success = i2c_write(pipe_ctx, slave_address,
1824                         buffer, sizeof(buffer));
1825         RETIMER_REDRIVER_INFO("retimer write to slave_addr = 0x%x,\
1826                 offset = 0x%x, reg_val= 0x%x, i2c_success = %d\n",
1827                 slave_address, buffer[0], buffer[1], i2c_success?1:0);
1828         if (!i2c_success)
1829                 /* Write failure */
1830                 ASSERT(i2c_success);
1831
1832         /* Write offset 0x0C to 0x1D or 0x91 */
1833         buffer[0] = 0x0C;
1834         buffer[1] = is_over_340mhz ? 0x1D : 0x91;
1835         i2c_success = i2c_write(pipe_ctx, slave_address,
1836                         buffer, sizeof(buffer));
1837         RETIMER_REDRIVER_INFO("retimer write to slave_addr = 0x%x,\
1838                 offset = 0x%x, reg_val = 0x%x, i2c_success = %d\n",
1839                 slave_address, buffer[0], buffer[1], i2c_success?1:0);
1840         if (!i2c_success)
1841                 /* Write failure */
1842                 ASSERT(i2c_success);
1843
1844         /* Write offset 0x0A to 0x17 */
1845         buffer[0] = 0x0A;
1846         buffer[1] = 0x17;
1847         i2c_success = i2c_write(pipe_ctx, slave_address,
1848                         buffer, sizeof(buffer));
1849         RETIMER_REDRIVER_INFO("retimer write to slave_addr = 0x%x,\
1850                 offset = 0x%x, reg_val = 0x%x, i2c_success = %d\n",
1851                 slave_address, buffer[0], buffer[1], i2c_success?1:0);
1852         if (!i2c_success)
1853                 /* Write failure */
1854                 ASSERT(i2c_success);
1855
1856
1857         if (is_vga_mode) {
1858                 /* Program additional settings if using 640x480 resolution */
1859
1860                 /* Write offset 0xFF to 0x01 */
1861                 buffer[0] = 0xff;
1862                 buffer[1] = 0x01;
1863                 i2c_success = i2c_write(pipe_ctx, slave_address,
1864                                 buffer, sizeof(buffer));
1865                 RETIMER_REDRIVER_INFO("retimer write to slave_addr = 0x%x,\
1866                         offset = 0x%x, reg_val = 0x%x, i2c_success = %d\n",
1867                         slave_address, buffer[0], buffer[1], i2c_success?1:0);
1868                 if (!i2c_success)
1869                         /* Write failure */
1870                         ASSERT(i2c_success);
1871
1872                 /* Write offset 0x00 to 0x23 */
1873                 buffer[0] = 0x00;
1874                 buffer[1] = 0x23;
1875                 i2c_success = i2c_write(pipe_ctx, slave_address,
1876                                 buffer, sizeof(buffer));
1877                 RETIMER_REDRIVER_INFO("retimer write to slave_addr = 0x%x,\
1878                         offset = 0x%x, reg_val= 0x%x, i2c_success = %d\n",
1879                         slave_address, buffer[0], buffer[1], i2c_success?1:0);
1880                 if (!i2c_success)
1881                         /* Write failure */
1882                         ASSERT(i2c_success);
1883
1884                 /* Write offset 0xff to 0x00 */
1885                 buffer[0] = 0xff;
1886                 buffer[1] = 0x00;
1887                 i2c_success = i2c_write(pipe_ctx, slave_address,
1888                                 buffer, sizeof(buffer));
1889                 RETIMER_REDRIVER_INFO("retimer write default setting to slave_addr = 0x%x,\
1890                         offset = 0x%x, reg_val= 0x%x, i2c_success = %d end here\n",
1891                         slave_address, buffer[0], buffer[1], i2c_success?1:0);
1892                 if (!i2c_success)
1893                         /* Write failure */
1894                         ASSERT(i2c_success);
1895         }
1896 }
1897
1898 static void write_i2c_redriver_setting(
1899                 struct pipe_ctx *pipe_ctx,
1900                 bool is_over_340mhz)
1901 {
1902         uint8_t slave_address = (0xF0 >> 1);
1903         uint8_t buffer[16];
1904         bool i2c_success = false;
1905         DC_LOGGER_INIT(pipe_ctx->stream->ctx->logger);
1906
1907         memset(&buffer, 0, sizeof(buffer));
1908
1909         // Program Slave Address for tuning single integrity
1910         buffer[3] = 0x4E;
1911         buffer[4] = 0x4E;
1912         buffer[5] = 0x4E;
1913         buffer[6] = is_over_340mhz ? 0x4E : 0x4A;
1914
1915         i2c_success = i2c_write(pipe_ctx, slave_address,
1916                                         buffer, sizeof(buffer));
1917         RETIMER_REDRIVER_INFO("redriver write 0 to all 16 reg offset expect following:\n\
1918                 \t slave_addr = 0x%x, offset[3] = 0x%x, offset[4] = 0x%x,\
1919                 offset[5] = 0x%x,offset[6] is_over_340mhz = 0x%x,\
1920                 i2c_success = %d\n",
1921                 slave_address, buffer[3], buffer[4], buffer[5], buffer[6], i2c_success?1:0);
1922
1923         if (!i2c_success)
1924                 /* Write failure */
1925                 ASSERT(i2c_success);
1926 }
1927
1928 static void enable_link_hdmi(struct pipe_ctx *pipe_ctx)
1929 {
1930         struct dc_stream_state *stream = pipe_ctx->stream;
1931         struct dc_link *link = stream->link;
1932         enum dc_color_depth display_color_depth;
1933         enum engine_id eng_id;
1934         struct ext_hdmi_settings settings = {0};
1935         bool is_over_340mhz = false;
1936         bool is_vga_mode = (stream->timing.h_addressable == 640)
1937                         && (stream->timing.v_addressable == 480);
1938
1939         if (stream->phy_pix_clk == 0)
1940                 stream->phy_pix_clk = stream->timing.pix_clk_100hz / 10;
1941         if (stream->phy_pix_clk > 340000)
1942                 is_over_340mhz = true;
1943
1944         if (dc_is_hdmi_signal(pipe_ctx->stream->signal)) {
1945                 unsigned short masked_chip_caps = pipe_ctx->stream->link->chip_caps &
1946                                 EXT_DISPLAY_PATH_CAPS__EXT_CHIP_MASK;
1947                 if (masked_chip_caps == EXT_DISPLAY_PATH_CAPS__HDMI20_TISN65DP159RSBT) {
1948                         /* DP159, Retimer settings */
1949                         eng_id = pipe_ctx->stream_res.stream_enc->id;
1950
1951                         if (get_ext_hdmi_settings(pipe_ctx, eng_id, &settings)) {
1952                                 write_i2c_retimer_setting(pipe_ctx,
1953                                                 is_vga_mode, is_over_340mhz, &settings);
1954                         } else {
1955                                 write_i2c_default_retimer_setting(pipe_ctx,
1956                                                 is_vga_mode, is_over_340mhz);
1957                         }
1958                 } else if (masked_chip_caps == EXT_DISPLAY_PATH_CAPS__HDMI20_PI3EQX1204) {
1959                         /* PI3EQX1204, Redriver settings */
1960                         write_i2c_redriver_setting(pipe_ctx, is_over_340mhz);
1961                 }
1962         }
1963
1964         if (dc_is_hdmi_signal(pipe_ctx->stream->signal))
1965                 dal_ddc_service_write_scdc_data(
1966                         stream->link->ddc,
1967                         stream->phy_pix_clk,
1968                         stream->timing.flags.LTE_340MCSC_SCRAMBLE);
1969
1970         memset(&stream->link->cur_link_settings, 0,
1971                         sizeof(struct dc_link_settings));
1972
1973         display_color_depth = stream->timing.display_color_depth;
1974         if (stream->timing.pixel_encoding == PIXEL_ENCODING_YCBCR422)
1975                 display_color_depth = COLOR_DEPTH_888;
1976
1977         link->link_enc->funcs->enable_tmds_output(
1978                         link->link_enc,
1979                         pipe_ctx->clock_source->id,
1980                         display_color_depth,
1981                         pipe_ctx->stream->signal,
1982                         stream->phy_pix_clk);
1983
1984         if (dc_is_hdmi_signal(pipe_ctx->stream->signal))
1985                 dal_ddc_service_read_scdc_data(link->ddc);
1986 }
1987
1988 static void enable_link_lvds(struct pipe_ctx *pipe_ctx)
1989 {
1990         struct dc_stream_state *stream = pipe_ctx->stream;
1991         struct dc_link *link = stream->link;
1992
1993         if (stream->phy_pix_clk == 0)
1994                 stream->phy_pix_clk = stream->timing.pix_clk_100hz / 10;
1995
1996         memset(&stream->link->cur_link_settings, 0,
1997                         sizeof(struct dc_link_settings));
1998
1999         link->link_enc->funcs->enable_lvds_output(
2000                         link->link_enc,
2001                         pipe_ctx->clock_source->id,
2002                         stream->phy_pix_clk);
2003
2004 }
2005
2006 /****************************enable_link***********************************/
2007 static enum dc_status enable_link(
2008                 struct dc_state *state,
2009                 struct pipe_ctx *pipe_ctx)
2010 {
2011         enum dc_status status = DC_ERROR_UNEXPECTED;
2012         switch (pipe_ctx->stream->signal) {
2013         case SIGNAL_TYPE_DISPLAY_PORT:
2014                 status = enable_link_dp(state, pipe_ctx);
2015                 break;
2016         case SIGNAL_TYPE_EDP:
2017                 status = enable_link_edp(state, pipe_ctx);
2018                 break;
2019         case SIGNAL_TYPE_DISPLAY_PORT_MST:
2020                 status = enable_link_dp_mst(state, pipe_ctx);
2021                 msleep(200);
2022                 break;
2023         case SIGNAL_TYPE_DVI_SINGLE_LINK:
2024         case SIGNAL_TYPE_DVI_DUAL_LINK:
2025         case SIGNAL_TYPE_HDMI_TYPE_A:
2026                 enable_link_hdmi(pipe_ctx);
2027                 status = DC_OK;
2028                 break;
2029         case SIGNAL_TYPE_LVDS:
2030                 enable_link_lvds(pipe_ctx);
2031                 status = DC_OK;
2032                 break;
2033         case SIGNAL_TYPE_VIRTUAL:
2034                 status = DC_OK;
2035                 break;
2036         default:
2037                 break;
2038         }
2039
2040         if (status == DC_OK)
2041                 pipe_ctx->stream->link->link_status.link_active = true;
2042
2043         return status;
2044 }
2045
2046 static void disable_link(struct dc_link *link, enum signal_type signal)
2047 {
2048         /*
2049          * TODO: implement call for dp_set_hw_test_pattern
2050          * it is needed for compliance testing
2051          */
2052
2053         /* here we need to specify that encoder output settings
2054          * need to be calculated as for the set mode,
2055          * it will lead to querying dynamic link capabilities
2056          * which should be done before enable output */
2057
2058         if (dc_is_dp_signal(signal)) {
2059                 /* SST DP, eDP */
2060                 if (dc_is_dp_sst_signal(signal))
2061                         dp_disable_link_phy(link, signal);
2062                 else
2063                         dp_disable_link_phy_mst(link, signal);
2064         } else
2065                 link->link_enc->funcs->disable_output(link->link_enc, signal);
2066
2067         if (signal == SIGNAL_TYPE_DISPLAY_PORT_MST) {
2068                 /* MST disable link only when no stream use the link */
2069                 if (link->mst_stream_alloc_table.stream_count <= 0)
2070                         link->link_status.link_active = false;
2071         } else {
2072                 link->link_status.link_active = false;
2073         }
2074 }
2075
2076 static uint32_t get_timing_pixel_clock_100hz(const struct dc_crtc_timing *timing)
2077 {
2078
2079         uint32_t pxl_clk = timing->pix_clk_100hz;
2080
2081         if (timing->pixel_encoding == PIXEL_ENCODING_YCBCR420)
2082                 pxl_clk /= 2;
2083         else if (timing->pixel_encoding == PIXEL_ENCODING_YCBCR422)
2084                 pxl_clk = pxl_clk * 2 / 3;
2085
2086         if (timing->display_color_depth == COLOR_DEPTH_101010)
2087                 pxl_clk = pxl_clk * 10 / 8;
2088         else if (timing->display_color_depth == COLOR_DEPTH_121212)
2089                 pxl_clk = pxl_clk * 12 / 8;
2090
2091         return pxl_clk;
2092 }
2093
2094 static bool dp_active_dongle_validate_timing(
2095                 const struct dc_crtc_timing *timing,
2096                 const struct dpcd_caps *dpcd_caps)
2097 {
2098         const struct dc_dongle_caps *dongle_caps = &dpcd_caps->dongle_caps;
2099
2100         switch (dpcd_caps->dongle_type) {
2101         case DISPLAY_DONGLE_DP_VGA_CONVERTER:
2102         case DISPLAY_DONGLE_DP_DVI_CONVERTER:
2103         case DISPLAY_DONGLE_DP_DVI_DONGLE:
2104                 if (timing->pixel_encoding == PIXEL_ENCODING_RGB)
2105                         return true;
2106                 else
2107                         return false;
2108         default:
2109                 break;
2110         }
2111
2112         if (dongle_caps->dongle_type != DISPLAY_DONGLE_DP_HDMI_CONVERTER ||
2113                 dongle_caps->extendedCapValid == false)
2114                 return true;
2115
2116         /* Check Pixel Encoding */
2117         switch (timing->pixel_encoding) {
2118         case PIXEL_ENCODING_RGB:
2119         case PIXEL_ENCODING_YCBCR444:
2120                 break;
2121         case PIXEL_ENCODING_YCBCR422:
2122                 if (!dongle_caps->is_dp_hdmi_ycbcr422_pass_through)
2123                         return false;
2124                 break;
2125         case PIXEL_ENCODING_YCBCR420:
2126                 if (!dongle_caps->is_dp_hdmi_ycbcr420_pass_through)
2127                         return false;
2128                 break;
2129         default:
2130                 /* Invalid Pixel Encoding*/
2131                 return false;
2132         }
2133
2134         switch (timing->display_color_depth) {
2135         case COLOR_DEPTH_666:
2136         case COLOR_DEPTH_888:
2137                 /*888 and 666 should always be supported*/
2138                 break;
2139         case COLOR_DEPTH_101010:
2140                 if (dongle_caps->dp_hdmi_max_bpc < 10)
2141                         return false;
2142                 break;
2143         case COLOR_DEPTH_121212:
2144                 if (dongle_caps->dp_hdmi_max_bpc < 12)
2145                         return false;
2146                 break;
2147         case COLOR_DEPTH_141414:
2148         case COLOR_DEPTH_161616:
2149         default:
2150                 /* These color depths are currently not supported */
2151                 return false;
2152         }
2153
2154         if (get_timing_pixel_clock_100hz(timing) > (dongle_caps->dp_hdmi_max_pixel_clk * 10))
2155                 return false;
2156
2157         return true;
2158 }
2159
2160 enum dc_status dc_link_validate_mode_timing(
2161                 const struct dc_stream_state *stream,
2162                 struct dc_link *link,
2163                 const struct dc_crtc_timing *timing)
2164 {
2165         uint32_t max_pix_clk = stream->link->dongle_max_pix_clk * 10;
2166         struct dpcd_caps *dpcd_caps = &link->dpcd_caps;
2167
2168         /* A hack to avoid failing any modes for EDID override feature on
2169          * topology change such as lower quality cable for DP or different dongle
2170          */
2171         if (link->remote_sinks[0])
2172                 return DC_OK;
2173
2174         /* Passive Dongle */
2175         if (max_pix_clk != 0 && get_timing_pixel_clock_100hz(timing) > max_pix_clk)
2176                 return DC_EXCEED_DONGLE_CAP;
2177
2178         /* Active Dongle*/
2179         if (!dp_active_dongle_validate_timing(timing, dpcd_caps))
2180                 return DC_EXCEED_DONGLE_CAP;
2181
2182         switch (stream->signal) {
2183         case SIGNAL_TYPE_EDP:
2184         case SIGNAL_TYPE_DISPLAY_PORT:
2185                 if (!dp_validate_mode_timing(
2186                                 link,
2187                                 timing))
2188                         return DC_NO_DP_LINK_BANDWIDTH;
2189                 break;
2190
2191         default:
2192                 break;
2193         }
2194
2195         return DC_OK;
2196 }
2197
2198 int dc_link_get_backlight_level(const struct dc_link *link)
2199 {
2200         struct abm *abm = link->ctx->dc->res_pool->abm;
2201
2202         if (abm == NULL || abm->funcs->get_current_backlight == NULL)
2203                 return DC_ERROR_UNEXPECTED;
2204
2205         return (int) abm->funcs->get_current_backlight(abm);
2206 }
2207
2208 bool dc_link_set_backlight_level(const struct dc_link *link,
2209                 uint32_t backlight_pwm_u16_16,
2210                 uint32_t frame_ramp)
2211 {
2212         struct dc  *core_dc = link->ctx->dc;
2213         struct abm *abm = core_dc->res_pool->abm;
2214         struct dmcu *dmcu = core_dc->res_pool->dmcu;
2215         unsigned int controller_id = 0;
2216         bool use_smooth_brightness = true;
2217         int i;
2218         DC_LOGGER_INIT(link->ctx->logger);
2219
2220         if ((dmcu == NULL) ||
2221                 (abm == NULL) ||
2222                 (abm->funcs->set_backlight_level_pwm == NULL))
2223                 return false;
2224
2225         use_smooth_brightness = dmcu->funcs->is_dmcu_initialized(dmcu);
2226
2227         DC_LOG_BACKLIGHT("New Backlight level: %d (0x%X)\n",
2228                         backlight_pwm_u16_16, backlight_pwm_u16_16);
2229
2230         if (dc_is_embedded_signal(link->connector_signal)) {
2231                 for (i = 0; i < MAX_PIPES; i++) {
2232                         if (core_dc->current_state->res_ctx.pipe_ctx[i].stream) {
2233                                 if (core_dc->current_state->res_ctx.
2234                                                 pipe_ctx[i].stream->link
2235                                                 == link)
2236                                         /* DMCU -1 for all controller id values,
2237                                          * therefore +1 here
2238                                          */
2239                                         controller_id =
2240                                                 core_dc->current_state->
2241                                                 res_ctx.pipe_ctx[i].stream_res.tg->inst +
2242                                                 1;
2243                         }
2244                 }
2245                 abm->funcs->set_backlight_level_pwm(
2246                                 abm,
2247                                 backlight_pwm_u16_16,
2248                                 frame_ramp,
2249                                 controller_id,
2250                                 use_smooth_brightness);
2251         }
2252
2253         return true;
2254 }
2255
2256 bool dc_link_set_abm_disable(const struct dc_link *link)
2257 {
2258         struct dc  *core_dc = link->ctx->dc;
2259         struct abm *abm = core_dc->res_pool->abm;
2260
2261         if ((abm == NULL) || (abm->funcs->set_backlight_level_pwm == NULL))
2262                 return false;
2263
2264         abm->funcs->set_abm_immediate_disable(abm);
2265
2266         return true;
2267 }
2268
2269 bool dc_link_set_psr_enable(const struct dc_link *link, bool enable, bool wait)
2270 {
2271         struct dc  *core_dc = link->ctx->dc;
2272         struct dmcu *dmcu = core_dc->res_pool->dmcu;
2273
2274         if ((dmcu != NULL && dmcu->funcs->is_dmcu_initialized(dmcu)) && link->psr_enabled)
2275                 dmcu->funcs->set_psr_enable(dmcu, enable, wait);
2276
2277         return true;
2278 }
2279
2280 const struct dc_link_status *dc_link_get_status(const struct dc_link *link)
2281 {
2282         return &link->link_status;
2283 }
2284
2285 void core_link_resume(struct dc_link *link)
2286 {
2287         if (link->connector_signal != SIGNAL_TYPE_VIRTUAL)
2288                 program_hpd_filter(link);
2289 }
2290
2291 static struct fixed31_32 get_pbn_per_slot(struct dc_stream_state *stream)
2292 {
2293         struct dc_link_settings *link_settings =
2294                         &stream->link->cur_link_settings;
2295         uint32_t link_rate_in_mbps =
2296                         link_settings->link_rate * LINK_RATE_REF_FREQ_IN_MHZ;
2297         struct fixed31_32 mbps = dc_fixpt_from_int(
2298                         link_rate_in_mbps * link_settings->lane_count);
2299
2300         return dc_fixpt_div_int(mbps, 54);
2301 }
2302
2303 static int get_color_depth(enum dc_color_depth color_depth)
2304 {
2305         switch (color_depth) {
2306         case COLOR_DEPTH_666: return 6;
2307         case COLOR_DEPTH_888: return 8;
2308         case COLOR_DEPTH_101010: return 10;
2309         case COLOR_DEPTH_121212: return 12;
2310         case COLOR_DEPTH_141414: return 14;
2311         case COLOR_DEPTH_161616: return 16;
2312         default: return 0;
2313         }
2314 }
2315
2316 static struct fixed31_32 get_pbn_from_timing(struct pipe_ctx *pipe_ctx)
2317 {
2318         uint32_t bpc;
2319         uint64_t kbps;
2320         struct fixed31_32 peak_kbps;
2321         uint32_t numerator;
2322         uint32_t denominator;
2323
2324         bpc = get_color_depth(pipe_ctx->stream_res.pix_clk_params.color_depth);
2325         kbps = pipe_ctx->stream_res.pix_clk_params.requested_pix_clk_100hz / 10 * bpc * 3;
2326
2327         /*
2328          * margin 5300ppm + 300ppm ~ 0.6% as per spec, factor is 1.006
2329          * The unit of 54/64Mbytes/sec is an arbitrary unit chosen based on
2330          * common multiplier to render an integer PBN for all link rate/lane
2331          * counts combinations
2332          * calculate
2333          * peak_kbps *= (1006/1000)
2334          * peak_kbps *= (64/54)
2335          * peak_kbps *= 8    convert to bytes
2336          */
2337
2338         numerator = 64 * PEAK_FACTOR_X1000;
2339         denominator = 54 * 8 * 1000 * 1000;
2340         kbps *= numerator;
2341         peak_kbps = dc_fixpt_from_fraction(kbps, denominator);
2342
2343         return peak_kbps;
2344 }
2345
2346 static void update_mst_stream_alloc_table(
2347         struct dc_link *link,
2348         struct stream_encoder *stream_enc,
2349         const struct dp_mst_stream_allocation_table *proposed_table)
2350 {
2351         struct link_mst_stream_allocation work_table[MAX_CONTROLLER_NUM] = {
2352                         { 0 } };
2353         struct link_mst_stream_allocation *dc_alloc;
2354
2355         int i;
2356         int j;
2357
2358         /* if DRM proposed_table has more than one new payload */
2359         ASSERT(proposed_table->stream_count -
2360                         link->mst_stream_alloc_table.stream_count < 2);
2361
2362         /* copy proposed_table to link, add stream encoder */
2363         for (i = 0; i < proposed_table->stream_count; i++) {
2364
2365                 for (j = 0; j < link->mst_stream_alloc_table.stream_count; j++) {
2366                         dc_alloc =
2367                         &link->mst_stream_alloc_table.stream_allocations[j];
2368
2369                         if (dc_alloc->vcp_id ==
2370                                 proposed_table->stream_allocations[i].vcp_id) {
2371
2372                                 work_table[i] = *dc_alloc;
2373                                 break; /* exit j loop */
2374                         }
2375                 }
2376
2377                 /* new vcp_id */
2378                 if (j == link->mst_stream_alloc_table.stream_count) {
2379                         work_table[i].vcp_id =
2380                                 proposed_table->stream_allocations[i].vcp_id;
2381                         work_table[i].slot_count =
2382                                 proposed_table->stream_allocations[i].slot_count;
2383                         work_table[i].stream_enc = stream_enc;
2384                 }
2385         }
2386
2387         /* update link->mst_stream_alloc_table with work_table */
2388         link->mst_stream_alloc_table.stream_count =
2389                         proposed_table->stream_count;
2390         for (i = 0; i < MAX_CONTROLLER_NUM; i++)
2391                 link->mst_stream_alloc_table.stream_allocations[i] =
2392                                 work_table[i];
2393 }
2394
2395 /* convert link_mst_stream_alloc_table to dm dp_mst_stream_alloc_table
2396  * because stream_encoder is not exposed to dm
2397  */
2398 static enum dc_status allocate_mst_payload(struct pipe_ctx *pipe_ctx)
2399 {
2400         struct dc_stream_state *stream = pipe_ctx->stream;
2401         struct dc_link *link = stream->link;
2402         struct link_encoder *link_encoder = link->link_enc;
2403         struct stream_encoder *stream_encoder = pipe_ctx->stream_res.stream_enc;
2404         struct dp_mst_stream_allocation_table proposed_table = {0};
2405         struct fixed31_32 avg_time_slots_per_mtp;
2406         struct fixed31_32 pbn;
2407         struct fixed31_32 pbn_per_slot;
2408         uint8_t i;
2409         DC_LOGGER_INIT(link->ctx->logger);
2410
2411         /* enable_link_dp_mst already check link->enabled_stream_count
2412          * and stream is in link->stream[]. This is called during set mode,
2413          * stream_enc is available.
2414          */
2415
2416         /* get calculate VC payload for stream: stream_alloc */
2417         if (dm_helpers_dp_mst_write_payload_allocation_table(
2418                 stream->ctx,
2419                 stream,
2420                 &proposed_table,
2421                 true)) {
2422                 update_mst_stream_alloc_table(
2423                                         link, pipe_ctx->stream_res.stream_enc, &proposed_table);
2424         }
2425         else
2426                 DC_LOG_WARNING("Failed to update"
2427                                 "MST allocation table for"
2428                                 "pipe idx:%d\n",
2429                                 pipe_ctx->pipe_idx);
2430
2431         DC_LOG_MST("%s  "
2432                         "stream_count: %d: \n ",
2433                         __func__,
2434                         link->mst_stream_alloc_table.stream_count);
2435
2436         for (i = 0; i < MAX_CONTROLLER_NUM; i++) {
2437                 DC_LOG_MST("stream_enc[%d]: %p      "
2438                 "stream[%d].vcp_id: %d      "
2439                 "stream[%d].slot_count: %d\n",
2440                 i,
2441                 (void *) link->mst_stream_alloc_table.stream_allocations[i].stream_enc,
2442                 i,
2443                 link->mst_stream_alloc_table.stream_allocations[i].vcp_id,
2444                 i,
2445                 link->mst_stream_alloc_table.stream_allocations[i].slot_count);
2446         }
2447
2448         ASSERT(proposed_table.stream_count > 0);
2449
2450         /* program DP source TX for payload */
2451         link_encoder->funcs->update_mst_stream_allocation_table(
2452                 link_encoder,
2453                 &link->mst_stream_alloc_table);
2454
2455         /* send down message */
2456         dm_helpers_dp_mst_poll_for_allocation_change_trigger(
2457                         stream->ctx,
2458                         stream);
2459
2460         dm_helpers_dp_mst_send_payload_allocation(
2461                         stream->ctx,
2462                         stream,
2463                         true);
2464
2465         /* slot X.Y for only current stream */
2466         pbn_per_slot = get_pbn_per_slot(stream);
2467         pbn = get_pbn_from_timing(pipe_ctx);
2468         avg_time_slots_per_mtp = dc_fixpt_div(pbn, pbn_per_slot);
2469
2470         stream_encoder->funcs->set_mst_bandwidth(
2471                 stream_encoder,
2472                 avg_time_slots_per_mtp);
2473
2474         return DC_OK;
2475
2476 }
2477
2478 static enum dc_status deallocate_mst_payload(struct pipe_ctx *pipe_ctx)
2479 {
2480         struct dc_stream_state *stream = pipe_ctx->stream;
2481         struct dc_link *link = stream->link;
2482         struct link_encoder *link_encoder = link->link_enc;
2483         struct stream_encoder *stream_encoder = pipe_ctx->stream_res.stream_enc;
2484         struct dp_mst_stream_allocation_table proposed_table = {0};
2485         struct fixed31_32 avg_time_slots_per_mtp = dc_fixpt_from_int(0);
2486         uint8_t i;
2487         bool mst_mode = (link->type == dc_connection_mst_branch);
2488         DC_LOGGER_INIT(link->ctx->logger);
2489
2490         /* deallocate_mst_payload is called before disable link. When mode or
2491          * disable/enable monitor, new stream is created which is not in link
2492          * stream[] yet. For this, payload is not allocated yet, so de-alloc
2493          * should not done. For new mode set, map_resources will get engine
2494          * for new stream, so stream_enc->id should be validated until here.
2495          */
2496
2497         /* slot X.Y */
2498         stream_encoder->funcs->set_mst_bandwidth(
2499                 stream_encoder,
2500                 avg_time_slots_per_mtp);
2501
2502         /* TODO: which component is responsible for remove payload table? */
2503         if (mst_mode) {
2504                 if (dm_helpers_dp_mst_write_payload_allocation_table(
2505                                 stream->ctx,
2506                                 stream,
2507                                 &proposed_table,
2508                                 false)) {
2509
2510                         update_mst_stream_alloc_table(
2511                                 link, pipe_ctx->stream_res.stream_enc, &proposed_table);
2512                 }
2513                 else {
2514                                 DC_LOG_WARNING("Failed to update"
2515                                                 "MST allocation table for"
2516                                                 "pipe idx:%d\n",
2517                                                 pipe_ctx->pipe_idx);
2518                 }
2519         }
2520
2521         DC_LOG_MST("%s"
2522                         "stream_count: %d: ",
2523                         __func__,
2524                         link->mst_stream_alloc_table.stream_count);
2525
2526         for (i = 0; i < MAX_CONTROLLER_NUM; i++) {
2527                 DC_LOG_MST("stream_enc[%d]: %p      "
2528                 "stream[%d].vcp_id: %d      "
2529                 "stream[%d].slot_count: %d\n",
2530                 i,
2531                 (void *) link->mst_stream_alloc_table.stream_allocations[i].stream_enc,
2532                 i,
2533                 link->mst_stream_alloc_table.stream_allocations[i].vcp_id,
2534                 i,
2535                 link->mst_stream_alloc_table.stream_allocations[i].slot_count);
2536         }
2537
2538         link_encoder->funcs->update_mst_stream_allocation_table(
2539                 link_encoder,
2540                 &link->mst_stream_alloc_table);
2541
2542         if (mst_mode) {
2543                 dm_helpers_dp_mst_poll_for_allocation_change_trigger(
2544                         stream->ctx,
2545                         stream);
2546
2547                 dm_helpers_dp_mst_send_payload_allocation(
2548                         stream->ctx,
2549                         stream,
2550                         false);
2551         }
2552
2553         return DC_OK;
2554 }
2555
2556 void core_link_enable_stream(
2557                 struct dc_state *state,
2558                 struct pipe_ctx *pipe_ctx)
2559 {
2560         struct dc *core_dc = pipe_ctx->stream->ctx->dc;
2561         struct dc_stream_state *stream = pipe_ctx->stream;
2562         enum dc_status status;
2563         DC_LOGGER_INIT(pipe_ctx->stream->ctx->logger);
2564
2565         if (pipe_ctx->stream->signal != SIGNAL_TYPE_VIRTUAL) {
2566                 stream->link->link_enc->funcs->setup(
2567                         stream->link->link_enc,
2568                         pipe_ctx->stream->signal);
2569                 pipe_ctx->stream_res.stream_enc->funcs->setup_stereo_sync(
2570                         pipe_ctx->stream_res.stream_enc,
2571                         pipe_ctx->stream_res.tg->inst,
2572                         stream->timing.timing_3d_format != TIMING_3D_FORMAT_NONE);
2573         }
2574
2575         if (dc_is_dp_signal(pipe_ctx->stream->signal))
2576                 pipe_ctx->stream_res.stream_enc->funcs->dp_set_stream_attribute(
2577                         pipe_ctx->stream_res.stream_enc,
2578                         &stream->timing,
2579                         stream->output_color_space);
2580
2581         if (dc_is_hdmi_tmds_signal(pipe_ctx->stream->signal))
2582                 pipe_ctx->stream_res.stream_enc->funcs->hdmi_set_stream_attribute(
2583                         pipe_ctx->stream_res.stream_enc,
2584                         &stream->timing,
2585                         stream->phy_pix_clk,
2586                         pipe_ctx->stream_res.audio != NULL);
2587
2588         if (dc_is_dvi_signal(pipe_ctx->stream->signal))
2589                 pipe_ctx->stream_res.stream_enc->funcs->dvi_set_stream_attribute(
2590                         pipe_ctx->stream_res.stream_enc,
2591                         &stream->timing,
2592                         (pipe_ctx->stream->signal == SIGNAL_TYPE_DVI_DUAL_LINK) ?
2593                         true : false);
2594
2595         if (dc_is_lvds_signal(pipe_ctx->stream->signal))
2596                 pipe_ctx->stream_res.stream_enc->funcs->lvds_set_stream_attribute(
2597                         pipe_ctx->stream_res.stream_enc,
2598                         &stream->timing);
2599
2600         if (!IS_FPGA_MAXIMUS_DC(core_dc->ctx->dce_environment)) {
2601                 bool apply_edp_fast_boot_optimization =
2602                         pipe_ctx->stream->apply_edp_fast_boot_optimization;
2603
2604                 pipe_ctx->stream->apply_edp_fast_boot_optimization = false;
2605
2606                 resource_build_info_frame(pipe_ctx);
2607                 core_dc->hwss.update_info_frame(pipe_ctx);
2608
2609                 /* Do not touch link on seamless boot optimization. */
2610                 if (pipe_ctx->stream->apply_seamless_boot_optimization) {
2611                         pipe_ctx->stream->dpms_off = false;
2612                         return;
2613                 }
2614
2615                 /* eDP lit up by bios already, no need to enable again. */
2616                 if (pipe_ctx->stream->signal == SIGNAL_TYPE_EDP &&
2617                                         apply_edp_fast_boot_optimization) {
2618                         pipe_ctx->stream->dpms_off = false;
2619                         return;
2620                 }
2621
2622                 if (pipe_ctx->stream->dpms_off)
2623                         return;
2624
2625                 status = enable_link(state, pipe_ctx);
2626
2627                 if (status != DC_OK) {
2628                         DC_LOG_WARNING("enabling link %u failed: %d\n",
2629                         pipe_ctx->stream->link->link_index,
2630                         status);
2631
2632                         /* Abort stream enable *unless* the failure was due to
2633                          * DP link training - some DP monitors will recover and
2634                          * show the stream anyway. But MST displays can't proceed
2635                          * without link training.
2636                          */
2637                         if (status != DC_FAIL_DP_LINK_TRAINING ||
2638                                         pipe_ctx->stream->signal == SIGNAL_TYPE_DISPLAY_PORT_MST) {
2639                                 BREAK_TO_DEBUGGER();
2640                                 return;
2641                         }
2642                 }
2643
2644                 core_dc->hwss.enable_audio_stream(pipe_ctx);
2645
2646                 /* turn off otg test pattern if enable */
2647                 if (pipe_ctx->stream_res.tg->funcs->set_test_pattern)
2648                         pipe_ctx->stream_res.tg->funcs->set_test_pattern(pipe_ctx->stream_res.tg,
2649                                         CONTROLLER_DP_TEST_PATTERN_VIDEOMODE,
2650                                         COLOR_DEPTH_UNDEFINED);
2651
2652                 core_dc->hwss.enable_stream(pipe_ctx);
2653
2654                 if (pipe_ctx->stream->signal == SIGNAL_TYPE_DISPLAY_PORT_MST)
2655                         allocate_mst_payload(pipe_ctx);
2656
2657                 core_dc->hwss.unblank_stream(pipe_ctx,
2658                         &pipe_ctx->stream->link->cur_link_settings);
2659
2660                 if (dc_is_dp_signal(pipe_ctx->stream->signal))
2661                         enable_stream_features(pipe_ctx);
2662         }
2663
2664 }
2665
2666 void core_link_disable_stream(struct pipe_ctx *pipe_ctx, int option)
2667 {
2668         struct dc  *core_dc = pipe_ctx->stream->ctx->dc;
2669
2670         core_dc->hwss.blank_stream(pipe_ctx);
2671
2672         if (pipe_ctx->stream->signal == SIGNAL_TYPE_DISPLAY_PORT_MST)
2673                 deallocate_mst_payload(pipe_ctx);
2674
2675         core_dc->hwss.disable_stream(pipe_ctx, option);
2676
2677         disable_link(pipe_ctx->stream->link, pipe_ctx->stream->signal);
2678 }
2679
2680 void core_link_set_avmute(struct pipe_ctx *pipe_ctx, bool enable)
2681 {
2682         struct dc  *core_dc = pipe_ctx->stream->ctx->dc;
2683
2684         if (pipe_ctx->stream->signal != SIGNAL_TYPE_HDMI_TYPE_A)
2685                 return;
2686
2687         core_dc->hwss.set_avmute(pipe_ctx, enable);
2688 }
2689
2690 /**
2691  *****************************************************************************
2692  *  Function: dc_link_enable_hpd_filter
2693  *
2694  *  @brief
2695  *     If enable is true, programs HPD filter on associated HPD line using
2696  *     delay_on_disconnect/delay_on_connect values dependent on
2697  *     link->connector_signal
2698  *
2699  *     If enable is false, programs HPD filter on associated HPD line with no
2700  *     delays on connect or disconnect
2701  *
2702  *  @param [in] link: pointer to the dc link
2703  *  @param [in] enable: boolean specifying whether to enable hbd
2704  *****************************************************************************
2705  */
2706 void dc_link_enable_hpd_filter(struct dc_link *link, bool enable)
2707 {
2708         struct gpio *hpd;
2709
2710         if (enable) {
2711                 link->is_hpd_filter_disabled = false;
2712                 program_hpd_filter(link);
2713         } else {
2714                 link->is_hpd_filter_disabled = true;
2715                 /* Obtain HPD handle */
2716                 hpd = get_hpd_gpio(link->ctx->dc_bios, link->link_id, link->ctx->gpio_service);
2717
2718                 if (!hpd)
2719                         return;
2720
2721                 /* Setup HPD filtering */
2722                 if (dal_gpio_open(hpd, GPIO_MODE_INTERRUPT) == GPIO_RESULT_OK) {
2723                         struct gpio_hpd_config config;
2724
2725                         config.delay_on_connect = 0;
2726                         config.delay_on_disconnect = 0;
2727
2728                         dal_irq_setup_hpd_filter(hpd, &config);
2729
2730                         dal_gpio_close(hpd);
2731                 } else {
2732                         ASSERT_CRITICAL(false);
2733                 }
2734                 /* Release HPD handle */
2735                 dal_gpio_destroy_irq(&hpd);
2736         }
2737 }
2738