drivers/gpu/drm/amd/display/dc/core/dc_link.c

   1 /*
   2  * Copyright 2012-15 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: AMD
  23  *
  24  */
  25
  26 #include "dm_services.h"
  27 #include "atom.h"
  28 #include "dm_helpers.h"
  29 #include "dc.h"
  30 #include "grph_object_id.h"
  31 #include "gpio_service_interface.h"
  32 #include "core_status.h"
  33 #include "dc_link_dp.h"
  34 #include "dc_link_ddc.h"
  35 #include "link_hwss.h"
  36
  37 #include "link_encoder.h"
  38 #include "hw_sequencer.h"
  39 #include "resource.h"
  40 #include "abm.h"
  41 #include "fixed31_32.h"
  42 #include "dpcd_defs.h"
  43 #include "dmcu.h"
  44
  45 #include "dce/dce_11_0_d.h"
  46 #include "dce/dce_11_0_enum.h"
  47 #include "dce/dce_11_0_sh_mask.h"
  48 #define DC_LOGGER \
  49         dc_ctx->logger
  50
  51 #define LINK_INFO(...) \
  52         DC_LOG_HW_HOTPLUG(  \
  53                 __VA_ARGS__)
  54
  55 /*******************************************************************************
  56  * Private structures
  57  ******************************************************************************/
  58
  59 enum {
  60         LINK_RATE_REF_FREQ_IN_MHZ = 27,
  61         PEAK_FACTOR_X1000 = 1006
  62 };
  63
  64 /*******************************************************************************
  65  * Private functions
  66  ******************************************************************************/
  67 static void destruct(struct dc_link *link)
  68 {
  69         int i;
  70
  71         if (link->ddc)
  72                 dal_ddc_service_destroy(&link->ddc);
  73
  74         if(link->link_enc)
  75                 link->link_enc->funcs->destroy(&link->link_enc);
  76
  77         if (link->local_sink)
  78                 dc_sink_release(link->local_sink);
  79
  80         for (i = 0; i < link->sink_count; ++i)
  81                 dc_sink_release(link->remote_sinks[i]);
  82 }
  83
  84 struct gpio *get_hpd_gpio(struct dc_bios *dcb,
  85                 struct graphics_object_id link_id,
  86                 struct gpio_service *gpio_service)
  87 {
  88         enum bp_result bp_result;
  89         struct graphics_object_hpd_info hpd_info;
  90         struct gpio_pin_info pin_info;
  91
  92         if (dcb->funcs->get_hpd_info(dcb, link_id, &hpd_info) != BP_RESULT_OK)
  93                 return NULL;
  94
  95         bp_result = dcb->funcs->get_gpio_pin_info(dcb,
  96                 hpd_info.hpd_int_gpio_uid, &pin_info);
  97
  98         if (bp_result != BP_RESULT_OK) {
  99                 ASSERT(bp_result == BP_RESULT_NORECORD);
 100                 return NULL;
 101         }
 102
 103         return dal_gpio_service_create_irq(
 104                 gpio_service,
 105                 pin_info.offset,
 106                 pin_info.mask);
 107 }
 108
 109 /*
 110  *  Function: program_hpd_filter
 111  *
 112  *  @brief
 113  *     Programs HPD filter on associated HPD line
 114  *
 115  *  @param [in] delay_on_connect_in_ms: Connect filter timeout
 116  *  @param [in] delay_on_disconnect_in_ms: Disconnect filter timeout
 117  *
 118  *  @return
 119  *     true on success, false otherwise
 120  */
 121 static bool program_hpd_filter(
 122         const struct dc_link *link)
 123 {
 124         bool result = false;
 125
 126         struct gpio *hpd;
 127
 128         int delay_on_connect_in_ms = 0;
 129         int delay_on_disconnect_in_ms = 0;
 130
 131         if (link->is_hpd_filter_disabled)
 132                 return false;
 133         /* Verify feature is supported */
 134         switch (link->connector_signal) {
 135         case SIGNAL_TYPE_DVI_SINGLE_LINK:
 136         case SIGNAL_TYPE_DVI_DUAL_LINK:
 137         case SIGNAL_TYPE_HDMI_TYPE_A:
 138                 /* Program hpd filter */
 139                 delay_on_connect_in_ms = 500;
 140                 delay_on_disconnect_in_ms = 100;
 141                 break;
 142         case SIGNAL_TYPE_DISPLAY_PORT:
 143         case SIGNAL_TYPE_DISPLAY_PORT_MST:
 144                 /* Program hpd filter to allow DP signal to settle */
 145                 /* 500: not able to detect MST <-> SST switch as HPD is low for
 146                  *      only 100ms on DELL U2413
 147                  * 0:   some passive dongle still show aux mode instead of i2c
 148                  * 20-50:not enough to hide bouncing HPD with passive dongle.
 149                  *      also see intermittent i2c read issues.
 150                  */
 151                 delay_on_connect_in_ms = 80;
 152                 delay_on_disconnect_in_ms = 0;
 153                 break;
 154         case SIGNAL_TYPE_LVDS:
 155         case SIGNAL_TYPE_EDP:
 156         default:
 157                 /* Don't program hpd filter */
 158                 return false;
 159         }
 160
 161         /* Obtain HPD handle */
 162         hpd = get_hpd_gpio(link->ctx->dc_bios, link->link_id, link->ctx->gpio_service);
 163
 164         if (!hpd)
 165                 return result;
 166
 167         /* Setup HPD filtering */
 168         if (dal_gpio_open(hpd, GPIO_MODE_INTERRUPT) == GPIO_RESULT_OK) {
 169                 struct gpio_hpd_config config;
 170
 171                 config.delay_on_connect = delay_on_connect_in_ms;
 172                 config.delay_on_disconnect = delay_on_disconnect_in_ms;
 173
 174                 dal_irq_setup_hpd_filter(hpd, &config);
 175
 176                 dal_gpio_close(hpd);
 177
 178                 result = true;
 179         } else {
 180                 ASSERT_CRITICAL(false);
 181         }
 182
 183         /* Release HPD handle */
 184         dal_gpio_destroy_irq(&hpd);
 185
 186         return result;
 187 }
 188
 189 static bool detect_sink(struct dc_link *link, enum dc_connection_type *type)
 190 {
 191         uint32_t is_hpd_high = 0;
 192         struct gpio *hpd_pin;
 193
 194         /* todo: may need to lock gpio access */
 195         hpd_pin = get_hpd_gpio(link->ctx->dc_bios, link->link_id, link->ctx->gpio_service);
 196         if (hpd_pin == NULL)
 197                 goto hpd_gpio_failure;
 198
 199         dal_gpio_open(hpd_pin, GPIO_MODE_INTERRUPT);
 200         dal_gpio_get_value(hpd_pin, &is_hpd_high);
 201         dal_gpio_close(hpd_pin);
 202         dal_gpio_destroy_irq(&hpd_pin);
 203
 204         if (is_hpd_high) {
 205                 *type = dc_connection_single;
 206                 /* TODO: need to do the actual detection */
 207         } else {
 208                 *type = dc_connection_none;
 209         }
 210
 211         return true;
 212
 213 hpd_gpio_failure:
 214         return false;
 215 }
 216
 217 static enum ddc_transaction_type get_ddc_transaction_type(
 218                 enum signal_type sink_signal)
 219 {
 220         enum ddc_transaction_type transaction_type = DDC_TRANSACTION_TYPE_NONE;
 221
 222         switch (sink_signal) {
 223         case SIGNAL_TYPE_DVI_SINGLE_LINK:
 224         case SIGNAL_TYPE_DVI_DUAL_LINK:
 225         case SIGNAL_TYPE_HDMI_TYPE_A:
 226         case SIGNAL_TYPE_LVDS:
 227         case SIGNAL_TYPE_RGB:
 228                 transaction_type = DDC_TRANSACTION_TYPE_I2C;
 229                 break;
 230
 231         case SIGNAL_TYPE_DISPLAY_PORT:
 232         case SIGNAL_TYPE_EDP:
 233                 transaction_type = DDC_TRANSACTION_TYPE_I2C_OVER_AUX;
 234                 break;
 235
 236         case SIGNAL_TYPE_DISPLAY_PORT_MST:
 237                 /* MST does not use I2COverAux, but there is the
 238                  * SPECIAL use case for "immediate dwnstrm device
 239                  * access" (EPR#370830). */
 240                 transaction_type = DDC_TRANSACTION_TYPE_I2C_OVER_AUX;
 241                 break;
 242
 243         default:
 244                 break;
 245         }
 246
 247         return transaction_type;
 248 }
 249
 250 static enum signal_type get_basic_signal_type(
 251         struct graphics_object_id encoder,
 252         struct graphics_object_id downstream)
 253 {
 254         if (downstream.type == OBJECT_TYPE_CONNECTOR) {
 255                 switch (downstream.id) {
 256                 case CONNECTOR_ID_SINGLE_LINK_DVII:
 257                         switch (encoder.id) {
 258                         case ENCODER_ID_INTERNAL_DAC1:
 259                         case ENCODER_ID_INTERNAL_KLDSCP_DAC1:
 260                         case ENCODER_ID_INTERNAL_DAC2:
 261                         case ENCODER_ID_INTERNAL_KLDSCP_DAC2:
 262                                 return SIGNAL_TYPE_RGB;
 263                         default:
 264                                 return SIGNAL_TYPE_DVI_SINGLE_LINK;
 265                         }
 266                 break;
 267                 case CONNECTOR_ID_DUAL_LINK_DVII:
 268                 {
 269                         switch (encoder.id) {
 270                         case ENCODER_ID_INTERNAL_DAC1:
 271                         case ENCODER_ID_INTERNAL_KLDSCP_DAC1:
 272                         case ENCODER_ID_INTERNAL_DAC2:
 273                         case ENCODER_ID_INTERNAL_KLDSCP_DAC2:
 274                                 return SIGNAL_TYPE_RGB;
 275                         default:
 276                                 return SIGNAL_TYPE_DVI_DUAL_LINK;
 277                         }
 278                 }
 279                 break;
 280                 case CONNECTOR_ID_SINGLE_LINK_DVID:
 281                         return SIGNAL_TYPE_DVI_SINGLE_LINK;
 282                 case CONNECTOR_ID_DUAL_LINK_DVID:
 283                         return SIGNAL_TYPE_DVI_DUAL_LINK;
 284                 case CONNECTOR_ID_VGA:
 285                         return SIGNAL_TYPE_RGB;
 286                 case CONNECTOR_ID_HDMI_TYPE_A:
 287                         return SIGNAL_TYPE_HDMI_TYPE_A;
 288                 case CONNECTOR_ID_LVDS:
 289                         return SIGNAL_TYPE_LVDS;
 290                 case CONNECTOR_ID_DISPLAY_PORT:
 291                         return SIGNAL_TYPE_DISPLAY_PORT;
 292                 case CONNECTOR_ID_EDP:
 293                         return SIGNAL_TYPE_EDP;
 294                 default:
 295                         return SIGNAL_TYPE_NONE;
 296                 }
 297         } else if (downstream.type == OBJECT_TYPE_ENCODER) {
 298                 switch (downstream.id) {
 299                 case ENCODER_ID_EXTERNAL_NUTMEG:
 300                 case ENCODER_ID_EXTERNAL_TRAVIS:
 301                         return SIGNAL_TYPE_DISPLAY_PORT;
 302                 default:
 303                         return SIGNAL_TYPE_NONE;
 304                 }
 305         }
 306
 307         return SIGNAL_TYPE_NONE;
 308 }
 309
 310 /*
 311  * @brief
 312  * Check whether there is a dongle on DP connector
 313  */
 314 static bool is_dp_sink_present(struct dc_link *link)
 315 {
 316         enum gpio_result gpio_result;
 317         uint32_t clock_pin = 0;
 318
 319         struct ddc *ddc;
 320
 321         enum connector_id connector_id =
 322                 dal_graphics_object_id_get_connector_id(link->link_id);
 323
 324         bool present =
 325                 ((connector_id == CONNECTOR_ID_DISPLAY_PORT) ||
 326                 (connector_id == CONNECTOR_ID_EDP));
 327
 328         ddc = dal_ddc_service_get_ddc_pin(link->ddc);
 329
 330         if (!ddc) {
 331                 BREAK_TO_DEBUGGER();
 332                 return present;
 333         }
 334
 335         /* Open GPIO and set it to I2C mode */
 336         /* Note: this GpioMode_Input will be converted
 337          * to GpioConfigType_I2cAuxDualMode in GPIO component,
 338          * which indicates we need additional delay */
 339
 340         if (GPIO_RESULT_OK != dal_ddc_open(
 341                 ddc, GPIO_MODE_INPUT, GPIO_DDC_CONFIG_TYPE_MODE_I2C)) {
 342                 dal_gpio_destroy_ddc(&ddc);
 343
 344                 return present;
 345         }
 346
 347         /* Read GPIO: DP sink is present if both clock and data pins are zero */
 348         /* [anaumov] in DAL2, there was no check for GPIO failure */
 349
 350         gpio_result = dal_gpio_get_value(ddc->pin_clock, &clock_pin);
 351         ASSERT(gpio_result == GPIO_RESULT_OK);
 352
 353         present = (gpio_result == GPIO_RESULT_OK) && !clock_pin;
 354
 355         dal_ddc_close(ddc);
 356
 357         return present;
 358 }
 359
 360 /*
 361  * @brief
 362  * Detect output sink type
 363  */
 364 static enum signal_type link_detect_sink(
 365         struct dc_link *link,
 366         enum dc_detect_reason reason)
 367 {
 368         enum signal_type result = get_basic_signal_type(
 369                 link->link_enc->id, link->link_id);
 370
 371         /* Internal digital encoder will detect only dongles
 372          * that require digital signal */
 373
 374         /* Detection mechanism is different
 375          * for different native connectors.
 376          * LVDS connector supports only LVDS signal;
 377          * PCIE is a bus slot, the actual connector needs to be detected first;
 378          * eDP connector supports only eDP signal;
 379          * HDMI should check straps for audio */
 380
 381         /* PCIE detects the actual connector on add-on board */
 382
 383         if (link->link_id.id == CONNECTOR_ID_PCIE) {
 384                 /* ZAZTODO implement PCIE add-on card detection */
 385         }
 386
 387         switch (link->link_id.id) {
 388         case CONNECTOR_ID_HDMI_TYPE_A: {
 389                 /* check audio support:
 390                  * if native HDMI is not supported, switch to DVI */
 391                 struct audio_support *aud_support = &link->dc->res_pool->audio_support;
 392
 393                 if (!aud_support->hdmi_audio_native)
 394                         if (link->link_id.id == CONNECTOR_ID_HDMI_TYPE_A)
 395                                 result = SIGNAL_TYPE_DVI_SINGLE_LINK;
 396         }
 397         break;
 398         case CONNECTOR_ID_DISPLAY_PORT: {
 399                 /* DP HPD short pulse. Passive DP dongle will not
 400                  * have short pulse
 401                  */
 402                 if (reason != DETECT_REASON_HPDRX) {
 403                         /* Check whether DP signal detected: if not -
 404                          * we assume signal is DVI; it could be corrected
 405                          * to HDMI after dongle detection
 406                          */
 407                         if (!is_dp_sink_present(link))
 408                                 result = SIGNAL_TYPE_DVI_SINGLE_LINK;
 409                 }
 410         }
 411         break;
 412         default:
 413         break;
 414         }
 415
 416         return result;
 417 }
 418
 419 static enum signal_type decide_signal_from_strap_and_dongle_type(
 420                 enum display_dongle_type dongle_type,
 421                 struct audio_support *audio_support)
 422 {
 423         enum signal_type signal = SIGNAL_TYPE_NONE;
 424
 425         switch (dongle_type) {
 426         case DISPLAY_DONGLE_DP_HDMI_DONGLE:
 427                 if (audio_support->hdmi_audio_on_dongle)
 428                         signal =  SIGNAL_TYPE_HDMI_TYPE_A;
 429                 else
 430                         signal = SIGNAL_TYPE_DVI_SINGLE_LINK;
 431                 break;
 432         case DISPLAY_DONGLE_DP_DVI_DONGLE:
 433                 signal = SIGNAL_TYPE_DVI_SINGLE_LINK;
 434                 break;
 435         case DISPLAY_DONGLE_DP_HDMI_MISMATCHED_DONGLE:
 436                 if (audio_support->hdmi_audio_native)
 437                         signal =  SIGNAL_TYPE_HDMI_TYPE_A;
 438                 else
 439                         signal = SIGNAL_TYPE_DVI_SINGLE_LINK;
 440                 break;
 441         default:
 442                 signal = SIGNAL_TYPE_NONE;
 443                 break;
 444         }
 445
 446         return signal;
 447 }
 448
 449 static enum signal_type dp_passive_dongle_detection(
 450                 struct ddc_service *ddc,
 451                 struct display_sink_capability *sink_cap,
 452                 struct audio_support *audio_support)
 453 {
 454         dal_ddc_service_i2c_query_dp_dual_mode_adaptor(
 455                                                 ddc, sink_cap);
 456         return decide_signal_from_strap_and_dongle_type(
 457                         sink_cap->dongle_type,
 458                         audio_support);
 459 }
 460
 461 static void link_disconnect_sink(struct dc_link *link)
 462 {
 463         if (link->local_sink) {
 464                 dc_sink_release(link->local_sink);
 465                 link->local_sink = NULL;
 466         }
 467
 468         link->dpcd_sink_count = 0;
 469 }
 470
 471 static bool detect_dp(
 472         struct dc_link *link,
 473         struct display_sink_capability *sink_caps,
 474         bool *converter_disable_audio,
 475         struct audio_support *audio_support,
 476         enum dc_detect_reason reason)
 477 {
 478         bool boot = false;
 479         sink_caps->signal = link_detect_sink(link, reason);
 480         sink_caps->transaction_type =
 481                 get_ddc_transaction_type(sink_caps->signal);
 482
 483         if (sink_caps->transaction_type == DDC_TRANSACTION_TYPE_I2C_OVER_AUX) {
 484                 sink_caps->signal = SIGNAL_TYPE_DISPLAY_PORT;
 485                 if (!detect_dp_sink_caps(link))
 486                         return false;
 487
 488                 if (is_mst_supported(link)) {
 489                         sink_caps->signal = SIGNAL_TYPE_DISPLAY_PORT_MST;
 490                         link->type = dc_connection_mst_branch;
 491
 492                         /*
 493                          * This call will initiate MST topology discovery. Which
 494                          * will detect MST ports and add new DRM connector DRM
 495                          * framework. Then read EDID via remote i2c over aux. In
 496                          * the end, will notify DRM detect result and save EDID
 497                          * into DRM framework.
 498                          *
 499                          * .detect is called by .fill_modes.
 500                          * .fill_modes is called by user mode ioctl
 501                          * DRM_IOCTL_MODE_GETCONNECTOR.
 502                          *
 503                          * .get_modes is called by .fill_modes.
 504                          *
 505                          * call .get_modes, AMDGPU DM implementation will create
 506                          * new dc_sink and add to dc_link. For long HPD plug
 507                          * in/out, MST has its own handle.
 508                          *
 509                          * Therefore, just after dc_create, link->sink is not
 510                          * created for MST until user mode app calls
 511                          * DRM_IOCTL_MODE_GETCONNECTOR.
 512                          *
 513                          * Need check ->sink usages in case ->sink = NULL
 514                          * TODO: s3 resume check
 515                          */
 516                         if (reason == DETECT_REASON_BOOT)
 517                                 boot = true;
 518
 519                         if (!dm_helpers_dp_mst_start_top_mgr(
 520                                 link->ctx,
 521                                 link, boot)) {
 522                                 /* MST not supported */
 523                                 link->type = dc_connection_single;
 524                                 sink_caps->signal = SIGNAL_TYPE_DISPLAY_PORT;
 525                         }
 526                 }
 527
 528                 if (link->type != dc_connection_mst_branch &&
 529                         is_dp_active_dongle(link)) {
 530                         /* DP active dongles */
 531                         link->type = dc_connection_active_dongle;
 532                         if (!link->dpcd_caps.sink_count.bits.SINK_COUNT) {
 533                                 /*
 534                                  * active dongle unplug processing for short irq
 535                                  */
 536                                 link_disconnect_sink(link);
 537                                 return true;
 538                         }
 539
 540                         if (link->dpcd_caps.dongle_type != DISPLAY_DONGLE_DP_HDMI_CONVERTER)
 541                                 *converter_disable_audio = true;
 542                 }
 543         } else {
 544                 /* DP passive dongles */
 545                 sink_caps->signal = dp_passive_dongle_detection(link->ddc,
 546                                 sink_caps,
 547                                 audio_support);
 548         }
 549
 550         return true;
 551 }
 552
 553 bool dc_link_detect(struct dc_link *link, enum dc_detect_reason reason)
 554 {
 555         struct dc_sink_init_data sink_init_data = { 0 };
 556         struct display_sink_capability sink_caps = { 0 };
 557         uint8_t i;
 558         bool converter_disable_audio = false;
 559         struct audio_support *aud_support = &link->dc->res_pool->audio_support;
 560         enum dc_edid_status edid_status;
 561         struct dc_context *dc_ctx = link->ctx;
 562         struct dc_sink *sink = NULL;
 563         enum dc_connection_type new_connection_type = dc_connection_none;
 564
 565         if (link->connector_signal == SIGNAL_TYPE_VIRTUAL)
 566                 return false;
 567
 568         if (false == detect_sink(link, &new_connection_type)) {
 569                 BREAK_TO_DEBUGGER();
 570                 return false;
 571         }
 572
 573         if (link->connector_signal == SIGNAL_TYPE_EDP &&
 574                         link->local_sink)
 575                 return true;
 576
 577         link_disconnect_sink(link);
 578
 579         if (new_connection_type != dc_connection_none) {
 580                 link->type = new_connection_type;
 581
 582                 /* From Disconnected-to-Connected. */
 583                 switch (link->connector_signal) {
 584                 case SIGNAL_TYPE_HDMI_TYPE_A: {
 585                         sink_caps.transaction_type = DDC_TRANSACTION_TYPE_I2C;
 586                         if (aud_support->hdmi_audio_native)
 587                                 sink_caps.signal = SIGNAL_TYPE_HDMI_TYPE_A;
 588                         else
 589                                 sink_caps.signal = SIGNAL_TYPE_DVI_SINGLE_LINK;
 590                         break;
 591                 }
 592
 593                 case SIGNAL_TYPE_DVI_SINGLE_LINK: {
 594                         sink_caps.transaction_type = DDC_TRANSACTION_TYPE_I2C;
 595                         sink_caps.signal = SIGNAL_TYPE_DVI_SINGLE_LINK;
 596                         break;
 597                 }
 598
 599                 case SIGNAL_TYPE_DVI_DUAL_LINK: {
 600                         sink_caps.transaction_type = DDC_TRANSACTION_TYPE_I2C;
 601                         sink_caps.signal = SIGNAL_TYPE_DVI_DUAL_LINK;
 602                         break;
 603                 }
 604
 605                 case SIGNAL_TYPE_EDP: {
 606                         detect_edp_sink_caps(link);
 607                         sink_caps.transaction_type =
 608                                 DDC_TRANSACTION_TYPE_I2C_OVER_AUX;
 609                         sink_caps.signal = SIGNAL_TYPE_EDP;
 610                         break;
 611                 }
 612
 613                 case SIGNAL_TYPE_DISPLAY_PORT: {
 614                         if (!detect_dp(
 615                                 link,
 616                                 &sink_caps,
 617                                 &converter_disable_audio,
 618                                 aud_support, reason))
 619                                 return false;
 620
 621                         /* Active dongle downstream unplug */
 622                         if (link->type == dc_connection_active_dongle
 623                                         && link->dpcd_caps.sink_count.
 624                                         bits.SINK_COUNT == 0)
 625                                 return true;
 626
 627                         if (link->type == dc_connection_mst_branch) {
 628                                 LINK_INFO("link=%d, mst branch is now Connected\n",
 629                                         link->link_index);
 630                                 /* Need to setup mst link_cap struct here
 631                                  * otherwise dc_link_detect() will leave mst link_cap
 632                                  * empty which leads to allocate_mst_payload() has "0"
 633                                  * pbn_per_slot value leading to exception on dal_fixed31_32_div()
 634                                  */
 635                                 link->verified_link_cap = link->reported_link_cap;
 636                                 return false;
 637                         }
 638
 639                         break;
 640                 }
 641
 642                 default:
 643                         DC_ERROR("Invalid connector type! signal:%d\n",
 644                                 link->connector_signal);
 645                         return false;
 646                 } /* switch() */
 647
 648                 if (link->dpcd_caps.sink_count.bits.SINK_COUNT)
 649                         link->dpcd_sink_count = link->dpcd_caps.sink_count.
 650                                         bits.SINK_COUNT;
 651                 else
 652                         link->dpcd_sink_count = 1;
 653
 654                 dal_ddc_service_set_transaction_type(
 655                                                 link->ddc,
 656                                                 sink_caps.transaction_type);
 657
 658                 link->aux_mode = dal_ddc_service_is_in_aux_transaction_mode(
 659                                 link->ddc);
 660
 661                 sink_init_data.link = link;
 662                 sink_init_data.sink_signal = sink_caps.signal;
 663
 664                 sink = dc_sink_create(&sink_init_data);
 665                 if (!sink) {
 666                         DC_ERROR("Failed to create sink!\n");
 667                         return false;
 668                 }
 669
 670                 sink->dongle_max_pix_clk = sink_caps.max_hdmi_pixel_clock;
 671                 sink->converter_disable_audio = converter_disable_audio;
 672
 673                 link->local_sink = sink;
 674
 675                 edid_status = dm_helpers_read_local_edid(
 676                                 link->ctx,
 677                                 link,
 678                                 sink);
 679
 680                 switch (edid_status) {
 681                 case EDID_BAD_CHECKSUM:
 682                         DC_LOG_ERROR("EDID checksum invalid.\n");
 683                         break;
 684                 case EDID_NO_RESPONSE:
 685                         DC_LOG_ERROR("No EDID read.\n");
 686                 default:
 687                         break;
 688                 }
 689
 690                 if (link->connector_signal == SIGNAL_TYPE_DISPLAY_PORT &&
 691                         sink_caps.transaction_type ==
 692                         DDC_TRANSACTION_TYPE_I2C_OVER_AUX) {
 693                         /*
 694                          * TODO debug why Dell 2413 doesn't like
 695                          *  two link trainings
 696                          */
 697
 698                         /* deal with non-mst cases */
 699                         dp_hbr_verify_link_cap(link, &link->reported_link_cap);
 700                 }
 701
 702                 /* HDMI-DVI Dongle */
 703                 if (sink->sink_signal == SIGNAL_TYPE_HDMI_TYPE_A &&
 704                                 !sink->edid_caps.edid_hdmi)
 705                         sink->sink_signal = SIGNAL_TYPE_DVI_SINGLE_LINK;
 706
 707                 /* Connectivity log: detection */
 708                 for (i = 0; i < sink->dc_edid.length / EDID_BLOCK_SIZE; i++) {
 709                         CONN_DATA_DETECT(link,
 710                                         &sink->dc_edid.raw_edid[i * EDID_BLOCK_SIZE],
 711                                         EDID_BLOCK_SIZE,
 712                                         "%s: [Block %d] ", sink->edid_caps.display_name, i);
 713                 }
 714
 715                 DC_LOG_DETECTION_EDID_PARSER("%s: "
 716                         "manufacturer_id = %X, "
 717                         "product_id = %X, "
 718                         "serial_number = %X, "
 719                         "manufacture_week = %d, "
 720                         "manufacture_year = %d, "
 721                         "display_name = %s, "
 722                         "speaker_flag = %d, "
 723                         "audio_mode_count = %d\n",
 724                         __func__,
 725                         sink->edid_caps.manufacturer_id,
 726                         sink->edid_caps.product_id,
 727                         sink->edid_caps.serial_number,
 728                         sink->edid_caps.manufacture_week,
 729                         sink->edid_caps.manufacture_year,
 730                         sink->edid_caps.display_name,
 731                         sink->edid_caps.speaker_flags,
 732                         sink->edid_caps.audio_mode_count);
 733
 734                 for (i = 0; i < sink->edid_caps.audio_mode_count; i++) {
 735                         DC_LOG_DETECTION_EDID_PARSER("%s: mode number = %d, "
 736                                 "format_code = %d, "
 737                                 "channel_count = %d, "
 738                                 "sample_rate = %d, "
 739                                 "sample_size = %d\n",
 740                                 __func__,
 741                                 i,
 742                                 sink->edid_caps.audio_modes[i].format_code,
 743                                 sink->edid_caps.audio_modes[i].channel_count,
 744                                 sink->edid_caps.audio_modes[i].sample_rate,
 745                                 sink->edid_caps.audio_modes[i].sample_size);
 746                 }
 747
 748         } else {
 749                 /* From Connected-to-Disconnected. */
 750                 if (link->type == dc_connection_mst_branch) {
 751                         LINK_INFO("link=%d, mst branch is now Disconnected\n",
 752                                 link->link_index);
 753
 754                         dm_helpers_dp_mst_stop_top_mgr(link->ctx, link);
 755
 756                         link->mst_stream_alloc_table.stream_count = 0;
 757                         memset(link->mst_stream_alloc_table.stream_allocations, 0, sizeof(link->mst_stream_alloc_table.stream_allocations));
 758                 }
 759
 760                 link->type = dc_connection_none;
 761                 sink_caps.signal = SIGNAL_TYPE_NONE;
 762         }
 763
 764         LINK_INFO("link=%d, dc_sink_in=%p is now %s\n",
 765                 link->link_index, sink,
 766                 (sink_caps.signal == SIGNAL_TYPE_NONE ?
 767                         "Disconnected":"Connected"));
 768
 769         return true;
 770 }
 771
 772 static enum hpd_source_id get_hpd_line(
 773                 struct dc_link *link)
 774 {
 775         struct gpio *hpd;
 776         enum hpd_source_id hpd_id = HPD_SOURCEID_UNKNOWN;
 777
 778         hpd = get_hpd_gpio(link->ctx->dc_bios, link->link_id, link->ctx->gpio_service);
 779
 780         if (hpd) {
 781                 switch (dal_irq_get_source(hpd)) {
 782                 case DC_IRQ_SOURCE_HPD1:
 783                         hpd_id = HPD_SOURCEID1;
 784                 break;
 785                 case DC_IRQ_SOURCE_HPD2:
 786                         hpd_id = HPD_SOURCEID2;
 787                 break;
 788                 case DC_IRQ_SOURCE_HPD3:
 789                         hpd_id = HPD_SOURCEID3;
 790                 break;
 791                 case DC_IRQ_SOURCE_HPD4:
 792                         hpd_id = HPD_SOURCEID4;
 793                 break;
 794                 case DC_IRQ_SOURCE_HPD5:
 795                         hpd_id = HPD_SOURCEID5;
 796                 break;
 797                 case DC_IRQ_SOURCE_HPD6:
 798                         hpd_id = HPD_SOURCEID6;
 799                 break;
 800                 default:
 801                         BREAK_TO_DEBUGGER();
 802                 break;
 803                 }
 804
 805                 dal_gpio_destroy_irq(&hpd);
 806         }
 807
 808         return hpd_id;
 809 }
 810
 811 static enum channel_id get_ddc_line(struct dc_link *link)
 812 {
 813         struct ddc *ddc;
 814         enum channel_id channel = CHANNEL_ID_UNKNOWN;
 815
 816         ddc = dal_ddc_service_get_ddc_pin(link->ddc);
 817
 818         if (ddc) {
 819                 switch (dal_ddc_get_line(ddc)) {
 820                 case GPIO_DDC_LINE_DDC1:
 821                         channel = CHANNEL_ID_DDC1;
 822                         break;
 823                 case GPIO_DDC_LINE_DDC2:
 824                         channel = CHANNEL_ID_DDC2;
 825                         break;
 826                 case GPIO_DDC_LINE_DDC3:
 827                         channel = CHANNEL_ID_DDC3;
 828                         break;
 829                 case GPIO_DDC_LINE_DDC4:
 830                         channel = CHANNEL_ID_DDC4;
 831                         break;
 832                 case GPIO_DDC_LINE_DDC5:
 833                         channel = CHANNEL_ID_DDC5;
 834                         break;
 835                 case GPIO_DDC_LINE_DDC6:
 836                         channel = CHANNEL_ID_DDC6;
 837                         break;
 838                 case GPIO_DDC_LINE_DDC_VGA:
 839                         channel = CHANNEL_ID_DDC_VGA;
 840                         break;
 841                 case GPIO_DDC_LINE_I2C_PAD:
 842                         channel = CHANNEL_ID_I2C_PAD;
 843                         break;
 844                 default:
 845                         BREAK_TO_DEBUGGER();
 846                         break;
 847                 }
 848         }
 849
 850         return channel;
 851 }
 852
 853 static enum transmitter translate_encoder_to_transmitter(
 854         struct graphics_object_id encoder)
 855 {
 856         switch (encoder.id) {
 857         case ENCODER_ID_INTERNAL_UNIPHY:
 858                 switch (encoder.enum_id) {
 859                 case ENUM_ID_1:
 860                         return TRANSMITTER_UNIPHY_A;
 861                 case ENUM_ID_2:
 862                         return TRANSMITTER_UNIPHY_B;
 863                 default:
 864                         return TRANSMITTER_UNKNOWN;
 865                 }
 866         break;
 867         case ENCODER_ID_INTERNAL_UNIPHY1:
 868                 switch (encoder.enum_id) {
 869                 case ENUM_ID_1:
 870                         return TRANSMITTER_UNIPHY_C;
 871                 case ENUM_ID_2:
 872                         return TRANSMITTER_UNIPHY_D;
 873                 default:
 874                         return TRANSMITTER_UNKNOWN;
 875                 }
 876         break;
 877         case ENCODER_ID_INTERNAL_UNIPHY2:
 878                 switch (encoder.enum_id) {
 879                 case ENUM_ID_1:
 880                         return TRANSMITTER_UNIPHY_E;
 881                 case ENUM_ID_2:
 882                         return TRANSMITTER_UNIPHY_F;
 883                 default:
 884                         return TRANSMITTER_UNKNOWN;
 885                 }
 886         break;
 887         case ENCODER_ID_INTERNAL_UNIPHY3:
 888                 switch (encoder.enum_id) {
 889                 case ENUM_ID_1:
 890                         return TRANSMITTER_UNIPHY_G;
 891                 default:
 892                         return TRANSMITTER_UNKNOWN;
 893                 }
 894         break;
 895         case ENCODER_ID_EXTERNAL_NUTMEG:
 896                 switch (encoder.enum_id) {
 897                 case ENUM_ID_1:
 898                         return TRANSMITTER_NUTMEG_CRT;
 899                 default:
 900                         return TRANSMITTER_UNKNOWN;
 901                 }
 902         break;
 903         case ENCODER_ID_EXTERNAL_TRAVIS:
 904                 switch (encoder.enum_id) {
 905                 case ENUM_ID_1:
 906                         return TRANSMITTER_TRAVIS_CRT;
 907                 case ENUM_ID_2:
 908                         return TRANSMITTER_TRAVIS_LCD;
 909                 default:
 910                         return TRANSMITTER_UNKNOWN;
 911                 }
 912         break;
 913         default:
 914                 return TRANSMITTER_UNKNOWN;
 915         }
 916 }
 917
 918 static bool construct(
 919         struct dc_link *link,
 920         const struct link_init_data *init_params)
 921 {
 922         uint8_t i;
 923         struct gpio *hpd_gpio = NULL;
 924         struct ddc_service_init_data ddc_service_init_data = { { 0 } };
 925         struct dc_context *dc_ctx = init_params->ctx;
 926         struct encoder_init_data enc_init_data = { 0 };
 927         struct integrated_info info = {{{ 0 }}};
 928         struct dc_bios *bios = init_params->dc->ctx->dc_bios;
 929         const struct dc_vbios_funcs *bp_funcs = bios->funcs;
 930
 931         link->irq_source_hpd = DC_IRQ_SOURCE_INVALID;
 932         link->irq_source_hpd_rx = DC_IRQ_SOURCE_INVALID;
 933
 934         link->link_status.dpcd_caps = &link->dpcd_caps;
 935
 936         link->dc = init_params->dc;
 937         link->ctx = dc_ctx;
 938         link->link_index = init_params->link_index;
 939
 940         link->link_id = bios->funcs->get_connector_id(bios, init_params->connector_index);
 941
 942         if (link->link_id.type != OBJECT_TYPE_CONNECTOR) {
 943                 dm_error("%s: Invalid Connector ObjectID from Adapter Service for connector index:%d! type %d expected %d\n",
 944                          __func__, init_params->connector_index,
 945                          link->link_id.type, OBJECT_TYPE_CONNECTOR);
 946                 goto create_fail;
 947         }
 948
 949         hpd_gpio = get_hpd_gpio(link->ctx->dc_bios, link->link_id, link->ctx->gpio_service);
 950
 951         if (hpd_gpio != NULL)
 952                 link->irq_source_hpd = dal_irq_get_source(hpd_gpio);
 953
 954         switch (link->link_id.id) {
 955         case CONNECTOR_ID_HDMI_TYPE_A:
 956                 link->connector_signal = SIGNAL_TYPE_HDMI_TYPE_A;
 957
 958                 break;
 959         case CONNECTOR_ID_SINGLE_LINK_DVID:
 960         case CONNECTOR_ID_SINGLE_LINK_DVII:
 961                 link->connector_signal = SIGNAL_TYPE_DVI_SINGLE_LINK;
 962                 break;
 963         case CONNECTOR_ID_DUAL_LINK_DVID:
 964         case CONNECTOR_ID_DUAL_LINK_DVII:
 965                 link->connector_signal = SIGNAL_TYPE_DVI_DUAL_LINK;
 966                 break;
 967         case CONNECTOR_ID_DISPLAY_PORT:
 968                 link->connector_signal =        SIGNAL_TYPE_DISPLAY_PORT;
 969
 970                 if (hpd_gpio != NULL)
 971                         link->irq_source_hpd_rx =
 972                                         dal_irq_get_rx_source(hpd_gpio);
 973
 974                 break;
 975         case CONNECTOR_ID_EDP:
 976                 link->connector_signal = SIGNAL_TYPE_EDP;
 977
 978                 if (hpd_gpio != NULL) {
 979                         link->irq_source_hpd = DC_IRQ_SOURCE_INVALID;
 980                         link->irq_source_hpd_rx =
 981                                         dal_irq_get_rx_source(hpd_gpio);
 982                 }
 983                 break;
 984         default:
 985                 DC_LOG_WARNING("Unsupported Connector type:%d!\n", link->link_id.id);
 986                 goto create_fail;
 987         }
 988
 989         if (hpd_gpio != NULL) {
 990                 dal_gpio_destroy_irq(&hpd_gpio);
 991                 hpd_gpio = NULL;
 992         }
 993
 994         /* TODO: #DAL3 Implement id to str function.*/
 995         LINK_INFO("Connector[%d] description:"
 996                         "signal %d\n",
 997                         init_params->connector_index,
 998                         link->connector_signal);
 999
1000         ddc_service_init_data.ctx = link->ctx;
1001         ddc_service_init_data.id = link->link_id;
1002         ddc_service_init_data.link = link;
1003         link->ddc = dal_ddc_service_create(&ddc_service_init_data);
1004
1005         if (link->ddc == NULL) {
1006                 DC_ERROR("Failed to create ddc_service!\n");
1007                 goto ddc_create_fail;
1008         }
1009
1010         link->ddc_hw_inst =
1011                 dal_ddc_get_line(
1012                         dal_ddc_service_get_ddc_pin(link->ddc));
1013
1014         enc_init_data.ctx = dc_ctx;
1015         bp_funcs->get_src_obj(dc_ctx->dc_bios, link->link_id, 0, &enc_init_data.encoder);
1016         enc_init_data.connector = link->link_id;
1017         enc_init_data.channel = get_ddc_line(link);
1018         enc_init_data.hpd_source = get_hpd_line(link);
1019
1020         link->hpd_src = enc_init_data.hpd_source;
1021
1022         enc_init_data.transmitter =
1023                         translate_encoder_to_transmitter(enc_init_data.encoder);
1024         link->link_enc = link->dc->res_pool->funcs->link_enc_create(
1025                                                                 &enc_init_data);
1026
1027         if( link->link_enc == NULL) {
1028                 DC_ERROR("Failed to create link encoder!\n");
1029                 goto link_enc_create_fail;
1030         }
1031
1032         link->link_enc_hw_inst = link->link_enc->transmitter;
1033
1034         for (i = 0; i < 4; i++) {
1035                 if (BP_RESULT_OK !=
1036                                 bp_funcs->get_device_tag(dc_ctx->dc_bios, link->link_id, i, &link->device_tag)) {
1037                         DC_ERROR("Failed to find device tag!\n");
1038                         goto device_tag_fail;
1039                 }
1040
1041                 /* Look for device tag that matches connector signal,
1042                  * CRT for rgb, LCD for other supported signal tyes
1043                  */
1044                 if (!bp_funcs->is_device_id_supported(dc_ctx->dc_bios, link->device_tag.dev_id))
1045                         continue;
1046                 if (link->device_tag.dev_id.device_type == DEVICE_TYPE_CRT
1047                         && link->connector_signal != SIGNAL_TYPE_RGB)
1048                         continue;
1049                 if (link->device_tag.dev_id.device_type == DEVICE_TYPE_LCD
1050                         && link->connector_signal == SIGNAL_TYPE_RGB)
1051                         continue;
1052                 break;
1053         }
1054
1055         if (bios->integrated_info)
1056                 info = *bios->integrated_info;
1057
1058         /* Look for channel mapping corresponding to connector and device tag */
1059         for (i = 0; i < MAX_NUMBER_OF_EXT_DISPLAY_PATH; i++) {
1060                 struct external_display_path *path =
1061                         &info.ext_disp_conn_info.path[i];
1062                 if (path->device_connector_id.enum_id == link->link_id.enum_id
1063                         && path->device_connector_id.id == link->link_id.id
1064                         && path->device_connector_id.type == link->link_id.type) {
1065
1066                         if (link->device_tag.acpi_device != 0
1067                                 && path->device_acpi_enum == link->device_tag.acpi_device) {
1068                                 link->ddi_channel_mapping = path->channel_mapping;
1069                                 link->chip_caps = path->caps;
1070                         } else if (path->device_tag ==
1071                                         link->device_tag.dev_id.raw_device_tag) {
1072                                 link->ddi_channel_mapping = path->channel_mapping;
1073                                 link->chip_caps = path->caps;
1074                         }
1075                         break;
1076                 }
1077         }
1078
1079         /*
1080          * TODO check if GPIO programmed correctly
1081          *
1082          * If GPIO isn't programmed correctly HPD might not rise or drain
1083          * fast enough, leading to bounces.
1084          */
1085         program_hpd_filter(link);
1086
1087         return true;
1088 device_tag_fail:
1089         link->link_enc->funcs->destroy(&link->link_enc);
1090 link_enc_create_fail:
1091         dal_ddc_service_destroy(&link->ddc);
1092 ddc_create_fail:
1093 create_fail:
1094
1095         if (hpd_gpio != NULL) {
1096                 dal_gpio_destroy_irq(&hpd_gpio);
1097         }
1098
1099         return false;
1100 }
1101
1102 /*******************************************************************************
1103  * Public functions
1104  ******************************************************************************/
1105 struct dc_link *link_create(const struct link_init_data *init_params)
1106 {
1107         struct dc_link *link =
1108                         kzalloc(sizeof(*link), GFP_KERNEL);
1109
1110         if (NULL == link)
1111                 goto alloc_fail;
1112
1113         if (false == construct(link, init_params))
1114                 goto construct_fail;
1115
1116         return link;
1117
1118 construct_fail:
1119         kfree(link);
1120
1121 alloc_fail:
1122         return NULL;
1123 }
1124
1125 void link_destroy(struct dc_link **link)
1126 {
1127         destruct(*link);
1128         kfree(*link);
1129         *link = NULL;
1130 }
1131
1132 static void dpcd_configure_panel_mode(
1133         struct dc_link *link,
1134         enum dp_panel_mode panel_mode)
1135 {
1136         union dpcd_edp_config edp_config_set;
1137         bool panel_mode_edp = false;
1138         struct dc_context *dc_ctx = link->ctx;
1139         memset(&edp_config_set, '\0', sizeof(union dpcd_edp_config));
1140
1141         if (DP_PANEL_MODE_DEFAULT != panel_mode) {
1142
1143                 switch (panel_mode) {
1144                 case DP_PANEL_MODE_EDP:
1145                 case DP_PANEL_MODE_SPECIAL:
1146                         panel_mode_edp = true;
1147                         break;
1148
1149                 default:
1150                         break;
1151                 }
1152
1153                 /*set edp panel mode in receiver*/
1154                 core_link_read_dpcd(
1155                         link,
1156                         DP_EDP_CONFIGURATION_SET,
1157                         &edp_config_set.raw,
1158                         sizeof(edp_config_set.raw));
1159
1160                 if (edp_config_set.bits.PANEL_MODE_EDP
1161                         != panel_mode_edp) {
1162                         enum ddc_result result = DDC_RESULT_UNKNOWN;
1163
1164                         edp_config_set.bits.PANEL_MODE_EDP =
1165                         panel_mode_edp;
1166                         result = core_link_write_dpcd(
1167                                 link,
1168                                 DP_EDP_CONFIGURATION_SET,
1169                                 &edp_config_set.raw,
1170                                 sizeof(edp_config_set.raw));
1171
1172                         ASSERT(result == DDC_RESULT_SUCESSFULL);
1173                 }
1174         }
1175         DC_LOG_DETECTION_DP_CAPS("Link: %d eDP panel mode supported: %d "
1176                         "eDP panel mode enabled: %d \n",
1177                         link->link_index,
1178                         link->dpcd_caps.panel_mode_edp,
1179                         panel_mode_edp);
1180 }
1181
1182 static void enable_stream_features(struct pipe_ctx *pipe_ctx)
1183 {
1184         struct dc_stream_state *stream = pipe_ctx->stream;
1185         struct dc_link *link = stream->sink->link;
1186         union down_spread_ctrl downspread;
1187
1188         core_link_read_dpcd(link, DP_DOWNSPREAD_CTRL,
1189                         &downspread.raw, sizeof(downspread));
1190
1191         downspread.bits.IGNORE_MSA_TIMING_PARAM =
1192                         (stream->ignore_msa_timing_param) ? 1 : 0;
1193
1194         core_link_write_dpcd(link, DP_DOWNSPREAD_CTRL,
1195                         &downspread.raw, sizeof(downspread));
1196 }
1197
1198 static enum dc_status enable_link_dp(
1199                 struct dc_state *state,
1200                 struct pipe_ctx *pipe_ctx)
1201 {
1202         struct dc_stream_state *stream = pipe_ctx->stream;
1203         enum dc_status status;
1204         bool skip_video_pattern;
1205         struct dc_link *link = stream->sink->link;
1206         struct dc_link_settings link_settings = {0};
1207         enum dp_panel_mode panel_mode;
1208         enum dc_link_rate max_link_rate = LINK_RATE_HIGH2;
1209
1210         /* get link settings for video mode timing */
1211         decide_link_settings(stream, &link_settings);
1212
1213         /* raise clock state for HBR3 if required. Confirmed with HW DCE/DPCS
1214          * logic for HBR3 still needs Nominal (0.8V) on VDDC rail
1215          */
1216         if (link->link_enc->features.flags.bits.IS_HBR3_CAPABLE)
1217                 max_link_rate = LINK_RATE_HIGH3;
1218
1219         if (link_settings.link_rate == max_link_rate) {
1220                 if (state->dis_clk->funcs->set_min_clocks_state) {
1221                         if (state->dis_clk->cur_min_clks_state < DM_PP_CLOCKS_STATE_NOMINAL)
1222                                 state->dis_clk->funcs->set_min_clocks_state(
1223                                         state->dis_clk, DM_PP_CLOCKS_STATE_NOMINAL);
1224                 } else {
1225                         uint32_t dp_phyclk_in_khz;
1226                         const struct clocks_value clocks_value =
1227                                         state->dis_clk->cur_clocks_value;
1228
1229                         /* 27mhz = 27000000hz= 27000khz */
1230                         dp_phyclk_in_khz = link_settings.link_rate * 27000;
1231
1232                         if (((clocks_value.max_non_dp_phyclk_in_khz != 0) &&
1233                                 (dp_phyclk_in_khz > clocks_value.max_non_dp_phyclk_in_khz)) ||
1234                                 (dp_phyclk_in_khz > clocks_value.max_dp_phyclk_in_khz)) {
1235                                 state->dis_clk->funcs->apply_clock_voltage_request(
1236                                                 state->dis_clk,
1237                                                 DM_PP_CLOCK_TYPE_DISPLAYPHYCLK,
1238                                                 dp_phyclk_in_khz,
1239                                                 false,
1240                                                 true);
1241                         }
1242                 }
1243         }
1244
1245         dp_enable_link_phy(
1246                 link,
1247                 pipe_ctx->stream->signal,
1248                 pipe_ctx->clock_source->id,
1249                 &link_settings);
1250
1251         if (stream->sink->edid_caps.panel_patch.dppowerup_delay > 0) {
1252                 int delay_dp_power_up_in_ms = stream->sink->edid_caps.panel_patch.dppowerup_delay;
1253
1254                 msleep(delay_dp_power_up_in_ms);
1255         }
1256
1257         panel_mode = dp_get_panel_mode(link);
1258         dpcd_configure_panel_mode(link, panel_mode);
1259
1260         skip_video_pattern = true;
1261
1262         if (link_settings.link_rate == LINK_RATE_LOW)
1263                         skip_video_pattern = false;
1264
1265         if (perform_link_training_with_retries(
1266                         link,
1267                         &link_settings,
1268                         skip_video_pattern,
1269                         LINK_TRAINING_ATTEMPTS)) {
1270                 link->cur_link_settings = link_settings;
1271                 status = DC_OK;
1272         }
1273         else
1274                 status = DC_FAIL_DP_LINK_TRAINING;
1275
1276         enable_stream_features(pipe_ctx);
1277
1278         return status;
1279 }
1280
1281 static enum dc_status enable_link_edp(
1282                 struct dc_state *state,
1283                 struct pipe_ctx *pipe_ctx)
1284 {
1285         enum dc_status status;
1286         struct dc_stream_state *stream = pipe_ctx->stream;
1287         struct dc_link *link = stream->sink->link;
1288         /*in case it is not on*/
1289         link->dc->hwss.edp_power_control(link, true);
1290         link->dc->hwss.edp_wait_for_hpd_ready(link, true);
1291
1292         status = enable_link_dp(state, pipe_ctx);
1293
1294
1295         return status;
1296 }
1297
1298 static enum dc_status enable_link_dp_mst(
1299                 struct dc_state *state,
1300                 struct pipe_ctx *pipe_ctx)
1301 {
1302         struct dc_link *link = pipe_ctx->stream->sink->link;
1303
1304         /* sink signal type after MST branch is MST. Multiple MST sinks
1305          * share one link. Link DP PHY is enable or training only once.
1306          */
1307         if (link->cur_link_settings.lane_count != LANE_COUNT_UNKNOWN)
1308                 return DC_OK;
1309
1310         /* clear payload table */
1311         dm_helpers_dp_mst_clear_payload_allocation_table(link->ctx, link);
1312
1313         /* set the sink to MST mode before enabling the link */
1314         dp_enable_mst_on_sink(link, true);
1315
1316         return enable_link_dp(state, pipe_ctx);
1317 }
1318
1319 static bool get_ext_hdmi_settings(struct pipe_ctx *pipe_ctx,
1320                 enum engine_id eng_id,
1321                 struct ext_hdmi_settings *settings)
1322 {
1323         bool result = false;
1324         int i = 0;
1325         struct integrated_info *integrated_info =
1326                         pipe_ctx->stream->ctx->dc_bios->integrated_info;
1327
1328         if (integrated_info == NULL)
1329                 return false;
1330
1331         /*
1332          * Get retimer settings from sbios for passing SI eye test for DCE11
1333          * The setting values are varied based on board revision and port id
1334          * Therefore the setting values of each ports is passed by sbios.
1335          */
1336
1337         // Check if current bios contains ext Hdmi settings
1338         if (integrated_info->gpu_cap_info & 0x20) {
1339                 switch (eng_id) {
1340                 case ENGINE_ID_DIGA:
1341                         settings->slv_addr = integrated_info->dp0_ext_hdmi_slv_addr;
1342                         settings->reg_num = integrated_info->dp0_ext_hdmi_6g_reg_num;
1343                         settings->reg_num_6g = integrated_info->dp0_ext_hdmi_6g_reg_num;
1344                         memmove(settings->reg_settings,
1345                                         integrated_info->dp0_ext_hdmi_reg_settings,
1346                                         sizeof(integrated_info->dp0_ext_hdmi_reg_settings));
1347                         memmove(settings->reg_settings_6g,
1348                                         integrated_info->dp0_ext_hdmi_6g_reg_settings,
1349                                         sizeof(integrated_info->dp0_ext_hdmi_6g_reg_settings));
1350                         result = true;
1351                         break;
1352                 case ENGINE_ID_DIGB:
1353                         settings->slv_addr = integrated_info->dp1_ext_hdmi_slv_addr;
1354                         settings->reg_num = integrated_info->dp1_ext_hdmi_6g_reg_num;
1355                         settings->reg_num_6g = integrated_info->dp1_ext_hdmi_6g_reg_num;
1356                         memmove(settings->reg_settings,
1357                                         integrated_info->dp1_ext_hdmi_reg_settings,
1358                                         sizeof(integrated_info->dp1_ext_hdmi_reg_settings));
1359                         memmove(settings->reg_settings_6g,
1360                                         integrated_info->dp1_ext_hdmi_6g_reg_settings,
1361                                         sizeof(integrated_info->dp1_ext_hdmi_6g_reg_settings));
1362                         result = true;
1363                         break;
1364                 case ENGINE_ID_DIGC:
1365                         settings->slv_addr = integrated_info->dp2_ext_hdmi_slv_addr;
1366                         settings->reg_num = integrated_info->dp2_ext_hdmi_6g_reg_num;
1367                         settings->reg_num_6g = integrated_info->dp2_ext_hdmi_6g_reg_num;
1368                         memmove(settings->reg_settings,
1369                                         integrated_info->dp2_ext_hdmi_reg_settings,
1370                                         sizeof(integrated_info->dp2_ext_hdmi_reg_settings));
1371                         memmove(settings->reg_settings_6g,
1372                                         integrated_info->dp2_ext_hdmi_6g_reg_settings,
1373                                         sizeof(integrated_info->dp2_ext_hdmi_6g_reg_settings));
1374                         result = true;
1375                         break;
1376                 case ENGINE_ID_DIGD:
1377                         settings->slv_addr = integrated_info->dp3_ext_hdmi_slv_addr;
1378                         settings->reg_num = integrated_info->dp3_ext_hdmi_6g_reg_num;
1379                         settings->reg_num_6g = integrated_info->dp3_ext_hdmi_6g_reg_num;
1380                         memmove(settings->reg_settings,
1381                                         integrated_info->dp3_ext_hdmi_reg_settings,
1382                                         sizeof(integrated_info->dp3_ext_hdmi_reg_settings));
1383                         memmove(settings->reg_settings_6g,
1384                                         integrated_info->dp3_ext_hdmi_6g_reg_settings,
1385                                         sizeof(integrated_info->dp3_ext_hdmi_6g_reg_settings));
1386                         result = true;
1387                         break;
1388                 default:
1389                         break;
1390                 }
1391
1392                 if (result == true) {
1393                         // Validate settings from bios integrated info table
1394                         if (settings->slv_addr == 0)
1395                                 return false;
1396                         if (settings->reg_num > 9)
1397                                 return false;
1398                         if (settings->reg_num_6g > 3)
1399                                 return false;
1400
1401                         for (i = 0; i < settings->reg_num; i++) {
1402                                 if (settings->reg_settings[i].i2c_reg_index > 0x20)
1403                                         return false;
1404                         }
1405
1406                         for (i = 0; i < settings->reg_num_6g; i++) {
1407                                 if (settings->reg_settings_6g[i].i2c_reg_index > 0x20)
1408                                         return false;
1409                         }
1410                 }
1411         }
1412
1413         return result;
1414 }
1415
1416 static bool i2c_write(struct pipe_ctx *pipe_ctx,
1417                 uint8_t address, uint8_t *buffer, uint32_t length)
1418 {
1419         struct i2c_command cmd = {0};
1420         struct i2c_payload payload = {0};
1421
1422         memset(&payload, 0, sizeof(payload));
1423         memset(&cmd, 0, sizeof(cmd));
1424
1425         cmd.number_of_payloads = 1;
1426         cmd.engine = I2C_COMMAND_ENGINE_DEFAULT;
1427         cmd.speed = pipe_ctx->stream->ctx->dc->caps.i2c_speed_in_khz;
1428
1429         payload.address = address;
1430         payload.data = buffer;
1431         payload.length = length;
1432         payload.write = true;
1433         cmd.payloads = &payload;
1434
1435         if (dc_submit_i2c(pipe_ctx->stream->ctx->dc,
1436                         pipe_ctx->stream->sink->link->link_index, &cmd))
1437                 return true;
1438
1439         return false;
1440 }
1441
1442 static void write_i2c_retimer_setting(
1443                 struct pipe_ctx *pipe_ctx,
1444                 bool is_vga_mode,
1445                 bool is_over_340mhz,
1446                 struct ext_hdmi_settings *settings)
1447 {
1448         uint8_t slave_address = (settings->slv_addr >> 1);
1449         uint8_t buffer[2];
1450         const uint8_t apply_rx_tx_change = 0x4;
1451         uint8_t offset = 0xA;
1452         uint8_t value = 0;
1453         int i = 0;
1454         bool i2c_success = false;
1455
1456         memset(&buffer, 0, sizeof(buffer));
1457
1458         /* Start Ext-Hdmi programming*/
1459
1460         for (i = 0; i < settings->reg_num; i++) {
1461                 /* Apply 3G settings */
1462                 if (settings->reg_settings[i].i2c_reg_index <= 0x20) {
1463
1464                         buffer[0] = settings->reg_settings[i].i2c_reg_index;
1465                         buffer[1] = settings->reg_settings[i].i2c_reg_val;
1466                         i2c_success = i2c_write(pipe_ctx, slave_address,
1467                                                 buffer, sizeof(buffer));
1468
1469                         if (!i2c_success)
1470                                 /* Write failure */
1471                                 ASSERT(i2c_success);
1472
1473                         /* Based on DP159 specs, APPLY_RX_TX_CHANGE bit in 0x0A
1474                          * needs to be set to 1 on every 0xA-0xC write.
1475                          */
1476                         if (settings->reg_settings[i].i2c_reg_index == 0xA ||
1477                                 settings->reg_settings[i].i2c_reg_index == 0xB ||
1478                                 settings->reg_settings[i].i2c_reg_index == 0xC) {
1479
1480                                 /* Query current value from offset 0xA */
1481                                 if (settings->reg_settings[i].i2c_reg_index == 0xA)
1482                                         value = settings->reg_settings[i].i2c_reg_val;
1483                                 else {
1484                                         i2c_success =
1485                                                 dal_ddc_service_query_ddc_data(
1486                                                 pipe_ctx->stream->sink->link->ddc,
1487                                                 slave_address, &offset, 1, &value, 1);
1488                                         if (!i2c_success)
1489                                                 /* Write failure */
1490                                                 ASSERT(i2c_success);
1491                                 }
1492
1493                                 buffer[0] = offset;
1494                                 /* Set APPLY_RX_TX_CHANGE bit to 1 */
1495                                 buffer[1] = value | apply_rx_tx_change;
1496                                 i2c_success = i2c_write(pipe_ctx, slave_address,
1497                                                 buffer, sizeof(buffer));
1498                                 if (!i2c_success)
1499                                         /* Write failure */
1500                                         ASSERT(i2c_success);
1501                         }
1502                 }
1503         }
1504
1505         /* Apply 3G settings */
1506         if (is_over_340mhz) {
1507                 for (i = 0; i < settings->reg_num_6g; i++) {
1508                         /* Apply 3G settings */
1509                         if (settings->reg_settings[i].i2c_reg_index <= 0x20) {
1510
1511                                 buffer[0] = settings->reg_settings_6g[i].i2c_reg_index;
1512                                 buffer[1] = settings->reg_settings_6g[i].i2c_reg_val;
1513                                 i2c_success = i2c_write(pipe_ctx, slave_address,
1514                                                         buffer, sizeof(buffer));
1515
1516                                 if (!i2c_success)
1517                                         /* Write failure */
1518                                         ASSERT(i2c_success);
1519
1520                                 /* Based on DP159 specs, APPLY_RX_TX_CHANGE bit in 0x0A
1521                                  * needs to be set to 1 on every 0xA-0xC write.
1522                                  */
1523                                 if (settings->reg_settings_6g[i].i2c_reg_index == 0xA ||
1524                                         settings->reg_settings_6g[i].i2c_reg_index == 0xB ||
1525                                         settings->reg_settings_6g[i].i2c_reg_index == 0xC) {
1526
1527                                         /* Query current value from offset 0xA */
1528                                         if (settings->reg_settings_6g[i].i2c_reg_index == 0xA)
1529                                                 value = settings->reg_settings_6g[i].i2c_reg_val;
1530                                         else {
1531                                                 i2c_success =
1532                                                                 dal_ddc_service_query_ddc_data(
1533                                                                 pipe_ctx->stream->sink->link->ddc,
1534                                                                 slave_address, &offset, 1, &value, 1);
1535                                                 if (!i2c_success)
1536                                                         /* Write failure */
1537                                                         ASSERT(i2c_success);
1538                                         }
1539
1540                                         buffer[0] = offset;
1541                                         /* Set APPLY_RX_TX_CHANGE bit to 1 */
1542                                         buffer[1] = value | apply_rx_tx_change;
1543                                         i2c_success = i2c_write(pipe_ctx, slave_address,
1544                                                         buffer, sizeof(buffer));
1545                                         if (!i2c_success)
1546                                                 /* Write failure */
1547                                                 ASSERT(i2c_success);
1548                                 }
1549                         }
1550                 }
1551         }
1552
1553         if (is_vga_mode) {
1554                 /* Program additional settings if using 640x480 resolution */
1555
1556                 /* Write offset 0xFF to 0x01 */
1557                 buffer[0] = 0xff;
1558                 buffer[1] = 0x01;
1559                 i2c_success = i2c_write(pipe_ctx, slave_address,
1560                                 buffer, sizeof(buffer));
1561                 if (!i2c_success)
1562                         /* Write failure */
1563                         ASSERT(i2c_success);
1564
1565                 /* Write offset 0x00 to 0x23 */
1566                 buffer[0] = 0x00;
1567                 buffer[1] = 0x23;
1568                 i2c_success = i2c_write(pipe_ctx, slave_address,
1569                                 buffer, sizeof(buffer));
1570                 if (!i2c_success)
1571                         /* Write failure */
1572                         ASSERT(i2c_success);
1573
1574                 /* Write offset 0xff to 0x00 */
1575                 buffer[0] = 0xff;
1576                 buffer[1] = 0x00;
1577                 i2c_success = i2c_write(pipe_ctx, slave_address,
1578                                 buffer, sizeof(buffer));
1579                 if (!i2c_success)
1580                         /* Write failure */
1581                         ASSERT(i2c_success);
1582
1583         }
1584 }
1585
1586 static void write_i2c_default_retimer_setting(
1587                 struct pipe_ctx *pipe_ctx,
1588                 bool is_vga_mode,
1589                 bool is_over_340mhz)
1590 {
1591         uint8_t slave_address = (0xBA >> 1);
1592         uint8_t buffer[2];
1593         bool i2c_success = false;
1594
1595         memset(&buffer, 0, sizeof(buffer));
1596
1597         /* Program Slave Address for tuning single integrity */
1598         /* Write offset 0x0A to 0x13 */
1599         buffer[0] = 0x0A;
1600         buffer[1] = 0x13;
1601         i2c_success = i2c_write(pipe_ctx, slave_address,
1602                         buffer, sizeof(buffer));
1603         if (!i2c_success)
1604                 /* Write failure */
1605                 ASSERT(i2c_success);
1606
1607         /* Write offset 0x0A to 0x17 */
1608         buffer[0] = 0x0A;
1609         buffer[1] = 0x17;
1610         i2c_success = i2c_write(pipe_ctx, slave_address,
1611                         buffer, sizeof(buffer));
1612         if (!i2c_success)
1613                 /* Write failure */
1614                 ASSERT(i2c_success);
1615
1616         /* Write offset 0x0B to 0xDA or 0xD8 */
1617         buffer[0] = 0x0B;
1618         buffer[1] = is_over_340mhz ? 0xDA : 0xD8;
1619         i2c_success = i2c_write(pipe_ctx, slave_address,
1620                         buffer, sizeof(buffer));
1621         if (!i2c_success)
1622                 /* Write failure */
1623                 ASSERT(i2c_success);
1624
1625         /* Write offset 0x0A to 0x17 */
1626         buffer[0] = 0x0A;
1627         buffer[1] = 0x17;
1628         i2c_success = i2c_write(pipe_ctx, slave_address,
1629                         buffer, sizeof(buffer));
1630         if (!i2c_success)
1631                 /* Write failure */
1632                 ASSERT(i2c_success);
1633
1634         /* Write offset 0x0C to 0x1D or 0x91 */
1635         buffer[0] = 0x0C;
1636         buffer[1] = is_over_340mhz ? 0x1D : 0x91;
1637         i2c_success = i2c_write(pipe_ctx, slave_address,
1638                         buffer, sizeof(buffer));
1639         if (!i2c_success)
1640                 /* Write failure */
1641                 ASSERT(i2c_success);
1642
1643         /* Write offset 0x0A to 0x17 */
1644         buffer[0] = 0x0A;
1645         buffer[1] = 0x17;
1646         i2c_success = i2c_write(pipe_ctx, slave_address,
1647                         buffer, sizeof(buffer));
1648         if (!i2c_success)
1649                 /* Write failure */
1650                 ASSERT(i2c_success);
1651
1652
1653         if (is_vga_mode) {
1654                 /* Program additional settings if using 640x480 resolution */
1655
1656                 /* Write offset 0xFF to 0x01 */
1657                 buffer[0] = 0xff;
1658                 buffer[1] = 0x01;
1659                 i2c_success = i2c_write(pipe_ctx, slave_address,
1660                                 buffer, sizeof(buffer));
1661                 if (!i2c_success)
1662                         /* Write failure */
1663                         ASSERT(i2c_success);
1664
1665                 /* Write offset 0x00 to 0x23 */
1666                 buffer[0] = 0x00;
1667                 buffer[1] = 0x23;
1668                 i2c_success = i2c_write(pipe_ctx, slave_address,
1669                                 buffer, sizeof(buffer));
1670                 if (!i2c_success)
1671                         /* Write failure */
1672                         ASSERT(i2c_success);
1673
1674                 /* Write offset 0xff to 0x00 */
1675                 buffer[0] = 0xff;
1676                 buffer[1] = 0x00;
1677                 i2c_success = i2c_write(pipe_ctx, slave_address,
1678                                 buffer, sizeof(buffer));
1679                 if (!i2c_success)
1680                         /* Write failure */
1681                         ASSERT(i2c_success);
1682         }
1683 }
1684
1685 static void write_i2c_redriver_setting(
1686                 struct pipe_ctx *pipe_ctx,
1687                 bool is_over_340mhz)
1688 {
1689         uint8_t slave_address = (0xF0 >> 1);
1690         uint8_t buffer[16];
1691         bool i2c_success = false;
1692
1693         memset(&buffer, 0, sizeof(buffer));
1694
1695         // Program Slave Address for tuning single integrity
1696         buffer[3] = 0x4E;
1697         buffer[4] = 0x4E;
1698         buffer[5] = 0x4E;
1699         buffer[6] = is_over_340mhz ? 0x4E : 0x4A;
1700
1701         i2c_success = i2c_write(pipe_ctx, slave_address,
1702                                         buffer, sizeof(buffer));
1703
1704         if (!i2c_success)
1705                 /* Write failure */
1706                 ASSERT(i2c_success);
1707 }
1708
1709 static void enable_link_hdmi(struct pipe_ctx *pipe_ctx)
1710 {
1711         struct dc_stream_state *stream = pipe_ctx->stream;
1712         struct dc_link *link = stream->sink->link;
1713         enum dc_color_depth display_color_depth;
1714         enum engine_id eng_id;
1715         struct ext_hdmi_settings settings = {0};
1716         bool is_over_340mhz = false;
1717         bool is_vga_mode = (stream->timing.h_addressable == 640)
1718                         && (stream->timing.v_addressable == 480);
1719
1720         if (stream->phy_pix_clk > 340000)
1721                 is_over_340mhz = true;
1722
1723         if (dc_is_hdmi_signal(pipe_ctx->stream->signal)) {
1724                 unsigned short masked_chip_caps = pipe_ctx->stream->sink->link->chip_caps &
1725                                 EXT_DISPLAY_PATH_CAPS__EXT_CHIP_MASK;
1726                 if (masked_chip_caps == EXT_DISPLAY_PATH_CAPS__HDMI20_TISN65DP159RSBT) {
1727                         /* DP159, Retimer settings */
1728                         eng_id = pipe_ctx->stream_res.stream_enc->id;
1729
1730                         if (get_ext_hdmi_settings(pipe_ctx, eng_id, &settings)) {
1731                                 write_i2c_retimer_setting(pipe_ctx,
1732                                                 is_vga_mode, is_over_340mhz, &settings);
1733                         } else {
1734                                 write_i2c_default_retimer_setting(pipe_ctx,
1735                                                 is_vga_mode, is_over_340mhz);
1736                         }
1737                 } else if (masked_chip_caps == EXT_DISPLAY_PATH_CAPS__HDMI20_PI3EQX1204) {
1738                         /* PI3EQX1204, Redriver settings */
1739                         write_i2c_redriver_setting(pipe_ctx, is_over_340mhz);
1740                 }
1741         }
1742
1743         if (dc_is_hdmi_signal(pipe_ctx->stream->signal))
1744                 dal_ddc_service_write_scdc_data(
1745                         stream->sink->link->ddc,
1746                         stream->phy_pix_clk,
1747                         stream->timing.flags.LTE_340MCSC_SCRAMBLE);
1748
1749         memset(&stream->sink->link->cur_link_settings, 0,
1750                         sizeof(struct dc_link_settings));
1751
1752         display_color_depth = stream->timing.display_color_depth;
1753         if (stream->timing.pixel_encoding == PIXEL_ENCODING_YCBCR422)
1754                 display_color_depth = COLOR_DEPTH_888;
1755
1756         link->link_enc->funcs->enable_tmds_output(
1757                         link->link_enc,
1758                         pipe_ctx->clock_source->id,
1759                         display_color_depth,
1760                         pipe_ctx->stream->signal,
1761                         stream->phy_pix_clk);
1762
1763         if (pipe_ctx->stream->signal == SIGNAL_TYPE_HDMI_TYPE_A)
1764                 dal_ddc_service_read_scdc_data(link->ddc);
1765 }
1766
1767 /****************************enable_link***********************************/
1768 static enum dc_status enable_link(
1769                 struct dc_state *state,
1770                 struct pipe_ctx *pipe_ctx)
1771 {
1772         enum dc_status status = DC_ERROR_UNEXPECTED;
1773         switch (pipe_ctx->stream->signal) {
1774         case SIGNAL_TYPE_DISPLAY_PORT:
1775                 status = enable_link_dp(state, pipe_ctx);
1776                 break;
1777         case SIGNAL_TYPE_EDP:
1778                 status = enable_link_edp(state, pipe_ctx);
1779                 break;
1780         case SIGNAL_TYPE_DISPLAY_PORT_MST:
1781                 status = enable_link_dp_mst(state, pipe_ctx);
1782                 msleep(200);
1783                 break;
1784         case SIGNAL_TYPE_DVI_SINGLE_LINK:
1785         case SIGNAL_TYPE_DVI_DUAL_LINK:
1786         case SIGNAL_TYPE_HDMI_TYPE_A:
1787                 enable_link_hdmi(pipe_ctx);
1788                 status = DC_OK;
1789                 break;
1790         case SIGNAL_TYPE_VIRTUAL:
1791                 status = DC_OK;
1792                 break;
1793         default:
1794                 break;
1795         }
1796
1797         if (pipe_ctx->stream_res.audio && status == DC_OK) {
1798                 struct dc *core_dc = pipe_ctx->stream->ctx->dc;
1799                 /* notify audio driver for audio modes of monitor */
1800                 struct pp_smu_funcs_rv *pp_smu = core_dc->res_pool->pp_smu;
1801                 unsigned int i, num_audio = 1;
1802                 for (i = 0; i < MAX_PIPES; i++) {
1803                         /*current_state not updated yet*/
1804                         if (core_dc->current_state->res_ctx.pipe_ctx[i].stream_res.audio != NULL)
1805                                 num_audio++;
1806                 }
1807
1808                 pipe_ctx->stream_res.audio->funcs->az_enable(pipe_ctx->stream_res.audio);
1809
1810                 if (num_audio == 1 && pp_smu != NULL && pp_smu->set_pme_wa_enable != NULL)
1811                         /*this is the first audio. apply the PME w/a in order to wake AZ from D3*/
1812                         pp_smu->set_pme_wa_enable(&pp_smu->pp_smu);
1813                 /* un-mute audio */
1814                 /* TODO: audio should be per stream rather than per link */
1815                 pipe_ctx->stream_res.stream_enc->funcs->audio_mute_control(
1816                         pipe_ctx->stream_res.stream_enc, false);
1817         }
1818
1819         return status;
1820 }
1821
1822 static void disable_link(struct dc_link *link, enum signal_type signal)
1823 {
1824         /*
1825          * TODO: implement call for dp_set_hw_test_pattern
1826          * it is needed for compliance testing
1827          */
1828
1829         /* here we need to specify that encoder output settings
1830          * need to be calculated as for the set mode,
1831          * it will lead to querying dynamic link capabilities
1832          * which should be done before enable output */
1833
1834         if (dc_is_dp_signal(signal)) {
1835                 /* SST DP, eDP */
1836                 if (dc_is_dp_sst_signal(signal))
1837                         dp_disable_link_phy(link, signal);
1838                 else
1839                         dp_disable_link_phy_mst(link, signal);
1840         } else
1841                 link->link_enc->funcs->disable_output(link->link_enc, signal);
1842 }
1843
1844 static bool dp_active_dongle_validate_timing(
1845                 const struct dc_crtc_timing *timing,
1846                 const struct dc_dongle_caps *dongle_caps)
1847 {
1848         unsigned int required_pix_clk = timing->pix_clk_khz;
1849
1850         if (dongle_caps->dongle_type != DISPLAY_DONGLE_DP_HDMI_CONVERTER ||
1851                 dongle_caps->extendedCapValid == false)
1852                 return true;
1853
1854         /* Check Pixel Encoding */
1855         switch (timing->pixel_encoding) {
1856         case PIXEL_ENCODING_RGB:
1857         case PIXEL_ENCODING_YCBCR444:
1858                 break;
1859         case PIXEL_ENCODING_YCBCR422:
1860                 if (!dongle_caps->is_dp_hdmi_ycbcr422_pass_through)
1861                         return false;
1862                 break;
1863         case PIXEL_ENCODING_YCBCR420:
1864                 if (!dongle_caps->is_dp_hdmi_ycbcr420_pass_through)
1865                         return false;
1866                 break;
1867         default:
1868                 /* Invalid Pixel Encoding*/
1869                 return false;
1870         }
1871
1872
1873         /* Check Color Depth and Pixel Clock */
1874         if (timing->pixel_encoding == PIXEL_ENCODING_YCBCR420)
1875                 required_pix_clk /= 2;
1876         else if (timing->pixel_encoding == PIXEL_ENCODING_YCBCR422)
1877                 required_pix_clk = required_pix_clk * 2 / 3;
1878
1879         switch (timing->display_color_depth) {
1880         case COLOR_DEPTH_666:
1881         case COLOR_DEPTH_888:
1882                 /*888 and 666 should always be supported*/
1883                 break;
1884         case COLOR_DEPTH_101010:
1885                 if (dongle_caps->dp_hdmi_max_bpc < 10)
1886                         return false;
1887                 required_pix_clk = required_pix_clk * 10 / 8;
1888                 break;
1889         case COLOR_DEPTH_121212:
1890                 if (dongle_caps->dp_hdmi_max_bpc < 12)
1891                         return false;
1892                 required_pix_clk = required_pix_clk * 12 / 8;
1893                 break;
1894
1895         case COLOR_DEPTH_141414:
1896         case COLOR_DEPTH_161616:
1897         default:
1898                 /* These color depths are currently not supported */
1899                 return false;
1900         }
1901
1902         if (required_pix_clk > dongle_caps->dp_hdmi_max_pixel_clk)
1903                 return false;
1904
1905         return true;
1906 }
1907
1908 enum dc_status dc_link_validate_mode_timing(
1909                 const struct dc_stream_state *stream,
1910                 struct dc_link *link,
1911                 const struct dc_crtc_timing *timing)
1912 {
1913         uint32_t max_pix_clk = stream->sink->dongle_max_pix_clk;
1914         struct dc_dongle_caps *dongle_caps = &link->dpcd_caps.dongle_caps;
1915
1916         /* A hack to avoid failing any modes for EDID override feature on
1917          * topology change such as lower quality cable for DP or different dongle
1918          */
1919         if (link->remote_sinks[0])
1920                 return DC_OK;
1921
1922         /* Passive Dongle */
1923         if (0 != max_pix_clk && timing->pix_clk_khz > max_pix_clk)
1924                 return DC_EXCEED_DONGLE_CAP;
1925
1926         /* Active Dongle*/
1927         if (!dp_active_dongle_validate_timing(timing, dongle_caps))
1928                 return DC_EXCEED_DONGLE_CAP;
1929
1930         switch (stream->signal) {
1931         case SIGNAL_TYPE_EDP:
1932         case SIGNAL_TYPE_DISPLAY_PORT:
1933                 if (!dp_validate_mode_timing(
1934                                 link,
1935                                 timing))
1936                         return DC_NO_DP_LINK_BANDWIDTH;
1937                 break;
1938
1939         default:
1940                 break;
1941         }
1942
1943         return DC_OK;
1944 }
1945
1946
1947 bool dc_link_set_backlight_level(const struct dc_link *link, uint32_t level,
1948                 uint32_t frame_ramp, const struct dc_stream_state *stream)
1949 {
1950         struct dc  *core_dc = link->ctx->dc;
1951         struct abm *abm = core_dc->res_pool->abm;
1952         struct dmcu *dmcu = core_dc->res_pool->dmcu;
1953         struct dc_context *dc_ctx = link->ctx;
1954         unsigned int controller_id = 0;
1955         bool use_smooth_brightness = true;
1956         int i;
1957
1958         if ((dmcu == NULL) ||
1959                 (abm == NULL) ||
1960                 (abm->funcs->set_backlight_level == NULL))
1961                 return false;
1962
1963         use_smooth_brightness = dmcu->funcs->is_dmcu_initialized(dmcu);
1964
1965         DC_LOG_BACKLIGHT("New Backlight level: %d (0x%X)\n", level, level);
1966
1967         if (dc_is_embedded_signal(link->connector_signal)) {
1968                 if (stream != NULL) {
1969                         for (i = 0; i < MAX_PIPES; i++) {
1970                                 if (core_dc->current_state->res_ctx.
1971                                                 pipe_ctx[i].stream
1972                                                 == stream)
1973                                         /* DMCU -1 for all controller id values,
1974                                          * therefore +1 here
1975                                          */
1976                                         controller_id =
1977                                                 core_dc->current_state->
1978                                                 res_ctx.pipe_ctx[i].stream_res.tg->inst +
1979                                                 1;
1980                         }
1981                 }
1982                 abm->funcs->set_backlight_level(
1983                                 abm,
1984                                 level,
1985                                 frame_ramp,
1986                                 controller_id,
1987                                 use_smooth_brightness);
1988         }
1989
1990         return true;
1991 }
1992
1993 bool dc_link_set_psr_enable(const struct dc_link *link, bool enable, bool wait)
1994 {
1995         struct dc  *core_dc = link->ctx->dc;
1996         struct dmcu *dmcu = core_dc->res_pool->dmcu;
1997
1998         if (dmcu != NULL && link->psr_enabled)
1999                 dmcu->funcs->set_psr_enable(dmcu, enable, wait);
2000
2001         return true;
2002 }
2003
2004 const struct dc_link_status *dc_link_get_status(const struct dc_link *link)
2005 {
2006         return &link->link_status;
2007 }
2008
2009 void core_link_resume(struct dc_link *link)
2010 {
2011         if (link->connector_signal != SIGNAL_TYPE_VIRTUAL)
2012                 program_hpd_filter(link);
2013 }
2014
2015 static struct fixed31_32 get_pbn_per_slot(struct dc_stream_state *stream)
2016 {
2017         struct dc_link_settings *link_settings =
2018                         &stream->sink->link->cur_link_settings;
2019         uint32_t link_rate_in_mbps =
2020                         link_settings->link_rate * LINK_RATE_REF_FREQ_IN_MHZ;
2021         struct fixed31_32 mbps = dal_fixed31_32_from_int(
2022                         link_rate_in_mbps * link_settings->lane_count);
2023
2024         return dal_fixed31_32_div_int(mbps, 54);
2025 }
2026
2027 static int get_color_depth(enum dc_color_depth color_depth)
2028 {
2029         switch (color_depth) {
2030         case COLOR_DEPTH_666: return 6;
2031         case COLOR_DEPTH_888: return 8;
2032         case COLOR_DEPTH_101010: return 10;
2033         case COLOR_DEPTH_121212: return 12;
2034         case COLOR_DEPTH_141414: return 14;
2035         case COLOR_DEPTH_161616: return 16;
2036         default: return 0;
2037         }
2038 }
2039
2040 static struct fixed31_32 get_pbn_from_timing(struct pipe_ctx *pipe_ctx)
2041 {
2042         uint32_t bpc;
2043         uint64_t kbps;
2044         struct fixed31_32 peak_kbps;
2045         uint32_t numerator;
2046         uint32_t denominator;
2047
2048         bpc = get_color_depth(pipe_ctx->stream_res.pix_clk_params.color_depth);
2049         kbps = pipe_ctx->stream_res.pix_clk_params.requested_pix_clk * bpc * 3;
2050
2051         /*
2052          * margin 5300ppm + 300ppm ~ 0.6% as per spec, factor is 1.006
2053          * The unit of 54/64Mbytes/sec is an arbitrary unit chosen based on
2054          * common multiplier to render an integer PBN for all link rate/lane
2055          * counts combinations
2056          * calculate
2057          * peak_kbps *= (1006/1000)
2058          * peak_kbps *= (64/54)
2059          * peak_kbps *= 8    convert to bytes
2060          */
2061
2062         numerator = 64 * PEAK_FACTOR_X1000;
2063         denominator = 54 * 8 * 1000 * 1000;
2064         kbps *= numerator;
2065         peak_kbps = dal_fixed31_32_from_fraction(kbps, denominator);
2066
2067         return peak_kbps;
2068 }
2069
2070 static void update_mst_stream_alloc_table(
2071         struct dc_link *link,
2072         struct stream_encoder *stream_enc,
2073         const struct dp_mst_stream_allocation_table *proposed_table)
2074 {
2075         struct link_mst_stream_allocation work_table[MAX_CONTROLLER_NUM] = {
2076                         { 0 } };
2077         struct link_mst_stream_allocation *dc_alloc;
2078
2079         int i;
2080         int j;
2081
2082         /* if DRM proposed_table has more than one new payload */
2083         ASSERT(proposed_table->stream_count -
2084                         link->mst_stream_alloc_table.stream_count < 2);
2085
2086         /* copy proposed_table to link, add stream encoder */
2087         for (i = 0; i < proposed_table->stream_count; i++) {
2088
2089                 for (j = 0; j < link->mst_stream_alloc_table.stream_count; j++) {
2090                         dc_alloc =
2091                         &link->mst_stream_alloc_table.stream_allocations[j];
2092
2093                         if (dc_alloc->vcp_id ==
2094                                 proposed_table->stream_allocations[i].vcp_id) {
2095
2096                                 work_table[i] = *dc_alloc;
2097                                 break; /* exit j loop */
2098                         }
2099                 }
2100
2101                 /* new vcp_id */
2102                 if (j == link->mst_stream_alloc_table.stream_count) {
2103                         work_table[i].vcp_id =
2104                                 proposed_table->stream_allocations[i].vcp_id;
2105                         work_table[i].slot_count =
2106                                 proposed_table->stream_allocations[i].slot_count;
2107                         work_table[i].stream_enc = stream_enc;
2108                 }
2109         }
2110
2111         /* update link->mst_stream_alloc_table with work_table */
2112         link->mst_stream_alloc_table.stream_count =
2113                         proposed_table->stream_count;
2114         for (i = 0; i < MAX_CONTROLLER_NUM; i++)
2115                 link->mst_stream_alloc_table.stream_allocations[i] =
2116                                 work_table[i];
2117 }
2118
2119 /* convert link_mst_stream_alloc_table to dm dp_mst_stream_alloc_table
2120  * because stream_encoder is not exposed to dm
2121  */
2122 static enum dc_status allocate_mst_payload(struct pipe_ctx *pipe_ctx)
2123 {
2124         struct dc_stream_state *stream = pipe_ctx->stream;
2125         struct dc_link *link = stream->sink->link;
2126         struct link_encoder *link_encoder = link->link_enc;
2127         struct stream_encoder *stream_encoder = pipe_ctx->stream_res.stream_enc;
2128         struct dp_mst_stream_allocation_table proposed_table = {0};
2129         struct fixed31_32 avg_time_slots_per_mtp;
2130         struct fixed31_32 pbn;
2131         struct fixed31_32 pbn_per_slot;
2132         struct dc_context *dc_ctx = link->ctx;
2133         uint8_t i;
2134
2135         /* enable_link_dp_mst already check link->enabled_stream_count
2136          * and stream is in link->stream[]. This is called during set mode,
2137          * stream_enc is available.
2138          */
2139
2140         /* get calculate VC payload for stream: stream_alloc */
2141         if (dm_helpers_dp_mst_write_payload_allocation_table(
2142                 stream->ctx,
2143                 stream,
2144                 &proposed_table,
2145                 true)) {
2146                 update_mst_stream_alloc_table(
2147                                         link, pipe_ctx->stream_res.stream_enc, &proposed_table);
2148         }
2149         else
2150                 DC_LOG_WARNING("Failed to update"
2151                                 "MST allocation table for"
2152                                 "pipe idx:%d\n",
2153                                 pipe_ctx->pipe_idx);
2154
2155         DC_LOG_MST("%s  "
2156                         "stream_count: %d: \n ",
2157                         __func__,
2158                         link->mst_stream_alloc_table.stream_count);
2159
2160         for (i = 0; i < MAX_CONTROLLER_NUM; i++) {
2161                 DC_LOG_MST("stream_enc[%d]: 0x%x      "
2162                 "stream[%d].vcp_id: %d      "
2163                 "stream[%d].slot_count: %d\n",
2164                 i,
2165                 link->mst_stream_alloc_table.stream_allocations[i].stream_enc,
2166                 i,
2167                 link->mst_stream_alloc_table.stream_allocations[i].vcp_id,
2168                 i,
2169                 link->mst_stream_alloc_table.stream_allocations[i].slot_count);
2170         }
2171
2172         ASSERT(proposed_table.stream_count > 0);
2173
2174         /* program DP source TX for payload */
2175         link_encoder->funcs->update_mst_stream_allocation_table(
2176                 link_encoder,
2177                 &link->mst_stream_alloc_table);
2178
2179         /* send down message */
2180         dm_helpers_dp_mst_poll_for_allocation_change_trigger(
2181                         stream->ctx,
2182                         stream);
2183
2184         dm_helpers_dp_mst_send_payload_allocation(
2185                         stream->ctx,
2186                         stream,
2187                         true);
2188
2189         /* slot X.Y for only current stream */
2190         pbn_per_slot = get_pbn_per_slot(stream);
2191         pbn = get_pbn_from_timing(pipe_ctx);
2192         avg_time_slots_per_mtp = dal_fixed31_32_div(pbn, pbn_per_slot);
2193
2194         stream_encoder->funcs->set_mst_bandwidth(
2195                 stream_encoder,
2196                 avg_time_slots_per_mtp);
2197
2198         return DC_OK;
2199
2200 }
2201
2202 static enum dc_status deallocate_mst_payload(struct pipe_ctx *pipe_ctx)
2203 {
2204         struct dc_stream_state *stream = pipe_ctx->stream;
2205         struct dc_link *link = stream->sink->link;
2206         struct link_encoder *link_encoder = link->link_enc;
2207         struct stream_encoder *stream_encoder = pipe_ctx->stream_res.stream_enc;
2208         struct dp_mst_stream_allocation_table proposed_table = {0};
2209         struct fixed31_32 avg_time_slots_per_mtp = dal_fixed31_32_from_int(0);
2210         uint8_t i;
2211         bool mst_mode = (link->type == dc_connection_mst_branch);
2212         struct dc_context *dc_ctx = link->ctx;
2213
2214         /* deallocate_mst_payload is called before disable link. When mode or
2215          * disable/enable monitor, new stream is created which is not in link
2216          * stream[] yet. For this, payload is not allocated yet, so de-alloc
2217          * should not done. For new mode set, map_resources will get engine
2218          * for new stream, so stream_enc->id should be validated until here.
2219          */
2220
2221         /* slot X.Y */
2222         stream_encoder->funcs->set_mst_bandwidth(
2223                 stream_encoder,
2224                 avg_time_slots_per_mtp);
2225
2226         /* TODO: which component is responsible for remove payload table? */
2227         if (mst_mode) {
2228                 if (dm_helpers_dp_mst_write_payload_allocation_table(
2229                                 stream->ctx,
2230                                 stream,
2231                                 &proposed_table,
2232                                 false)) {
2233
2234                         update_mst_stream_alloc_table(
2235                                 link, pipe_ctx->stream_res.stream_enc, &proposed_table);
2236                 }
2237                 else {
2238                                 DC_LOG_WARNING("Failed to update"
2239                                                 "MST allocation table for"
2240                                                 "pipe idx:%d\n",
2241                                                 pipe_ctx->pipe_idx);
2242                 }
2243         }
2244
2245         DC_LOG_MST("%s"
2246                         "stream_count: %d: ",
2247                         __func__,
2248                         link->mst_stream_alloc_table.stream_count);
2249
2250         for (i = 0; i < MAX_CONTROLLER_NUM; i++) {
2251                 DC_LOG_MST("stream_enc[%d]: 0x%x      "
2252                 "stream[%d].vcp_id: %d      "
2253                 "stream[%d].slot_count: %d\n",
2254                 i,
2255                 link->mst_stream_alloc_table.stream_allocations[i].stream_enc,
2256                 i,
2257                 link->mst_stream_alloc_table.stream_allocations[i].vcp_id,
2258                 i,
2259                 link->mst_stream_alloc_table.stream_allocations[i].slot_count);
2260         }
2261
2262         link_encoder->funcs->update_mst_stream_allocation_table(
2263                 link_encoder,
2264                 &link->mst_stream_alloc_table);
2265
2266         if (mst_mode) {
2267                 dm_helpers_dp_mst_poll_for_allocation_change_trigger(
2268                         stream->ctx,
2269                         stream);
2270
2271                 dm_helpers_dp_mst_send_payload_allocation(
2272                         stream->ctx,
2273                         stream,
2274                         false);
2275         }
2276
2277         return DC_OK;
2278 }
2279
2280 void core_link_enable_stream(
2281                 struct dc_state *state,
2282                 struct pipe_ctx *pipe_ctx)
2283 {
2284         struct dc  *core_dc = pipe_ctx->stream->ctx->dc;
2285         struct dc_context *dc_ctx = pipe_ctx->stream->ctx;
2286         enum dc_status status;
2287
2288         /* eDP lit up by bios already, no need to enable again. */
2289         if (pipe_ctx->stream->signal == SIGNAL_TYPE_EDP &&
2290                 core_dc->apply_edp_fast_boot_optimization) {
2291                 core_dc->apply_edp_fast_boot_optimization = false;
2292                 pipe_ctx->stream->dpms_off = false;
2293                 return;
2294         }
2295
2296         if (pipe_ctx->stream->dpms_off)
2297                 return;
2298
2299         status = enable_link(state, pipe_ctx);
2300
2301         if (status != DC_OK) {
2302                         DC_LOG_WARNING("enabling link %u failed: %d\n",
2303                         pipe_ctx->stream->sink->link->link_index,
2304                         status);
2305
2306                         /* Abort stream enable *unless* the failure was due to
2307                          * DP link training - some DP monitors will recover and
2308                          * show the stream anyway. But MST displays can't proceed
2309                          * without link training.
2310                          */
2311                         if (status != DC_FAIL_DP_LINK_TRAINING ||
2312                                         pipe_ctx->stream->signal == SIGNAL_TYPE_DISPLAY_PORT_MST) {
2313                                 BREAK_TO_DEBUGGER();
2314                                 return;
2315                         }
2316         }
2317
2318         /* turn off otg test pattern if enable */
2319         pipe_ctx->stream_res.tg->funcs->set_test_pattern(pipe_ctx->stream_res.tg,
2320                         CONTROLLER_DP_TEST_PATTERN_VIDEOMODE,
2321                         COLOR_DEPTH_UNDEFINED);
2322
2323         core_dc->hwss.enable_stream(pipe_ctx);
2324
2325         if (pipe_ctx->stream->signal == SIGNAL_TYPE_DISPLAY_PORT_MST)
2326                 allocate_mst_payload(pipe_ctx);
2327
2328         core_dc->hwss.unblank_stream(pipe_ctx,
2329                 &pipe_ctx->stream->sink->link->cur_link_settings);
2330 }
2331
2332 void core_link_disable_stream(struct pipe_ctx *pipe_ctx, int option)
2333 {
2334         struct dc  *core_dc = pipe_ctx->stream->ctx->dc;
2335
2336         if (pipe_ctx->stream->signal == SIGNAL_TYPE_DISPLAY_PORT_MST)
2337                 deallocate_mst_payload(pipe_ctx);
2338
2339         core_dc->hwss.blank_stream(pipe_ctx);
2340
2341         core_dc->hwss.disable_stream(pipe_ctx, option);
2342
2343         disable_link(pipe_ctx->stream->sink->link, pipe_ctx->stream->signal);
2344 }
2345
2346 void core_link_set_avmute(struct pipe_ctx *pipe_ctx, bool enable)
2347 {
2348         struct dc  *core_dc = pipe_ctx->stream->ctx->dc;
2349
2350         if (pipe_ctx->stream->signal != SIGNAL_TYPE_HDMI_TYPE_A)
2351                 return;
2352
2353         core_dc->hwss.set_avmute(pipe_ctx, enable);
2354 }
2355
2356 void dc_link_enable_hpd_filter(struct dc_link *link, bool enable)
2357 {
2358         struct gpio *hpd;
2359
2360         if (enable) {
2361                 link->is_hpd_filter_disabled = false;
2362                 program_hpd_filter(link);
2363         } else {
2364                 link->is_hpd_filter_disabled = true;
2365                 /* Obtain HPD handle */
2366                 hpd = get_hpd_gpio(link->ctx->dc_bios, link->link_id, link->ctx->gpio_service);
2367
2368                 if (!hpd)
2369                         return;
2370
2371                 /* Setup HPD filtering */
2372                 if (dal_gpio_open(hpd, GPIO_MODE_INTERRUPT) == GPIO_RESULT_OK) {
2373                         struct gpio_hpd_config config;
2374
2375                         config.delay_on_connect = 0;
2376                         config.delay_on_disconnect = 0;
2377
2378                         dal_irq_setup_hpd_filter(hpd, &config);
2379
2380                         dal_gpio_close(hpd);
2381                 } else {
2382                         ASSERT_CRITICAL(false);
2383                 }
2384                 /* Release HPD handle */
2385                 dal_gpio_destroy_irq(&hpd);
2386         }
2387 }
2388