drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c

   1 /* Copyright 2015 Advanced Micro Devices, Inc. */
   2 #include "dm_services.h"
   3 #include "dc.h"
   4 #include "dc_link_dp.h"
   5 #include "dm_helpers.h"
   6 #include "opp.h"
   7
   8 #include "inc/core_types.h"
   9 #include "link_hwss.h"
  10 #include "dc_link_ddc.h"
  11 #include "core_status.h"
  12 #include "dpcd_defs.h"
  13
  14 #include "resource.h"
  15 #define DC_LOGGER \
  16         link->ctx->logger
  17
  18 /* maximum pre emphasis level allowed for each voltage swing level*/
  19 static const enum dc_pre_emphasis voltage_swing_to_pre_emphasis[] = {
  20                 PRE_EMPHASIS_LEVEL3,
  21                 PRE_EMPHASIS_LEVEL2,
  22                 PRE_EMPHASIS_LEVEL1,
  23                 PRE_EMPHASIS_DISABLED };
  24
  25 enum {
  26         POST_LT_ADJ_REQ_LIMIT = 6,
  27         POST_LT_ADJ_REQ_TIMEOUT = 200
  28 };
  29
  30 enum {
  31         LINK_TRAINING_MAX_RETRY_COUNT = 5,
  32         /* to avoid infinite loop where-in the receiver
  33          * switches between different VS
  34          */
  35         LINK_TRAINING_MAX_CR_RETRY = 100
  36 };
  37
  38 static bool decide_fallback_link_setting(
  39                 struct dc_link_settings initial_link_settings,
  40                 struct dc_link_settings *current_link_setting,
  41                 enum link_training_result training_result);
  42 static struct dc_link_settings get_common_supported_link_settings(
  43                 struct dc_link_settings link_setting_a,
  44                 struct dc_link_settings link_setting_b);
  45
  46 static void wait_for_training_aux_rd_interval(
  47         struct dc_link *link,
  48         uint32_t default_wait_in_micro_secs)
  49 {
  50         union training_aux_rd_interval training_rd_interval;
  51
  52         memset(&training_rd_interval, 0, sizeof(training_rd_interval));
  53
  54         /* overwrite the delay if rev > 1.1*/
  55         if (link->dpcd_caps.dpcd_rev.raw >= DPCD_REV_12) {
  56                 /* DP 1.2 or later - retrieve delay through
  57                  * "DPCD_ADDR_TRAINING_AUX_RD_INTERVAL" register */
  58                 core_link_read_dpcd(
  59                         link,
  60                         DP_TRAINING_AUX_RD_INTERVAL,
  61                         (uint8_t *)&training_rd_interval,
  62                         sizeof(training_rd_interval));
  63
  64                 if (training_rd_interval.bits.TRAINIG_AUX_RD_INTERVAL)
  65                         default_wait_in_micro_secs =
  66                                 training_rd_interval.bits.TRAINIG_AUX_RD_INTERVAL * 4000;
  67         }
  68
  69         udelay(default_wait_in_micro_secs);
  70
  71         DC_LOG_HW_LINK_TRAINING("%s:\n wait = %d\n",
  72                 __func__,
  73                 default_wait_in_micro_secs);
  74 }
  75
  76 static void dpcd_set_training_pattern(
  77         struct dc_link *link,
  78         union dpcd_training_pattern dpcd_pattern)
  79 {
  80         core_link_write_dpcd(
  81                 link,
  82                 DP_TRAINING_PATTERN_SET,
  83                 &dpcd_pattern.raw,
  84                 1);
  85
  86         DC_LOG_HW_LINK_TRAINING("%s\n %x pattern = %x\n",
  87                 __func__,
  88                 DP_TRAINING_PATTERN_SET,
  89                 dpcd_pattern.v1_4.TRAINING_PATTERN_SET);
  90 }
  91
  92 static void dpcd_set_link_settings(
  93         struct dc_link *link,
  94         const struct link_training_settings *lt_settings)
  95 {
  96         uint8_t rate;
  97
  98         union down_spread_ctrl downspread = { {0} };
  99         union lane_count_set lane_count_set = { {0} };
 100
 101         downspread.raw = (uint8_t)
 102         (lt_settings->link_settings.link_spread);
 103
 104         lane_count_set.bits.LANE_COUNT_SET =
 105         lt_settings->link_settings.lane_count;
 106
 107         lane_count_set.bits.ENHANCED_FRAMING = 1;
 108
 109         lane_count_set.bits.POST_LT_ADJ_REQ_GRANTED =
 110                 link->dpcd_caps.max_ln_count.bits.POST_LT_ADJ_REQ_SUPPORTED;
 111
 112         core_link_write_dpcd(link, DP_DOWNSPREAD_CTRL,
 113         &downspread.raw, sizeof(downspread));
 114
 115         core_link_write_dpcd(link, DP_LANE_COUNT_SET,
 116         &lane_count_set.raw, 1);
 117
 118         if (link->dpcd_caps.dpcd_rev.raw >= DPCD_REV_14 &&
 119                         lt_settings->link_settings.use_link_rate_set == true) {
 120                 rate = 0;
 121                 core_link_write_dpcd(link, DP_LINK_BW_SET, &rate, 1);
 122                 core_link_write_dpcd(link, DP_LINK_RATE_SET,
 123                                 &lt_settings->link_settings.link_rate_set, 1);
 124         } else {
 125                 rate = (uint8_t) (lt_settings->link_settings.link_rate);
 126                 core_link_write_dpcd(link, DP_LINK_BW_SET, &rate, 1);
 127         }
 128
 129         if (rate) {
 130                 DC_LOG_HW_LINK_TRAINING("%s\n %x rate = %x\n %x lane = %x\n %x spread = %x\n",
 131                         __func__,
 132                         DP_LINK_BW_SET,
 133                         lt_settings->link_settings.link_rate,
 134                         DP_LANE_COUNT_SET,
 135                         lt_settings->link_settings.lane_count,
 136                         DP_DOWNSPREAD_CTRL,
 137                         lt_settings->link_settings.link_spread);
 138         } else {
 139                 DC_LOG_HW_LINK_TRAINING("%s\n %x rate set = %x\n %x lane = %x\n %x spread = %x\n",
 140                         __func__,
 141                         DP_LINK_RATE_SET,
 142                         lt_settings->link_settings.link_rate_set,
 143                         DP_LANE_COUNT_SET,
 144                         lt_settings->link_settings.lane_count,
 145                         DP_DOWNSPREAD_CTRL,
 146                         lt_settings->link_settings.link_spread);
 147         }
 148
 149 }
 150
 151 static enum dpcd_training_patterns
 152         hw_training_pattern_to_dpcd_training_pattern(
 153         struct dc_link *link,
 154         enum hw_dp_training_pattern pattern)
 155 {
 156         enum dpcd_training_patterns dpcd_tr_pattern =
 157         DPCD_TRAINING_PATTERN_VIDEOIDLE;
 158
 159         switch (pattern) {
 160         case HW_DP_TRAINING_PATTERN_1:
 161                 dpcd_tr_pattern = DPCD_TRAINING_PATTERN_1;
 162                 break;
 163         case HW_DP_TRAINING_PATTERN_2:
 164                 dpcd_tr_pattern = DPCD_TRAINING_PATTERN_2;
 165                 break;
 166         case HW_DP_TRAINING_PATTERN_3:
 167                 dpcd_tr_pattern = DPCD_TRAINING_PATTERN_3;
 168                 break;
 169         case HW_DP_TRAINING_PATTERN_4:
 170                 dpcd_tr_pattern = DPCD_TRAINING_PATTERN_4;
 171                 break;
 172         default:
 173                 ASSERT(0);
 174                 DC_LOG_HW_LINK_TRAINING("%s: Invalid HW Training pattern: %d\n",
 175                         __func__, pattern);
 176                 break;
 177         }
 178
 179         return dpcd_tr_pattern;
 180
 181 }
 182
 183 static void dpcd_set_lt_pattern_and_lane_settings(
 184         struct dc_link *link,
 185         const struct link_training_settings *lt_settings,
 186         enum hw_dp_training_pattern pattern)
 187 {
 188         union dpcd_training_lane dpcd_lane[LANE_COUNT_DP_MAX] = { { {0} } };
 189         const uint32_t dpcd_base_lt_offset =
 190         DP_TRAINING_PATTERN_SET;
 191         uint8_t dpcd_lt_buffer[5] = {0};
 192         union dpcd_training_pattern dpcd_pattern = { {0} };
 193         uint32_t lane;
 194         uint32_t size_in_bytes;
 195         bool edp_workaround = false; /* TODO link_prop.INTERNAL */
 196
 197         /*****************************************************************
 198         * DpcdAddress_TrainingPatternSet
 199         *****************************************************************/
 200         dpcd_pattern.v1_4.TRAINING_PATTERN_SET =
 201                 hw_training_pattern_to_dpcd_training_pattern(link, pattern);
 202
 203         dpcd_lt_buffer[DP_TRAINING_PATTERN_SET - dpcd_base_lt_offset]
 204                 = dpcd_pattern.raw;
 205
 206         DC_LOG_HW_LINK_TRAINING("%s\n %x pattern = %x\n",
 207                 __func__,
 208                 DP_TRAINING_PATTERN_SET,
 209                 dpcd_pattern.v1_4.TRAINING_PATTERN_SET);
 210
 211         /*****************************************************************
 212         * DpcdAddress_Lane0Set -> DpcdAddress_Lane3Set
 213         *****************************************************************/
 214         for (lane = 0; lane <
 215                 (uint32_t)(lt_settings->link_settings.lane_count); lane++) {
 216
 217                 dpcd_lane[lane].bits.VOLTAGE_SWING_SET =
 218                 (uint8_t)(lt_settings->lane_settings[lane].VOLTAGE_SWING);
 219                 dpcd_lane[lane].bits.PRE_EMPHASIS_SET =
 220                 (uint8_t)(lt_settings->lane_settings[lane].PRE_EMPHASIS);
 221
 222                 dpcd_lane[lane].bits.MAX_SWING_REACHED =
 223                 (lt_settings->lane_settings[lane].VOLTAGE_SWING ==
 224                 VOLTAGE_SWING_MAX_LEVEL ? 1 : 0);
 225                 dpcd_lane[lane].bits.MAX_PRE_EMPHASIS_REACHED =
 226                 (lt_settings->lane_settings[lane].PRE_EMPHASIS ==
 227                 PRE_EMPHASIS_MAX_LEVEL ? 1 : 0);
 228         }
 229
 230         /* concatinate everything into one buffer*/
 231
 232         size_in_bytes = lt_settings->link_settings.lane_count * sizeof(dpcd_lane[0]);
 233
 234          // 0x00103 - 0x00102
 235         memmove(
 236                 &dpcd_lt_buffer[DP_TRAINING_LANE0_SET - dpcd_base_lt_offset],
 237                 dpcd_lane,
 238                 size_in_bytes);
 239
 240         DC_LOG_HW_LINK_TRAINING("%s:\n %x VS set = %x  PE set = %x max VS Reached = %x  max PE Reached = %x\n",
 241                 __func__,
 242                 DP_TRAINING_LANE0_SET,
 243                 dpcd_lane[0].bits.VOLTAGE_SWING_SET,
 244                 dpcd_lane[0].bits.PRE_EMPHASIS_SET,
 245                 dpcd_lane[0].bits.MAX_SWING_REACHED,
 246                 dpcd_lane[0].bits.MAX_PRE_EMPHASIS_REACHED);
 247
 248         if (edp_workaround) {
 249                 /* for eDP write in 2 parts because the 5-byte burst is
 250                 * causing issues on some eDP panels (EPR#366724)
 251                 */
 252                 core_link_write_dpcd(
 253                         link,
 254                         DP_TRAINING_PATTERN_SET,
 255                         &dpcd_pattern.raw,
 256                         sizeof(dpcd_pattern.raw));
 257
 258                 core_link_write_dpcd(
 259                         link,
 260                         DP_TRAINING_LANE0_SET,
 261                         (uint8_t *)(dpcd_lane),
 262                         size_in_bytes);
 263
 264                 } else
 265                 /* write it all in (1 + number-of-lanes)-byte burst*/
 266                         core_link_write_dpcd(
 267                                 link,
 268                                 dpcd_base_lt_offset,
 269                                 dpcd_lt_buffer,
 270                                 size_in_bytes + sizeof(dpcd_pattern.raw));
 271
 272         link->cur_lane_setting = lt_settings->lane_settings[0];
 273 }
 274
 275 static bool is_cr_done(enum dc_lane_count ln_count,
 276         union lane_status *dpcd_lane_status)
 277 {
 278         bool done = true;
 279         uint32_t lane;
 280         /*LANEx_CR_DONE bits All 1's?*/
 281         for (lane = 0; lane < (uint32_t)(ln_count); lane++) {
 282                 if (!dpcd_lane_status[lane].bits.CR_DONE_0)
 283                         done = false;
 284         }
 285         return done;
 286
 287 }
 288
 289 static bool is_ch_eq_done(enum dc_lane_count ln_count,
 290         union lane_status *dpcd_lane_status,
 291         union lane_align_status_updated *lane_status_updated)
 292 {
 293         bool done = true;
 294         uint32_t lane;
 295         if (!lane_status_updated->bits.INTERLANE_ALIGN_DONE)
 296                 done = false;
 297         else {
 298                 for (lane = 0; lane < (uint32_t)(ln_count); lane++) {
 299                         if (!dpcd_lane_status[lane].bits.SYMBOL_LOCKED_0 ||
 300                                 !dpcd_lane_status[lane].bits.CHANNEL_EQ_DONE_0)
 301                                 done = false;
 302                 }
 303         }
 304         return done;
 305
 306 }
 307
 308 static void update_drive_settings(
 309                 struct link_training_settings *dest,
 310                 struct link_training_settings src)
 311 {
 312         uint32_t lane;
 313         for (lane = 0; lane < src.link_settings.lane_count; lane++) {
 314                 dest->lane_settings[lane].VOLTAGE_SWING =
 315                         src.lane_settings[lane].VOLTAGE_SWING;
 316                 dest->lane_settings[lane].PRE_EMPHASIS =
 317                         src.lane_settings[lane].PRE_EMPHASIS;
 318                 dest->lane_settings[lane].POST_CURSOR2 =
 319                         src.lane_settings[lane].POST_CURSOR2;
 320         }
 321 }
 322
 323 static uint8_t get_nibble_at_index(const uint8_t *buf,
 324         uint32_t index)
 325 {
 326         uint8_t nibble;
 327         nibble = buf[index / 2];
 328
 329         if (index % 2)
 330                 nibble >>= 4;
 331         else
 332                 nibble &= 0x0F;
 333
 334         return nibble;
 335 }
 336
 337 static enum dc_pre_emphasis get_max_pre_emphasis_for_voltage_swing(
 338         enum dc_voltage_swing voltage)
 339 {
 340         enum dc_pre_emphasis pre_emphasis;
 341         pre_emphasis = PRE_EMPHASIS_MAX_LEVEL;
 342
 343         if (voltage <= VOLTAGE_SWING_MAX_LEVEL)
 344                 pre_emphasis = voltage_swing_to_pre_emphasis[voltage];
 345
 346         return pre_emphasis;
 347
 348 }
 349
 350 static void find_max_drive_settings(
 351         const struct link_training_settings *link_training_setting,
 352         struct link_training_settings *max_lt_setting)
 353 {
 354         uint32_t lane;
 355         struct dc_lane_settings max_requested;
 356
 357         max_requested.VOLTAGE_SWING =
 358                 link_training_setting->
 359                 lane_settings[0].VOLTAGE_SWING;
 360         max_requested.PRE_EMPHASIS =
 361                 link_training_setting->
 362                 lane_settings[0].PRE_EMPHASIS;
 363         /*max_requested.postCursor2 =
 364          * link_training_setting->laneSettings[0].postCursor2;*/
 365
 366         /* Determine what the maximum of the requested settings are*/
 367         for (lane = 1; lane < link_training_setting->link_settings.lane_count;
 368                         lane++) {
 369                 if (link_training_setting->lane_settings[lane].VOLTAGE_SWING >
 370                         max_requested.VOLTAGE_SWING)
 371
 372                         max_requested.VOLTAGE_SWING =
 373                         link_training_setting->
 374                         lane_settings[lane].VOLTAGE_SWING;
 375
 376                 if (link_training_setting->lane_settings[lane].PRE_EMPHASIS >
 377                                 max_requested.PRE_EMPHASIS)
 378                         max_requested.PRE_EMPHASIS =
 379                         link_training_setting->
 380                         lane_settings[lane].PRE_EMPHASIS;
 381
 382                 /*
 383                 if (link_training_setting->laneSettings[lane].postCursor2 >
 384                  max_requested.postCursor2)
 385                 {
 386                 max_requested.postCursor2 =
 387                 link_training_setting->laneSettings[lane].postCursor2;
 388                 }
 389                 */
 390         }
 391
 392         /* make sure the requested settings are
 393          * not higher than maximum settings*/
 394         if (max_requested.VOLTAGE_SWING > VOLTAGE_SWING_MAX_LEVEL)
 395                 max_requested.VOLTAGE_SWING = VOLTAGE_SWING_MAX_LEVEL;
 396
 397         if (max_requested.PRE_EMPHASIS > PRE_EMPHASIS_MAX_LEVEL)
 398                 max_requested.PRE_EMPHASIS = PRE_EMPHASIS_MAX_LEVEL;
 399         /*
 400         if (max_requested.postCursor2 > PostCursor2_MaxLevel)
 401         max_requested.postCursor2 = PostCursor2_MaxLevel;
 402         */
 403
 404         /* make sure the pre-emphasis matches the voltage swing*/
 405         if (max_requested.PRE_EMPHASIS >
 406                 get_max_pre_emphasis_for_voltage_swing(
 407                         max_requested.VOLTAGE_SWING))
 408                 max_requested.PRE_EMPHASIS =
 409                 get_max_pre_emphasis_for_voltage_swing(
 410                         max_requested.VOLTAGE_SWING);
 411
 412         /*
 413          * Post Cursor2 levels are completely independent from
 414          * pre-emphasis (Post Cursor1) levels. But Post Cursor2 levels
 415          * can only be applied to each allowable combination of voltage
 416          * swing and pre-emphasis levels */
 417          /* if ( max_requested.postCursor2 >
 418           *  getMaxPostCursor2ForVoltageSwing(max_requested.voltageSwing))
 419           *  max_requested.postCursor2 =
 420           *  getMaxPostCursor2ForVoltageSwing(max_requested.voltageSwing);
 421           */
 422
 423         max_lt_setting->link_settings.link_rate =
 424                 link_training_setting->link_settings.link_rate;
 425         max_lt_setting->link_settings.lane_count =
 426         link_training_setting->link_settings.lane_count;
 427         max_lt_setting->link_settings.link_spread =
 428                 link_training_setting->link_settings.link_spread;
 429
 430         for (lane = 0; lane <
 431                 link_training_setting->link_settings.lane_count;
 432                 lane++) {
 433                 max_lt_setting->lane_settings[lane].VOLTAGE_SWING =
 434                         max_requested.VOLTAGE_SWING;
 435                 max_lt_setting->lane_settings[lane].PRE_EMPHASIS =
 436                         max_requested.PRE_EMPHASIS;
 437                 /*max_lt_setting->laneSettings[lane].postCursor2 =
 438                  * max_requested.postCursor2;
 439                  */
 440         }
 441
 442 }
 443
 444 static void get_lane_status_and_drive_settings(
 445         struct dc_link *link,
 446         const struct link_training_settings *link_training_setting,
 447         union lane_status *ln_status,
 448         union lane_align_status_updated *ln_status_updated,
 449         struct link_training_settings *req_settings)
 450 {
 451         uint8_t dpcd_buf[6] = {0};
 452         union lane_adjust dpcd_lane_adjust[LANE_COUNT_DP_MAX] = { { {0} } };
 453         struct link_training_settings request_settings = { {0} };
 454         uint32_t lane;
 455
 456         memset(req_settings, '\0', sizeof(struct link_training_settings));
 457
 458         core_link_read_dpcd(
 459                 link,
 460                 DP_LANE0_1_STATUS,
 461                 (uint8_t *)(dpcd_buf),
 462                 sizeof(dpcd_buf));
 463
 464         for (lane = 0; lane <
 465                 (uint32_t)(link_training_setting->link_settings.lane_count);
 466                 lane++) {
 467
 468                 ln_status[lane].raw =
 469                         get_nibble_at_index(&dpcd_buf[0], lane);
 470                 dpcd_lane_adjust[lane].raw =
 471                         get_nibble_at_index(&dpcd_buf[4], lane);
 472         }
 473
 474         ln_status_updated->raw = dpcd_buf[2];
 475
 476         DC_LOG_HW_LINK_TRAINING("%s:\n%x Lane01Status = %x\n %x Lane23Status = %x\n ",
 477                 __func__,
 478                 DP_LANE0_1_STATUS, dpcd_buf[0],
 479                 DP_LANE2_3_STATUS, dpcd_buf[1]);
 480
 481         DC_LOG_HW_LINK_TRAINING("%s:\n %x Lane01AdjustRequest = %x\n %x Lane23AdjustRequest = %x\n",
 482                 __func__,
 483                 DP_ADJUST_REQUEST_LANE0_1,
 484                 dpcd_buf[4],
 485                 DP_ADJUST_REQUEST_LANE2_3,
 486                 dpcd_buf[5]);
 487
 488         /*copy to req_settings*/
 489         request_settings.link_settings.lane_count =
 490                 link_training_setting->link_settings.lane_count;
 491         request_settings.link_settings.link_rate =
 492                 link_training_setting->link_settings.link_rate;
 493         request_settings.link_settings.link_spread =
 494                 link_training_setting->link_settings.link_spread;
 495
 496         for (lane = 0; lane <
 497                 (uint32_t)(link_training_setting->link_settings.lane_count);
 498                 lane++) {
 499
 500                 request_settings.lane_settings[lane].VOLTAGE_SWING =
 501                         (enum dc_voltage_swing)(dpcd_lane_adjust[lane].bits.
 502                                 VOLTAGE_SWING_LANE);
 503                 request_settings.lane_settings[lane].PRE_EMPHASIS =
 504                         (enum dc_pre_emphasis)(dpcd_lane_adjust[lane].bits.
 505                                 PRE_EMPHASIS_LANE);
 506         }
 507
 508         /*Note: for postcursor2, read adjusted
 509          * postcursor2 settings from*/
 510         /*DpcdAddress_AdjustRequestPostCursor2 =
 511          *0x020C (not implemented yet)*/
 512
 513         /* we find the maximum of the requested settings across all lanes*/
 514         /* and set this maximum for all lanes*/
 515         find_max_drive_settings(&request_settings, req_settings);
 516
 517         /* if post cursor 2 is needed in the future,
 518          * read DpcdAddress_AdjustRequestPostCursor2 = 0x020C
 519          */
 520
 521 }
 522
 523 static void dpcd_set_lane_settings(
 524         struct dc_link *link,
 525         const struct link_training_settings *link_training_setting)
 526 {
 527         union dpcd_training_lane dpcd_lane[LANE_COUNT_DP_MAX] = {{{0}}};
 528         uint32_t lane;
 529
 530         for (lane = 0; lane <
 531                 (uint32_t)(link_training_setting->
 532                 link_settings.lane_count);
 533                 lane++) {
 534                 dpcd_lane[lane].bits.VOLTAGE_SWING_SET =
 535                         (uint8_t)(link_training_setting->
 536                         lane_settings[lane].VOLTAGE_SWING);
 537                 dpcd_lane[lane].bits.PRE_EMPHASIS_SET =
 538                         (uint8_t)(link_training_setting->
 539                         lane_settings[lane].PRE_EMPHASIS);
 540                 dpcd_lane[lane].bits.MAX_SWING_REACHED =
 541                         (link_training_setting->
 542                         lane_settings[lane].VOLTAGE_SWING ==
 543                         VOLTAGE_SWING_MAX_LEVEL ? 1 : 0);
 544                 dpcd_lane[lane].bits.MAX_PRE_EMPHASIS_REACHED =
 545                         (link_training_setting->
 546                         lane_settings[lane].PRE_EMPHASIS ==
 547                         PRE_EMPHASIS_MAX_LEVEL ? 1 : 0);
 548         }
 549
 550         core_link_write_dpcd(link,
 551                 DP_TRAINING_LANE0_SET,
 552                 (uint8_t *)(dpcd_lane),
 553                 link_training_setting->link_settings.lane_count);
 554
 555         /*
 556         if (LTSettings.link.rate == LinkRate_High2)
 557         {
 558                 DpcdTrainingLaneSet2 dpcd_lane2[lane_count_DPMax] = {0};
 559                 for ( uint32_t lane = 0;
 560                 lane < lane_count_DPMax; lane++)
 561                 {
 562                         dpcd_lane2[lane].bits.post_cursor2_set =
 563                         static_cast<unsigned char>(
 564                         LTSettings.laneSettings[lane].postCursor2);
 565                         dpcd_lane2[lane].bits.max_post_cursor2_reached = 0;
 566                 }
 567                 m_pDpcdAccessSrv->WriteDpcdData(
 568                 DpcdAddress_Lane0Set2,
 569                 reinterpret_cast<unsigned char*>(dpcd_lane2),
 570                 LTSettings.link.lanes);
 571         }
 572         */
 573
 574         DC_LOG_HW_LINK_TRAINING("%s\n %x VS set = %x  PE set = %x max VS Reached = %x  max PE Reached = %x\n",
 575                 __func__,
 576                 DP_TRAINING_LANE0_SET,
 577                 dpcd_lane[0].bits.VOLTAGE_SWING_SET,
 578                 dpcd_lane[0].bits.PRE_EMPHASIS_SET,
 579                 dpcd_lane[0].bits.MAX_SWING_REACHED,
 580                 dpcd_lane[0].bits.MAX_PRE_EMPHASIS_REACHED);
 581
 582         link->cur_lane_setting = link_training_setting->lane_settings[0];
 583
 584 }
 585
 586 static bool is_max_vs_reached(
 587         const struct link_training_settings *lt_settings)
 588 {
 589         uint32_t lane;
 590         for (lane = 0; lane <
 591                 (uint32_t)(lt_settings->link_settings.lane_count);
 592                 lane++) {
 593                 if (lt_settings->lane_settings[lane].VOLTAGE_SWING
 594                         == VOLTAGE_SWING_MAX_LEVEL)
 595                         return true;
 596         }
 597         return false;
 598
 599 }
 600
 601 void dc_link_dp_set_drive_settings(
 602         struct dc_link *link,
 603         struct link_training_settings *lt_settings)
 604 {
 605         /* program ASIC PHY settings*/
 606         dp_set_hw_lane_settings(link, lt_settings);
 607
 608         /* Notify DP sink the PHY settings from source */
 609         dpcd_set_lane_settings(link, lt_settings);
 610 }
 611
 612 static bool perform_post_lt_adj_req_sequence(
 613         struct dc_link *link,
 614         struct link_training_settings *lt_settings)
 615 {
 616         enum dc_lane_count lane_count =
 617         lt_settings->link_settings.lane_count;
 618
 619         uint32_t adj_req_count;
 620         uint32_t adj_req_timer;
 621         bool req_drv_setting_changed;
 622         uint32_t lane;
 623
 624         req_drv_setting_changed = false;
 625         for (adj_req_count = 0; adj_req_count < POST_LT_ADJ_REQ_LIMIT;
 626         adj_req_count++) {
 627
 628                 req_drv_setting_changed = false;
 629
 630                 for (adj_req_timer = 0;
 631                         adj_req_timer < POST_LT_ADJ_REQ_TIMEOUT;
 632                         adj_req_timer++) {
 633
 634                         struct link_training_settings req_settings;
 635                         union lane_status dpcd_lane_status[LANE_COUNT_DP_MAX];
 636                         union lane_align_status_updated
 637                                 dpcd_lane_status_updated;
 638
 639                         get_lane_status_and_drive_settings(
 640                         link,
 641                         lt_settings,
 642                         dpcd_lane_status,
 643                         &dpcd_lane_status_updated,
 644                         &req_settings);
 645
 646                         if (dpcd_lane_status_updated.bits.
 647                                         POST_LT_ADJ_REQ_IN_PROGRESS == 0)
 648                                 return true;
 649
 650                         if (!is_cr_done(lane_count, dpcd_lane_status))
 651                                 return false;
 652
 653                         if (!is_ch_eq_done(
 654                                 lane_count,
 655                                 dpcd_lane_status,
 656                                 &dpcd_lane_status_updated))
 657                                 return false;
 658
 659                         for (lane = 0; lane < (uint32_t)(lane_count); lane++) {
 660
 661                                 if (lt_settings->
 662                                 lane_settings[lane].VOLTAGE_SWING !=
 663                                 req_settings.lane_settings[lane].
 664                                 VOLTAGE_SWING ||
 665                                 lt_settings->lane_settings[lane].PRE_EMPHASIS !=
 666                                 req_settings.lane_settings[lane].PRE_EMPHASIS) {
 667
 668                                         req_drv_setting_changed = true;
 669                                         break;
 670                                 }
 671                         }
 672
 673                         if (req_drv_setting_changed) {
 674                                 update_drive_settings(
 675                                         lt_settings, req_settings);
 676
 677                                 dc_link_dp_set_drive_settings(link,
 678                                                 lt_settings);
 679                                 break;
 680                         }
 681
 682                         msleep(1);
 683                 }
 684
 685                 if (!req_drv_setting_changed) {
 686                         DC_LOG_WARNING("%s: Post Link Training Adjust Request Timed out\n",
 687                                 __func__);
 688
 689                         ASSERT(0);
 690                         return true;
 691                 }
 692         }
 693         DC_LOG_WARNING("%s: Post Link Training Adjust Request limit reached\n",
 694                 __func__);
 695
 696         ASSERT(0);
 697         return true;
 698
 699 }
 700
 701 static enum hw_dp_training_pattern get_supported_tp(struct dc_link *link)
 702 {
 703         enum hw_dp_training_pattern highest_tp = HW_DP_TRAINING_PATTERN_2;
 704         struct encoder_feature_support *features = &link->link_enc->features;
 705         struct dpcd_caps *dpcd_caps = &link->dpcd_caps;
 706
 707         if (features->flags.bits.IS_TPS3_CAPABLE)
 708                 highest_tp = HW_DP_TRAINING_PATTERN_3;
 709
 710         if (features->flags.bits.IS_TPS4_CAPABLE)
 711                 highest_tp = HW_DP_TRAINING_PATTERN_4;
 712
 713         if (dpcd_caps->max_down_spread.bits.TPS4_SUPPORTED &&
 714                 highest_tp >= HW_DP_TRAINING_PATTERN_4)
 715                 return HW_DP_TRAINING_PATTERN_4;
 716
 717         if (dpcd_caps->max_ln_count.bits.TPS3_SUPPORTED &&
 718                 highest_tp >= HW_DP_TRAINING_PATTERN_3)
 719                 return HW_DP_TRAINING_PATTERN_3;
 720
 721         return HW_DP_TRAINING_PATTERN_2;
 722 }
 723
 724 static enum link_training_result get_cr_failure(enum dc_lane_count ln_count,
 725                                         union lane_status *dpcd_lane_status)
 726 {
 727         enum link_training_result result = LINK_TRAINING_SUCCESS;
 728
 729         if (ln_count >= LANE_COUNT_ONE && !dpcd_lane_status[0].bits.CR_DONE_0)
 730                 result = LINK_TRAINING_CR_FAIL_LANE0;
 731         else if (ln_count >= LANE_COUNT_TWO && !dpcd_lane_status[1].bits.CR_DONE_0)
 732                 result = LINK_TRAINING_CR_FAIL_LANE1;
 733         else if (ln_count >= LANE_COUNT_FOUR && !dpcd_lane_status[2].bits.CR_DONE_0)
 734                 result = LINK_TRAINING_CR_FAIL_LANE23;
 735         else if (ln_count >= LANE_COUNT_FOUR && !dpcd_lane_status[3].bits.CR_DONE_0)
 736                 result = LINK_TRAINING_CR_FAIL_LANE23;
 737         return result;
 738 }
 739
 740 static enum link_training_result perform_channel_equalization_sequence(
 741         struct dc_link *link,
 742         struct link_training_settings *lt_settings)
 743 {
 744         struct link_training_settings req_settings;
 745         enum hw_dp_training_pattern hw_tr_pattern;
 746         uint32_t retries_ch_eq;
 747         enum dc_lane_count lane_count = lt_settings->link_settings.lane_count;
 748         union lane_align_status_updated dpcd_lane_status_updated = { {0} };
 749         union lane_status dpcd_lane_status[LANE_COUNT_DP_MAX] = { { {0} } };
 750
 751         hw_tr_pattern = get_supported_tp(link);
 752
 753         dp_set_hw_training_pattern(link, hw_tr_pattern);
 754
 755         for (retries_ch_eq = 0; retries_ch_eq <= LINK_TRAINING_MAX_RETRY_COUNT;
 756                 retries_ch_eq++) {
 757
 758                 dp_set_hw_lane_settings(link, lt_settings);
 759
 760                 /* 2. update DPCD*/
 761                 if (!retries_ch_eq)
 762                         /* EPR #361076 - write as a 5-byte burst,
 763                          * but only for the 1-st iteration*/
 764                         dpcd_set_lt_pattern_and_lane_settings(
 765                                 link,
 766                                 lt_settings,
 767                                 hw_tr_pattern);
 768                 else
 769                         dpcd_set_lane_settings(link, lt_settings);
 770
 771                 /* 3. wait for receiver to lock-on*/
 772                 wait_for_training_aux_rd_interval(link, 400);
 773
 774                 /* 4. Read lane status and requested
 775                  * drive settings as set by the sink*/
 776
 777                 get_lane_status_and_drive_settings(
 778                         link,
 779                         lt_settings,
 780                         dpcd_lane_status,
 781                         &dpcd_lane_status_updated,
 782                         &req_settings);
 783
 784                 /* 5. check CR done*/
 785                 if (!is_cr_done(lane_count, dpcd_lane_status))
 786                         return LINK_TRAINING_EQ_FAIL_CR;
 787
 788                 /* 6. check CHEQ done*/
 789                 if (is_ch_eq_done(lane_count,
 790                         dpcd_lane_status,
 791                         &dpcd_lane_status_updated))
 792                         return LINK_TRAINING_SUCCESS;
 793
 794                 /* 7. update VS/PE/PC2 in lt_settings*/
 795                 update_drive_settings(lt_settings, req_settings);
 796         }
 797
 798         return LINK_TRAINING_EQ_FAIL_EQ;
 799
 800 }
 801
 802 static enum link_training_result perform_clock_recovery_sequence(
 803         struct dc_link *link,
 804         struct link_training_settings *lt_settings)
 805 {
 806         uint32_t retries_cr;
 807         uint32_t retry_count;
 808         uint32_t lane;
 809         struct link_training_settings req_settings;
 810         enum dc_lane_count lane_count =
 811         lt_settings->link_settings.lane_count;
 812         enum hw_dp_training_pattern hw_tr_pattern = HW_DP_TRAINING_PATTERN_1;
 813         union lane_status dpcd_lane_status[LANE_COUNT_DP_MAX];
 814         union lane_align_status_updated dpcd_lane_status_updated;
 815
 816         retries_cr = 0;
 817         retry_count = 0;
 818         /* initial drive setting (VS/PE/PC2)*/
 819         for (lane = 0; lane < LANE_COUNT_DP_MAX; lane++) {
 820                 lt_settings->lane_settings[lane].VOLTAGE_SWING =
 821                 VOLTAGE_SWING_LEVEL0;
 822                 lt_settings->lane_settings[lane].PRE_EMPHASIS =
 823                 PRE_EMPHASIS_DISABLED;
 824                 lt_settings->lane_settings[lane].POST_CURSOR2 =
 825                 POST_CURSOR2_DISABLED;
 826         }
 827
 828         dp_set_hw_training_pattern(link, hw_tr_pattern);
 829
 830         /* najeeb - The synaptics MST hub can put the LT in
 831         * infinite loop by switching the VS
 832         */
 833         /* between level 0 and level 1 continuously, here
 834         * we try for CR lock for LinkTrainingMaxCRRetry count*/
 835         while ((retries_cr < LINK_TRAINING_MAX_RETRY_COUNT) &&
 836         (retry_count < LINK_TRAINING_MAX_CR_RETRY)) {
 837
 838                 memset(&dpcd_lane_status, '\0', sizeof(dpcd_lane_status));
 839                 memset(&dpcd_lane_status_updated, '\0',
 840                 sizeof(dpcd_lane_status_updated));
 841
 842                 /* 1. call HWSS to set lane settings*/
 843                 dp_set_hw_lane_settings(
 844                                 link,
 845                                 lt_settings);
 846
 847                 /* 2. update DPCD of the receiver*/
 848                 if (!retries_cr)
 849                         /* EPR #361076 - write as a 5-byte burst,
 850                          * but only for the 1-st iteration.*/
 851                         dpcd_set_lt_pattern_and_lane_settings(
 852                                         link,
 853                                         lt_settings,
 854                                         hw_tr_pattern);
 855                 else
 856                         dpcd_set_lane_settings(
 857                                         link,
 858                                         lt_settings);
 859
 860                 /* 3. wait receiver to lock-on*/
 861                 wait_for_training_aux_rd_interval(
 862                                 link,
 863                                 100);
 864
 865                 /* 4. Read lane status and requested drive
 866                 * settings as set by the sink
 867                 */
 868                 get_lane_status_and_drive_settings(
 869                                 link,
 870                                 lt_settings,
 871                                 dpcd_lane_status,
 872                                 &dpcd_lane_status_updated,
 873                                 &req_settings);
 874
 875                 /* 5. check CR done*/
 876                 if (is_cr_done(lane_count, dpcd_lane_status))
 877                         return LINK_TRAINING_SUCCESS;
 878
 879                 /* 6. max VS reached*/
 880                 if (is_max_vs_reached(lt_settings))
 881                         break;
 882
 883                 /* 7. same voltage*/
 884                 /* Note: VS same for all lanes,
 885                 * so comparing first lane is sufficient*/
 886                 if (lt_settings->lane_settings[0].VOLTAGE_SWING ==
 887                         req_settings.lane_settings[0].VOLTAGE_SWING)
 888                         retries_cr++;
 889                 else
 890                         retries_cr = 0;
 891
 892                 /* 8. update VS/PE/PC2 in lt_settings*/
 893                 update_drive_settings(lt_settings, req_settings);
 894
 895                 retry_count++;
 896         }
 897
 898         if (retry_count >= LINK_TRAINING_MAX_CR_RETRY) {
 899                 ASSERT(0);
 900                 DC_LOG_ERROR("%s: Link Training Error, could not get CR after %d tries. Possibly voltage swing issue",
 901                         __func__,
 902                         LINK_TRAINING_MAX_CR_RETRY);
 903
 904         }
 905
 906         return get_cr_failure(lane_count, dpcd_lane_status);
 907 }
 908
 909 static inline enum link_training_result perform_link_training_int(
 910         struct dc_link *link,
 911         struct link_training_settings *lt_settings,
 912         enum link_training_result status)
 913 {
 914         union lane_count_set lane_count_set = { {0} };
 915         union dpcd_training_pattern dpcd_pattern = { {0} };
 916
 917         /* 3. set training not in progress*/
 918         dpcd_pattern.v1_4.TRAINING_PATTERN_SET = DPCD_TRAINING_PATTERN_VIDEOIDLE;
 919         dpcd_set_training_pattern(link, dpcd_pattern);
 920
 921         /* 4. mainlink output idle pattern*/
 922         dp_set_hw_test_pattern(link, DP_TEST_PATTERN_VIDEO_MODE, NULL, 0);
 923
 924         /*
 925          * 5. post training adjust if required
 926          * If the upstream DPTX and downstream DPRX both support TPS4,
 927          * TPS4 must be used instead of POST_LT_ADJ_REQ.
 928          */
 929         if (link->dpcd_caps.max_ln_count.bits.POST_LT_ADJ_REQ_SUPPORTED != 1 ||
 930                         get_supported_tp(link) == HW_DP_TRAINING_PATTERN_4)
 931                 return status;
 932
 933         if (status == LINK_TRAINING_SUCCESS &&
 934                 perform_post_lt_adj_req_sequence(link, lt_settings) == false)
 935                 status = LINK_TRAINING_LQA_FAIL;
 936
 937         lane_count_set.bits.LANE_COUNT_SET = lt_settings->link_settings.lane_count;
 938         lane_count_set.bits.ENHANCED_FRAMING = 1;
 939         lane_count_set.bits.POST_LT_ADJ_REQ_GRANTED = 0;
 940
 941         core_link_write_dpcd(
 942                 link,
 943                 DP_LANE_COUNT_SET,
 944                 &lane_count_set.raw,
 945                 sizeof(lane_count_set));
 946
 947         return status;
 948 }
 949
 950 enum link_training_result dc_link_dp_perform_link_training(
 951         struct dc_link *link,
 952         const struct dc_link_settings *link_setting,
 953         bool skip_video_pattern)
 954 {
 955         enum link_training_result status = LINK_TRAINING_SUCCESS;
 956
 957         char *link_rate = "Unknown";
 958         char *lt_result = "Unknown";
 959
 960         struct link_training_settings lt_settings;
 961
 962         memset(&lt_settings, '\0', sizeof(lt_settings));
 963
 964         lt_settings.link_settings.link_rate = link_setting->link_rate;
 965         lt_settings.link_settings.lane_count = link_setting->lane_count;
 966         lt_settings.link_settings.use_link_rate_set = link_setting->use_link_rate_set;
 967         lt_settings.link_settings.link_rate_set = link_setting->link_rate_set;
 968
 969         /*@todo[vdevulap] move SS to LS, should not be handled by displaypath*/
 970
 971         /* TODO hard coded to SS for now
 972          * lt_settings.link_settings.link_spread =
 973          * dal_display_path_is_ss_supported(
 974          * path_mode->display_path) ?
 975          * LINK_SPREAD_05_DOWNSPREAD_30KHZ :
 976          * LINK_SPREAD_DISABLED;
 977          */
 978         if (link->dp_ss_off)
 979                 lt_settings.link_settings.link_spread = LINK_SPREAD_DISABLED;
 980         else
 981                 lt_settings.link_settings.link_spread = LINK_SPREAD_05_DOWNSPREAD_30KHZ;
 982
 983         /* 1. set link rate, lane count and spread*/
 984         dpcd_set_link_settings(link, &lt_settings);
 985
 986         /* 2. perform link training (set link training done
 987          *  to false is done as well)*/
 988         status = perform_clock_recovery_sequence(link, &lt_settings);
 989         if (status == LINK_TRAINING_SUCCESS) {
 990                 status = perform_channel_equalization_sequence(link,
 991                                 &lt_settings);
 992         }
 993
 994         if ((status == LINK_TRAINING_SUCCESS) || !skip_video_pattern) {
 995                 status = perform_link_training_int(link,
 996                                 &lt_settings,
 997                                 status);
 998         }
 999
1000         /* 6. print status message*/
1001         switch (lt_settings.link_settings.link_rate) {
1002
1003         case LINK_RATE_LOW:
1004                 link_rate = "RBR";
1005                 break;
1006         case LINK_RATE_HIGH:
1007                 link_rate = "HBR";
1008                 break;
1009         case LINK_RATE_HIGH2:
1010                 link_rate = "HBR2";
1011                 break;
1012         case LINK_RATE_RBR2:
1013                 link_rate = "RBR2";
1014                 break;
1015         case LINK_RATE_HIGH3:
1016                 link_rate = "HBR3";
1017                 break;
1018         default:
1019                 break;
1020         }
1021
1022         switch (status) {
1023         case LINK_TRAINING_SUCCESS:
1024                 lt_result = "pass";
1025                 break;
1026         case LINK_TRAINING_CR_FAIL_LANE0:
1027                 lt_result = "CR failed lane0";
1028                 break;
1029         case LINK_TRAINING_CR_FAIL_LANE1:
1030                 lt_result = "CR failed lane1";
1031                 break;
1032         case LINK_TRAINING_CR_FAIL_LANE23:
1033                 lt_result = "CR failed lane23";
1034                 break;
1035         case LINK_TRAINING_EQ_FAIL_CR:
1036                 lt_result = "CR failed in EQ";
1037                 break;
1038         case LINK_TRAINING_EQ_FAIL_EQ:
1039                 lt_result = "EQ failed";
1040                 break;
1041         case LINK_TRAINING_LQA_FAIL:
1042                 lt_result = "LQA failed";
1043                 break;
1044         default:
1045                 break;
1046         }
1047
1048         /* Connectivity log: link training */
1049         CONN_MSG_LT(link, "%sx%d %s VS=%d, PE=%d",
1050                         link_rate,
1051                         lt_settings.link_settings.lane_count,
1052                         lt_result,
1053                         lt_settings.lane_settings[0].VOLTAGE_SWING,
1054                         lt_settings.lane_settings[0].PRE_EMPHASIS);
1055
1056         if (status != LINK_TRAINING_SUCCESS)
1057                 link->ctx->dc->debug_data.ltFailCount++;
1058
1059         return status;
1060 }
1061
1062
1063 bool perform_link_training_with_retries(
1064         struct dc_link *link,
1065         const struct dc_link_settings *link_setting,
1066         bool skip_video_pattern,
1067         int attempts)
1068 {
1069         uint8_t j;
1070         uint8_t delay_between_attempts = LINK_TRAINING_RETRY_DELAY;
1071
1072         for (j = 0; j < attempts; ++j) {
1073
1074                 if (dc_link_dp_perform_link_training(
1075                                 link,
1076                                 link_setting,
1077                                 skip_video_pattern) == LINK_TRAINING_SUCCESS)
1078                         return true;
1079
1080                 msleep(delay_between_attempts);
1081                 delay_between_attempts += LINK_TRAINING_RETRY_DELAY;
1082         }
1083
1084         return false;
1085 }
1086
1087 static struct dc_link_settings get_max_link_cap(struct dc_link *link)
1088 {
1089         /* Set Default link settings */
1090         struct dc_link_settings max_link_cap = {LANE_COUNT_FOUR, LINK_RATE_HIGH,
1091                         LINK_SPREAD_05_DOWNSPREAD_30KHZ, false, 0};
1092
1093         /* Higher link settings based on feature supported */
1094         if (link->link_enc->features.flags.bits.IS_HBR2_CAPABLE)
1095                 max_link_cap.link_rate = LINK_RATE_HIGH2;
1096
1097         if (link->link_enc->features.flags.bits.IS_HBR3_CAPABLE)
1098                 max_link_cap.link_rate = LINK_RATE_HIGH3;
1099
1100         /* Lower link settings based on sink's link cap */
1101         if (link->reported_link_cap.lane_count < max_link_cap.lane_count)
1102                 max_link_cap.lane_count =
1103                                 link->reported_link_cap.lane_count;
1104         if (link->reported_link_cap.link_rate < max_link_cap.link_rate)
1105                 max_link_cap.link_rate =
1106                                 link->reported_link_cap.link_rate;
1107         if (link->reported_link_cap.link_spread <
1108                         max_link_cap.link_spread)
1109                 max_link_cap.link_spread =
1110                                 link->reported_link_cap.link_spread;
1111         return max_link_cap;
1112 }
1113
1114 static enum dc_status read_hpd_rx_irq_data(
1115         struct dc_link *link,
1116         union hpd_irq_data *irq_data)
1117 {
1118         static enum dc_status retval;
1119
1120         /* The HW reads 16 bytes from 200h on HPD,
1121          * but if we get an AUX_DEFER, the HW cannot retry
1122          * and this causes the CTS tests 4.3.2.1 - 3.2.4 to
1123          * fail, so we now explicitly read 6 bytes which is
1124          * the req from the above mentioned test cases.
1125          *
1126          * For DP 1.4 we need to read those from 2002h range.
1127          */
1128         if (link->dpcd_caps.dpcd_rev.raw < DPCD_REV_14)
1129                 retval = core_link_read_dpcd(
1130                         link,
1131                         DP_SINK_COUNT,
1132                         irq_data->raw,
1133                         sizeof(union hpd_irq_data));
1134         else {
1135                 /* Read 14 bytes in a single read and then copy only the required fields.
1136                  * This is more efficient than doing it in two separate AUX reads. */
1137
1138                 uint8_t tmp[DP_SINK_STATUS_ESI - DP_SINK_COUNT_ESI + 1];
1139
1140                 retval = core_link_read_dpcd(
1141                         link,
1142                         DP_SINK_COUNT_ESI,
1143                         tmp,
1144                         sizeof(tmp));
1145
1146                 if (retval != DC_OK)
1147                         return retval;
1148
1149                 irq_data->bytes.sink_cnt.raw = tmp[DP_SINK_COUNT_ESI - DP_SINK_COUNT_ESI];
1150                 irq_data->bytes.device_service_irq.raw = tmp[DP_DEVICE_SERVICE_IRQ_VECTOR_ESI0 - DP_SINK_COUNT_ESI];
1151                 irq_data->bytes.lane01_status.raw = tmp[DP_LANE0_1_STATUS_ESI - DP_SINK_COUNT_ESI];
1152                 irq_data->bytes.lane23_status.raw = tmp[DP_LANE2_3_STATUS_ESI - DP_SINK_COUNT_ESI];
1153                 irq_data->bytes.lane_status_updated.raw = tmp[DP_LANE_ALIGN_STATUS_UPDATED_ESI - DP_SINK_COUNT_ESI];
1154                 irq_data->bytes.sink_status.raw = tmp[DP_SINK_STATUS_ESI - DP_SINK_COUNT_ESI];
1155         }
1156
1157         return retval;
1158 }
1159
1160 static bool hpd_rx_irq_check_link_loss_status(
1161         struct dc_link *link,
1162         union hpd_irq_data *hpd_irq_dpcd_data)
1163 {
1164         uint8_t irq_reg_rx_power_state = 0;
1165         enum dc_status dpcd_result = DC_ERROR_UNEXPECTED;
1166         union lane_status lane_status;
1167         uint32_t lane;
1168         bool sink_status_changed;
1169         bool return_code;
1170
1171         sink_status_changed = false;
1172         return_code = false;
1173
1174         if (link->cur_link_settings.lane_count == 0)
1175                 return return_code;
1176
1177         /*1. Check that Link Status changed, before re-training.*/
1178
1179         /*parse lane status*/
1180         for (lane = 0; lane < link->cur_link_settings.lane_count; lane++) {
1181                 /* check status of lanes 0,1
1182                  * changed DpcdAddress_Lane01Status (0x202)
1183                  */
1184                 lane_status.raw = get_nibble_at_index(
1185                         &hpd_irq_dpcd_data->bytes.lane01_status.raw,
1186                         lane);
1187
1188                 if (!lane_status.bits.CHANNEL_EQ_DONE_0 ||
1189                         !lane_status.bits.CR_DONE_0 ||
1190                         !lane_status.bits.SYMBOL_LOCKED_0) {
1191                         /* if one of the channel equalization, clock
1192                          * recovery or symbol lock is dropped
1193                          * consider it as (link has been
1194                          * dropped) dp sink status has changed
1195                          */
1196                         sink_status_changed = true;
1197                         break;
1198                 }
1199         }
1200
1201         /* Check interlane align.*/
1202         if (sink_status_changed ||
1203                 !hpd_irq_dpcd_data->bytes.lane_status_updated.bits.INTERLANE_ALIGN_DONE) {
1204
1205                 DC_LOG_HW_HPD_IRQ("%s: Link Status changed.\n", __func__);
1206
1207                 return_code = true;
1208
1209                 /*2. Check that we can handle interrupt: Not in FS DOS,
1210                  *  Not in "Display Timeout" state, Link is trained.
1211                  */
1212                 dpcd_result = core_link_read_dpcd(link,
1213                         DP_SET_POWER,
1214                         &irq_reg_rx_power_state,
1215                         sizeof(irq_reg_rx_power_state));
1216
1217                 if (dpcd_result != DC_OK) {
1218                         DC_LOG_HW_HPD_IRQ("%s: DPCD read failed to obtain power state.\n",
1219                                 __func__);
1220                 } else {
1221                         if (irq_reg_rx_power_state != DP_SET_POWER_D0)
1222                                 return_code = false;
1223                 }
1224         }
1225
1226         return return_code;
1227 }
1228
1229 bool dp_verify_link_cap(
1230         struct dc_link *link,
1231         struct dc_link_settings *known_limit_link_setting,
1232         int *fail_count)
1233 {
1234         struct dc_link_settings max_link_cap = {0};
1235         struct dc_link_settings cur_link_setting = {0};
1236         struct dc_link_settings *cur = &cur_link_setting;
1237         struct dc_link_settings initial_link_settings = {0};
1238         bool success;
1239         bool skip_link_training;
1240         bool skip_video_pattern;
1241         struct clock_source *dp_cs;
1242         enum clock_source_id dp_cs_id = CLOCK_SOURCE_ID_EXTERNAL;
1243         enum link_training_result status;
1244         union hpd_irq_data irq_data;
1245
1246         if (link->dc->debug.skip_detection_link_training) {
1247                 link->verified_link_cap = *known_limit_link_setting;
1248                 return true;
1249         }
1250
1251         memset(&irq_data, 0, sizeof(irq_data));
1252         success = false;
1253         skip_link_training = false;
1254
1255         max_link_cap = get_max_link_cap(link);
1256
1257         /* TODO implement override and monitor patch later */
1258
1259         /* try to train the link from high to low to
1260          * find the physical link capability
1261          */
1262         /* disable PHY done possible by BIOS, will be done by driver itself */
1263         dp_disable_link_phy(link, link->connector_signal);
1264
1265         dp_cs = link->dc->res_pool->dp_clock_source;
1266
1267         if (dp_cs)
1268                 dp_cs_id = dp_cs->id;
1269         else {
1270                 /*
1271                  * dp clock source is not initialized for some reason.
1272                  * Should not happen, CLOCK_SOURCE_ID_EXTERNAL will be used
1273                  */
1274                 ASSERT(dp_cs);
1275         }
1276
1277         /* link training starts with the maximum common settings
1278          * supported by both sink and ASIC.
1279          */
1280         initial_link_settings = get_common_supported_link_settings(
1281                         *known_limit_link_setting,
1282                         max_link_cap);
1283         cur_link_setting = initial_link_settings;
1284         do {
1285                 skip_video_pattern = true;
1286
1287                 if (cur->link_rate == LINK_RATE_LOW)
1288                         skip_video_pattern = false;
1289
1290                 dp_enable_link_phy(
1291                                 link,
1292                                 link->connector_signal,
1293                                 dp_cs_id,
1294                                 cur);
1295
1296
1297                 if (skip_link_training)
1298                         success = true;
1299                 else {
1300                         status = dc_link_dp_perform_link_training(
1301                                                         link,
1302                                                         cur,
1303                                                         skip_video_pattern);
1304                         if (status == LINK_TRAINING_SUCCESS)
1305                                 success = true;
1306                         else
1307                                 (*fail_count)++;
1308                 }
1309
1310                 if (success) {
1311                         link->verified_link_cap = *cur;
1312                         udelay(1000);
1313                         if (read_hpd_rx_irq_data(link, &irq_data) == DC_OK)
1314                                 if (hpd_rx_irq_check_link_loss_status(
1315                                                 link,
1316                                                 &irq_data))
1317                                         (*fail_count)++;
1318                 }
1319                 /* always disable the link before trying another
1320                  * setting or before returning we'll enable it later
1321                  * based on the actual mode we're driving
1322                  */
1323                 dp_disable_link_phy(link, link->connector_signal);
1324         } while (!success && decide_fallback_link_setting(
1325                         initial_link_settings, cur, status));
1326
1327         /* Link Training failed for all Link Settings
1328          *  (Lane Count is still unknown)
1329          */
1330         if (!success) {
1331                 /* If all LT fails for all settings,
1332                  * set verified = failed safe (1 lane low)
1333                  */
1334                 link->verified_link_cap.lane_count = LANE_COUNT_ONE;
1335                 link->verified_link_cap.link_rate = LINK_RATE_LOW;
1336
1337                 link->verified_link_cap.link_spread =
1338                 LINK_SPREAD_DISABLED;
1339         }
1340
1341
1342         return success;
1343 }
1344
1345 static struct dc_link_settings get_common_supported_link_settings(
1346                 struct dc_link_settings link_setting_a,
1347                 struct dc_link_settings link_setting_b)
1348 {
1349         struct dc_link_settings link_settings = {0};
1350
1351         link_settings.lane_count =
1352                 (link_setting_a.lane_count <=
1353                         link_setting_b.lane_count) ?
1354                         link_setting_a.lane_count :
1355                         link_setting_b.lane_count;
1356         link_settings.link_rate =
1357                 (link_setting_a.link_rate <=
1358                         link_setting_b.link_rate) ?
1359                         link_setting_a.link_rate :
1360                         link_setting_b.link_rate;
1361         link_settings.link_spread = LINK_SPREAD_DISABLED;
1362
1363         /* in DP compliance test, DPR-120 may have
1364          * a random value in its MAX_LINK_BW dpcd field.
1365          * We map it to the maximum supported link rate that
1366          * is smaller than MAX_LINK_BW in this case.
1367          */
1368         if (link_settings.link_rate > LINK_RATE_HIGH3) {
1369                 link_settings.link_rate = LINK_RATE_HIGH3;
1370         } else if (link_settings.link_rate < LINK_RATE_HIGH3
1371                         && link_settings.link_rate > LINK_RATE_HIGH2) {
1372                 link_settings.link_rate = LINK_RATE_HIGH2;
1373         } else if (link_settings.link_rate < LINK_RATE_HIGH2
1374                         && link_settings.link_rate > LINK_RATE_HIGH) {
1375                 link_settings.link_rate = LINK_RATE_HIGH;
1376         } else if (link_settings.link_rate < LINK_RATE_HIGH
1377                         && link_settings.link_rate > LINK_RATE_LOW) {
1378                 link_settings.link_rate = LINK_RATE_LOW;
1379         } else if (link_settings.link_rate < LINK_RATE_LOW) {
1380                 link_settings.link_rate = LINK_RATE_UNKNOWN;
1381         }
1382
1383         return link_settings;
1384 }
1385
1386 static inline bool reached_minimum_lane_count(enum dc_lane_count lane_count)
1387 {
1388         return lane_count <= LANE_COUNT_ONE;
1389 }
1390
1391 static inline bool reached_minimum_link_rate(enum dc_link_rate link_rate)
1392 {
1393         return link_rate <= LINK_RATE_LOW;
1394 }
1395
1396 static enum dc_lane_count reduce_lane_count(enum dc_lane_count lane_count)
1397 {
1398         switch (lane_count) {
1399         case LANE_COUNT_FOUR:
1400                 return LANE_COUNT_TWO;
1401         case LANE_COUNT_TWO:
1402                 return LANE_COUNT_ONE;
1403         case LANE_COUNT_ONE:
1404                 return LANE_COUNT_UNKNOWN;
1405         default:
1406                 return LANE_COUNT_UNKNOWN;
1407         }
1408 }
1409
1410 static enum dc_link_rate reduce_link_rate(enum dc_link_rate link_rate)
1411 {
1412         switch (link_rate) {
1413         case LINK_RATE_HIGH3:
1414                 return LINK_RATE_HIGH2;
1415         case LINK_RATE_HIGH2:
1416                 return LINK_RATE_HIGH;
1417         case LINK_RATE_HIGH:
1418                 return LINK_RATE_LOW;
1419         case LINK_RATE_LOW:
1420                 return LINK_RATE_UNKNOWN;
1421         default:
1422                 return LINK_RATE_UNKNOWN;
1423         }
1424 }
1425
1426 static enum dc_lane_count increase_lane_count(enum dc_lane_count lane_count)
1427 {
1428         switch (lane_count) {
1429         case LANE_COUNT_ONE:
1430                 return LANE_COUNT_TWO;
1431         case LANE_COUNT_TWO:
1432                 return LANE_COUNT_FOUR;
1433         default:
1434                 return LANE_COUNT_UNKNOWN;
1435         }
1436 }
1437
1438 static enum dc_link_rate increase_link_rate(enum dc_link_rate link_rate)
1439 {
1440         switch (link_rate) {
1441         case LINK_RATE_LOW:
1442                 return LINK_RATE_HIGH;
1443         case LINK_RATE_HIGH:
1444                 return LINK_RATE_HIGH2;
1445         case LINK_RATE_HIGH2:
1446                 return LINK_RATE_HIGH3;
1447         default:
1448                 return LINK_RATE_UNKNOWN;
1449         }
1450 }
1451
1452 /*
1453  * function: set link rate and lane count fallback based
1454  * on current link setting and last link training result
1455  * return value:
1456  *                      true - link setting could be set
1457  *                      false - has reached minimum setting
1458  *                                      and no further fallback could be done
1459  */
1460 static bool decide_fallback_link_setting(
1461                 struct dc_link_settings initial_link_settings,
1462                 struct dc_link_settings *current_link_setting,
1463                 enum link_training_result training_result)
1464 {
1465         if (!current_link_setting)
1466                 return false;
1467
1468         switch (training_result) {
1469         case LINK_TRAINING_CR_FAIL_LANE0:
1470         case LINK_TRAINING_CR_FAIL_LANE1:
1471         case LINK_TRAINING_CR_FAIL_LANE23:
1472         case LINK_TRAINING_LQA_FAIL:
1473         {
1474                 if (!reached_minimum_link_rate
1475                                 (current_link_setting->link_rate)) {
1476                         current_link_setting->link_rate =
1477                                 reduce_link_rate(
1478                                         current_link_setting->link_rate);
1479                 } else if (!reached_minimum_lane_count
1480                                 (current_link_setting->lane_count)) {
1481                         current_link_setting->link_rate =
1482                                 initial_link_settings.link_rate;
1483                         if (training_result == LINK_TRAINING_CR_FAIL_LANE0)
1484                                 return false;
1485                         else if (training_result == LINK_TRAINING_CR_FAIL_LANE1)
1486                                 current_link_setting->lane_count =
1487                                                 LANE_COUNT_ONE;
1488                         else if (training_result ==
1489                                         LINK_TRAINING_CR_FAIL_LANE23)
1490                                 current_link_setting->lane_count =
1491                                                 LANE_COUNT_TWO;
1492                         else
1493                                 current_link_setting->lane_count =
1494                                         reduce_lane_count(
1495                                         current_link_setting->lane_count);
1496                 } else {
1497                         return false;
1498                 }
1499                 break;
1500         }
1501         case LINK_TRAINING_EQ_FAIL_EQ:
1502         {
1503                 if (!reached_minimum_lane_count
1504                                 (current_link_setting->lane_count)) {
1505                         current_link_setting->lane_count =
1506                                 reduce_lane_count(
1507                                         current_link_setting->lane_count);
1508                 } else if (!reached_minimum_link_rate
1509                                 (current_link_setting->link_rate)) {
1510                         current_link_setting->link_rate =
1511                                 reduce_link_rate(
1512                                         current_link_setting->link_rate);
1513                 } else {
1514                         return false;
1515                 }
1516                 break;
1517         }
1518         case LINK_TRAINING_EQ_FAIL_CR:
1519         {
1520                 if (!reached_minimum_link_rate
1521                                 (current_link_setting->link_rate)) {
1522                         current_link_setting->link_rate =
1523                                 reduce_link_rate(
1524                                         current_link_setting->link_rate);
1525                 } else {
1526                         return false;
1527                 }
1528                 break;
1529         }
1530         default:
1531                 return false;
1532         }
1533         return true;
1534 }
1535
1536 static uint32_t bandwidth_in_kbps_from_timing(
1537         const struct dc_crtc_timing *timing)
1538 {
1539         uint32_t bits_per_channel = 0;
1540         uint32_t kbps;
1541
1542         switch (timing->display_color_depth) {
1543         case COLOR_DEPTH_666:
1544                 bits_per_channel = 6;
1545                 break;
1546         case COLOR_DEPTH_888:
1547                 bits_per_channel = 8;
1548                 break;
1549         case COLOR_DEPTH_101010:
1550                 bits_per_channel = 10;
1551                 break;
1552         case COLOR_DEPTH_121212:
1553                 bits_per_channel = 12;
1554                 break;
1555         case COLOR_DEPTH_141414:
1556                 bits_per_channel = 14;
1557                 break;
1558         case COLOR_DEPTH_161616:
1559                 bits_per_channel = 16;
1560                 break;
1561         default:
1562                 break;
1563         }
1564
1565         ASSERT(bits_per_channel != 0);
1566
1567         kbps = timing->pix_clk_100hz / 10;
1568         kbps *= bits_per_channel;
1569
1570         if (timing->flags.Y_ONLY != 1) {
1571                 /*Only YOnly make reduce bandwidth by 1/3 compares to RGB*/
1572                 kbps *= 3;
1573                 if (timing->pixel_encoding == PIXEL_ENCODING_YCBCR420)
1574                         kbps /= 2;
1575                 else if (timing->pixel_encoding == PIXEL_ENCODING_YCBCR422)
1576                         kbps = kbps * 2 / 3;
1577         }
1578
1579         return kbps;
1580
1581 }
1582
1583 static uint32_t bandwidth_in_kbps_from_link_settings(
1584         const struct dc_link_settings *link_setting)
1585 {
1586         uint32_t link_rate_in_kbps = link_setting->link_rate *
1587                 LINK_RATE_REF_FREQ_IN_KHZ;
1588
1589         uint32_t lane_count  = link_setting->lane_count;
1590         uint32_t kbps = link_rate_in_kbps;
1591
1592         kbps *= lane_count;
1593         kbps *= 8;   /* 8 bits per byte*/
1594
1595         return kbps;
1596
1597 }
1598
1599 bool dp_validate_mode_timing(
1600         struct dc_link *link,
1601         const struct dc_crtc_timing *timing)
1602 {
1603         uint32_t req_bw;
1604         uint32_t max_bw;
1605
1606         const struct dc_link_settings *link_setting;
1607
1608         /*always DP fail safe mode*/
1609         if ((timing->pix_clk_100hz / 10) == (uint32_t) 25175 &&
1610                 timing->h_addressable == (uint32_t) 640 &&
1611                 timing->v_addressable == (uint32_t) 480)
1612                 return true;
1613
1614         /* We always use verified link settings */
1615         link_setting = &link->verified_link_cap;
1616
1617         /* TODO: DYNAMIC_VALIDATION needs to be implemented */
1618         /*if (flags.DYNAMIC_VALIDATION == 1 &&
1619                 link->verified_link_cap.lane_count != LANE_COUNT_UNKNOWN)
1620                 link_setting = &link->verified_link_cap;
1621         */
1622
1623         req_bw = bandwidth_in_kbps_from_timing(timing);
1624         max_bw = bandwidth_in_kbps_from_link_settings(link_setting);
1625
1626         if (req_bw <= max_bw) {
1627                 /* remember the biggest mode here, during
1628                  * initial link training (to get
1629                  * verified_link_cap), LS sends event about
1630                  * cannot train at reported cap to upper
1631                  * layer and upper layer will re-enumerate modes.
1632                  * this is not necessary if the lower
1633                  * verified_link_cap is enough to drive
1634                  * all the modes */
1635
1636                 /* TODO: DYNAMIC_VALIDATION needs to be implemented */
1637                 /* if (flags.DYNAMIC_VALIDATION == 1)
1638                         dpsst->max_req_bw_for_verified_linkcap = dal_max(
1639                                 dpsst->max_req_bw_for_verified_linkcap, req_bw); */
1640                 return true;
1641         } else
1642                 return false;
1643 }
1644
1645 static bool decide_dp_link_settings(struct dc_link *link, struct dc_link_settings *link_setting, uint32_t req_bw)
1646 {
1647         struct dc_link_settings initial_link_setting = {
1648                 LANE_COUNT_ONE, LINK_RATE_LOW, LINK_SPREAD_DISABLED, false, 0};
1649         struct dc_link_settings current_link_setting =
1650                         initial_link_setting;
1651         uint32_t link_bw;
1652
1653         /* search for the minimum link setting that:
1654          * 1. is supported according to the link training result
1655          * 2. could support the b/w requested by the timing
1656          */
1657         while (current_link_setting.link_rate <=
1658                         link->verified_link_cap.link_rate) {
1659                 link_bw = bandwidth_in_kbps_from_link_settings(
1660                                 &current_link_setting);
1661                 if (req_bw <= link_bw) {
1662                         *link_setting = current_link_setting;
1663                         return true;
1664                 }
1665
1666                 if (current_link_setting.lane_count <
1667                                 link->verified_link_cap.lane_count) {
1668                         current_link_setting.lane_count =
1669                                         increase_lane_count(
1670                                                         current_link_setting.lane_count);
1671                 } else {
1672                         current_link_setting.link_rate =
1673                                         increase_link_rate(
1674                                                         current_link_setting.link_rate);
1675                         current_link_setting.lane_count =
1676                                         initial_link_setting.lane_count;
1677                 }
1678         }
1679
1680         return false;
1681 }
1682
1683 static bool decide_edp_link_settings(struct dc_link *link, struct dc_link_settings *link_setting, uint32_t req_bw)
1684 {
1685         struct dc_link_settings initial_link_setting;
1686         struct dc_link_settings current_link_setting;
1687         uint32_t link_bw;
1688
1689         if (link->dpcd_caps.dpcd_rev.raw < DPCD_REV_14 ||
1690                         link->dpcd_caps.edp_supported_link_rates_count == 0 ||
1691                         link->dc->config.optimize_edp_link_rate == false) {
1692                 *link_setting = link->verified_link_cap;
1693                 return true;
1694         }
1695
1696         memset(&initial_link_setting, 0, sizeof(initial_link_setting));
1697         initial_link_setting.lane_count = LANE_COUNT_ONE;
1698         initial_link_setting.link_rate = link->dpcd_caps.edp_supported_link_rates[0];
1699         initial_link_setting.link_spread = LINK_SPREAD_DISABLED;
1700         initial_link_setting.use_link_rate_set = true;
1701         initial_link_setting.link_rate_set = 0;
1702         current_link_setting = initial_link_setting;
1703
1704         /* search for the minimum link setting that:
1705          * 1. is supported according to the link training result
1706          * 2. could support the b/w requested by the timing
1707          */
1708         while (current_link_setting.link_rate <=
1709                         link->verified_link_cap.link_rate) {
1710                 link_bw = bandwidth_in_kbps_from_link_settings(
1711                                 &current_link_setting);
1712                 if (req_bw <= link_bw) {
1713                         *link_setting = current_link_setting;
1714                         return true;
1715                 }
1716
1717                 if (current_link_setting.lane_count <
1718                                 link->verified_link_cap.lane_count) {
1719                         current_link_setting.lane_count =
1720                                         increase_lane_count(
1721                                                         current_link_setting.lane_count);
1722                 } else {
1723                         if (current_link_setting.link_rate_set < link->dpcd_caps.edp_supported_link_rates_count) {
1724                                 current_link_setting.link_rate_set++;
1725                                 current_link_setting.link_rate =
1726                                         link->dpcd_caps.edp_supported_link_rates[current_link_setting.link_rate_set];
1727                                 current_link_setting.lane_count =
1728                                                                         initial_link_setting.lane_count;
1729                         } else
1730                                 break;
1731                 }
1732         }
1733         return false;
1734 }
1735
1736 void decide_link_settings(struct dc_stream_state *stream,
1737         struct dc_link_settings *link_setting)
1738 {
1739         struct dc_link *link;
1740         uint32_t req_bw;
1741
1742         req_bw = bandwidth_in_kbps_from_timing(&stream->timing);
1743
1744         link = stream->link;
1745
1746         /* if preferred is specified through AMDDP, use it, if it's enough
1747          * to drive the mode
1748          */
1749         if (link->preferred_link_setting.lane_count !=
1750                         LANE_COUNT_UNKNOWN &&
1751                         link->preferred_link_setting.link_rate !=
1752                                         LINK_RATE_UNKNOWN) {
1753                 *link_setting =  link->preferred_link_setting;
1754                 return;
1755         }
1756
1757         /* MST doesn't perform link training for now
1758          * TODO: add MST specific link training routine
1759          */
1760         if (stream->signal == SIGNAL_TYPE_DISPLAY_PORT_MST) {
1761                 *link_setting = link->verified_link_cap;
1762                 return;
1763         }
1764
1765         if (link->connector_signal == SIGNAL_TYPE_EDP) {
1766                 if (decide_edp_link_settings(link, link_setting, req_bw))
1767                         return;
1768         } else if (decide_dp_link_settings(link, link_setting, req_bw))
1769                 return;
1770
1771         BREAK_TO_DEBUGGER();
1772         ASSERT(link->verified_link_cap.lane_count != LANE_COUNT_UNKNOWN);
1773
1774         *link_setting = link->verified_link_cap;
1775 }
1776
1777 /*************************Short Pulse IRQ***************************/
1778 static bool allow_hpd_rx_irq(const struct dc_link *link)
1779 {
1780         /*
1781          * Don't handle RX IRQ unless one of following is met:
1782          * 1) The link is established (cur_link_settings != unknown)
1783          * 2) We kicked off MST detection
1784          * 3) We know we're dealing with an active dongle
1785          */
1786
1787         if ((link->cur_link_settings.lane_count != LANE_COUNT_UNKNOWN) ||
1788                 (link->type == dc_connection_mst_branch) ||
1789                 is_dp_active_dongle(link))
1790                 return true;
1791
1792         return false;
1793 }
1794
1795 static bool handle_hpd_irq_psr_sink(const struct dc_link *link)
1796 {
1797         union dpcd_psr_configuration psr_configuration;
1798
1799         if (!link->psr_enabled)
1800                 return false;
1801
1802         dm_helpers_dp_read_dpcd(
1803                 link->ctx,
1804                 link,
1805                 368,/*DpcdAddress_PSR_Enable_Cfg*/
1806                 &psr_configuration.raw,
1807                 sizeof(psr_configuration.raw));
1808
1809
1810         if (psr_configuration.bits.ENABLE) {
1811                 unsigned char dpcdbuf[3] = {0};
1812                 union psr_error_status psr_error_status;
1813                 union psr_sink_psr_status psr_sink_psr_status;
1814
1815                 dm_helpers_dp_read_dpcd(
1816                         link->ctx,
1817                         link,
1818                         0x2006, /*DpcdAddress_PSR_Error_Status*/
1819                         (unsigned char *) dpcdbuf,
1820                         sizeof(dpcdbuf));
1821
1822                 /*DPCD 2006h   ERROR STATUS*/
1823                 psr_error_status.raw = dpcdbuf[0];
1824                 /*DPCD 2008h   SINK PANEL SELF REFRESH STATUS*/
1825                 psr_sink_psr_status.raw = dpcdbuf[2];
1826
1827                 if (psr_error_status.bits.LINK_CRC_ERROR ||
1828                                 psr_error_status.bits.RFB_STORAGE_ERROR) {
1829                         /* Acknowledge and clear error bits */
1830                         dm_helpers_dp_write_dpcd(
1831                                 link->ctx,
1832                                 link,
1833                                 8198,/*DpcdAddress_PSR_Error_Status*/
1834                                 &psr_error_status.raw,
1835                                 sizeof(psr_error_status.raw));
1836
1837                         /* PSR error, disable and re-enable PSR */
1838                         dc_link_set_psr_enable(link, false, true);
1839                         dc_link_set_psr_enable(link, true, true);
1840
1841                         return true;
1842                 } else if (psr_sink_psr_status.bits.SINK_SELF_REFRESH_STATUS ==
1843                                 PSR_SINK_STATE_ACTIVE_DISPLAY_FROM_SINK_RFB){
1844                         /* No error is detect, PSR is active.
1845                          * We should return with IRQ_HPD handled without
1846                          * checking for loss of sync since PSR would have
1847                          * powered down main link.
1848                          */
1849                         return true;
1850                 }
1851         }
1852         return false;
1853 }
1854
1855 static void dp_test_send_link_training(struct dc_link *link)
1856 {
1857         struct dc_link_settings link_settings = {0};
1858
1859         core_link_read_dpcd(
1860                         link,
1861                         DP_TEST_LANE_COUNT,
1862                         (unsigned char *)(&link_settings.lane_count),
1863                         1);
1864         core_link_read_dpcd(
1865                         link,
1866                         DP_TEST_LINK_RATE,
1867                         (unsigned char *)(&link_settings.link_rate),
1868                         1);
1869
1870         /* Set preferred link settings */
1871         link->verified_link_cap.lane_count = link_settings.lane_count;
1872         link->verified_link_cap.link_rate = link_settings.link_rate;
1873
1874         dp_retrain_link_dp_test(link, &link_settings, false);
1875 }
1876
1877 /* TODO Raven hbr2 compliance eye output is unstable
1878  * (toggling on and off) with debugger break
1879  * This caueses intermittent PHY automation failure
1880  * Need to look into the root cause */
1881 static void dp_test_send_phy_test_pattern(struct dc_link *link)
1882 {
1883         union phy_test_pattern dpcd_test_pattern;
1884         union lane_adjust dpcd_lane_adjustment[2];
1885         unsigned char dpcd_post_cursor_2_adjustment = 0;
1886         unsigned char test_80_bit_pattern[
1887                         (DP_TEST_80BIT_CUSTOM_PATTERN_79_72 -
1888                         DP_TEST_80BIT_CUSTOM_PATTERN_7_0)+1] = {0};
1889         enum dp_test_pattern test_pattern;
1890         struct dc_link_training_settings link_settings;
1891         union lane_adjust dpcd_lane_adjust;
1892         unsigned int lane;
1893         struct link_training_settings link_training_settings;
1894         int i = 0;
1895
1896         dpcd_test_pattern.raw = 0;
1897         memset(dpcd_lane_adjustment, 0, sizeof(dpcd_lane_adjustment));
1898         memset(&link_settings, 0, sizeof(link_settings));
1899
1900         /* get phy test pattern and pattern parameters from DP receiver */
1901         core_link_read_dpcd(
1902                         link,
1903                         DP_TEST_PHY_PATTERN,
1904                         &dpcd_test_pattern.raw,
1905                         sizeof(dpcd_test_pattern));
1906         core_link_read_dpcd(
1907                         link,
1908                         DP_ADJUST_REQUEST_LANE0_1,
1909                         &dpcd_lane_adjustment[0].raw,
1910                         sizeof(dpcd_lane_adjustment));
1911
1912         /*get post cursor 2 parameters
1913          * For DP 1.1a or eariler, this DPCD register's value is 0
1914          * For DP 1.2 or later:
1915          * Bits 1:0 = POST_CURSOR2_LANE0; Bits 3:2 = POST_CURSOR2_LANE1
1916          * Bits 5:4 = POST_CURSOR2_LANE2; Bits 7:6 = POST_CURSOR2_LANE3
1917          */
1918         core_link_read_dpcd(
1919                         link,
1920                         DP_ADJUST_REQUEST_POST_CURSOR2,
1921                         &dpcd_post_cursor_2_adjustment,
1922                         sizeof(dpcd_post_cursor_2_adjustment));
1923
1924         /* translate request */
1925         switch (dpcd_test_pattern.bits.PATTERN) {
1926         case PHY_TEST_PATTERN_D10_2:
1927                 test_pattern = DP_TEST_PATTERN_D102;
1928                 break;
1929         case PHY_TEST_PATTERN_SYMBOL_ERROR:
1930                 test_pattern = DP_TEST_PATTERN_SYMBOL_ERROR;
1931                 break;
1932         case PHY_TEST_PATTERN_PRBS7:
1933                 test_pattern = DP_TEST_PATTERN_PRBS7;
1934                 break;
1935         case PHY_TEST_PATTERN_80BIT_CUSTOM:
1936                 test_pattern = DP_TEST_PATTERN_80BIT_CUSTOM;
1937                 break;
1938         case PHY_TEST_PATTERN_CP2520_1:
1939                 /* CP2520 pattern is unstable, temporarily use TPS4 instead */
1940                 test_pattern = (link->dc->caps.force_dp_tps4_for_cp2520 == 1) ?
1941                                 DP_TEST_PATTERN_TRAINING_PATTERN4 :
1942                                 DP_TEST_PATTERN_HBR2_COMPLIANCE_EYE;
1943                 break;
1944         case PHY_TEST_PATTERN_CP2520_2:
1945                 /* CP2520 pattern is unstable, temporarily use TPS4 instead */
1946                 test_pattern = (link->dc->caps.force_dp_tps4_for_cp2520 == 1) ?
1947                                 DP_TEST_PATTERN_TRAINING_PATTERN4 :
1948                                 DP_TEST_PATTERN_HBR2_COMPLIANCE_EYE;
1949                 break;
1950         case PHY_TEST_PATTERN_CP2520_3:
1951                 test_pattern = DP_TEST_PATTERN_TRAINING_PATTERN4;
1952                 break;
1953         default:
1954                 test_pattern = DP_TEST_PATTERN_VIDEO_MODE;
1955         break;
1956         }
1957
1958         if (test_pattern == DP_TEST_PATTERN_80BIT_CUSTOM)
1959                 core_link_read_dpcd(
1960                                 link,
1961                                 DP_TEST_80BIT_CUSTOM_PATTERN_7_0,
1962                                 test_80_bit_pattern,
1963                                 sizeof(test_80_bit_pattern));
1964
1965         /* prepare link training settings */
1966         link_settings.link = link->cur_link_settings;
1967
1968         for (lane = 0; lane <
1969                 (unsigned int)(link->cur_link_settings.lane_count);
1970                 lane++) {
1971                 dpcd_lane_adjust.raw =
1972                         get_nibble_at_index(&dpcd_lane_adjustment[0].raw, lane);
1973                 link_settings.lane_settings[lane].VOLTAGE_SWING =
1974                         (enum dc_voltage_swing)
1975                         (dpcd_lane_adjust.bits.VOLTAGE_SWING_LANE);
1976                 link_settings.lane_settings[lane].PRE_EMPHASIS =
1977                         (enum dc_pre_emphasis)
1978                         (dpcd_lane_adjust.bits.PRE_EMPHASIS_LANE);
1979                 link_settings.lane_settings[lane].POST_CURSOR2 =
1980                         (enum dc_post_cursor2)
1981                         ((dpcd_post_cursor_2_adjustment >> (lane * 2)) & 0x03);
1982         }
1983
1984         for (i = 0; i < 4; i++)
1985                 link_training_settings.lane_settings[i] =
1986                                 link_settings.lane_settings[i];
1987         link_training_settings.link_settings = link_settings.link;
1988         link_training_settings.allow_invalid_msa_timing_param = false;
1989         /*Usage: Measure DP physical lane signal
1990          * by DP SI test equipment automatically.
1991          * PHY test pattern request is generated by equipment via HPD interrupt.
1992          * HPD needs to be active all the time. HPD should be active
1993          * all the time. Do not touch it.
1994          * forward request to DS
1995          */
1996         dc_link_dp_set_test_pattern(
1997                 link,
1998                 test_pattern,
1999                 &link_training_settings,
2000                 test_80_bit_pattern,
2001                 (DP_TEST_80BIT_CUSTOM_PATTERN_79_72 -
2002                 DP_TEST_80BIT_CUSTOM_PATTERN_7_0)+1);
2003 }
2004
2005 static void dp_test_send_link_test_pattern(struct dc_link *link)
2006 {
2007         union link_test_pattern dpcd_test_pattern;
2008         union test_misc dpcd_test_params;
2009         enum dp_test_pattern test_pattern;
2010
2011         memset(&dpcd_test_pattern, 0, sizeof(dpcd_test_pattern));
2012         memset(&dpcd_test_params, 0, sizeof(dpcd_test_params));
2013
2014         /* get link test pattern and pattern parameters */
2015         core_link_read_dpcd(
2016                         link,
2017                         DP_TEST_PATTERN,
2018                         &dpcd_test_pattern.raw,
2019                         sizeof(dpcd_test_pattern));
2020         core_link_read_dpcd(
2021                         link,
2022                         DP_TEST_MISC0,
2023                         &dpcd_test_params.raw,
2024                         sizeof(dpcd_test_params));
2025
2026         switch (dpcd_test_pattern.bits.PATTERN) {
2027         case LINK_TEST_PATTERN_COLOR_RAMP:
2028                 test_pattern = DP_TEST_PATTERN_COLOR_RAMP;
2029         break;
2030         case LINK_TEST_PATTERN_VERTICAL_BARS:
2031                 test_pattern = DP_TEST_PATTERN_VERTICAL_BARS;
2032         break; /* black and white */
2033         case LINK_TEST_PATTERN_COLOR_SQUARES:
2034                 test_pattern = (dpcd_test_params.bits.DYN_RANGE ==
2035                                 TEST_DYN_RANGE_VESA ?
2036                                 DP_TEST_PATTERN_COLOR_SQUARES :
2037                                 DP_TEST_PATTERN_COLOR_SQUARES_CEA);
2038         break;
2039         default:
2040                 test_pattern = DP_TEST_PATTERN_VIDEO_MODE;
2041         break;
2042         }
2043
2044         dc_link_dp_set_test_pattern(
2045                         link,
2046                         test_pattern,
2047                         NULL,
2048                         NULL,
2049                         0);
2050 }
2051
2052 static void handle_automated_test(struct dc_link *link)
2053 {
2054         union test_request test_request;
2055         union test_response test_response;
2056
2057         memset(&test_request, 0, sizeof(test_request));
2058         memset(&test_response, 0, sizeof(test_response));
2059
2060         core_link_read_dpcd(
2061                 link,
2062                 DP_TEST_REQUEST,
2063                 &test_request.raw,
2064                 sizeof(union test_request));
2065         if (test_request.bits.LINK_TRAINING) {
2066                 /* ACK first to let DP RX test box monitor LT sequence */
2067                 test_response.bits.ACK = 1;
2068                 core_link_write_dpcd(
2069                         link,
2070                         DP_TEST_RESPONSE,
2071                         &test_response.raw,
2072                         sizeof(test_response));
2073                 dp_test_send_link_training(link);
2074                 /* no acknowledge request is needed again */
2075                 test_response.bits.ACK = 0;
2076         }
2077         if (test_request.bits.LINK_TEST_PATTRN) {
2078                 dp_test_send_link_test_pattern(link);
2079                 test_response.bits.ACK = 1;
2080         }
2081         if (test_request.bits.PHY_TEST_PATTERN) {
2082                 dp_test_send_phy_test_pattern(link);
2083                 test_response.bits.ACK = 1;
2084         }
2085
2086         /* send request acknowledgment */
2087         if (test_response.bits.ACK)
2088                 core_link_write_dpcd(
2089                         link,
2090                         DP_TEST_RESPONSE,
2091                         &test_response.raw,
2092                         sizeof(test_response));
2093 }
2094
2095 bool dc_link_handle_hpd_rx_irq(struct dc_link *link, union hpd_irq_data *out_hpd_irq_dpcd_data, bool *out_link_loss)
2096 {
2097         union hpd_irq_data hpd_irq_dpcd_data = { { { {0} } } };
2098         union device_service_irq device_service_clear = { { 0 } };
2099         enum dc_status result;
2100
2101         bool status = false;
2102
2103         if (out_link_loss)
2104                 *out_link_loss = false;
2105         /* For use cases related to down stream connection status change,
2106          * PSR and device auto test, refer to function handle_sst_hpd_irq
2107          * in DAL2.1*/
2108
2109         DC_LOG_HW_HPD_IRQ("%s: Got short pulse HPD on link %d\n",
2110                 __func__, link->link_index);
2111
2112
2113          /* All the "handle_hpd_irq_xxx()" methods
2114                  * should be called only after
2115                  * dal_dpsst_ls_read_hpd_irq_data
2116                  * Order of calls is important too
2117                  */
2118         result = read_hpd_rx_irq_data(link, &hpd_irq_dpcd_data);
2119         if (out_hpd_irq_dpcd_data)
2120                 *out_hpd_irq_dpcd_data = hpd_irq_dpcd_data;
2121
2122         if (result != DC_OK) {
2123                 DC_LOG_HW_HPD_IRQ("%s: DPCD read failed to obtain irq data\n",
2124                         __func__);
2125                 return false;
2126         }
2127
2128         if (hpd_irq_dpcd_data.bytes.device_service_irq.bits.AUTOMATED_TEST) {
2129                 device_service_clear.bits.AUTOMATED_TEST = 1;
2130                 core_link_write_dpcd(
2131                         link,
2132                         DP_DEVICE_SERVICE_IRQ_VECTOR,
2133                         &device_service_clear.raw,
2134                         sizeof(device_service_clear.raw));
2135                 device_service_clear.raw = 0;
2136                 handle_automated_test(link);
2137                 return false;
2138         }
2139
2140         if (!allow_hpd_rx_irq(link)) {
2141                 DC_LOG_HW_HPD_IRQ("%s: skipping HPD handling on %d\n",
2142                         __func__, link->link_index);
2143                 return false;
2144         }
2145
2146         if (handle_hpd_irq_psr_sink(link))
2147                 /* PSR-related error was detected and handled */
2148                 return true;
2149
2150         /* If PSR-related error handled, Main link may be off,
2151          * so do not handle as a normal sink status change interrupt.
2152          */
2153
2154         if (hpd_irq_dpcd_data.bytes.device_service_irq.bits.UP_REQ_MSG_RDY)
2155                 return true;
2156
2157         /* check if we have MST msg and return since we poll for it */
2158         if (hpd_irq_dpcd_data.bytes.device_service_irq.bits.DOWN_REP_MSG_RDY)
2159                 return false;
2160
2161         /* For now we only handle 'Downstream port status' case.
2162          * If we got sink count changed it means
2163          * Downstream port status changed,
2164          * then DM should call DC to do the detection. */
2165         if (hpd_rx_irq_check_link_loss_status(
2166                 link,
2167                 &hpd_irq_dpcd_data)) {
2168                 /* Connectivity log: link loss */
2169                 CONN_DATA_LINK_LOSS(link,
2170                                         hpd_irq_dpcd_data.raw,
2171                                         sizeof(hpd_irq_dpcd_data),
2172                                         "Status: ");
2173
2174                 perform_link_training_with_retries(link,
2175                         &link->cur_link_settings,
2176                         true, LINK_TRAINING_ATTEMPTS);
2177
2178                 status = false;
2179                 if (out_link_loss)
2180                         *out_link_loss = true;
2181         }
2182
2183         if (link->type == dc_connection_active_dongle &&
2184                 hpd_irq_dpcd_data.bytes.sink_cnt.bits.SINK_COUNT
2185                         != link->dpcd_sink_count)
2186                 status = true;
2187
2188         /* reasons for HPD RX:
2189          * 1. Link Loss - ie Re-train the Link
2190          * 2. MST sideband message
2191          * 3. Automated Test - ie. Internal Commit
2192          * 4. CP (copy protection) - (not interesting for DM???)
2193          * 5. DRR
2194          * 6. Downstream Port status changed
2195          * -ie. Detect - this the only one
2196          * which is interesting for DM because
2197          * it must call dc_link_detect.
2198          */
2199         return status;
2200 }
2201
2202 /*query dpcd for version and mst cap addresses*/
2203 bool is_mst_supported(struct dc_link *link)
2204 {
2205         bool mst          = false;
2206         enum dc_status st = DC_OK;
2207         union dpcd_rev rev;
2208         union mstm_cap cap;
2209
2210         rev.raw  = 0;
2211         cap.raw  = 0;
2212
2213         st = core_link_read_dpcd(link, DP_DPCD_REV, &rev.raw,
2214                         sizeof(rev));
2215
2216         if (st == DC_OK && rev.raw >= DPCD_REV_12) {
2217
2218                 st = core_link_read_dpcd(link, DP_MSTM_CAP,
2219                                 &cap.raw, sizeof(cap));
2220                 if (st == DC_OK && cap.bits.MST_CAP == 1)
2221                         mst = true;
2222         }
2223         return mst;
2224
2225 }
2226
2227 bool is_dp_active_dongle(const struct dc_link *link)
2228 {
2229         return link->dpcd_caps.is_branch_dev;
2230 }
2231
2232 static int translate_dpcd_max_bpc(enum dpcd_downstream_port_max_bpc bpc)
2233 {
2234         switch (bpc) {
2235         case DOWN_STREAM_MAX_8BPC:
2236                 return 8;
2237         case DOWN_STREAM_MAX_10BPC:
2238                 return 10;
2239         case DOWN_STREAM_MAX_12BPC:
2240                 return 12;
2241         case DOWN_STREAM_MAX_16BPC:
2242                 return 16;
2243         default:
2244                 break;
2245         }
2246
2247         return -1;
2248 }
2249
2250 static void get_active_converter_info(
2251         uint8_t data, struct dc_link *link)
2252 {
2253         union dp_downstream_port_present ds_port = { .byte = data };
2254
2255         /* decode converter info*/
2256         if (!ds_port.fields.PORT_PRESENT) {
2257                 link->dpcd_caps.dongle_type = DISPLAY_DONGLE_NONE;
2258                 ddc_service_set_dongle_type(link->ddc,
2259                                 link->dpcd_caps.dongle_type);
2260                 return;
2261         }
2262
2263         /* DPCD 0x5 bit 0 = 1, it indicate it's branch device */
2264         link->dpcd_caps.is_branch_dev = ds_port.fields.PORT_PRESENT;
2265
2266         switch (ds_port.fields.PORT_TYPE) {
2267         case DOWNSTREAM_VGA:
2268                 link->dpcd_caps.dongle_type = DISPLAY_DONGLE_DP_VGA_CONVERTER;
2269                 break;
2270         case DOWNSTREAM_DVI_HDMI:
2271                 /* At this point we don't know is it DVI or HDMI,
2272                  * assume DVI.*/
2273                 link->dpcd_caps.dongle_type = DISPLAY_DONGLE_DP_DVI_CONVERTER;
2274                 break;
2275         default:
2276                 link->dpcd_caps.dongle_type = DISPLAY_DONGLE_NONE;
2277                 break;
2278         }
2279
2280         if (link->dpcd_caps.dpcd_rev.raw >= DPCD_REV_11) {
2281                 uint8_t det_caps[16]; /* CTS 4.2.2.7 expects source to read Detailed Capabilities Info : 00080h-0008F.*/
2282                 union dwnstream_port_caps_byte0 *port_caps =
2283                         (union dwnstream_port_caps_byte0 *)det_caps;
2284                 core_link_read_dpcd(link, DP_DOWNSTREAM_PORT_0,
2285                                 det_caps, sizeof(det_caps));
2286
2287                 switch (port_caps->bits.DWN_STRM_PORTX_TYPE) {
2288                 case DOWN_STREAM_DETAILED_VGA:
2289                         link->dpcd_caps.dongle_type =
2290                                 DISPLAY_DONGLE_DP_VGA_CONVERTER;
2291                         break;
2292                 case DOWN_STREAM_DETAILED_DVI:
2293                         link->dpcd_caps.dongle_type =
2294                                 DISPLAY_DONGLE_DP_DVI_CONVERTER;
2295                         break;
2296                 case DOWN_STREAM_DETAILED_HDMI:
2297                         link->dpcd_caps.dongle_type =
2298                                 DISPLAY_DONGLE_DP_HDMI_CONVERTER;
2299
2300                         link->dpcd_caps.dongle_caps.dongle_type = link->dpcd_caps.dongle_type;
2301                         if (ds_port.fields.DETAILED_CAPS) {
2302
2303                                 union dwnstream_port_caps_byte3_hdmi
2304                                         hdmi_caps = {.raw = det_caps[3] };
2305                                 union dwnstream_port_caps_byte2
2306                                         hdmi_color_caps = {.raw = det_caps[2] };
2307                                 link->dpcd_caps.dongle_caps.dp_hdmi_max_pixel_clk =
2308                                         det_caps[1] * 25000;
2309
2310                                 link->dpcd_caps.dongle_caps.is_dp_hdmi_s3d_converter =
2311                                         hdmi_caps.bits.FRAME_SEQ_TO_FRAME_PACK;
2312                                 link->dpcd_caps.dongle_caps.is_dp_hdmi_ycbcr422_pass_through =
2313                                         hdmi_caps.bits.YCrCr422_PASS_THROUGH;
2314                                 link->dpcd_caps.dongle_caps.is_dp_hdmi_ycbcr420_pass_through =
2315                                         hdmi_caps.bits.YCrCr420_PASS_THROUGH;
2316                                 link->dpcd_caps.dongle_caps.is_dp_hdmi_ycbcr422_converter =
2317                                         hdmi_caps.bits.YCrCr422_CONVERSION;
2318                                 link->dpcd_caps.dongle_caps.is_dp_hdmi_ycbcr420_converter =
2319                                         hdmi_caps.bits.YCrCr420_CONVERSION;
2320
2321                                 link->dpcd_caps.dongle_caps.dp_hdmi_max_bpc =
2322                                         translate_dpcd_max_bpc(
2323                                                 hdmi_color_caps.bits.MAX_BITS_PER_COLOR_COMPONENT);
2324
2325                                 if (link->dpcd_caps.dongle_caps.dp_hdmi_max_pixel_clk != 0)
2326                                         link->dpcd_caps.dongle_caps.extendedCapValid = true;
2327                         }
2328
2329                         break;
2330                 }
2331         }
2332
2333         ddc_service_set_dongle_type(link->ddc, link->dpcd_caps.dongle_type);
2334
2335         {
2336                 struct dp_device_vendor_id dp_id;
2337
2338                 /* read IEEE branch device id */
2339                 core_link_read_dpcd(
2340                         link,
2341                         DP_BRANCH_OUI,
2342                         (uint8_t *)&dp_id,
2343                         sizeof(dp_id));
2344
2345                 link->dpcd_caps.branch_dev_id =
2346                         (dp_id.ieee_oui[0] << 16) +
2347                         (dp_id.ieee_oui[1] << 8) +
2348                         dp_id.ieee_oui[2];
2349
2350                 memmove(
2351                         link->dpcd_caps.branch_dev_name,
2352                         dp_id.ieee_device_id,
2353                         sizeof(dp_id.ieee_device_id));
2354         }
2355
2356         {
2357                 struct dp_sink_hw_fw_revision dp_hw_fw_revision;
2358
2359                 core_link_read_dpcd(
2360                         link,
2361                         DP_BRANCH_REVISION_START,
2362                         (uint8_t *)&dp_hw_fw_revision,
2363                         sizeof(dp_hw_fw_revision));
2364
2365                 link->dpcd_caps.branch_hw_revision =
2366                         dp_hw_fw_revision.ieee_hw_rev;
2367
2368                 memmove(
2369                         link->dpcd_caps.branch_fw_revision,
2370                         dp_hw_fw_revision.ieee_fw_rev,
2371                         sizeof(dp_hw_fw_revision.ieee_fw_rev));
2372         }
2373 }
2374
2375 static void dp_wa_power_up_0010FA(struct dc_link *link, uint8_t *dpcd_data,
2376                 int length)
2377 {
2378         int retry = 0;
2379         union dp_downstream_port_present ds_port = { 0 };
2380
2381         if (!link->dpcd_caps.dpcd_rev.raw) {
2382                 do {
2383                         dp_receiver_power_ctrl(link, true);
2384                         core_link_read_dpcd(link, DP_DPCD_REV,
2385                                                         dpcd_data, length);
2386                         link->dpcd_caps.dpcd_rev.raw = dpcd_data[
2387                                 DP_DPCD_REV -
2388                                 DP_DPCD_REV];
2389                 } while (retry++ < 4 && !link->dpcd_caps.dpcd_rev.raw);
2390         }
2391
2392         ds_port.byte = dpcd_data[DP_DOWNSTREAMPORT_PRESENT -
2393                                  DP_DPCD_REV];
2394
2395         if (link->dpcd_caps.dongle_type == DISPLAY_DONGLE_DP_VGA_CONVERTER) {
2396                 switch (link->dpcd_caps.branch_dev_id) {
2397                 /* Some active dongles (DP-VGA, DP-DLDVI converters) power down
2398                  * all internal circuits including AUX communication preventing
2399                  * reading DPCD table and EDID (spec violation).
2400                  * Encoder will skip DP RX power down on disable_output to
2401                  * keep receiver powered all the time.*/
2402                 case DP_BRANCH_DEVICE_ID_1:
2403                 case DP_BRANCH_DEVICE_ID_4:
2404                         link->wa_flags.dp_keep_receiver_powered = true;
2405                         break;
2406
2407                 /* TODO: May need work around for other dongles. */
2408                 default:
2409                         link->wa_flags.dp_keep_receiver_powered = false;
2410                         break;
2411                 }
2412         } else
2413                 link->wa_flags.dp_keep_receiver_powered = false;
2414 }
2415
2416 static bool retrieve_link_cap(struct dc_link *link)
2417 {
2418         uint8_t dpcd_data[DP_ADAPTER_CAP - DP_DPCD_REV + 1];
2419
2420         /*Only need to read 1 byte starting from DP_DPRX_FEATURE_ENUMERATION_LIST.
2421          */
2422         uint8_t dpcd_dprx_data = '\0';
2423
2424         struct dp_device_vendor_id sink_id;
2425         union down_stream_port_count down_strm_port_count;
2426         union edp_configuration_cap edp_config_cap;
2427         union dp_downstream_port_present ds_port = { 0 };
2428         enum dc_status status = DC_ERROR_UNEXPECTED;
2429         uint32_t read_dpcd_retry_cnt = 3;
2430         int i;
2431         struct dp_sink_hw_fw_revision dp_hw_fw_revision;
2432
2433         memset(dpcd_data, '\0', sizeof(dpcd_data));
2434         memset(&down_strm_port_count,
2435                 '\0', sizeof(union down_stream_port_count));
2436         memset(&edp_config_cap, '\0',
2437                 sizeof(union edp_configuration_cap));
2438
2439         for (i = 0; i < read_dpcd_retry_cnt; i++) {
2440                 status = core_link_read_dpcd(
2441                                 link,
2442                                 DP_DPCD_REV,
2443                                 dpcd_data,
2444                                 sizeof(dpcd_data));
2445                 if (status == DC_OK)
2446                         break;
2447         }
2448
2449         if (status != DC_OK) {
2450                 dm_error("%s: Read dpcd data failed.\n", __func__);
2451                 return false;
2452         }
2453
2454         {
2455                 union training_aux_rd_interval aux_rd_interval;
2456
2457                 aux_rd_interval.raw =
2458                         dpcd_data[DP_TRAINING_AUX_RD_INTERVAL];
2459
2460                 link->dpcd_caps.ext_receiver_cap_field_present =
2461                                 aux_rd_interval.bits.EXT_RECEIVER_CAP_FIELD_PRESENT == 1 ? true:false;
2462
2463                 if (aux_rd_interval.bits.EXT_RECEIVER_CAP_FIELD_PRESENT == 1) {
2464                         uint8_t ext_cap_data[16];
2465
2466                         memset(ext_cap_data, '\0', sizeof(ext_cap_data));
2467                         for (i = 0; i < read_dpcd_retry_cnt; i++) {
2468                                 status = core_link_read_dpcd(
2469                                 link,
2470                                 DP_DP13_DPCD_REV,
2471                                 ext_cap_data,
2472                                 sizeof(ext_cap_data));
2473                                 if (status == DC_OK) {
2474                                         memcpy(dpcd_data, ext_cap_data, sizeof(dpcd_data));
2475                                         break;
2476                                 }
2477                         }
2478                         if (status != DC_OK)
2479                                 dm_error("%s: Read extend caps data failed, use cap from dpcd 0.\n", __func__);
2480                 }
2481         }
2482
2483         link->dpcd_caps.dpcd_rev.raw =
2484                         dpcd_data[DP_DPCD_REV - DP_DPCD_REV];
2485
2486         if (link->dpcd_caps.dpcd_rev.raw >= 0x14) {
2487                 for (i = 0; i < read_dpcd_retry_cnt; i++) {
2488                         status = core_link_read_dpcd(
2489                                         link,
2490                                         DP_DPRX_FEATURE_ENUMERATION_LIST,
2491                                         &dpcd_dprx_data,
2492                                         sizeof(dpcd_dprx_data));
2493                         if (status == DC_OK)
2494                                 break;
2495                 }
2496
2497                 link->dpcd_caps.dprx_feature.raw = dpcd_dprx_data;
2498
2499                 if (status != DC_OK)
2500                         dm_error("%s: Read DPRX caps data failed.\n", __func__);
2501         }
2502
2503         else {
2504                 link->dpcd_caps.dprx_feature.raw = 0;
2505         }
2506
2507
2508         /* Error condition checking...
2509          * It is impossible for Sink to report Max Lane Count = 0.
2510          * It is possible for Sink to report Max Link Rate = 0, if it is
2511          * an eDP device that is reporting specialized link rates in the
2512          * SUPPORTED_LINK_RATE table.
2513          */
2514         if (dpcd_data[DP_MAX_LANE_COUNT - DP_DPCD_REV] == 0)
2515                 return false;
2516
2517         ds_port.byte = dpcd_data[DP_DOWNSTREAMPORT_PRESENT -
2518                                  DP_DPCD_REV];
2519
2520         get_active_converter_info(ds_port.byte, link);
2521
2522         dp_wa_power_up_0010FA(link, dpcd_data, sizeof(dpcd_data));
2523
2524         down_strm_port_count.raw = dpcd_data[DP_DOWN_STREAM_PORT_COUNT -
2525                                  DP_DPCD_REV];
2526
2527         link->dpcd_caps.allow_invalid_MSA_timing_param =
2528                 down_strm_port_count.bits.IGNORE_MSA_TIMING_PARAM;
2529
2530         link->dpcd_caps.max_ln_count.raw = dpcd_data[
2531                 DP_MAX_LANE_COUNT - DP_DPCD_REV];
2532
2533         link->dpcd_caps.max_down_spread.raw = dpcd_data[
2534                 DP_MAX_DOWNSPREAD - DP_DPCD_REV];
2535
2536         link->reported_link_cap.lane_count =
2537                 link->dpcd_caps.max_ln_count.bits.MAX_LANE_COUNT;
2538         link->reported_link_cap.link_rate = dpcd_data[
2539                 DP_MAX_LINK_RATE - DP_DPCD_REV];
2540         link->reported_link_cap.link_spread =
2541                 link->dpcd_caps.max_down_spread.bits.MAX_DOWN_SPREAD ?
2542                 LINK_SPREAD_05_DOWNSPREAD_30KHZ : LINK_SPREAD_DISABLED;
2543
2544         edp_config_cap.raw = dpcd_data[
2545                 DP_EDP_CONFIGURATION_CAP - DP_DPCD_REV];
2546         link->dpcd_caps.panel_mode_edp =
2547                 edp_config_cap.bits.ALT_SCRAMBLER_RESET;
2548         link->dpcd_caps.dpcd_display_control_capable =
2549                 edp_config_cap.bits.DPCD_DISPLAY_CONTROL_CAPABLE;
2550
2551         link->test_pattern_enabled = false;
2552         link->compliance_test_state.raw = 0;
2553
2554         /* read sink count */
2555         core_link_read_dpcd(link,
2556                         DP_SINK_COUNT,
2557                         &link->dpcd_caps.sink_count.raw,
2558                         sizeof(link->dpcd_caps.sink_count.raw));
2559
2560         /* read sink ieee oui */
2561         core_link_read_dpcd(link,
2562                         DP_SINK_OUI,
2563                         (uint8_t *)(&sink_id),
2564                         sizeof(sink_id));
2565
2566         link->dpcd_caps.sink_dev_id =
2567                         (sink_id.ieee_oui[0] << 16) +
2568                         (sink_id.ieee_oui[1] << 8) +
2569                         (sink_id.ieee_oui[2]);
2570
2571         memmove(
2572                 link->dpcd_caps.sink_dev_id_str,
2573                 sink_id.ieee_device_id,
2574                 sizeof(sink_id.ieee_device_id));
2575
2576         core_link_read_dpcd(
2577                 link,
2578                 DP_SINK_HW_REVISION_START,
2579                 (uint8_t *)&dp_hw_fw_revision,
2580                 sizeof(dp_hw_fw_revision));
2581
2582         link->dpcd_caps.sink_hw_revision =
2583                 dp_hw_fw_revision.ieee_hw_rev;
2584
2585         memmove(
2586                 link->dpcd_caps.sink_fw_revision,
2587                 dp_hw_fw_revision.ieee_fw_rev,
2588                 sizeof(dp_hw_fw_revision.ieee_fw_rev));
2589
2590         /* Connectivity log: detection */
2591         CONN_DATA_DETECT(link, dpcd_data, sizeof(dpcd_data), "Rx Caps: ");
2592
2593         return true;
2594 }
2595
2596 bool detect_dp_sink_caps(struct dc_link *link)
2597 {
2598         return retrieve_link_cap(link);
2599
2600         /* dc init_hw has power encoder using default
2601          * signal for connector. For native DP, no
2602          * need to power up encoder again. If not native
2603          * DP, hw_init may need check signal or power up
2604          * encoder here.
2605          */
2606         /* TODO save sink caps in link->sink */
2607 }
2608
2609 enum dc_link_rate linkRateInKHzToLinkRateMultiplier(uint32_t link_rate_in_khz)
2610 {
2611         enum dc_link_rate link_rate;
2612         // LinkRate is normally stored as a multiplier of 0.27 Gbps per lane. Do the translation.
2613         switch (link_rate_in_khz) {
2614         case 1620000:
2615                 link_rate = LINK_RATE_LOW;              // Rate_1 (RBR)         - 1.62 Gbps/Lane
2616                 break;
2617         case 2160000:
2618                 link_rate = LINK_RATE_RATE_2;   // Rate_2                       - 2.16 Gbps/Lane
2619                 break;
2620         case 2430000:
2621                 link_rate = LINK_RATE_RATE_3;   // Rate_3                       - 2.43 Gbps/Lane
2622                 break;
2623         case 2700000:
2624                 link_rate = LINK_RATE_HIGH;             // Rate_4 (HBR)         - 2.70 Gbps/Lane
2625                 break;
2626         case 3240000:
2627                 link_rate = LINK_RATE_RBR2;             // Rate_5 (RBR2)        - 3.24 Gbps/Lane
2628                 break;
2629         case 4320000:
2630                 link_rate = LINK_RATE_RATE_6;   // Rate_6                       - 4.32 Gbps/Lane
2631                 break;
2632         case 5400000:
2633                 link_rate = LINK_RATE_HIGH2;    // Rate_7 (HBR2)        - 5.40 Gbps/Lane
2634                 break;
2635         case 8100000:
2636                 link_rate = LINK_RATE_HIGH3;    // Rate_8 (HBR3)        - 8.10 Gbps/Lane
2637                 break;
2638         default:
2639                 link_rate = LINK_RATE_UNKNOWN;
2640                 break;
2641         }
2642         return link_rate;
2643 }
2644
2645 void detect_edp_sink_caps(struct dc_link *link)
2646 {
2647         uint8_t supported_link_rates[16];
2648         uint32_t entry;
2649         uint32_t link_rate_in_khz;
2650         enum dc_link_rate link_rate = LINK_RATE_UNKNOWN;
2651
2652         retrieve_link_cap(link);
2653         link->dpcd_caps.edp_supported_link_rates_count = 0;
2654         memset(supported_link_rates, 0, sizeof(supported_link_rates));
2655
2656         if (link->dpcd_caps.dpcd_rev.raw >= DPCD_REV_14 &&
2657                         link->dc->config.optimize_edp_link_rate) {
2658                 // Read DPCD 00010h - 0001Fh 16 bytes at one shot
2659                 core_link_read_dpcd(link, DP_SUPPORTED_LINK_RATES,
2660                                                         supported_link_rates, sizeof(supported_link_rates));
2661
2662                 for (entry = 0; entry < 16; entry += 2) {
2663                         // DPCD register reports per-lane link rate = 16-bit link rate capability
2664                         // value X 200 kHz. Need multiplier to find link rate in kHz.
2665                         link_rate_in_khz = (supported_link_rates[entry+1] * 0x100 +
2666                                                                                 supported_link_rates[entry]) * 200;
2667
2668                         if (link_rate_in_khz != 0) {
2669                                 link_rate = linkRateInKHzToLinkRateMultiplier(link_rate_in_khz);
2670                                 link->dpcd_caps.edp_supported_link_rates[link->dpcd_caps.edp_supported_link_rates_count] = link_rate;
2671                                 link->dpcd_caps.edp_supported_link_rates_count++;
2672                         }
2673                 }
2674         }
2675         link->verified_link_cap = link->reported_link_cap;
2676 }
2677
2678 void dc_link_dp_enable_hpd(const struct dc_link *link)
2679 {
2680         struct link_encoder *encoder = link->link_enc;
2681
2682         if (encoder != NULL && encoder->funcs->enable_hpd != NULL)
2683                 encoder->funcs->enable_hpd(encoder);
2684 }
2685
2686 void dc_link_dp_disable_hpd(const struct dc_link *link)
2687 {
2688         struct link_encoder *encoder = link->link_enc;
2689
2690         if (encoder != NULL && encoder->funcs->enable_hpd != NULL)
2691                 encoder->funcs->disable_hpd(encoder);
2692 }
2693
2694 static bool is_dp_phy_pattern(enum dp_test_pattern test_pattern)
2695 {
2696         if ((DP_TEST_PATTERN_PHY_PATTERN_BEGIN <= test_pattern &&
2697                         test_pattern <= DP_TEST_PATTERN_PHY_PATTERN_END) ||
2698                         test_pattern == DP_TEST_PATTERN_VIDEO_MODE)
2699                 return true;
2700         else
2701                 return false;
2702 }
2703
2704 static void set_crtc_test_pattern(struct dc_link *link,
2705                                 struct pipe_ctx *pipe_ctx,
2706                                 enum dp_test_pattern test_pattern)
2707 {
2708         enum controller_dp_test_pattern controller_test_pattern;
2709         enum dc_color_depth color_depth = pipe_ctx->
2710                 stream->timing.display_color_depth;
2711         struct bit_depth_reduction_params params;
2712         struct output_pixel_processor *opp = pipe_ctx->stream_res.opp;
2713
2714         memset(&params, 0, sizeof(params));
2715
2716         switch (test_pattern) {
2717         case DP_TEST_PATTERN_COLOR_SQUARES:
2718                 controller_test_pattern =
2719                                 CONTROLLER_DP_TEST_PATTERN_COLORSQUARES;
2720         break;
2721         case DP_TEST_PATTERN_COLOR_SQUARES_CEA:
2722                 controller_test_pattern =
2723                                 CONTROLLER_DP_TEST_PATTERN_COLORSQUARES_CEA;
2724         break;
2725         case DP_TEST_PATTERN_VERTICAL_BARS:
2726                 controller_test_pattern =
2727                                 CONTROLLER_DP_TEST_PATTERN_VERTICALBARS;
2728         break;
2729         case DP_TEST_PATTERN_HORIZONTAL_BARS:
2730                 controller_test_pattern =
2731                                 CONTROLLER_DP_TEST_PATTERN_HORIZONTALBARS;
2732         break;
2733         case DP_TEST_PATTERN_COLOR_RAMP:
2734                 controller_test_pattern =
2735                                 CONTROLLER_DP_TEST_PATTERN_COLORRAMP;
2736         break;
2737         default:
2738                 controller_test_pattern =
2739                                 CONTROLLER_DP_TEST_PATTERN_VIDEOMODE;
2740         break;
2741         }
2742
2743         switch (test_pattern) {
2744         case DP_TEST_PATTERN_COLOR_SQUARES:
2745         case DP_TEST_PATTERN_COLOR_SQUARES_CEA:
2746         case DP_TEST_PATTERN_VERTICAL_BARS:
2747         case DP_TEST_PATTERN_HORIZONTAL_BARS:
2748         case DP_TEST_PATTERN_COLOR_RAMP:
2749         {
2750                 /* disable bit depth reduction */
2751                 pipe_ctx->stream->bit_depth_params = params;
2752                 opp->funcs->opp_program_bit_depth_reduction(opp, &params);
2753                 if (pipe_ctx->stream_res.tg->funcs->set_test_pattern)
2754                         pipe_ctx->stream_res.tg->funcs->set_test_pattern(pipe_ctx->stream_res.tg,
2755                                 controller_test_pattern, color_depth);
2756         }
2757         break;
2758         case DP_TEST_PATTERN_VIDEO_MODE:
2759         {
2760                 /* restore bitdepth reduction */
2761                 resource_build_bit_depth_reduction_params(pipe_ctx->stream, &params);
2762                 pipe_ctx->stream->bit_depth_params = params;
2763                 opp->funcs->opp_program_bit_depth_reduction(opp, &params);
2764                 if (pipe_ctx->stream_res.tg->funcs->set_test_pattern)
2765                         pipe_ctx->stream_res.tg->funcs->set_test_pattern(pipe_ctx->stream_res.tg,
2766                                 CONTROLLER_DP_TEST_PATTERN_VIDEOMODE,
2767                                 color_depth);
2768         }
2769         break;
2770
2771         default:
2772         break;
2773         }
2774 }
2775
2776 bool dc_link_dp_set_test_pattern(
2777         struct dc_link *link,
2778         enum dp_test_pattern test_pattern,
2779         const struct link_training_settings *p_link_settings,
2780         const unsigned char *p_custom_pattern,
2781         unsigned int cust_pattern_size)
2782 {
2783         struct pipe_ctx *pipes = link->dc->current_state->res_ctx.pipe_ctx;
2784         struct pipe_ctx *pipe_ctx = &pipes[0];
2785         unsigned int lane;
2786         unsigned int i;
2787         unsigned char link_qual_pattern[LANE_COUNT_DP_MAX] = {0};
2788         union dpcd_training_pattern training_pattern;
2789         enum dpcd_phy_test_patterns pattern;
2790
2791         memset(&training_pattern, 0, sizeof(training_pattern));
2792
2793         for (i = 0; i < MAX_PIPES; i++) {
2794                 if (pipes[i].stream->link == link) {
2795                         pipe_ctx = &pipes[i];
2796                         break;
2797                 }
2798         }
2799
2800         /* Reset CRTC Test Pattern if it is currently running and request
2801          * is VideoMode Reset DP Phy Test Pattern if it is currently running
2802          * and request is VideoMode
2803          */
2804         if (link->test_pattern_enabled && test_pattern ==
2805                         DP_TEST_PATTERN_VIDEO_MODE) {
2806                 /* Set CRTC Test Pattern */
2807                 set_crtc_test_pattern(link, pipe_ctx, test_pattern);
2808                 dp_set_hw_test_pattern(link, test_pattern,
2809                                 (uint8_t *)p_custom_pattern,
2810                                 (uint32_t)cust_pattern_size);
2811
2812                 /* Unblank Stream */
2813                 link->dc->hwss.unblank_stream(
2814                         pipe_ctx,
2815                         &link->verified_link_cap);
2816                 /* TODO:m_pHwss->MuteAudioEndpoint
2817                  * (pPathMode->pDisplayPath, false);
2818                  */
2819
2820                 /* Reset Test Pattern state */
2821                 link->test_pattern_enabled = false;
2822
2823                 return true;
2824         }
2825
2826         /* Check for PHY Test Patterns */
2827         if (is_dp_phy_pattern(test_pattern)) {
2828                 /* Set DPCD Lane Settings before running test pattern */
2829                 if (p_link_settings != NULL) {
2830                         dp_set_hw_lane_settings(link, p_link_settings);
2831                         dpcd_set_lane_settings(link, p_link_settings);
2832                 }
2833
2834                 /* Blank stream if running test pattern */
2835                 if (test_pattern != DP_TEST_PATTERN_VIDEO_MODE) {
2836                         /*TODO:
2837                          * m_pHwss->
2838                          * MuteAudioEndpoint(pPathMode->pDisplayPath, true);
2839                          */
2840                         /* Blank stream */
2841                         pipes->stream_res.stream_enc->funcs->dp_blank(pipe_ctx->stream_res.stream_enc);
2842                 }
2843
2844                 dp_set_hw_test_pattern(link, test_pattern,
2845                                 (uint8_t *)p_custom_pattern,
2846                                 (uint32_t)cust_pattern_size);
2847
2848                 if (test_pattern != DP_TEST_PATTERN_VIDEO_MODE) {
2849                         /* Set Test Pattern state */
2850                         link->test_pattern_enabled = true;
2851                         if (p_link_settings != NULL)
2852                                 dpcd_set_link_settings(link,
2853                                                 p_link_settings);
2854                 }
2855
2856                 switch (test_pattern) {
2857                 case DP_TEST_PATTERN_VIDEO_MODE:
2858                         pattern = PHY_TEST_PATTERN_NONE;
2859                         break;
2860                 case DP_TEST_PATTERN_D102:
2861                         pattern = PHY_TEST_PATTERN_D10_2;
2862                         break;
2863                 case DP_TEST_PATTERN_SYMBOL_ERROR:
2864                         pattern = PHY_TEST_PATTERN_SYMBOL_ERROR;
2865                         break;
2866                 case DP_TEST_PATTERN_PRBS7:
2867                         pattern = PHY_TEST_PATTERN_PRBS7;
2868                         break;
2869                 case DP_TEST_PATTERN_80BIT_CUSTOM:
2870                         pattern = PHY_TEST_PATTERN_80BIT_CUSTOM;
2871                         break;
2872                 case DP_TEST_PATTERN_CP2520_1:
2873                         pattern = PHY_TEST_PATTERN_CP2520_1;
2874                         break;
2875                 case DP_TEST_PATTERN_CP2520_2:
2876                         pattern = PHY_TEST_PATTERN_CP2520_2;
2877                         break;
2878                 case DP_TEST_PATTERN_CP2520_3:
2879                         pattern = PHY_TEST_PATTERN_CP2520_3;
2880                         break;
2881                 default:
2882                         return false;
2883                 }
2884
2885                 if (test_pattern == DP_TEST_PATTERN_VIDEO_MODE
2886                 /*TODO:&& !pPathMode->pDisplayPath->IsTargetPoweredOn()*/)
2887                         return false;
2888
2889                 if (link->dpcd_caps.dpcd_rev.raw >= DPCD_REV_12) {
2890                         /* tell receiver that we are sending qualification
2891                          * pattern DP 1.2 or later - DP receiver's link quality
2892                          * pattern is set using DPCD LINK_QUAL_LANEx_SET
2893                          * register (0x10B~0x10E)\
2894                          */
2895                         for (lane = 0; lane < LANE_COUNT_DP_MAX; lane++)
2896                                 link_qual_pattern[lane] =
2897                                                 (unsigned char)(pattern);
2898
2899                         core_link_write_dpcd(link,
2900                                         DP_LINK_QUAL_LANE0_SET,
2901                                         link_qual_pattern,
2902                                         sizeof(link_qual_pattern));
2903                 } else if (link->dpcd_caps.dpcd_rev.raw >= DPCD_REV_10 ||
2904                            link->dpcd_caps.dpcd_rev.raw == 0) {
2905                         /* tell receiver that we are sending qualification
2906                          * pattern DP 1.1a or earlier - DP receiver's link
2907                          * quality pattern is set using
2908                          * DPCD TRAINING_PATTERN_SET -> LINK_QUAL_PATTERN_SET
2909                          * register (0x102). We will use v_1.3 when we are
2910                          * setting test pattern for DP 1.1.
2911                          */
2912                         core_link_read_dpcd(link, DP_TRAINING_PATTERN_SET,
2913                                             &training_pattern.raw,
2914                                             sizeof(training_pattern));
2915                         training_pattern.v1_3.LINK_QUAL_PATTERN_SET = pattern;
2916                         core_link_write_dpcd(link, DP_TRAINING_PATTERN_SET,
2917                                              &training_pattern.raw,
2918                                              sizeof(training_pattern));
2919                 }
2920         } else {
2921         /* CRTC Patterns */
2922                 set_crtc_test_pattern(link, pipe_ctx, test_pattern);
2923                 /* Set Test Pattern state */
2924                 link->test_pattern_enabled = true;
2925         }
2926
2927         return true;
2928 }
2929
2930 void dp_enable_mst_on_sink(struct dc_link *link, bool enable)
2931 {
2932         unsigned char mstmCntl;
2933
2934         core_link_read_dpcd(link, DP_MSTM_CTRL, &mstmCntl, 1);
2935         if (enable)
2936                 mstmCntl |= DP_MST_EN;
2937         else
2938                 mstmCntl &= (~DP_MST_EN);
2939
2940         core_link_write_dpcd(link, DP_MSTM_CTRL, &mstmCntl, 1);
2941 }