drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c

   1 /* Copyright 2015 Advanced Micro Devices, Inc. */
   2 #include "dm_services.h"
   3 #include "dc.h"
   4 #include "dc_link_dp.h"
   5 #include "dm_helpers.h"
   6 #include "opp.h"
   7 #include "dsc.h"
   8 #include "resource.h"
   9
  10 #include "inc/core_types.h"
  11 #include "link_hwss.h"
  12 #include "dc_link_ddc.h"
  13 #include "core_status.h"
  14 #include "dpcd_defs.h"
  15
  16 #include "resource.h"
  17 #define DC_LOGGER \
  18         link->ctx->logger
  19
  20
  21 #define DP_REPEATER_CONFIGURATION_AND_STATUS_SIZE   0x50
  22
  23 /* maximum pre emphasis level allowed for each voltage swing level*/
  24 static const enum dc_pre_emphasis voltage_swing_to_pre_emphasis[] = {
  25                 PRE_EMPHASIS_LEVEL3,
  26                 PRE_EMPHASIS_LEVEL2,
  27                 PRE_EMPHASIS_LEVEL1,
  28                 PRE_EMPHASIS_DISABLED };
  29
  30 enum {
  31         POST_LT_ADJ_REQ_LIMIT = 6,
  32         POST_LT_ADJ_REQ_TIMEOUT = 200
  33 };
  34
  35 enum {
  36         LINK_TRAINING_MAX_RETRY_COUNT = 5,
  37         /* to avoid infinite loop where-in the receiver
  38          * switches between different VS
  39          */
  40         LINK_TRAINING_MAX_CR_RETRY = 100
  41 };
  42
  43 static bool decide_fallback_link_setting(
  44                 struct dc_link_settings initial_link_settings,
  45                 struct dc_link_settings *current_link_setting,
  46                 enum link_training_result training_result);
  47 static struct dc_link_settings get_common_supported_link_settings(
  48                 struct dc_link_settings link_setting_a,
  49                 struct dc_link_settings link_setting_b);
  50
  51 static uint32_t get_training_aux_rd_interval(
  52         struct dc_link *link,
  53         uint32_t default_wait_in_micro_secs)
  54 {
  55         union training_aux_rd_interval training_rd_interval;
  56
  57         memset(&training_rd_interval, 0, sizeof(training_rd_interval));
  58
  59         /* overwrite the delay if rev > 1.1*/
  60         if (link->dpcd_caps.dpcd_rev.raw >= DPCD_REV_12) {
  61                 /* DP 1.2 or later - retrieve delay through
  62                  * "DPCD_ADDR_TRAINING_AUX_RD_INTERVAL" register */
  63                 core_link_read_dpcd(
  64                         link,
  65                         DP_TRAINING_AUX_RD_INTERVAL,
  66                         (uint8_t *)&training_rd_interval,
  67                         sizeof(training_rd_interval));
  68
  69                 if (training_rd_interval.bits.TRAINIG_AUX_RD_INTERVAL)
  70                         default_wait_in_micro_secs = training_rd_interval.bits.TRAINIG_AUX_RD_INTERVAL * 4000;
  71         }
  72
  73         return default_wait_in_micro_secs;
  74 }
  75
  76 static void wait_for_training_aux_rd_interval(
  77         struct dc_link *link,
  78         uint32_t wait_in_micro_secs)
  79 {
  80         udelay(wait_in_micro_secs);
  81
  82         DC_LOG_HW_LINK_TRAINING("%s:\n wait = %d\n",
  83                 __func__,
  84                 wait_in_micro_secs);
  85 }
  86
  87 static void dpcd_set_training_pattern(
  88         struct dc_link *link,
  89         union dpcd_training_pattern dpcd_pattern)
  90 {
  91         core_link_write_dpcd(
  92                 link,
  93                 DP_TRAINING_PATTERN_SET,
  94                 &dpcd_pattern.raw,
  95                 1);
  96
  97         DC_LOG_HW_LINK_TRAINING("%s\n %x pattern = %x\n",
  98                 __func__,
  99                 DP_TRAINING_PATTERN_SET,
 100                 dpcd_pattern.v1_4.TRAINING_PATTERN_SET);
 101 }
 102
 103 static enum dc_dp_training_pattern get_supported_tp(struct dc_link *link)
 104 {
 105         enum dc_dp_training_pattern highest_tp = DP_TRAINING_PATTERN_SEQUENCE_2;
 106         struct encoder_feature_support *features = &link->link_enc->features;
 107         struct dpcd_caps *dpcd_caps = &link->dpcd_caps;
 108
 109         if (features->flags.bits.IS_TPS3_CAPABLE)
 110                 highest_tp = DP_TRAINING_PATTERN_SEQUENCE_3;
 111
 112         if (features->flags.bits.IS_TPS4_CAPABLE)
 113                 highest_tp = DP_TRAINING_PATTERN_SEQUENCE_4;
 114
 115         if (dpcd_caps->max_down_spread.bits.TPS4_SUPPORTED &&
 116                 highest_tp >= DP_TRAINING_PATTERN_SEQUENCE_4)
 117                 return DP_TRAINING_PATTERN_SEQUENCE_4;
 118
 119         if (dpcd_caps->max_ln_count.bits.TPS3_SUPPORTED &&
 120                 highest_tp >= DP_TRAINING_PATTERN_SEQUENCE_3)
 121                 return DP_TRAINING_PATTERN_SEQUENCE_3;
 122
 123         return DP_TRAINING_PATTERN_SEQUENCE_2;
 124 }
 125
 126 static void dpcd_set_link_settings(
 127         struct dc_link *link,
 128         const struct link_training_settings *lt_settings)
 129 {
 130         uint8_t rate;
 131
 132         union down_spread_ctrl downspread = { {0} };
 133         union lane_count_set lane_count_set = { {0} };
 134         enum dc_dp_training_pattern dp_tr_pattern;
 135
 136         downspread.raw = (uint8_t)
 137         (lt_settings->link_settings.link_spread);
 138
 139         lane_count_set.bits.LANE_COUNT_SET =
 140         lt_settings->link_settings.lane_count;
 141
 142         lane_count_set.bits.ENHANCED_FRAMING = lt_settings->enhanced_framing;
 143         lane_count_set.bits.POST_LT_ADJ_REQ_GRANTED = 0;
 144
 145         dp_tr_pattern = get_supported_tp(link);
 146
 147         if (dp_tr_pattern != DP_TRAINING_PATTERN_SEQUENCE_4) {
 148                 lane_count_set.bits.POST_LT_ADJ_REQ_GRANTED =
 149                                 link->dpcd_caps.max_ln_count.bits.POST_LT_ADJ_REQ_SUPPORTED;
 150         }
 151
 152         core_link_write_dpcd(link, DP_DOWNSPREAD_CTRL,
 153                 &downspread.raw, sizeof(downspread));
 154
 155         core_link_write_dpcd(link, DP_LANE_COUNT_SET,
 156                 &lane_count_set.raw, 1);
 157
 158         if (link->dpcd_caps.dpcd_rev.raw >= DPCD_REV_14 &&
 159                         lt_settings->link_settings.use_link_rate_set == true) {
 160                 rate = 0;
 161                 core_link_write_dpcd(link, DP_LINK_BW_SET, &rate, 1);
 162                 core_link_write_dpcd(link, DP_LINK_RATE_SET,
 163                                 &lt_settings->link_settings.link_rate_set, 1);
 164         } else {
 165                 rate = (uint8_t) (lt_settings->link_settings.link_rate);
 166                 core_link_write_dpcd(link, DP_LINK_BW_SET, &rate, 1);
 167         }
 168
 169         if (rate) {
 170                 DC_LOG_HW_LINK_TRAINING("%s\n %x rate = %x\n %x lane = %x framing = %x\n %x spread = %x\n",
 171                         __func__,
 172                         DP_LINK_BW_SET,
 173                         lt_settings->link_settings.link_rate,
 174                         DP_LANE_COUNT_SET,
 175                         lt_settings->link_settings.lane_count,
 176                         lt_settings->enhanced_framing,
 177                         DP_DOWNSPREAD_CTRL,
 178                         lt_settings->link_settings.link_spread);
 179         } else {
 180                 DC_LOG_HW_LINK_TRAINING("%s\n %x rate set = %x\n %x lane = %x framing = %x\n %x spread = %x\n",
 181                         __func__,
 182                         DP_LINK_RATE_SET,
 183                         lt_settings->link_settings.link_rate_set,
 184                         DP_LANE_COUNT_SET,
 185                         lt_settings->link_settings.lane_count,
 186                         lt_settings->enhanced_framing,
 187                         DP_DOWNSPREAD_CTRL,
 188                         lt_settings->link_settings.link_spread);
 189         }
 190 }
 191
 192 static enum dpcd_training_patterns
 193         dc_dp_training_pattern_to_dpcd_training_pattern(
 194         struct dc_link *link,
 195         enum dc_dp_training_pattern pattern)
 196 {
 197         enum dpcd_training_patterns dpcd_tr_pattern =
 198         DPCD_TRAINING_PATTERN_VIDEOIDLE;
 199
 200         switch (pattern) {
 201         case DP_TRAINING_PATTERN_SEQUENCE_1:
 202                 dpcd_tr_pattern = DPCD_TRAINING_PATTERN_1;
 203                 break;
 204         case DP_TRAINING_PATTERN_SEQUENCE_2:
 205                 dpcd_tr_pattern = DPCD_TRAINING_PATTERN_2;
 206                 break;
 207         case DP_TRAINING_PATTERN_SEQUENCE_3:
 208                 dpcd_tr_pattern = DPCD_TRAINING_PATTERN_3;
 209                 break;
 210         case DP_TRAINING_PATTERN_SEQUENCE_4:
 211                 dpcd_tr_pattern = DPCD_TRAINING_PATTERN_4;
 212                 break;
 213         default:
 214                 ASSERT(0);
 215                 DC_LOG_HW_LINK_TRAINING("%s: Invalid HW Training pattern: %d\n",
 216                         __func__, pattern);
 217                 break;
 218         }
 219
 220         return dpcd_tr_pattern;
 221 }
 222
 223 static inline bool is_repeater(struct dc_link *link, uint32_t offset)
 224 {
 225         return (!link->is_lttpr_mode_transparent && offset != 0);
 226 }
 227
 228 static void dpcd_set_lt_pattern_and_lane_settings(
 229         struct dc_link *link,
 230         const struct link_training_settings *lt_settings,
 231         enum dc_dp_training_pattern pattern,
 232         uint32_t offset)
 233 {
 234         union dpcd_training_lane dpcd_lane[LANE_COUNT_DP_MAX] = { { {0} } };
 235
 236         uint32_t dpcd_base_lt_offset;
 237
 238         uint8_t dpcd_lt_buffer[5] = {0};
 239         union dpcd_training_pattern dpcd_pattern = { {0} };
 240         uint32_t lane;
 241         uint32_t size_in_bytes;
 242         bool edp_workaround = false; /* TODO link_prop.INTERNAL */
 243         dpcd_base_lt_offset = DP_TRAINING_PATTERN_SET;
 244
 245         if (is_repeater(link, offset))
 246                 dpcd_base_lt_offset = DP_TRAINING_PATTERN_SET_PHY_REPEATER1 +
 247                         ((DP_REPEATER_CONFIGURATION_AND_STATUS_SIZE) * (offset - 1));
 248
 249         /*****************************************************************
 250         * DpcdAddress_TrainingPatternSet
 251         *****************************************************************/
 252         dpcd_pattern.v1_4.TRAINING_PATTERN_SET =
 253                 dc_dp_training_pattern_to_dpcd_training_pattern(link, pattern);
 254
 255         dpcd_lt_buffer[DP_TRAINING_PATTERN_SET - DP_TRAINING_PATTERN_SET]
 256                 = dpcd_pattern.raw;
 257
 258         if (is_repeater(link, offset)) {
 259                 DC_LOG_HW_LINK_TRAINING("%s\n LTTPR Repeater ID: %d\n 0x%X pattern = %x\n",
 260                         __func__,
 261                         offset,
 262                         dpcd_base_lt_offset,
 263                         dpcd_pattern.v1_4.TRAINING_PATTERN_SET);
 264         } else {
 265                 DC_LOG_HW_LINK_TRAINING("%s\n 0x%X pattern = %x\n",
 266                         __func__,
 267                         dpcd_base_lt_offset,
 268                         dpcd_pattern.v1_4.TRAINING_PATTERN_SET);
 269         }
 270         /*****************************************************************
 271         * DpcdAddress_Lane0Set -> DpcdAddress_Lane3Set
 272         *****************************************************************/
 273         for (lane = 0; lane <
 274                 (uint32_t)(lt_settings->link_settings.lane_count); lane++) {
 275
 276                 dpcd_lane[lane].bits.VOLTAGE_SWING_SET =
 277                 (uint8_t)(lt_settings->lane_settings[lane].VOLTAGE_SWING);
 278                 dpcd_lane[lane].bits.PRE_EMPHASIS_SET =
 279                 (uint8_t)(lt_settings->lane_settings[lane].PRE_EMPHASIS);
 280
 281                 dpcd_lane[lane].bits.MAX_SWING_REACHED =
 282                 (lt_settings->lane_settings[lane].VOLTAGE_SWING ==
 283                 VOLTAGE_SWING_MAX_LEVEL ? 1 : 0);
 284                 dpcd_lane[lane].bits.MAX_PRE_EMPHASIS_REACHED =
 285                 (lt_settings->lane_settings[lane].PRE_EMPHASIS ==
 286                 PRE_EMPHASIS_MAX_LEVEL ? 1 : 0);
 287         }
 288
 289         /* concatenate everything into one buffer*/
 290
 291         size_in_bytes = lt_settings->link_settings.lane_count * sizeof(dpcd_lane[0]);
 292
 293          // 0x00103 - 0x00102
 294         memmove(
 295                 &dpcd_lt_buffer[DP_TRAINING_LANE0_SET - DP_TRAINING_PATTERN_SET],
 296                 dpcd_lane,
 297                 size_in_bytes);
 298
 299         if (is_repeater(link, offset)) {
 300                 DC_LOG_HW_LINK_TRAINING("%s:\n LTTPR Repeater ID: %d\n"
 301                                 " 0x%X VS set = %x PE set = %x max VS Reached = %x  max PE Reached = %x\n",
 302                         __func__,
 303                         offset,
 304                         dpcd_base_lt_offset,
 305                         dpcd_lane[0].bits.VOLTAGE_SWING_SET,
 306                         dpcd_lane[0].bits.PRE_EMPHASIS_SET,
 307                         dpcd_lane[0].bits.MAX_SWING_REACHED,
 308                         dpcd_lane[0].bits.MAX_PRE_EMPHASIS_REACHED);
 309         } else {
 310                 DC_LOG_HW_LINK_TRAINING("%s:\n 0x%X VS set = %x  PE set = %x max VS Reached = %x  max PE Reached = %x\n",
 311                         __func__,
 312                         dpcd_base_lt_offset,
 313                         dpcd_lane[0].bits.VOLTAGE_SWING_SET,
 314                         dpcd_lane[0].bits.PRE_EMPHASIS_SET,
 315                         dpcd_lane[0].bits.MAX_SWING_REACHED,
 316                         dpcd_lane[0].bits.MAX_PRE_EMPHASIS_REACHED);
 317         }
 318         if (edp_workaround) {
 319                 /* for eDP write in 2 parts because the 5-byte burst is
 320                 * causing issues on some eDP panels (EPR#366724)
 321                 */
 322                 core_link_write_dpcd(
 323                         link,
 324                         DP_TRAINING_PATTERN_SET,
 325                         &dpcd_pattern.raw,
 326                         sizeof(dpcd_pattern.raw));
 327
 328                 core_link_write_dpcd(
 329                         link,
 330                         DP_TRAINING_LANE0_SET,
 331                         (uint8_t *)(dpcd_lane),
 332                         size_in_bytes);
 333
 334                 } else
 335                 /* write it all in (1 + number-of-lanes)-byte burst*/
 336                         core_link_write_dpcd(
 337                                 link,
 338                                 dpcd_base_lt_offset,
 339                                 dpcd_lt_buffer,
 340                                 size_in_bytes + sizeof(dpcd_pattern.raw));
 341
 342         link->cur_lane_setting = lt_settings->lane_settings[0];
 343 }
 344
 345 static bool is_cr_done(enum dc_lane_count ln_count,
 346         union lane_status *dpcd_lane_status)
 347 {
 348         bool done = true;
 349         uint32_t lane;
 350         /*LANEx_CR_DONE bits All 1's?*/
 351         for (lane = 0; lane < (uint32_t)(ln_count); lane++) {
 352                 if (!dpcd_lane_status[lane].bits.CR_DONE_0)
 353                         done = false;
 354         }
 355         return done;
 356
 357 }
 358
 359 static bool is_ch_eq_done(enum dc_lane_count ln_count,
 360         union lane_status *dpcd_lane_status,
 361         union lane_align_status_updated *lane_status_updated)
 362 {
 363         bool done = true;
 364         uint32_t lane;
 365         if (!lane_status_updated->bits.INTERLANE_ALIGN_DONE)
 366                 done = false;
 367         else {
 368                 for (lane = 0; lane < (uint32_t)(ln_count); lane++) {
 369                         if (!dpcd_lane_status[lane].bits.SYMBOL_LOCKED_0 ||
 370                                 !dpcd_lane_status[lane].bits.CHANNEL_EQ_DONE_0)
 371                                 done = false;
 372                 }
 373         }
 374         return done;
 375
 376 }
 377
 378 static void update_drive_settings(
 379                 struct link_training_settings *dest,
 380                 struct link_training_settings src)
 381 {
 382         uint32_t lane;
 383         for (lane = 0; lane < src.link_settings.lane_count; lane++) {
 384                 if (dest->voltage_swing == NULL)
 385                         dest->lane_settings[lane].VOLTAGE_SWING = src.lane_settings[lane].VOLTAGE_SWING;
 386                 else
 387                         dest->lane_settings[lane].VOLTAGE_SWING = *dest->voltage_swing;
 388
 389                 if (dest->pre_emphasis == NULL)
 390                         dest->lane_settings[lane].PRE_EMPHASIS = src.lane_settings[lane].PRE_EMPHASIS;
 391                 else
 392                         dest->lane_settings[lane].PRE_EMPHASIS = *dest->pre_emphasis;
 393
 394                 if (dest->post_cursor2 == NULL)
 395                         dest->lane_settings[lane].POST_CURSOR2 = src.lane_settings[lane].POST_CURSOR2;
 396                 else
 397                         dest->lane_settings[lane].POST_CURSOR2 = *dest->post_cursor2;
 398         }
 399 }
 400
 401 static uint8_t get_nibble_at_index(const uint8_t *buf,
 402         uint32_t index)
 403 {
 404         uint8_t nibble;
 405         nibble = buf[index / 2];
 406
 407         if (index % 2)
 408                 nibble >>= 4;
 409         else
 410                 nibble &= 0x0F;
 411
 412         return nibble;
 413 }
 414
 415 static enum dc_pre_emphasis get_max_pre_emphasis_for_voltage_swing(
 416         enum dc_voltage_swing voltage)
 417 {
 418         enum dc_pre_emphasis pre_emphasis;
 419         pre_emphasis = PRE_EMPHASIS_MAX_LEVEL;
 420
 421         if (voltage <= VOLTAGE_SWING_MAX_LEVEL)
 422                 pre_emphasis = voltage_swing_to_pre_emphasis[voltage];
 423
 424         return pre_emphasis;
 425
 426 }
 427
 428 static void find_max_drive_settings(
 429         const struct link_training_settings *link_training_setting,
 430         struct link_training_settings *max_lt_setting)
 431 {
 432         uint32_t lane;
 433         struct dc_lane_settings max_requested;
 434
 435         max_requested.VOLTAGE_SWING =
 436                 link_training_setting->
 437                 lane_settings[0].VOLTAGE_SWING;
 438         max_requested.PRE_EMPHASIS =
 439                 link_training_setting->
 440                 lane_settings[0].PRE_EMPHASIS;
 441         /*max_requested.postCursor2 =
 442          * link_training_setting->laneSettings[0].postCursor2;*/
 443
 444         /* Determine what the maximum of the requested settings are*/
 445         for (lane = 1; lane < link_training_setting->link_settings.lane_count;
 446                         lane++) {
 447                 if (link_training_setting->lane_settings[lane].VOLTAGE_SWING >
 448                         max_requested.VOLTAGE_SWING)
 449
 450                         max_requested.VOLTAGE_SWING =
 451                         link_training_setting->
 452                         lane_settings[lane].VOLTAGE_SWING;
 453
 454                 if (link_training_setting->lane_settings[lane].PRE_EMPHASIS >
 455                                 max_requested.PRE_EMPHASIS)
 456                         max_requested.PRE_EMPHASIS =
 457                         link_training_setting->
 458                         lane_settings[lane].PRE_EMPHASIS;
 459
 460                 /*
 461                 if (link_training_setting->laneSettings[lane].postCursor2 >
 462                  max_requested.postCursor2)
 463                 {
 464                 max_requested.postCursor2 =
 465                 link_training_setting->laneSettings[lane].postCursor2;
 466                 }
 467                 */
 468         }
 469
 470         /* make sure the requested settings are
 471          * not higher than maximum settings*/
 472         if (max_requested.VOLTAGE_SWING > VOLTAGE_SWING_MAX_LEVEL)
 473                 max_requested.VOLTAGE_SWING = VOLTAGE_SWING_MAX_LEVEL;
 474
 475         if (max_requested.PRE_EMPHASIS > PRE_EMPHASIS_MAX_LEVEL)
 476                 max_requested.PRE_EMPHASIS = PRE_EMPHASIS_MAX_LEVEL;
 477         /*
 478         if (max_requested.postCursor2 > PostCursor2_MaxLevel)
 479         max_requested.postCursor2 = PostCursor2_MaxLevel;
 480         */
 481
 482         /* make sure the pre-emphasis matches the voltage swing*/
 483         if (max_requested.PRE_EMPHASIS >
 484                 get_max_pre_emphasis_for_voltage_swing(
 485                         max_requested.VOLTAGE_SWING))
 486                 max_requested.PRE_EMPHASIS =
 487                 get_max_pre_emphasis_for_voltage_swing(
 488                         max_requested.VOLTAGE_SWING);
 489
 490         /*
 491          * Post Cursor2 levels are completely independent from
 492          * pre-emphasis (Post Cursor1) levels. But Post Cursor2 levels
 493          * can only be applied to each allowable combination of voltage
 494          * swing and pre-emphasis levels */
 495          /* if ( max_requested.postCursor2 >
 496           *  getMaxPostCursor2ForVoltageSwing(max_requested.voltageSwing))
 497           *  max_requested.postCursor2 =
 498           *  getMaxPostCursor2ForVoltageSwing(max_requested.voltageSwing);
 499           */
 500
 501         max_lt_setting->link_settings.link_rate =
 502                 link_training_setting->link_settings.link_rate;
 503         max_lt_setting->link_settings.lane_count =
 504         link_training_setting->link_settings.lane_count;
 505         max_lt_setting->link_settings.link_spread =
 506                 link_training_setting->link_settings.link_spread;
 507
 508         for (lane = 0; lane <
 509                 link_training_setting->link_settings.lane_count;
 510                 lane++) {
 511                 max_lt_setting->lane_settings[lane].VOLTAGE_SWING =
 512                         max_requested.VOLTAGE_SWING;
 513                 max_lt_setting->lane_settings[lane].PRE_EMPHASIS =
 514                         max_requested.PRE_EMPHASIS;
 515                 /*max_lt_setting->laneSettings[lane].postCursor2 =
 516                  * max_requested.postCursor2;
 517                  */
 518         }
 519
 520 }
 521
 522 static void get_lane_status_and_drive_settings(
 523         struct dc_link *link,
 524         const struct link_training_settings *link_training_setting,
 525         union lane_status *ln_status,
 526         union lane_align_status_updated *ln_status_updated,
 527         struct link_training_settings *req_settings,
 528         uint32_t offset)
 529 {
 530         unsigned int lane01_status_address = DP_LANE0_1_STATUS;
 531         uint8_t lane_adjust_offset = 4;
 532         unsigned int lane01_adjust_address;
 533         uint8_t dpcd_buf[6] = {0};
 534         union lane_adjust dpcd_lane_adjust[LANE_COUNT_DP_MAX] = { { {0} } };
 535         struct link_training_settings request_settings = { {0} };
 536         uint32_t lane;
 537
 538         memset(req_settings, '\0', sizeof(struct link_training_settings));
 539
 540         if (is_repeater(link, offset)) {
 541                 lane01_status_address =
 542                                 DP_LANE0_1_STATUS_PHY_REPEATER1 +
 543                                 ((DP_REPEATER_CONFIGURATION_AND_STATUS_SIZE) * (offset - 1));
 544                 lane_adjust_offset = 3;
 545         }
 546
 547         core_link_read_dpcd(
 548                 link,
 549                 lane01_status_address,
 550                 (uint8_t *)(dpcd_buf),
 551                 sizeof(dpcd_buf));
 552
 553         for (lane = 0; lane <
 554                 (uint32_t)(link_training_setting->link_settings.lane_count);
 555                 lane++) {
 556
 557                 ln_status[lane].raw =
 558                         get_nibble_at_index(&dpcd_buf[0], lane);
 559                 dpcd_lane_adjust[lane].raw =
 560                         get_nibble_at_index(&dpcd_buf[lane_adjust_offset], lane);
 561         }
 562
 563         ln_status_updated->raw = dpcd_buf[2];
 564
 565         if (is_repeater(link, offset)) {
 566                 DC_LOG_HW_LINK_TRAINING("%s:\n LTTPR Repeater ID: %d\n"
 567                                 " 0x%X Lane01Status = %x\n 0x%X Lane23Status = %x\n ",
 568                         __func__,
 569                         offset,
 570                         lane01_status_address, dpcd_buf[0],
 571                         lane01_status_address + 1, dpcd_buf[1]);
 572         } else {
 573                 DC_LOG_HW_LINK_TRAINING("%s:\n 0x%X Lane01Status = %x\n 0x%X Lane23Status = %x\n ",
 574                         __func__,
 575                         lane01_status_address, dpcd_buf[0],
 576                         lane01_status_address + 1, dpcd_buf[1]);
 577         }
 578         lane01_adjust_address = DP_ADJUST_REQUEST_LANE0_1;
 579
 580         if (is_repeater(link, offset))
 581                 lane01_adjust_address = DP_ADJUST_REQUEST_LANE0_1_PHY_REPEATER1 +
 582                                 ((DP_REPEATER_CONFIGURATION_AND_STATUS_SIZE) * (offset - 1));
 583
 584         if (is_repeater(link, offset)) {
 585                 DC_LOG_HW_LINK_TRAINING("%s:\n LTTPR Repeater ID: %d\n"
 586                                 " 0x%X Lane01AdjustRequest = %x\n 0x%X Lane23AdjustRequest = %x\n",
 587                                         __func__,
 588                                         offset,
 589                                         lane01_adjust_address,
 590                                         dpcd_buf[lane_adjust_offset],
 591                                         lane01_adjust_address + 1,
 592                                         dpcd_buf[lane_adjust_offset + 1]);
 593         } else {
 594                 DC_LOG_HW_LINK_TRAINING("%s:\n 0x%X Lane01AdjustRequest = %x\n 0x%X Lane23AdjustRequest = %x\n",
 595                         __func__,
 596                         lane01_adjust_address,
 597                         dpcd_buf[lane_adjust_offset],
 598                         lane01_adjust_address + 1,
 599                         dpcd_buf[lane_adjust_offset + 1]);
 600         }
 601
 602         /*copy to req_settings*/
 603         request_settings.link_settings.lane_count =
 604                 link_training_setting->link_settings.lane_count;
 605         request_settings.link_settings.link_rate =
 606                 link_training_setting->link_settings.link_rate;
 607         request_settings.link_settings.link_spread =
 608                 link_training_setting->link_settings.link_spread;
 609
 610         for (lane = 0; lane <
 611                 (uint32_t)(link_training_setting->link_settings.lane_count);
 612                 lane++) {
 613
 614                 request_settings.lane_settings[lane].VOLTAGE_SWING =
 615                         (enum dc_voltage_swing)(dpcd_lane_adjust[lane].bits.
 616                                 VOLTAGE_SWING_LANE);
 617                 request_settings.lane_settings[lane].PRE_EMPHASIS =
 618                         (enum dc_pre_emphasis)(dpcd_lane_adjust[lane].bits.
 619                                 PRE_EMPHASIS_LANE);
 620         }
 621
 622         /*Note: for postcursor2, read adjusted
 623          * postcursor2 settings from*/
 624         /*DpcdAddress_AdjustRequestPostCursor2 =
 625          *0x020C (not implemented yet)*/
 626
 627         /* we find the maximum of the requested settings across all lanes*/
 628         /* and set this maximum for all lanes*/
 629         find_max_drive_settings(&request_settings, req_settings);
 630
 631         /* if post cursor 2 is needed in the future,
 632          * read DpcdAddress_AdjustRequestPostCursor2 = 0x020C
 633          */
 634
 635 }
 636
 637 static void dpcd_set_lane_settings(
 638         struct dc_link *link,
 639         const struct link_training_settings *link_training_setting,
 640         uint32_t offset)
 641 {
 642         union dpcd_training_lane dpcd_lane[LANE_COUNT_DP_MAX] = {{{0}}};
 643         uint32_t lane;
 644         unsigned int lane0_set_address;
 645
 646         lane0_set_address = DP_TRAINING_LANE0_SET;
 647
 648         if (is_repeater(link, offset))
 649                 lane0_set_address = DP_TRAINING_LANE0_SET_PHY_REPEATER1 +
 650                 ((DP_REPEATER_CONFIGURATION_AND_STATUS_SIZE) * (offset - 1));
 651
 652         for (lane = 0; lane <
 653                 (uint32_t)(link_training_setting->
 654                 link_settings.lane_count);
 655                 lane++) {
 656                 dpcd_lane[lane].bits.VOLTAGE_SWING_SET =
 657                         (uint8_t)(link_training_setting->
 658                         lane_settings[lane].VOLTAGE_SWING);
 659                 dpcd_lane[lane].bits.PRE_EMPHASIS_SET =
 660                         (uint8_t)(link_training_setting->
 661                         lane_settings[lane].PRE_EMPHASIS);
 662                 dpcd_lane[lane].bits.MAX_SWING_REACHED =
 663                         (link_training_setting->
 664                         lane_settings[lane].VOLTAGE_SWING ==
 665                         VOLTAGE_SWING_MAX_LEVEL ? 1 : 0);
 666                 dpcd_lane[lane].bits.MAX_PRE_EMPHASIS_REACHED =
 667                         (link_training_setting->
 668                         lane_settings[lane].PRE_EMPHASIS ==
 669                         PRE_EMPHASIS_MAX_LEVEL ? 1 : 0);
 670         }
 671
 672         core_link_write_dpcd(link,
 673                 lane0_set_address,
 674                 (uint8_t *)(dpcd_lane),
 675                 link_training_setting->link_settings.lane_count);
 676
 677         /*
 678         if (LTSettings.link.rate == LinkRate_High2)
 679         {
 680                 DpcdTrainingLaneSet2 dpcd_lane2[lane_count_DPMax] = {0};
 681                 for ( uint32_t lane = 0;
 682                 lane < lane_count_DPMax; lane++)
 683                 {
 684                         dpcd_lane2[lane].bits.post_cursor2_set =
 685                         static_cast<unsigned char>(
 686                         LTSettings.laneSettings[lane].postCursor2);
 687                         dpcd_lane2[lane].bits.max_post_cursor2_reached = 0;
 688                 }
 689                 m_pDpcdAccessSrv->WriteDpcdData(
 690                 DpcdAddress_Lane0Set2,
 691                 reinterpret_cast<unsigned char*>(dpcd_lane2),
 692                 LTSettings.link.lanes);
 693         }
 694         */
 695
 696         if (is_repeater(link, offset)) {
 697                 DC_LOG_HW_LINK_TRAINING("%s\n LTTPR Repeater ID: %d\n"
 698                                 " 0x%X VS set = %x  PE set = %x max VS Reached = %x  max PE Reached = %x\n",
 699                         __func__,
 700                         offset,
 701                         lane0_set_address,
 702                         dpcd_lane[0].bits.VOLTAGE_SWING_SET,
 703                         dpcd_lane[0].bits.PRE_EMPHASIS_SET,
 704                         dpcd_lane[0].bits.MAX_SWING_REACHED,
 705                         dpcd_lane[0].bits.MAX_PRE_EMPHASIS_REACHED);
 706
 707         } else {
 708                 DC_LOG_HW_LINK_TRAINING("%s\n 0x%X VS set = %x  PE set = %x max VS Reached = %x  max PE Reached = %x\n",
 709                         __func__,
 710                         lane0_set_address,
 711                         dpcd_lane[0].bits.VOLTAGE_SWING_SET,
 712                         dpcd_lane[0].bits.PRE_EMPHASIS_SET,
 713                         dpcd_lane[0].bits.MAX_SWING_REACHED,
 714                         dpcd_lane[0].bits.MAX_PRE_EMPHASIS_REACHED);
 715         }
 716         link->cur_lane_setting = link_training_setting->lane_settings[0];
 717
 718 }
 719
 720 static bool is_max_vs_reached(
 721         const struct link_training_settings *lt_settings)
 722 {
 723         uint32_t lane;
 724         for (lane = 0; lane <
 725                 (uint32_t)(lt_settings->link_settings.lane_count);
 726                 lane++) {
 727                 if (lt_settings->lane_settings[lane].VOLTAGE_SWING
 728                         == VOLTAGE_SWING_MAX_LEVEL)
 729                         return true;
 730         }
 731         return false;
 732
 733 }
 734
 735 static bool perform_post_lt_adj_req_sequence(
 736         struct dc_link *link,
 737         struct link_training_settings *lt_settings)
 738 {
 739         enum dc_lane_count lane_count =
 740         lt_settings->link_settings.lane_count;
 741
 742         uint32_t adj_req_count;
 743         uint32_t adj_req_timer;
 744         bool req_drv_setting_changed;
 745         uint32_t lane;
 746
 747         req_drv_setting_changed = false;
 748         for (adj_req_count = 0; adj_req_count < POST_LT_ADJ_REQ_LIMIT;
 749         adj_req_count++) {
 750
 751                 req_drv_setting_changed = false;
 752
 753                 for (adj_req_timer = 0;
 754                         adj_req_timer < POST_LT_ADJ_REQ_TIMEOUT;
 755                         adj_req_timer++) {
 756
 757                         struct link_training_settings req_settings;
 758                         union lane_status dpcd_lane_status[LANE_COUNT_DP_MAX];
 759                         union lane_align_status_updated
 760                                 dpcd_lane_status_updated;
 761
 762                         get_lane_status_and_drive_settings(
 763                         link,
 764                         lt_settings,
 765                         dpcd_lane_status,
 766                         &dpcd_lane_status_updated,
 767                         &req_settings,
 768                         DPRX);
 769
 770                         if (dpcd_lane_status_updated.bits.
 771                                         POST_LT_ADJ_REQ_IN_PROGRESS == 0)
 772                                 return true;
 773
 774                         if (!is_cr_done(lane_count, dpcd_lane_status))
 775                                 return false;
 776
 777                         if (!is_ch_eq_done(
 778                                 lane_count,
 779                                 dpcd_lane_status,
 780                                 &dpcd_lane_status_updated))
 781                                 return false;
 782
 783                         for (lane = 0; lane < (uint32_t)(lane_count); lane++) {
 784
 785                                 if (lt_settings->
 786                                 lane_settings[lane].VOLTAGE_SWING !=
 787                                 req_settings.lane_settings[lane].
 788                                 VOLTAGE_SWING ||
 789                                 lt_settings->lane_settings[lane].PRE_EMPHASIS !=
 790                                 req_settings.lane_settings[lane].PRE_EMPHASIS) {
 791
 792                                         req_drv_setting_changed = true;
 793                                         break;
 794                                 }
 795                         }
 796
 797                         if (req_drv_setting_changed) {
 798                                 update_drive_settings(
 799                                         lt_settings, req_settings);
 800
 801                                 dc_link_dp_set_drive_settings(link,
 802                                                 lt_settings);
 803                                 break;
 804                         }
 805
 806                         msleep(1);
 807                 }
 808
 809                 if (!req_drv_setting_changed) {
 810                         DC_LOG_WARNING("%s: Post Link Training Adjust Request Timed out\n",
 811                                 __func__);
 812
 813                         ASSERT(0);
 814                         return true;
 815                 }
 816         }
 817         DC_LOG_WARNING("%s: Post Link Training Adjust Request limit reached\n",
 818                 __func__);
 819
 820         ASSERT(0);
 821         return true;
 822
 823 }
 824
 825 /* Only used for channel equalization */
 826 static uint32_t translate_training_aux_read_interval(uint32_t dpcd_aux_read_interval)
 827 {
 828         unsigned int aux_rd_interval_us = 400;
 829
 830         switch (dpcd_aux_read_interval) {
 831         case 0x01:
 832                 aux_rd_interval_us = 400;
 833                 break;
 834         case 0x02:
 835                 aux_rd_interval_us = 4000;
 836                 break;
 837         case 0x03:
 838                 aux_rd_interval_us = 8000;
 839                 break;
 840         case 0x04:
 841                 aux_rd_interval_us = 16000;
 842                 break;
 843         default:
 844                 break;
 845         }
 846
 847         return aux_rd_interval_us;
 848 }
 849
 850 static enum link_training_result get_cr_failure(enum dc_lane_count ln_count,
 851                                         union lane_status *dpcd_lane_status)
 852 {
 853         enum link_training_result result = LINK_TRAINING_SUCCESS;
 854
 855         if (ln_count >= LANE_COUNT_ONE && !dpcd_lane_status[0].bits.CR_DONE_0)
 856                 result = LINK_TRAINING_CR_FAIL_LANE0;
 857         else if (ln_count >= LANE_COUNT_TWO && !dpcd_lane_status[1].bits.CR_DONE_0)
 858                 result = LINK_TRAINING_CR_FAIL_LANE1;
 859         else if (ln_count >= LANE_COUNT_FOUR && !dpcd_lane_status[2].bits.CR_DONE_0)
 860                 result = LINK_TRAINING_CR_FAIL_LANE23;
 861         else if (ln_count >= LANE_COUNT_FOUR && !dpcd_lane_status[3].bits.CR_DONE_0)
 862                 result = LINK_TRAINING_CR_FAIL_LANE23;
 863         return result;
 864 }
 865
 866 static enum link_training_result perform_channel_equalization_sequence(
 867         struct dc_link *link,
 868         struct link_training_settings *lt_settings,
 869         uint32_t offset)
 870 {
 871         struct link_training_settings req_settings;
 872         enum dc_dp_training_pattern tr_pattern;
 873         uint32_t retries_ch_eq;
 874         uint32_t wait_time_microsec;
 875         enum dc_lane_count lane_count = lt_settings->link_settings.lane_count;
 876         union lane_align_status_updated dpcd_lane_status_updated = { {0} };
 877         union lane_status dpcd_lane_status[LANE_COUNT_DP_MAX] = { { {0} } };
 878
 879         /* Note: also check that TPS4 is a supported feature*/
 880
 881         tr_pattern = lt_settings->pattern_for_eq;
 882
 883         if (is_repeater(link, offset))
 884                 tr_pattern = DP_TRAINING_PATTERN_SEQUENCE_4;
 885
 886         dp_set_hw_training_pattern(link, tr_pattern, offset);
 887
 888         for (retries_ch_eq = 0; retries_ch_eq <= LINK_TRAINING_MAX_RETRY_COUNT;
 889                 retries_ch_eq++) {
 890
 891                 dp_set_hw_lane_settings(link, lt_settings, offset);
 892
 893                 /* 2. update DPCD*/
 894                 if (!retries_ch_eq)
 895                         /* EPR #361076 - write as a 5-byte burst,
 896                          * but only for the 1-st iteration
 897                          */
 898
 899                         dpcd_set_lt_pattern_and_lane_settings(
 900                                 link,
 901                                 lt_settings,
 902                                 tr_pattern, offset);
 903                 else
 904                         dpcd_set_lane_settings(link, lt_settings, offset);
 905
 906                 /* 3. wait for receiver to lock-on*/
 907                 wait_time_microsec = lt_settings->eq_pattern_time;
 908
 909                 if (is_repeater(link, offset))
 910                         wait_time_microsec =
 911                                         translate_training_aux_read_interval(
 912                                                 link->dpcd_caps.lttpr_caps.aux_rd_interval[offset - 1]);
 913
 914                 wait_for_training_aux_rd_interval(
 915                                 link,
 916                                 wait_time_microsec);
 917
 918                 /* 4. Read lane status and requested
 919                  * drive settings as set by the sink*/
 920
 921                 get_lane_status_and_drive_settings(
 922                         link,
 923                         lt_settings,
 924                         dpcd_lane_status,
 925                         &dpcd_lane_status_updated,
 926                         &req_settings,
 927                         offset);
 928
 929                 /* 5. check CR done*/
 930                 if (!is_cr_done(lane_count, dpcd_lane_status))
 931                         return LINK_TRAINING_EQ_FAIL_CR;
 932
 933                 /* 6. check CHEQ done*/
 934                 if (is_ch_eq_done(lane_count,
 935                         dpcd_lane_status,
 936                         &dpcd_lane_status_updated))
 937                         return LINK_TRAINING_SUCCESS;
 938
 939                 /* 7. update VS/PE/PC2 in lt_settings*/
 940                 update_drive_settings(lt_settings, req_settings);
 941         }
 942
 943         return LINK_TRAINING_EQ_FAIL_EQ;
 944
 945 }
 946 #define TRAINING_AUX_RD_INTERVAL 100 //us
 947
 948 static enum link_training_result perform_clock_recovery_sequence(
 949         struct dc_link *link,
 950         struct link_training_settings *lt_settings,
 951         uint32_t offset)
 952 {
 953         uint32_t retries_cr;
 954         uint32_t retry_count;
 955         uint32_t wait_time_microsec;
 956         struct link_training_settings req_settings;
 957         enum dc_lane_count lane_count = lt_settings->link_settings.lane_count;
 958         enum dc_dp_training_pattern tr_pattern = DP_TRAINING_PATTERN_SEQUENCE_1;
 959         union lane_status dpcd_lane_status[LANE_COUNT_DP_MAX];
 960         union lane_align_status_updated dpcd_lane_status_updated;
 961
 962         retries_cr = 0;
 963         retry_count = 0;
 964
 965         dp_set_hw_training_pattern(link, tr_pattern, offset);
 966
 967         /* najeeb - The synaptics MST hub can put the LT in
 968         * infinite loop by switching the VS
 969         */
 970         /* between level 0 and level 1 continuously, here
 971         * we try for CR lock for LinkTrainingMaxCRRetry count*/
 972         while ((retries_cr < LINK_TRAINING_MAX_RETRY_COUNT) &&
 973                 (retry_count < LINK_TRAINING_MAX_CR_RETRY)) {
 974
 975                 memset(&dpcd_lane_status, '\0', sizeof(dpcd_lane_status));
 976                 memset(&dpcd_lane_status_updated, '\0',
 977                 sizeof(dpcd_lane_status_updated));
 978
 979                 /* 1. call HWSS to set lane settings*/
 980                 dp_set_hw_lane_settings(
 981                                 link,
 982                                 lt_settings,
 983                                 offset);
 984
 985                 /* 2. update DPCD of the receiver*/
 986                 if (!retry_count)
 987                         /* EPR #361076 - write as a 5-byte burst,
 988                          * but only for the 1-st iteration.*/
 989                         dpcd_set_lt_pattern_and_lane_settings(
 990                                         link,
 991                                         lt_settings,
 992                                         tr_pattern,
 993                                         offset);
 994                 else
 995                         dpcd_set_lane_settings(
 996                                         link,
 997                                         lt_settings,
 998                                         offset);
 999
1000                 /* 3. wait receiver to lock-on*/
1001                 wait_time_microsec = lt_settings->cr_pattern_time;
1002
1003                 if (!link->is_lttpr_mode_transparent)
1004                         wait_time_microsec = TRAINING_AUX_RD_INTERVAL;
1005
1006                 wait_for_training_aux_rd_interval(
1007                                 link,
1008                                 wait_time_microsec);
1009
1010                 /* 4. Read lane status and requested drive
1011                 * settings as set by the sink
1012                 */
1013                 get_lane_status_and_drive_settings(
1014                                 link,
1015                                 lt_settings,
1016                                 dpcd_lane_status,
1017                                 &dpcd_lane_status_updated,
1018                                 &req_settings,
1019                                 offset);
1020
1021                 /* 5. check CR done*/
1022                 if (is_cr_done(lane_count, dpcd_lane_status))
1023                         return LINK_TRAINING_SUCCESS;
1024
1025                 /* 6. max VS reached*/
1026                 if (is_max_vs_reached(lt_settings))
1027                         break;
1028
1029                 /* 7. same voltage*/
1030                 /* Note: VS same for all lanes,
1031                 * so comparing first lane is sufficient*/
1032                 if (lt_settings->lane_settings[0].VOLTAGE_SWING ==
1033                         req_settings.lane_settings[0].VOLTAGE_SWING)
1034                         retries_cr++;
1035                 else
1036                         retries_cr = 0;
1037
1038                 /* 8. update VS/PE/PC2 in lt_settings*/
1039                 update_drive_settings(lt_settings, req_settings);
1040
1041                 retry_count++;
1042         }
1043
1044         if (retry_count >= LINK_TRAINING_MAX_CR_RETRY) {
1045                 ASSERT(0);
1046                 DC_LOG_ERROR("%s: Link Training Error, could not get CR after %d tries. Possibly voltage swing issue",
1047                         __func__,
1048                         LINK_TRAINING_MAX_CR_RETRY);
1049
1050         }
1051
1052         return get_cr_failure(lane_count, dpcd_lane_status);
1053 }
1054
1055 static inline enum link_training_result perform_link_training_int(
1056         struct dc_link *link,
1057         struct link_training_settings *lt_settings,
1058         enum link_training_result status)
1059 {
1060         union lane_count_set lane_count_set = { {0} };
1061         union dpcd_training_pattern dpcd_pattern = { {0} };
1062
1063         /* 3. set training not in progress*/
1064         dpcd_pattern.v1_4.TRAINING_PATTERN_SET = DPCD_TRAINING_PATTERN_VIDEOIDLE;
1065         dpcd_set_training_pattern(link, dpcd_pattern);
1066
1067         /* 4. mainlink output idle pattern*/
1068         dp_set_hw_test_pattern(link, DP_TEST_PATTERN_VIDEO_MODE, NULL, 0);
1069
1070         /*
1071          * 5. post training adjust if required
1072          * If the upstream DPTX and downstream DPRX both support TPS4,
1073          * TPS4 must be used instead of POST_LT_ADJ_REQ.
1074          */
1075         if (link->dpcd_caps.max_ln_count.bits.POST_LT_ADJ_REQ_SUPPORTED != 1 ||
1076                         get_supported_tp(link) == DP_TRAINING_PATTERN_SEQUENCE_4)
1077                 return status;
1078
1079         if (status == LINK_TRAINING_SUCCESS &&
1080                 perform_post_lt_adj_req_sequence(link, lt_settings) == false)
1081                 status = LINK_TRAINING_LQA_FAIL;
1082
1083         lane_count_set.bits.LANE_COUNT_SET = lt_settings->link_settings.lane_count;
1084         lane_count_set.bits.ENHANCED_FRAMING = lt_settings->enhanced_framing;
1085         lane_count_set.bits.POST_LT_ADJ_REQ_GRANTED = 0;
1086
1087         core_link_write_dpcd(
1088                 link,
1089                 DP_LANE_COUNT_SET,
1090                 &lane_count_set.raw,
1091                 sizeof(lane_count_set));
1092
1093         return status;
1094 }
1095
1096 static void initialize_training_settings(
1097          struct dc_link *link,
1098         const struct dc_link_settings *link_setting,
1099         const struct dc_link_training_overrides *overrides,
1100         struct link_training_settings *lt_settings)
1101 {
1102         uint32_t lane;
1103
1104         memset(lt_settings, '\0', sizeof(struct link_training_settings));
1105
1106         /* Initialize link settings */
1107         lt_settings->link_settings.use_link_rate_set = link_setting->use_link_rate_set;
1108         lt_settings->link_settings.link_rate_set = link_setting->link_rate_set;
1109
1110         if (link->preferred_link_setting.link_rate != LINK_RATE_UNKNOWN)
1111                 lt_settings->link_settings.link_rate = link->preferred_link_setting.link_rate;
1112         else
1113                 lt_settings->link_settings.link_rate = link_setting->link_rate;
1114
1115         if (link->preferred_link_setting.lane_count != LANE_COUNT_UNKNOWN)
1116                 lt_settings->link_settings.lane_count = link->preferred_link_setting.lane_count;
1117         else
1118                 lt_settings->link_settings.lane_count = link_setting->lane_count;
1119
1120         /*@todo[vdevulap] move SS to LS, should not be handled by displaypath*/
1121
1122         /* TODO hard coded to SS for now
1123          * lt_settings.link_settings.link_spread =
1124          * dal_display_path_is_ss_supported(
1125          * path_mode->display_path) ?
1126          * LINK_SPREAD_05_DOWNSPREAD_30KHZ :
1127          * LINK_SPREAD_DISABLED;
1128          */
1129         /* Initialize link spread */
1130         if (link->dp_ss_off)
1131                 lt_settings->link_settings.link_spread = LINK_SPREAD_DISABLED;
1132         else if (overrides->downspread != NULL)
1133                 lt_settings->link_settings.link_spread
1134                         = *overrides->downspread
1135                         ? LINK_SPREAD_05_DOWNSPREAD_30KHZ
1136                         : LINK_SPREAD_DISABLED;
1137         else
1138                 lt_settings->link_settings.link_spread = LINK_SPREAD_05_DOWNSPREAD_30KHZ;
1139
1140         /* Initialize lane settings overrides */
1141         if (overrides->voltage_swing != NULL)
1142                 lt_settings->voltage_swing = overrides->voltage_swing;
1143
1144         if (overrides->pre_emphasis != NULL)
1145                 lt_settings->pre_emphasis = overrides->pre_emphasis;
1146
1147         if (overrides->post_cursor2 != NULL)
1148                 lt_settings->post_cursor2 = overrides->post_cursor2;
1149
1150         /* Initialize lane settings (VS/PE/PC2) */
1151         for (lane = 0; lane < LANE_COUNT_DP_MAX; lane++) {
1152                 lt_settings->lane_settings[lane].VOLTAGE_SWING =
1153                         lt_settings->voltage_swing != NULL ?
1154                         *lt_settings->voltage_swing :
1155                         VOLTAGE_SWING_LEVEL0;
1156                 lt_settings->lane_settings[lane].PRE_EMPHASIS =
1157                         lt_settings->pre_emphasis != NULL ?
1158                         *lt_settings->pre_emphasis
1159                         : PRE_EMPHASIS_DISABLED;
1160                 lt_settings->lane_settings[lane].POST_CURSOR2 =
1161                         lt_settings->post_cursor2 != NULL ?
1162                         *lt_settings->post_cursor2
1163                         : POST_CURSOR2_DISABLED;
1164         }
1165
1166         /* Initialize training timings */
1167         if (overrides->cr_pattern_time != NULL)
1168                 lt_settings->cr_pattern_time = *overrides->cr_pattern_time;
1169         else
1170                 lt_settings->cr_pattern_time = get_training_aux_rd_interval(link, 100);
1171
1172         if (overrides->eq_pattern_time != NULL)
1173                 lt_settings->eq_pattern_time = *overrides->eq_pattern_time;
1174         else
1175                 lt_settings->eq_pattern_time = get_training_aux_rd_interval(link, 400);
1176
1177         if (overrides->pattern_for_eq != NULL)
1178                 lt_settings->pattern_for_eq = *overrides->pattern_for_eq;
1179         else
1180                 lt_settings->pattern_for_eq = get_supported_tp(link);
1181
1182         if (overrides->enhanced_framing != NULL)
1183                 lt_settings->enhanced_framing = *overrides->enhanced_framing;
1184         else
1185                 lt_settings->enhanced_framing = 1;
1186 }
1187
1188 static uint8_t convert_to_count(uint8_t lttpr_repeater_count)
1189 {
1190         switch (lttpr_repeater_count) {
1191         case 0x80: // 1 lttpr repeater
1192                 return 1;
1193         case 0x40: // 2 lttpr repeaters
1194                 return 2;
1195         case 0x20: // 3 lttpr repeaters
1196                 return 3;
1197         case 0x10: // 4 lttpr repeaters
1198                 return 4;
1199         case 0x08: // 5 lttpr repeaters
1200                 return 5;
1201         case 0x04: // 6 lttpr repeaters
1202                 return 6;
1203         case 0x02: // 7 lttpr repeaters
1204                 return 7;
1205         case 0x01: // 8 lttpr repeaters
1206                 return 8;
1207         default:
1208                 break;
1209         }
1210         return 0; // invalid value
1211 }
1212
1213 static void configure_lttpr_mode(struct dc_link *link)
1214 {
1215         /* aux timeout is already set to extended */
1216         /* RESET/SET lttpr mode to enable non transparent mode */
1217         uint8_t repeater_cnt;
1218         uint32_t aux_interval_address;
1219         uint8_t repeater_id;
1220         enum dc_status result = DC_ERROR_UNEXPECTED;
1221         uint8_t repeater_mode = DP_PHY_REPEATER_MODE_TRANSPARENT;
1222
1223         DC_LOG_HW_LINK_TRAINING("%s\n Set LTTPR to Transparent Mode\n", __func__);
1224         result = core_link_write_dpcd(link,
1225                         DP_PHY_REPEATER_MODE,
1226                         (uint8_t *)&repeater_mode,
1227                         sizeof(repeater_mode));
1228
1229         if (result == DC_OK) {
1230                 link->dpcd_caps.lttpr_caps.mode = repeater_mode;
1231         }
1232
1233         if (!link->is_lttpr_mode_transparent) {
1234
1235                 DC_LOG_HW_LINK_TRAINING("%s\n Set LTTPR to Non Transparent Mode\n", __func__);
1236
1237                 repeater_mode = DP_PHY_REPEATER_MODE_NON_TRANSPARENT;
1238                 result = core_link_write_dpcd(link,
1239                                 DP_PHY_REPEATER_MODE,
1240                                 (uint8_t *)&repeater_mode,
1241                                 sizeof(repeater_mode));
1242
1243                 if (result == DC_OK) {
1244                         link->dpcd_caps.lttpr_caps.mode = repeater_mode;
1245                 }
1246
1247                 repeater_cnt = convert_to_count(link->dpcd_caps.lttpr_caps.phy_repeater_cnt);
1248                 for (repeater_id = repeater_cnt; repeater_id > 0; repeater_id--) {
1249                         aux_interval_address = DP_TRAINING_AUX_RD_INTERVAL_PHY_REPEATER1 +
1250                                                 ((DP_REPEATER_CONFIGURATION_AND_STATUS_SIZE) * (repeater_id - 1));
1251                         core_link_read_dpcd(
1252                                 link,
1253                                 aux_interval_address,
1254                                 (uint8_t *)&link->dpcd_caps.lttpr_caps.aux_rd_interval[repeater_id - 1],
1255                                 sizeof(link->dpcd_caps.lttpr_caps.aux_rd_interval[repeater_id - 1]));
1256                         link->dpcd_caps.lttpr_caps.aux_rd_interval[repeater_id - 1] &= 0x7F;
1257                 }
1258         }
1259 }
1260
1261 static void repeater_training_done(struct dc_link *link, uint32_t offset)
1262 {
1263         union dpcd_training_pattern dpcd_pattern = { {0} };
1264
1265         const uint32_t dpcd_base_lt_offset =
1266                         DP_TRAINING_PATTERN_SET_PHY_REPEATER1 +
1267                                 ((DP_REPEATER_CONFIGURATION_AND_STATUS_SIZE) * (offset - 1));
1268         /* Set training not in progress*/
1269         dpcd_pattern.v1_4.TRAINING_PATTERN_SET = DPCD_TRAINING_PATTERN_VIDEOIDLE;
1270
1271         core_link_write_dpcd(
1272                 link,
1273                 dpcd_base_lt_offset,
1274                 &dpcd_pattern.raw,
1275                 1);
1276
1277         DC_LOG_HW_LINK_TRAINING("%s\n LTTPR Id: %d 0x%X pattern = %x\n",
1278                 __func__,
1279                 offset,
1280                 dpcd_base_lt_offset,
1281                 dpcd_pattern.v1_4.TRAINING_PATTERN_SET);
1282 }
1283
1284 static void print_status_message(
1285         struct dc_link *link,
1286         const struct link_training_settings *lt_settings,
1287         enum link_training_result status)
1288 {
1289         char *link_rate = "Unknown";
1290         char *lt_result = "Unknown";
1291         char *lt_spread = "Disabled";
1292
1293         switch (lt_settings->link_settings.link_rate) {
1294         case LINK_RATE_LOW:
1295                 link_rate = "RBR";
1296                 break;
1297         case LINK_RATE_HIGH:
1298                 link_rate = "HBR";
1299                 break;
1300         case LINK_RATE_HIGH2:
1301                 link_rate = "HBR2";
1302                 break;
1303         case LINK_RATE_RBR2:
1304                 link_rate = "RBR2";
1305                 break;
1306         case LINK_RATE_HIGH3:
1307                 link_rate = "HBR3";
1308                 break;
1309         default:
1310                 break;
1311         }
1312
1313         switch (status) {
1314         case LINK_TRAINING_SUCCESS:
1315                 lt_result = "pass";
1316                 break;
1317         case LINK_TRAINING_CR_FAIL_LANE0:
1318                 lt_result = "CR failed lane0";
1319                 break;
1320         case LINK_TRAINING_CR_FAIL_LANE1:
1321                 lt_result = "CR failed lane1";
1322                 break;
1323         case LINK_TRAINING_CR_FAIL_LANE23:
1324                 lt_result = "CR failed lane23";
1325                 break;
1326         case LINK_TRAINING_EQ_FAIL_CR:
1327                 lt_result = "CR failed in EQ";
1328                 break;
1329         case LINK_TRAINING_EQ_FAIL_EQ:
1330                 lt_result = "EQ failed";
1331                 break;
1332         case LINK_TRAINING_LQA_FAIL:
1333                 lt_result = "LQA failed";
1334                 break;
1335         default:
1336                 break;
1337         }
1338
1339         switch (lt_settings->link_settings.link_spread) {
1340         case LINK_SPREAD_DISABLED:
1341                 lt_spread = "Disabled";
1342                 break;
1343         case LINK_SPREAD_05_DOWNSPREAD_30KHZ:
1344                 lt_spread = "0.5% 30KHz";
1345                 break;
1346         case LINK_SPREAD_05_DOWNSPREAD_33KHZ:
1347                 lt_spread = "0.5% 33KHz";
1348                 break;
1349         default:
1350                 break;
1351         }
1352
1353         /* Connectivity log: link training */
1354         CONN_MSG_LT(link, "%sx%d %s VS=%d, PE=%d, DS=%s",
1355                                 link_rate,
1356                                 lt_settings->link_settings.lane_count,
1357                                 lt_result,
1358                                 lt_settings->lane_settings[0].VOLTAGE_SWING,
1359                                 lt_settings->lane_settings[0].PRE_EMPHASIS,
1360                                 lt_spread);
1361 }
1362
1363 void dc_link_dp_set_drive_settings(
1364         struct dc_link *link,
1365         struct link_training_settings *lt_settings)
1366 {
1367         /* program ASIC PHY settings*/
1368         dp_set_hw_lane_settings(link, lt_settings, DPRX);
1369
1370         /* Notify DP sink the PHY settings from source */
1371         dpcd_set_lane_settings(link, lt_settings, DPRX);
1372 }
1373
1374 bool dc_link_dp_perform_link_training_skip_aux(
1375         struct dc_link *link,
1376         const struct dc_link_settings *link_setting)
1377 {
1378         struct link_training_settings lt_settings;
1379         enum dc_dp_training_pattern pattern_for_cr = DP_TRAINING_PATTERN_SEQUENCE_1;
1380
1381         initialize_training_settings(
1382                         link,
1383                         link_setting,
1384                         &link->preferred_training_settings,
1385                         &lt_settings);
1386
1387         /* 1. Perform_clock_recovery_sequence. */
1388
1389         /* transmit training pattern for clock recovery */
1390         dp_set_hw_training_pattern(link, pattern_for_cr, DPRX);
1391
1392         /* call HWSS to set lane settings*/
1393         dp_set_hw_lane_settings(link, &lt_settings, DPRX);
1394
1395         /* wait receiver to lock-on*/
1396         wait_for_training_aux_rd_interval(link, lt_settings.cr_pattern_time);
1397
1398         /* 2. Perform_channel_equalization_sequence. */
1399
1400         /* transmit training pattern for channel equalization. */
1401         dp_set_hw_training_pattern(link, lt_settings.pattern_for_eq, DPRX);
1402
1403         /* call HWSS to set lane settings*/
1404         dp_set_hw_lane_settings(link, &lt_settings, DPRX);
1405
1406         /* wait receiver to lock-on. */
1407         wait_for_training_aux_rd_interval(link, lt_settings.eq_pattern_time);
1408
1409         /* 3. Perform_link_training_int. */
1410
1411         /* Mainlink output idle pattern. */
1412         dp_set_hw_test_pattern(link, DP_TEST_PATTERN_VIDEO_MODE, NULL, 0);
1413
1414         print_status_message(link, &lt_settings, LINK_TRAINING_SUCCESS);
1415
1416         return true;
1417 }
1418
1419 enum link_training_result dc_link_dp_perform_link_training(
1420         struct dc_link *link,
1421         const struct dc_link_settings *link_setting,
1422         bool skip_video_pattern)
1423 {
1424         enum link_training_result status = LINK_TRAINING_SUCCESS;
1425         struct link_training_settings lt_settings;
1426
1427         bool fec_enable;
1428         uint8_t repeater_cnt;
1429         uint8_t repeater_id;
1430
1431         initialize_training_settings(
1432                         link,
1433                         link_setting,
1434                         &link->preferred_training_settings,
1435                         &lt_settings);
1436
1437         /* 1. set link rate, lane count and spread. */
1438         dpcd_set_link_settings(link, &lt_settings);
1439
1440         if (link->preferred_training_settings.fec_enable != NULL)
1441                 fec_enable = *link->preferred_training_settings.fec_enable;
1442         else
1443                 fec_enable = true;
1444
1445         dp_set_fec_ready(link, fec_enable);
1446
1447         if (!link->is_lttpr_mode_transparent) {
1448                 /* Configure lttpr mode */
1449                 configure_lttpr_mode(link);
1450
1451                 /* 2. perform link training (set link training done
1452                  *  to false is done as well)
1453                  */
1454                 repeater_cnt = convert_to_count(link->dpcd_caps.lttpr_caps.phy_repeater_cnt);
1455
1456                 for (repeater_id = repeater_cnt; (repeater_id > 0 && status == LINK_TRAINING_SUCCESS);
1457                                 repeater_id--) {
1458                         status = perform_clock_recovery_sequence(link, &lt_settings, repeater_id);
1459
1460                         if (status != LINK_TRAINING_SUCCESS)
1461                                 break;
1462
1463                         status = perform_channel_equalization_sequence(link,
1464                                         &lt_settings,
1465                                         repeater_id);
1466
1467                         if (status != LINK_TRAINING_SUCCESS)
1468                                 break;
1469
1470                         repeater_training_done(link, repeater_id);
1471                 }
1472         }
1473
1474         if (status == LINK_TRAINING_SUCCESS) {
1475                 status = perform_clock_recovery_sequence(link, &lt_settings, DPRX);
1476         if (status == LINK_TRAINING_SUCCESS) {
1477                 status = perform_channel_equalization_sequence(link,
1478                                         &lt_settings,
1479                                         DPRX);
1480                 }
1481         }
1482
1483         if ((status == LINK_TRAINING_SUCCESS) || !skip_video_pattern) {
1484                 status = perform_link_training_int(link,
1485                                 &lt_settings,
1486                                 status);
1487         }
1488
1489         /* 6. print status message*/
1490         print_status_message(link, &lt_settings, status);
1491
1492         if (status != LINK_TRAINING_SUCCESS)
1493                 link->ctx->dc->debug_data.ltFailCount++;
1494
1495         return status;
1496 }
1497
1498 bool perform_link_training_with_retries(
1499         const struct dc_link_settings *link_setting,
1500         bool skip_video_pattern,
1501         int attempts,
1502         struct pipe_ctx *pipe_ctx,
1503         enum signal_type signal)
1504 {
1505         uint8_t j;
1506         uint8_t delay_between_attempts = LINK_TRAINING_RETRY_DELAY;
1507         struct dc_stream_state *stream = pipe_ctx->stream;
1508         struct dc_link *link = stream->link;
1509         enum dp_panel_mode panel_mode = dp_get_panel_mode(link);
1510
1511         for (j = 0; j < attempts; ++j) {
1512
1513                 dp_enable_link_phy(
1514                         link,
1515                         signal,
1516                         pipe_ctx->clock_source->id,
1517                         link_setting);
1518
1519                 if (stream->sink_patches.dppowerup_delay > 0) {
1520                         int delay_dp_power_up_in_ms = stream->sink_patches.dppowerup_delay;
1521
1522                         msleep(delay_dp_power_up_in_ms);
1523                 }
1524
1525                 dp_set_panel_mode(link, panel_mode);
1526
1527                 /* We need to do this before the link training to ensure the idle pattern in SST
1528                  * mode will be sent right after the link training
1529                  */
1530                 link->link_enc->funcs->connect_dig_be_to_fe(link->link_enc,
1531                                                                 pipe_ctx->stream_res.stream_enc->id, true);
1532
1533                 if (link->aux_access_disabled) {
1534                         dc_link_dp_perform_link_training_skip_aux(link, link_setting);
1535                         return true;
1536                 } else if (dc_link_dp_perform_link_training(
1537                                 link,
1538                                 link_setting,
1539                                 skip_video_pattern) == LINK_TRAINING_SUCCESS)
1540                         return true;
1541
1542                 /* latest link training still fail, skip delay and keep PHY on
1543                  */
1544                 if (j == (attempts - 1))
1545                         break;
1546
1547                 dp_disable_link_phy(link, signal);
1548
1549                 msleep(delay_between_attempts);
1550
1551                 delay_between_attempts += LINK_TRAINING_RETRY_DELAY;
1552         }
1553
1554         return false;
1555 }
1556
1557 static enum clock_source_id get_clock_source_id(struct dc_link *link)
1558 {
1559         enum clock_source_id dp_cs_id = CLOCK_SOURCE_ID_UNDEFINED;
1560         struct clock_source *dp_cs = link->dc->res_pool->dp_clock_source;
1561
1562         if (dp_cs != NULL) {
1563                 dp_cs_id = dp_cs->id;
1564         } else {
1565                 /*
1566                  * dp clock source is not initialized for some reason.
1567                  * Should not happen, CLOCK_SOURCE_ID_EXTERNAL will be used
1568                  */
1569                 ASSERT(dp_cs);
1570         }
1571
1572         return dp_cs_id;
1573 }
1574
1575 static void set_dp_mst_mode(struct dc_link *link, bool mst_enable)
1576 {
1577         if (mst_enable == false &&
1578                 link->type == dc_connection_mst_branch) {
1579                 /* Disable MST on link. Use only local sink. */
1580                 dp_disable_link_phy_mst(link, link->connector_signal);
1581
1582                 link->type = dc_connection_single;
1583                 link->local_sink = link->remote_sinks[0];
1584                 link->local_sink->sink_signal = SIGNAL_TYPE_DISPLAY_PORT;
1585         } else if (mst_enable == true &&
1586                         link->type == dc_connection_single &&
1587                         link->remote_sinks[0] != NULL) {
1588                 /* Re-enable MST on link. */
1589                 dp_disable_link_phy(link, link->connector_signal);
1590                 dp_enable_mst_on_sink(link, true);
1591
1592                 link->type = dc_connection_mst_branch;
1593                 link->local_sink->sink_signal = SIGNAL_TYPE_DISPLAY_PORT_MST;
1594         }
1595 }
1596
1597 bool dc_link_dp_sync_lt_begin(struct dc_link *link)
1598 {
1599         /* Begin Sync LT. During this time,
1600          * DPCD:600h must not be powered down.
1601          */
1602         link->sync_lt_in_progress = true;
1603
1604         /*Clear any existing preferred settings.*/
1605         memset(&link->preferred_training_settings, 0,
1606                 sizeof(struct dc_link_training_overrides));
1607         memset(&link->preferred_link_setting, 0,
1608                 sizeof(struct dc_link_settings));
1609
1610         return true;
1611 }
1612
1613 enum link_training_result dc_link_dp_sync_lt_attempt(
1614     struct dc_link *link,
1615     struct dc_link_settings *link_settings,
1616     struct dc_link_training_overrides *lt_overrides)
1617 {
1618         struct link_training_settings lt_settings;
1619         enum link_training_result lt_status = LINK_TRAINING_SUCCESS;
1620         enum dp_panel_mode panel_mode = DP_PANEL_MODE_DEFAULT;
1621         enum clock_source_id dp_cs_id = CLOCK_SOURCE_ID_EXTERNAL;
1622         bool fec_enable = false;
1623
1624         initialize_training_settings(
1625                 link,
1626                 link_settings,
1627                 lt_overrides,
1628                 &lt_settings);
1629
1630         /* Setup MST Mode */
1631         if (lt_overrides->mst_enable)
1632                 set_dp_mst_mode(link, *lt_overrides->mst_enable);
1633
1634         /* Disable link */
1635         dp_disable_link_phy(link, link->connector_signal);
1636
1637         /* Enable link */
1638         dp_cs_id = get_clock_source_id(link);
1639         dp_enable_link_phy(link, link->connector_signal,
1640                 dp_cs_id, link_settings);
1641
1642         /* Set FEC enable */
1643         fec_enable = lt_overrides->fec_enable && *lt_overrides->fec_enable;
1644         dp_set_fec_ready(link, fec_enable);
1645
1646         if (lt_overrides->alternate_scrambler_reset) {
1647                 if (*lt_overrides->alternate_scrambler_reset)
1648                         panel_mode = DP_PANEL_MODE_EDP;
1649                 else
1650                         panel_mode = DP_PANEL_MODE_DEFAULT;
1651         } else
1652                 panel_mode = dp_get_panel_mode(link);
1653
1654         dp_set_panel_mode(link, panel_mode);
1655
1656         /* Attempt to train with given link training settings */
1657
1658         /* Set link rate, lane count and spread. */
1659         dpcd_set_link_settings(link, &lt_settings);
1660
1661         /* 2. perform link training (set link training done
1662          *  to false is done as well)
1663          */
1664         lt_status = perform_clock_recovery_sequence(link, &lt_settings, DPRX);
1665         if (lt_status == LINK_TRAINING_SUCCESS) {
1666                 lt_status = perform_channel_equalization_sequence(link,
1667                                                 &lt_settings,
1668                                                 DPRX);
1669         }
1670
1671         /* 3. Sync LT must skip TRAINING_PATTERN_SET:0 (video pattern)*/
1672         /* 4. print status message*/
1673         print_status_message(link, &lt_settings, lt_status);
1674
1675         return lt_status;
1676 }
1677
1678 bool dc_link_dp_sync_lt_end(struct dc_link *link, bool link_down)
1679 {
1680         /* If input parameter is set, shut down phy.
1681          * Still shouldn't turn off dp_receiver (DPCD:600h)
1682          */
1683         if (link_down == true) {
1684                 dp_disable_link_phy(link, link->connector_signal);
1685                 dp_set_fec_ready(link, false);
1686         }
1687
1688         link->sync_lt_in_progress = false;
1689         return true;
1690 }
1691
1692 static struct dc_link_settings get_max_link_cap(struct dc_link *link)
1693 {
1694         /* Set Default link settings */
1695         struct dc_link_settings max_link_cap = {LANE_COUNT_FOUR, LINK_RATE_HIGH,
1696                         LINK_SPREAD_05_DOWNSPREAD_30KHZ, false, 0};
1697
1698         /* Higher link settings based on feature supported */
1699         if (link->link_enc->features.flags.bits.IS_HBR2_CAPABLE)
1700                 max_link_cap.link_rate = LINK_RATE_HIGH2;
1701
1702         if (link->link_enc->features.flags.bits.IS_HBR3_CAPABLE)
1703                 max_link_cap.link_rate = LINK_RATE_HIGH3;
1704
1705         if (link->link_enc->funcs->get_max_link_cap)
1706                 link->link_enc->funcs->get_max_link_cap(link->link_enc, &max_link_cap);
1707
1708         /* Lower link settings based on sink's link cap */
1709         if (link->reported_link_cap.lane_count < max_link_cap.lane_count)
1710                 max_link_cap.lane_count =
1711                                 link->reported_link_cap.lane_count;
1712         if (link->reported_link_cap.link_rate < max_link_cap.link_rate)
1713                 max_link_cap.link_rate =
1714                                 link->reported_link_cap.link_rate;
1715         if (link->reported_link_cap.link_spread <
1716                         max_link_cap.link_spread)
1717                 max_link_cap.link_spread =
1718                                 link->reported_link_cap.link_spread;
1719         /*
1720          * account for lttpr repeaters cap
1721          * notes: repeaters do not snoop in the DPRX Capabilities addresses (3.6.3).
1722          */
1723         if (!link->is_lttpr_mode_transparent) {
1724                 if (link->dpcd_caps.lttpr_caps.max_lane_count < max_link_cap.lane_count)
1725                         max_link_cap.lane_count = link->dpcd_caps.lttpr_caps.max_lane_count;
1726
1727                 if (link->dpcd_caps.lttpr_caps.max_link_rate < max_link_cap.link_rate)
1728                         max_link_cap.link_rate = link->dpcd_caps.lttpr_caps.max_link_rate;
1729
1730                 DC_LOG_HW_LINK_TRAINING("%s\n Training with LTTPR,  max_lane count %d max_link rate %d \n",
1731                                                 __func__,
1732                                                 max_link_cap.lane_count,
1733                                                 max_link_cap.link_rate);
1734         }
1735         return max_link_cap;
1736 }
1737
1738 static enum dc_status read_hpd_rx_irq_data(
1739         struct dc_link *link,
1740         union hpd_irq_data *irq_data)
1741 {
1742         static enum dc_status retval;
1743
1744         /* The HW reads 16 bytes from 200h on HPD,
1745          * but if we get an AUX_DEFER, the HW cannot retry
1746          * and this causes the CTS tests 4.3.2.1 - 3.2.4 to
1747          * fail, so we now explicitly read 6 bytes which is
1748          * the req from the above mentioned test cases.
1749          *
1750          * For DP 1.4 we need to read those from 2002h range.
1751          */
1752         if (link->dpcd_caps.dpcd_rev.raw < DPCD_REV_14)
1753                 retval = core_link_read_dpcd(
1754                         link,
1755                         DP_SINK_COUNT,
1756                         irq_data->raw,
1757                         sizeof(union hpd_irq_data));
1758         else {
1759                 /* Read 14 bytes in a single read and then copy only the required fields.
1760                  * This is more efficient than doing it in two separate AUX reads. */
1761
1762                 uint8_t tmp[DP_SINK_STATUS_ESI - DP_SINK_COUNT_ESI + 1];
1763
1764                 retval = core_link_read_dpcd(
1765                         link,
1766                         DP_SINK_COUNT_ESI,
1767                         tmp,
1768                         sizeof(tmp));
1769
1770                 if (retval != DC_OK)
1771                         return retval;
1772
1773                 irq_data->bytes.sink_cnt.raw = tmp[DP_SINK_COUNT_ESI - DP_SINK_COUNT_ESI];
1774                 irq_data->bytes.device_service_irq.raw = tmp[DP_DEVICE_SERVICE_IRQ_VECTOR_ESI0 - DP_SINK_COUNT_ESI];
1775                 irq_data->bytes.lane01_status.raw = tmp[DP_LANE0_1_STATUS_ESI - DP_SINK_COUNT_ESI];
1776                 irq_data->bytes.lane23_status.raw = tmp[DP_LANE2_3_STATUS_ESI - DP_SINK_COUNT_ESI];
1777                 irq_data->bytes.lane_status_updated.raw = tmp[DP_LANE_ALIGN_STATUS_UPDATED_ESI - DP_SINK_COUNT_ESI];
1778                 irq_data->bytes.sink_status.raw = tmp[DP_SINK_STATUS_ESI - DP_SINK_COUNT_ESI];
1779         }
1780
1781         return retval;
1782 }
1783
1784 static bool hpd_rx_irq_check_link_loss_status(
1785         struct dc_link *link,
1786         union hpd_irq_data *hpd_irq_dpcd_data)
1787 {
1788         uint8_t irq_reg_rx_power_state = 0;
1789         enum dc_status dpcd_result = DC_ERROR_UNEXPECTED;
1790         union lane_status lane_status;
1791         uint32_t lane;
1792         bool sink_status_changed;
1793         bool return_code;
1794
1795         sink_status_changed = false;
1796         return_code = false;
1797
1798         if (link->cur_link_settings.lane_count == 0)
1799                 return return_code;
1800
1801         /*1. Check that Link Status changed, before re-training.*/
1802
1803         /*parse lane status*/
1804         for (lane = 0; lane < link->cur_link_settings.lane_count; lane++) {
1805                 /* check status of lanes 0,1
1806                  * changed DpcdAddress_Lane01Status (0x202)
1807                  */
1808                 lane_status.raw = get_nibble_at_index(
1809                         &hpd_irq_dpcd_data->bytes.lane01_status.raw,
1810                         lane);
1811
1812                 if (!lane_status.bits.CHANNEL_EQ_DONE_0 ||
1813                         !lane_status.bits.CR_DONE_0 ||
1814                         !lane_status.bits.SYMBOL_LOCKED_0) {
1815                         /* if one of the channel equalization, clock
1816                          * recovery or symbol lock is dropped
1817                          * consider it as (link has been
1818                          * dropped) dp sink status has changed
1819                          */
1820                         sink_status_changed = true;
1821                         break;
1822                 }
1823         }
1824
1825         /* Check interlane align.*/
1826         if (sink_status_changed ||
1827                 !hpd_irq_dpcd_data->bytes.lane_status_updated.bits.INTERLANE_ALIGN_DONE) {
1828
1829                 DC_LOG_HW_HPD_IRQ("%s: Link Status changed.\n", __func__);
1830
1831                 return_code = true;
1832
1833                 /*2. Check that we can handle interrupt: Not in FS DOS,
1834                  *  Not in "Display Timeout" state, Link is trained.
1835                  */
1836                 dpcd_result = core_link_read_dpcd(link,
1837                         DP_SET_POWER,
1838                         &irq_reg_rx_power_state,
1839                         sizeof(irq_reg_rx_power_state));
1840
1841                 if (dpcd_result != DC_OK) {
1842                         DC_LOG_HW_HPD_IRQ("%s: DPCD read failed to obtain power state.\n",
1843                                 __func__);
1844                 } else {
1845                         if (irq_reg_rx_power_state != DP_SET_POWER_D0)
1846                                 return_code = false;
1847                 }
1848         }
1849
1850         return return_code;
1851 }
1852
1853 bool dp_verify_link_cap(
1854         struct dc_link *link,
1855         struct dc_link_settings *known_limit_link_setting,
1856         int *fail_count)
1857 {
1858         struct dc_link_settings max_link_cap = {0};
1859         struct dc_link_settings cur_link_setting = {0};
1860         struct dc_link_settings *cur = &cur_link_setting;
1861         struct dc_link_settings initial_link_settings = {0};
1862         bool success;
1863         bool skip_link_training;
1864         bool skip_video_pattern;
1865         enum clock_source_id dp_cs_id = CLOCK_SOURCE_ID_EXTERNAL;
1866         enum link_training_result status;
1867         union hpd_irq_data irq_data;
1868
1869         if (link->dc->debug.skip_detection_link_training) {
1870                 link->verified_link_cap = *known_limit_link_setting;
1871                 return true;
1872         }
1873
1874         memset(&irq_data, 0, sizeof(irq_data));
1875         success = false;
1876         skip_link_training = false;
1877
1878         max_link_cap = get_max_link_cap(link);
1879
1880         /* Grant extended timeout request */
1881         if (!link->is_lttpr_mode_transparent && link->dpcd_caps.lttpr_caps.max_ext_timeout > 0) {
1882                 uint8_t grant = link->dpcd_caps.lttpr_caps.max_ext_timeout & 0x80;
1883
1884                 core_link_write_dpcd(link, DP_PHY_REPEATER_EXTENDED_WAIT_TIMEOUT, &grant, sizeof(grant));
1885         }
1886
1887         /* TODO implement override and monitor patch later */
1888
1889         /* try to train the link from high to low to
1890          * find the physical link capability
1891          */
1892         /* disable PHY done possible by BIOS, will be done by driver itself */
1893         dp_disable_link_phy(link, link->connector_signal);
1894
1895         /* Temporary Renoir-specific workaround for SWDEV-215184;
1896          * PHY will sometimes be in bad state on hotplugging display from certain USB-C dongle,
1897          * so add extra cycle of enabling and disabling the PHY before first link training.
1898          */
1899         if (link->link_enc->features.flags.bits.DP_IS_USB_C &&
1900                         link->dc->debug.usbc_combo_phy_reset_wa) {
1901                 dp_enable_link_phy(link, link->connector_signal, dp_cs_id, cur);
1902                 dp_disable_link_phy(link, link->connector_signal);
1903         }
1904
1905         dp_cs_id = get_clock_source_id(link);
1906
1907         /* link training starts with the maximum common settings
1908          * supported by both sink and ASIC.
1909          */
1910         initial_link_settings = get_common_supported_link_settings(
1911                         *known_limit_link_setting,
1912                         max_link_cap);
1913         cur_link_setting = initial_link_settings;
1914         do {
1915                 skip_video_pattern = true;
1916
1917                 if (cur->link_rate == LINK_RATE_LOW)
1918                         skip_video_pattern = false;
1919
1920                 dp_enable_link_phy(
1921                                 link,
1922                                 link->connector_signal,
1923                                 dp_cs_id,
1924                                 cur);
1925
1926
1927                 if (skip_link_training)
1928                         success = true;
1929                 else {
1930                         status = dc_link_dp_perform_link_training(
1931                                                         link,
1932                                                         cur,
1933                                                         skip_video_pattern);
1934                         if (status == LINK_TRAINING_SUCCESS)
1935                                 success = true;
1936                         else
1937                                 (*fail_count)++;
1938                 }
1939
1940                 if (success) {
1941                         link->verified_link_cap = *cur;
1942                         udelay(1000);
1943                         if (read_hpd_rx_irq_data(link, &irq_data) == DC_OK)
1944                                 if (hpd_rx_irq_check_link_loss_status(
1945                                                 link,
1946                                                 &irq_data))
1947                                         (*fail_count)++;
1948                 }
1949                 /* always disable the link before trying another
1950                  * setting or before returning we'll enable it later
1951                  * based on the actual mode we're driving
1952                  */
1953                 dp_disable_link_phy(link, link->connector_signal);
1954         } while (!success && decide_fallback_link_setting(
1955                         initial_link_settings, cur, status));
1956
1957         /* Link Training failed for all Link Settings
1958          *  (Lane Count is still unknown)
1959          */
1960         if (!success) {
1961                 /* If all LT fails for all settings,
1962                  * set verified = failed safe (1 lane low)
1963                  */
1964                 link->verified_link_cap.lane_count = LANE_COUNT_ONE;
1965                 link->verified_link_cap.link_rate = LINK_RATE_LOW;
1966
1967                 link->verified_link_cap.link_spread =
1968                 LINK_SPREAD_DISABLED;
1969         }
1970
1971
1972         return success;
1973 }
1974
1975 bool dp_verify_link_cap_with_retries(
1976         struct dc_link *link,
1977         struct dc_link_settings *known_limit_link_setting,
1978         int attempts)
1979 {
1980         uint8_t i = 0;
1981         bool success = false;
1982
1983         for (i = 0; i < attempts; i++) {
1984                 int fail_count = 0;
1985                 enum dc_connection_type type = dc_connection_none;
1986
1987                 memset(&link->verified_link_cap, 0,
1988                                 sizeof(struct dc_link_settings));
1989                 if (!dc_link_detect_sink(link, &type) || type == dc_connection_none) {
1990                         link->verified_link_cap.lane_count = LANE_COUNT_ONE;
1991                         link->verified_link_cap.link_rate = LINK_RATE_LOW;
1992                         link->verified_link_cap.link_spread = LINK_SPREAD_DISABLED;
1993                         break;
1994                 } else if (dp_verify_link_cap(link,
1995                                 &link->reported_link_cap,
1996                                 &fail_count) && fail_count == 0) {
1997                         success = true;
1998                         break;
1999                 }
2000                 msleep(10);
2001         }
2002         return success;
2003 }
2004
2005 bool dp_verify_mst_link_cap(
2006         struct dc_link *link)
2007 {
2008         struct dc_link_settings max_link_cap = {0};
2009
2010         max_link_cap = get_max_link_cap(link);
2011         link->verified_link_cap = get_common_supported_link_settings(
2012                 link->reported_link_cap,
2013                 max_link_cap);
2014
2015         return true;
2016 }
2017
2018 static struct dc_link_settings get_common_supported_link_settings(
2019                 struct dc_link_settings link_setting_a,
2020                 struct dc_link_settings link_setting_b)
2021 {
2022         struct dc_link_settings link_settings = {0};
2023
2024         link_settings.lane_count =
2025                 (link_setting_a.lane_count <=
2026                         link_setting_b.lane_count) ?
2027                         link_setting_a.lane_count :
2028                         link_setting_b.lane_count;
2029         link_settings.link_rate =
2030                 (link_setting_a.link_rate <=
2031                         link_setting_b.link_rate) ?
2032                         link_setting_a.link_rate :
2033                         link_setting_b.link_rate;
2034         link_settings.link_spread = LINK_SPREAD_DISABLED;
2035
2036         /* in DP compliance test, DPR-120 may have
2037          * a random value in its MAX_LINK_BW dpcd field.
2038          * We map it to the maximum supported link rate that
2039          * is smaller than MAX_LINK_BW in this case.
2040          */
2041         if (link_settings.link_rate > LINK_RATE_HIGH3) {
2042                 link_settings.link_rate = LINK_RATE_HIGH3;
2043         } else if (link_settings.link_rate < LINK_RATE_HIGH3
2044                         && link_settings.link_rate > LINK_RATE_HIGH2) {
2045                 link_settings.link_rate = LINK_RATE_HIGH2;
2046         } else if (link_settings.link_rate < LINK_RATE_HIGH2
2047                         && link_settings.link_rate > LINK_RATE_HIGH) {
2048                 link_settings.link_rate = LINK_RATE_HIGH;
2049         } else if (link_settings.link_rate < LINK_RATE_HIGH
2050                         && link_settings.link_rate > LINK_RATE_LOW) {
2051                 link_settings.link_rate = LINK_RATE_LOW;
2052         } else if (link_settings.link_rate < LINK_RATE_LOW) {
2053                 link_settings.link_rate = LINK_RATE_UNKNOWN;
2054         }
2055
2056         return link_settings;
2057 }
2058
2059 static inline bool reached_minimum_lane_count(enum dc_lane_count lane_count)
2060 {
2061         return lane_count <= LANE_COUNT_ONE;
2062 }
2063
2064 static inline bool reached_minimum_link_rate(enum dc_link_rate link_rate)
2065 {
2066         return link_rate <= LINK_RATE_LOW;
2067 }
2068
2069 static enum dc_lane_count reduce_lane_count(enum dc_lane_count lane_count)
2070 {
2071         switch (lane_count) {
2072         case LANE_COUNT_FOUR:
2073                 return LANE_COUNT_TWO;
2074         case LANE_COUNT_TWO:
2075                 return LANE_COUNT_ONE;
2076         case LANE_COUNT_ONE:
2077                 return LANE_COUNT_UNKNOWN;
2078         default:
2079                 return LANE_COUNT_UNKNOWN;
2080         }
2081 }
2082
2083 static enum dc_link_rate reduce_link_rate(enum dc_link_rate link_rate)
2084 {
2085         switch (link_rate) {
2086         case LINK_RATE_HIGH3:
2087                 return LINK_RATE_HIGH2;
2088         case LINK_RATE_HIGH2:
2089                 return LINK_RATE_HIGH;
2090         case LINK_RATE_HIGH:
2091                 return LINK_RATE_LOW;
2092         case LINK_RATE_LOW:
2093                 return LINK_RATE_UNKNOWN;
2094         default:
2095                 return LINK_RATE_UNKNOWN;
2096         }
2097 }
2098
2099 static enum dc_lane_count increase_lane_count(enum dc_lane_count lane_count)
2100 {
2101         switch (lane_count) {
2102         case LANE_COUNT_ONE:
2103                 return LANE_COUNT_TWO;
2104         case LANE_COUNT_TWO:
2105                 return LANE_COUNT_FOUR;
2106         default:
2107                 return LANE_COUNT_UNKNOWN;
2108         }
2109 }
2110
2111 static enum dc_link_rate increase_link_rate(enum dc_link_rate link_rate)
2112 {
2113         switch (link_rate) {
2114         case LINK_RATE_LOW:
2115                 return LINK_RATE_HIGH;
2116         case LINK_RATE_HIGH:
2117                 return LINK_RATE_HIGH2;
2118         case LINK_RATE_HIGH2:
2119                 return LINK_RATE_HIGH3;
2120         default:
2121                 return LINK_RATE_UNKNOWN;
2122         }
2123 }
2124
2125 /*
2126  * function: set link rate and lane count fallback based
2127  * on current link setting and last link training result
2128  * return value:
2129  *                      true - link setting could be set
2130  *                      false - has reached minimum setting
2131  *                                      and no further fallback could be done
2132  */
2133 static bool decide_fallback_link_setting(
2134                 struct dc_link_settings initial_link_settings,
2135                 struct dc_link_settings *current_link_setting,
2136                 enum link_training_result training_result)
2137 {
2138         if (!current_link_setting)
2139                 return false;
2140
2141         switch (training_result) {
2142         case LINK_TRAINING_CR_FAIL_LANE0:
2143         case LINK_TRAINING_CR_FAIL_LANE1:
2144         case LINK_TRAINING_CR_FAIL_LANE23:
2145         case LINK_TRAINING_LQA_FAIL:
2146         {
2147                 if (!reached_minimum_link_rate
2148                                 (current_link_setting->link_rate)) {
2149                         current_link_setting->link_rate =
2150                                 reduce_link_rate(
2151                                         current_link_setting->link_rate);
2152                 } else if (!reached_minimum_lane_count
2153                                 (current_link_setting->lane_count)) {
2154                         current_link_setting->link_rate =
2155                                 initial_link_settings.link_rate;
2156                         if (training_result == LINK_TRAINING_CR_FAIL_LANE0)
2157                                 return false;
2158                         else if (training_result == LINK_TRAINING_CR_FAIL_LANE1)
2159                                 current_link_setting->lane_count =
2160                                                 LANE_COUNT_ONE;
2161                         else if (training_result ==
2162                                         LINK_TRAINING_CR_FAIL_LANE23)
2163                                 current_link_setting->lane_count =
2164                                                 LANE_COUNT_TWO;
2165                         else
2166                                 current_link_setting->lane_count =
2167                                         reduce_lane_count(
2168                                         current_link_setting->lane_count);
2169                 } else {
2170                         return false;
2171                 }
2172                 break;
2173         }
2174         case LINK_TRAINING_EQ_FAIL_EQ:
2175         {
2176                 if (!reached_minimum_lane_count
2177                                 (current_link_setting->lane_count)) {
2178                         current_link_setting->lane_count =
2179                                 reduce_lane_count(
2180                                         current_link_setting->lane_count);
2181                 } else if (!reached_minimum_link_rate
2182                                 (current_link_setting->link_rate)) {
2183                         current_link_setting->link_rate =
2184                                 reduce_link_rate(
2185                                         current_link_setting->link_rate);
2186                 } else {
2187                         return false;
2188                 }
2189                 break;
2190         }
2191         case LINK_TRAINING_EQ_FAIL_CR:
2192         {
2193                 if (!reached_minimum_link_rate
2194                                 (current_link_setting->link_rate)) {
2195                         current_link_setting->link_rate =
2196                                 reduce_link_rate(
2197                                         current_link_setting->link_rate);
2198                 } else {
2199                         return false;
2200                 }
2201                 break;
2202         }
2203         default:
2204                 return false;
2205         }
2206         return true;
2207 }
2208
2209 bool dp_validate_mode_timing(
2210         struct dc_link *link,
2211         const struct dc_crtc_timing *timing)
2212 {
2213         uint32_t req_bw;
2214         uint32_t max_bw;
2215
2216         const struct dc_link_settings *link_setting;
2217
2218         /*always DP fail safe mode*/
2219         if ((timing->pix_clk_100hz / 10) == (uint32_t) 25175 &&
2220                 timing->h_addressable == (uint32_t) 640 &&
2221                 timing->v_addressable == (uint32_t) 480)
2222                 return true;
2223
2224         link_setting = dc_link_get_link_cap(link);
2225
2226         /* TODO: DYNAMIC_VALIDATION needs to be implemented */
2227         /*if (flags.DYNAMIC_VALIDATION == 1 &&
2228                 link->verified_link_cap.lane_count != LANE_COUNT_UNKNOWN)
2229                 link_setting = &link->verified_link_cap;
2230         */
2231
2232         req_bw = dc_bandwidth_in_kbps_from_timing(timing);
2233         max_bw = dc_link_bandwidth_kbps(link, link_setting);
2234
2235         if (req_bw <= max_bw) {
2236                 /* remember the biggest mode here, during
2237                  * initial link training (to get
2238                  * verified_link_cap), LS sends event about
2239                  * cannot train at reported cap to upper
2240                  * layer and upper layer will re-enumerate modes.
2241                  * this is not necessary if the lower
2242                  * verified_link_cap is enough to drive
2243                  * all the modes */
2244
2245                 /* TODO: DYNAMIC_VALIDATION needs to be implemented */
2246                 /* if (flags.DYNAMIC_VALIDATION == 1)
2247                         dpsst->max_req_bw_for_verified_linkcap = dal_max(
2248                                 dpsst->max_req_bw_for_verified_linkcap, req_bw); */
2249                 return true;
2250         } else
2251                 return false;
2252 }
2253
2254 static bool decide_dp_link_settings(struct dc_link *link, struct dc_link_settings *link_setting, uint32_t req_bw)
2255 {
2256         struct dc_link_settings initial_link_setting = {
2257                 LANE_COUNT_ONE, LINK_RATE_LOW, LINK_SPREAD_DISABLED, false, 0};
2258         struct dc_link_settings current_link_setting =
2259                         initial_link_setting;
2260         uint32_t link_bw;
2261
2262         /* search for the minimum link setting that:
2263          * 1. is supported according to the link training result
2264          * 2. could support the b/w requested by the timing
2265          */
2266         while (current_link_setting.link_rate <=
2267                         link->verified_link_cap.link_rate) {
2268                 link_bw = dc_link_bandwidth_kbps(
2269                                 link,
2270                                 &current_link_setting);
2271                 if (req_bw <= link_bw) {
2272                         *link_setting = current_link_setting;
2273                         return true;
2274                 }
2275
2276                 if (current_link_setting.lane_count <
2277                                 link->verified_link_cap.lane_count) {
2278                         current_link_setting.lane_count =
2279                                         increase_lane_count(
2280                                                         current_link_setting.lane_count);
2281                 } else {
2282                         current_link_setting.link_rate =
2283                                         increase_link_rate(
2284                                                         current_link_setting.link_rate);
2285                         current_link_setting.lane_count =
2286                                         initial_link_setting.lane_count;
2287                 }
2288         }
2289
2290         return false;
2291 }
2292
2293 static bool decide_edp_link_settings(struct dc_link *link, struct dc_link_settings *link_setting, uint32_t req_bw)
2294 {
2295         struct dc_link_settings initial_link_setting;
2296         struct dc_link_settings current_link_setting;
2297         uint32_t link_bw;
2298
2299         if (link->dpcd_caps.dpcd_rev.raw < DPCD_REV_14 ||
2300                         link->dpcd_caps.edp_supported_link_rates_count == 0) {
2301                 *link_setting = link->verified_link_cap;
2302                 return true;
2303         }
2304
2305         memset(&initial_link_setting, 0, sizeof(initial_link_setting));
2306         initial_link_setting.lane_count = LANE_COUNT_ONE;
2307         initial_link_setting.link_rate = link->dpcd_caps.edp_supported_link_rates[0];
2308         initial_link_setting.link_spread = LINK_SPREAD_DISABLED;
2309         initial_link_setting.use_link_rate_set = true;
2310         initial_link_setting.link_rate_set = 0;
2311         current_link_setting = initial_link_setting;
2312
2313         /* search for the minimum link setting that:
2314          * 1. is supported according to the link training result
2315          * 2. could support the b/w requested by the timing
2316          */
2317         while (current_link_setting.link_rate <=
2318                         link->verified_link_cap.link_rate) {
2319                 link_bw = dc_link_bandwidth_kbps(
2320                                 link,
2321                                 &current_link_setting);
2322                 if (req_bw <= link_bw) {
2323                         *link_setting = current_link_setting;
2324                         return true;
2325                 }
2326
2327                 if (current_link_setting.lane_count <
2328                                 link->verified_link_cap.lane_count) {
2329                         current_link_setting.lane_count =
2330                                         increase_lane_count(
2331                                                         current_link_setting.lane_count);
2332                 } else {
2333                         if (current_link_setting.link_rate_set < link->dpcd_caps.edp_supported_link_rates_count) {
2334                                 current_link_setting.link_rate_set++;
2335                                 current_link_setting.link_rate =
2336                                         link->dpcd_caps.edp_supported_link_rates[current_link_setting.link_rate_set];
2337                                 current_link_setting.lane_count =
2338                                                                         initial_link_setting.lane_count;
2339                         } else
2340                                 break;
2341                 }
2342         }
2343         return false;
2344 }
2345
2346 void decide_link_settings(struct dc_stream_state *stream,
2347         struct dc_link_settings *link_setting)
2348 {
2349         struct dc_link *link;
2350         uint32_t req_bw;
2351
2352         req_bw = dc_bandwidth_in_kbps_from_timing(&stream->timing);
2353
2354         link = stream->link;
2355
2356         /* if preferred is specified through AMDDP, use it, if it's enough
2357          * to drive the mode
2358          */
2359         if (link->preferred_link_setting.lane_count !=
2360                         LANE_COUNT_UNKNOWN &&
2361                         link->preferred_link_setting.link_rate !=
2362                                         LINK_RATE_UNKNOWN) {
2363                 *link_setting =  link->preferred_link_setting;
2364                 return;
2365         }
2366
2367         /* MST doesn't perform link training for now
2368          * TODO: add MST specific link training routine
2369          */
2370         if (stream->signal == SIGNAL_TYPE_DISPLAY_PORT_MST) {
2371                 *link_setting = link->verified_link_cap;
2372                 return;
2373         }
2374
2375         if (link->connector_signal == SIGNAL_TYPE_EDP) {
2376                 if (decide_edp_link_settings(link, link_setting, req_bw))
2377                         return;
2378         } else if (decide_dp_link_settings(link, link_setting, req_bw))
2379                 return;
2380
2381         BREAK_TO_DEBUGGER();
2382         ASSERT(link->verified_link_cap.lane_count != LANE_COUNT_UNKNOWN);
2383
2384         *link_setting = link->verified_link_cap;
2385 }
2386
2387 /*************************Short Pulse IRQ***************************/
2388 static bool allow_hpd_rx_irq(const struct dc_link *link)
2389 {
2390         /*
2391          * Don't handle RX IRQ unless one of following is met:
2392          * 1) The link is established (cur_link_settings != unknown)
2393          * 2) We kicked off MST detection
2394          * 3) We know we're dealing with an active dongle
2395          */
2396
2397         if ((link->cur_link_settings.lane_count != LANE_COUNT_UNKNOWN) ||
2398                 (link->type == dc_connection_mst_branch) ||
2399                 is_dp_active_dongle(link))
2400                 return true;
2401
2402         return false;
2403 }
2404
2405 static bool handle_hpd_irq_psr_sink(struct dc_link *link)
2406 {
2407         union dpcd_psr_configuration psr_configuration;
2408
2409         if (!link->psr_feature_enabled)
2410                 return false;
2411
2412         dm_helpers_dp_read_dpcd(
2413                 link->ctx,
2414                 link,
2415                 368,/*DpcdAddress_PSR_Enable_Cfg*/
2416                 &psr_configuration.raw,
2417                 sizeof(psr_configuration.raw));
2418
2419
2420         if (psr_configuration.bits.ENABLE) {
2421                 unsigned char dpcdbuf[3] = {0};
2422                 union psr_error_status psr_error_status;
2423                 union psr_sink_psr_status psr_sink_psr_status;
2424
2425                 dm_helpers_dp_read_dpcd(
2426                         link->ctx,
2427                         link,
2428                         0x2006, /*DpcdAddress_PSR_Error_Status*/
2429                         (unsigned char *) dpcdbuf,
2430                         sizeof(dpcdbuf));
2431
2432                 /*DPCD 2006h   ERROR STATUS*/
2433                 psr_error_status.raw = dpcdbuf[0];
2434                 /*DPCD 2008h   SINK PANEL SELF REFRESH STATUS*/
2435                 psr_sink_psr_status.raw = dpcdbuf[2];
2436
2437                 if (psr_error_status.bits.LINK_CRC_ERROR ||
2438                                 psr_error_status.bits.RFB_STORAGE_ERROR) {
2439                         /* Acknowledge and clear error bits */
2440                         dm_helpers_dp_write_dpcd(
2441                                 link->ctx,
2442                                 link,
2443                                 8198,/*DpcdAddress_PSR_Error_Status*/
2444                                 &psr_error_status.raw,
2445                                 sizeof(psr_error_status.raw));
2446
2447                         /* PSR error, disable and re-enable PSR */
2448                         dc_link_set_psr_allow_active(link, false, true);
2449                         dc_link_set_psr_allow_active(link, true, true);
2450
2451                         return true;
2452                 } else if (psr_sink_psr_status.bits.SINK_SELF_REFRESH_STATUS ==
2453                                 PSR_SINK_STATE_ACTIVE_DISPLAY_FROM_SINK_RFB){
2454                         /* No error is detect, PSR is active.
2455                          * We should return with IRQ_HPD handled without
2456                          * checking for loss of sync since PSR would have
2457                          * powered down main link.
2458                          */
2459                         return true;
2460                 }
2461         }
2462         return false;
2463 }
2464
2465 static void dp_test_send_link_training(struct dc_link *link)
2466 {
2467         struct dc_link_settings link_settings = {0};
2468
2469         core_link_read_dpcd(
2470                         link,
2471                         DP_TEST_LANE_COUNT,
2472                         (unsigned char *)(&link_settings.lane_count),
2473                         1);
2474         core_link_read_dpcd(
2475                         link,
2476                         DP_TEST_LINK_RATE,
2477                         (unsigned char *)(&link_settings.link_rate),
2478                         1);
2479
2480         /* Set preferred link settings */
2481         link->verified_link_cap.lane_count = link_settings.lane_count;
2482         link->verified_link_cap.link_rate = link_settings.link_rate;
2483
2484         dp_retrain_link_dp_test(link, &link_settings, false);
2485 }
2486
2487 /* TODO Raven hbr2 compliance eye output is unstable
2488  * (toggling on and off) with debugger break
2489  * This caueses intermittent PHY automation failure
2490  * Need to look into the root cause */
2491 static void dp_test_send_phy_test_pattern(struct dc_link *link)
2492 {
2493         union phy_test_pattern dpcd_test_pattern;
2494         union lane_adjust dpcd_lane_adjustment[2];
2495         unsigned char dpcd_post_cursor_2_adjustment = 0;
2496         unsigned char test_80_bit_pattern[
2497                         (DP_TEST_80BIT_CUSTOM_PATTERN_79_72 -
2498                         DP_TEST_80BIT_CUSTOM_PATTERN_7_0)+1] = {0};
2499         enum dp_test_pattern test_pattern;
2500         struct dc_link_training_settings link_settings;
2501         union lane_adjust dpcd_lane_adjust;
2502         unsigned int lane;
2503         struct link_training_settings link_training_settings;
2504         int i = 0;
2505
2506         dpcd_test_pattern.raw = 0;
2507         memset(dpcd_lane_adjustment, 0, sizeof(dpcd_lane_adjustment));
2508         memset(&link_settings, 0, sizeof(link_settings));
2509
2510         /* get phy test pattern and pattern parameters from DP receiver */
2511         core_link_read_dpcd(
2512                         link,
2513                         DP_TEST_PHY_PATTERN,
2514                         &dpcd_test_pattern.raw,
2515                         sizeof(dpcd_test_pattern));
2516         core_link_read_dpcd(
2517                         link,
2518                         DP_ADJUST_REQUEST_LANE0_1,
2519                         &dpcd_lane_adjustment[0].raw,
2520                         sizeof(dpcd_lane_adjustment));
2521
2522         /*get post cursor 2 parameters
2523          * For DP 1.1a or eariler, this DPCD register's value is 0
2524          * For DP 1.2 or later:
2525          * Bits 1:0 = POST_CURSOR2_LANE0; Bits 3:2 = POST_CURSOR2_LANE1
2526          * Bits 5:4 = POST_CURSOR2_LANE2; Bits 7:6 = POST_CURSOR2_LANE3
2527          */
2528         core_link_read_dpcd(
2529                         link,
2530                         DP_ADJUST_REQUEST_POST_CURSOR2,
2531                         &dpcd_post_cursor_2_adjustment,
2532                         sizeof(dpcd_post_cursor_2_adjustment));
2533
2534         /* translate request */
2535         switch (dpcd_test_pattern.bits.PATTERN) {
2536         case PHY_TEST_PATTERN_D10_2:
2537                 test_pattern = DP_TEST_PATTERN_D102;
2538                 break;
2539         case PHY_TEST_PATTERN_SYMBOL_ERROR:
2540                 test_pattern = DP_TEST_PATTERN_SYMBOL_ERROR;
2541                 break;
2542         case PHY_TEST_PATTERN_PRBS7:
2543                 test_pattern = DP_TEST_PATTERN_PRBS7;
2544                 break;
2545         case PHY_TEST_PATTERN_80BIT_CUSTOM:
2546                 test_pattern = DP_TEST_PATTERN_80BIT_CUSTOM;
2547                 break;
2548         case PHY_TEST_PATTERN_CP2520_1:
2549                 /* CP2520 pattern is unstable, temporarily use TPS4 instead */
2550                 test_pattern = (link->dc->caps.force_dp_tps4_for_cp2520 == 1) ?
2551                                 DP_TEST_PATTERN_TRAINING_PATTERN4 :
2552                                 DP_TEST_PATTERN_HBR2_COMPLIANCE_EYE;
2553                 break;
2554         case PHY_TEST_PATTERN_CP2520_2:
2555                 /* CP2520 pattern is unstable, temporarily use TPS4 instead */
2556                 test_pattern = (link->dc->caps.force_dp_tps4_for_cp2520 == 1) ?
2557                                 DP_TEST_PATTERN_TRAINING_PATTERN4 :
2558                                 DP_TEST_PATTERN_HBR2_COMPLIANCE_EYE;
2559                 break;
2560         case PHY_TEST_PATTERN_CP2520_3:
2561                 test_pattern = DP_TEST_PATTERN_TRAINING_PATTERN4;
2562                 break;
2563         default:
2564                 test_pattern = DP_TEST_PATTERN_VIDEO_MODE;
2565         break;
2566         }
2567
2568         if (test_pattern == DP_TEST_PATTERN_80BIT_CUSTOM)
2569                 core_link_read_dpcd(
2570                                 link,
2571                                 DP_TEST_80BIT_CUSTOM_PATTERN_7_0,
2572                                 test_80_bit_pattern,
2573                                 sizeof(test_80_bit_pattern));
2574
2575         /* prepare link training settings */
2576         link_settings.link = link->cur_link_settings;
2577
2578         for (lane = 0; lane <
2579                 (unsigned int)(link->cur_link_settings.lane_count);
2580                 lane++) {
2581                 dpcd_lane_adjust.raw =
2582                         get_nibble_at_index(&dpcd_lane_adjustment[0].raw, lane);
2583                 link_settings.lane_settings[lane].VOLTAGE_SWING =
2584                         (enum dc_voltage_swing)
2585                         (dpcd_lane_adjust.bits.VOLTAGE_SWING_LANE);
2586                 link_settings.lane_settings[lane].PRE_EMPHASIS =
2587                         (enum dc_pre_emphasis)
2588                         (dpcd_lane_adjust.bits.PRE_EMPHASIS_LANE);
2589                 link_settings.lane_settings[lane].POST_CURSOR2 =
2590                         (enum dc_post_cursor2)
2591                         ((dpcd_post_cursor_2_adjustment >> (lane * 2)) & 0x03);
2592         }
2593
2594         for (i = 0; i < 4; i++)
2595                 link_training_settings.lane_settings[i] =
2596                                 link_settings.lane_settings[i];
2597         link_training_settings.link_settings = link_settings.link;
2598         link_training_settings.allow_invalid_msa_timing_param = false;
2599         /*Usage: Measure DP physical lane signal
2600          * by DP SI test equipment automatically.
2601          * PHY test pattern request is generated by equipment via HPD interrupt.
2602          * HPD needs to be active all the time. HPD should be active
2603          * all the time. Do not touch it.
2604          * forward request to DS
2605          */
2606         dc_link_dp_set_test_pattern(
2607                 link,
2608                 test_pattern,
2609                 DP_TEST_PATTERN_COLOR_SPACE_UNDEFINED,
2610                 &link_training_settings,
2611                 test_80_bit_pattern,
2612                 (DP_TEST_80BIT_CUSTOM_PATTERN_79_72 -
2613                 DP_TEST_80BIT_CUSTOM_PATTERN_7_0)+1);
2614 }
2615
2616 static void dp_test_send_link_test_pattern(struct dc_link *link)
2617 {
2618         union link_test_pattern dpcd_test_pattern;
2619         union test_misc dpcd_test_params;
2620         enum dp_test_pattern test_pattern;
2621         enum dp_test_pattern_color_space test_pattern_color_space =
2622                         DP_TEST_PATTERN_COLOR_SPACE_UNDEFINED;
2623
2624         memset(&dpcd_test_pattern, 0, sizeof(dpcd_test_pattern));
2625         memset(&dpcd_test_params, 0, sizeof(dpcd_test_params));
2626
2627         /* get link test pattern and pattern parameters */
2628         core_link_read_dpcd(
2629                         link,
2630                         DP_TEST_PATTERN,
2631                         &dpcd_test_pattern.raw,
2632                         sizeof(dpcd_test_pattern));
2633         core_link_read_dpcd(
2634                         link,
2635                         DP_TEST_MISC0,
2636                         &dpcd_test_params.raw,
2637                         sizeof(dpcd_test_params));
2638
2639         switch (dpcd_test_pattern.bits.PATTERN) {
2640         case LINK_TEST_PATTERN_COLOR_RAMP:
2641                 test_pattern = DP_TEST_PATTERN_COLOR_RAMP;
2642         break;
2643         case LINK_TEST_PATTERN_VERTICAL_BARS:
2644                 test_pattern = DP_TEST_PATTERN_VERTICAL_BARS;
2645         break; /* black and white */
2646         case LINK_TEST_PATTERN_COLOR_SQUARES:
2647                 test_pattern = (dpcd_test_params.bits.DYN_RANGE ==
2648                                 TEST_DYN_RANGE_VESA ?
2649                                 DP_TEST_PATTERN_COLOR_SQUARES :
2650                                 DP_TEST_PATTERN_COLOR_SQUARES_CEA);
2651         break;
2652         default:
2653                 test_pattern = DP_TEST_PATTERN_VIDEO_MODE;
2654         break;
2655         }
2656
2657         test_pattern_color_space = dpcd_test_params.bits.YCBCR_COEFS ?
2658                         DP_TEST_PATTERN_COLOR_SPACE_YCBCR709 :
2659                         DP_TEST_PATTERN_COLOR_SPACE_YCBCR601;
2660
2661         dc_link_dp_set_test_pattern(
2662                         link,
2663                         test_pattern,
2664                         test_pattern_color_space,
2665                         NULL,
2666                         NULL,
2667                         0);
2668 }
2669
2670 static void dp_test_get_audio_test_data(struct dc_link *link, bool disable_video)
2671 {
2672         union audio_test_mode            dpcd_test_mode = {0};
2673         struct audio_test_pattern_type   dpcd_pattern_type = {0};
2674         union audio_test_pattern_period  dpcd_pattern_period[AUDIO_CHANNELS_COUNT] = {0};
2675         enum dp_test_pattern test_pattern = DP_TEST_PATTERN_AUDIO_OPERATOR_DEFINED;
2676
2677         struct pipe_ctx *pipes = link->dc->current_state->res_ctx.pipe_ctx;
2678         struct pipe_ctx *pipe_ctx = &pipes[0];
2679         unsigned int channel_count;
2680         unsigned int channel = 0;
2681         unsigned int modes = 0;
2682         unsigned int sampling_rate_in_hz = 0;
2683
2684         // get audio test mode and test pattern parameters
2685         core_link_read_dpcd(
2686                 link,
2687                 DP_TEST_AUDIO_MODE,
2688                 &dpcd_test_mode.raw,
2689                 sizeof(dpcd_test_mode));
2690
2691         core_link_read_dpcd(
2692                 link,
2693                 DP_TEST_AUDIO_PATTERN_TYPE,
2694                 &dpcd_pattern_type.value,
2695                 sizeof(dpcd_pattern_type));
2696
2697         channel_count = dpcd_test_mode.bits.channel_count + 1;
2698
2699         // read pattern periods for requested channels when sawTooth pattern is requested
2700         if (dpcd_pattern_type.value == AUDIO_TEST_PATTERN_SAWTOOTH ||
2701                         dpcd_pattern_type.value == AUDIO_TEST_PATTERN_OPERATOR_DEFINED) {
2702
2703                 test_pattern = (dpcd_pattern_type.value == AUDIO_TEST_PATTERN_SAWTOOTH) ?
2704                                 DP_TEST_PATTERN_AUDIO_SAWTOOTH : DP_TEST_PATTERN_AUDIO_OPERATOR_DEFINED;
2705                 // read period for each channel
2706                 for (channel = 0; channel < channel_count; channel++) {
2707                         core_link_read_dpcd(
2708                                                         link,
2709                                                         DP_TEST_AUDIO_PERIOD_CH1 + channel,
2710                                                         &dpcd_pattern_period[channel].raw,
2711                                                         sizeof(dpcd_pattern_period[channel]));
2712                 }
2713         }
2714
2715         // translate sampling rate
2716         switch (dpcd_test_mode.bits.sampling_rate) {
2717         case AUDIO_SAMPLING_RATE_32KHZ:
2718                 sampling_rate_in_hz = 32000;
2719                 break;
2720         case AUDIO_SAMPLING_RATE_44_1KHZ:
2721                 sampling_rate_in_hz = 44100;
2722                 break;
2723         case AUDIO_SAMPLING_RATE_48KHZ:
2724                 sampling_rate_in_hz = 48000;
2725                 break;
2726         case AUDIO_SAMPLING_RATE_88_2KHZ:
2727                 sampling_rate_in_hz = 88200;
2728                 break;
2729         case AUDIO_SAMPLING_RATE_96KHZ:
2730                 sampling_rate_in_hz = 96000;
2731                 break;
2732         case AUDIO_SAMPLING_RATE_176_4KHZ:
2733                 sampling_rate_in_hz = 176400;
2734                 break;
2735         case AUDIO_SAMPLING_RATE_192KHZ:
2736                 sampling_rate_in_hz = 192000;
2737                 break;
2738         default:
2739                 sampling_rate_in_hz = 0;
2740                 break;
2741         }
2742
2743         link->audio_test_data.flags.test_requested = 1;
2744         link->audio_test_data.flags.disable_video = disable_video;
2745         link->audio_test_data.sampling_rate = sampling_rate_in_hz;
2746         link->audio_test_data.channel_count = channel_count;
2747         link->audio_test_data.pattern_type = test_pattern;
2748
2749         if (test_pattern == DP_TEST_PATTERN_AUDIO_SAWTOOTH) {
2750                 for (modes = 0; modes < pipe_ctx->stream->audio_info.mode_count; modes++) {
2751                         link->audio_test_data.pattern_period[modes] = dpcd_pattern_period[modes].bits.pattern_period;
2752                 }
2753         }
2754 }
2755
2756 static void handle_automated_test(struct dc_link *link)
2757 {
2758         union test_request test_request;
2759         union test_response test_response;
2760
2761         memset(&test_request, 0, sizeof(test_request));
2762         memset(&test_response, 0, sizeof(test_response));
2763
2764         core_link_read_dpcd(
2765                 link,
2766                 DP_TEST_REQUEST,
2767                 &test_request.raw,
2768                 sizeof(union test_request));
2769         if (test_request.bits.LINK_TRAINING) {
2770                 /* ACK first to let DP RX test box monitor LT sequence */
2771                 test_response.bits.ACK = 1;
2772                 core_link_write_dpcd(
2773                         link,
2774                         DP_TEST_RESPONSE,
2775                         &test_response.raw,
2776                         sizeof(test_response));
2777                 dp_test_send_link_training(link);
2778                 /* no acknowledge request is needed again */
2779                 test_response.bits.ACK = 0;
2780         }
2781         if (test_request.bits.LINK_TEST_PATTRN) {
2782                 dp_test_send_link_test_pattern(link);
2783                 test_response.bits.ACK = 1;
2784         }
2785
2786         if (test_request.bits.AUDIO_TEST_PATTERN) {
2787                 dp_test_get_audio_test_data(link, test_request.bits.TEST_AUDIO_DISABLED_VIDEO);
2788                 test_response.bits.ACK = 1;
2789         }
2790
2791         if (test_request.bits.PHY_TEST_PATTERN) {
2792                 dp_test_send_phy_test_pattern(link);
2793                 test_response.bits.ACK = 1;
2794         }
2795
2796         /* send request acknowledgment */
2797         if (test_response.bits.ACK)
2798                 core_link_write_dpcd(
2799                         link,
2800                         DP_TEST_RESPONSE,
2801                         &test_response.raw,
2802                         sizeof(test_response));
2803 }
2804
2805 bool dc_link_handle_hpd_rx_irq(struct dc_link *link, union hpd_irq_data *out_hpd_irq_dpcd_data, bool *out_link_loss)
2806 {
2807         union hpd_irq_data hpd_irq_dpcd_data = { { { {0} } } };
2808         union device_service_irq device_service_clear = { { 0 } };
2809         enum dc_status result;
2810         bool status = false;
2811         struct pipe_ctx *pipe_ctx;
2812         struct dc_link_settings previous_link_settings;
2813         int i;
2814
2815         if (out_link_loss)
2816                 *out_link_loss = false;
2817         /* For use cases related to down stream connection status change,
2818          * PSR and device auto test, refer to function handle_sst_hpd_irq
2819          * in DAL2.1*/
2820
2821         DC_LOG_HW_HPD_IRQ("%s: Got short pulse HPD on link %d\n",
2822                 __func__, link->link_index);
2823
2824
2825          /* All the "handle_hpd_irq_xxx()" methods
2826                  * should be called only after
2827                  * dal_dpsst_ls_read_hpd_irq_data
2828                  * Order of calls is important too
2829                  */
2830         result = read_hpd_rx_irq_data(link, &hpd_irq_dpcd_data);
2831         if (out_hpd_irq_dpcd_data)
2832                 *out_hpd_irq_dpcd_data = hpd_irq_dpcd_data;
2833
2834         if (result != DC_OK) {
2835                 DC_LOG_HW_HPD_IRQ("%s: DPCD read failed to obtain irq data\n",
2836                         __func__);
2837                 return false;
2838         }
2839
2840         if (hpd_irq_dpcd_data.bytes.device_service_irq.bits.AUTOMATED_TEST) {
2841                 device_service_clear.bits.AUTOMATED_TEST = 1;
2842                 core_link_write_dpcd(
2843                         link,
2844                         DP_DEVICE_SERVICE_IRQ_VECTOR,
2845                         &device_service_clear.raw,
2846                         sizeof(device_service_clear.raw));
2847                 device_service_clear.raw = 0;
2848                 handle_automated_test(link);
2849                 return false;
2850         }
2851
2852         if (!allow_hpd_rx_irq(link)) {
2853                 DC_LOG_HW_HPD_IRQ("%s: skipping HPD handling on %d\n",
2854                         __func__, link->link_index);
2855                 return false;
2856         }
2857
2858         if (handle_hpd_irq_psr_sink(link))
2859                 /* PSR-related error was detected and handled */
2860                 return true;
2861
2862         /* If PSR-related error handled, Main link may be off,
2863          * so do not handle as a normal sink status change interrupt.
2864          */
2865
2866         if (hpd_irq_dpcd_data.bytes.device_service_irq.bits.UP_REQ_MSG_RDY)
2867                 return true;
2868
2869         /* check if we have MST msg and return since we poll for it */
2870         if (hpd_irq_dpcd_data.bytes.device_service_irq.bits.DOWN_REP_MSG_RDY)
2871                 return false;
2872
2873         /* For now we only handle 'Downstream port status' case.
2874          * If we got sink count changed it means
2875          * Downstream port status changed,
2876          * then DM should call DC to do the detection.
2877          * NOTE: Do not handle link loss on eDP since it is internal link*/
2878         if ((link->connector_signal != SIGNAL_TYPE_EDP) &&
2879                 hpd_rx_irq_check_link_loss_status(
2880                         link,
2881                         &hpd_irq_dpcd_data)) {
2882                 /* Connectivity log: link loss */
2883                 CONN_DATA_LINK_LOSS(link,
2884                                         hpd_irq_dpcd_data.raw,
2885                                         sizeof(hpd_irq_dpcd_data),
2886                                         "Status: ");
2887
2888                 for (i = 0; i < MAX_PIPES; i++) {
2889                         pipe_ctx = &link->dc->current_state->res_ctx.pipe_ctx[i];
2890                         if (pipe_ctx && pipe_ctx->stream && pipe_ctx->stream->link == link)
2891                                 break;
2892                 }
2893
2894                 if (pipe_ctx == NULL || pipe_ctx->stream == NULL)
2895                         return false;
2896
2897                 previous_link_settings = link->cur_link_settings;
2898
2899                 perform_link_training_with_retries(&previous_link_settings,
2900                         true, LINK_TRAINING_ATTEMPTS,
2901                         pipe_ctx,
2902                         pipe_ctx->stream->signal);
2903
2904                 if (pipe_ctx->stream->signal == SIGNAL_TYPE_DISPLAY_PORT_MST)
2905                         dc_link_reallocate_mst_payload(link);
2906
2907                 status = false;
2908                 if (out_link_loss)
2909                         *out_link_loss = true;
2910         }
2911
2912         if (link->type == dc_connection_active_dongle &&
2913                 hpd_irq_dpcd_data.bytes.sink_cnt.bits.SINK_COUNT
2914                         != link->dpcd_sink_count)
2915                 status = true;
2916
2917         /* reasons for HPD RX:
2918          * 1. Link Loss - ie Re-train the Link
2919          * 2. MST sideband message
2920          * 3. Automated Test - ie. Internal Commit
2921          * 4. CP (copy protection) - (not interesting for DM???)
2922          * 5. DRR
2923          * 6. Downstream Port status changed
2924          * -ie. Detect - this the only one
2925          * which is interesting for DM because
2926          * it must call dc_link_detect.
2927          */
2928         return status;
2929 }
2930
2931 /*query dpcd for version and mst cap addresses*/
2932 bool is_mst_supported(struct dc_link *link)
2933 {
2934         bool mst          = false;
2935         enum dc_status st = DC_OK;
2936         union dpcd_rev rev;
2937         union mstm_cap cap;
2938
2939         if (link->preferred_training_settings.mst_enable &&
2940                 *link->preferred_training_settings.mst_enable == false) {
2941                 return false;
2942         }
2943
2944         rev.raw  = 0;
2945         cap.raw  = 0;
2946
2947         st = core_link_read_dpcd(link, DP_DPCD_REV, &rev.raw,
2948                         sizeof(rev));
2949
2950         if (st == DC_OK && rev.raw >= DPCD_REV_12) {
2951
2952                 st = core_link_read_dpcd(link, DP_MSTM_CAP,
2953                                 &cap.raw, sizeof(cap));
2954                 if (st == DC_OK && cap.bits.MST_CAP == 1)
2955                         mst = true;
2956         }
2957         return mst;
2958
2959 }
2960
2961 bool is_dp_active_dongle(const struct dc_link *link)
2962 {
2963         return link->dpcd_caps.is_branch_dev;
2964 }
2965
2966 static int translate_dpcd_max_bpc(enum dpcd_downstream_port_max_bpc bpc)
2967 {
2968         switch (bpc) {
2969         case DOWN_STREAM_MAX_8BPC:
2970                 return 8;
2971         case DOWN_STREAM_MAX_10BPC:
2972                 return 10;
2973         case DOWN_STREAM_MAX_12BPC:
2974                 return 12;
2975         case DOWN_STREAM_MAX_16BPC:
2976                 return 16;
2977         default:
2978                 break;
2979         }
2980
2981         return -1;
2982 }
2983
2984 static void read_dp_device_vendor_id(struct dc_link *link)
2985 {
2986         struct dp_device_vendor_id dp_id;
2987
2988         /* read IEEE branch device id */
2989         core_link_read_dpcd(
2990                 link,
2991                 DP_BRANCH_OUI,
2992                 (uint8_t *)&dp_id,
2993                 sizeof(dp_id));
2994
2995         link->dpcd_caps.branch_dev_id =
2996                 (dp_id.ieee_oui[0] << 16) +
2997                 (dp_id.ieee_oui[1] << 8) +
2998                 dp_id.ieee_oui[2];
2999
3000         memmove(
3001                 link->dpcd_caps.branch_dev_name,
3002                 dp_id.ieee_device_id,
3003                 sizeof(dp_id.ieee_device_id));
3004 }
3005
3006
3007
3008 static void get_active_converter_info(
3009         uint8_t data, struct dc_link *link)
3010 {
3011         union dp_downstream_port_present ds_port = { .byte = data };
3012         memset(&link->dpcd_caps.dongle_caps, 0, sizeof(link->dpcd_caps.dongle_caps));
3013
3014         /* decode converter info*/
3015         if (!ds_port.fields.PORT_PRESENT) {
3016                 link->dpcd_caps.dongle_type = DISPLAY_DONGLE_NONE;
3017                 ddc_service_set_dongle_type(link->ddc,
3018                                 link->dpcd_caps.dongle_type);
3019                 link->dpcd_caps.is_branch_dev = false;
3020                 return;
3021         }
3022
3023         /* DPCD 0x5 bit 0 = 1, it indicate it's branch device */
3024         if (ds_port.fields.PORT_TYPE == DOWNSTREAM_DP) {
3025                 link->dpcd_caps.is_branch_dev = false;
3026         }
3027
3028         else {
3029                 link->dpcd_caps.is_branch_dev = ds_port.fields.PORT_PRESENT;
3030         }
3031
3032         switch (ds_port.fields.PORT_TYPE) {
3033         case DOWNSTREAM_VGA:
3034                 link->dpcd_caps.dongle_type = DISPLAY_DONGLE_DP_VGA_CONVERTER;
3035                 break;
3036         case DOWNSTREAM_DVI_HDMI_DP_PLUS_PLUS:
3037                 /* At this point we don't know is it DVI or HDMI or DP++,
3038                  * assume DVI.*/
3039                 link->dpcd_caps.dongle_type = DISPLAY_DONGLE_DP_DVI_CONVERTER;
3040                 break;
3041         default:
3042                 link->dpcd_caps.dongle_type = DISPLAY_DONGLE_NONE;
3043                 break;
3044         }
3045
3046         if (link->dpcd_caps.dpcd_rev.raw >= DPCD_REV_11) {
3047                 uint8_t det_caps[16]; /* CTS 4.2.2.7 expects source to read Detailed Capabilities Info : 00080h-0008F.*/
3048                 union dwnstream_port_caps_byte0 *port_caps =
3049                         (union dwnstream_port_caps_byte0 *)det_caps;
3050                 core_link_read_dpcd(link, DP_DOWNSTREAM_PORT_0,
3051                                 det_caps, sizeof(det_caps));
3052
3053                 switch (port_caps->bits.DWN_STRM_PORTX_TYPE) {
3054                 /*Handle DP case as DONGLE_NONE*/
3055                 case DOWN_STREAM_DETAILED_DP:
3056                         link->dpcd_caps.dongle_type = DISPLAY_DONGLE_NONE;
3057                         break;
3058                 case DOWN_STREAM_DETAILED_VGA:
3059                         link->dpcd_caps.dongle_type =
3060                                 DISPLAY_DONGLE_DP_VGA_CONVERTER;
3061                         break;
3062                 case DOWN_STREAM_DETAILED_DVI:
3063                         link->dpcd_caps.dongle_type =
3064                                 DISPLAY_DONGLE_DP_DVI_CONVERTER;
3065                         break;
3066                 case DOWN_STREAM_DETAILED_HDMI:
3067                 case DOWN_STREAM_DETAILED_DP_PLUS_PLUS:
3068                         /*Handle DP++ active converter case, process DP++ case as HDMI case according DP1.4 spec*/
3069                         link->dpcd_caps.dongle_type =
3070                                 DISPLAY_DONGLE_DP_HDMI_CONVERTER;
3071
3072                         link->dpcd_caps.dongle_caps.dongle_type = link->dpcd_caps.dongle_type;
3073                         if (ds_port.fields.DETAILED_CAPS) {
3074
3075                                 union dwnstream_port_caps_byte3_hdmi
3076                                         hdmi_caps = {.raw = det_caps[3] };
3077                                 union dwnstream_port_caps_byte2
3078                                         hdmi_color_caps = {.raw = det_caps[2] };
3079                                 link->dpcd_caps.dongle_caps.dp_hdmi_max_pixel_clk_in_khz =
3080                                         det_caps[1] * 2500;
3081
3082                                 link->dpcd_caps.dongle_caps.is_dp_hdmi_s3d_converter =
3083                                         hdmi_caps.bits.FRAME_SEQ_TO_FRAME_PACK;
3084                                 /*YCBCR capability only for HDMI case*/
3085                                 if (port_caps->bits.DWN_STRM_PORTX_TYPE
3086                                                 == DOWN_STREAM_DETAILED_HDMI) {
3087                                         link->dpcd_caps.dongle_caps.is_dp_hdmi_ycbcr422_pass_through =
3088                                                         hdmi_caps.bits.YCrCr422_PASS_THROUGH;
3089                                         link->dpcd_caps.dongle_caps.is_dp_hdmi_ycbcr420_pass_through =
3090                                                         hdmi_caps.bits.YCrCr420_PASS_THROUGH;
3091                                         link->dpcd_caps.dongle_caps.is_dp_hdmi_ycbcr422_converter =
3092                                                         hdmi_caps.bits.YCrCr422_CONVERSION;
3093                                         link->dpcd_caps.dongle_caps.is_dp_hdmi_ycbcr420_converter =
3094                                                         hdmi_caps.bits.YCrCr420_CONVERSION;
3095                                 }
3096
3097                                 link->dpcd_caps.dongle_caps.dp_hdmi_max_bpc =
3098                                         translate_dpcd_max_bpc(
3099                                                 hdmi_color_caps.bits.MAX_BITS_PER_COLOR_COMPONENT);
3100
3101                                 if (link->dpcd_caps.dongle_caps.dp_hdmi_max_pixel_clk_in_khz != 0)
3102                                         link->dpcd_caps.dongle_caps.extendedCapValid = true;
3103                         }
3104
3105                         break;
3106                 }
3107         }
3108
3109         ddc_service_set_dongle_type(link->ddc, link->dpcd_caps.dongle_type);
3110
3111         {
3112                 struct dp_sink_hw_fw_revision dp_hw_fw_revision;
3113
3114                 core_link_read_dpcd(
3115                         link,
3116                         DP_BRANCH_REVISION_START,
3117                         (uint8_t *)&dp_hw_fw_revision,
3118                         sizeof(dp_hw_fw_revision));
3119
3120                 link->dpcd_caps.branch_hw_revision =
3121                         dp_hw_fw_revision.ieee_hw_rev;
3122
3123                 memmove(
3124                         link->dpcd_caps.branch_fw_revision,
3125                         dp_hw_fw_revision.ieee_fw_rev,
3126                         sizeof(dp_hw_fw_revision.ieee_fw_rev));
3127         }
3128 }
3129
3130 static void dp_wa_power_up_0010FA(struct dc_link *link, uint8_t *dpcd_data,
3131                 int length)
3132 {
3133         int retry = 0;
3134
3135         if (!link->dpcd_caps.dpcd_rev.raw) {
3136                 do {
3137                         dp_receiver_power_ctrl(link, true);
3138                         core_link_read_dpcd(link, DP_DPCD_REV,
3139                                                         dpcd_data, length);
3140                         link->dpcd_caps.dpcd_rev.raw = dpcd_data[
3141                                 DP_DPCD_REV -
3142                                 DP_DPCD_REV];
3143                 } while (retry++ < 4 && !link->dpcd_caps.dpcd_rev.raw);
3144         }
3145
3146         if (link->dpcd_caps.dongle_type == DISPLAY_DONGLE_DP_VGA_CONVERTER) {
3147                 switch (link->dpcd_caps.branch_dev_id) {
3148                 /* 0010FA active dongles (DP-VGA, DP-DLDVI converters) power down
3149                  * all internal circuits including AUX communication preventing
3150                  * reading DPCD table and EDID (spec violation).
3151                  * Encoder will skip DP RX power down on disable_output to
3152                  * keep receiver powered all the time.*/
3153                 case DP_BRANCH_DEVICE_ID_0010FA:
3154                 case DP_BRANCH_DEVICE_ID_0080E1:
3155                 case DP_BRANCH_DEVICE_ID_00E04C:
3156                         link->wa_flags.dp_keep_receiver_powered = true;
3157                         break;
3158
3159                 /* TODO: May need work around for other dongles. */
3160                 default:
3161                         link->wa_flags.dp_keep_receiver_powered = false;
3162                         break;
3163                 }
3164         } else
3165                 link->wa_flags.dp_keep_receiver_powered = false;
3166 }
3167
3168 static bool retrieve_link_cap(struct dc_link *link)
3169 {
3170         /* DP_ADAPTER_CAP - DP_DPCD_REV + 1 == 16 and also DP_DSC_BITS_PER_PIXEL_INC - DP_DSC_SUPPORT + 1 == 16,
3171          * which means size 16 will be good for both of those DPCD register block reads
3172          */
3173         uint8_t dpcd_data[16];
3174         uint8_t lttpr_dpcd_data[6];
3175
3176         /*Only need to read 1 byte starting from DP_DPRX_FEATURE_ENUMERATION_LIST.
3177          */
3178         uint8_t dpcd_dprx_data = '\0';
3179         uint8_t dpcd_power_state = '\0';
3180
3181         struct dp_device_vendor_id sink_id;
3182         union down_stream_port_count down_strm_port_count;
3183         union edp_configuration_cap edp_config_cap;
3184         union dp_downstream_port_present ds_port = { 0 };
3185         enum dc_status status = DC_ERROR_UNEXPECTED;
3186         uint32_t read_dpcd_retry_cnt = 3;
3187         int i;
3188         struct dp_sink_hw_fw_revision dp_hw_fw_revision;
3189
3190         /* Set default timeout to 3.2ms and read LTTPR capabilities */
3191         bool ext_timeout_support = link->dc->caps.extended_aux_timeout_support &&
3192                         !link->dc->config.disable_extended_timeout_support;
3193
3194         link->is_lttpr_mode_transparent = true;
3195
3196         if (ext_timeout_support) {
3197                 dc_link_aux_configure_timeout(link->ddc,
3198                                         LINK_AUX_DEFAULT_EXTENDED_TIMEOUT_PERIOD);
3199         }
3200
3201         memset(dpcd_data, '\0', sizeof(dpcd_data));
3202         memset(lttpr_dpcd_data, '\0', sizeof(lttpr_dpcd_data));
3203         memset(&down_strm_port_count,
3204                 '\0', sizeof(union down_stream_port_count));
3205         memset(&edp_config_cap, '\0',
3206                 sizeof(union edp_configuration_cap));
3207
3208         status = core_link_read_dpcd(link, DP_SET_POWER,
3209                                 &dpcd_power_state, sizeof(dpcd_power_state));
3210
3211         /* Delay 1 ms if AUX CH is in power down state. Based on spec
3212          * section 2.3.1.2, if AUX CH may be powered down due to
3213          * write to DPCD 600h = 2. Sink AUX CH is monitoring differential
3214          * signal and may need up to 1 ms before being able to reply.
3215          */
3216         if (status != DC_OK || dpcd_power_state == DP_SET_POWER_D3)
3217                 udelay(1000);
3218
3219         for (i = 0; i < read_dpcd_retry_cnt; i++) {
3220                 status = core_link_read_dpcd(
3221                                 link,
3222                                 DP_DPCD_REV,
3223                                 dpcd_data,
3224                                 sizeof(dpcd_data));
3225                 if (status == DC_OK)
3226                         break;
3227         }
3228
3229         if (status != DC_OK) {
3230                 dm_error("%s: Read dpcd data failed.\n", __func__);
3231                 return false;
3232         }
3233
3234         if (ext_timeout_support) {
3235
3236                 status = core_link_read_dpcd(
3237                                 link,
3238                                 DP_LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV,
3239                                 lttpr_dpcd_data,
3240                                 sizeof(lttpr_dpcd_data));
3241
3242                 link->dpcd_caps.lttpr_caps.revision.raw =
3243                                 lttpr_dpcd_data[DP_LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV -
3244                                                                 DP_LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV];
3245
3246                 link->dpcd_caps.lttpr_caps.max_link_rate =
3247                                 lttpr_dpcd_data[DP_MAX_LINK_RATE_PHY_REPEATER -
3248                                                                 DP_LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV];
3249
3250                 link->dpcd_caps.lttpr_caps.phy_repeater_cnt =
3251                                 lttpr_dpcd_data[DP_PHY_REPEATER_CNT -
3252                                                                 DP_LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV];
3253
3254                 link->dpcd_caps.lttpr_caps.max_lane_count =
3255                                 lttpr_dpcd_data[DP_MAX_LANE_COUNT_PHY_REPEATER -
3256                                                                 DP_LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV];
3257
3258                 link->dpcd_caps.lttpr_caps.mode =
3259                                 lttpr_dpcd_data[DP_PHY_REPEATER_MODE -
3260                                                                 DP_LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV];
3261
3262                 link->dpcd_caps.lttpr_caps.max_ext_timeout =
3263                                 lttpr_dpcd_data[DP_PHY_REPEATER_EXTENDED_WAIT_TIMEOUT -
3264                                                                 DP_LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV];
3265
3266                 if (link->dpcd_caps.lttpr_caps.phy_repeater_cnt > 0 &&
3267                                 link->dpcd_caps.lttpr_caps.max_lane_count > 0 &&
3268                                 link->dpcd_caps.lttpr_caps.max_lane_count <= 4 &&
3269                                 link->dpcd_caps.lttpr_caps.revision.raw >= 0x14) {
3270                         link->is_lttpr_mode_transparent = false;
3271                 } else {
3272                         /*No lttpr reset timeout to its default value*/
3273                         link->is_lttpr_mode_transparent = true;
3274                         dc_link_aux_configure_timeout(link->ddc, LINK_AUX_DEFAULT_TIMEOUT_PERIOD);
3275                 }
3276
3277                 CONN_DATA_DETECT(link, lttpr_dpcd_data, sizeof(lttpr_dpcd_data), "LTTPR Caps: ");
3278         }
3279
3280         {
3281                 union training_aux_rd_interval aux_rd_interval;
3282
3283                 aux_rd_interval.raw =
3284                         dpcd_data[DP_TRAINING_AUX_RD_INTERVAL];
3285
3286                 link->dpcd_caps.ext_receiver_cap_field_present =
3287                                 aux_rd_interval.bits.EXT_RECEIVER_CAP_FIELD_PRESENT == 1;
3288
3289                 if (aux_rd_interval.bits.EXT_RECEIVER_CAP_FIELD_PRESENT == 1) {
3290                         uint8_t ext_cap_data[16];
3291
3292                         memset(ext_cap_data, '\0', sizeof(ext_cap_data));
3293                         for (i = 0; i < read_dpcd_retry_cnt; i++) {
3294                                 status = core_link_read_dpcd(
3295                                 link,
3296                                 DP_DP13_DPCD_REV,
3297                                 ext_cap_data,
3298                                 sizeof(ext_cap_data));
3299                                 if (status == DC_OK) {
3300                                         memcpy(dpcd_data, ext_cap_data, sizeof(dpcd_data));
3301                                         break;
3302                                 }
3303                         }
3304                         if (status != DC_OK)
3305                                 dm_error("%s: Read extend caps data failed, use cap from dpcd 0.\n", __func__);
3306                 }
3307         }
3308
3309         link->dpcd_caps.dpcd_rev.raw =
3310                         dpcd_data[DP_DPCD_REV - DP_DPCD_REV];
3311
3312         if (link->dpcd_caps.dpcd_rev.raw >= 0x14) {
3313                 for (i = 0; i < read_dpcd_retry_cnt; i++) {
3314                         status = core_link_read_dpcd(
3315                                         link,
3316                                         DP_DPRX_FEATURE_ENUMERATION_LIST,
3317                                         &dpcd_dprx_data,
3318                                         sizeof(dpcd_dprx_data));
3319                         if (status == DC_OK)
3320                                 break;
3321                 }
3322
3323                 link->dpcd_caps.dprx_feature.raw = dpcd_dprx_data;
3324
3325                 if (status != DC_OK)
3326                         dm_error("%s: Read DPRX caps data failed.\n", __func__);
3327         }
3328
3329         else {
3330                 link->dpcd_caps.dprx_feature.raw = 0;
3331         }
3332
3333
3334         /* Error condition checking...
3335          * It is impossible for Sink to report Max Lane Count = 0.
3336          * It is possible for Sink to report Max Link Rate = 0, if it is
3337          * an eDP device that is reporting specialized link rates in the
3338          * SUPPORTED_LINK_RATE table.
3339          */
3340         if (dpcd_data[DP_MAX_LANE_COUNT - DP_DPCD_REV] == 0)
3341                 return false;
3342
3343         ds_port.byte = dpcd_data[DP_DOWNSTREAMPORT_PRESENT -
3344                                  DP_DPCD_REV];
3345
3346         read_dp_device_vendor_id(link);
3347
3348         get_active_converter_info(ds_port.byte, link);
3349
3350         dp_wa_power_up_0010FA(link, dpcd_data, sizeof(dpcd_data));
3351
3352         down_strm_port_count.raw = dpcd_data[DP_DOWN_STREAM_PORT_COUNT -
3353                                  DP_DPCD_REV];
3354
3355         link->dpcd_caps.allow_invalid_MSA_timing_param =
3356                 down_strm_port_count.bits.IGNORE_MSA_TIMING_PARAM;
3357
3358         link->dpcd_caps.max_ln_count.raw = dpcd_data[
3359                 DP_MAX_LANE_COUNT - DP_DPCD_REV];
3360
3361         link->dpcd_caps.max_down_spread.raw = dpcd_data[
3362                 DP_MAX_DOWNSPREAD - DP_DPCD_REV];
3363
3364         link->reported_link_cap.lane_count =
3365                 link->dpcd_caps.max_ln_count.bits.MAX_LANE_COUNT;
3366         link->reported_link_cap.link_rate = dpcd_data[
3367                 DP_MAX_LINK_RATE - DP_DPCD_REV];
3368         link->reported_link_cap.link_spread =
3369                 link->dpcd_caps.max_down_spread.bits.MAX_DOWN_SPREAD ?
3370                 LINK_SPREAD_05_DOWNSPREAD_30KHZ : LINK_SPREAD_DISABLED;
3371
3372         edp_config_cap.raw = dpcd_data[
3373                 DP_EDP_CONFIGURATION_CAP - DP_DPCD_REV];
3374         link->dpcd_caps.panel_mode_edp =
3375                 edp_config_cap.bits.ALT_SCRAMBLER_RESET;
3376         link->dpcd_caps.dpcd_display_control_capable =
3377                 edp_config_cap.bits.DPCD_DISPLAY_CONTROL_CAPABLE;
3378
3379         link->test_pattern_enabled = false;
3380         link->compliance_test_state.raw = 0;
3381
3382         /* read sink count */
3383         core_link_read_dpcd(link,
3384                         DP_SINK_COUNT,
3385                         &link->dpcd_caps.sink_count.raw,
3386                         sizeof(link->dpcd_caps.sink_count.raw));
3387
3388         /* read sink ieee oui */
3389         core_link_read_dpcd(link,
3390                         DP_SINK_OUI,
3391                         (uint8_t *)(&sink_id),
3392                         sizeof(sink_id));
3393
3394         link->dpcd_caps.sink_dev_id =
3395                         (sink_id.ieee_oui[0] << 16) +
3396                         (sink_id.ieee_oui[1] << 8) +
3397                         (sink_id.ieee_oui[2]);
3398
3399         memmove(
3400                 link->dpcd_caps.sink_dev_id_str,
3401                 sink_id.ieee_device_id,
3402                 sizeof(sink_id.ieee_device_id));
3403
3404         core_link_read_dpcd(
3405                 link,
3406                 DP_SINK_HW_REVISION_START,
3407                 (uint8_t *)&dp_hw_fw_revision,
3408                 sizeof(dp_hw_fw_revision));
3409
3410         link->dpcd_caps.sink_hw_revision =
3411                 dp_hw_fw_revision.ieee_hw_rev;
3412
3413         memmove(
3414                 link->dpcd_caps.sink_fw_revision,
3415                 dp_hw_fw_revision.ieee_fw_rev,
3416                 sizeof(dp_hw_fw_revision.ieee_fw_rev));
3417
3418         memset(&link->dpcd_caps.dsc_caps, '\0',
3419                         sizeof(link->dpcd_caps.dsc_caps));
3420         memset(&link->dpcd_caps.fec_cap, '\0', sizeof(link->dpcd_caps.fec_cap));
3421         /* Read DSC and FEC sink capabilities if DP revision is 1.4 and up */
3422         if (link->dpcd_caps.dpcd_rev.raw >= DPCD_REV_14) {
3423                 status = core_link_read_dpcd(
3424                                 link,
3425                                 DP_FEC_CAPABILITY,
3426                                 &link->dpcd_caps.fec_cap.raw,
3427                                 sizeof(link->dpcd_caps.fec_cap.raw));
3428                 status = core_link_read_dpcd(
3429                                 link,
3430                                 DP_DSC_SUPPORT,
3431                                 link->dpcd_caps.dsc_caps.dsc_basic_caps.raw,
3432                                 sizeof(link->dpcd_caps.dsc_caps.dsc_basic_caps.raw));
3433                 status = core_link_read_dpcd(
3434                                 link,
3435                                 DP_DSC_BRANCH_OVERALL_THROUGHPUT_0,
3436                                 link->dpcd_caps.dsc_caps.dsc_ext_caps.raw,
3437                                 sizeof(link->dpcd_caps.dsc_caps.dsc_ext_caps.raw));
3438         }
3439
3440         /* Connectivity log: detection */
3441         CONN_DATA_DETECT(link, dpcd_data, sizeof(dpcd_data), "Rx Caps: ");
3442
3443         return true;
3444 }
3445
3446 bool dp_overwrite_extended_receiver_cap(struct dc_link *link)
3447 {
3448         uint8_t dpcd_data[16];
3449         uint32_t read_dpcd_retry_cnt = 3;
3450         enum dc_status status = DC_ERROR_UNEXPECTED;
3451         union dp_downstream_port_present ds_port = { 0 };
3452         union down_stream_port_count down_strm_port_count;
3453         union edp_configuration_cap edp_config_cap;
3454
3455         int i;
3456
3457         for (i = 0; i < read_dpcd_retry_cnt; i++) {
3458                 status = core_link_read_dpcd(
3459                                 link,
3460                                 DP_DPCD_REV,
3461                                 dpcd_data,
3462                                 sizeof(dpcd_data));
3463                 if (status == DC_OK)
3464                         break;
3465         }
3466
3467         link->dpcd_caps.dpcd_rev.raw =
3468                 dpcd_data[DP_DPCD_REV - DP_DPCD_REV];
3469
3470         if (dpcd_data[DP_MAX_LANE_COUNT - DP_DPCD_REV] == 0)
3471                 return false;
3472
3473         ds_port.byte = dpcd_data[DP_DOWNSTREAMPORT_PRESENT -
3474                         DP_DPCD_REV];
3475
3476         get_active_converter_info(ds_port.byte, link);
3477
3478         down_strm_port_count.raw = dpcd_data[DP_DOWN_STREAM_PORT_COUNT -
3479                         DP_DPCD_REV];
3480
3481         link->dpcd_caps.allow_invalid_MSA_timing_param =
3482                 down_strm_port_count.bits.IGNORE_MSA_TIMING_PARAM;
3483
3484         link->dpcd_caps.max_ln_count.raw = dpcd_data[
3485                 DP_MAX_LANE_COUNT - DP_DPCD_REV];
3486
3487         link->dpcd_caps.max_down_spread.raw = dpcd_data[
3488                 DP_MAX_DOWNSPREAD - DP_DPCD_REV];
3489
3490         link->reported_link_cap.lane_count =
3491                 link->dpcd_caps.max_ln_count.bits.MAX_LANE_COUNT;
3492         link->reported_link_cap.link_rate = dpcd_data[
3493                 DP_MAX_LINK_RATE - DP_DPCD_REV];
3494         link->reported_link_cap.link_spread =
3495                 link->dpcd_caps.max_down_spread.bits.MAX_DOWN_SPREAD ?
3496                 LINK_SPREAD_05_DOWNSPREAD_30KHZ : LINK_SPREAD_DISABLED;
3497
3498         edp_config_cap.raw = dpcd_data[
3499                 DP_EDP_CONFIGURATION_CAP - DP_DPCD_REV];
3500         link->dpcd_caps.panel_mode_edp =
3501                 edp_config_cap.bits.ALT_SCRAMBLER_RESET;
3502         link->dpcd_caps.dpcd_display_control_capable =
3503                 edp_config_cap.bits.DPCD_DISPLAY_CONTROL_CAPABLE;
3504
3505         return true;
3506 }
3507
3508 bool detect_dp_sink_caps(struct dc_link *link)
3509 {
3510         return retrieve_link_cap(link);
3511
3512         /* dc init_hw has power encoder using default
3513          * signal for connector. For native DP, no
3514          * need to power up encoder again. If not native
3515          * DP, hw_init may need check signal or power up
3516          * encoder here.
3517          */
3518         /* TODO save sink caps in link->sink */
3519 }
3520
3521 enum dc_link_rate linkRateInKHzToLinkRateMultiplier(uint32_t link_rate_in_khz)
3522 {
3523         enum dc_link_rate link_rate;
3524         // LinkRate is normally stored as a multiplier of 0.27 Gbps per lane. Do the translation.
3525         switch (link_rate_in_khz) {
3526         case 1620000:
3527                 link_rate = LINK_RATE_LOW;              // Rate_1 (RBR)         - 1.62 Gbps/Lane
3528                 break;
3529         case 2160000:
3530                 link_rate = LINK_RATE_RATE_2;   // Rate_2                       - 2.16 Gbps/Lane
3531                 break;
3532         case 2430000:
3533                 link_rate = LINK_RATE_RATE_3;   // Rate_3                       - 2.43 Gbps/Lane
3534                 break;
3535         case 2700000:
3536                 link_rate = LINK_RATE_HIGH;             // Rate_4 (HBR)         - 2.70 Gbps/Lane
3537                 break;
3538         case 3240000:
3539                 link_rate = LINK_RATE_RBR2;             // Rate_5 (RBR2)        - 3.24 Gbps/Lane
3540                 break;
3541         case 4320000:
3542                 link_rate = LINK_RATE_RATE_6;   // Rate_6                       - 4.32 Gbps/Lane
3543                 break;
3544         case 5400000:
3545                 link_rate = LINK_RATE_HIGH2;    // Rate_7 (HBR2)        - 5.40 Gbps/Lane
3546                 break;
3547         case 8100000:
3548                 link_rate = LINK_RATE_HIGH3;    // Rate_8 (HBR3)        - 8.10 Gbps/Lane
3549                 break;
3550         default:
3551                 link_rate = LINK_RATE_UNKNOWN;
3552                 break;
3553         }
3554         return link_rate;
3555 }
3556
3557 void detect_edp_sink_caps(struct dc_link *link)
3558 {
3559         uint8_t supported_link_rates[16];
3560         uint32_t entry;
3561         uint32_t link_rate_in_khz;
3562         enum dc_link_rate link_rate = LINK_RATE_UNKNOWN;
3563
3564         retrieve_link_cap(link);
3565         link->dpcd_caps.edp_supported_link_rates_count = 0;
3566         memset(supported_link_rates, 0, sizeof(supported_link_rates));
3567
3568         if (link->dpcd_caps.dpcd_rev.raw >= DPCD_REV_14 &&
3569                         (link->dc->config.optimize_edp_link_rate ||
3570                         link->reported_link_cap.link_rate == LINK_RATE_UNKNOWN)) {
3571                 // Read DPCD 00010h - 0001Fh 16 bytes at one shot
3572                 core_link_read_dpcd(link, DP_SUPPORTED_LINK_RATES,
3573                                                         supported_link_rates, sizeof(supported_link_rates));
3574
3575                 for (entry = 0; entry < 16; entry += 2) {
3576                         // DPCD register reports per-lane link rate = 16-bit link rate capability
3577                         // value X 200 kHz. Need multiplier to find link rate in kHz.
3578                         link_rate_in_khz = (supported_link_rates[entry+1] * 0x100 +
3579                                                                                 supported_link_rates[entry]) * 200;
3580
3581                         if (link_rate_in_khz != 0) {
3582                                 link_rate = linkRateInKHzToLinkRateMultiplier(link_rate_in_khz);
3583                                 link->dpcd_caps.edp_supported_link_rates[link->dpcd_caps.edp_supported_link_rates_count] = link_rate;
3584                                 link->dpcd_caps.edp_supported_link_rates_count++;
3585
3586                                 if (link->reported_link_cap.link_rate < link_rate)
3587                                         link->reported_link_cap.link_rate = link_rate;
3588                         }
3589                 }
3590         }
3591         link->verified_link_cap = link->reported_link_cap;
3592 }
3593
3594 void dc_link_dp_enable_hpd(const struct dc_link *link)
3595 {
3596         struct link_encoder *encoder = link->link_enc;
3597
3598         if (encoder != NULL && encoder->funcs->enable_hpd != NULL)
3599                 encoder->funcs->enable_hpd(encoder);
3600 }
3601
3602 void dc_link_dp_disable_hpd(const struct dc_link *link)
3603 {
3604         struct link_encoder *encoder = link->link_enc;
3605
3606         if (encoder != NULL && encoder->funcs->enable_hpd != NULL)
3607                 encoder->funcs->disable_hpd(encoder);
3608 }
3609
3610 static bool is_dp_phy_pattern(enum dp_test_pattern test_pattern)
3611 {
3612         if ((DP_TEST_PATTERN_PHY_PATTERN_BEGIN <= test_pattern &&
3613                         test_pattern <= DP_TEST_PATTERN_PHY_PATTERN_END) ||
3614                         test_pattern == DP_TEST_PATTERN_VIDEO_MODE)
3615                 return true;
3616         else
3617                 return false;
3618 }
3619
3620 static void set_crtc_test_pattern(struct dc_link *link,
3621                                 struct pipe_ctx *pipe_ctx,
3622                                 enum dp_test_pattern test_pattern,
3623                                 enum dp_test_pattern_color_space test_pattern_color_space)
3624 {
3625         enum controller_dp_test_pattern controller_test_pattern;
3626         enum dc_color_depth color_depth = pipe_ctx->
3627                 stream->timing.display_color_depth;
3628         struct bit_depth_reduction_params params;
3629         struct output_pixel_processor *opp = pipe_ctx->stream_res.opp;
3630         int width = pipe_ctx->stream->timing.h_addressable +
3631                 pipe_ctx->stream->timing.h_border_left +
3632                 pipe_ctx->stream->timing.h_border_right;
3633         int height = pipe_ctx->stream->timing.v_addressable +
3634                 pipe_ctx->stream->timing.v_border_bottom +
3635                 pipe_ctx->stream->timing.v_border_top;
3636
3637         memset(&params, 0, sizeof(params));
3638
3639         switch (test_pattern) {
3640         case DP_TEST_PATTERN_COLOR_SQUARES:
3641                 controller_test_pattern =
3642                                 CONTROLLER_DP_TEST_PATTERN_COLORSQUARES;
3643         break;
3644         case DP_TEST_PATTERN_COLOR_SQUARES_CEA:
3645                 controller_test_pattern =
3646                                 CONTROLLER_DP_TEST_PATTERN_COLORSQUARES_CEA;
3647         break;
3648         case DP_TEST_PATTERN_VERTICAL_BARS:
3649                 controller_test_pattern =
3650                                 CONTROLLER_DP_TEST_PATTERN_VERTICALBARS;
3651         break;
3652         case DP_TEST_PATTERN_HORIZONTAL_BARS:
3653                 controller_test_pattern =
3654                                 CONTROLLER_DP_TEST_PATTERN_HORIZONTALBARS;
3655         break;
3656         case DP_TEST_PATTERN_COLOR_RAMP:
3657                 controller_test_pattern =
3658                                 CONTROLLER_DP_TEST_PATTERN_COLORRAMP;
3659         break;
3660         default:
3661                 controller_test_pattern =
3662                                 CONTROLLER_DP_TEST_PATTERN_VIDEOMODE;
3663         break;
3664         }
3665
3666         switch (test_pattern) {
3667         case DP_TEST_PATTERN_COLOR_SQUARES:
3668         case DP_TEST_PATTERN_COLOR_SQUARES_CEA:
3669         case DP_TEST_PATTERN_VERTICAL_BARS:
3670         case DP_TEST_PATTERN_HORIZONTAL_BARS:
3671         case DP_TEST_PATTERN_COLOR_RAMP:
3672         {
3673                 /* disable bit depth reduction */
3674                 pipe_ctx->stream->bit_depth_params = params;
3675                 opp->funcs->opp_program_bit_depth_reduction(opp, &params);
3676                 if (pipe_ctx->stream_res.tg->funcs->set_test_pattern)
3677                         pipe_ctx->stream_res.tg->funcs->set_test_pattern(pipe_ctx->stream_res.tg,
3678                                 controller_test_pattern, color_depth);
3679                 else if (opp->funcs->opp_set_disp_pattern_generator) {
3680                         struct pipe_ctx *odm_pipe;
3681                         enum controller_dp_color_space controller_color_space;
3682                         int opp_cnt = 1;
3683                         int count;
3684
3685                         switch (test_pattern_color_space) {
3686                         case DP_TEST_PATTERN_COLOR_SPACE_RGB:
3687                                 controller_color_space = CONTROLLER_DP_COLOR_SPACE_RGB;
3688                                 break;
3689                         case DP_TEST_PATTERN_COLOR_SPACE_YCBCR601:
3690                                 controller_color_space = CONTROLLER_DP_COLOR_SPACE_YCBCR601;
3691                                 break;
3692                         case DP_TEST_PATTERN_COLOR_SPACE_YCBCR709:
3693                                 controller_color_space = CONTROLLER_DP_COLOR_SPACE_YCBCR709;
3694                                 break;
3695                         case DP_TEST_PATTERN_COLOR_SPACE_UNDEFINED:
3696                         default:
3697                                 controller_color_space = CONTROLLER_DP_COLOR_SPACE_UDEFINED;
3698                                 DC_LOG_ERROR("%s: Color space must be defined for test pattern", __func__);
3699                                 ASSERT(0);
3700                                 break;
3701                         }
3702
3703                         for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe)
3704                                 opp_cnt++;
3705
3706                         width /= opp_cnt;
3707
3708                         for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe) {
3709                                 struct output_pixel_processor *odm_opp = odm_pipe->stream_res.opp;
3710
3711                                 odm_opp->funcs->opp_program_bit_depth_reduction(odm_opp, &params);
3712                                 odm_opp->funcs->opp_set_disp_pattern_generator(odm_opp,
3713                                         controller_test_pattern,
3714                                         controller_color_space,
3715                                         color_depth,
3716                                         NULL,
3717                                         width,
3718                                         height);
3719                         }
3720                         opp->funcs->opp_set_disp_pattern_generator(opp,
3721                                 controller_test_pattern,
3722                                 controller_color_space,
3723                                 color_depth,
3724                                 NULL,
3725                                 width,
3726                                 height);
3727                         /* wait for dpg to blank pixel data with test pattern */
3728                         for (count = 0; count < 1000; count++) {
3729                                 if (opp->funcs->dpg_is_blanked(opp))
3730                                         break;
3731                                 udelay(100);
3732                         }
3733                 }
3734         }
3735         break;
3736         case DP_TEST_PATTERN_VIDEO_MODE:
3737         {
3738                 /* restore bitdepth reduction */
3739                 resource_build_bit_depth_reduction_params(pipe_ctx->stream, &params);
3740                 pipe_ctx->stream->bit_depth_params = params;
3741                 opp->funcs->opp_program_bit_depth_reduction(opp, &params);
3742                 if (pipe_ctx->stream_res.tg->funcs->set_test_pattern)
3743                         pipe_ctx->stream_res.tg->funcs->set_test_pattern(pipe_ctx->stream_res.tg,
3744                                 CONTROLLER_DP_TEST_PATTERN_VIDEOMODE,
3745                                 color_depth);
3746                 else if (opp->funcs->opp_set_disp_pattern_generator) {
3747                         struct pipe_ctx *odm_pipe;
3748                         int opp_cnt = 1;
3749
3750                         for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe)
3751                                 opp_cnt++;
3752
3753                         width /= opp_cnt;
3754                         for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe) {
3755                                 struct output_pixel_processor *odm_opp = odm_pipe->stream_res.opp;
3756
3757                                 odm_opp->funcs->opp_program_bit_depth_reduction(odm_opp, &params);
3758                                 odm_opp->funcs->opp_set_disp_pattern_generator(odm_opp,
3759                                         CONTROLLER_DP_TEST_PATTERN_VIDEOMODE,
3760                                         CONTROLLER_DP_COLOR_SPACE_UDEFINED,
3761                                         color_depth,
3762                                         NULL,
3763                                         width,
3764                                         height);
3765                         }
3766                         opp->funcs->opp_set_disp_pattern_generator(opp,
3767                                 CONTROLLER_DP_TEST_PATTERN_VIDEOMODE,
3768                                 CONTROLLER_DP_COLOR_SPACE_UDEFINED,
3769                                 color_depth,
3770                                 NULL,
3771                                 width,
3772                                 height);
3773                 }
3774         }
3775         break;
3776
3777         default:
3778         break;
3779         }
3780 }
3781
3782 bool dc_link_dp_set_test_pattern(
3783         struct dc_link *link,
3784         enum dp_test_pattern test_pattern,
3785         enum dp_test_pattern_color_space test_pattern_color_space,
3786         const struct link_training_settings *p_link_settings,
3787         const unsigned char *p_custom_pattern,
3788         unsigned int cust_pattern_size)
3789 {
3790         struct pipe_ctx *pipes = link->dc->current_state->res_ctx.pipe_ctx;
3791         struct pipe_ctx *pipe_ctx = &pipes[0];
3792         unsigned int lane;
3793         unsigned int i;
3794         unsigned char link_qual_pattern[LANE_COUNT_DP_MAX] = {0};
3795         union dpcd_training_pattern training_pattern;
3796         enum dpcd_phy_test_patterns pattern;
3797
3798         memset(&training_pattern, 0, sizeof(training_pattern));
3799
3800         for (i = 0; i < MAX_PIPES; i++) {
3801                 if (pipes[i].stream->link == link && !pipes[i].top_pipe && !pipes[i].prev_odm_pipe) {
3802                         pipe_ctx = &pipes[i];
3803                         break;
3804                 }
3805         }
3806
3807         /* Reset CRTC Test Pattern if it is currently running and request
3808          * is VideoMode Reset DP Phy Test Pattern if it is currently running
3809          * and request is VideoMode
3810          */
3811         if (link->test_pattern_enabled && test_pattern ==
3812                         DP_TEST_PATTERN_VIDEO_MODE) {
3813                 /* Set CRTC Test Pattern */
3814                 set_crtc_test_pattern(link, pipe_ctx, test_pattern, test_pattern_color_space);
3815                 dp_set_hw_test_pattern(link, test_pattern,
3816                                 (uint8_t *)p_custom_pattern,
3817                                 (uint32_t)cust_pattern_size);
3818
3819                 /* Unblank Stream */
3820                 link->dc->hwss.unblank_stream(
3821                         pipe_ctx,
3822                         &link->verified_link_cap);
3823                 /* TODO:m_pHwss->MuteAudioEndpoint
3824                  * (pPathMode->pDisplayPath, false);
3825                  */
3826
3827                 /* Reset Test Pattern state */
3828                 link->test_pattern_enabled = false;
3829
3830                 return true;
3831         }
3832
3833         /* Check for PHY Test Patterns */
3834         if (is_dp_phy_pattern(test_pattern)) {
3835                 /* Set DPCD Lane Settings before running test pattern */
3836                 if (p_link_settings != NULL) {
3837                         dp_set_hw_lane_settings(link, p_link_settings, DPRX);
3838                         dpcd_set_lane_settings(link, p_link_settings, DPRX);
3839                 }
3840
3841                 /* Blank stream if running test pattern */
3842                 if (test_pattern != DP_TEST_PATTERN_VIDEO_MODE) {
3843                         /*TODO:
3844                          * m_pHwss->
3845                          * MuteAudioEndpoint(pPathMode->pDisplayPath, true);
3846                          */
3847                         /* Blank stream */
3848                         pipes->stream_res.stream_enc->funcs->dp_blank(pipe_ctx->stream_res.stream_enc);
3849                 }
3850
3851                 dp_set_hw_test_pattern(link, test_pattern,
3852                                 (uint8_t *)p_custom_pattern,
3853                                 (uint32_t)cust_pattern_size);
3854
3855                 if (test_pattern != DP_TEST_PATTERN_VIDEO_MODE) {
3856                         /* Set Test Pattern state */
3857                         link->test_pattern_enabled = true;
3858                         if (p_link_settings != NULL)
3859                                 dpcd_set_link_settings(link,
3860                                                 p_link_settings);
3861                 }
3862
3863                 switch (test_pattern) {
3864                 case DP_TEST_PATTERN_VIDEO_MODE:
3865                         pattern = PHY_TEST_PATTERN_NONE;
3866                         break;
3867                 case DP_TEST_PATTERN_D102:
3868                         pattern = PHY_TEST_PATTERN_D10_2;
3869                         break;
3870                 case DP_TEST_PATTERN_SYMBOL_ERROR:
3871                         pattern = PHY_TEST_PATTERN_SYMBOL_ERROR;
3872                         break;
3873                 case DP_TEST_PATTERN_PRBS7:
3874                         pattern = PHY_TEST_PATTERN_PRBS7;
3875                         break;
3876                 case DP_TEST_PATTERN_80BIT_CUSTOM:
3877                         pattern = PHY_TEST_PATTERN_80BIT_CUSTOM;
3878                         break;
3879                 case DP_TEST_PATTERN_CP2520_1:
3880                         pattern = PHY_TEST_PATTERN_CP2520_1;
3881                         break;
3882                 case DP_TEST_PATTERN_CP2520_2:
3883                         pattern = PHY_TEST_PATTERN_CP2520_2;
3884                         break;
3885                 case DP_TEST_PATTERN_CP2520_3:
3886                         pattern = PHY_TEST_PATTERN_CP2520_3;
3887                         break;
3888                 default:
3889                         return false;
3890                 }
3891
3892                 if (test_pattern == DP_TEST_PATTERN_VIDEO_MODE
3893                 /*TODO:&& !pPathMode->pDisplayPath->IsTargetPoweredOn()*/)
3894                         return false;
3895
3896                 if (link->dpcd_caps.dpcd_rev.raw >= DPCD_REV_12) {
3897                         /* tell receiver that we are sending qualification
3898                          * pattern DP 1.2 or later - DP receiver's link quality
3899                          * pattern is set using DPCD LINK_QUAL_LANEx_SET
3900                          * register (0x10B~0x10E)\
3901                          */
3902                         for (lane = 0; lane < LANE_COUNT_DP_MAX; lane++)
3903                                 link_qual_pattern[lane] =
3904                                                 (unsigned char)(pattern);
3905
3906                         core_link_write_dpcd(link,
3907                                         DP_LINK_QUAL_LANE0_SET,
3908                                         link_qual_pattern,
3909                                         sizeof(link_qual_pattern));
3910                 } else if (link->dpcd_caps.dpcd_rev.raw >= DPCD_REV_10 ||
3911                            link->dpcd_caps.dpcd_rev.raw == 0) {
3912                         /* tell receiver that we are sending qualification
3913                          * pattern DP 1.1a or earlier - DP receiver's link
3914                          * quality pattern is set using
3915                          * DPCD TRAINING_PATTERN_SET -> LINK_QUAL_PATTERN_SET
3916                          * register (0x102). We will use v_1.3 when we are
3917                          * setting test pattern for DP 1.1.
3918                          */
3919                         core_link_read_dpcd(link, DP_TRAINING_PATTERN_SET,
3920                                             &training_pattern.raw,
3921                                             sizeof(training_pattern));
3922                         training_pattern.v1_3.LINK_QUAL_PATTERN_SET = pattern;
3923                         core_link_write_dpcd(link, DP_TRAINING_PATTERN_SET,
3924                                              &training_pattern.raw,
3925                                              sizeof(training_pattern));
3926                 }
3927         } else {
3928                 enum dc_color_space color_space = COLOR_SPACE_UNKNOWN;
3929
3930                 switch (test_pattern_color_space) {
3931                 case DP_TEST_PATTERN_COLOR_SPACE_RGB:
3932                         color_space = COLOR_SPACE_SRGB;
3933                         if (test_pattern == DP_TEST_PATTERN_COLOR_SQUARES_CEA)
3934                                 color_space = COLOR_SPACE_SRGB_LIMITED;
3935                         break;
3936
3937                 case DP_TEST_PATTERN_COLOR_SPACE_YCBCR601:
3938                         color_space = COLOR_SPACE_YCBCR601;
3939                         if (test_pattern == DP_TEST_PATTERN_COLOR_SQUARES_CEA)
3940                                 color_space = COLOR_SPACE_YCBCR601_LIMITED;
3941                         break;
3942                 case DP_TEST_PATTERN_COLOR_SPACE_YCBCR709:
3943                         color_space = COLOR_SPACE_YCBCR709;
3944                         if (test_pattern == DP_TEST_PATTERN_COLOR_SQUARES_CEA)
3945                                 color_space = COLOR_SPACE_YCBCR709_LIMITED;
3946                         break;
3947                 default:
3948                         break;
3949                 }
3950                 /* update MSA to requested color space */
3951                 pipe_ctx->stream_res.stream_enc->funcs->dp_set_stream_attribute(pipe_ctx->stream_res.stream_enc,
3952                                 &pipe_ctx->stream->timing,
3953                                 color_space,
3954                                 pipe_ctx->stream->use_vsc_sdp_for_colorimetry,
3955                                 link->dpcd_caps.dprx_feature.bits.SST_SPLIT_SDP_CAP);
3956
3957                 /* CRTC Patterns */
3958                 set_crtc_test_pattern(link, pipe_ctx, test_pattern, test_pattern_color_space);
3959
3960                 /* Set Test Pattern state */
3961                 link->test_pattern_enabled = true;
3962         }
3963
3964         return true;
3965 }
3966
3967 void dp_enable_mst_on_sink(struct dc_link *link, bool enable)
3968 {
3969         unsigned char mstmCntl;
3970
3971         core_link_read_dpcd(link, DP_MSTM_CTRL, &mstmCntl, 1);
3972         if (enable)
3973                 mstmCntl |= DP_MST_EN;
3974         else
3975                 mstmCntl &= (~DP_MST_EN);
3976
3977         core_link_write_dpcd(link, DP_MSTM_CTRL, &mstmCntl, 1);
3978 }
3979
3980 void dp_set_panel_mode(struct dc_link *link, enum dp_panel_mode panel_mode)
3981 {
3982         union dpcd_edp_config edp_config_set;
3983         bool panel_mode_edp = false;
3984
3985         memset(&edp_config_set, '\0', sizeof(union dpcd_edp_config));
3986
3987         if (panel_mode != DP_PANEL_MODE_DEFAULT) {
3988
3989                 switch (panel_mode) {
3990                 case DP_PANEL_MODE_EDP:
3991                 case DP_PANEL_MODE_SPECIAL:
3992                         panel_mode_edp = true;
3993                         break;
3994
3995                 default:
3996                                 break;
3997                 }
3998
3999                 /*set edp panel mode in receiver*/
4000                 core_link_read_dpcd(
4001                         link,
4002                         DP_EDP_CONFIGURATION_SET,
4003                         &edp_config_set.raw,
4004                         sizeof(edp_config_set.raw));
4005
4006                 if (edp_config_set.bits.PANEL_MODE_EDP
4007                         != panel_mode_edp) {
4008                         enum ddc_result result = DDC_RESULT_UNKNOWN;
4009
4010                         edp_config_set.bits.PANEL_MODE_EDP =
4011                         panel_mode_edp;
4012                         result = core_link_write_dpcd(
4013                                 link,
4014                                 DP_EDP_CONFIGURATION_SET,
4015                                 &edp_config_set.raw,
4016                                 sizeof(edp_config_set.raw));
4017
4018                         ASSERT(result == DDC_RESULT_SUCESSFULL);
4019                 }
4020         }
4021         DC_LOG_DETECTION_DP_CAPS("Link: %d eDP panel mode supported: %d "
4022                  "eDP panel mode enabled: %d \n",
4023                  link->link_index,
4024                  link->dpcd_caps.panel_mode_edp,
4025                  panel_mode_edp);
4026 }
4027
4028 enum dp_panel_mode dp_get_panel_mode(struct dc_link *link)
4029 {
4030         /* We need to explicitly check that connector
4031          * is not DP. Some Travis_VGA get reported
4032          * by video bios as DP.
4033          */
4034         if (link->connector_signal != SIGNAL_TYPE_DISPLAY_PORT) {
4035
4036                 switch (link->dpcd_caps.branch_dev_id) {
4037                 case DP_BRANCH_DEVICE_ID_0022B9:
4038                         /* alternate scrambler reset is required for Travis
4039                          * for the case when external chip does not
4040                          * provide sink device id, alternate scrambler
4041                          * scheme will  be overriden later by querying
4042                          * Encoder features
4043                          */
4044                         if (strncmp(
4045                                 link->dpcd_caps.branch_dev_name,
4046                                 DP_VGA_LVDS_CONVERTER_ID_2,
4047                                 sizeof(
4048                                 link->dpcd_caps.
4049                                 branch_dev_name)) == 0) {
4050                                         return DP_PANEL_MODE_SPECIAL;
4051                         }
4052                         break;
4053                 case DP_BRANCH_DEVICE_ID_00001A:
4054                         /* alternate scrambler reset is required for Travis
4055                          * for the case when external chip does not provide
4056                          * sink device id, alternate scrambler scheme will
4057                          * be overriden later by querying Encoder feature
4058                          */
4059                         if (strncmp(link->dpcd_caps.branch_dev_name,
4060                                 DP_VGA_LVDS_CONVERTER_ID_3,
4061                                 sizeof(
4062                                 link->dpcd_caps.
4063                                 branch_dev_name)) == 0) {
4064                                         return DP_PANEL_MODE_SPECIAL;
4065                         }
4066                         break;
4067                 default:
4068                         break;
4069                 }
4070         }
4071
4072         if (link->dpcd_caps.panel_mode_edp) {
4073                 return DP_PANEL_MODE_EDP;
4074         }
4075
4076         return DP_PANEL_MODE_DEFAULT;
4077 }
4078
4079 void dp_set_fec_ready(struct dc_link *link, bool ready)
4080 {
4081         /* FEC has to be "set ready" before the link training.
4082          * The policy is to always train with FEC
4083          * if the sink supports it and leave it enabled on link.
4084          * If FEC is not supported, disable it.
4085          */
4086         struct link_encoder *link_enc = link->link_enc;
4087         uint8_t fec_config = 0;
4088
4089         if (link->dc->debug.disable_fec ||
4090                         IS_FPGA_MAXIMUS_DC(link->ctx->dce_environment))
4091                 return;
4092
4093         if (link_enc->funcs->fec_set_ready &&
4094                         link->dpcd_caps.fec_cap.bits.FEC_CAPABLE) {
4095                 if (ready) {
4096                         fec_config = 1;
4097                         if (core_link_write_dpcd(link,
4098                                         DP_FEC_CONFIGURATION,
4099                                         &fec_config,
4100                                         sizeof(fec_config)) == DC_OK) {
4101                                 link_enc->funcs->fec_set_ready(link_enc, true);
4102                                 link->fec_state = dc_link_fec_ready;
4103                         } else {
4104                                 link->link_enc->funcs->fec_set_ready(link->link_enc, false);
4105                                 link->fec_state = dc_link_fec_not_ready;
4106                                 dm_error("dpcd write failed to set fec_ready");
4107                         }
4108                 } else if (link->fec_state == dc_link_fec_ready) {
4109                         fec_config = 0;
4110                         core_link_write_dpcd(link,
4111                                         DP_FEC_CONFIGURATION,
4112                                         &fec_config,
4113                                         sizeof(fec_config));
4114                         link->link_enc->funcs->fec_set_ready(
4115                                         link->link_enc, false);
4116                         link->fec_state = dc_link_fec_not_ready;
4117                 }
4118         }
4119 }
4120
4121 void dp_set_fec_enable(struct dc_link *link, bool enable)
4122 {
4123         struct link_encoder *link_enc = link->link_enc;
4124
4125         if (link->dc->debug.disable_fec ||
4126                         IS_FPGA_MAXIMUS_DC(link->ctx->dce_environment))
4127                 return;
4128
4129         if (link_enc->funcs->fec_set_enable &&
4130                         link->dpcd_caps.fec_cap.bits.FEC_CAPABLE) {
4131                 if (link->fec_state == dc_link_fec_ready && enable) {
4132                         /* Accord to DP spec, FEC enable sequence can first
4133                          * be transmitted anytime after 1000 LL codes have
4134                          * been transmitted on the link after link training
4135                          * completion. Using 1 lane RBR should have the maximum
4136                          * time for transmitting 1000 LL codes which is 6.173 us.
4137                          * So use 7 microseconds delay instead.
4138                          */
4139                         udelay(7);
4140                         link_enc->funcs->fec_set_enable(link_enc, true);
4141                         link->fec_state = dc_link_fec_enabled;
4142                 } else if (link->fec_state == dc_link_fec_enabled && !enable) {
4143                         link_enc->funcs->fec_set_enable(link_enc, false);
4144                         link->fec_state = dc_link_fec_ready;
4145                 }
4146         }
4147 }
4148