drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c

   1 /* Copyright 2015 Advanced Micro Devices, Inc. */
   2
   3
   4 #include "dm_services.h"
   5 #include "dc.h"
   6 #include "inc/core_types.h"
   7 #include "include/ddc_service_types.h"
   8 #include "include/i2caux_interface.h"
   9 #include "link_hwss.h"
  10 #include "hw_sequencer.h"
  11 #include "dc_link_dp.h"
  12 #include "dc_link_ddc.h"
  13 #include "dm_helpers.h"
  14 #include "dpcd_defs.h"
  15 #include "dsc.h"
  16 #include "resource.h"
  17
  18 static uint8_t convert_to_count(uint8_t lttpr_repeater_count)
  19 {
  20         switch (lttpr_repeater_count) {
  21         case 0x80: // 1 lttpr repeater
  22                 return 1;
  23         case 0x40: // 2 lttpr repeaters
  24                 return 2;
  25         case 0x20: // 3 lttpr repeaters
  26                 return 3;
  27         case 0x10: // 4 lttpr repeaters
  28                 return 4;
  29         case 0x08: // 5 lttpr repeaters
  30                 return 5;
  31         case 0x04: // 6 lttpr repeaters
  32                 return 6;
  33         case 0x02: // 7 lttpr repeaters
  34                 return 7;
  35         case 0x01: // 8 lttpr repeaters
  36                 return 8;
  37         default:
  38                 break;
  39         }
  40         return 0; // invalid value
  41 }
  42
  43 static inline bool is_immediate_downstream(struct dc_link *link, uint32_t offset)
  44 {
  45         return (convert_to_count(link->dpcd_caps.lttpr_caps.phy_repeater_cnt) == offset);
  46 }
  47
  48 enum dc_status core_link_read_dpcd(
  49         struct dc_link *link,
  50         uint32_t address,
  51         uint8_t *data,
  52         uint32_t size)
  53 {
  54         if (!link->aux_access_disabled &&
  55                         !dm_helpers_dp_read_dpcd(link->ctx,
  56                         link, address, data, size)) {
  57                 return DC_ERROR_UNEXPECTED;
  58         }
  59
  60         return DC_OK;
  61 }
  62
  63 enum dc_status core_link_write_dpcd(
  64         struct dc_link *link,
  65         uint32_t address,
  66         const uint8_t *data,
  67         uint32_t size)
  68 {
  69         if (!link->aux_access_disabled &&
  70                         !dm_helpers_dp_write_dpcd(link->ctx,
  71                         link, address, data, size)) {
  72                 return DC_ERROR_UNEXPECTED;
  73         }
  74
  75         return DC_OK;
  76 }
  77
  78 void dp_receiver_power_ctrl(struct dc_link *link, bool on)
  79 {
  80         uint8_t state;
  81
  82         state = on ? DP_POWER_STATE_D0 : DP_POWER_STATE_D3;
  83
  84         if (link->sync_lt_in_progress)
  85                 return;
  86
  87         core_link_write_dpcd(link, DP_SET_POWER, &state,
  88                         sizeof(state));
  89 }
  90
  91 void dp_enable_link_phy(
  92         struct dc_link *link,
  93         enum signal_type signal,
  94         enum clock_source_id clock_source,
  95         const struct dc_link_settings *link_settings)
  96 {
  97         struct link_encoder *link_enc = link->link_enc;
  98         struct dc  *dc = link->ctx->dc;
  99         struct dmcu *dmcu = dc->res_pool->dmcu;
 100
 101         struct pipe_ctx *pipes =
 102                         link->dc->current_state->res_ctx.pipe_ctx;
 103         struct clock_source *dp_cs =
 104                         link->dc->res_pool->dp_clock_source;
 105         unsigned int i;
 106         /* If the current pixel clock source is not DTO(happens after
 107          * switching from HDMI passive dongle to DP on the same connector),
 108          * switch the pixel clock source to DTO.
 109          */
 110         for (i = 0; i < MAX_PIPES; i++) {
 111                 if (pipes[i].stream != NULL &&
 112                         pipes[i].stream->link == link) {
 113                         if (pipes[i].clock_source != NULL &&
 114                                         pipes[i].clock_source->id != CLOCK_SOURCE_ID_DP_DTO) {
 115                                 pipes[i].clock_source = dp_cs;
 116                                 pipes[i].stream_res.pix_clk_params.requested_pix_clk_100hz =
 117                                                 pipes[i].stream->timing.pix_clk_100hz;
 118                                 pipes[i].clock_source->funcs->program_pix_clk(
 119                                                         pipes[i].clock_source,
 120                                                         &pipes[i].stream_res.pix_clk_params,
 121                                                         &pipes[i].pll_settings);
 122                         }
 123                 }
 124         }
 125
 126         if (dmcu != NULL && dmcu->funcs->lock_phy)
 127                 dmcu->funcs->lock_phy(dmcu);
 128
 129         if (dc_is_dp_sst_signal(signal)) {
 130                 link_enc->funcs->enable_dp_output(
 131                                                 link_enc,
 132                                                 link_settings,
 133                                                 clock_source);
 134         } else {
 135                 link_enc->funcs->enable_dp_mst_output(
 136                                                 link_enc,
 137                                                 link_settings,
 138                                                 clock_source);
 139         }
 140
 141         if (dmcu != NULL && dmcu->funcs->unlock_phy)
 142                 dmcu->funcs->unlock_phy(dmcu);
 143
 144         link->cur_link_settings = *link_settings;
 145
 146         dp_receiver_power_ctrl(link, true);
 147 }
 148
 149 bool edp_receiver_ready_T9(struct dc_link *link)
 150 {
 151         unsigned int tries = 0;
 152         unsigned char sinkstatus = 0;
 153         unsigned char edpRev = 0;
 154         enum dc_status result = DC_OK;
 155         result = core_link_read_dpcd(link, DP_EDP_DPCD_REV, &edpRev, sizeof(edpRev));
 156         if (edpRev < DP_EDP_12)
 157                 return true;
 158         /* start from eDP version 1.2, SINK_STAUS indicate the sink is ready.*/
 159         do {
 160                 sinkstatus = 1;
 161                 result = core_link_read_dpcd(link, DP_SINK_STATUS, &sinkstatus, sizeof(sinkstatus));
 162                 if (sinkstatus == 0)
 163                         break;
 164                 if (result != DC_OK)
 165                         break;
 166                 udelay(100); //MAx T9
 167         } while (++tries < 50);
 168
 169         if (link->local_sink->edid_caps.panel_patch.extra_delay_backlight_off > 0)
 170                 udelay(link->local_sink->edid_caps.panel_patch.extra_delay_backlight_off * 1000);
 171
 172         return result;
 173 }
 174 bool edp_receiver_ready_T7(struct dc_link *link)
 175 {
 176         unsigned char sinkstatus = 0;
 177         unsigned char edpRev = 0;
 178         enum dc_status result = DC_OK;
 179
 180         /* use absolute time stamp to constrain max T7*/
 181         unsigned long long enter_timestamp = 0;
 182         unsigned long long finish_timestamp = 0;
 183         unsigned long long time_taken_in_ns = 0;
 184
 185         result = core_link_read_dpcd(link, DP_EDP_DPCD_REV, &edpRev, sizeof(edpRev));
 186         if (result == DC_OK && edpRev < DP_EDP_12)
 187                 return true;
 188         /* start from eDP version 1.2, SINK_STAUS indicate the sink is ready.*/
 189         enter_timestamp = dm_get_timestamp(link->ctx);
 190         do {
 191                 sinkstatus = 0;
 192                 result = core_link_read_dpcd(link, DP_SINK_STATUS, &sinkstatus, sizeof(sinkstatus));
 193                 if (sinkstatus == 1)
 194                         break;
 195                 if (result != DC_OK)
 196                         break;
 197                 udelay(25);
 198                 finish_timestamp = dm_get_timestamp(link->ctx);
 199                 time_taken_in_ns = dm_get_elapse_time_in_ns(link->ctx, finish_timestamp, enter_timestamp);
 200         } while (time_taken_in_ns < 50 * 1000000); //MAx T7 is 50ms
 201
 202         if (link->local_sink->edid_caps.panel_patch.extra_t7_ms > 0)
 203                 udelay(link->local_sink->edid_caps.panel_patch.extra_t7_ms * 1000);
 204
 205         return result;
 206 }
 207
 208 void dp_disable_link_phy(struct dc_link *link, enum signal_type signal)
 209 {
 210         struct dc  *dc = link->ctx->dc;
 211         struct dmcu *dmcu = dc->res_pool->dmcu;
 212
 213         if (!link->wa_flags.dp_keep_receiver_powered)
 214                 dp_receiver_power_ctrl(link, false);
 215
 216         if (signal == SIGNAL_TYPE_EDP) {
 217                 link->link_enc->funcs->disable_output(link->link_enc, signal);
 218                 link->dc->hwss.edp_power_control(link, false);
 219         } else {
 220                 if (dmcu != NULL && dmcu->funcs->lock_phy)
 221                         dmcu->funcs->lock_phy(dmcu);
 222
 223                 link->link_enc->funcs->disable_output(link->link_enc, signal);
 224
 225                 if (dmcu != NULL && dmcu->funcs->unlock_phy)
 226                         dmcu->funcs->unlock_phy(dmcu);
 227         }
 228
 229         /* Clear current link setting.*/
 230         memset(&link->cur_link_settings, 0,
 231                         sizeof(link->cur_link_settings));
 232 }
 233
 234 void dp_disable_link_phy_mst(struct dc_link *link, enum signal_type signal)
 235 {
 236         /* MST disable link only when no stream use the link */
 237         if (link->mst_stream_alloc_table.stream_count > 0)
 238                 return;
 239
 240         dp_disable_link_phy(link, signal);
 241
 242         /* set the sink to SST mode after disabling the link */
 243         dp_enable_mst_on_sink(link, false);
 244 }
 245
 246 bool dp_set_hw_training_pattern(
 247         struct dc_link *link,
 248         enum dc_dp_training_pattern pattern,
 249         uint32_t offset)
 250 {
 251         enum dp_test_pattern test_pattern = DP_TEST_PATTERN_UNSUPPORTED;
 252
 253         switch (pattern) {
 254         case DP_TRAINING_PATTERN_SEQUENCE_1:
 255                 test_pattern = DP_TEST_PATTERN_TRAINING_PATTERN1;
 256                 break;
 257         case DP_TRAINING_PATTERN_SEQUENCE_2:
 258                 test_pattern = DP_TEST_PATTERN_TRAINING_PATTERN2;
 259                 break;
 260         case DP_TRAINING_PATTERN_SEQUENCE_3:
 261                 test_pattern = DP_TEST_PATTERN_TRAINING_PATTERN3;
 262                 break;
 263         case DP_TRAINING_PATTERN_SEQUENCE_4:
 264                 test_pattern = DP_TEST_PATTERN_TRAINING_PATTERN4;
 265                 break;
 266         default:
 267                 break;
 268         }
 269
 270         dp_set_hw_test_pattern(link, test_pattern, NULL, 0);
 271
 272         return true;
 273 }
 274
 275 void dp_set_hw_lane_settings(
 276         struct dc_link *link,
 277         const struct link_training_settings *link_settings,
 278         uint32_t offset)
 279 {
 280         struct link_encoder *encoder = link->link_enc;
 281
 282         if (!link->is_lttpr_mode_transparent && !is_immediate_downstream(link, offset))
 283                 return;
 284
 285         /* call Encoder to set lane settings */
 286         encoder->funcs->dp_set_lane_settings(encoder, link_settings);
 287 }
 288
 289 void dp_set_hw_test_pattern(
 290         struct dc_link *link,
 291         enum dp_test_pattern test_pattern,
 292         uint8_t *custom_pattern,
 293         uint32_t custom_pattern_size)
 294 {
 295         struct encoder_set_dp_phy_pattern_param pattern_param = {0};
 296         struct link_encoder *encoder = link->link_enc;
 297
 298         pattern_param.dp_phy_pattern = test_pattern;
 299         pattern_param.custom_pattern = custom_pattern;
 300         pattern_param.custom_pattern_size = custom_pattern_size;
 301         pattern_param.dp_panel_mode = dp_get_panel_mode(link);
 302
 303         encoder->funcs->dp_set_phy_pattern(encoder, &pattern_param);
 304 }
 305
 306 void dp_retrain_link_dp_test(struct dc_link *link,
 307                         struct dc_link_settings *link_setting,
 308                         bool skip_video_pattern)
 309 {
 310         struct pipe_ctx *pipes =
 311                         &link->dc->current_state->res_ctx.pipe_ctx[0];
 312         unsigned int i;
 313
 314         for (i = 0; i < MAX_PIPES; i++) {
 315                 if (pipes[i].stream != NULL &&
 316                         !pipes[i].top_pipe && !pipes[i].prev_odm_pipe &&
 317                         pipes[i].stream->link != NULL &&
 318                         pipes[i].stream_res.stream_enc != NULL &&
 319                         pipes[i].stream->link == link) {
 320                         udelay(100);
 321
 322                         pipes[i].stream_res.stream_enc->funcs->dp_blank(
 323                                         pipes[i].stream_res.stream_enc);
 324
 325                         /* disable any test pattern that might be active */
 326                         dp_set_hw_test_pattern(link,
 327                                         DP_TEST_PATTERN_VIDEO_MODE, NULL, 0);
 328
 329                         dp_receiver_power_ctrl(link, false);
 330
 331                         link->dc->hwss.disable_stream(&pipes[i]);
 332                         if ((&pipes[i])->stream_res.audio && !link->dc->debug.az_endpoint_mute_only)
 333                                 (&pipes[i])->stream_res.audio->funcs->az_disable((&pipes[i])->stream_res.audio);
 334
 335                         link->link_enc->funcs->disable_output(
 336                                         link->link_enc,
 337                                         SIGNAL_TYPE_DISPLAY_PORT);
 338
 339                         /* Clear current link setting. */
 340                         memset(&link->cur_link_settings, 0,
 341                                 sizeof(link->cur_link_settings));
 342
 343                         perform_link_training_with_retries(
 344                                         link_setting,
 345                                         skip_video_pattern,
 346                                         LINK_TRAINING_ATTEMPTS,
 347                                         &pipes[i],
 348                                         SIGNAL_TYPE_DISPLAY_PORT);
 349
 350                         link->dc->hwss.enable_stream(&pipes[i]);
 351
 352                         link->dc->hwss.unblank_stream(&pipes[i],
 353                                         link_setting);
 354
 355                         if (pipes[i].stream_res.audio) {
 356                                 /* notify audio driver for
 357                                  * audio modes of monitor */
 358                                 pipes[i].stream_res.audio->funcs->az_enable(
 359                                                 pipes[i].stream_res.audio);
 360
 361                                 /* un-mute audio */
 362                                 /* TODO: audio should be per stream rather than
 363                                  * per link */
 364                                 pipes[i].stream_res.stream_enc->funcs->
 365                                 audio_mute_control(
 366                                         pipes[i].stream_res.stream_enc, false);
 367                         }
 368                 }
 369         }
 370 }
 371
 372 #define DC_LOGGER \
 373         dsc->ctx->logger
 374 static void dsc_optc_config_log(struct display_stream_compressor *dsc,
 375                 struct dsc_optc_config *config)
 376 {
 377         uint32_t precision = 1 << 28;
 378         uint32_t bytes_per_pixel_int = config->bytes_per_pixel / precision;
 379         uint32_t bytes_per_pixel_mod = config->bytes_per_pixel % precision;
 380         uint64_t ll_bytes_per_pix_fraq = bytes_per_pixel_mod;
 381
 382         /* 7 fractional digits decimal precision for bytes per pixel is enough because DSC
 383          * bits per pixel precision is 1/16th of a pixel, which means bytes per pixel precision is
 384          * 1/16/8 = 1/128 of a byte, or 0.0078125 decimal
 385          */
 386         ll_bytes_per_pix_fraq *= 10000000;
 387         ll_bytes_per_pix_fraq /= precision;
 388
 389         DC_LOG_DSC("\tbytes_per_pixel 0x%08x (%d.%07d)",
 390                         config->bytes_per_pixel, bytes_per_pixel_int, (uint32_t)ll_bytes_per_pix_fraq);
 391         DC_LOG_DSC("\tis_pixel_format_444 %d", config->is_pixel_format_444);
 392         DC_LOG_DSC("\tslice_width %d", config->slice_width);
 393 }
 394
 395 static bool dp_set_dsc_on_rx(struct pipe_ctx *pipe_ctx, bool enable)
 396 {
 397         struct dc *dc = pipe_ctx->stream->ctx->dc;
 398         struct dc_stream_state *stream = pipe_ctx->stream;
 399         bool result = false;
 400
 401         if (IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment))
 402                 result = true;
 403         else
 404                 result = dm_helpers_dp_write_dsc_enable(dc->ctx, stream, enable);
 405         return result;
 406 }
 407
 408 /* The stream with these settings can be sent (unblanked) only after DSC was enabled on RX first,
 409  * i.e. after dp_enable_dsc_on_rx() had been called
 410  */
 411 void dp_set_dsc_on_stream(struct pipe_ctx *pipe_ctx, bool enable)
 412 {
 413         struct display_stream_compressor *dsc = pipe_ctx->stream_res.dsc;
 414         struct dc *dc = pipe_ctx->stream->ctx->dc;
 415         struct dc_stream_state *stream = pipe_ctx->stream;
 416         struct pipe_ctx *odm_pipe;
 417         int opp_cnt = 1;
 418
 419         for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe)
 420                 opp_cnt++;
 421
 422         if (enable) {
 423                 struct dsc_config dsc_cfg;
 424                 struct dsc_optc_config dsc_optc_cfg;
 425                 enum optc_dsc_mode optc_dsc_mode;
 426
 427                 /* Enable DSC hw block */
 428                 dsc_cfg.pic_width = (stream->timing.h_addressable + stream->timing.h_border_left + stream->timing.h_border_right) / opp_cnt;
 429                 dsc_cfg.pic_height = stream->timing.v_addressable + stream->timing.v_border_top + stream->timing.v_border_bottom;
 430                 dsc_cfg.pixel_encoding = stream->timing.pixel_encoding;
 431                 dsc_cfg.color_depth = stream->timing.display_color_depth;
 432                 dsc_cfg.dc_dsc_cfg = stream->timing.dsc_cfg;
 433                 ASSERT(dsc_cfg.dc_dsc_cfg.num_slices_h % opp_cnt == 0);
 434                 dsc_cfg.dc_dsc_cfg.num_slices_h /= opp_cnt;
 435
 436                 dsc->funcs->dsc_set_config(dsc, &dsc_cfg, &dsc_optc_cfg);
 437                 dsc->funcs->dsc_enable(dsc, pipe_ctx->stream_res.opp->inst);
 438                 for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe) {
 439                         struct display_stream_compressor *odm_dsc = odm_pipe->stream_res.dsc;
 440
 441                         odm_dsc->funcs->dsc_set_config(odm_dsc, &dsc_cfg, &dsc_optc_cfg);
 442                         odm_dsc->funcs->dsc_enable(odm_dsc, odm_pipe->stream_res.opp->inst);
 443                 }
 444                 dsc_cfg.dc_dsc_cfg.num_slices_h *= opp_cnt;
 445                 dsc_cfg.pic_width *= opp_cnt;
 446
 447                 optc_dsc_mode = dsc_optc_cfg.is_pixel_format_444 ? OPTC_DSC_ENABLED_444 : OPTC_DSC_ENABLED_NATIVE_SUBSAMPLED;
 448
 449                 /* Enable DSC in encoder */
 450                 if (dc_is_dp_signal(stream->signal) && !IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) {
 451                         DC_LOG_DSC("Setting stream encoder DSC config for engine %d:", (int)pipe_ctx->stream_res.stream_enc->id);
 452                         dsc_optc_config_log(dsc, &dsc_optc_cfg);
 453                         pipe_ctx->stream_res.stream_enc->funcs->dp_set_dsc_config(pipe_ctx->stream_res.stream_enc,
 454                                                                         optc_dsc_mode,
 455                                                                         dsc_optc_cfg.bytes_per_pixel,
 456                                                                         dsc_optc_cfg.slice_width);
 457
 458                         /* PPS SDP is set elsewhere because it has to be done after DIG FE is connected to DIG BE */
 459                 }
 460
 461                 /* Enable DSC in OPTC */
 462                 DC_LOG_DSC("Setting optc DSC config for tg instance %d:", pipe_ctx->stream_res.tg->inst);
 463                 dsc_optc_config_log(dsc, &dsc_optc_cfg);
 464                 pipe_ctx->stream_res.tg->funcs->set_dsc_config(pipe_ctx->stream_res.tg,
 465                                                         optc_dsc_mode,
 466                                                         dsc_optc_cfg.bytes_per_pixel,
 467                                                         dsc_optc_cfg.slice_width);
 468         } else {
 469                 /* disable DSC in OPTC */
 470                 pipe_ctx->stream_res.tg->funcs->set_dsc_config(
 471                                 pipe_ctx->stream_res.tg,
 472                                 OPTC_DSC_DISABLED, 0, 0);
 473
 474                 /* disable DSC in stream encoder */
 475                 if (dc_is_dp_signal(stream->signal) && !IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) {
 476                         pipe_ctx->stream_res.stream_enc->funcs->dp_set_dsc_config(
 477                                         pipe_ctx->stream_res.stream_enc,
 478                                         OPTC_DSC_DISABLED, 0, 0);
 479
 480                         pipe_ctx->stream_res.stream_enc->funcs->dp_set_dsc_pps_info_packet(
 481                                         pipe_ctx->stream_res.stream_enc, false, NULL);
 482                 }
 483
 484                 /* disable DSC block */
 485                 pipe_ctx->stream_res.dsc->funcs->dsc_disable(pipe_ctx->stream_res.dsc);
 486                 for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe)
 487                         odm_pipe->stream_res.dsc->funcs->dsc_disable(odm_pipe->stream_res.dsc);
 488         }
 489 }
 490
 491 bool dp_set_dsc_enable(struct pipe_ctx *pipe_ctx, bool enable)
 492 {
 493         struct display_stream_compressor *dsc = pipe_ctx->stream_res.dsc;
 494         bool result = false;
 495
 496         if (!pipe_ctx->stream->timing.flags.DSC)
 497                 goto out;
 498         if (!dsc)
 499                 goto out;
 500
 501         if (enable) {
 502                 if (dp_set_dsc_on_rx(pipe_ctx, true)) {
 503                         dp_set_dsc_on_stream(pipe_ctx, true);
 504                         result = true;
 505                 }
 506         } else {
 507                 dp_set_dsc_on_rx(pipe_ctx, false);
 508                 dp_set_dsc_on_stream(pipe_ctx, false);
 509                 result = true;
 510         }
 511 out:
 512         return result;
 513 }
 514
 515 bool dp_set_dsc_pps_sdp(struct pipe_ctx *pipe_ctx, bool enable)
 516 {
 517         struct display_stream_compressor *dsc = pipe_ctx->stream_res.dsc;
 518         struct dc *dc = pipe_ctx->stream->ctx->dc;
 519         struct dc_stream_state *stream = pipe_ctx->stream;
 520
 521         if (!pipe_ctx->stream->timing.flags.DSC || !dsc)
 522                 return false;
 523
 524         if (enable) {
 525                 struct dsc_config dsc_cfg;
 526                 uint8_t dsc_packed_pps[128];
 527
 528                 /* Enable DSC hw block */
 529                 dsc_cfg.pic_width = stream->timing.h_addressable + stream->timing.h_border_left + stream->timing.h_border_right;
 530                 dsc_cfg.pic_height = stream->timing.v_addressable + stream->timing.v_border_top + stream->timing.v_border_bottom;
 531                 dsc_cfg.pixel_encoding = stream->timing.pixel_encoding;
 532                 dsc_cfg.color_depth = stream->timing.display_color_depth;
 533                 dsc_cfg.dc_dsc_cfg = stream->timing.dsc_cfg;
 534
 535                 DC_LOG_DSC(" ");
 536                 dsc->funcs->dsc_get_packed_pps(dsc, &dsc_cfg, &dsc_packed_pps[0]);
 537                 if (dc_is_dp_signal(stream->signal) && !IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) {
 538                         DC_LOG_DSC("Setting stream encoder DSC PPS SDP for engine %d\n", (int)pipe_ctx->stream_res.stream_enc->id);
 539                         pipe_ctx->stream_res.stream_enc->funcs->dp_set_dsc_pps_info_packet(
 540                                                                         pipe_ctx->stream_res.stream_enc,
 541                                                                         true,
 542                                                                         &dsc_packed_pps[0]);
 543                 }
 544         } else {
 545                 /* disable DSC PPS in stream encoder */
 546                 if (dc_is_dp_signal(stream->signal) && !IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) {
 547                         pipe_ctx->stream_res.stream_enc->funcs->dp_set_dsc_pps_info_packet(
 548                                                 pipe_ctx->stream_res.stream_enc, false, NULL);
 549                 }
 550         }
 551
 552         return true;
 553 }
 554
 555
 556 bool dp_update_dsc_config(struct pipe_ctx *pipe_ctx)
 557 {
 558         struct display_stream_compressor *dsc = pipe_ctx->stream_res.dsc;
 559
 560         if (!pipe_ctx->stream->timing.flags.DSC)
 561                 return false;
 562         if (!dsc)
 563                 return false;
 564
 565         dp_set_dsc_on_stream(pipe_ctx, true);
 566         dp_set_dsc_pps_sdp(pipe_ctx, true);
 567         return true;
 568 }
 569