2 * Copyright 2012-14 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
26 #ifndef DC_INTERFACE_H_
27 #define DC_INTERFACE_H_
30 #include "grph_object_defs.h"
31 #include "logger_types.h"
32 #include "gpio_types.h"
33 #include "link_service_types.h"
34 #include "grph_object_ctrl_defs.h"
35 #include <inc/hw/opp.h>
37 #include "inc/hw_sequencer.h"
38 #include "inc/compressor.h"
39 #include "dml/display_mode_lib.h"
41 #define DC_VER "3.1.29"
43 #define MAX_SURFACES 3
45 #define MAX_SINKS_PER_LINK 4
48 /*******************************************************************************
49 * Display Core Interfaces
50 ******************************************************************************/
55 uint32_t max_slave_planes;
57 uint32_t max_downscale_ratio;
58 uint32_t i2c_speed_in_khz;
59 unsigned int max_cursor_size;
60 unsigned int max_video_width;
61 int linear_pitch_alignment;
68 struct dc_dcc_surface_param {
69 struct dc_size surface_size;
70 enum surface_pixel_format format;
71 enum swizzle_mode_values swizzle_mode;
72 enum dc_scan_direction scan;
75 struct dc_dcc_setting {
76 unsigned int max_compressed_blk_size;
77 unsigned int max_uncompressed_blk_size;
78 bool independent_64b_blks;
81 struct dc_surface_dcc_cap {
84 struct dc_dcc_setting rgb;
88 struct dc_dcc_setting luma;
89 struct dc_dcc_setting chroma;
94 bool const_color_support;
97 struct dc_static_screen_events {
104 /* Surface update type is used by dc_update_surfaces_and_stream
105 * The update type is determined at the very beginning of the function based
106 * on parameters passed in and decides how much programming (or updating) is
107 * going to be done during the call.
109 * UPDATE_TYPE_FAST is used for really fast updates that do not require much
110 * logical calculations or hardware register programming. This update MUST be
111 * ISR safe on windows. Currently fast update will only be used to flip surface
114 * UPDATE_TYPE_MED is used for slower updates which require significant hw
115 * re-programming however do not affect bandwidth consumption or clock
116 * requirements. At present, this is the level at which front end updates
117 * that do not require us to run bw_calcs happen. These are in/out transfer func
118 * updates, viewport offset changes, recout size changes and pixel depth changes.
119 * This update can be done at ISR, but we want to minimize how often this happens.
121 * UPDATE_TYPE_FULL is slow. Really slow. This requires us to recalculate our
122 * bandwidth and clocks, possibly rearrange some pipes and reprogram anything front
123 * end related. Any time viewport dimensions, recout dimensions, scaling ratios or
124 * gamma need to be adjusted or pipe needs to be turned on (or disconnected) we do
125 * a full update. This cannot be done at ISR level and should be a rare event.
126 * Unless someone is stress testing mpo enter/exit, playing with colour or adjusting
127 * underscan we don't expect to see this call at all.
130 enum surface_update_type {
131 UPDATE_TYPE_FAST, /* super fast, safe to execute in isr */
132 UPDATE_TYPE_MED, /* ISR safe, most of programming needed, no bw/clk change*/
133 UPDATE_TYPE_FULL, /* may need to shuffle resources */
136 /* Forward declaration*/
138 struct dc_plane_state;
142 struct dc_cap_funcs {
143 bool (*get_dcc_compression_cap)(const struct dc *dc,
144 const struct dc_dcc_surface_param *input,
145 struct dc_surface_dcc_cap *output);
148 struct link_training_settings;
151 /* Structure to hold configuration flags set by dm at dc creation. */
154 bool disable_disp_pll_sharing;
160 DCC_HALF_REQ_DISALBE = 2,
163 enum pipe_split_policy {
164 MPC_SPLIT_DYNAMIC = 0,
166 MPC_SPLIT_AVOID_MULT_DISP = 2,
169 enum wm_report_mode {
170 WM_REPORT_DEFAULT = 0,
171 WM_REPORT_OVERRIDE = 1,
175 bool surface_visual_confirm;
181 bool validation_trace;
183 /* stutter efficiency related */
184 bool disable_stutter;
186 enum dcc_option disable_dcc;
187 enum pipe_split_policy pipe_split_policy;
188 bool force_single_disp_pipe_split;
189 bool voltage_align_fclk;
191 bool disable_dfs_bypass;
192 bool disable_dpp_power_gate;
193 bool disable_hubp_power_gate;
194 bool disable_pplib_wm_range;
195 enum wm_report_mode pplib_wm_report_mode;
196 unsigned int min_disp_clk_khz;
197 int sr_exit_time_dpm0_ns;
198 int sr_enter_plus_exit_time_dpm0_ns;
200 int sr_enter_plus_exit_time_ns;
201 int urgent_latency_ns;
202 int percent_of_ideal_drambw;
203 int dram_clock_change_latency_ns;
205 bool disable_pplib_clock_request;
206 bool disable_clock_gate;
209 bool force_abm_enable;
210 bool disable_hbup_pg;
212 bool disable_stereo_support;
214 bool performance_trace;
215 bool az_endpoint_mute_only;
216 bool always_use_regamma;
219 struct resource_pool;
223 struct dc_cap_funcs cap_funcs;
224 struct dc_config config;
225 struct dc_debug debug;
227 struct dc_context *ctx;
230 struct dc_link *links[MAX_PIPES * 2];
232 struct dc_state *current_state;
233 struct resource_pool *res_pool;
235 /* Display Engine Clock levels */
236 struct dm_pp_clock_levels sclk_lvls;
238 /* Inputs into BW and WM calculations. */
239 struct bw_calcs_dceip *bw_dceip;
240 struct bw_calcs_vbios *bw_vbios;
241 #ifdef CONFIG_DRM_AMD_DC_DCN1_0
242 struct dcn_soc_bounding_box *dcn_soc;
243 struct dcn_ip_params *dcn_ip;
244 struct display_mode_lib dml;
248 struct hw_sequencer_funcs hwss;
249 struct dce_hwseq *hwseq;
251 /* temp store of dm_pp_display_configuration
252 * to compare to see if display config changed
254 struct dm_pp_display_configuration prev_display_config;
256 bool optimized_required;
259 #if defined(CONFIG_DRM_AMD_DC_FBC)
260 struct compressor *fbc_compressor;
264 enum frame_buffer_mode {
265 FRAME_BUFFER_MODE_LOCAL_ONLY = 0,
266 FRAME_BUFFER_MODE_ZFB_ONLY,
267 FRAME_BUFFER_MODE_MIXED_ZFB_AND_LOCAL,
270 struct dchub_init_data {
271 int64_t zfb_phys_addr_base;
272 int64_t zfb_mc_base_addr;
273 uint64_t zfb_size_in_byte;
274 enum frame_buffer_mode fb_mode;
275 bool dchub_initialzied;
276 bool dchub_info_valid;
279 struct dc_init_data {
280 struct hw_asic_id asic_id;
281 void *driver; /* ctx */
282 struct cgs_device *cgs_device;
284 int num_virtual_links;
286 * If 'vbios_override' not NULL, it will be called instead
287 * of the real VBIOS. Intended use is Diagnostics on FPGA.
289 struct dc_bios *vbios_override;
290 enum dce_environment dce_environment;
292 struct dc_config flags;
296 struct dc *dc_create(const struct dc_init_data *init_params);
298 void dc_destroy(struct dc **dc);
300 /*******************************************************************************
302 ******************************************************************************/
305 TRANSFER_FUNC_POINTS = 1025
308 // Moved here from color module for linux
309 enum color_transfer_func {
310 transfer_func_unknown,
313 transfer_func_pq2084,
314 transfer_func_pq2084_interim,
315 transfer_func_linear_0_1,
316 transfer_func_linear_0_125,
317 transfer_func_dolbyvision,
318 transfer_func_gamma_22,
319 transfer_func_gamma_26
322 struct dc_hdr_static_metadata {
323 /* display chromaticities and white point in units of 0.00001 */
324 unsigned int chromaticity_green_x;
325 unsigned int chromaticity_green_y;
326 unsigned int chromaticity_blue_x;
327 unsigned int chromaticity_blue_y;
328 unsigned int chromaticity_red_x;
329 unsigned int chromaticity_red_y;
330 unsigned int chromaticity_white_point_x;
331 unsigned int chromaticity_white_point_y;
333 uint32_t min_luminance;
334 uint32_t max_luminance;
335 uint32_t maximum_content_light_level;
336 uint32_t maximum_frame_average_light_level;
342 enum dc_transfer_func_type {
344 TF_TYPE_DISTRIBUTED_POINTS,
348 struct dc_transfer_func_distributed_points {
349 struct fixed31_32 red[TRANSFER_FUNC_POINTS];
350 struct fixed31_32 green[TRANSFER_FUNC_POINTS];
351 struct fixed31_32 blue[TRANSFER_FUNC_POINTS];
353 uint16_t end_exponent;
354 uint16_t x_point_at_y1_red;
355 uint16_t x_point_at_y1_green;
356 uint16_t x_point_at_y1_blue;
359 enum dc_transfer_func_predefined {
360 TRANSFER_FUNCTION_SRGB,
361 TRANSFER_FUNCTION_BT709,
362 TRANSFER_FUNCTION_PQ,
363 TRANSFER_FUNCTION_LINEAR,
364 TRANSFER_FUNCTION_UNITY,
367 struct dc_transfer_func {
368 struct kref refcount;
369 struct dc_transfer_func_distributed_points tf_pts;
370 enum dc_transfer_func_type type;
371 enum dc_transfer_func_predefined tf;
372 /* FP16 1.0 reference level in nits, default is 80 nits, only for PQ*/
373 uint32_t sdr_ref_white_level;
374 struct dc_context *ctx;
378 * This structure is filled in by dc_surface_get_status and contains
379 * the last requested address and the currently active address so the called
380 * can determine if there are any outstanding flips
382 struct dc_plane_status {
383 struct dc_plane_address requested_address;
384 struct dc_plane_address current_address;
385 bool is_flip_pending;
389 union surface_update_flags {
393 uint32_t dcc_change:1;
394 uint32_t color_space_change:1;
395 uint32_t input_tf_change:1;
396 uint32_t horizontal_mirror_change:1;
397 uint32_t per_pixel_alpha_change:1;
398 uint32_t rotation_change:1;
399 uint32_t swizzle_change:1;
400 uint32_t scaling_change:1;
401 uint32_t position_change:1;
402 uint32_t in_transfer_func_change:1;
403 uint32_t input_csc_change:1;
404 uint32_t output_tf_change:1;
405 uint32_t pixel_format_change:1;
408 uint32_t new_plane:1;
409 uint32_t bpp_change:1;
410 uint32_t gamma_change:1;
411 uint32_t bandwidth_change:1;
412 uint32_t clock_change:1;
413 uint32_t stereo_format_change:1;
414 uint32_t full_update:1;
420 struct dc_plane_state {
421 struct dc_plane_address address;
422 struct scaling_taps scaling_quality;
423 struct rect src_rect;
424 struct rect dst_rect;
425 struct rect clip_rect;
427 union plane_size plane_size;
428 union dc_tiling_info tiling_info;
430 struct dc_plane_dcc_param dcc;
432 struct dc_gamma *gamma_correction;
433 struct dc_transfer_func *in_transfer_func;
434 struct dc_bias_and_scale *bias_and_scale;
435 struct csc_transform input_csc_color_matrix;
436 struct fixed31_32 coeff_reduction_factor;
437 uint32_t sdr_white_level;
439 // TODO: No longer used, remove
440 struct dc_hdr_static_metadata hdr_static_ctx;
442 enum dc_color_space color_space;
443 enum color_transfer_func input_tf;
445 enum surface_pixel_format format;
446 enum dc_rotation_angle rotation;
447 enum plane_stereo_format stereo_format;
449 bool is_tiling_rotated;
450 bool per_pixel_alpha;
453 bool horizontal_mirror;
455 union surface_update_flags update_flags;
456 /* private to DC core */
457 struct dc_plane_status status;
458 struct dc_context *ctx;
460 /* private to dc_surface.c */
461 enum dc_irq_source irq_source;
462 struct kref refcount;
465 struct dc_plane_info {
466 union plane_size plane_size;
467 union dc_tiling_info tiling_info;
468 struct dc_plane_dcc_param dcc;
469 enum surface_pixel_format format;
470 enum dc_rotation_angle rotation;
471 enum plane_stereo_format stereo_format;
472 enum dc_color_space color_space;
473 enum color_transfer_func input_tf;
474 unsigned int sdr_white_level;
475 bool horizontal_mirror;
477 bool per_pixel_alpha;
478 bool input_csc_enabled;
481 struct dc_scaling_info {
482 struct rect src_rect;
483 struct rect dst_rect;
484 struct rect clip_rect;
485 struct scaling_taps scaling_quality;
488 struct dc_surface_update {
489 struct dc_plane_state *surface;
491 /* isr safe update parameters. null means no updates */
492 struct dc_flip_addrs *flip_addr;
493 struct dc_plane_info *plane_info;
494 struct dc_scaling_info *scaling_info;
496 /* following updates require alloc/sleep/spin that is not isr safe,
497 * null means no updates
499 struct dc_gamma *gamma;
500 enum color_transfer_func color_input_tf;
501 struct dc_transfer_func *in_transfer_func;
503 struct csc_transform *input_csc_color_matrix;
504 struct fixed31_32 *coeff_reduction_factor;
508 * Create a new surface with default parameters;
510 struct dc_plane_state *dc_create_plane_state(struct dc *dc);
511 const struct dc_plane_status *dc_plane_get_status(
512 const struct dc_plane_state *plane_state);
514 void dc_plane_state_retain(struct dc_plane_state *plane_state);
515 void dc_plane_state_release(struct dc_plane_state *plane_state);
517 void dc_gamma_retain(struct dc_gamma *dc_gamma);
518 void dc_gamma_release(struct dc_gamma **dc_gamma);
519 struct dc_gamma *dc_create_gamma(void);
521 void dc_transfer_func_retain(struct dc_transfer_func *dc_tf);
522 void dc_transfer_func_release(struct dc_transfer_func *dc_tf);
523 struct dc_transfer_func *dc_create_transfer_func(void);
526 * This structure holds a surface address. There could be multiple addresses
527 * in cases such as Stereo 3D, Planar YUV, etc. Other per-flip attributes such
528 * as frame durations and DCC format can also be set.
530 struct dc_flip_addrs {
531 struct dc_plane_address address;
533 /* TODO: add flip duration for FreeSync */
536 bool dc_post_update_surfaces_to_stream(
539 #include "dc_stream.h"
542 * Structure to store surface/stream associations for validation
544 struct dc_validation_set {
545 struct dc_stream_state *stream;
546 struct dc_plane_state *plane_states[MAX_SURFACES];
550 enum dc_status dc_validate_plane(struct dc *dc, const struct dc_plane_state *plane_state);
552 enum dc_status dc_validate_global_state(
554 struct dc_state *new_ctx);
557 void dc_resource_state_construct(
559 struct dc_state *dst_ctx);
561 void dc_resource_state_copy_construct(
562 const struct dc_state *src_ctx,
563 struct dc_state *dst_ctx);
565 void dc_resource_state_copy_construct_current(
567 struct dc_state *dst_ctx);
569 void dc_resource_state_destruct(struct dc_state *context);
572 * TODO update to make it about validation sets
573 * Set up streams and links associated to drive sinks
574 * The streams parameter is an absolute set of all active streams.
577 * Phy, Encoder, Timing Generator are programmed and enabled.
578 * New streams are enabled with blank stream; no memory read.
580 bool dc_commit_state(struct dc *dc, struct dc_state *context);
583 struct dc_state *dc_create_state(void);
584 void dc_retain_state(struct dc_state *context);
585 void dc_release_state(struct dc_state *context);
587 /*******************************************************************************
589 ******************************************************************************/
592 union dpcd_rev dpcd_rev;
593 union max_lane_count max_ln_count;
594 union max_down_spread max_down_spread;
596 /* dongle type (DP converter, CV smart dongle) */
597 enum display_dongle_type dongle_type;
598 /* Dongle's downstream count. */
599 union sink_count sink_count;
600 /* If dongle_type == DISPLAY_DONGLE_DP_HDMI_CONVERTER,
601 indicates 'Frame Sequential-to-lllFrame Pack' conversion capability.*/
602 struct dc_dongle_caps dongle_caps;
604 uint32_t sink_dev_id;
605 uint32_t branch_dev_id;
606 int8_t branch_dev_name[6];
607 int8_t branch_hw_revision;
609 bool allow_invalid_MSA_timing_param;
611 bool dpcd_display_control_capable;
616 /*******************************************************************************
617 * Sink Interfaces - A sink corresponds to a display output device
618 ******************************************************************************/
620 struct dc_container_id {
621 // 128bit GUID in binary form
622 unsigned char guid[16];
623 // 8 byte port ID -> ELD.PortID
624 unsigned int portId[2];
625 // 128bit GUID in binary formufacturer name -> ELD.ManufacturerName
626 unsigned short manufacturerName;
627 // 2 byte product code -> ELD.ProductCode
628 unsigned short productCode;
634 * The sink structure contains EDID and other display device properties
637 enum signal_type sink_signal;
638 struct dc_edid dc_edid; /* raw edid */
639 struct dc_edid_caps edid_caps; /* parse display caps */
640 struct dc_container_id *dc_container_id;
641 uint32_t dongle_max_pix_clk;
643 struct stereo_3d_features features_3d[TIMING_3D_FORMAT_MAX];
644 bool converter_disable_audio;
646 /* private to DC core */
647 struct dc_link *link;
648 struct dc_context *ctx;
650 /* private to dc_sink.c */
651 struct kref refcount;
655 void dc_sink_retain(struct dc_sink *sink);
656 void dc_sink_release(struct dc_sink *sink);
658 struct dc_sink_init_data {
659 enum signal_type sink_signal;
660 struct dc_link *link;
661 uint32_t dongle_max_pix_clk;
662 bool converter_disable_audio;
665 struct dc_sink *dc_sink_create(const struct dc_sink_init_data *init_params);
667 /* Newer interfaces */
669 struct dc_plane_address address;
670 struct dc_cursor_attributes attributes;
673 /*******************************************************************************
674 * Interrupt interfaces
675 ******************************************************************************/
676 enum dc_irq_source dc_interrupt_to_irq_source(
680 void dc_interrupt_set(struct dc *dc, enum dc_irq_source src, bool enable);
681 void dc_interrupt_ack(struct dc *dc, enum dc_irq_source src);
682 enum dc_irq_source dc_get_hpd_irq_source_at_index(
683 struct dc *dc, uint32_t link_index);
685 /*******************************************************************************
687 ******************************************************************************/
689 void dc_set_power_state(
691 enum dc_acpi_cm_power_state power_state);
692 void dc_resume(struct dc *dc);
694 #endif /* DC_INTERFACE_H_ */