2 * Copyright 2012-14 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
26 #ifndef DC_INTERFACE_H_
27 #define DC_INTERFACE_H_
30 #include "grph_object_defs.h"
31 #include "logger_types.h"
32 #include "gpio_types.h"
33 #include "link_service_types.h"
34 #include "grph_object_ctrl_defs.h"
35 #include <inc/hw/opp.h>
37 #include "inc/hw_sequencer.h"
38 #include "inc/compressor.h"
39 #include "inc/hw/dmcu.h"
40 #include "dml/display_mode_lib.h"
42 #define DC_VER "3.2.23"
44 #define MAX_SURFACES 3
47 #define MAX_SINKS_PER_LINK 4
49 /*******************************************************************************
50 * Display Core Interfaces
51 ******************************************************************************/
54 struct dmcu_version dmcu_version;
58 DC_PLANE_TYPE_INVALID,
59 DC_PLANE_TYPE_DCE_RGB,
60 DC_PLANE_TYPE_DCE_UNDERLAY,
61 DC_PLANE_TYPE_DCN_UNIVERSAL,
65 enum dc_plane_type type;
66 uint32_t blends_with_above : 1;
67 uint32_t blends_with_below : 1;
68 uint32_t per_pixel_alpha : 1;
69 uint32_t supports_argb8888 : 1;
70 uint32_t supports_nv12 : 1;
77 uint32_t max_slave_planes;
79 uint32_t max_downscale_ratio;
80 uint32_t i2c_speed_in_khz;
81 uint32_t dmdata_alloc_size;
82 unsigned int max_cursor_size;
83 unsigned int max_video_width;
84 int linear_pitch_alignment;
89 bool post_blend_color_processing;
90 bool force_dp_tps4_for_cp2520;
91 bool disable_dp_clk_share;
92 bool psp_setup_panel_mode;
93 struct dc_plane_cap planes[MAX_PLANES];
96 struct dc_dcc_surface_param {
97 struct dc_size surface_size;
98 enum surface_pixel_format format;
99 enum swizzle_mode_values swizzle_mode;
100 enum dc_scan_direction scan;
103 struct dc_dcc_setting {
104 unsigned int max_compressed_blk_size;
105 unsigned int max_uncompressed_blk_size;
106 bool independent_64b_blks;
109 struct dc_surface_dcc_cap {
112 struct dc_dcc_setting rgb;
116 struct dc_dcc_setting luma;
117 struct dc_dcc_setting chroma;
122 bool const_color_support;
125 struct dc_static_screen_events {
133 /* Surface update type is used by dc_update_surfaces_and_stream
134 * The update type is determined at the very beginning of the function based
135 * on parameters passed in and decides how much programming (or updating) is
136 * going to be done during the call.
138 * UPDATE_TYPE_FAST is used for really fast updates that do not require much
139 * logical calculations or hardware register programming. This update MUST be
140 * ISR safe on windows. Currently fast update will only be used to flip surface
143 * UPDATE_TYPE_MED is used for slower updates which require significant hw
144 * re-programming however do not affect bandwidth consumption or clock
145 * requirements. At present, this is the level at which front end updates
146 * that do not require us to run bw_calcs happen. These are in/out transfer func
147 * updates, viewport offset changes, recout size changes and pixel depth changes.
148 * This update can be done at ISR, but we want to minimize how often this happens.
150 * UPDATE_TYPE_FULL is slow. Really slow. This requires us to recalculate our
151 * bandwidth and clocks, possibly rearrange some pipes and reprogram anything front
152 * end related. Any time viewport dimensions, recout dimensions, scaling ratios or
153 * gamma need to be adjusted or pipe needs to be turned on (or disconnected) we do
154 * a full update. This cannot be done at ISR level and should be a rare event.
155 * Unless someone is stress testing mpo enter/exit, playing with colour or adjusting
156 * underscan we don't expect to see this call at all.
159 enum surface_update_type {
160 UPDATE_TYPE_FAST, /* super fast, safe to execute in isr */
161 UPDATE_TYPE_MED, /* ISR safe, most of programming needed, no bw/clk change*/
162 UPDATE_TYPE_FULL, /* may need to shuffle resources */
165 /* Forward declaration*/
167 struct dc_plane_state;
171 struct dc_cap_funcs {
172 bool (*get_dcc_compression_cap)(const struct dc *dc,
173 const struct dc_dcc_surface_param *input,
174 struct dc_surface_dcc_cap *output);
177 struct link_training_settings;
180 /* Structure to hold configuration flags set by dm at dc creation. */
183 bool disable_disp_pll_sharing;
185 bool optimize_edp_link_rate;
186 bool allow_seamless_boot_optimization;
189 enum visual_confirm {
190 VISUAL_CONFIRM_DISABLE = 0,
191 VISUAL_CONFIRM_SURFACE = 1,
192 VISUAL_CONFIRM_HDR = 2,
198 DCC_HALF_REQ_DISALBE = 2,
201 enum pipe_split_policy {
202 MPC_SPLIT_DYNAMIC = 0,
204 MPC_SPLIT_AVOID_MULT_DISP = 2,
207 enum wm_report_mode {
208 WM_REPORT_DEFAULT = 0,
209 WM_REPORT_OVERRIDE = 1,
213 * For any clocks that may differ per pipe
214 * only the max is stored in this structure
218 int max_supported_dppclk_khz;
222 int dcfclk_deep_sleep_khz;
226 bool p_state_change_support;
229 struct dc_debug_options {
230 enum visual_confirm visual_confirm;
236 bool validation_trace;
237 bool bandwidth_calcs_trace;
238 int max_downscale_src_width;
240 /* stutter efficiency related */
241 bool disable_stutter;
243 enum dcc_option disable_dcc;
244 enum pipe_split_policy pipe_split_policy;
245 bool force_single_disp_pipe_split;
246 bool voltage_align_fclk;
248 bool disable_dfs_bypass;
249 bool disable_dpp_power_gate;
250 bool disable_hubp_power_gate;
251 bool disable_pplib_wm_range;
252 enum wm_report_mode pplib_wm_report_mode;
253 unsigned int min_disp_clk_khz;
254 int sr_exit_time_dpm0_ns;
255 int sr_enter_plus_exit_time_dpm0_ns;
257 int sr_enter_plus_exit_time_ns;
258 int urgent_latency_ns;
259 int percent_of_ideal_drambw;
260 int dram_clock_change_latency_ns;
261 bool optimized_watermark;
263 bool disable_pplib_clock_request;
264 bool disable_clock_gate;
267 bool force_abm_enable;
268 bool disable_stereo_support;
270 bool performance_trace;
271 bool az_endpoint_mute_only;
272 bool always_use_regamma;
273 bool p010_mpo_support;
274 bool recovery_enabled;
275 bool avoid_vbios_exec_table;
276 bool scl_reset_length10;
278 bool skip_detection_link_training;
279 unsigned int force_odm_combine; //bit vector based on otg inst
280 unsigned int force_fclk_khz;
281 bool disable_tri_buf;
284 struct dc_debug_data {
285 uint32_t ltFailCount;
286 uint32_t i2cErrorCount;
287 uint32_t auxErrorCount;
290 struct dc_bounding_box_overrides {
292 int sr_enter_plus_exit_time_ns;
293 int urgent_latency_ns;
294 int percent_of_ideal_drambw;
295 int dram_clock_change_latency_ns;
299 struct resource_pool;
302 struct dc_versions versions;
304 struct dc_cap_funcs cap_funcs;
305 struct dc_config config;
306 struct dc_debug_options debug;
307 struct dc_bounding_box_overrides bb_overrides;
308 struct dc_context *ctx;
311 struct dc_link *links[MAX_PIPES * 2];
313 struct dc_state *current_state;
314 struct resource_pool *res_pool;
316 /* Display Engine Clock levels */
317 struct dm_pp_clock_levels sclk_lvls;
319 /* Inputs into BW and WM calculations. */
320 struct bw_calcs_dceip *bw_dceip;
321 struct bw_calcs_vbios *bw_vbios;
322 #ifdef CONFIG_DRM_AMD_DC_DCN1_0
323 struct dcn_soc_bounding_box *dcn_soc;
324 struct dcn_ip_params *dcn_ip;
325 struct display_mode_lib dml;
329 struct hw_sequencer_funcs hwss;
330 struct dce_hwseq *hwseq;
332 /* Require to optimize clocks and bandwidth for added/removed planes */
333 bool optimized_required;
335 /* Require to maintain clocks and bandwidth for UEFI enabled HW */
336 bool optimize_seamless_boot;
339 struct compressor *fbc_compressor;
341 struct dc_debug_data debug_data;
343 const char *build_id;
346 enum frame_buffer_mode {
347 FRAME_BUFFER_MODE_LOCAL_ONLY = 0,
348 FRAME_BUFFER_MODE_ZFB_ONLY,
349 FRAME_BUFFER_MODE_MIXED_ZFB_AND_LOCAL,
352 struct dchub_init_data {
353 int64_t zfb_phys_addr_base;
354 int64_t zfb_mc_base_addr;
355 uint64_t zfb_size_in_byte;
356 enum frame_buffer_mode fb_mode;
357 bool dchub_initialzied;
358 bool dchub_info_valid;
361 struct dc_init_data {
362 struct hw_asic_id asic_id;
363 void *driver; /* ctx */
364 struct cgs_device *cgs_device;
365 struct dc_bounding_box_overrides bb_overrides;
367 int num_virtual_links;
369 * If 'vbios_override' not NULL, it will be called instead
370 * of the real VBIOS. Intended use is Diagnostics on FPGA.
372 struct dc_bios *vbios_override;
373 enum dce_environment dce_environment;
375 struct dc_config flags;
379 struct dc_callback_init {
383 struct dc *dc_create(const struct dc_init_data *init_params);
384 void dc_init_callbacks(struct dc *dc,
385 const struct dc_callback_init *init_params);
386 void dc_destroy(struct dc **dc);
388 /*******************************************************************************
390 ******************************************************************************/
393 TRANSFER_FUNC_POINTS = 1025
396 struct dc_hdr_static_metadata {
397 /* display chromaticities and white point in units of 0.00001 */
398 unsigned int chromaticity_green_x;
399 unsigned int chromaticity_green_y;
400 unsigned int chromaticity_blue_x;
401 unsigned int chromaticity_blue_y;
402 unsigned int chromaticity_red_x;
403 unsigned int chromaticity_red_y;
404 unsigned int chromaticity_white_point_x;
405 unsigned int chromaticity_white_point_y;
407 uint32_t min_luminance;
408 uint32_t max_luminance;
409 uint32_t maximum_content_light_level;
410 uint32_t maximum_frame_average_light_level;
413 enum dc_transfer_func_type {
415 TF_TYPE_DISTRIBUTED_POINTS,
420 struct dc_transfer_func_distributed_points {
421 struct fixed31_32 red[TRANSFER_FUNC_POINTS];
422 struct fixed31_32 green[TRANSFER_FUNC_POINTS];
423 struct fixed31_32 blue[TRANSFER_FUNC_POINTS];
425 uint16_t end_exponent;
426 uint16_t x_point_at_y1_red;
427 uint16_t x_point_at_y1_green;
428 uint16_t x_point_at_y1_blue;
431 enum dc_transfer_func_predefined {
432 TRANSFER_FUNCTION_SRGB,
433 TRANSFER_FUNCTION_BT709,
434 TRANSFER_FUNCTION_PQ,
435 TRANSFER_FUNCTION_LINEAR,
436 TRANSFER_FUNCTION_UNITY,
437 TRANSFER_FUNCTION_HLG,
438 TRANSFER_FUNCTION_HLG12,
439 TRANSFER_FUNCTION_GAMMA22
442 struct dc_transfer_func {
443 struct kref refcount;
444 enum dc_transfer_func_type type;
445 enum dc_transfer_func_predefined tf;
446 /* FP16 1.0 reference level in nits, default is 80 nits, only for PQ*/
447 uint32_t sdr_ref_white_level;
448 struct dc_context *ctx;
450 struct pwl_params pwl;
451 struct dc_transfer_func_distributed_points tf_pts;
456 * This structure is filled in by dc_surface_get_status and contains
457 * the last requested address and the currently active address so the called
458 * can determine if there are any outstanding flips
460 struct dc_plane_status {
461 struct dc_plane_address requested_address;
462 struct dc_plane_address current_address;
463 bool is_flip_pending;
467 union surface_update_flags {
471 uint32_t dcc_change:1;
472 uint32_t color_space_change:1;
473 uint32_t horizontal_mirror_change:1;
474 uint32_t per_pixel_alpha_change:1;
475 uint32_t global_alpha_change:1;
476 uint32_t rotation_change:1;
477 uint32_t swizzle_change:1;
478 uint32_t scaling_change:1;
479 uint32_t position_change:1;
480 uint32_t in_transfer_func_change:1;
481 uint32_t input_csc_change:1;
482 uint32_t coeff_reduction_change:1;
483 uint32_t output_tf_change:1;
484 uint32_t pixel_format_change:1;
485 uint32_t plane_size_change:1;
488 uint32_t new_plane:1;
489 uint32_t bpp_change:1;
490 uint32_t gamma_change:1;
491 uint32_t bandwidth_change:1;
492 uint32_t clock_change:1;
493 uint32_t stereo_format_change:1;
494 uint32_t full_update:1;
500 struct dc_plane_state {
501 struct dc_plane_address address;
502 struct dc_plane_flip_time time;
503 struct scaling_taps scaling_quality;
504 struct rect src_rect;
505 struct rect dst_rect;
506 struct rect clip_rect;
508 union plane_size plane_size;
509 union dc_tiling_info tiling_info;
511 struct dc_plane_dcc_param dcc;
513 struct dc_gamma *gamma_correction;
514 struct dc_transfer_func *in_transfer_func;
515 struct dc_bias_and_scale *bias_and_scale;
516 struct dc_csc_transform input_csc_color_matrix;
517 struct fixed31_32 coeff_reduction_factor;
518 uint32_t sdr_white_level;
520 // TODO: No longer used, remove
521 struct dc_hdr_static_metadata hdr_static_ctx;
523 enum dc_color_space color_space;
525 enum surface_pixel_format format;
526 enum dc_rotation_angle rotation;
527 enum plane_stereo_format stereo_format;
529 bool is_tiling_rotated;
530 bool per_pixel_alpha;
532 int global_alpha_value;
535 bool horizontal_mirror;
537 union surface_update_flags update_flags;
538 /* private to DC core */
539 struct dc_plane_status status;
540 struct dc_context *ctx;
542 /* private to dc_surface.c */
543 enum dc_irq_source irq_source;
544 struct kref refcount;
547 struct dc_plane_info {
548 union plane_size plane_size;
549 union dc_tiling_info tiling_info;
550 struct dc_plane_dcc_param dcc;
551 enum surface_pixel_format format;
552 enum dc_rotation_angle rotation;
553 enum plane_stereo_format stereo_format;
554 enum dc_color_space color_space;
555 unsigned int sdr_white_level;
556 bool horizontal_mirror;
558 bool per_pixel_alpha;
560 int global_alpha_value;
561 bool input_csc_enabled;
564 struct dc_scaling_info {
565 struct rect src_rect;
566 struct rect dst_rect;
567 struct rect clip_rect;
568 struct scaling_taps scaling_quality;
571 struct dc_surface_update {
572 struct dc_plane_state *surface;
574 /* isr safe update parameters. null means no updates */
575 const struct dc_flip_addrs *flip_addr;
576 const struct dc_plane_info *plane_info;
577 const struct dc_scaling_info *scaling_info;
579 /* following updates require alloc/sleep/spin that is not isr safe,
580 * null means no updates
582 const struct dc_gamma *gamma;
583 const struct dc_transfer_func *in_transfer_func;
585 const struct dc_csc_transform *input_csc_color_matrix;
586 const struct fixed31_32 *coeff_reduction_factor;
590 * Create a new surface with default parameters;
592 struct dc_plane_state *dc_create_plane_state(struct dc *dc);
593 const struct dc_plane_status *dc_plane_get_status(
594 const struct dc_plane_state *plane_state);
596 void dc_plane_state_retain(struct dc_plane_state *plane_state);
597 void dc_plane_state_release(struct dc_plane_state *plane_state);
599 void dc_gamma_retain(struct dc_gamma *dc_gamma);
600 void dc_gamma_release(struct dc_gamma **dc_gamma);
601 struct dc_gamma *dc_create_gamma(void);
603 void dc_transfer_func_retain(struct dc_transfer_func *dc_tf);
604 void dc_transfer_func_release(struct dc_transfer_func *dc_tf);
605 struct dc_transfer_func *dc_create_transfer_func(void);
608 * This structure holds a surface address. There could be multiple addresses
609 * in cases such as Stereo 3D, Planar YUV, etc. Other per-flip attributes such
610 * as frame durations and DCC format can also be set.
612 struct dc_flip_addrs {
613 struct dc_plane_address address;
614 unsigned int flip_timestamp_in_us;
616 /* TODO: add flip duration for FreeSync */
619 bool dc_post_update_surfaces_to_stream(
622 #include "dc_stream.h"
625 * Structure to store surface/stream associations for validation
627 struct dc_validation_set {
628 struct dc_stream_state *stream;
629 struct dc_plane_state *plane_states[MAX_SURFACES];
633 bool dc_validate_seamless_boot_timing(const struct dc *dc,
634 const struct dc_sink *sink,
635 struct dc_crtc_timing *crtc_timing);
637 enum dc_status dc_validate_plane(struct dc *dc, const struct dc_plane_state *plane_state);
639 void get_clock_requirements_for_state(struct dc_state *state, struct AsicStateEx *info);
641 enum dc_status dc_validate_global_state(
643 struct dc_state *new_ctx);
646 void dc_resource_state_construct(
648 struct dc_state *dst_ctx);
650 void dc_resource_state_copy_construct(
651 const struct dc_state *src_ctx,
652 struct dc_state *dst_ctx);
654 void dc_resource_state_copy_construct_current(
656 struct dc_state *dst_ctx);
658 void dc_resource_state_destruct(struct dc_state *context);
661 * TODO update to make it about validation sets
662 * Set up streams and links associated to drive sinks
663 * The streams parameter is an absolute set of all active streams.
666 * Phy, Encoder, Timing Generator are programmed and enabled.
667 * New streams are enabled with blank stream; no memory read.
669 bool dc_commit_state(struct dc *dc, struct dc_state *context);
672 struct dc_state *dc_create_state(void);
673 void dc_retain_state(struct dc_state *context);
674 void dc_release_state(struct dc_state *context);
676 /*******************************************************************************
678 ******************************************************************************/
681 union dpcd_rev dpcd_rev;
682 union max_lane_count max_ln_count;
683 union max_down_spread max_down_spread;
684 union dprx_feature dprx_feature;
686 /* valid only for eDP v1.4 or higher*/
687 uint8_t edp_supported_link_rates_count;
688 enum dc_link_rate edp_supported_link_rates[8];
690 /* dongle type (DP converter, CV smart dongle) */
691 enum display_dongle_type dongle_type;
692 /* branch device or sink device */
694 /* Dongle's downstream count. */
695 union sink_count sink_count;
696 /* If dongle_type == DISPLAY_DONGLE_DP_HDMI_CONVERTER,
697 indicates 'Frame Sequential-to-lllFrame Pack' conversion capability.*/
698 struct dc_dongle_caps dongle_caps;
700 uint32_t sink_dev_id;
701 int8_t sink_dev_id_str[6];
702 int8_t sink_hw_revision;
703 int8_t sink_fw_revision[2];
705 uint32_t branch_dev_id;
706 int8_t branch_dev_name[6];
707 int8_t branch_hw_revision;
708 int8_t branch_fw_revision[2];
710 bool allow_invalid_MSA_timing_param;
712 bool dpcd_display_control_capable;
713 bool ext_receiver_cap_field_present;
718 /*******************************************************************************
719 * Sink Interfaces - A sink corresponds to a display output device
720 ******************************************************************************/
722 struct dc_container_id {
723 // 128bit GUID in binary form
724 unsigned char guid[16];
725 // 8 byte port ID -> ELD.PortID
726 unsigned int portId[2];
727 // 128bit GUID in binary formufacturer name -> ELD.ManufacturerName
728 unsigned short manufacturerName;
729 // 2 byte product code -> ELD.ProductCode
730 unsigned short productCode;
736 * The sink structure contains EDID and other display device properties
739 enum signal_type sink_signal;
740 struct dc_edid dc_edid; /* raw edid */
741 struct dc_edid_caps edid_caps; /* parse display caps */
742 struct dc_container_id *dc_container_id;
743 uint32_t dongle_max_pix_clk;
745 struct stereo_3d_features features_3d[TIMING_3D_FORMAT_MAX];
746 bool converter_disable_audio;
748 /* private to DC core */
749 struct dc_link *link;
750 struct dc_context *ctx;
754 /* private to dc_sink.c */
755 // refcount must be the last member in dc_sink, since we want the
756 // sink structure to be logically cloneable up to (but not including)
758 struct kref refcount;
761 void dc_sink_retain(struct dc_sink *sink);
762 void dc_sink_release(struct dc_sink *sink);
764 struct dc_sink_init_data {
765 enum signal_type sink_signal;
766 struct dc_link *link;
767 uint32_t dongle_max_pix_clk;
768 bool converter_disable_audio;
771 struct dc_sink *dc_sink_create(const struct dc_sink_init_data *init_params);
773 /* Newer interfaces */
775 struct dc_plane_address address;
776 struct dc_cursor_attributes attributes;
780 /*******************************************************************************
781 * Interrupt interfaces
782 ******************************************************************************/
783 enum dc_irq_source dc_interrupt_to_irq_source(
787 bool dc_interrupt_set(struct dc *dc, enum dc_irq_source src, bool enable);
788 void dc_interrupt_ack(struct dc *dc, enum dc_irq_source src);
789 enum dc_irq_source dc_get_hpd_irq_source_at_index(
790 struct dc *dc, uint32_t link_index);
792 /*******************************************************************************
794 ******************************************************************************/
796 void dc_set_power_state(
798 enum dc_acpi_cm_power_state power_state);
799 void dc_resume(struct dc *dc);
800 unsigned int dc_get_current_backlight_pwm(struct dc *dc);
801 unsigned int dc_get_target_backlight_pwm(struct dc *dc);
803 bool dc_is_dmcu_initialized(struct dc *dc);
805 #endif /* DC_INTERFACE_H_ */