2 * Copyright 2012-14 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
26 #ifndef DC_INTERFACE_H_
27 #define DC_INTERFACE_H_
30 #include "grph_object_defs.h"
31 #include "logger_types.h"
32 #include "gpio_types.h"
33 #include "link_service_types.h"
34 #include "grph_object_ctrl_defs.h"
35 #include <inc/hw/opp.h>
37 #include "inc/hw_sequencer.h"
38 #include "inc/compressor.h"
39 #include "inc/hw/dmcu.h"
40 #include "dml/display_mode_lib.h"
42 #define DC_VER "3.2.69"
44 #define MAX_SURFACES 3
47 #define MAX_SINKS_PER_LINK 4
49 /*******************************************************************************
50 * Display Core Interfaces
51 ******************************************************************************/
54 struct dmcu_version dmcu_version;
57 enum dp_protocol_version {
62 DC_PLANE_TYPE_INVALID,
63 DC_PLANE_TYPE_DCE_RGB,
64 DC_PLANE_TYPE_DCE_UNDERLAY,
65 DC_PLANE_TYPE_DCN_UNIVERSAL,
69 enum dc_plane_type type;
70 uint32_t blends_with_above : 1;
71 uint32_t blends_with_below : 1;
72 uint32_t per_pixel_alpha : 1;
74 uint32_t argb8888 : 1;
79 } pixel_format_support;
80 // max upscaling factor x1000
81 // upscaling factors are always >= 1
82 // for example, 1080p -> 8K is 4.0, or 4000 raw value
88 // max downscale factor x1000
89 // downscale factors are always <= 1
90 // for example, 8K -> 1080p is 0.25, or 250 raw value
95 } max_downscale_factor;
102 uint32_t max_slave_planes;
104 uint32_t max_downscale_ratio;
105 uint32_t i2c_speed_in_khz;
106 uint32_t dmdata_alloc_size;
107 unsigned int max_cursor_size;
108 unsigned int max_video_width;
109 int linear_pitch_alignment;
110 bool dcc_const_color;
114 bool post_blend_color_processing;
115 bool force_dp_tps4_for_cp2520;
116 bool disable_dp_clk_share;
117 bool psp_setup_panel_mode;
118 bool extended_aux_timeout_support;
121 enum dp_protocol_version max_dp_protocol_version;
122 struct dc_plane_cap planes[MAX_PLANES];
126 bool no_connect_phy_config;
128 bool skip_clock_update;
131 struct dc_dcc_surface_param {
132 struct dc_size surface_size;
133 enum surface_pixel_format format;
134 enum swizzle_mode_values swizzle_mode;
135 enum dc_scan_direction scan;
138 struct dc_dcc_setting {
139 unsigned int max_compressed_blk_size;
140 unsigned int max_uncompressed_blk_size;
141 bool independent_64b_blks;
144 struct dc_surface_dcc_cap {
147 struct dc_dcc_setting rgb;
151 struct dc_dcc_setting luma;
152 struct dc_dcc_setting chroma;
157 bool const_color_support;
160 struct dc_static_screen_params {
167 unsigned int num_frames;
171 /* Surface update type is used by dc_update_surfaces_and_stream
172 * The update type is determined at the very beginning of the function based
173 * on parameters passed in and decides how much programming (or updating) is
174 * going to be done during the call.
176 * UPDATE_TYPE_FAST is used for really fast updates that do not require much
177 * logical calculations or hardware register programming. This update MUST be
178 * ISR safe on windows. Currently fast update will only be used to flip surface
181 * UPDATE_TYPE_MED is used for slower updates which require significant hw
182 * re-programming however do not affect bandwidth consumption or clock
183 * requirements. At present, this is the level at which front end updates
184 * that do not require us to run bw_calcs happen. These are in/out transfer func
185 * updates, viewport offset changes, recout size changes and pixel depth changes.
186 * This update can be done at ISR, but we want to minimize how often this happens.
188 * UPDATE_TYPE_FULL is slow. Really slow. This requires us to recalculate our
189 * bandwidth and clocks, possibly rearrange some pipes and reprogram anything front
190 * end related. Any time viewport dimensions, recout dimensions, scaling ratios or
191 * gamma need to be adjusted or pipe needs to be turned on (or disconnected) we do
192 * a full update. This cannot be done at ISR level and should be a rare event.
193 * Unless someone is stress testing mpo enter/exit, playing with colour or adjusting
194 * underscan we don't expect to see this call at all.
197 enum surface_update_type {
198 UPDATE_TYPE_FAST, /* super fast, safe to execute in isr */
199 UPDATE_TYPE_MED, /* ISR safe, most of programming needed, no bw/clk change*/
200 UPDATE_TYPE_FULL, /* may need to shuffle resources */
203 /* Forward declaration*/
205 struct dc_plane_state;
209 struct dc_cap_funcs {
210 bool (*get_dcc_compression_cap)(const struct dc *dc,
211 const struct dc_dcc_surface_param *input,
212 struct dc_surface_dcc_cap *output);
215 struct link_training_settings;
218 /* Structure to hold configuration flags set by dm at dc creation. */
221 bool disable_disp_pll_sharing;
223 bool optimize_edp_link_rate;
224 bool disable_fractional_pwm;
225 bool allow_seamless_boot_optimization;
226 bool power_down_display_on_boot;
227 bool edp_not_connected;
230 bool disable_extended_timeout_support; // Used to disable extended timeout and lttpr feature as well
231 bool multi_mon_pp_mclk_switch;
234 enum visual_confirm {
235 VISUAL_CONFIRM_DISABLE = 0,
236 VISUAL_CONFIRM_SURFACE = 1,
237 VISUAL_CONFIRM_HDR = 2,
238 VISUAL_CONFIRM_MPCTREE = 4,
244 DCC_HALF_REQ_DISALBE = 2,
247 enum pipe_split_policy {
248 MPC_SPLIT_DYNAMIC = 0,
250 MPC_SPLIT_AVOID_MULT_DISP = 2,
253 enum wm_report_mode {
254 WM_REPORT_DEFAULT = 0,
255 WM_REPORT_OVERRIDE = 1,
258 dtm_level_p0 = 0,/*highest voltage*/
262 dtm_level_p4,/*when active_display_count = 0*/
266 DCN_PWR_STATE_UNKNOWN = -1,
267 DCN_PWR_STATE_MISSION_MODE = 0,
268 DCN_PWR_STATE_LOW_POWER = 3,
272 * For any clocks that may differ per pipe
273 * only the max is stored in this structure
280 int dcfclk_deep_sleep_khz;
284 bool p_state_change_support;
285 enum dcn_pwr_state pwr_state;
287 * Elements below are not compared for the purposes of
288 * optimization required
290 bool prev_p_state_change_support;
291 enum dtm_pstate dtm_level;
292 int max_supported_dppclk_khz;
293 int max_supported_dispclk_khz;
294 int bw_dppclk_khz; /*a copy of dppclk_khz*/
298 struct dc_bw_validation_profile {
301 unsigned long long total_ticks;
302 unsigned long long voltage_level_ticks;
303 unsigned long long watermark_ticks;
304 unsigned long long rq_dlg_ticks;
306 unsigned long long total_count;
307 unsigned long long skip_fast_count;
308 unsigned long long skip_pass_count;
309 unsigned long long skip_fail_count;
312 #define BW_VAL_TRACE_SETUP() \
313 unsigned long long end_tick = 0; \
314 unsigned long long voltage_level_tick = 0; \
315 unsigned long long watermark_tick = 0; \
316 unsigned long long start_tick = dc->debug.bw_val_profile.enable ? \
317 dm_get_timestamp(dc->ctx) : 0
319 #define BW_VAL_TRACE_COUNT() \
320 if (dc->debug.bw_val_profile.enable) \
321 dc->debug.bw_val_profile.total_count++
323 #define BW_VAL_TRACE_SKIP(status) \
324 if (dc->debug.bw_val_profile.enable) { \
325 if (!voltage_level_tick) \
326 voltage_level_tick = dm_get_timestamp(dc->ctx); \
327 dc->debug.bw_val_profile.skip_ ## status ## _count++; \
330 #define BW_VAL_TRACE_END_VOLTAGE_LEVEL() \
331 if (dc->debug.bw_val_profile.enable) \
332 voltage_level_tick = dm_get_timestamp(dc->ctx)
334 #define BW_VAL_TRACE_END_WATERMARKS() \
335 if (dc->debug.bw_val_profile.enable) \
336 watermark_tick = dm_get_timestamp(dc->ctx)
338 #define BW_VAL_TRACE_FINISH() \
339 if (dc->debug.bw_val_profile.enable) { \
340 end_tick = dm_get_timestamp(dc->ctx); \
341 dc->debug.bw_val_profile.total_ticks += end_tick - start_tick; \
342 dc->debug.bw_val_profile.voltage_level_ticks += voltage_level_tick - start_tick; \
343 if (watermark_tick) { \
344 dc->debug.bw_val_profile.watermark_ticks += watermark_tick - voltage_level_tick; \
345 dc->debug.bw_val_profile.rq_dlg_ticks += end_tick - watermark_tick; \
349 struct dc_debug_options {
350 enum visual_confirm visual_confirm;
356 bool validation_trace;
357 bool bandwidth_calcs_trace;
358 int max_downscale_src_width;
360 /* stutter efficiency related */
361 bool disable_stutter;
363 enum dcc_option disable_dcc;
364 enum pipe_split_policy pipe_split_policy;
365 bool force_single_disp_pipe_split;
366 bool voltage_align_fclk;
368 bool disable_dfs_bypass;
369 bool disable_dpp_power_gate;
370 bool disable_hubp_power_gate;
371 bool disable_dsc_power_gate;
372 int dsc_min_slice_height_override;
373 int dsc_bpp_increment_div;
374 bool native422_support;
375 bool disable_pplib_wm_range;
376 enum wm_report_mode pplib_wm_report_mode;
377 unsigned int min_disp_clk_khz;
378 unsigned int min_dpp_clk_khz;
379 int sr_exit_time_dpm0_ns;
380 int sr_enter_plus_exit_time_dpm0_ns;
382 int sr_enter_plus_exit_time_ns;
383 int urgent_latency_ns;
384 uint32_t underflow_assert_delay_us;
385 int percent_of_ideal_drambw;
386 int dram_clock_change_latency_ns;
387 bool optimized_watermark;
389 bool disable_pplib_clock_request;
390 bool disable_clock_gate;
393 bool force_abm_enable;
394 bool disable_stereo_support;
396 bool performance_trace;
397 bool az_endpoint_mute_only;
398 bool always_use_regamma;
399 bool p010_mpo_support;
400 bool recovery_enabled;
401 bool avoid_vbios_exec_table;
402 bool scl_reset_length10;
404 bool skip_detection_link_training;
405 bool remove_disconnect_edp;
406 unsigned int force_odm_combine; //bit vector based on otg inst
407 unsigned int force_fclk_khz;
408 bool disable_tri_buf;
409 bool dmub_offload_enabled;
410 bool dmcub_emulation;
411 bool dmub_command_table; /* for testing only */
412 struct dc_bw_validation_profile bw_val_profile;
414 bool disable_48mhz_pwrdwn;
415 /* This forces a hard min on the DCFCLK requested to SMU/PP
416 * watermarks are not affected.
418 unsigned int force_min_dcfclk_mhz;
419 bool disable_timing_sync;
421 int force_clock_mode;/*every mode change.*/
423 bool nv12_iflip_vm_wa;
424 bool disable_dram_clock_change_vactive_support;
425 bool validate_dml_output;
426 bool enable_dmcub_surface_flip;
427 bool usbc_combo_phy_reset_wa;
431 struct dc_debug_data {
432 uint32_t ltFailCount;
433 uint32_t i2cErrorCount;
434 uint32_t auxErrorCount;
437 struct dc_phy_addr_space_config {
450 uint64_t page_table_start_addr;
451 uint64_t page_table_end_addr;
452 uint64_t page_table_base_addr;
456 uint64_t page_table_default_page_addr;
459 struct dc_virtual_addr_space_config {
460 uint64_t page_table_base_addr;
461 uint64_t page_table_start_addr;
462 uint64_t page_table_end_addr;
463 uint32_t page_table_block_size_in_bytes;
464 uint8_t page_table_depth; // 1 = 1 level, 2 = 2 level, etc. 0 = invalid
467 struct dc_bounding_box_overrides {
469 int sr_enter_plus_exit_time_ns;
470 int urgent_latency_ns;
471 int percent_of_ideal_drambw;
472 int dram_clock_change_latency_ns;
473 /* This forces a hard min on the DCFCLK we use
474 * for DML. Unlike the debug option for forcing
475 * DCFCLK, this override affects watermark calculations
481 struct resource_pool;
483 struct gpu_info_soc_bounding_box_v1_0;
485 struct dc_versions versions;
487 struct dc_cap_funcs cap_funcs;
488 struct dc_config config;
489 struct dc_debug_options debug;
490 struct dc_bounding_box_overrides bb_overrides;
491 struct dc_bug_wa work_arounds;
492 struct dc_context *ctx;
493 struct dc_phy_addr_space_config vm_pa_config;
496 struct dc_link *links[MAX_PIPES * 2];
498 struct dc_state *current_state;
499 struct resource_pool *res_pool;
501 struct clk_mgr *clk_mgr;
503 /* Display Engine Clock levels */
504 struct dm_pp_clock_levels sclk_lvls;
506 /* Inputs into BW and WM calculations. */
507 struct bw_calcs_dceip *bw_dceip;
508 struct bw_calcs_vbios *bw_vbios;
509 #ifdef CONFIG_DRM_AMD_DC_DCN
510 struct dcn_soc_bounding_box *dcn_soc;
511 struct dcn_ip_params *dcn_ip;
512 struct display_mode_lib dml;
516 struct hw_sequencer_funcs hwss;
517 struct dce_hwseq *hwseq;
519 /* Require to optimize clocks and bandwidth for added/removed planes */
520 bool optimized_required;
522 /* Require to maintain clocks and bandwidth for UEFI enabled HW */
523 int optimize_seamless_boot_streams;
526 struct compressor *fbc_compressor;
528 struct dc_debug_data debug_data;
530 const char *build_id;
531 struct vm_helper *vm_helper;
532 const struct gpu_info_soc_bounding_box_v1_0 *soc_bounding_box;
535 enum frame_buffer_mode {
536 FRAME_BUFFER_MODE_LOCAL_ONLY = 0,
537 FRAME_BUFFER_MODE_ZFB_ONLY,
538 FRAME_BUFFER_MODE_MIXED_ZFB_AND_LOCAL,
541 struct dchub_init_data {
542 int64_t zfb_phys_addr_base;
543 int64_t zfb_mc_base_addr;
544 uint64_t zfb_size_in_byte;
545 enum frame_buffer_mode fb_mode;
546 bool dchub_initialzied;
547 bool dchub_info_valid;
550 struct dc_init_data {
551 struct hw_asic_id asic_id;
552 void *driver; /* ctx */
553 struct cgs_device *cgs_device;
554 struct dc_bounding_box_overrides bb_overrides;
556 int num_virtual_links;
558 * If 'vbios_override' not NULL, it will be called instead
559 * of the real VBIOS. Intended use is Diagnostics on FPGA.
561 struct dc_bios *vbios_override;
562 enum dce_environment dce_environment;
564 struct dmub_offload_funcs *dmub_if;
565 struct dc_reg_helper_state *dmub_offload;
567 struct dc_config flags;
570 * gpu_info FW provided soc bounding box struct or 0 if not
573 const struct gpu_info_soc_bounding_box_v1_0 *soc_bounding_box;
576 struct dc_callback_init {
577 #ifdef CONFIG_DRM_AMD_DC_HDCP
578 struct cp_psp cp_psp;
584 struct dc *dc_create(const struct dc_init_data *init_params);
585 void dc_hardware_init(struct dc *dc);
587 int dc_get_vmid_use_vector(struct dc *dc);
588 void dc_setup_vm_context(struct dc *dc, struct dc_virtual_addr_space_config *va_config, int vmid);
589 /* Returns the number of vmids supported */
590 int dc_setup_system_context(struct dc *dc, struct dc_phy_addr_space_config *pa_config);
591 void dc_init_callbacks(struct dc *dc,
592 const struct dc_callback_init *init_params);
593 void dc_deinit_callbacks(struct dc *dc);
594 void dc_destroy(struct dc **dc);
596 /*******************************************************************************
598 ******************************************************************************/
601 TRANSFER_FUNC_POINTS = 1025
604 struct dc_hdr_static_metadata {
605 /* display chromaticities and white point in units of 0.00001 */
606 unsigned int chromaticity_green_x;
607 unsigned int chromaticity_green_y;
608 unsigned int chromaticity_blue_x;
609 unsigned int chromaticity_blue_y;
610 unsigned int chromaticity_red_x;
611 unsigned int chromaticity_red_y;
612 unsigned int chromaticity_white_point_x;
613 unsigned int chromaticity_white_point_y;
615 uint32_t min_luminance;
616 uint32_t max_luminance;
617 uint32_t maximum_content_light_level;
618 uint32_t maximum_frame_average_light_level;
621 enum dc_transfer_func_type {
623 TF_TYPE_DISTRIBUTED_POINTS,
628 struct dc_transfer_func_distributed_points {
629 struct fixed31_32 red[TRANSFER_FUNC_POINTS];
630 struct fixed31_32 green[TRANSFER_FUNC_POINTS];
631 struct fixed31_32 blue[TRANSFER_FUNC_POINTS];
633 uint16_t end_exponent;
634 uint16_t x_point_at_y1_red;
635 uint16_t x_point_at_y1_green;
636 uint16_t x_point_at_y1_blue;
639 enum dc_transfer_func_predefined {
640 TRANSFER_FUNCTION_SRGB,
641 TRANSFER_FUNCTION_BT709,
642 TRANSFER_FUNCTION_PQ,
643 TRANSFER_FUNCTION_LINEAR,
644 TRANSFER_FUNCTION_UNITY,
645 TRANSFER_FUNCTION_HLG,
646 TRANSFER_FUNCTION_HLG12,
647 TRANSFER_FUNCTION_GAMMA22,
648 TRANSFER_FUNCTION_GAMMA24,
649 TRANSFER_FUNCTION_GAMMA26
653 struct dc_transfer_func {
654 struct kref refcount;
655 enum dc_transfer_func_type type;
656 enum dc_transfer_func_predefined tf;
657 /* FP16 1.0 reference level in nits, default is 80 nits, only for PQ*/
658 uint32_t sdr_ref_white_level;
659 struct dc_context *ctx;
661 struct pwl_params pwl;
662 struct dc_transfer_func_distributed_points tf_pts;
667 union dc_3dlut_state {
669 uint32_t initialized:1; /*if 3dlut is went through color module for initialization */
670 uint32_t rmu_idx_valid:1; /*if mux settings are valid*/
671 uint32_t rmu_mux_num:3; /*index of mux to use*/
672 uint32_t mpc_rmu0_mux:4; /*select mpcc on mux, one of the following : mpcc0, mpcc1, mpcc2, mpcc3*/
673 uint32_t mpc_rmu1_mux:4;
674 uint32_t mpc_rmu2_mux:4;
675 uint32_t reserved:15;
682 struct kref refcount;
683 struct tetrahedral_params lut_3d;
684 struct fixed31_32 hdr_multiplier;
685 bool initialized; /*remove after diag fix*/
686 union dc_3dlut_state state;
687 struct dc_context *ctx;
690 * This structure is filled in by dc_surface_get_status and contains
691 * the last requested address and the currently active address so the called
692 * can determine if there are any outstanding flips
694 struct dc_plane_status {
695 struct dc_plane_address requested_address;
696 struct dc_plane_address current_address;
697 bool is_flip_pending;
701 union surface_update_flags {
704 uint32_t addr_update:1;
706 uint32_t dcc_change:1;
707 uint32_t color_space_change:1;
708 uint32_t horizontal_mirror_change:1;
709 uint32_t per_pixel_alpha_change:1;
710 uint32_t global_alpha_change:1;
712 uint32_t rotation_change:1;
713 uint32_t swizzle_change:1;
714 uint32_t scaling_change:1;
715 uint32_t position_change:1;
716 uint32_t in_transfer_func_change:1;
717 uint32_t input_csc_change:1;
718 uint32_t coeff_reduction_change:1;
719 uint32_t output_tf_change:1;
720 uint32_t pixel_format_change:1;
721 uint32_t plane_size_change:1;
724 uint32_t new_plane:1;
725 uint32_t bpp_change:1;
726 uint32_t gamma_change:1;
727 uint32_t bandwidth_change:1;
728 uint32_t clock_change:1;
729 uint32_t stereo_format_change:1;
730 uint32_t full_update:1;
736 struct dc_plane_state {
737 struct dc_plane_address address;
738 struct dc_plane_flip_time time;
739 bool triplebuffer_flips;
740 struct scaling_taps scaling_quality;
741 struct rect src_rect;
742 struct rect dst_rect;
743 struct rect clip_rect;
745 struct plane_size plane_size;
746 union dc_tiling_info tiling_info;
748 struct dc_plane_dcc_param dcc;
750 struct dc_gamma *gamma_correction;
751 struct dc_transfer_func *in_transfer_func;
752 struct dc_bias_and_scale *bias_and_scale;
753 struct dc_csc_transform input_csc_color_matrix;
754 struct fixed31_32 coeff_reduction_factor;
755 struct fixed31_32 hdr_mult;
757 // TODO: No longer used, remove
758 struct dc_hdr_static_metadata hdr_static_ctx;
760 enum dc_color_space color_space;
762 struct dc_3dlut *lut3d_func;
763 struct dc_transfer_func *in_shaper_func;
764 struct dc_transfer_func *blend_tf;
766 enum surface_pixel_format format;
767 enum dc_rotation_angle rotation;
768 enum plane_stereo_format stereo_format;
770 bool is_tiling_rotated;
771 bool per_pixel_alpha;
773 int global_alpha_value;
776 bool horizontal_mirror;
779 union surface_update_flags update_flags;
780 /* private to DC core */
781 struct dc_plane_status status;
782 struct dc_context *ctx;
784 /* HACK: Workaround for forcing full reprogramming under some conditions */
785 bool force_full_update;
787 /* private to dc_surface.c */
788 enum dc_irq_source irq_source;
789 struct kref refcount;
792 struct dc_plane_info {
793 struct plane_size plane_size;
794 union dc_tiling_info tiling_info;
795 struct dc_plane_dcc_param dcc;
796 enum surface_pixel_format format;
797 enum dc_rotation_angle rotation;
798 enum plane_stereo_format stereo_format;
799 enum dc_color_space color_space;
800 bool horizontal_mirror;
802 bool per_pixel_alpha;
804 int global_alpha_value;
805 bool input_csc_enabled;
809 struct dc_scaling_info {
810 struct rect src_rect;
811 struct rect dst_rect;
812 struct rect clip_rect;
813 struct scaling_taps scaling_quality;
816 struct dc_surface_update {
817 struct dc_plane_state *surface;
819 /* isr safe update parameters. null means no updates */
820 const struct dc_flip_addrs *flip_addr;
821 const struct dc_plane_info *plane_info;
822 const struct dc_scaling_info *scaling_info;
823 struct fixed31_32 hdr_mult;
824 /* following updates require alloc/sleep/spin that is not isr safe,
825 * null means no updates
827 const struct dc_gamma *gamma;
828 const struct dc_transfer_func *in_transfer_func;
830 const struct dc_csc_transform *input_csc_color_matrix;
831 const struct fixed31_32 *coeff_reduction_factor;
832 const struct dc_transfer_func *func_shaper;
833 const struct dc_3dlut *lut3d_func;
834 const struct dc_transfer_func *blend_tf;
838 * Create a new surface with default parameters;
840 struct dc_plane_state *dc_create_plane_state(struct dc *dc);
841 const struct dc_plane_status *dc_plane_get_status(
842 const struct dc_plane_state *plane_state);
844 void dc_plane_state_retain(struct dc_plane_state *plane_state);
845 void dc_plane_state_release(struct dc_plane_state *plane_state);
847 void dc_gamma_retain(struct dc_gamma *dc_gamma);
848 void dc_gamma_release(struct dc_gamma **dc_gamma);
849 struct dc_gamma *dc_create_gamma(void);
851 void dc_transfer_func_retain(struct dc_transfer_func *dc_tf);
852 void dc_transfer_func_release(struct dc_transfer_func *dc_tf);
853 struct dc_transfer_func *dc_create_transfer_func(void);
855 struct dc_3dlut *dc_create_3dlut_func(void);
856 void dc_3dlut_func_release(struct dc_3dlut *lut);
857 void dc_3dlut_func_retain(struct dc_3dlut *lut);
859 * This structure holds a surface address. There could be multiple addresses
860 * in cases such as Stereo 3D, Planar YUV, etc. Other per-flip attributes such
861 * as frame durations and DCC format can also be set.
863 struct dc_flip_addrs {
864 struct dc_plane_address address;
865 unsigned int flip_timestamp_in_us;
867 /* TODO: add flip duration for FreeSync */
870 bool dc_post_update_surfaces_to_stream(
873 #include "dc_stream.h"
876 * Structure to store surface/stream associations for validation
878 struct dc_validation_set {
879 struct dc_stream_state *stream;
880 struct dc_plane_state *plane_states[MAX_SURFACES];
884 bool dc_validate_seamless_boot_timing(const struct dc *dc,
885 const struct dc_sink *sink,
886 struct dc_crtc_timing *crtc_timing);
888 enum dc_status dc_validate_plane(struct dc *dc, const struct dc_plane_state *plane_state);
890 void get_clock_requirements_for_state(struct dc_state *state, struct AsicStateEx *info);
892 bool dc_set_generic_gpio_for_stereo(bool enable,
893 struct gpio_service *gpio_service);
896 * fast_validate: we return after determining if we can support the new state,
897 * but before we populate the programming info
899 enum dc_status dc_validate_global_state(
901 struct dc_state *new_ctx,
905 void dc_resource_state_construct(
907 struct dc_state *dst_ctx);
909 void dc_resource_state_copy_construct(
910 const struct dc_state *src_ctx,
911 struct dc_state *dst_ctx);
913 void dc_resource_state_copy_construct_current(
915 struct dc_state *dst_ctx);
917 void dc_resource_state_destruct(struct dc_state *context);
919 bool dc_resource_is_dsc_encoding_supported(const struct dc *dc);
922 * TODO update to make it about validation sets
923 * Set up streams and links associated to drive sinks
924 * The streams parameter is an absolute set of all active streams.
927 * Phy, Encoder, Timing Generator are programmed and enabled.
928 * New streams are enabled with blank stream; no memory read.
930 bool dc_commit_state(struct dc *dc, struct dc_state *context);
933 struct dc_state *dc_create_state(struct dc *dc);
934 struct dc_state *dc_copy_state(struct dc_state *src_ctx);
935 void dc_retain_state(struct dc_state *context);
936 void dc_release_state(struct dc_state *context);
938 /*******************************************************************************
940 ******************************************************************************/
943 union dpcd_rev dpcd_rev;
944 union max_lane_count max_ln_count;
945 union max_down_spread max_down_spread;
946 union dprx_feature dprx_feature;
948 /* valid only for eDP v1.4 or higher*/
949 uint8_t edp_supported_link_rates_count;
950 enum dc_link_rate edp_supported_link_rates[8];
952 /* dongle type (DP converter, CV smart dongle) */
953 enum display_dongle_type dongle_type;
954 /* branch device or sink device */
956 /* Dongle's downstream count. */
957 union sink_count sink_count;
958 /* If dongle_type == DISPLAY_DONGLE_DP_HDMI_CONVERTER,
959 indicates 'Frame Sequential-to-lllFrame Pack' conversion capability.*/
960 struct dc_dongle_caps dongle_caps;
962 uint32_t sink_dev_id;
963 int8_t sink_dev_id_str[6];
964 int8_t sink_hw_revision;
965 int8_t sink_fw_revision[2];
967 uint32_t branch_dev_id;
968 int8_t branch_dev_name[6];
969 int8_t branch_hw_revision;
970 int8_t branch_fw_revision[2];
972 bool allow_invalid_MSA_timing_param;
974 bool dpcd_display_control_capable;
975 bool ext_receiver_cap_field_present;
976 union dpcd_fec_capability fec_cap;
977 struct dpcd_dsc_capabilities dsc_caps;
978 struct dc_lttpr_caps lttpr_caps;
984 /*******************************************************************************
985 * Sink Interfaces - A sink corresponds to a display output device
986 ******************************************************************************/
988 struct dc_container_id {
989 // 128bit GUID in binary form
990 unsigned char guid[16];
991 // 8 byte port ID -> ELD.PortID
992 unsigned int portId[2];
993 // 128bit GUID in binary formufacturer name -> ELD.ManufacturerName
994 unsigned short manufacturerName;
995 // 2 byte product code -> ELD.ProductCode
996 unsigned short productCode;
1000 struct dc_sink_dsc_caps {
1001 // 'true' if these are virtual DPCD's DSC caps (immediately upstream of sink in MST topology),
1002 // 'false' if they are sink's DSC caps
1003 bool is_virtual_dpcd_dsc;
1004 struct dsc_dec_dpcd_caps dsc_dec_caps;
1008 * The sink structure contains EDID and other display device properties
1011 enum signal_type sink_signal;
1012 struct dc_edid dc_edid; /* raw edid */
1013 struct dc_edid_caps edid_caps; /* parse display caps */
1014 struct dc_container_id *dc_container_id;
1015 uint32_t dongle_max_pix_clk;
1017 struct stereo_3d_features features_3d[TIMING_3D_FORMAT_MAX];
1018 bool converter_disable_audio;
1020 struct dc_sink_dsc_caps sink_dsc_caps;
1022 /* private to DC core */
1023 struct dc_link *link;
1024 struct dc_context *ctx;
1028 /* private to dc_sink.c */
1029 // refcount must be the last member in dc_sink, since we want the
1030 // sink structure to be logically cloneable up to (but not including)
1032 struct kref refcount;
1035 void dc_sink_retain(struct dc_sink *sink);
1036 void dc_sink_release(struct dc_sink *sink);
1038 struct dc_sink_init_data {
1039 enum signal_type sink_signal;
1040 struct dc_link *link;
1041 uint32_t dongle_max_pix_clk;
1042 bool converter_disable_audio;
1045 struct dc_sink *dc_sink_create(const struct dc_sink_init_data *init_params);
1047 /* Newer interfaces */
1049 struct dc_plane_address address;
1050 struct dc_cursor_attributes attributes;
1054 /*******************************************************************************
1055 * Interrupt interfaces
1056 ******************************************************************************/
1057 enum dc_irq_source dc_interrupt_to_irq_source(
1061 bool dc_interrupt_set(struct dc *dc, enum dc_irq_source src, bool enable);
1062 void dc_interrupt_ack(struct dc *dc, enum dc_irq_source src);
1063 enum dc_irq_source dc_get_hpd_irq_source_at_index(
1064 struct dc *dc, uint32_t link_index);
1066 /*******************************************************************************
1068 ******************************************************************************/
1070 void dc_set_power_state(
1072 enum dc_acpi_cm_power_state power_state);
1073 void dc_resume(struct dc *dc);
1074 unsigned int dc_get_current_backlight_pwm(struct dc *dc);
1075 unsigned int dc_get_target_backlight_pwm(struct dc *dc);
1077 bool dc_is_dmcu_initialized(struct dc *dc);
1078 bool dc_is_hw_initialized(struct dc *dc);
1080 enum dc_status dc_set_clock(struct dc *dc, enum dc_clock_type clock_type, uint32_t clk_khz, uint32_t stepping);
1081 void dc_get_clock(struct dc *dc, enum dc_clock_type clock_type, struct dc_clock_config *clock_cfg);
1082 /*******************************************************************************
1084 ******************************************************************************/
1086 #endif /* DC_INTERFACE_H_ */