drivers/gpu/drm/amd/display/dc/dce/dce_clocks.c

   1 /*
   2  * Copyright 2012-16 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: AMD
  23  *
  24  */
  25
  26 #include "dce_clocks.h"
  27 #include "dm_services.h"
  28 #include "reg_helper.h"
  29 #include "fixed31_32.h"
  30 #include "bios_parser_interface.h"
  31 #include "dc.h"
  32 #include "dmcu.h"
  33 #ifdef CONFIG_X86
  34 #include "dcn_calcs.h"
  35 #endif
  36 #include "core_types.h"
  37 #include "dc_types.h"
  38 #include "dal_asic_id.h"
  39
  40 #define TO_DCE_CLOCKS(clocks)\
  41         container_of(clocks, struct dce_dccg, base)
  42
  43 #define REG(reg) \
  44         (clk_dce->regs->reg)
  45
  46 #undef FN
  47 #define FN(reg_name, field_name) \
  48         clk_dce->clk_shift->field_name, clk_dce->clk_mask->field_name
  49
  50 #define CTX \
  51         clk_dce->base.ctx
  52 #define DC_LOGGER \
  53         clk->ctx->logger
  54
  55 /* Max clock values for each state indexed by "enum clocks_state": */
  56 static const struct state_dependent_clocks dce80_max_clks_by_state[] = {
  57 /* ClocksStateInvalid - should not be used */
  58 { .display_clk_khz = 0, .pixel_clk_khz = 0 },
  59 /* ClocksStateUltraLow - not expected to be used for DCE 8.0 */
  60 { .display_clk_khz = 0, .pixel_clk_khz = 0 },
  61 /* ClocksStateLow */
  62 { .display_clk_khz = 352000, .pixel_clk_khz = 330000},
  63 /* ClocksStateNominal */
  64 { .display_clk_khz = 600000, .pixel_clk_khz = 400000 },
  65 /* ClocksStatePerformance */
  66 { .display_clk_khz = 600000, .pixel_clk_khz = 400000 } };
  67
  68 static const struct state_dependent_clocks dce110_max_clks_by_state[] = {
  69 /*ClocksStateInvalid - should not be used*/
  70 { .display_clk_khz = 0, .pixel_clk_khz = 0 },
  71 /*ClocksStateUltraLow - currently by HW design team not supposed to be used*/
  72 { .display_clk_khz = 352000, .pixel_clk_khz = 330000 },
  73 /*ClocksStateLow*/
  74 { .display_clk_khz = 352000, .pixel_clk_khz = 330000 },
  75 /*ClocksStateNominal*/
  76 { .display_clk_khz = 467000, .pixel_clk_khz = 400000 },
  77 /*ClocksStatePerformance*/
  78 { .display_clk_khz = 643000, .pixel_clk_khz = 400000 } };
  79
  80 static const struct state_dependent_clocks dce112_max_clks_by_state[] = {
  81 /*ClocksStateInvalid - should not be used*/
  82 { .display_clk_khz = 0, .pixel_clk_khz = 0 },
  83 /*ClocksStateUltraLow - currently by HW design team not supposed to be used*/
  84 { .display_clk_khz = 389189, .pixel_clk_khz = 346672 },
  85 /*ClocksStateLow*/
  86 { .display_clk_khz = 459000, .pixel_clk_khz = 400000 },
  87 /*ClocksStateNominal*/
  88 { .display_clk_khz = 667000, .pixel_clk_khz = 600000 },
  89 /*ClocksStatePerformance*/
  90 { .display_clk_khz = 1132000, .pixel_clk_khz = 600000 } };
  91
  92 static const struct state_dependent_clocks dce120_max_clks_by_state[] = {
  93 /*ClocksStateInvalid - should not be used*/
  94 { .display_clk_khz = 0, .pixel_clk_khz = 0 },
  95 /*ClocksStateUltraLow - currently by HW design team not supposed to be used*/
  96 { .display_clk_khz = 0, .pixel_clk_khz = 0 },
  97 /*ClocksStateLow*/
  98 { .display_clk_khz = 460000, .pixel_clk_khz = 400000 },
  99 /*ClocksStateNominal*/
 100 { .display_clk_khz = 670000, .pixel_clk_khz = 600000 },
 101 /*ClocksStatePerformance*/
 102 { .display_clk_khz = 1133000, .pixel_clk_khz = 600000 } };
 103
 104 /* Starting DID for each range */
 105 enum dentist_base_divider_id {
 106         DENTIST_BASE_DID_1 = 0x08,
 107         DENTIST_BASE_DID_2 = 0x40,
 108         DENTIST_BASE_DID_3 = 0x60,
 109         DENTIST_MAX_DID    = 0x80
 110 };
 111
 112 /* Starting point and step size for each divider range.*/
 113 enum dentist_divider_range {
 114         DENTIST_DIVIDER_RANGE_1_START = 8,   /* 2.00  */
 115         DENTIST_DIVIDER_RANGE_1_STEP  = 1,   /* 0.25  */
 116         DENTIST_DIVIDER_RANGE_2_START = 64,  /* 16.00 */
 117         DENTIST_DIVIDER_RANGE_2_STEP  = 2,   /* 0.50  */
 118         DENTIST_DIVIDER_RANGE_3_START = 128, /* 32.00 */
 119         DENTIST_DIVIDER_RANGE_3_STEP  = 4,   /* 1.00  */
 120         DENTIST_DIVIDER_RANGE_SCALE_FACTOR = 4
 121 };
 122
 123 static int dentist_get_divider_from_did(int did)
 124 {
 125         if (did < DENTIST_BASE_DID_1)
 126                 did = DENTIST_BASE_DID_1;
 127         if (did > DENTIST_MAX_DID)
 128                 did = DENTIST_MAX_DID;
 129
 130         if (did < DENTIST_BASE_DID_2) {
 131                 return DENTIST_DIVIDER_RANGE_1_START + DENTIST_DIVIDER_RANGE_1_STEP
 132                                                         * (did - DENTIST_BASE_DID_1);
 133         } else if (did < DENTIST_BASE_DID_3) {
 134                 return DENTIST_DIVIDER_RANGE_2_START + DENTIST_DIVIDER_RANGE_2_STEP
 135                                                         * (did - DENTIST_BASE_DID_2);
 136         } else {
 137                 return DENTIST_DIVIDER_RANGE_3_START + DENTIST_DIVIDER_RANGE_3_STEP
 138                                                         * (did - DENTIST_BASE_DID_3);
 139         }
 140 }
 141
 142 /* SW will adjust DP REF Clock average value for all purposes
 143  * (DP DTO / DP Audio DTO and DP GTC)
 144  if clock is spread for all cases:
 145  -if SS enabled on DP Ref clock and HW de-spreading enabled with SW
 146  calculations for DS_INCR/DS_MODULO (this is planned to be default case)
 147  -if SS enabled on DP Ref clock and HW de-spreading enabled with HW
 148  calculations (not planned to be used, but average clock should still
 149  be valid)
 150  -if SS enabled on DP Ref clock and HW de-spreading disabled
 151  (should not be case with CIK) then SW should program all rates
 152  generated according to average value (case as with previous ASICs)
 153   */
 154 static int dccg_adjust_dp_ref_freq_for_ss(struct dce_dccg *clk_dce, int dp_ref_clk_khz)
 155 {
 156         if (clk_dce->ss_on_dprefclk && clk_dce->dprefclk_ss_divider != 0) {
 157                 struct fixed31_32 ss_percentage = dc_fixpt_div_int(
 158                                 dc_fixpt_from_fraction(clk_dce->dprefclk_ss_percentage,
 159                                                         clk_dce->dprefclk_ss_divider), 200);
 160                 struct fixed31_32 adj_dp_ref_clk_khz;
 161
 162                 ss_percentage = dc_fixpt_sub(dc_fixpt_one, ss_percentage);
 163                 adj_dp_ref_clk_khz = dc_fixpt_mul_int(ss_percentage, dp_ref_clk_khz);
 164                 dp_ref_clk_khz = dc_fixpt_floor(adj_dp_ref_clk_khz);
 165         }
 166         return dp_ref_clk_khz;
 167 }
 168
 169 static int dce_get_dp_ref_freq_khz(struct dccg *clk)
 170 {
 171         struct dce_dccg *clk_dce = TO_DCE_CLOCKS(clk);
 172         int dprefclk_wdivider;
 173         int dprefclk_src_sel;
 174         int dp_ref_clk_khz = 600000;
 175         int target_div;
 176
 177         /* ASSERT DP Reference Clock source is from DFS*/
 178         REG_GET(DPREFCLK_CNTL, DPREFCLK_SRC_SEL, &dprefclk_src_sel);
 179         ASSERT(dprefclk_src_sel == 0);
 180
 181         /* Read the mmDENTIST_DISPCLK_CNTL to get the currently
 182          * programmed DID DENTIST_DPREFCLK_WDIVIDER*/
 183         REG_GET(DENTIST_DISPCLK_CNTL, DENTIST_DPREFCLK_WDIVIDER, &dprefclk_wdivider);
 184
 185         /* Convert DENTIST_DPREFCLK_WDIVIDERto actual divider*/
 186         target_div = dentist_get_divider_from_did(dprefclk_wdivider);
 187
 188         /* Calculate the current DFS clock, in kHz.*/
 189         dp_ref_clk_khz = (DENTIST_DIVIDER_RANGE_SCALE_FACTOR
 190                 * clk_dce->dentist_vco_freq_khz) / target_div;
 191
 192         return dccg_adjust_dp_ref_freq_for_ss(clk_dce, dp_ref_clk_khz);
 193 }
 194
 195 static int dce12_get_dp_ref_freq_khz(struct dccg *clk)
 196 {
 197         struct dce_dccg *clk_dce = TO_DCE_CLOCKS(clk);
 198
 199         return dccg_adjust_dp_ref_freq_for_ss(clk_dce, 600000);
 200 }
 201
 202 static enum dm_pp_clocks_state dce_get_required_clocks_state(
 203         struct dccg *clk,
 204         struct dc_clocks *req_clocks)
 205 {
 206         struct dce_dccg *clk_dce = TO_DCE_CLOCKS(clk);
 207         int i;
 208         enum dm_pp_clocks_state low_req_clk;
 209
 210         /* Iterate from highest supported to lowest valid state, and update
 211          * lowest RequiredState with the lowest state that satisfies
 212          * all required clocks
 213          */
 214         for (i = clk->max_clks_state; i >= DM_PP_CLOCKS_STATE_ULTRA_LOW; i--)
 215                 if (req_clocks->dispclk_khz >
 216                                 clk_dce->max_clks_by_state[i].display_clk_khz
 217                         || req_clocks->phyclk_khz >
 218                                 clk_dce->max_clks_by_state[i].pixel_clk_khz)
 219                         break;
 220
 221         low_req_clk = i + 1;
 222         if (low_req_clk > clk->max_clks_state) {
 223                 /* set max clock state for high phyclock, invalid on exceeding display clock */
 224                 if (clk_dce->max_clks_by_state[clk->max_clks_state].display_clk_khz
 225                                 < req_clocks->dispclk_khz)
 226                         low_req_clk = DM_PP_CLOCKS_STATE_INVALID;
 227                 else
 228                         low_req_clk = clk->max_clks_state;
 229         }
 230
 231         return low_req_clk;
 232 }
 233
 234 static int dce_set_clock(
 235         struct dccg *clk,
 236         int requested_clk_khz)
 237 {
 238         struct dce_dccg *clk_dce = TO_DCE_CLOCKS(clk);
 239         struct bp_pixel_clock_parameters pxl_clk_params = { 0 };
 240         struct dc_bios *bp = clk->ctx->dc_bios;
 241         int actual_clock = requested_clk_khz;
 242
 243         /* Make sure requested clock isn't lower than minimum threshold*/
 244         if (requested_clk_khz > 0)
 245                 requested_clk_khz = max(requested_clk_khz,
 246                                 clk_dce->dentist_vco_freq_khz / 64);
 247
 248         /* Prepare to program display clock*/
 249         pxl_clk_params.target_pixel_clock = requested_clk_khz;
 250         pxl_clk_params.pll_id = CLOCK_SOURCE_ID_DFS;
 251
 252         bp->funcs->program_display_engine_pll(bp, &pxl_clk_params);
 253
 254         if (clk_dce->dfs_bypass_enabled) {
 255
 256                 /* Cache the fixed display clock*/
 257                 clk_dce->dfs_bypass_disp_clk =
 258                         pxl_clk_params.dfs_bypass_display_clock;
 259                 actual_clock = pxl_clk_params.dfs_bypass_display_clock;
 260         }
 261
 262         /* from power down, we need mark the clock state as ClocksStateNominal
 263          * from HWReset, so when resume we will call pplib voltage regulator.*/
 264         if (requested_clk_khz == 0)
 265                 clk->cur_min_clks_state = DM_PP_CLOCKS_STATE_NOMINAL;
 266         return actual_clock;
 267 }
 268
 269 static int dce_psr_set_clock(
 270         struct dccg *clk,
 271         int requested_clk_khz)
 272 {
 273         struct dce_dccg *clk_dce = TO_DCE_CLOCKS(clk);
 274         struct dc_context *ctx = clk_dce->base.ctx;
 275         struct dc *core_dc = ctx->dc;
 276         struct dmcu *dmcu = core_dc->res_pool->dmcu;
 277         int actual_clk_khz = requested_clk_khz;
 278
 279         actual_clk_khz = dce_set_clock(clk, requested_clk_khz);
 280
 281         dmcu->funcs->set_psr_wait_loop(dmcu, actual_clk_khz / 1000 / 7);
 282         return actual_clk_khz;
 283 }
 284
 285 static int dce112_set_clock(
 286         struct dccg *clk,
 287         int requested_clk_khz)
 288 {
 289         struct dce_dccg *clk_dce = TO_DCE_CLOCKS(clk);
 290         struct bp_set_dce_clock_parameters dce_clk_params;
 291         struct dc_bios *bp = clk->ctx->dc_bios;
 292         struct dc *core_dc = clk->ctx->dc;
 293         struct dmcu *dmcu = core_dc->res_pool->dmcu;
 294         int actual_clock = requested_clk_khz;
 295         /* Prepare to program display clock*/
 296         memset(&dce_clk_params, 0, sizeof(dce_clk_params));
 297
 298         /* Make sure requested clock isn't lower than minimum threshold*/
 299         if (requested_clk_khz > 0)
 300                 requested_clk_khz = max(requested_clk_khz,
 301                                 clk_dce->dentist_vco_freq_khz / 62);
 302
 303         dce_clk_params.target_clock_frequency = requested_clk_khz;
 304         dce_clk_params.pll_id = CLOCK_SOURCE_ID_DFS;
 305         dce_clk_params.clock_type = DCECLOCK_TYPE_DISPLAY_CLOCK;
 306
 307         bp->funcs->set_dce_clock(bp, &dce_clk_params);
 308         actual_clock = dce_clk_params.target_clock_frequency;
 309
 310         /* from power down, we need mark the clock state as ClocksStateNominal
 311          * from HWReset, so when resume we will call pplib voltage regulator.*/
 312         if (requested_clk_khz == 0)
 313                 clk->cur_min_clks_state = DM_PP_CLOCKS_STATE_NOMINAL;
 314
 315         /*Program DP ref Clock*/
 316         /*VBIOS will determine DPREFCLK frequency, so we don't set it*/
 317         dce_clk_params.target_clock_frequency = 0;
 318         dce_clk_params.clock_type = DCECLOCK_TYPE_DPREFCLK;
 319         if (!ASICREV_IS_VEGA20_P(clk->ctx->asic_id.hw_internal_rev))
 320                 dce_clk_params.flags.USE_GENLOCK_AS_SOURCE_FOR_DPREFCLK =
 321                         (dce_clk_params.pll_id ==
 322                                         CLOCK_SOURCE_COMBO_DISPLAY_PLL0);
 323         else
 324                 dce_clk_params.flags.USE_GENLOCK_AS_SOURCE_FOR_DPREFCLK = false;
 325
 326         bp->funcs->set_dce_clock(bp, &dce_clk_params);
 327
 328         if (!IS_FPGA_MAXIMUS_DC(core_dc->ctx->dce_environment)) {
 329                 if (clk_dce->dfs_bypass_disp_clk != actual_clock)
 330                         dmcu->funcs->set_psr_wait_loop(dmcu,
 331                                         actual_clock / 1000 / 7);
 332         }
 333
 334         clk_dce->dfs_bypass_disp_clk = actual_clock;
 335         return actual_clock;
 336 }
 337
 338 static void dce_clock_read_integrated_info(struct dce_dccg *clk_dce)
 339 {
 340         struct dc_debug_options *debug = &clk_dce->base.ctx->dc->debug;
 341         struct dc_bios *bp = clk_dce->base.ctx->dc_bios;
 342         struct integrated_info info = { { { 0 } } };
 343         struct dc_firmware_info fw_info = { { 0 } };
 344         int i;
 345
 346         if (bp->integrated_info)
 347                 info = *bp->integrated_info;
 348
 349         clk_dce->dentist_vco_freq_khz = info.dentist_vco_freq;
 350         if (clk_dce->dentist_vco_freq_khz == 0) {
 351                 bp->funcs->get_firmware_info(bp, &fw_info);
 352                 clk_dce->dentist_vco_freq_khz =
 353                         fw_info.smu_gpu_pll_output_freq;
 354                 if (clk_dce->dentist_vco_freq_khz == 0)
 355                         clk_dce->dentist_vco_freq_khz = 3600000;
 356         }
 357
 358         /*update the maximum display clock for each power state*/
 359         for (i = 0; i < NUMBER_OF_DISP_CLK_VOLTAGE; ++i) {
 360                 enum dm_pp_clocks_state clk_state = DM_PP_CLOCKS_STATE_INVALID;
 361
 362                 switch (i) {
 363                 case 0:
 364                         clk_state = DM_PP_CLOCKS_STATE_ULTRA_LOW;
 365                         break;
 366
 367                 case 1:
 368                         clk_state = DM_PP_CLOCKS_STATE_LOW;
 369                         break;
 370
 371                 case 2:
 372                         clk_state = DM_PP_CLOCKS_STATE_NOMINAL;
 373                         break;
 374
 375                 case 3:
 376                         clk_state = DM_PP_CLOCKS_STATE_PERFORMANCE;
 377                         break;
 378
 379                 default:
 380                         clk_state = DM_PP_CLOCKS_STATE_INVALID;
 381                         break;
 382                 }
 383
 384                 /*Do not allow bad VBIOS/SBIOS to override with invalid values,
 385                  * check for > 100MHz*/
 386                 if (info.disp_clk_voltage[i].max_supported_clk >= 100000)
 387                         clk_dce->max_clks_by_state[clk_state].display_clk_khz =
 388                                 info.disp_clk_voltage[i].max_supported_clk;
 389         }
 390
 391         if (!debug->disable_dfs_bypass && bp->integrated_info)
 392                 if (bp->integrated_info->gpu_cap_info & DFS_BYPASS_ENABLE)
 393                         clk_dce->dfs_bypass_enabled = true;
 394 }
 395
 396 static void dce_clock_read_ss_info(struct dce_dccg *clk_dce)
 397 {
 398         struct dc_bios *bp = clk_dce->base.ctx->dc_bios;
 399         int ss_info_num = bp->funcs->get_ss_entry_number(
 400                         bp, AS_SIGNAL_TYPE_GPU_PLL);
 401
 402         if (ss_info_num) {
 403                 struct spread_spectrum_info info = { { 0 } };
 404                 enum bp_result result = bp->funcs->get_spread_spectrum_info(
 405                                 bp, AS_SIGNAL_TYPE_GPU_PLL, 0, &info);
 406
 407                 /* Based on VBIOS, VBIOS will keep entry for GPU PLL SS
 408                  * even if SS not enabled and in that case
 409                  * SSInfo.spreadSpectrumPercentage !=0 would be sign
 410                  * that SS is enabled
 411                  */
 412                 if (result == BP_RESULT_OK &&
 413                                 info.spread_spectrum_percentage != 0) {
 414                         clk_dce->ss_on_dprefclk = true;
 415                         clk_dce->dprefclk_ss_divider = info.spread_percentage_divider;
 416
 417                         if (info.type.CENTER_MODE == 0) {
 418                                 /* TODO: Currently for DP Reference clock we
 419                                  * need only SS percentage for
 420                                  * downspread */
 421                                 clk_dce->dprefclk_ss_percentage =
 422                                                 info.spread_spectrum_percentage;
 423                         }
 424
 425                         return;
 426                 }
 427
 428                 result = bp->funcs->get_spread_spectrum_info(
 429                                 bp, AS_SIGNAL_TYPE_DISPLAY_PORT, 0, &info);
 430
 431                 /* Based on VBIOS, VBIOS will keep entry for DPREFCLK SS
 432                  * even if SS not enabled and in that case
 433                  * SSInfo.spreadSpectrumPercentage !=0 would be sign
 434                  * that SS is enabled
 435                  */
 436                 if (result == BP_RESULT_OK &&
 437                                 info.spread_spectrum_percentage != 0) {
 438                         clk_dce->ss_on_dprefclk = true;
 439                         clk_dce->dprefclk_ss_divider = info.spread_percentage_divider;
 440
 441                         if (info.type.CENTER_MODE == 0) {
 442                                 /* Currently for DP Reference clock we
 443                                  * need only SS percentage for
 444                                  * downspread */
 445                                 clk_dce->dprefclk_ss_percentage =
 446                                                 info.spread_spectrum_percentage;
 447                         }
 448                 }
 449         }
 450 }
 451
 452 static inline bool should_set_clock(bool safe_to_lower, int calc_clk, int cur_clk)
 453 {
 454         return ((safe_to_lower && calc_clk < cur_clk) || calc_clk > cur_clk);
 455 }
 456
 457 static void dce12_update_clocks(struct dccg *dccg,
 458                         struct dc_clocks *new_clocks,
 459                         bool safe_to_lower)
 460 {
 461         struct dm_pp_clock_for_voltage_req clock_voltage_req = {0};
 462
 463         if (should_set_clock(safe_to_lower, new_clocks->dispclk_khz, dccg->clks.dispclk_khz)) {
 464                 clock_voltage_req.clk_type = DM_PP_CLOCK_TYPE_DISPLAY_CLK;
 465                 clock_voltage_req.clocks_in_khz = new_clocks->dispclk_khz;
 466                 dccg->funcs->set_dispclk(dccg, new_clocks->dispclk_khz);
 467                 dccg->clks.dispclk_khz = new_clocks->dispclk_khz;
 468
 469                 dm_pp_apply_clock_for_voltage_request(dccg->ctx, &clock_voltage_req);
 470         }
 471
 472         if (should_set_clock(safe_to_lower, new_clocks->phyclk_khz, dccg->clks.phyclk_khz)) {
 473                 clock_voltage_req.clk_type = DM_PP_CLOCK_TYPE_DISPLAYPHYCLK;
 474                 clock_voltage_req.clocks_in_khz = new_clocks->phyclk_khz;
 475                 dccg->clks.phyclk_khz = new_clocks->phyclk_khz;
 476
 477                 dm_pp_apply_clock_for_voltage_request(dccg->ctx, &clock_voltage_req);
 478         }
 479 }
 480
 481 #ifdef CONFIG_X86
 482 static int dcn1_determine_dppclk_threshold(struct dccg *dccg, struct dc_clocks *new_clocks)
 483 {
 484         bool request_dpp_div = new_clocks->dispclk_khz > new_clocks->dppclk_khz;
 485         bool dispclk_increase = new_clocks->dispclk_khz > dccg->clks.dispclk_khz;
 486         int disp_clk_threshold = new_clocks->max_supported_dppclk_khz;
 487         bool cur_dpp_div = dccg->clks.dispclk_khz > dccg->clks.dppclk_khz;
 488
 489         /* increase clock, looking for div is 0 for current, request div is 1*/
 490         if (dispclk_increase) {
 491                 /* already divided by 2, no need to reach target clk with 2 steps*/
 492                 if (cur_dpp_div)
 493                         return new_clocks->dispclk_khz;
 494
 495                 /* request disp clk is lower than maximum supported dpp clk,
 496                  * no need to reach target clk with two steps.
 497                  */
 498                 if (new_clocks->dispclk_khz <= disp_clk_threshold)
 499                         return new_clocks->dispclk_khz;
 500
 501                 /* target dpp clk not request divided by 2, still within threshold */
 502                 if (!request_dpp_div)
 503                         return new_clocks->dispclk_khz;
 504
 505         } else {
 506                 /* decrease clock, looking for current dppclk divided by 2,
 507                  * request dppclk not divided by 2.
 508                  */
 509
 510                 /* current dpp clk not divided by 2, no need to ramp*/
 511                 if (!cur_dpp_div)
 512                         return new_clocks->dispclk_khz;
 513
 514                 /* current disp clk is lower than current maximum dpp clk,
 515                  * no need to ramp
 516                  */
 517                 if (dccg->clks.dispclk_khz <= disp_clk_threshold)
 518                         return new_clocks->dispclk_khz;
 519
 520                 /* request dpp clk need to be divided by 2 */
 521                 if (request_dpp_div)
 522                         return new_clocks->dispclk_khz;
 523         }
 524
 525         return disp_clk_threshold;
 526 }
 527
 528 static void dcn1_ramp_up_dispclk_with_dpp(struct dccg *dccg, struct dc_clocks *new_clocks)
 529 {
 530         struct dc *dc = dccg->ctx->dc;
 531         int dispclk_to_dpp_threshold = dcn1_determine_dppclk_threshold(dccg, new_clocks);
 532         bool request_dpp_div = new_clocks->dispclk_khz > new_clocks->dppclk_khz;
 533         int i;
 534
 535         /* set disp clk to dpp clk threshold */
 536         dccg->funcs->set_dispclk(dccg, dispclk_to_dpp_threshold);
 537
 538         /* update request dpp clk division option */
 539         for (i = 0; i < dc->res_pool->pipe_count; i++) {
 540                 struct pipe_ctx *pipe_ctx = &dc->current_state->res_ctx.pipe_ctx[i];
 541
 542                 if (!pipe_ctx->plane_state)
 543                         continue;
 544
 545                 pipe_ctx->plane_res.dpp->funcs->dpp_dppclk_control(
 546                                 pipe_ctx->plane_res.dpp,
 547                                 request_dpp_div,
 548                                 true);
 549         }
 550
 551         /* If target clk not same as dppclk threshold, set to target clock */
 552         if (dispclk_to_dpp_threshold != new_clocks->dispclk_khz)
 553                 dccg->funcs->set_dispclk(dccg, new_clocks->dispclk_khz);
 554
 555         dccg->clks.dispclk_khz = new_clocks->dispclk_khz;
 556         dccg->clks.dppclk_khz = new_clocks->dppclk_khz;
 557         dccg->clks.max_supported_dppclk_khz = new_clocks->max_supported_dppclk_khz;
 558 }
 559
 560 static void dcn1_update_clocks(struct dccg *dccg,
 561                         struct dc_clocks *new_clocks,
 562                         bool safe_to_lower)
 563 {
 564         struct dc *dc = dccg->ctx->dc;
 565         struct pp_smu_display_requirement_rv *smu_req_cur =
 566                         &dc->res_pool->pp_smu_req;
 567         struct pp_smu_display_requirement_rv smu_req = *smu_req_cur;
 568         struct pp_smu_funcs_rv *pp_smu = dc->res_pool->pp_smu;
 569         struct dm_pp_clock_for_voltage_req clock_voltage_req = {0};
 570         bool send_request_to_increase = false;
 571         bool send_request_to_lower = false;
 572
 573         if (new_clocks->phyclk_khz)
 574                 smu_req.display_count = 1;
 575         else
 576                 smu_req.display_count = 0;
 577
 578         if (new_clocks->dispclk_khz > dccg->clks.dispclk_khz
 579                         || new_clocks->phyclk_khz > dccg->clks.phyclk_khz
 580                         || new_clocks->fclk_khz > dccg->clks.fclk_khz
 581                         || new_clocks->dcfclk_khz > dccg->clks.dcfclk_khz)
 582                 send_request_to_increase = true;
 583
 584         if (should_set_clock(safe_to_lower, new_clocks->phyclk_khz, dccg->clks.phyclk_khz)) {
 585                 dccg->clks.phyclk_khz = new_clocks->phyclk_khz;
 586
 587                 send_request_to_lower = true;
 588         }
 589
 590         if (should_set_clock(safe_to_lower, new_clocks->fclk_khz, dccg->clks.fclk_khz)) {
 591                 dccg->clks.fclk_khz = new_clocks->fclk_khz;
 592                 clock_voltage_req.clk_type = DM_PP_CLOCK_TYPE_FCLK;
 593                 clock_voltage_req.clocks_in_khz = new_clocks->fclk_khz;
 594                 smu_req.hard_min_fclk_khz = new_clocks->fclk_khz;
 595
 596                 dm_pp_apply_clock_for_voltage_request(dccg->ctx, &clock_voltage_req);
 597                 send_request_to_lower = true;
 598         }
 599
 600         if (should_set_clock(safe_to_lower, new_clocks->dcfclk_khz, dccg->clks.dcfclk_khz)) {
 601                 dccg->clks.dcfclk_khz = new_clocks->dcfclk_khz;
 602                 smu_req.hard_min_dcefclk_khz = new_clocks->dcfclk_khz;
 603
 604                 send_request_to_lower = true;
 605         }
 606
 607         if (should_set_clock(safe_to_lower,
 608                         new_clocks->dcfclk_deep_sleep_khz, dccg->clks.dcfclk_deep_sleep_khz)) {
 609                 dccg->clks.dcfclk_deep_sleep_khz = new_clocks->dcfclk_deep_sleep_khz;
 610                 smu_req.min_deep_sleep_dcefclk_mhz = new_clocks->dcfclk_deep_sleep_khz;
 611
 612                 send_request_to_lower = true;
 613         }
 614
 615         /* make sure dcf clk is before dpp clk to
 616          * make sure we have enough voltage to run dpp clk
 617          */
 618         if (send_request_to_increase) {
 619                 /*use dcfclk to request voltage*/
 620                 clock_voltage_req.clk_type = DM_PP_CLOCK_TYPE_DCFCLK;
 621                 clock_voltage_req.clocks_in_khz = dcn_find_dcfclk_suits_all(dc, new_clocks);
 622                 dm_pp_apply_clock_for_voltage_request(dccg->ctx, &clock_voltage_req);
 623                 if (pp_smu->set_display_requirement)
 624                         pp_smu->set_display_requirement(&pp_smu->pp_smu, &smu_req);
 625         }
 626
 627         /* dcn1 dppclk is tied to dispclk */
 628         if (should_set_clock(safe_to_lower, new_clocks->dispclk_khz, dccg->clks.dispclk_khz)) {
 629                 dcn1_ramp_up_dispclk_with_dpp(dccg, new_clocks);
 630                 dccg->clks.dispclk_khz = new_clocks->dispclk_khz;
 631
 632                 send_request_to_lower = true;
 633         }
 634
 635         if (!send_request_to_increase && send_request_to_lower) {
 636                 /*use dcfclk to request voltage*/
 637                 clock_voltage_req.clk_type = DM_PP_CLOCK_TYPE_DCFCLK;
 638                 clock_voltage_req.clocks_in_khz = dcn_find_dcfclk_suits_all(dc, new_clocks);
 639                 dm_pp_apply_clock_for_voltage_request(dccg->ctx, &clock_voltage_req);
 640                 if (pp_smu->set_display_requirement)
 641                         pp_smu->set_display_requirement(&pp_smu->pp_smu, &smu_req);
 642         }
 643
 644
 645         *smu_req_cur = smu_req;
 646 }
 647 #endif
 648
 649 static void dce_update_clocks(struct dccg *dccg,
 650                         struct dc_clocks *new_clocks,
 651                         bool safe_to_lower)
 652 {
 653         struct dm_pp_power_level_change_request level_change_req;
 654
 655         level_change_req.power_level = dce_get_required_clocks_state(dccg, new_clocks);
 656         /* get max clock state from PPLIB */
 657         if ((level_change_req.power_level < dccg->cur_min_clks_state && safe_to_lower)
 658                         || level_change_req.power_level > dccg->cur_min_clks_state) {
 659                 if (dm_pp_apply_power_level_change_request(dccg->ctx, &level_change_req))
 660                         dccg->cur_min_clks_state = level_change_req.power_level;
 661         }
 662
 663         if (should_set_clock(safe_to_lower, new_clocks->dispclk_khz, dccg->clks.dispclk_khz)) {
 664                 dccg->funcs->set_dispclk(dccg, new_clocks->dispclk_khz);
 665                 dccg->clks.dispclk_khz = new_clocks->dispclk_khz;
 666         }
 667 }
 668
 669 #ifdef CONFIG_X86
 670 static const struct display_clock_funcs dcn1_funcs = {
 671         .get_dp_ref_clk_frequency = dce12_get_dp_ref_freq_khz,
 672         .set_dispclk = dce112_set_clock,
 673         .update_clocks = dcn1_update_clocks
 674 };
 675 #endif
 676
 677 static const struct display_clock_funcs dce120_funcs = {
 678         .get_dp_ref_clk_frequency = dce12_get_dp_ref_freq_khz,
 679         .set_dispclk = dce112_set_clock,
 680         .update_clocks = dce12_update_clocks
 681 };
 682
 683 static const struct display_clock_funcs dce112_funcs = {
 684         .get_dp_ref_clk_frequency = dce_get_dp_ref_freq_khz,
 685         .set_dispclk = dce112_set_clock,
 686         .update_clocks = dce_update_clocks
 687 };
 688
 689 static const struct display_clock_funcs dce110_funcs = {
 690         .get_dp_ref_clk_frequency = dce_get_dp_ref_freq_khz,
 691         .set_dispclk = dce_psr_set_clock,
 692         .update_clocks = dce_update_clocks
 693 };
 694
 695 static const struct display_clock_funcs dce_funcs = {
 696         .get_dp_ref_clk_frequency = dce_get_dp_ref_freq_khz,
 697         .set_dispclk = dce_set_clock,
 698         .update_clocks = dce_update_clocks
 699 };
 700
 701 static void dce_dccg_construct(
 702         struct dce_dccg *clk_dce,
 703         struct dc_context *ctx,
 704         const struct dccg_registers *regs,
 705         const struct dccg_shift *clk_shift,
 706         const struct dccg_mask *clk_mask)
 707 {
 708         struct dccg *base = &clk_dce->base;
 709
 710         base->ctx = ctx;
 711         base->funcs = &dce_funcs;
 712
 713         clk_dce->regs = regs;
 714         clk_dce->clk_shift = clk_shift;
 715         clk_dce->clk_mask = clk_mask;
 716
 717         clk_dce->dfs_bypass_disp_clk = 0;
 718
 719         clk_dce->dprefclk_ss_percentage = 0;
 720         clk_dce->dprefclk_ss_divider = 1000;
 721         clk_dce->ss_on_dprefclk = false;
 722
 723         base->max_clks_state = DM_PP_CLOCKS_STATE_NOMINAL;
 724         base->cur_min_clks_state = DM_PP_CLOCKS_STATE_INVALID;
 725
 726         dce_clock_read_integrated_info(clk_dce);
 727         dce_clock_read_ss_info(clk_dce);
 728 }
 729
 730 struct dccg *dce_dccg_create(
 731         struct dc_context *ctx,
 732         const struct dccg_registers *regs,
 733         const struct dccg_shift *clk_shift,
 734         const struct dccg_mask *clk_mask)
 735 {
 736         struct dce_dccg *clk_dce = kzalloc(sizeof(*clk_dce), GFP_KERNEL);
 737
 738         if (clk_dce == NULL) {
 739                 BREAK_TO_DEBUGGER();
 740                 return NULL;
 741         }
 742
 743         memcpy(clk_dce->max_clks_by_state,
 744                 dce80_max_clks_by_state,
 745                 sizeof(dce80_max_clks_by_state));
 746
 747         dce_dccg_construct(
 748                 clk_dce, ctx, regs, clk_shift, clk_mask);
 749
 750         return &clk_dce->base;
 751 }
 752
 753 struct dccg *dce110_dccg_create(
 754         struct dc_context *ctx,
 755         const struct dccg_registers *regs,
 756         const struct dccg_shift *clk_shift,
 757         const struct dccg_mask *clk_mask)
 758 {
 759         struct dce_dccg *clk_dce = kzalloc(sizeof(*clk_dce), GFP_KERNEL);
 760
 761         if (clk_dce == NULL) {
 762                 BREAK_TO_DEBUGGER();
 763                 return NULL;
 764         }
 765
 766         memcpy(clk_dce->max_clks_by_state,
 767                 dce110_max_clks_by_state,
 768                 sizeof(dce110_max_clks_by_state));
 769
 770         dce_dccg_construct(
 771                 clk_dce, ctx, regs, clk_shift, clk_mask);
 772
 773         clk_dce->base.funcs = &dce110_funcs;
 774
 775         return &clk_dce->base;
 776 }
 777
 778 struct dccg *dce112_dccg_create(
 779         struct dc_context *ctx,
 780         const struct dccg_registers *regs,
 781         const struct dccg_shift *clk_shift,
 782         const struct dccg_mask *clk_mask)
 783 {
 784         struct dce_dccg *clk_dce = kzalloc(sizeof(*clk_dce), GFP_KERNEL);
 785
 786         if (clk_dce == NULL) {
 787                 BREAK_TO_DEBUGGER();
 788                 return NULL;
 789         }
 790
 791         memcpy(clk_dce->max_clks_by_state,
 792                 dce112_max_clks_by_state,
 793                 sizeof(dce112_max_clks_by_state));
 794
 795         dce_dccg_construct(
 796                 clk_dce, ctx, regs, clk_shift, clk_mask);
 797
 798         clk_dce->base.funcs = &dce112_funcs;
 799
 800         return &clk_dce->base;
 801 }
 802
 803 struct dccg *dce120_dccg_create(struct dc_context *ctx)
 804 {
 805         struct dce_dccg *clk_dce = kzalloc(sizeof(*clk_dce), GFP_KERNEL);
 806
 807         if (clk_dce == NULL) {
 808                 BREAK_TO_DEBUGGER();
 809                 return NULL;
 810         }
 811
 812         memcpy(clk_dce->max_clks_by_state,
 813                 dce120_max_clks_by_state,
 814                 sizeof(dce120_max_clks_by_state));
 815
 816         dce_dccg_construct(
 817                 clk_dce, ctx, NULL, NULL, NULL);
 818
 819         clk_dce->base.funcs = &dce120_funcs;
 820
 821         return &clk_dce->base;
 822 }
 823
 824 #ifdef CONFIG_X86
 825 struct dccg *dcn1_dccg_create(struct dc_context *ctx)
 826 {
 827         struct dc_debug_options *debug = &ctx->dc->debug;
 828         struct dc_bios *bp = ctx->dc_bios;
 829         struct dc_firmware_info fw_info = { { 0 } };
 830         struct dce_dccg *clk_dce = kzalloc(sizeof(*clk_dce), GFP_KERNEL);
 831
 832         if (clk_dce == NULL) {
 833                 BREAK_TO_DEBUGGER();
 834                 return NULL;
 835         }
 836
 837         clk_dce->base.ctx = ctx;
 838         clk_dce->base.funcs = &dcn1_funcs;
 839
 840         clk_dce->dfs_bypass_disp_clk = 0;
 841
 842         clk_dce->dprefclk_ss_percentage = 0;
 843         clk_dce->dprefclk_ss_divider = 1000;
 844         clk_dce->ss_on_dprefclk = false;
 845
 846         if (bp->integrated_info)
 847                 clk_dce->dentist_vco_freq_khz = bp->integrated_info->dentist_vco_freq;
 848         if (clk_dce->dentist_vco_freq_khz == 0) {
 849                 bp->funcs->get_firmware_info(bp, &fw_info);
 850                 clk_dce->dentist_vco_freq_khz = fw_info.smu_gpu_pll_output_freq;
 851                 if (clk_dce->dentist_vco_freq_khz == 0)
 852                         clk_dce->dentist_vco_freq_khz = 3600000;
 853         }
 854
 855         if (!debug->disable_dfs_bypass && bp->integrated_info)
 856                 if (bp->integrated_info->gpu_cap_info & DFS_BYPASS_ENABLE)
 857                         clk_dce->dfs_bypass_enabled = true;
 858
 859         dce_clock_read_ss_info(clk_dce);
 860
 861         return &clk_dce->base;
 862 }
 863 #endif
 864
 865 void dce_dccg_destroy(struct dccg **dccg)
 866 {
 867         struct dce_dccg *clk_dce = TO_DCE_CLOCKS(*dccg);
 868
 869         kfree(clk_dce);
 870         *dccg = NULL;
 871 }