2 * Copyright 2012-16 Advanced Micro Devices, Inc.
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5 * copy of this software and associated documentation files (the "Software"),
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9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
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27 #ifndef _DCE_CLOCKS_H_
28 #define _DCE_CLOCKS_H_
30 #include "display_clock.h"
32 #define CLK_COMMON_REG_LIST_DCE_BASE() \
33 .DPREFCLK_CNTL = mmDPREFCLK_CNTL, \
34 .DENTIST_DISPCLK_CNTL = mmDENTIST_DISPCLK_CNTL
36 #define CLK_SF(reg_name, field_name, post_fix)\
37 .field_name = reg_name ## __ ## field_name ## post_fix
39 #define CLK_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(mask_sh) \
40 CLK_SF(DPREFCLK_CNTL, DPREFCLK_SRC_SEL, mask_sh), \
41 CLK_SF(DENTIST_DISPCLK_CNTL, DENTIST_DPREFCLK_WDIVIDER, mask_sh)
43 #define CLK_REG_FIELD_LIST(type) \
44 type DPREFCLK_SRC_SEL; \
45 type DENTIST_DPREFCLK_WDIVIDER;
47 struct dce_disp_clk_shift {
48 CLK_REG_FIELD_LIST(uint8_t)
51 struct dce_disp_clk_mask {
52 CLK_REG_FIELD_LIST(uint32_t)
55 struct dce_disp_clk_registers {
56 uint32_t DPREFCLK_CNTL;
57 uint32_t DENTIST_DISPCLK_CNTL;
60 /* Array identifiers and count for the divider ranges.*/
61 enum dce_divider_range_count {
65 DIVIDER_RANGE_MAX /* == 3*/
68 enum dce_divider_error_types {
73 struct dce_divider_range {
75 /* The end of this range of dividers.*/
77 /* The distance between each divider in this range.*/
79 /* The divider id for the lowest divider.*/
81 /* The divider id for the highest divider.*/
86 struct display_clock base;
87 const struct dce_disp_clk_registers *regs;
88 const struct dce_disp_clk_shift *clk_shift;
89 const struct dce_disp_clk_mask *clk_mask;
91 struct state_dependent_clocks max_clks_by_state[DM_PP_CLOCKS_MAX_STATES];
92 struct dce_divider_range divider_ranges[DIVIDER_RANGE_MAX];
94 bool use_max_disp_clk;
95 int dentist_vco_freq_khz;
97 /* Cache the status of DFS-bypass feature*/
98 bool dfs_bypass_enabled;
99 /* Cache the display clock returned by VBIOS if DFS-bypass is enabled.
100 * This is basically "Crystal Frequency In KHz" (XTALIN) frequency */
101 int dfs_bypass_disp_clk;
103 /* Flag for Enabled SS on DPREFCLK */
105 /* DPREFCLK SS percentage (if down-spread enabled) */
106 int dprefclk_ss_percentage;
107 /* DPREFCLK SS percentage Divider (100 or 1000) */
108 int dprefclk_ss_divider;
110 /* max disp_clk from PPLIB for max validation display clock*/
111 int max_displ_clk_in_khz;
115 struct display_clock *dce_disp_clk_create(
116 struct dc_context *ctx,
117 const struct dce_disp_clk_registers *regs,
118 const struct dce_disp_clk_shift *clk_shift,
119 const struct dce_disp_clk_mask *clk_mask);
121 struct display_clock *dce110_disp_clk_create(
122 struct dc_context *ctx,
123 const struct dce_disp_clk_registers *regs,
124 const struct dce_disp_clk_shift *clk_shift,
125 const struct dce_disp_clk_mask *clk_mask);
127 struct display_clock *dce112_disp_clk_create(
128 struct dc_context *ctx,
129 const struct dce_disp_clk_registers *regs,
130 const struct dce_disp_clk_shift *clk_shift,
131 const struct dce_disp_clk_mask *clk_mask);
133 struct display_clock *dce120_disp_clk_create(struct dc_context *ctx);
135 void dce_disp_clk_destroy(struct display_clock **disp_clk);
137 #endif /* _DCE_CLOCKS_H_ */