drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c

   1 /*
   2  * Copyright 2012-16 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: AMD
  23  *
  24  */
  25
  26 #include "core_types.h"
  27 #include "link_encoder.h"
  28 #include "dce_dmcu.h"
  29 #include "dm_services.h"
  30 #include "reg_helper.h"
  31 #include "fixed31_32.h"
  32 #include "dc.h"
  33
  34 #define TO_DCE_DMCU(dmcu)\
  35         container_of(dmcu, struct dce_dmcu, base)
  36
  37 #define REG(reg) \
  38         (dmcu_dce->regs->reg)
  39
  40 #undef FN
  41 #define FN(reg_name, field_name) \
  42         dmcu_dce->dmcu_shift->field_name, dmcu_dce->dmcu_mask->field_name
  43
  44 #define CTX \
  45         dmcu_dce->base.ctx
  46
  47 /* PSR related commands */
  48 #define PSR_ENABLE 0x20
  49 #define PSR_EXIT 0x21
  50 #define PSR_SET 0x23
  51 #define PSR_SET_WAITLOOP 0x31
  52 #define MCP_INIT_DMCU 0x88
  53 #define MCP_INIT_IRAM 0x89
  54 #define MCP_DMCU_VERSION 0x90
  55 #define MASTER_COMM_CNTL_REG__MASTER_COMM_INTERRUPT_MASK   0x00000001L
  56
  57 static bool dce_dmcu_init(struct dmcu *dmcu)
  58 {
  59         // Do nothing
  60         return true;
  61 }
  62
  63 bool dce_dmcu_load_iram(struct dmcu *dmcu,
  64                 unsigned int start_offset,
  65                 const char *src,
  66                 unsigned int bytes)
  67 {
  68         struct dce_dmcu *dmcu_dce = TO_DCE_DMCU(dmcu);
  69         unsigned int count = 0;
  70
  71         /* Enable write access to IRAM */
  72         REG_UPDATE_2(DMCU_RAM_ACCESS_CTRL,
  73                         IRAM_HOST_ACCESS_EN, 1,
  74                         IRAM_WR_ADDR_AUTO_INC, 1);
  75
  76         REG_WAIT(DCI_MEM_PWR_STATUS, DMCU_IRAM_MEM_PWR_STATE, 0, 2, 10);
  77
  78         REG_WRITE(DMCU_IRAM_WR_CTRL, start_offset);
  79
  80         for (count = 0; count < bytes; count++)
  81                 REG_WRITE(DMCU_IRAM_WR_DATA, src[count]);
  82
  83         /* Disable write access to IRAM to allow dynamic sleep state */
  84         REG_UPDATE_2(DMCU_RAM_ACCESS_CTRL,
  85                         IRAM_HOST_ACCESS_EN, 0,
  86                         IRAM_WR_ADDR_AUTO_INC, 0);
  87
  88         return true;
  89 }
  90
  91 static void dce_get_dmcu_psr_state(struct dmcu *dmcu, uint32_t *psr_state)
  92 {
  93         struct dce_dmcu *dmcu_dce = TO_DCE_DMCU(dmcu);
  94
  95         uint32_t psr_state_offset = 0xf0;
  96
  97         /* Enable write access to IRAM */
  98         REG_UPDATE(DMCU_RAM_ACCESS_CTRL, IRAM_HOST_ACCESS_EN, 1);
  99
 100         REG_WAIT(DCI_MEM_PWR_STATUS, DMCU_IRAM_MEM_PWR_STATE, 0, 2, 10);
 101
 102         /* Write address to IRAM_RD_ADDR in DMCU_IRAM_RD_CTRL */
 103         REG_WRITE(DMCU_IRAM_RD_CTRL, psr_state_offset);
 104
 105         /* Read data from IRAM_RD_DATA in DMCU_IRAM_RD_DATA*/
 106         *psr_state = REG_READ(DMCU_IRAM_RD_DATA);
 107
 108         /* Disable write access to IRAM after finished using IRAM
 109          * in order to allow dynamic sleep state
 110          */
 111         REG_UPDATE(DMCU_RAM_ACCESS_CTRL, IRAM_HOST_ACCESS_EN, 0);
 112 }
 113
 114 static void dce_dmcu_set_psr_enable(struct dmcu *dmcu, bool enable, bool wait)
 115 {
 116         struct dce_dmcu *dmcu_dce = TO_DCE_DMCU(dmcu);
 117         unsigned int dmcu_max_retry_on_wait_reg_ready = 801;
 118         unsigned int dmcu_wait_reg_ready_interval = 100;
 119
 120         unsigned int retryCount;
 121         uint32_t psr_state = 0;
 122
 123         /* waitDMCUReadyForCmd */
 124         REG_WAIT(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 0,
 125                                 dmcu_wait_reg_ready_interval,
 126                                 dmcu_max_retry_on_wait_reg_ready);
 127
 128         /* setDMCUParam_Cmd */
 129         if (enable)
 130                 REG_UPDATE(MASTER_COMM_CMD_REG, MASTER_COMM_CMD_REG_BYTE0,
 131                                 PSR_ENABLE);
 132         else
 133                 REG_UPDATE(MASTER_COMM_CMD_REG, MASTER_COMM_CMD_REG_BYTE0,
 134                                 PSR_EXIT);
 135
 136         /* notifyDMCUMsg */
 137         REG_UPDATE(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 1);
 138         if (wait == true) {
 139                 for (retryCount = 0; retryCount <= 100; retryCount++) {
 140                         dce_get_dmcu_psr_state(dmcu, &psr_state);
 141                         if (enable) {
 142                                 if (psr_state != 0)
 143                                         break;
 144                         } else {
 145                                 if (psr_state == 0)
 146                                         break;
 147                         }
 148                         udelay(10);
 149                 }
 150         }
 151 }
 152
 153 static void dce_dmcu_setup_psr(struct dmcu *dmcu,
 154                 struct dc_link *link,
 155                 struct psr_context *psr_context)
 156 {
 157         struct dce_dmcu *dmcu_dce = TO_DCE_DMCU(dmcu);
 158
 159         unsigned int dmcu_max_retry_on_wait_reg_ready = 801;
 160         unsigned int dmcu_wait_reg_ready_interval = 100;
 161
 162         union dce_dmcu_psr_config_data_reg1 masterCmdData1;
 163         union dce_dmcu_psr_config_data_reg2 masterCmdData2;
 164         union dce_dmcu_psr_config_data_reg3 masterCmdData3;
 165
 166         link->link_enc->funcs->psr_program_dp_dphy_fast_training(link->link_enc,
 167                         psr_context->psrExitLinkTrainingRequired);
 168
 169         /* Enable static screen interrupts for PSR supported display */
 170         /* Disable the interrupt coming from other displays. */
 171         REG_UPDATE_4(DMCU_INTERRUPT_TO_UC_EN_MASK,
 172                         STATIC_SCREEN1_INT_TO_UC_EN, 0,
 173                         STATIC_SCREEN2_INT_TO_UC_EN, 0,
 174                         STATIC_SCREEN3_INT_TO_UC_EN, 0,
 175                         STATIC_SCREEN4_INT_TO_UC_EN, 0);
 176
 177         switch (psr_context->controllerId) {
 178         /* Driver uses case 1 for unconfigured */
 179         case 1:
 180                 REG_UPDATE(DMCU_INTERRUPT_TO_UC_EN_MASK,
 181                                 STATIC_SCREEN1_INT_TO_UC_EN, 1);
 182                 break;
 183         case 2:
 184                 REG_UPDATE(DMCU_INTERRUPT_TO_UC_EN_MASK,
 185                                 STATIC_SCREEN2_INT_TO_UC_EN, 1);
 186                 break;
 187         case 3:
 188                 REG_UPDATE(DMCU_INTERRUPT_TO_UC_EN_MASK,
 189                                 STATIC_SCREEN3_INT_TO_UC_EN, 1);
 190                 break;
 191         case 4:
 192                 REG_UPDATE(DMCU_INTERRUPT_TO_UC_EN_MASK,
 193                                 STATIC_SCREEN4_INT_TO_UC_EN, 1);
 194                 break;
 195         case 5:
 196                 /* CZ/NL only has 4 CRTC!!
 197                  * really valid.
 198                  * There is no interrupt enable mask for these instances.
 199                  */
 200                 break;
 201         case 6:
 202                 /* CZ/NL only has 4 CRTC!!
 203                  * These are here because they are defined in HW regspec,
 204                  * but not really valid. There is no interrupt enable mask
 205                  * for these instances.
 206                  */
 207                 break;
 208         default:
 209                 REG_UPDATE(DMCU_INTERRUPT_TO_UC_EN_MASK,
 210                                 STATIC_SCREEN1_INT_TO_UC_EN, 1);
 211                 break;
 212         }
 213
 214         link->link_enc->funcs->psr_program_secondary_packet(link->link_enc,
 215                         psr_context->sdpTransmitLineNumDeadline);
 216
 217         if (psr_context->psr_level.bits.SKIP_SMU_NOTIFICATION)
 218                 REG_UPDATE(SMU_INTERRUPT_CONTROL, DC_SMU_INT_ENABLE, 1);
 219
 220         /* waitDMCUReadyForCmd */
 221         REG_WAIT(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 0,
 222                                         dmcu_wait_reg_ready_interval,
 223                                         dmcu_max_retry_on_wait_reg_ready);
 224
 225         /* setDMCUParam_PSRHostConfigData */
 226         masterCmdData1.u32All = 0;
 227         masterCmdData1.bits.timehyst_frames = psr_context->timehyst_frames;
 228         masterCmdData1.bits.hyst_lines = psr_context->hyst_lines;
 229         masterCmdData1.bits.rfb_update_auto_en =
 230                         psr_context->rfb_update_auto_en;
 231         masterCmdData1.bits.dp_port_num = psr_context->transmitterId;
 232         masterCmdData1.bits.dcp_sel = psr_context->controllerId;
 233         masterCmdData1.bits.phy_type  = psr_context->phyType;
 234         masterCmdData1.bits.frame_cap_ind =
 235                         psr_context->psrFrameCaptureIndicationReq;
 236         masterCmdData1.bits.aux_chan = psr_context->channel;
 237         masterCmdData1.bits.aux_repeat = psr_context->aux_repeats;
 238         dm_write_reg(dmcu->ctx, REG(MASTER_COMM_DATA_REG1),
 239                                         masterCmdData1.u32All);
 240
 241         masterCmdData2.u32All = 0;
 242         masterCmdData2.bits.dig_fe = psr_context->engineId;
 243         masterCmdData2.bits.dig_be = psr_context->transmitterId;
 244         masterCmdData2.bits.skip_wait_for_pll_lock =
 245                         psr_context->skipPsrWaitForPllLock;
 246         masterCmdData2.bits.frame_delay = psr_context->frame_delay;
 247         masterCmdData2.bits.smu_phy_id = psr_context->smuPhyId;
 248         masterCmdData2.bits.num_of_controllers =
 249                         psr_context->numberOfControllers;
 250         dm_write_reg(dmcu->ctx, REG(MASTER_COMM_DATA_REG2),
 251                         masterCmdData2.u32All);
 252
 253         masterCmdData3.u32All = 0;
 254         masterCmdData3.bits.psr_level = psr_context->psr_level.u32all;
 255         dm_write_reg(dmcu->ctx, REG(MASTER_COMM_DATA_REG3),
 256                         masterCmdData3.u32All);
 257
 258         /* setDMCUParam_Cmd */
 259         REG_UPDATE(MASTER_COMM_CMD_REG,
 260                         MASTER_COMM_CMD_REG_BYTE0, PSR_SET);
 261
 262         /* notifyDMCUMsg */
 263         REG_UPDATE(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 1);
 264 }
 265
 266 static bool dce_is_dmcu_initialized(struct dmcu *dmcu)
 267 {
 268         struct dce_dmcu *dmcu_dce = TO_DCE_DMCU(dmcu);
 269         unsigned int dmcu_uc_reset;
 270
 271         /* microcontroller is not running */
 272         REG_GET(DMCU_STATUS, UC_IN_RESET, &dmcu_uc_reset);
 273
 274         /* DMCU is not running */
 275         if (dmcu_uc_reset)
 276                 return false;
 277
 278         return true;
 279 }
 280
 281 static void dce_psr_wait_loop(
 282         struct dmcu *dmcu,
 283         unsigned int wait_loop_number)
 284 {
 285         struct dce_dmcu *dmcu_dce = TO_DCE_DMCU(dmcu);
 286         union dce_dmcu_psr_config_data_wait_loop_reg1 masterCmdData1;
 287
 288         if (dmcu->cached_wait_loop_number == wait_loop_number)
 289                 return;
 290
 291         /* DMCU is not running */
 292         if (!dce_is_dmcu_initialized(dmcu))
 293                 return;
 294
 295         /* waitDMCUReadyForCmd */
 296         REG_WAIT(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 0, 1, 10000);
 297
 298         masterCmdData1.u32 = 0;
 299         masterCmdData1.bits.wait_loop = wait_loop_number;
 300         dmcu->cached_wait_loop_number = wait_loop_number;
 301         dm_write_reg(dmcu->ctx, REG(MASTER_COMM_DATA_REG1), masterCmdData1.u32);
 302
 303         /* setDMCUParam_Cmd */
 304         REG_UPDATE(MASTER_COMM_CMD_REG, MASTER_COMM_CMD_REG_BYTE0, PSR_SET_WAITLOOP);
 305
 306         /* notifyDMCUMsg */
 307         REG_UPDATE(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 1);
 308 }
 309
 310 static void dce_get_psr_wait_loop(
 311                 struct dmcu *dmcu, unsigned int *psr_wait_loop_number)
 312 {
 313         *psr_wait_loop_number = dmcu->cached_wait_loop_number;
 314         return;
 315 }
 316
 317 #ifdef CONFIG_X86
 318 static void dcn10_get_dmcu_state(struct dmcu *dmcu)
 319 {
 320         struct dce_dmcu *dmcu_dce = TO_DCE_DMCU(dmcu);
 321         uint32_t dmcu_state_offset = 0xf6;
 322
 323         /* Enable write access to IRAM */
 324         REG_UPDATE_2(DMCU_RAM_ACCESS_CTRL,
 325                         IRAM_HOST_ACCESS_EN, 1,
 326                         IRAM_RD_ADDR_AUTO_INC, 1);
 327
 328         REG_WAIT(DMU_MEM_PWR_CNTL, DMCU_IRAM_MEM_PWR_STATE, 0, 2, 10);
 329
 330         /* Write address to IRAM_RD_ADDR in DMCU_IRAM_RD_CTRL */
 331         REG_WRITE(DMCU_IRAM_RD_CTRL, dmcu_state_offset);
 332
 333         /* Read data from IRAM_RD_DATA in DMCU_IRAM_RD_DATA*/
 334         dmcu->dmcu_state = REG_READ(DMCU_IRAM_RD_DATA);
 335
 336         /* Disable write access to IRAM to allow dynamic sleep state */
 337         REG_UPDATE_2(DMCU_RAM_ACCESS_CTRL,
 338                         IRAM_HOST_ACCESS_EN, 0,
 339                         IRAM_RD_ADDR_AUTO_INC, 0);
 340 }
 341
 342 static void dcn10_get_dmcu_version(struct dmcu *dmcu)
 343 {
 344         struct dce_dmcu *dmcu_dce = TO_DCE_DMCU(dmcu);
 345         uint32_t dmcu_version_offset = 0xf1;
 346
 347         /* Clear scratch */
 348         REG_WRITE(DC_DMCU_SCRATCH, 0);
 349
 350         /* Enable write access to IRAM */
 351         REG_UPDATE_2(DMCU_RAM_ACCESS_CTRL,
 352                         IRAM_HOST_ACCESS_EN, 1,
 353                         IRAM_RD_ADDR_AUTO_INC, 1);
 354
 355         REG_WAIT(DMU_MEM_PWR_CNTL, DMCU_IRAM_MEM_PWR_STATE, 0, 2, 10);
 356
 357         /* Write address to IRAM_RD_ADDR and read from DATA register */
 358         REG_WRITE(DMCU_IRAM_RD_CTRL, dmcu_version_offset);
 359         dmcu->dmcu_version.interface_version = REG_READ(DMCU_IRAM_RD_DATA);
 360         dmcu->dmcu_version.year = ((REG_READ(DMCU_IRAM_RD_DATA) << 8) |
 361                                                 REG_READ(DMCU_IRAM_RD_DATA));
 362         dmcu->dmcu_version.month = REG_READ(DMCU_IRAM_RD_DATA);
 363         dmcu->dmcu_version.date = REG_READ(DMCU_IRAM_RD_DATA);
 364
 365         /* Disable write access to IRAM to allow dynamic sleep state */
 366         REG_UPDATE_2(DMCU_RAM_ACCESS_CTRL,
 367                         IRAM_HOST_ACCESS_EN, 0,
 368                         IRAM_RD_ADDR_AUTO_INC, 0);
 369
 370         /* Send MCP command message to DMCU to get version reply from FW.
 371          * We expect this version should match the one in IRAM, otherwise
 372          * something is wrong with DMCU and we should fail and disable UC.
 373          */
 374         REG_WAIT(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 0, 100, 800);
 375
 376         /* Set command to get DMCU version from microcontroller */
 377         REG_UPDATE(MASTER_COMM_CMD_REG, MASTER_COMM_CMD_REG_BYTE0,
 378                         MCP_DMCU_VERSION);
 379
 380         /* Notify microcontroller of new command */
 381         REG_UPDATE(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 1);
 382
 383         /* Ensure command has been executed before continuing */
 384         REG_WAIT(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 0, 100, 800);
 385
 386         /* Somehow version does not match, so fail and return version 0 */
 387         if (dmcu->dmcu_version.interface_version != REG_READ(DC_DMCU_SCRATCH))
 388                 dmcu->dmcu_version.interface_version = 0;
 389 }
 390
 391 static bool dcn10_dmcu_init(struct dmcu *dmcu)
 392 {
 393         struct dce_dmcu *dmcu_dce = TO_DCE_DMCU(dmcu);
 394
 395         /* DMCU FW should populate the scratch register if running */
 396         if (REG_READ(DC_DMCU_SCRATCH) == 0)
 397                 return false;
 398
 399         /* Check state is uninitialized */
 400         dcn10_get_dmcu_state(dmcu);
 401
 402         /* If microcontroller is already initialized, do nothing */
 403         if (dmcu->dmcu_state == DMCU_RUNNING)
 404                 return true;
 405
 406         /* Retrieve and cache the DMCU firmware version. */
 407         dcn10_get_dmcu_version(dmcu);
 408
 409         /* Check interface version to confirm firmware is loaded and running */
 410         if (dmcu->dmcu_version.interface_version == 0)
 411                 return false;
 412
 413         /* Wait until microcontroller is ready to process interrupt */
 414         REG_WAIT(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 0, 100, 800);
 415
 416         /* Set initialized ramping boundary value */
 417         REG_WRITE(MASTER_COMM_DATA_REG1, 0xFFFF);
 418
 419         /* Set command to initialize microcontroller */
 420         REG_UPDATE(MASTER_COMM_CMD_REG, MASTER_COMM_CMD_REG_BYTE0,
 421                         MCP_INIT_DMCU);
 422
 423         /* Notify microcontroller of new command */
 424         REG_UPDATE(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 1);
 425
 426         /* Ensure command has been executed before continuing */
 427         REG_WAIT(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 0, 100, 800);
 428
 429         // Check state is initialized
 430         dcn10_get_dmcu_state(dmcu);
 431
 432         // If microcontroller is not in running state, fail
 433         if (dmcu->dmcu_state != DMCU_RUNNING)
 434                 return false;
 435
 436         return true;
 437 }
 438
 439 static bool dcn10_dmcu_load_iram(struct dmcu *dmcu,
 440                 unsigned int start_offset,
 441                 const char *src,
 442                 unsigned int bytes)
 443 {
 444         struct dce_dmcu *dmcu_dce = TO_DCE_DMCU(dmcu);
 445         unsigned int count = 0;
 446
 447         /* If microcontroller is not running, do nothing */
 448         if (dmcu->dmcu_state != DMCU_RUNNING)
 449                 return false;
 450
 451         /* Enable write access to IRAM */
 452         REG_UPDATE_2(DMCU_RAM_ACCESS_CTRL,
 453                         IRAM_HOST_ACCESS_EN, 1,
 454                         IRAM_WR_ADDR_AUTO_INC, 1);
 455
 456         REG_WAIT(DMU_MEM_PWR_CNTL, DMCU_IRAM_MEM_PWR_STATE, 0, 2, 10);
 457
 458         REG_WRITE(DMCU_IRAM_WR_CTRL, start_offset);
 459
 460         for (count = 0; count < bytes; count++)
 461                 REG_WRITE(DMCU_IRAM_WR_DATA, src[count]);
 462
 463         /* Disable write access to IRAM to allow dynamic sleep state */
 464         REG_UPDATE_2(DMCU_RAM_ACCESS_CTRL,
 465                         IRAM_HOST_ACCESS_EN, 0,
 466                         IRAM_WR_ADDR_AUTO_INC, 0);
 467
 468         /* Wait until microcontroller is ready to process interrupt */
 469         REG_WAIT(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 0, 100, 800);
 470
 471         /* Set command to signal IRAM is loaded and to initialize IRAM */
 472         REG_UPDATE(MASTER_COMM_CMD_REG, MASTER_COMM_CMD_REG_BYTE0,
 473                         MCP_INIT_IRAM);
 474
 475         /* Notify microcontroller of new command */
 476         REG_UPDATE(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 1);
 477
 478         /* Ensure command has been executed before continuing */
 479         REG_WAIT(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 0, 100, 800);
 480
 481         return true;
 482 }
 483
 484 static void dcn10_get_dmcu_psr_state(struct dmcu *dmcu, uint32_t *psr_state)
 485 {
 486         struct dce_dmcu *dmcu_dce = TO_DCE_DMCU(dmcu);
 487
 488         uint32_t psr_state_offset = 0xf0;
 489
 490         /* If microcontroller is not running, do nothing */
 491         if (dmcu->dmcu_state != DMCU_RUNNING)
 492                 return;
 493
 494         /* Enable write access to IRAM */
 495         REG_UPDATE(DMCU_RAM_ACCESS_CTRL, IRAM_HOST_ACCESS_EN, 1);
 496
 497         REG_WAIT(DMU_MEM_PWR_CNTL, DMCU_IRAM_MEM_PWR_STATE, 0, 2, 10);
 498
 499         /* Write address to IRAM_RD_ADDR in DMCU_IRAM_RD_CTRL */
 500         REG_WRITE(DMCU_IRAM_RD_CTRL, psr_state_offset);
 501
 502         /* Read data from IRAM_RD_DATA in DMCU_IRAM_RD_DATA*/
 503         *psr_state = REG_READ(DMCU_IRAM_RD_DATA);
 504
 505         /* Disable write access to IRAM after finished using IRAM
 506          * in order to allow dynamic sleep state
 507          */
 508         REG_UPDATE(DMCU_RAM_ACCESS_CTRL, IRAM_HOST_ACCESS_EN, 0);
 509 }
 510
 511 static void dcn10_dmcu_set_psr_enable(struct dmcu *dmcu, bool enable, bool wait)
 512 {
 513         struct dce_dmcu *dmcu_dce = TO_DCE_DMCU(dmcu);
 514         unsigned int dmcu_max_retry_on_wait_reg_ready = 801;
 515         unsigned int dmcu_wait_reg_ready_interval = 100;
 516
 517         unsigned int retryCount;
 518         uint32_t psr_state = 0;
 519
 520         /* If microcontroller is not running, do nothing */
 521         if (dmcu->dmcu_state != DMCU_RUNNING)
 522                 return;
 523
 524         dcn10_get_dmcu_psr_state(dmcu, &psr_state);
 525         if (psr_state == 0 && !enable)
 526                 return;
 527         /* waitDMCUReadyForCmd */
 528         REG_WAIT(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 0,
 529                                 dmcu_wait_reg_ready_interval,
 530                                 dmcu_max_retry_on_wait_reg_ready);
 531
 532         /* setDMCUParam_Cmd */
 533         if (enable)
 534                 REG_UPDATE(MASTER_COMM_CMD_REG, MASTER_COMM_CMD_REG_BYTE0,
 535                                 PSR_ENABLE);
 536         else
 537                 REG_UPDATE(MASTER_COMM_CMD_REG, MASTER_COMM_CMD_REG_BYTE0,
 538                                 PSR_EXIT);
 539
 540         /* notifyDMCUMsg */
 541         REG_UPDATE(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 1);
 542
 543         /* Below loops 1000 x 500us = 500 ms.
 544          *  Exit PSR may need to wait 1-2 frames to power up. Timeout after at
 545          *  least a few frames. Should never hit the max retry assert below.
 546          */
 547         if (wait == true) {
 548         for (retryCount = 0; retryCount <= 1000; retryCount++) {
 549                 dcn10_get_dmcu_psr_state(dmcu, &psr_state);
 550                 if (enable) {
 551                         if (psr_state != 0)
 552                                 break;
 553                 } else {
 554                         if (psr_state == 0)
 555                                 break;
 556                 }
 557                 udelay(500);
 558         }
 559
 560         /* assert if max retry hit */
 561         ASSERT(retryCount <= 1000);
 562         }
 563 }
 564
 565 static void dcn10_dmcu_setup_psr(struct dmcu *dmcu,
 566                 struct dc_link *link,
 567                 struct psr_context *psr_context)
 568 {
 569         struct dce_dmcu *dmcu_dce = TO_DCE_DMCU(dmcu);
 570
 571         unsigned int dmcu_max_retry_on_wait_reg_ready = 801;
 572         unsigned int dmcu_wait_reg_ready_interval = 100;
 573
 574         union dce_dmcu_psr_config_data_reg1 masterCmdData1;
 575         union dce_dmcu_psr_config_data_reg2 masterCmdData2;
 576         union dce_dmcu_psr_config_data_reg3 masterCmdData3;
 577
 578         /* If microcontroller is not running, do nothing */
 579         if (dmcu->dmcu_state != DMCU_RUNNING)
 580                 return;
 581
 582         link->link_enc->funcs->psr_program_dp_dphy_fast_training(link->link_enc,
 583                         psr_context->psrExitLinkTrainingRequired);
 584
 585         /* Enable static screen interrupts for PSR supported display */
 586         /* Disable the interrupt coming from other displays. */
 587         REG_UPDATE_4(DMCU_INTERRUPT_TO_UC_EN_MASK,
 588                         STATIC_SCREEN1_INT_TO_UC_EN, 0,
 589                         STATIC_SCREEN2_INT_TO_UC_EN, 0,
 590                         STATIC_SCREEN3_INT_TO_UC_EN, 0,
 591                         STATIC_SCREEN4_INT_TO_UC_EN, 0);
 592
 593         switch (psr_context->controllerId) {
 594         /* Driver uses case 1 for unconfigured */
 595         case 1:
 596                 REG_UPDATE(DMCU_INTERRUPT_TO_UC_EN_MASK,
 597                                 STATIC_SCREEN1_INT_TO_UC_EN, 1);
 598                 break;
 599         case 2:
 600                 REG_UPDATE(DMCU_INTERRUPT_TO_UC_EN_MASK,
 601                                 STATIC_SCREEN2_INT_TO_UC_EN, 1);
 602                 break;
 603         case 3:
 604                 REG_UPDATE(DMCU_INTERRUPT_TO_UC_EN_MASK,
 605                                 STATIC_SCREEN3_INT_TO_UC_EN, 1);
 606                 break;
 607         case 4:
 608                 REG_UPDATE(DMCU_INTERRUPT_TO_UC_EN_MASK,
 609                                 STATIC_SCREEN4_INT_TO_UC_EN, 1);
 610                 break;
 611         case 5:
 612                 /* CZ/NL only has 4 CRTC!!
 613                  * really valid.
 614                  * There is no interrupt enable mask for these instances.
 615                  */
 616                 break;
 617         case 6:
 618                 /* CZ/NL only has 4 CRTC!!
 619                  * These are here because they are defined in HW regspec,
 620                  * but not really valid. There is no interrupt enable mask
 621                  * for these instances.
 622                  */
 623                 break;
 624         default:
 625                 REG_UPDATE(DMCU_INTERRUPT_TO_UC_EN_MASK,
 626                                 STATIC_SCREEN1_INT_TO_UC_EN, 1);
 627                 break;
 628         }
 629
 630         link->link_enc->funcs->psr_program_secondary_packet(link->link_enc,
 631                         psr_context->sdpTransmitLineNumDeadline);
 632
 633         if (psr_context->psr_level.bits.SKIP_SMU_NOTIFICATION)
 634                 REG_UPDATE(SMU_INTERRUPT_CONTROL, DC_SMU_INT_ENABLE, 1);
 635
 636         /* waitDMCUReadyForCmd */
 637         REG_WAIT(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 0,
 638                         dmcu_wait_reg_ready_interval,
 639                         dmcu_max_retry_on_wait_reg_ready);
 640
 641         /* setDMCUParam_PSRHostConfigData */
 642         masterCmdData1.u32All = 0;
 643         masterCmdData1.bits.timehyst_frames = psr_context->timehyst_frames;
 644         masterCmdData1.bits.hyst_lines = psr_context->hyst_lines;
 645         masterCmdData1.bits.rfb_update_auto_en =
 646                         psr_context->rfb_update_auto_en;
 647         masterCmdData1.bits.dp_port_num = psr_context->transmitterId;
 648         masterCmdData1.bits.dcp_sel = psr_context->controllerId;
 649         masterCmdData1.bits.phy_type  = psr_context->phyType;
 650         masterCmdData1.bits.frame_cap_ind =
 651                         psr_context->psrFrameCaptureIndicationReq;
 652         masterCmdData1.bits.aux_chan = psr_context->channel;
 653         masterCmdData1.bits.aux_repeat = psr_context->aux_repeats;
 654         dm_write_reg(dmcu->ctx, REG(MASTER_COMM_DATA_REG1),
 655                                         masterCmdData1.u32All);
 656
 657         masterCmdData2.u32All = 0;
 658         masterCmdData2.bits.dig_fe = psr_context->engineId;
 659         masterCmdData2.bits.dig_be = psr_context->transmitterId;
 660         masterCmdData2.bits.skip_wait_for_pll_lock =
 661                         psr_context->skipPsrWaitForPllLock;
 662         masterCmdData2.bits.frame_delay = psr_context->frame_delay;
 663         masterCmdData2.bits.smu_phy_id = psr_context->smuPhyId;
 664         masterCmdData2.bits.num_of_controllers =
 665                         psr_context->numberOfControllers;
 666         dm_write_reg(dmcu->ctx, REG(MASTER_COMM_DATA_REG2),
 667                         masterCmdData2.u32All);
 668
 669         masterCmdData3.u32All = 0;
 670         masterCmdData3.bits.psr_level = psr_context->psr_level.u32all;
 671         dm_write_reg(dmcu->ctx, REG(MASTER_COMM_DATA_REG3),
 672                         masterCmdData3.u32All);
 673
 674         /* setDMCUParam_Cmd */
 675         REG_UPDATE(MASTER_COMM_CMD_REG,
 676                         MASTER_COMM_CMD_REG_BYTE0, PSR_SET);
 677
 678         /* notifyDMCUMsg */
 679         REG_UPDATE(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 1);
 680 }
 681
 682 static void dcn10_psr_wait_loop(
 683         struct dmcu *dmcu,
 684         unsigned int wait_loop_number)
 685 {
 686         struct dce_dmcu *dmcu_dce = TO_DCE_DMCU(dmcu);
 687         union dce_dmcu_psr_config_data_wait_loop_reg1 masterCmdData1;
 688
 689         /* If microcontroller is not running, do nothing */
 690         if (dmcu->dmcu_state != DMCU_RUNNING)
 691                 return;
 692
 693         if (wait_loop_number != 0) {
 694         /* waitDMCUReadyForCmd */
 695         REG_WAIT(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 0, 1, 10000);
 696
 697         masterCmdData1.u32 = 0;
 698         masterCmdData1.bits.wait_loop = wait_loop_number;
 699         dmcu->cached_wait_loop_number = wait_loop_number;
 700         dm_write_reg(dmcu->ctx, REG(MASTER_COMM_DATA_REG1), masterCmdData1.u32);
 701
 702         /* setDMCUParam_Cmd */
 703         REG_UPDATE(MASTER_COMM_CMD_REG, MASTER_COMM_CMD_REG_BYTE0, PSR_SET_WAITLOOP);
 704
 705         /* notifyDMCUMsg */
 706         REG_UPDATE(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 1);
 707         }
 708 }
 709
 710 static void dcn10_get_psr_wait_loop(
 711                 struct dmcu *dmcu, unsigned int *psr_wait_loop_number)
 712 {
 713         *psr_wait_loop_number = dmcu->cached_wait_loop_number;
 714         return;
 715 }
 716
 717 static bool dcn10_is_dmcu_initialized(struct dmcu *dmcu)
 718 {
 719         /* microcontroller is not running */
 720         if (dmcu->dmcu_state != DMCU_RUNNING)
 721                 return false;
 722         return true;
 723 }
 724
 725 #endif
 726
 727 static const struct dmcu_funcs dce_funcs = {
 728         .dmcu_init = dce_dmcu_init,
 729         .load_iram = dce_dmcu_load_iram,
 730         .set_psr_enable = dce_dmcu_set_psr_enable,
 731         .setup_psr = dce_dmcu_setup_psr,
 732         .get_psr_state = dce_get_dmcu_psr_state,
 733         .set_psr_wait_loop = dce_psr_wait_loop,
 734         .get_psr_wait_loop = dce_get_psr_wait_loop,
 735         .is_dmcu_initialized = dce_is_dmcu_initialized
 736 };
 737
 738 #ifdef CONFIG_X86
 739 static const struct dmcu_funcs dcn10_funcs = {
 740         .dmcu_init = dcn10_dmcu_init,
 741         .load_iram = dcn10_dmcu_load_iram,
 742         .set_psr_enable = dcn10_dmcu_set_psr_enable,
 743         .setup_psr = dcn10_dmcu_setup_psr,
 744         .get_psr_state = dcn10_get_dmcu_psr_state,
 745         .set_psr_wait_loop = dcn10_psr_wait_loop,
 746         .get_psr_wait_loop = dcn10_get_psr_wait_loop,
 747         .is_dmcu_initialized = dcn10_is_dmcu_initialized
 748 };
 749 #endif
 750
 751 static void dce_dmcu_construct(
 752         struct dce_dmcu *dmcu_dce,
 753         struct dc_context *ctx,
 754         const struct dce_dmcu_registers *regs,
 755         const struct dce_dmcu_shift *dmcu_shift,
 756         const struct dce_dmcu_mask *dmcu_mask)
 757 {
 758         struct dmcu *base = &dmcu_dce->base;
 759
 760         base->ctx = ctx;
 761         base->funcs = &dce_funcs;
 762         base->cached_wait_loop_number = 0;
 763
 764         dmcu_dce->regs = regs;
 765         dmcu_dce->dmcu_shift = dmcu_shift;
 766         dmcu_dce->dmcu_mask = dmcu_mask;
 767 }
 768
 769 struct dmcu *dce_dmcu_create(
 770         struct dc_context *ctx,
 771         const struct dce_dmcu_registers *regs,
 772         const struct dce_dmcu_shift *dmcu_shift,
 773         const struct dce_dmcu_mask *dmcu_mask)
 774 {
 775         struct dce_dmcu *dmcu_dce = kzalloc(sizeof(*dmcu_dce), GFP_KERNEL);
 776
 777         if (dmcu_dce == NULL) {
 778                 BREAK_TO_DEBUGGER();
 779                 return NULL;
 780         }
 781
 782         dce_dmcu_construct(
 783                 dmcu_dce, ctx, regs, dmcu_shift, dmcu_mask);
 784
 785         dmcu_dce->base.funcs = &dce_funcs;
 786
 787         return &dmcu_dce->base;
 788 }
 789
 790 #ifdef CONFIG_X86
 791 struct dmcu *dcn10_dmcu_create(
 792         struct dc_context *ctx,
 793         const struct dce_dmcu_registers *regs,
 794         const struct dce_dmcu_shift *dmcu_shift,
 795         const struct dce_dmcu_mask *dmcu_mask)
 796 {
 797         struct dce_dmcu *dmcu_dce = kzalloc(sizeof(*dmcu_dce), GFP_KERNEL);
 798
 799         if (dmcu_dce == NULL) {
 800                 BREAK_TO_DEBUGGER();
 801                 return NULL;
 802         }
 803
 804         dce_dmcu_construct(
 805                 dmcu_dce, ctx, regs, dmcu_shift, dmcu_mask);
 806
 807         dmcu_dce->base.funcs = &dcn10_funcs;
 808
 809         return &dmcu_dce->base;
 810 }
 811 #endif
 812
 813 void dce_dmcu_destroy(struct dmcu **dmcu)
 814 {
 815         struct dce_dmcu *dmcu_dce = TO_DCE_DMCU(*dmcu);
 816
 817         kfree(dmcu_dce);
 818         *dmcu = NULL;
 819 }