drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.c

   1 /*
   2  * Copyright 2012-15 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: AMD
  23  *
  24  */
  25
  26 #include "reg_helper.h"
  27
  28 #include "core_types.h"
  29 #include "link_encoder.h"
  30 #include "dce_link_encoder.h"
  31 #include "stream_encoder.h"
  32 #include "i2caux_interface.h"
  33 #include "dc_bios_types.h"
  34
  35 #include "gpio_service_interface.h"
  36
  37 #include "dce/dce_11_0_d.h"
  38 #include "dce/dce_11_0_sh_mask.h"
  39 #include "dce/dce_11_0_enum.h"
  40
  41 #ifndef DMU_MEM_PWR_CNTL__DMCU_IRAM_MEM_PWR_STATE__SHIFT
  42 #define DMU_MEM_PWR_CNTL__DMCU_IRAM_MEM_PWR_STATE__SHIFT 0xa
  43 #endif
  44
  45 #ifndef DMU_MEM_PWR_CNTL__DMCU_IRAM_MEM_PWR_STATE_MASK
  46 #define DMU_MEM_PWR_CNTL__DMCU_IRAM_MEM_PWR_STATE_MASK 0x00000400L
  47 #endif
  48
  49 #ifndef HPD0_DC_HPD_CONTROL__DC_HPD_EN_MASK
  50 #define HPD0_DC_HPD_CONTROL__DC_HPD_EN_MASK  0x10000000L
  51 #endif
  52
  53 #ifndef HPD0_DC_HPD_CONTROL__DC_HPD_EN__SHIFT
  54 #define HPD0_DC_HPD_CONTROL__DC_HPD_EN__SHIFT  0x1c
  55 #endif
  56
  57 #define CTX \
  58         enc110->base.ctx
  59 #define DC_LOGGER \
  60         enc110->base.ctx->logger
  61
  62 #define REG(reg)\
  63         (enc110->link_regs->reg)
  64
  65 #define AUX_REG(reg)\
  66         (enc110->aux_regs->reg)
  67
  68 #define HPD_REG(reg)\
  69         (enc110->hpd_regs->reg)
  70
  71 #define DEFAULT_AUX_MAX_DATA_SIZE 16
  72 #define AUX_MAX_DEFER_WRITE_RETRY 20
  73 /*
  74  * @brief
  75  * Trigger Source Select
  76  * ASIC-dependent, actual values for register programming
  77  */
  78 #define DCE110_DIG_FE_SOURCE_SELECT_INVALID 0x0
  79 #define DCE110_DIG_FE_SOURCE_SELECT_DIGA 0x1
  80 #define DCE110_DIG_FE_SOURCE_SELECT_DIGB 0x2
  81 #define DCE110_DIG_FE_SOURCE_SELECT_DIGC 0x4
  82 #define DCE110_DIG_FE_SOURCE_SELECT_DIGD 0x08
  83 #define DCE110_DIG_FE_SOURCE_SELECT_DIGE 0x10
  84 #define DCE110_DIG_FE_SOURCE_SELECT_DIGF 0x20
  85 #define DCE110_DIG_FE_SOURCE_SELECT_DIGG 0x40
  86
  87 enum {
  88         DP_MST_UPDATE_MAX_RETRY = 50
  89 };
  90
  91 #define DIG_REG(reg)\
  92         (reg + enc110->offsets.dig)
  93
  94 #define DP_REG(reg)\
  95         (reg + enc110->offsets.dp)
  96
  97 static const struct link_encoder_funcs dce110_lnk_enc_funcs = {
  98         .validate_output_with_stream =
  99                 dce110_link_encoder_validate_output_with_stream,
 100         .hw_init = dce110_link_encoder_hw_init,
 101         .setup = dce110_link_encoder_setup,
 102         .enable_tmds_output = dce110_link_encoder_enable_tmds_output,
 103         .enable_dp_output = dce110_link_encoder_enable_dp_output,
 104         .enable_dp_mst_output = dce110_link_encoder_enable_dp_mst_output,
 105         .enable_lvds_output = dce110_link_encoder_enable_lvds_output,
 106         .disable_output = dce110_link_encoder_disable_output,
 107         .dp_set_lane_settings = dce110_link_encoder_dp_set_lane_settings,
 108         .dp_set_phy_pattern = dce110_link_encoder_dp_set_phy_pattern,
 109         .update_mst_stream_allocation_table =
 110                 dce110_link_encoder_update_mst_stream_allocation_table,
 111         .psr_program_dp_dphy_fast_training =
 112                         dce110_psr_program_dp_dphy_fast_training,
 113         .psr_program_secondary_packet = dce110_psr_program_secondary_packet,
 114         .connect_dig_be_to_fe = dce110_link_encoder_connect_dig_be_to_fe,
 115         .enable_hpd = dce110_link_encoder_enable_hpd,
 116         .disable_hpd = dce110_link_encoder_disable_hpd,
 117         .is_dig_enabled = dce110_is_dig_enabled,
 118         .destroy = dce110_link_encoder_destroy
 119 };
 120
 121 static enum bp_result link_transmitter_control(
 122         struct dce110_link_encoder *enc110,
 123         struct bp_transmitter_control *cntl)
 124 {
 125         enum bp_result result;
 126         struct dc_bios *bp = enc110->base.ctx->dc_bios;
 127
 128         result = bp->funcs->transmitter_control(bp, cntl);
 129
 130         return result;
 131 }
 132
 133 static void enable_phy_bypass_mode(
 134         struct dce110_link_encoder *enc110,
 135         bool enable)
 136 {
 137         /* This register resides in DP back end block;
 138          * transmitter is used for the offset */
 139
 140         REG_UPDATE(DP_DPHY_CNTL, DPHY_BYPASS, enable);
 141
 142 }
 143
 144 static void disable_prbs_symbols(
 145         struct dce110_link_encoder *enc110,
 146         bool disable)
 147 {
 148         /* This register resides in DP back end block;
 149          * transmitter is used for the offset */
 150
 151         REG_UPDATE_4(DP_DPHY_CNTL,
 152                         DPHY_ATEST_SEL_LANE0, disable,
 153                         DPHY_ATEST_SEL_LANE1, disable,
 154                         DPHY_ATEST_SEL_LANE2, disable,
 155                         DPHY_ATEST_SEL_LANE3, disable);
 156 }
 157
 158 static void disable_prbs_mode(
 159         struct dce110_link_encoder *enc110)
 160 {
 161         REG_UPDATE(DP_DPHY_PRBS_CNTL, DPHY_PRBS_EN, 0);
 162 }
 163
 164 static void program_pattern_symbols(
 165         struct dce110_link_encoder *enc110,
 166         uint16_t pattern_symbols[8])
 167 {
 168         /* This register resides in DP back end block;
 169          * transmitter is used for the offset */
 170
 171         REG_SET_3(DP_DPHY_SYM0, 0,
 172                         DPHY_SYM1, pattern_symbols[0],
 173                         DPHY_SYM2, pattern_symbols[1],
 174                         DPHY_SYM3, pattern_symbols[2]);
 175
 176         /* This register resides in DP back end block;
 177          * transmitter is used for the offset */
 178
 179         REG_SET_3(DP_DPHY_SYM1, 0,
 180                         DPHY_SYM4, pattern_symbols[3],
 181                         DPHY_SYM5, pattern_symbols[4],
 182                         DPHY_SYM6, pattern_symbols[5]);
 183
 184         /* This register resides in DP back end block;
 185          * transmitter is used for the offset */
 186
 187         REG_SET_2(DP_DPHY_SYM2, 0,
 188                         DPHY_SYM7, pattern_symbols[6],
 189                         DPHY_SYM8, pattern_symbols[7]);
 190 }
 191
 192 static void set_dp_phy_pattern_d102(
 193         struct dce110_link_encoder *enc110)
 194 {
 195         /* Disable PHY Bypass mode to setup the test pattern */
 196         enable_phy_bypass_mode(enc110, false);
 197
 198         /* For 10-bit PRBS or debug symbols
 199          * please use the following sequence: */
 200
 201         /* Enable debug symbols on the lanes */
 202
 203         disable_prbs_symbols(enc110, true);
 204
 205         /* Disable PRBS mode */
 206         disable_prbs_mode(enc110);
 207
 208         /* Program debug symbols to be output */
 209         {
 210                 uint16_t pattern_symbols[8] = {
 211                         0x2AA, 0x2AA, 0x2AA, 0x2AA,
 212                         0x2AA, 0x2AA, 0x2AA, 0x2AA
 213                 };
 214
 215                 program_pattern_symbols(enc110, pattern_symbols);
 216         }
 217
 218         /* Enable phy bypass mode to enable the test pattern */
 219
 220         enable_phy_bypass_mode(enc110, true);
 221 }
 222
 223 static void set_link_training_complete(
 224         struct dce110_link_encoder *enc110,
 225         bool complete)
 226 {
 227         /* This register resides in DP back end block;
 228          * transmitter is used for the offset */
 229
 230         REG_UPDATE(DP_LINK_CNTL, DP_LINK_TRAINING_COMPLETE, complete);
 231
 232 }
 233
 234 void dce110_link_encoder_set_dp_phy_pattern_training_pattern(
 235         struct link_encoder *enc,
 236         uint32_t index)
 237 {
 238         struct dce110_link_encoder *enc110 = TO_DCE110_LINK_ENC(enc);
 239         /* Write Training Pattern */
 240
 241         REG_WRITE(DP_DPHY_TRAINING_PATTERN_SEL, index);
 242
 243         /* Set HW Register Training Complete to false */
 244
 245         set_link_training_complete(enc110, false);
 246
 247         /* Disable PHY Bypass mode to output Training Pattern */
 248
 249         enable_phy_bypass_mode(enc110, false);
 250
 251         /* Disable PRBS mode */
 252         disable_prbs_mode(enc110);
 253 }
 254
 255 static void setup_panel_mode(
 256         struct dce110_link_encoder *enc110,
 257         enum dp_panel_mode panel_mode)
 258 {
 259         uint32_t value;
 260         struct dc_context *ctx = enc110->base.ctx;
 261
 262         /* if psp set panel mode, dal should be program it */
 263         if (ctx->dc->caps.psp_setup_panel_mode)
 264                 return;
 265
 266         ASSERT(REG(DP_DPHY_INTERNAL_CTRL));
 267         value = REG_READ(DP_DPHY_INTERNAL_CTRL);
 268
 269         switch (panel_mode) {
 270         case DP_PANEL_MODE_EDP:
 271                 value = 0x1;
 272                 break;
 273         case DP_PANEL_MODE_SPECIAL:
 274                 value = 0x11;
 275                 break;
 276         default:
 277                 value = 0x0;
 278                 break;
 279         }
 280
 281         REG_WRITE(DP_DPHY_INTERNAL_CTRL, value);
 282 }
 283
 284 static void set_dp_phy_pattern_symbol_error(
 285         struct dce110_link_encoder *enc110)
 286 {
 287         /* Disable PHY Bypass mode to setup the test pattern */
 288         enable_phy_bypass_mode(enc110, false);
 289
 290         /* program correct panel mode*/
 291         setup_panel_mode(enc110, DP_PANEL_MODE_DEFAULT);
 292
 293         /* A PRBS23 pattern is used for most DP electrical measurements. */
 294
 295         /* Enable PRBS symbols on the lanes */
 296         disable_prbs_symbols(enc110, false);
 297
 298         /* For PRBS23 Set bit DPHY_PRBS_SEL=1 and Set bit DPHY_PRBS_EN=1 */
 299         REG_UPDATE_2(DP_DPHY_PRBS_CNTL,
 300                         DPHY_PRBS_SEL, 1,
 301                         DPHY_PRBS_EN, 1);
 302
 303         /* Enable phy bypass mode to enable the test pattern */
 304         enable_phy_bypass_mode(enc110, true);
 305 }
 306
 307 static void set_dp_phy_pattern_prbs7(
 308         struct dce110_link_encoder *enc110)
 309 {
 310         /* Disable PHY Bypass mode to setup the test pattern */
 311         enable_phy_bypass_mode(enc110, false);
 312
 313         /* A PRBS7 pattern is used for most DP electrical measurements. */
 314
 315         /* Enable PRBS symbols on the lanes */
 316         disable_prbs_symbols(enc110, false);
 317
 318         /* For PRBS7 Set bit DPHY_PRBS_SEL=0 and Set bit DPHY_PRBS_EN=1 */
 319         REG_UPDATE_2(DP_DPHY_PRBS_CNTL,
 320                         DPHY_PRBS_SEL, 0,
 321                         DPHY_PRBS_EN, 1);
 322
 323         /* Enable phy bypass mode to enable the test pattern */
 324         enable_phy_bypass_mode(enc110, true);
 325 }
 326
 327 static void set_dp_phy_pattern_80bit_custom(
 328         struct dce110_link_encoder *enc110,
 329         const uint8_t *pattern)
 330 {
 331         /* Disable PHY Bypass mode to setup the test pattern */
 332         enable_phy_bypass_mode(enc110, false);
 333
 334         /* Enable debug symbols on the lanes */
 335
 336         disable_prbs_symbols(enc110, true);
 337
 338         /* Enable PHY bypass mode to enable the test pattern */
 339         /* TODO is it really needed ? */
 340
 341         enable_phy_bypass_mode(enc110, true);
 342
 343         /* Program 80 bit custom pattern */
 344         {
 345                 uint16_t pattern_symbols[8];
 346
 347                 pattern_symbols[0] =
 348                         ((pattern[1] & 0x03) << 8) | pattern[0];
 349                 pattern_symbols[1] =
 350                         ((pattern[2] & 0x0f) << 6) | ((pattern[1] >> 2) & 0x3f);
 351                 pattern_symbols[2] =
 352                         ((pattern[3] & 0x3f) << 4) | ((pattern[2] >> 4) & 0x0f);
 353                 pattern_symbols[3] =
 354                         (pattern[4] << 2) | ((pattern[3] >> 6) & 0x03);
 355                 pattern_symbols[4] =
 356                         ((pattern[6] & 0x03) << 8) | pattern[5];
 357                 pattern_symbols[5] =
 358                         ((pattern[7] & 0x0f) << 6) | ((pattern[6] >> 2) & 0x3f);
 359                 pattern_symbols[6] =
 360                         ((pattern[8] & 0x3f) << 4) | ((pattern[7] >> 4) & 0x0f);
 361                 pattern_symbols[7] =
 362                         (pattern[9] << 2) | ((pattern[8] >> 6) & 0x03);
 363
 364                 program_pattern_symbols(enc110, pattern_symbols);
 365         }
 366
 367         /* Enable phy bypass mode to enable the test pattern */
 368
 369         enable_phy_bypass_mode(enc110, true);
 370 }
 371
 372 static void set_dp_phy_pattern_hbr2_compliance_cp2520_2(
 373         struct dce110_link_encoder *enc110,
 374         unsigned int cp2520_pattern)
 375 {
 376
 377         /* previously there is a register DP_HBR2_EYE_PATTERN
 378          * that is enabled to get the pattern.
 379          * But it does not work with the latest spec change,
 380          * so we are programming the following registers manually.
 381          *
 382          * The following settings have been confirmed
 383          * by Nick Chorney and Sandra Liu */
 384
 385         /* Disable PHY Bypass mode to setup the test pattern */
 386
 387         enable_phy_bypass_mode(enc110, false);
 388
 389         /* Setup DIG encoder in DP SST mode */
 390         enc110->base.funcs->setup(&enc110->base, SIGNAL_TYPE_DISPLAY_PORT);
 391
 392         /* ensure normal panel mode. */
 393         setup_panel_mode(enc110, DP_PANEL_MODE_DEFAULT);
 394
 395         /* no vbid after BS (SR)
 396          * DP_LINK_FRAMING_CNTL changed history Sandra Liu
 397          * 11000260 / 11000104 / 110000FC */
 398         REG_UPDATE_3(DP_LINK_FRAMING_CNTL,
 399                         DP_IDLE_BS_INTERVAL, 0xFC,
 400                         DP_VBID_DISABLE, 1,
 401                         DP_VID_ENHANCED_FRAME_MODE, 1);
 402
 403         /* swap every BS with SR */
 404         REG_UPDATE(DP_DPHY_SCRAM_CNTL, DPHY_SCRAMBLER_BS_COUNT, 0);
 405
 406         /* select cp2520 patterns */
 407         if (REG(DP_DPHY_HBR2_PATTERN_CONTROL))
 408                 REG_UPDATE(DP_DPHY_HBR2_PATTERN_CONTROL,
 409                                 DP_DPHY_HBR2_PATTERN_CONTROL, cp2520_pattern);
 410         else
 411                 /* pre-DCE11 can only generate CP2520 pattern 2 */
 412                 ASSERT(cp2520_pattern == 2);
 413
 414         /* set link training complete */
 415         set_link_training_complete(enc110, true);
 416
 417         /* disable video stream */
 418         REG_UPDATE(DP_VID_STREAM_CNTL, DP_VID_STREAM_ENABLE, 0);
 419
 420         /* Disable PHY Bypass mode to setup the test pattern */
 421         enable_phy_bypass_mode(enc110, false);
 422 }
 423
 424 static void set_dp_phy_pattern_passthrough_mode(
 425         struct dce110_link_encoder *enc110,
 426         enum dp_panel_mode panel_mode)
 427 {
 428         /* program correct panel mode */
 429         setup_panel_mode(enc110, panel_mode);
 430
 431         /* restore LINK_FRAMING_CNTL and DPHY_SCRAMBLER_BS_COUNT
 432          * in case we were doing HBR2 compliance pattern before
 433          */
 434         REG_UPDATE_3(DP_LINK_FRAMING_CNTL,
 435                         DP_IDLE_BS_INTERVAL, 0x2000,
 436                         DP_VBID_DISABLE, 0,
 437                         DP_VID_ENHANCED_FRAME_MODE, 1);
 438
 439         REG_UPDATE(DP_DPHY_SCRAM_CNTL, DPHY_SCRAMBLER_BS_COUNT, 0x1FF);
 440
 441         /* set link training complete */
 442         set_link_training_complete(enc110, true);
 443
 444         /* Disable PHY Bypass mode to setup the test pattern */
 445         enable_phy_bypass_mode(enc110, false);
 446
 447         /* Disable PRBS mode */
 448         disable_prbs_mode(enc110);
 449 }
 450
 451 /* return value is bit-vector */
 452 static uint8_t get_frontend_source(
 453         enum engine_id engine)
 454 {
 455         switch (engine) {
 456         case ENGINE_ID_DIGA:
 457                 return DCE110_DIG_FE_SOURCE_SELECT_DIGA;
 458         case ENGINE_ID_DIGB:
 459                 return DCE110_DIG_FE_SOURCE_SELECT_DIGB;
 460         case ENGINE_ID_DIGC:
 461                 return DCE110_DIG_FE_SOURCE_SELECT_DIGC;
 462         case ENGINE_ID_DIGD:
 463                 return DCE110_DIG_FE_SOURCE_SELECT_DIGD;
 464         case ENGINE_ID_DIGE:
 465                 return DCE110_DIG_FE_SOURCE_SELECT_DIGE;
 466         case ENGINE_ID_DIGF:
 467                 return DCE110_DIG_FE_SOURCE_SELECT_DIGF;
 468         case ENGINE_ID_DIGG:
 469                 return DCE110_DIG_FE_SOURCE_SELECT_DIGG;
 470         default:
 471                 ASSERT_CRITICAL(false);
 472                 return DCE110_DIG_FE_SOURCE_SELECT_INVALID;
 473         }
 474 }
 475
 476 static void configure_encoder(
 477         struct dce110_link_encoder *enc110,
 478         const struct dc_link_settings *link_settings)
 479 {
 480         /* set number of lanes */
 481
 482         REG_SET(DP_CONFIG, 0,
 483                         DP_UDI_LANES, link_settings->lane_count - LANE_COUNT_ONE);
 484
 485         /* setup scrambler */
 486         REG_UPDATE(DP_DPHY_SCRAM_CNTL, DPHY_SCRAMBLER_ADVANCE, 1);
 487 }
 488
 489 static void aux_initialize(
 490         struct dce110_link_encoder *enc110)
 491 {
 492         struct dc_context *ctx = enc110->base.ctx;
 493         enum hpd_source_id hpd_source = enc110->base.hpd_source;
 494         uint32_t addr = AUX_REG(AUX_CONTROL);
 495         uint32_t value = dm_read_reg(ctx, addr);
 496
 497         set_reg_field_value(value, hpd_source, AUX_CONTROL, AUX_HPD_SEL);
 498         set_reg_field_value(value, 0, AUX_CONTROL, AUX_LS_READ_EN);
 499         dm_write_reg(ctx, addr, value);
 500
 501         addr = AUX_REG(AUX_DPHY_RX_CONTROL0);
 502         value = dm_read_reg(ctx, addr);
 503
 504         /* 1/4 window (the maximum allowed) */
 505         set_reg_field_value(value, 1,
 506                         AUX_DPHY_RX_CONTROL0, AUX_RX_RECEIVE_WINDOW);
 507         dm_write_reg(ctx, addr, value);
 508
 509 }
 510
 511 void dce110_psr_program_dp_dphy_fast_training(struct link_encoder *enc,
 512                         bool exit_link_training_required)
 513 {
 514         struct dce110_link_encoder *enc110 = TO_DCE110_LINK_ENC(enc);
 515
 516         if (exit_link_training_required)
 517                 REG_UPDATE(DP_DPHY_FAST_TRAINING,
 518                                 DPHY_RX_FAST_TRAINING_CAPABLE, 1);
 519         else {
 520                 REG_UPDATE(DP_DPHY_FAST_TRAINING,
 521                                 DPHY_RX_FAST_TRAINING_CAPABLE, 0);
 522                 /*In DCE 11, we are able to pre-program a Force SR register
 523                  * to be able to trigger SR symbol after 5 idle patterns
 524                  * transmitted. Upon PSR Exit, DMCU can trigger
 525                  * DPHY_LOAD_BS_COUNT_START = 1. Upon writing 1 to
 526                  * DPHY_LOAD_BS_COUNT_START and the internal counter
 527                  * reaches DPHY_LOAD_BS_COUNT, the next BS symbol will be
 528                  * replaced by SR symbol once.
 529                  */
 530
 531                 REG_UPDATE(DP_DPHY_BS_SR_SWAP_CNTL, DPHY_LOAD_BS_COUNT, 0x5);
 532         }
 533 }
 534
 535 void dce110_psr_program_secondary_packet(struct link_encoder *enc,
 536                         unsigned int sdp_transmit_line_num_deadline)
 537 {
 538         struct dce110_link_encoder *enc110 = TO_DCE110_LINK_ENC(enc);
 539
 540         REG_UPDATE_2(DP_SEC_CNTL1,
 541                 DP_SEC_GSP0_LINE_NUM, sdp_transmit_line_num_deadline,
 542                 DP_SEC_GSP0_PRIORITY, 1);
 543 }
 544
 545 bool dce110_is_dig_enabled(struct link_encoder *enc)
 546 {
 547         struct dce110_link_encoder *enc110 = TO_DCE110_LINK_ENC(enc);
 548         uint32_t value;
 549
 550         REG_GET(DIG_BE_EN_CNTL, DIG_ENABLE, &value);
 551         return value;
 552 }
 553
 554 static void link_encoder_disable(struct dce110_link_encoder *enc110)
 555 {
 556         /* reset training pattern */
 557         REG_SET(DP_DPHY_TRAINING_PATTERN_SEL, 0,
 558                         DPHY_TRAINING_PATTERN_SEL, 0);
 559
 560         /* reset training complete */
 561         REG_UPDATE(DP_LINK_CNTL, DP_LINK_TRAINING_COMPLETE, 0);
 562
 563         /* reset panel mode */
 564         setup_panel_mode(enc110, DP_PANEL_MODE_DEFAULT);
 565 }
 566
 567 static void hpd_initialize(
 568         struct dce110_link_encoder *enc110)
 569 {
 570         /* Associate HPD with DIG_BE */
 571         enum hpd_source_id hpd_source = enc110->base.hpd_source;
 572
 573         REG_UPDATE(DIG_BE_CNTL, DIG_HPD_SELECT, hpd_source);
 574 }
 575
 576 bool dce110_link_encoder_validate_dvi_output(
 577         const struct dce110_link_encoder *enc110,
 578         enum signal_type connector_signal,
 579         enum signal_type signal,
 580         const struct dc_crtc_timing *crtc_timing)
 581 {
 582         uint32_t max_pixel_clock = TMDS_MAX_PIXEL_CLOCK;
 583
 584         if (signal == SIGNAL_TYPE_DVI_DUAL_LINK)
 585                 max_pixel_clock *= 2;
 586
 587         /* This handles the case of HDMI downgrade to DVI we don't want to
 588          * we don't want to cap the pixel clock if the DDI is not DVI.
 589          */
 590         if (connector_signal != SIGNAL_TYPE_DVI_DUAL_LINK &&
 591                         connector_signal != SIGNAL_TYPE_DVI_SINGLE_LINK)
 592                 max_pixel_clock = enc110->base.features.max_hdmi_pixel_clock;
 593
 594         /* DVI only support RGB pixel encoding */
 595         if (crtc_timing->pixel_encoding != PIXEL_ENCODING_RGB)
 596                 return false;
 597
 598         /*connect DVI via adpater's HDMI connector*/
 599         if ((connector_signal == SIGNAL_TYPE_DVI_SINGLE_LINK ||
 600                 connector_signal == SIGNAL_TYPE_HDMI_TYPE_A) &&
 601                 signal != SIGNAL_TYPE_HDMI_TYPE_A &&
 602                 crtc_timing->pix_clk_khz > TMDS_MAX_PIXEL_CLOCK)
 603                 return false;
 604         if (crtc_timing->pix_clk_khz < TMDS_MIN_PIXEL_CLOCK)
 605                 return false;
 606
 607         if (crtc_timing->pix_clk_khz > max_pixel_clock)
 608                 return false;
 609
 610         /* DVI supports 6/8bpp single-link and 10/16bpp dual-link */
 611         switch (crtc_timing->display_color_depth) {
 612         case COLOR_DEPTH_666:
 613         case COLOR_DEPTH_888:
 614         break;
 615         case COLOR_DEPTH_101010:
 616         case COLOR_DEPTH_161616:
 617                 if (signal != SIGNAL_TYPE_DVI_DUAL_LINK)
 618                         return false;
 619         break;
 620         default:
 621                 return false;
 622         }
 623
 624         return true;
 625 }
 626
 627 static bool dce110_link_encoder_validate_hdmi_output(
 628         const struct dce110_link_encoder *enc110,
 629         const struct dc_crtc_timing *crtc_timing,
 630         int adjusted_pix_clk_khz)
 631 {
 632         enum dc_color_depth max_deep_color =
 633                         enc110->base.features.max_hdmi_deep_color;
 634
 635         if (max_deep_color < crtc_timing->display_color_depth)
 636                 return false;
 637
 638         if (crtc_timing->display_color_depth < COLOR_DEPTH_888)
 639                 return false;
 640         if (adjusted_pix_clk_khz < TMDS_MIN_PIXEL_CLOCK)
 641                 return false;
 642
 643         if ((adjusted_pix_clk_khz == 0) ||
 644                 (adjusted_pix_clk_khz > enc110->base.features.max_hdmi_pixel_clock))
 645                 return false;
 646
 647         /* DCE11 HW does not support 420 */
 648         if (!enc110->base.features.ycbcr420_supported &&
 649                         crtc_timing->pixel_encoding == PIXEL_ENCODING_YCBCR420)
 650                 return false;
 651
 652         if (!enc110->base.features.flags.bits.HDMI_6GB_EN &&
 653                 adjusted_pix_clk_khz >= 300000)
 654                 return false;
 655         if (enc110->base.ctx->dc->debug.hdmi20_disable &&
 656                 crtc_timing->pixel_encoding == PIXEL_ENCODING_YCBCR420)
 657                 return false;
 658         return true;
 659 }
 660
 661 bool dce110_link_encoder_validate_dp_output(
 662         const struct dce110_link_encoder *enc110,
 663         const struct dc_crtc_timing *crtc_timing)
 664 {
 665         if (crtc_timing->pixel_encoding == PIXEL_ENCODING_YCBCR420)
 666                 return false;
 667
 668         /* default RGB only */
 669         if (crtc_timing->pixel_encoding == PIXEL_ENCODING_RGB)
 670                 return true;
 671
 672         if (enc110->base.features.flags.bits.IS_YCBCR_CAPABLE)
 673                 return true;
 674
 675         /* for DCE 8.x or later DP Y-only feature,
 676          * we need ASIC cap + FeatureSupportDPYonly, not support 666 */
 677         if (crtc_timing->flags.Y_ONLY &&
 678                 enc110->base.features.flags.bits.IS_YCBCR_CAPABLE &&
 679                 crtc_timing->display_color_depth != COLOR_DEPTH_666)
 680                 return true;
 681
 682         return false;
 683 }
 684
 685 void dce110_link_encoder_construct(
 686         struct dce110_link_encoder *enc110,
 687         const struct encoder_init_data *init_data,
 688         const struct encoder_feature_support *enc_features,
 689         const struct dce110_link_enc_registers *link_regs,
 690         const struct dce110_link_enc_aux_registers *aux_regs,
 691         const struct dce110_link_enc_hpd_registers *hpd_regs)
 692 {
 693         struct bp_encoder_cap_info bp_cap_info = {0};
 694         const struct dc_vbios_funcs *bp_funcs = init_data->ctx->dc_bios->funcs;
 695         enum bp_result result = BP_RESULT_OK;
 696
 697         enc110->base.funcs = &dce110_lnk_enc_funcs;
 698         enc110->base.ctx = init_data->ctx;
 699         enc110->base.id = init_data->encoder;
 700
 701         enc110->base.hpd_source = init_data->hpd_source;
 702         enc110->base.connector = init_data->connector;
 703
 704         enc110->base.preferred_engine = ENGINE_ID_UNKNOWN;
 705
 706         enc110->base.features = *enc_features;
 707
 708         enc110->base.transmitter = init_data->transmitter;
 709
 710         /* set the flag to indicate whether driver poll the I2C data pin
 711          * while doing the DP sink detect
 712          */
 713
 714 /*      if (dal_adapter_service_is_feature_supported(as,
 715                 FEATURE_DP_SINK_DETECT_POLL_DATA_PIN))
 716                 enc110->base.features.flags.bits.
 717                         DP_SINK_DETECT_POLL_DATA_PIN = true;*/
 718
 719         enc110->base.output_signals =
 720                 SIGNAL_TYPE_DVI_SINGLE_LINK |
 721                 SIGNAL_TYPE_DVI_DUAL_LINK |
 722                 SIGNAL_TYPE_LVDS |
 723                 SIGNAL_TYPE_DISPLAY_PORT |
 724                 SIGNAL_TYPE_DISPLAY_PORT_MST |
 725                 SIGNAL_TYPE_EDP |
 726                 SIGNAL_TYPE_HDMI_TYPE_A;
 727
 728         /* For DCE 8.0 and 8.1, by design, UNIPHY is hardwired to DIG_BE.
 729          * SW always assign DIG_FE 1:1 mapped to DIG_FE for non-MST UNIPHY.
 730          * SW assign DIG_FE to non-MST UNIPHY first and MST last. So prefer
 731          * DIG is per UNIPHY and used by SST DP, eDP, HDMI, DVI and LVDS.
 732          * Prefer DIG assignment is decided by board design.
 733          * For DCE 8.0, there are only max 6 UNIPHYs, we assume board design
 734          * and VBIOS will filter out 7 UNIPHY for DCE 8.0.
 735          * By this, adding DIGG should not hurt DCE 8.0.
 736          * This will let DCE 8.1 share DCE 8.0 as much as possible
 737          */
 738
 739         enc110->link_regs = link_regs;
 740         enc110->aux_regs = aux_regs;
 741         enc110->hpd_regs = hpd_regs;
 742
 743         switch (enc110->base.transmitter) {
 744         case TRANSMITTER_UNIPHY_A:
 745                 enc110->base.preferred_engine = ENGINE_ID_DIGA;
 746         break;
 747         case TRANSMITTER_UNIPHY_B:
 748                 enc110->base.preferred_engine = ENGINE_ID_DIGB;
 749         break;
 750         case TRANSMITTER_UNIPHY_C:
 751                 enc110->base.preferred_engine = ENGINE_ID_DIGC;
 752         break;
 753         case TRANSMITTER_UNIPHY_D:
 754                 enc110->base.preferred_engine = ENGINE_ID_DIGD;
 755         break;
 756         case TRANSMITTER_UNIPHY_E:
 757                 enc110->base.preferred_engine = ENGINE_ID_DIGE;
 758         break;
 759         case TRANSMITTER_UNIPHY_F:
 760                 enc110->base.preferred_engine = ENGINE_ID_DIGF;
 761         break;
 762         case TRANSMITTER_UNIPHY_G:
 763                 enc110->base.preferred_engine = ENGINE_ID_DIGG;
 764         break;
 765         default:
 766                 ASSERT_CRITICAL(false);
 767                 enc110->base.preferred_engine = ENGINE_ID_UNKNOWN;
 768         }
 769
 770         /* default to one to mirror Windows behavior */
 771         enc110->base.features.flags.bits.HDMI_6GB_EN = 1;
 772
 773         result = bp_funcs->get_encoder_cap_info(enc110->base.ctx->dc_bios,
 774                                                 enc110->base.id, &bp_cap_info);
 775
 776         /* Override features with DCE-specific values */
 777         if (BP_RESULT_OK == result) {
 778                 enc110->base.features.flags.bits.IS_HBR2_CAPABLE =
 779                                 bp_cap_info.DP_HBR2_EN;
 780                 enc110->base.features.flags.bits.IS_HBR3_CAPABLE =
 781                                 bp_cap_info.DP_HBR3_EN;
 782                 enc110->base.features.flags.bits.HDMI_6GB_EN = bp_cap_info.HDMI_6GB_EN;
 783         } else {
 784                 DC_LOG_WARNING("%s: Failed to get encoder_cap_info from VBIOS with error code %d!\n",
 785                                 __func__,
 786                                 result);
 787         }
 788         if (enc110->base.ctx->dc->debug.hdmi20_disable) {
 789                 enc110->base.features.flags.bits.HDMI_6GB_EN = 0;
 790         }
 791 }
 792
 793 bool dce110_link_encoder_validate_output_with_stream(
 794         struct link_encoder *enc,
 795         const struct dc_stream_state *stream)
 796 {
 797         struct dce110_link_encoder *enc110 = TO_DCE110_LINK_ENC(enc);
 798         bool is_valid;
 799
 800         switch (stream->signal) {
 801         case SIGNAL_TYPE_DVI_SINGLE_LINK:
 802         case SIGNAL_TYPE_DVI_DUAL_LINK:
 803                 is_valid = dce110_link_encoder_validate_dvi_output(
 804                         enc110,
 805                         stream->sink->link->connector_signal,
 806                         stream->signal,
 807                         &stream->timing);
 808         break;
 809         case SIGNAL_TYPE_HDMI_TYPE_A:
 810                 is_valid = dce110_link_encoder_validate_hdmi_output(
 811                                 enc110,
 812                                 &stream->timing,
 813                                 stream->phy_pix_clk);
 814         break;
 815         case SIGNAL_TYPE_DISPLAY_PORT:
 816         case SIGNAL_TYPE_DISPLAY_PORT_MST:
 817                 is_valid = dce110_link_encoder_validate_dp_output(
 818                                         enc110, &stream->timing);
 819         break;
 820         case SIGNAL_TYPE_EDP:
 821         case SIGNAL_TYPE_LVDS:
 822                 is_valid =
 823                         (stream->timing.
 824                                 pixel_encoding == PIXEL_ENCODING_RGB) ? true : false;
 825         break;
 826         case SIGNAL_TYPE_VIRTUAL:
 827                 is_valid = true;
 828                 break;
 829         default:
 830                 is_valid = false;
 831         break;
 832         }
 833
 834         return is_valid;
 835 }
 836
 837 void dce110_link_encoder_hw_init(
 838         struct link_encoder *enc)
 839 {
 840         struct dce110_link_encoder *enc110 = TO_DCE110_LINK_ENC(enc);
 841         struct bp_transmitter_control cntl = { 0 };
 842         enum bp_result result;
 843
 844         cntl.action = TRANSMITTER_CONTROL_INIT;
 845         cntl.engine_id = ENGINE_ID_UNKNOWN;
 846         cntl.transmitter = enc110->base.transmitter;
 847         cntl.connector_obj_id = enc110->base.connector;
 848         cntl.lanes_number = LANE_COUNT_FOUR;
 849         cntl.coherent = false;
 850         cntl.hpd_sel = enc110->base.hpd_source;
 851
 852         if (enc110->base.connector.id == CONNECTOR_ID_EDP)
 853                 cntl.signal = SIGNAL_TYPE_EDP;
 854
 855         result = link_transmitter_control(enc110, &cntl);
 856
 857         if (result != BP_RESULT_OK) {
 858                 DC_LOG_ERROR("%s: Failed to execute VBIOS command table!\n",
 859                         __func__);
 860                 BREAK_TO_DEBUGGER();
 861                 return;
 862         }
 863
 864         if (enc110->base.connector.id == CONNECTOR_ID_LVDS) {
 865                 cntl.action = TRANSMITTER_CONTROL_BACKLIGHT_BRIGHTNESS;
 866
 867                 result = link_transmitter_control(enc110, &cntl);
 868
 869                 ASSERT(result == BP_RESULT_OK);
 870
 871         }
 872         aux_initialize(enc110);
 873
 874         /* reinitialize HPD.
 875          * hpd_initialize() will pass DIG_FE id to HW context.
 876          * All other routine within HW context will use fe_engine_offset
 877          * as DIG_FE id even caller pass DIG_FE id.
 878          * So this routine must be called first. */
 879         hpd_initialize(enc110);
 880 }
 881
 882 void dce110_link_encoder_destroy(struct link_encoder **enc)
 883 {
 884         kfree(TO_DCE110_LINK_ENC(*enc));
 885         *enc = NULL;
 886 }
 887
 888 void dce110_link_encoder_setup(
 889         struct link_encoder *enc,
 890         enum signal_type signal)
 891 {
 892         struct dce110_link_encoder *enc110 = TO_DCE110_LINK_ENC(enc);
 893
 894         switch (signal) {
 895         case SIGNAL_TYPE_EDP:
 896         case SIGNAL_TYPE_DISPLAY_PORT:
 897                 /* DP SST */
 898                 REG_UPDATE(DIG_BE_CNTL, DIG_MODE, 0);
 899                 break;
 900         case SIGNAL_TYPE_LVDS:
 901                 /* LVDS */
 902                 REG_UPDATE(DIG_BE_CNTL, DIG_MODE, 1);
 903                 break;
 904         case SIGNAL_TYPE_DVI_SINGLE_LINK:
 905         case SIGNAL_TYPE_DVI_DUAL_LINK:
 906                 /* TMDS-DVI */
 907                 REG_UPDATE(DIG_BE_CNTL, DIG_MODE, 2);
 908                 break;
 909         case SIGNAL_TYPE_HDMI_TYPE_A:
 910                 /* TMDS-HDMI */
 911                 REG_UPDATE(DIG_BE_CNTL, DIG_MODE, 3);
 912                 break;
 913         case SIGNAL_TYPE_DISPLAY_PORT_MST:
 914                 /* DP MST */
 915                 REG_UPDATE(DIG_BE_CNTL, DIG_MODE, 5);
 916                 break;
 917         default:
 918                 ASSERT_CRITICAL(false);
 919                 /* invalid mode ! */
 920                 break;
 921         }
 922
 923 }
 924
 925 /* TODO: still need depth or just pass in adjusted pixel clock? */
 926 void dce110_link_encoder_enable_tmds_output(
 927         struct link_encoder *enc,
 928         enum clock_source_id clock_source,
 929         enum dc_color_depth color_depth,
 930         enum signal_type signal,
 931         uint32_t pixel_clock)
 932 {
 933         struct dce110_link_encoder *enc110 = TO_DCE110_LINK_ENC(enc);
 934         struct bp_transmitter_control cntl = { 0 };
 935         enum bp_result result;
 936
 937         /* Enable the PHY */
 938         cntl.connector_obj_id = enc110->base.connector;
 939         cntl.action = TRANSMITTER_CONTROL_ENABLE;
 940         cntl.engine_id = enc->preferred_engine;
 941         cntl.transmitter = enc110->base.transmitter;
 942         cntl.pll_id = clock_source;
 943         cntl.signal = signal;
 944         if (cntl.signal == SIGNAL_TYPE_DVI_DUAL_LINK)
 945                 cntl.lanes_number = 8;
 946         else
 947                 cntl.lanes_number = 4;
 948
 949         cntl.hpd_sel = enc110->base.hpd_source;
 950
 951         cntl.pixel_clock = pixel_clock;
 952         cntl.color_depth = color_depth;
 953
 954         result = link_transmitter_control(enc110, &cntl);
 955
 956         if (result != BP_RESULT_OK) {
 957                 DC_LOG_ERROR("%s: Failed to execute VBIOS command table!\n",
 958                         __func__);
 959                 BREAK_TO_DEBUGGER();
 960         }
 961 }
 962
 963 /* TODO: still need depth or just pass in adjusted pixel clock? */
 964 void dce110_link_encoder_enable_lvds_output(
 965         struct link_encoder *enc,
 966         enum clock_source_id clock_source,
 967         uint32_t pixel_clock)
 968 {
 969         struct dce110_link_encoder *enc110 = TO_DCE110_LINK_ENC(enc);
 970         struct bp_transmitter_control cntl = { 0 };
 971         enum bp_result result;
 972
 973         /* Enable the PHY */
 974         cntl.connector_obj_id = enc110->base.connector;
 975         cntl.action = TRANSMITTER_CONTROL_ENABLE;
 976         cntl.engine_id = enc->preferred_engine;
 977         cntl.transmitter = enc110->base.transmitter;
 978         cntl.pll_id = clock_source;
 979         cntl.signal = SIGNAL_TYPE_LVDS;
 980         cntl.lanes_number = 4;
 981
 982         cntl.hpd_sel = enc110->base.hpd_source;
 983
 984         cntl.pixel_clock = pixel_clock;
 985
 986         result = link_transmitter_control(enc110, &cntl);
 987
 988         if (result != BP_RESULT_OK) {
 989                 DC_LOG_ERROR("%s: Failed to execute VBIOS command table!\n",
 990                         __func__);
 991                 BREAK_TO_DEBUGGER();
 992         }
 993 }
 994
 995 /* enables DP PHY output */
 996 void dce110_link_encoder_enable_dp_output(
 997         struct link_encoder *enc,
 998         const struct dc_link_settings *link_settings,
 999         enum clock_source_id clock_source)
1000 {
1001         struct dce110_link_encoder *enc110 = TO_DCE110_LINK_ENC(enc);
1002         struct bp_transmitter_control cntl = { 0 };
1003         enum bp_result result;
1004
1005         /* Enable the PHY */
1006
1007         /* number_of_lanes is used for pixel clock adjust,
1008          * but it's not passed to asic_control.
1009          * We need to set number of lanes manually.
1010          */
1011         configure_encoder(enc110, link_settings);
1012         cntl.connector_obj_id = enc110->base.connector;
1013         cntl.action = TRANSMITTER_CONTROL_ENABLE;
1014         cntl.engine_id = enc->preferred_engine;
1015         cntl.transmitter = enc110->base.transmitter;
1016         cntl.pll_id = clock_source;
1017         cntl.signal = SIGNAL_TYPE_DISPLAY_PORT;
1018         cntl.lanes_number = link_settings->lane_count;
1019         cntl.hpd_sel = enc110->base.hpd_source;
1020         cntl.pixel_clock = link_settings->link_rate
1021                                                 * LINK_RATE_REF_FREQ_IN_KHZ;
1022         /* TODO: check if undefined works */
1023         cntl.color_depth = COLOR_DEPTH_UNDEFINED;
1024
1025         result = link_transmitter_control(enc110, &cntl);
1026
1027         if (result != BP_RESULT_OK) {
1028                 DC_LOG_ERROR("%s: Failed to execute VBIOS command table!\n",
1029                         __func__);
1030                 BREAK_TO_DEBUGGER();
1031         }
1032 }
1033
1034 /* enables DP PHY output in MST mode */
1035 void dce110_link_encoder_enable_dp_mst_output(
1036         struct link_encoder *enc,
1037         const struct dc_link_settings *link_settings,
1038         enum clock_source_id clock_source)
1039 {
1040         struct dce110_link_encoder *enc110 = TO_DCE110_LINK_ENC(enc);
1041         struct bp_transmitter_control cntl = { 0 };
1042         enum bp_result result;
1043
1044         /* Enable the PHY */
1045
1046         /* number_of_lanes is used for pixel clock adjust,
1047          * but it's not passed to asic_control.
1048          * We need to set number of lanes manually.
1049          */
1050         configure_encoder(enc110, link_settings);
1051
1052         cntl.action = TRANSMITTER_CONTROL_ENABLE;
1053         cntl.engine_id = ENGINE_ID_UNKNOWN;
1054         cntl.transmitter = enc110->base.transmitter;
1055         cntl.pll_id = clock_source;
1056         cntl.signal = SIGNAL_TYPE_DISPLAY_PORT_MST;
1057         cntl.lanes_number = link_settings->lane_count;
1058         cntl.hpd_sel = enc110->base.hpd_source;
1059         cntl.pixel_clock = link_settings->link_rate
1060                                                 * LINK_RATE_REF_FREQ_IN_KHZ;
1061         /* TODO: check if undefined works */
1062         cntl.color_depth = COLOR_DEPTH_UNDEFINED;
1063
1064         result = link_transmitter_control(enc110, &cntl);
1065
1066         if (result != BP_RESULT_OK) {
1067                 DC_LOG_ERROR("%s: Failed to execute VBIOS command table!\n",
1068                         __func__);
1069                 BREAK_TO_DEBUGGER();
1070         }
1071 }
1072 /*
1073  * @brief
1074  * Disable transmitter and its encoder
1075  */
1076 void dce110_link_encoder_disable_output(
1077         struct link_encoder *enc,
1078         enum signal_type signal)
1079 {
1080         struct dce110_link_encoder *enc110 = TO_DCE110_LINK_ENC(enc);
1081         struct bp_transmitter_control cntl = { 0 };
1082         enum bp_result result;
1083
1084         if (!dce110_is_dig_enabled(enc)) {
1085                 /* OF_SKIP_POWER_DOWN_INACTIVE_ENCODER */
1086                 return;
1087         }
1088         /* Power-down RX and disable GPU PHY should be paired.
1089          * Disabling PHY without powering down RX may cause
1090          * symbol lock loss, on which we will get DP Sink interrupt. */
1091
1092         /* There is a case for the DP active dongles
1093          * where we want to disable the PHY but keep RX powered,
1094          * for those we need to ignore DP Sink interrupt
1095          * by checking lane count that has been set
1096          * on the last do_enable_output(). */
1097
1098         /* disable transmitter */
1099         cntl.action = TRANSMITTER_CONTROL_DISABLE;
1100         cntl.transmitter = enc110->base.transmitter;
1101         cntl.hpd_sel = enc110->base.hpd_source;
1102         cntl.signal = signal;
1103         cntl.connector_obj_id = enc110->base.connector;
1104
1105         result = link_transmitter_control(enc110, &cntl);
1106
1107         if (result != BP_RESULT_OK) {
1108                 DC_LOG_ERROR("%s: Failed to execute VBIOS command table!\n",
1109                         __func__);
1110                 BREAK_TO_DEBUGGER();
1111                 return;
1112         }
1113
1114         /* disable encoder */
1115         if (dc_is_dp_signal(signal))
1116                 link_encoder_disable(enc110);
1117 }
1118
1119 void dce110_link_encoder_dp_set_lane_settings(
1120         struct link_encoder *enc,
1121         const struct link_training_settings *link_settings)
1122 {
1123         struct dce110_link_encoder *enc110 = TO_DCE110_LINK_ENC(enc);
1124         union dpcd_training_lane_set training_lane_set = { { 0 } };
1125         int32_t lane = 0;
1126         struct bp_transmitter_control cntl = { 0 };
1127
1128         if (!link_settings) {
1129                 BREAK_TO_DEBUGGER();
1130                 return;
1131         }
1132
1133         cntl.action = TRANSMITTER_CONTROL_SET_VOLTAGE_AND_PREEMPASIS;
1134         cntl.transmitter = enc110->base.transmitter;
1135         cntl.connector_obj_id = enc110->base.connector;
1136         cntl.lanes_number = link_settings->link_settings.lane_count;
1137         cntl.hpd_sel = enc110->base.hpd_source;
1138         cntl.pixel_clock = link_settings->link_settings.link_rate *
1139                                                 LINK_RATE_REF_FREQ_IN_KHZ;
1140
1141         for (lane = 0; lane < link_settings->link_settings.lane_count; lane++) {
1142                 /* translate lane settings */
1143
1144                 training_lane_set.bits.VOLTAGE_SWING_SET =
1145                         link_settings->lane_settings[lane].VOLTAGE_SWING;
1146                 training_lane_set.bits.PRE_EMPHASIS_SET =
1147                         link_settings->lane_settings[lane].PRE_EMPHASIS;
1148
1149                 /* post cursor 2 setting only applies to HBR2 link rate */
1150                 if (link_settings->link_settings.link_rate == LINK_RATE_HIGH2) {
1151                         /* this is passed to VBIOS
1152                          * to program post cursor 2 level */
1153
1154                         training_lane_set.bits.POST_CURSOR2_SET =
1155                                 link_settings->lane_settings[lane].POST_CURSOR2;
1156                 }
1157
1158                 cntl.lane_select = lane;
1159                 cntl.lane_settings = training_lane_set.raw;
1160
1161                 /* call VBIOS table to set voltage swing and pre-emphasis */
1162                 link_transmitter_control(enc110, &cntl);
1163         }
1164 }
1165
1166 /* set DP PHY test and training patterns */
1167 void dce110_link_encoder_dp_set_phy_pattern(
1168         struct link_encoder *enc,
1169         const struct encoder_set_dp_phy_pattern_param *param)
1170 {
1171         struct dce110_link_encoder *enc110 = TO_DCE110_LINK_ENC(enc);
1172
1173         switch (param->dp_phy_pattern) {
1174         case DP_TEST_PATTERN_TRAINING_PATTERN1:
1175                 dce110_link_encoder_set_dp_phy_pattern_training_pattern(enc, 0);
1176                 break;
1177         case DP_TEST_PATTERN_TRAINING_PATTERN2:
1178                 dce110_link_encoder_set_dp_phy_pattern_training_pattern(enc, 1);
1179                 break;
1180         case DP_TEST_PATTERN_TRAINING_PATTERN3:
1181                 dce110_link_encoder_set_dp_phy_pattern_training_pattern(enc, 2);
1182                 break;
1183         case DP_TEST_PATTERN_TRAINING_PATTERN4:
1184                 dce110_link_encoder_set_dp_phy_pattern_training_pattern(enc, 3);
1185                 break;
1186         case DP_TEST_PATTERN_D102:
1187                 set_dp_phy_pattern_d102(enc110);
1188                 break;
1189         case DP_TEST_PATTERN_SYMBOL_ERROR:
1190                 set_dp_phy_pattern_symbol_error(enc110);
1191                 break;
1192         case DP_TEST_PATTERN_PRBS7:
1193                 set_dp_phy_pattern_prbs7(enc110);
1194                 break;
1195         case DP_TEST_PATTERN_80BIT_CUSTOM:
1196                 set_dp_phy_pattern_80bit_custom(
1197                         enc110, param->custom_pattern);
1198                 break;
1199         case DP_TEST_PATTERN_CP2520_1:
1200                 set_dp_phy_pattern_hbr2_compliance_cp2520_2(enc110, 1);
1201                 break;
1202         case DP_TEST_PATTERN_CP2520_2:
1203                 set_dp_phy_pattern_hbr2_compliance_cp2520_2(enc110, 2);
1204                 break;
1205         case DP_TEST_PATTERN_CP2520_3:
1206                 set_dp_phy_pattern_hbr2_compliance_cp2520_2(enc110, 3);
1207                 break;
1208         case DP_TEST_PATTERN_VIDEO_MODE: {
1209                 set_dp_phy_pattern_passthrough_mode(
1210                         enc110, param->dp_panel_mode);
1211                 break;
1212         }
1213
1214         default:
1215                 /* invalid phy pattern */
1216                 ASSERT_CRITICAL(false);
1217                 break;
1218         }
1219 }
1220
1221 static void fill_stream_allocation_row_info(
1222         const struct link_mst_stream_allocation *stream_allocation,
1223         uint32_t *src,
1224         uint32_t *slots)
1225 {
1226         const struct stream_encoder *stream_enc = stream_allocation->stream_enc;
1227
1228         if (stream_enc) {
1229                 *src = stream_enc->id;
1230                 *slots = stream_allocation->slot_count;
1231         } else {
1232                 *src = 0;
1233                 *slots = 0;
1234         }
1235 }
1236
1237 /* programs DP MST VC payload allocation */
1238 void dce110_link_encoder_update_mst_stream_allocation_table(
1239         struct link_encoder *enc,
1240         const struct link_mst_stream_allocation_table *table)
1241 {
1242         struct dce110_link_encoder *enc110 = TO_DCE110_LINK_ENC(enc);
1243         uint32_t value0 = 0;
1244         uint32_t value1 = 0;
1245         uint32_t value2 = 0;
1246         uint32_t slots = 0;
1247         uint32_t src = 0;
1248         uint32_t retries = 0;
1249
1250         /* For CZ, there are only 3 pipes. So Virtual channel is up 3.*/
1251
1252         /* --- Set MSE Stream Attribute -
1253          * Setup VC Payload Table on Tx Side,
1254          * Issue allocation change trigger
1255          * to commit payload on both tx and rx side */
1256
1257         /* we should clean-up table each time */
1258
1259         if (table->stream_count >= 1) {
1260                 fill_stream_allocation_row_info(
1261                         &table->stream_allocations[0],
1262                         &src,
1263                         &slots);
1264         } else {
1265                 src = 0;
1266                 slots = 0;
1267         }
1268
1269         REG_UPDATE_2(DP_MSE_SAT0,
1270                         DP_MSE_SAT_SRC0, src,
1271                         DP_MSE_SAT_SLOT_COUNT0, slots);
1272
1273         if (table->stream_count >= 2) {
1274                 fill_stream_allocation_row_info(
1275                         &table->stream_allocations[1],
1276                         &src,
1277                         &slots);
1278         } else {
1279                 src = 0;
1280                 slots = 0;
1281         }
1282
1283         REG_UPDATE_2(DP_MSE_SAT0,
1284                         DP_MSE_SAT_SRC1, src,
1285                         DP_MSE_SAT_SLOT_COUNT1, slots);
1286
1287         if (table->stream_count >= 3) {
1288                 fill_stream_allocation_row_info(
1289                         &table->stream_allocations[2],
1290                         &src,
1291                         &slots);
1292         } else {
1293                 src = 0;
1294                 slots = 0;
1295         }
1296
1297         REG_UPDATE_2(DP_MSE_SAT1,
1298                         DP_MSE_SAT_SRC2, src,
1299                         DP_MSE_SAT_SLOT_COUNT2, slots);
1300
1301         if (table->stream_count >= 4) {
1302                 fill_stream_allocation_row_info(
1303                         &table->stream_allocations[3],
1304                         &src,
1305                         &slots);
1306         } else {
1307                 src = 0;
1308                 slots = 0;
1309         }
1310
1311         REG_UPDATE_2(DP_MSE_SAT1,
1312                         DP_MSE_SAT_SRC3, src,
1313                         DP_MSE_SAT_SLOT_COUNT3, slots);
1314
1315         /* --- wait for transaction finish */
1316
1317         /* send allocation change trigger (ACT) ?
1318          * this step first sends the ACT,
1319          * then double buffers the SAT into the hardware
1320          * making the new allocation active on the DP MST mode link */
1321
1322
1323         /* DP_MSE_SAT_UPDATE:
1324          * 0 - No Action
1325          * 1 - Update SAT with trigger
1326          * 2 - Update SAT without trigger */
1327
1328         REG_UPDATE(DP_MSE_SAT_UPDATE,
1329                         DP_MSE_SAT_UPDATE, 1);
1330
1331         /* wait for update to complete
1332          * (i.e. DP_MSE_SAT_UPDATE field is reset to 0)
1333          * then wait for the transmission
1334          * of at least 16 MTP headers on immediate local link.
1335          * i.e. DP_MSE_16_MTP_KEEPOUT field (read only) is reset to 0
1336          * a value of 1 indicates that DP MST mode
1337          * is in the 16 MTP keepout region after a VC has been added.
1338          * MST stream bandwidth (VC rate) can be configured
1339          * after this bit is cleared */
1340
1341         do {
1342                 udelay(10);
1343
1344                 value0 = REG_READ(DP_MSE_SAT_UPDATE);
1345
1346                 REG_GET(DP_MSE_SAT_UPDATE,
1347                                 DP_MSE_SAT_UPDATE, &value1);
1348
1349                 REG_GET(DP_MSE_SAT_UPDATE,
1350                                 DP_MSE_16_MTP_KEEPOUT, &value2);
1351
1352                 /* bit field DP_MSE_SAT_UPDATE is set to 1 already */
1353                 if (!value1 && !value2)
1354                         break;
1355                 ++retries;
1356         } while (retries < DP_MST_UPDATE_MAX_RETRY);
1357 }
1358
1359 void dce110_link_encoder_connect_dig_be_to_fe(
1360         struct link_encoder *enc,
1361         enum engine_id engine,
1362         bool connect)
1363 {
1364         struct dce110_link_encoder *enc110 = TO_DCE110_LINK_ENC(enc);
1365         uint32_t field;
1366
1367         if (engine != ENGINE_ID_UNKNOWN) {
1368
1369                 REG_GET(DIG_BE_CNTL, DIG_FE_SOURCE_SELECT, &field);
1370
1371                 if (connect)
1372                         field |= get_frontend_source(engine);
1373                 else
1374                         field &= ~get_frontend_source(engine);
1375
1376                 REG_UPDATE(DIG_BE_CNTL, DIG_FE_SOURCE_SELECT, field);
1377         }
1378 }
1379
1380 void dce110_link_encoder_enable_hpd(struct link_encoder *enc)
1381 {
1382         struct dce110_link_encoder *enc110 = TO_DCE110_LINK_ENC(enc);
1383         struct dc_context *ctx = enc110->base.ctx;
1384         uint32_t addr = HPD_REG(DC_HPD_CONTROL);
1385         uint32_t hpd_enable = 0;
1386         uint32_t value = dm_read_reg(ctx, addr);
1387
1388         get_reg_field_value(hpd_enable, DC_HPD_CONTROL, DC_HPD_EN);
1389
1390         if (hpd_enable == 0)
1391                 set_reg_field_value(value, 1, DC_HPD_CONTROL, DC_HPD_EN);
1392 }
1393
1394 void dce110_link_encoder_disable_hpd(struct link_encoder *enc)
1395 {
1396         struct dce110_link_encoder *enc110 = TO_DCE110_LINK_ENC(enc);
1397         struct dc_context *ctx = enc110->base.ctx;
1398         uint32_t addr = HPD_REG(DC_HPD_CONTROL);
1399         uint32_t value = dm_read_reg(ctx, addr);
1400
1401         set_reg_field_value(value, 0, DC_HPD_CONTROL, DC_HPD_EN);
1402 }