drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c

   1 /*
   2  * Copyright 2012-15 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  *  and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: AMD
  23  *
  24  */
  25
  26 #include "dc_bios_types.h"
  27 #include "dce_stream_encoder.h"
  28 #include "reg_helper.h"
  29 #include "hw_shared.h"
  30
  31 #define DC_LOGGER \
  32                 enc110->base.ctx->logger
  33
  34
  35 #define REG(reg)\
  36         (enc110->regs->reg)
  37
  38 #undef FN
  39 #define FN(reg_name, field_name) \
  40         enc110->se_shift->field_name, enc110->se_mask->field_name
  41
  42 #define VBI_LINE_0 0
  43 #define DP_BLANK_MAX_RETRY 20
  44 #define HDMI_CLOCK_CHANNEL_RATE_MORE_340M 340000
  45
  46 #ifndef TMDS_CNTL__TMDS_PIXEL_ENCODING_MASK
  47         #define TMDS_CNTL__TMDS_PIXEL_ENCODING_MASK       0x00000010L
  48         #define TMDS_CNTL__TMDS_COLOR_FORMAT_MASK         0x00000300L
  49         #define TMDS_CNTL__TMDS_PIXEL_ENCODING__SHIFT     0x00000004
  50         #define TMDS_CNTL__TMDS_COLOR_FORMAT__SHIFT       0x00000008
  51 #endif
  52
  53 enum {
  54         DP_MST_UPDATE_MAX_RETRY = 50
  55 };
  56
  57 #define DCE110_SE(audio)\
  58         container_of(audio, struct dce110_stream_encoder, base)
  59
  60 #define CTX \
  61         enc110->base.ctx
  62
  63 static void dce110_update_generic_info_packet(
  64         struct dce110_stream_encoder *enc110,
  65         uint32_t packet_index,
  66         const struct dc_info_packet *info_packet)
  67 {
  68         uint32_t regval;
  69         /* TODOFPGA Figure out a proper number for max_retries polling for lock
  70          * use 50 for now.
  71          */
  72         uint32_t max_retries = 50;
  73
  74         /*we need turn on clock before programming AFMT block*/
  75         if (REG(AFMT_CNTL))
  76                 REG_UPDATE(AFMT_CNTL, AFMT_AUDIO_CLOCK_EN, 1);
  77
  78         if (REG(AFMT_VBI_PACKET_CONTROL1)) {
  79                 if (packet_index >= 8)
  80                         ASSERT(0);
  81
  82                 /* poll dig_update_lock is not locked -> asic internal signal
  83                  * assume otg master lock will unlock it
  84                  */
  85 /*              REG_WAIT(AFMT_VBI_PACKET_CONTROL, AFMT_GENERIC_LOCK_STATUS,
  86                                 0, 10, max_retries);*/
  87
  88                 /* check if HW reading GSP memory */
  89                 REG_WAIT(AFMT_VBI_PACKET_CONTROL, AFMT_GENERIC_CONFLICT,
  90                                 0, 10, max_retries);
  91
  92                 /* HW does is not reading GSP memory not reading too long ->
  93                  * something wrong. clear GPS memory access and notify?
  94                  * hw SW is writing to GSP memory
  95                  */
  96                 REG_UPDATE(AFMT_VBI_PACKET_CONTROL, AFMT_GENERIC_CONFLICT_CLR, 1);
  97         }
  98         /* choose which generic packet to use */
  99         {
 100                 regval = REG_READ(AFMT_VBI_PACKET_CONTROL);
 101                 REG_UPDATE(AFMT_VBI_PACKET_CONTROL,
 102                                 AFMT_GENERIC_INDEX, packet_index);
 103         }
 104
 105         /* write generic packet header
 106          * (4th byte is for GENERIC0 only) */
 107         {
 108                 REG_SET_4(AFMT_GENERIC_HDR, 0,
 109                                 AFMT_GENERIC_HB0, info_packet->hb0,
 110                                 AFMT_GENERIC_HB1, info_packet->hb1,
 111                                 AFMT_GENERIC_HB2, info_packet->hb2,
 112                                 AFMT_GENERIC_HB3, info_packet->hb3);
 113         }
 114
 115         /* write generic packet contents
 116          * (we never use last 4 bytes)
 117          * there are 8 (0-7) mmDIG0_AFMT_GENERIC0_x registers */
 118         {
 119                 const uint32_t *content =
 120                         (const uint32_t *) &info_packet->sb[0];
 121
 122                 REG_WRITE(AFMT_GENERIC_0, *content++);
 123                 REG_WRITE(AFMT_GENERIC_1, *content++);
 124                 REG_WRITE(AFMT_GENERIC_2, *content++);
 125                 REG_WRITE(AFMT_GENERIC_3, *content++);
 126                 REG_WRITE(AFMT_GENERIC_4, *content++);
 127                 REG_WRITE(AFMT_GENERIC_5, *content++);
 128                 REG_WRITE(AFMT_GENERIC_6, *content++);
 129                 REG_WRITE(AFMT_GENERIC_7, *content);
 130         }
 131
 132         if (!REG(AFMT_VBI_PACKET_CONTROL1)) {
 133                 /* force double-buffered packet update */
 134                 REG_UPDATE_2(AFMT_VBI_PACKET_CONTROL,
 135                         AFMT_GENERIC0_UPDATE, (packet_index == 0),
 136                         AFMT_GENERIC2_UPDATE, (packet_index == 2));
 137         }
 138 #if defined(CONFIG_DRM_AMD_DC_DCN1_0)
 139         if (REG(AFMT_VBI_PACKET_CONTROL1)) {
 140                 switch (packet_index) {
 141                 case 0:
 142                         REG_UPDATE(AFMT_VBI_PACKET_CONTROL1,
 143                                         AFMT_GENERIC0_FRAME_UPDATE, 1);
 144                         break;
 145                 case 1:
 146                         REG_UPDATE(AFMT_VBI_PACKET_CONTROL1,
 147                                         AFMT_GENERIC1_FRAME_UPDATE, 1);
 148                         break;
 149                 case 2:
 150                         REG_UPDATE(AFMT_VBI_PACKET_CONTROL1,
 151                                         AFMT_GENERIC2_FRAME_UPDATE, 1);
 152                         break;
 153                 case 3:
 154                         REG_UPDATE(AFMT_VBI_PACKET_CONTROL1,
 155                                         AFMT_GENERIC3_FRAME_UPDATE, 1);
 156                         break;
 157                 case 4:
 158                         REG_UPDATE(AFMT_VBI_PACKET_CONTROL1,
 159                                         AFMT_GENERIC4_FRAME_UPDATE, 1);
 160                         break;
 161                 case 5:
 162                         REG_UPDATE(AFMT_VBI_PACKET_CONTROL1,
 163                                         AFMT_GENERIC5_FRAME_UPDATE, 1);
 164                         break;
 165                 case 6:
 166                         REG_UPDATE(AFMT_VBI_PACKET_CONTROL1,
 167                                         AFMT_GENERIC6_FRAME_UPDATE, 1);
 168                         break;
 169                 case 7:
 170                         REG_UPDATE(AFMT_VBI_PACKET_CONTROL1,
 171                                         AFMT_GENERIC7_FRAME_UPDATE, 1);
 172                         break;
 173                 default:
 174                         break;
 175                 }
 176         }
 177 #endif
 178 }
 179
 180 static void dce110_update_hdmi_info_packet(
 181         struct dce110_stream_encoder *enc110,
 182         uint32_t packet_index,
 183         const struct dc_info_packet *info_packet)
 184 {
 185         uint32_t cont, send, line;
 186
 187         if (info_packet->valid) {
 188                 dce110_update_generic_info_packet(
 189                         enc110,
 190                         packet_index,
 191                         info_packet);
 192
 193                 /* enable transmission of packet(s) -
 194                  * packet transmission begins on the next frame */
 195                 cont = 1;
 196                 /* send packet(s) every frame */
 197                 send = 1;
 198                 /* select line number to send packets on */
 199                 line = 2;
 200         } else {
 201                 cont = 0;
 202                 send = 0;
 203                 line = 0;
 204         }
 205
 206         /* choose which generic packet control to use */
 207         switch (packet_index) {
 208         case 0:
 209                 REG_UPDATE_3(HDMI_GENERIC_PACKET_CONTROL0,
 210                                 HDMI_GENERIC0_CONT, cont,
 211                                 HDMI_GENERIC0_SEND, send,
 212                                 HDMI_GENERIC0_LINE, line);
 213                 break;
 214         case 1:
 215                 REG_UPDATE_3(HDMI_GENERIC_PACKET_CONTROL0,
 216                                 HDMI_GENERIC1_CONT, cont,
 217                                 HDMI_GENERIC1_SEND, send,
 218                                 HDMI_GENERIC1_LINE, line);
 219                 break;
 220         case 2:
 221                 REG_UPDATE_3(HDMI_GENERIC_PACKET_CONTROL1,
 222                                 HDMI_GENERIC0_CONT, cont,
 223                                 HDMI_GENERIC0_SEND, send,
 224                                 HDMI_GENERIC0_LINE, line);
 225                 break;
 226         case 3:
 227                 REG_UPDATE_3(HDMI_GENERIC_PACKET_CONTROL1,
 228                                 HDMI_GENERIC1_CONT, cont,
 229                                 HDMI_GENERIC1_SEND, send,
 230                                 HDMI_GENERIC1_LINE, line);
 231                 break;
 232 #if defined(CONFIG_DRM_AMD_DC_DCN1_0)
 233         case 4:
 234                 if (REG(HDMI_GENERIC_PACKET_CONTROL2))
 235                         REG_UPDATE_3(HDMI_GENERIC_PACKET_CONTROL2,
 236                                         HDMI_GENERIC0_CONT, cont,
 237                                         HDMI_GENERIC0_SEND, send,
 238                                         HDMI_GENERIC0_LINE, line);
 239                 break;
 240         case 5:
 241                 if (REG(HDMI_GENERIC_PACKET_CONTROL2))
 242                         REG_UPDATE_3(HDMI_GENERIC_PACKET_CONTROL2,
 243                                         HDMI_GENERIC1_CONT, cont,
 244                                         HDMI_GENERIC1_SEND, send,
 245                                         HDMI_GENERIC1_LINE, line);
 246                 break;
 247         case 6:
 248                 if (REG(HDMI_GENERIC_PACKET_CONTROL3))
 249                         REG_UPDATE_3(HDMI_GENERIC_PACKET_CONTROL3,
 250                                         HDMI_GENERIC0_CONT, cont,
 251                                         HDMI_GENERIC0_SEND, send,
 252                                         HDMI_GENERIC0_LINE, line);
 253                 break;
 254         case 7:
 255                 if (REG(HDMI_GENERIC_PACKET_CONTROL3))
 256                         REG_UPDATE_3(HDMI_GENERIC_PACKET_CONTROL3,
 257                                         HDMI_GENERIC1_CONT, cont,
 258                                         HDMI_GENERIC1_SEND, send,
 259                                         HDMI_GENERIC1_LINE, line);
 260                 break;
 261 #endif
 262         default:
 263                 /* invalid HW packet index */
 264                 DC_LOG_WARNING(
 265                         "Invalid HW packet index: %s()\n",
 266                         __func__);
 267                 return;
 268         }
 269 }
 270
 271 /* setup stream encoder in dp mode */
 272 static void dce110_stream_encoder_dp_set_stream_attribute(
 273         struct stream_encoder *enc,
 274         struct dc_crtc_timing *crtc_timing,
 275         enum dc_color_space output_color_space)
 276 {
 277 #if defined(CONFIG_DRM_AMD_DC_DCN1_0)
 278         uint32_t h_active_start;
 279         uint32_t v_active_start;
 280         uint32_t misc0 = 0;
 281         uint32_t misc1 = 0;
 282         uint32_t h_blank;
 283         uint32_t h_back_porch;
 284         uint8_t synchronous_clock = 0; /* asynchronous mode */
 285         uint8_t colorimetry_bpc;
 286         uint8_t dynamic_range_rgb = 0; /*full range*/
 287         uint8_t dynamic_range_ycbcr = 1; /*bt709*/
 288 #endif
 289
 290         struct dce110_stream_encoder *enc110 = DCE110STRENC_FROM_STRENC(enc);
 291         struct dc_crtc_timing hw_crtc_timing = *crtc_timing;
 292         if (hw_crtc_timing.flags.INTERLACE) {
 293                 /*the input timing is in VESA spec format with Interlace flag =1*/
 294                 hw_crtc_timing.v_total /= 2;
 295                 hw_crtc_timing.v_border_top /= 2;
 296                 hw_crtc_timing.v_addressable /= 2;
 297                 hw_crtc_timing.v_border_bottom /= 2;
 298                 hw_crtc_timing.v_front_porch /= 2;
 299                 hw_crtc_timing.v_sync_width /= 2;
 300         }
 301         /* set pixel encoding */
 302         switch (hw_crtc_timing.pixel_encoding) {
 303         case PIXEL_ENCODING_YCBCR422:
 304                 REG_UPDATE(DP_PIXEL_FORMAT, DP_PIXEL_ENCODING,
 305                                 DP_PIXEL_ENCODING_TYPE_YCBCR422);
 306                 break;
 307         case PIXEL_ENCODING_YCBCR444:
 308                 REG_UPDATE(DP_PIXEL_FORMAT, DP_PIXEL_ENCODING,
 309                                 DP_PIXEL_ENCODING_TYPE_YCBCR444);
 310
 311                 if (hw_crtc_timing.flags.Y_ONLY)
 312                         if (hw_crtc_timing.display_color_depth != COLOR_DEPTH_666)
 313                                 /* HW testing only, no use case yet.
 314                                  * Color depth of Y-only could be
 315                                  * 8, 10, 12, 16 bits */
 316                                 REG_UPDATE(DP_PIXEL_FORMAT, DP_PIXEL_ENCODING,
 317                                                 DP_PIXEL_ENCODING_TYPE_Y_ONLY);
 318                 /* Note: DP_MSA_MISC1 bit 7 is the indicator
 319                  * of Y-only mode.
 320                  * This bit is set in HW if register
 321                  * DP_PIXEL_ENCODING is programmed to 0x4 */
 322                 break;
 323         case PIXEL_ENCODING_YCBCR420:
 324                 REG_UPDATE(DP_PIXEL_FORMAT, DP_PIXEL_ENCODING,
 325                                 DP_PIXEL_ENCODING_TYPE_YCBCR420);
 326                 if (enc110->se_mask->DP_VID_M_DOUBLE_VALUE_EN)
 327                         REG_UPDATE(DP_VID_TIMING, DP_VID_M_DOUBLE_VALUE_EN, 1);
 328
 329 #if defined(CONFIG_DRM_AMD_DC_DCN1_0)
 330                 if (enc110->se_mask->DP_VID_N_MUL)
 331                         REG_UPDATE(DP_VID_TIMING, DP_VID_N_MUL, 1);
 332 #endif
 333                 break;
 334         default:
 335                 REG_UPDATE(DP_PIXEL_FORMAT, DP_PIXEL_ENCODING,
 336                                 DP_PIXEL_ENCODING_TYPE_RGB444);
 337                 break;
 338         }
 339
 340 #if defined(CONFIG_DRM_AMD_DC_DCN1_0)
 341         if (REG(DP_MSA_MISC))
 342                 misc1 = REG_READ(DP_MSA_MISC);
 343 #endif
 344
 345         /* set color depth */
 346
 347         switch (hw_crtc_timing.display_color_depth) {
 348         case COLOR_DEPTH_666:
 349                 REG_UPDATE(DP_PIXEL_FORMAT, DP_COMPONENT_DEPTH,
 350                                 0);
 351                 break;
 352         case COLOR_DEPTH_888:
 353                 REG_UPDATE(DP_PIXEL_FORMAT, DP_COMPONENT_DEPTH,
 354                                 DP_COMPONENT_PIXEL_DEPTH_8BPC);
 355                 break;
 356         case COLOR_DEPTH_101010:
 357                 REG_UPDATE(DP_PIXEL_FORMAT, DP_COMPONENT_DEPTH,
 358                                 DP_COMPONENT_PIXEL_DEPTH_10BPC);
 359
 360                 break;
 361         case COLOR_DEPTH_121212:
 362                 REG_UPDATE(DP_PIXEL_FORMAT, DP_COMPONENT_DEPTH,
 363                                 DP_COMPONENT_PIXEL_DEPTH_12BPC);
 364                 break;
 365         default:
 366                 REG_UPDATE(DP_PIXEL_FORMAT, DP_COMPONENT_DEPTH,
 367                                 DP_COMPONENT_PIXEL_DEPTH_6BPC);
 368                 break;
 369         }
 370
 371         /* set dynamic range and YCbCr range */
 372
 373
 374 #if defined(CONFIG_DRM_AMD_DC_DCN1_0)
 375         switch (hw_crtc_timing.display_color_depth) {
 376         case COLOR_DEPTH_666:
 377                 colorimetry_bpc = 0;
 378                 break;
 379         case COLOR_DEPTH_888:
 380                 colorimetry_bpc = 1;
 381                 break;
 382         case COLOR_DEPTH_101010:
 383                 colorimetry_bpc = 2;
 384                 break;
 385         case COLOR_DEPTH_121212:
 386                 colorimetry_bpc = 3;
 387                 break;
 388         default:
 389                 colorimetry_bpc = 0;
 390                 break;
 391         }
 392
 393         misc0 = misc0 | synchronous_clock;
 394         misc0 = colorimetry_bpc << 5;
 395
 396         if (REG(DP_MSA_TIMING_PARAM1)) {
 397                 switch (output_color_space) {
 398                 case COLOR_SPACE_SRGB:
 399                         misc0 = misc0 | 0x0;
 400                         misc1 = misc1 & ~0x80; /* bit7 = 0*/
 401                         dynamic_range_rgb = 0; /*full range*/
 402                         break;
 403                 case COLOR_SPACE_SRGB_LIMITED:
 404                         misc0 = misc0 | 0x8; /* bit3=1 */
 405                         misc1 = misc1 & ~0x80; /* bit7 = 0*/
 406                         dynamic_range_rgb = 1; /*limited range*/
 407                         break;
 408                 case COLOR_SPACE_YCBCR601:
 409                 case COLOR_SPACE_YCBCR601_LIMITED:
 410                         misc0 = misc0 | 0x8; /* bit3=1, bit4=0 */
 411                         misc1 = misc1 & ~0x80; /* bit7 = 0*/
 412                         dynamic_range_ycbcr = 0; /*bt601*/
 413                         if (hw_crtc_timing.pixel_encoding == PIXEL_ENCODING_YCBCR422)
 414                                 misc0 = misc0 | 0x2; /* bit2=0, bit1=1 */
 415                         else if (hw_crtc_timing.pixel_encoding == PIXEL_ENCODING_YCBCR444)
 416                                 misc0 = misc0 | 0x4; /* bit2=1, bit1=0 */
 417                         break;
 418                 case COLOR_SPACE_YCBCR709:
 419                 case COLOR_SPACE_YCBCR709_LIMITED:
 420                         misc0 = misc0 | 0x18; /* bit3=1, bit4=1 */
 421                         misc1 = misc1 & ~0x80; /* bit7 = 0*/
 422                         dynamic_range_ycbcr = 1; /*bt709*/
 423                         if (hw_crtc_timing.pixel_encoding == PIXEL_ENCODING_YCBCR422)
 424                                 misc0 = misc0 | 0x2; /* bit2=0, bit1=1 */
 425                         else if (hw_crtc_timing.pixel_encoding == PIXEL_ENCODING_YCBCR444)
 426                                 misc0 = misc0 | 0x4; /* bit2=1, bit1=0 */
 427                         break;
 428                 case COLOR_SPACE_2020_RGB_LIMITEDRANGE:
 429                         dynamic_range_rgb = 1; /*limited range*/
 430                         break;
 431                 case COLOR_SPACE_2020_RGB_FULLRANGE:
 432                 case COLOR_SPACE_2020_YCBCR:
 433                 case COLOR_SPACE_XR_RGB:
 434                 case COLOR_SPACE_MSREF_SCRGB:
 435                 case COLOR_SPACE_ADOBERGB:
 436                 case COLOR_SPACE_DCIP3:
 437                 case COLOR_SPACE_XV_YCC_709:
 438                 case COLOR_SPACE_XV_YCC_601:
 439                 case COLOR_SPACE_DISPLAYNATIVE:
 440                 case COLOR_SPACE_DOLBYVISION:
 441                 case COLOR_SPACE_APPCTRL:
 442                 case COLOR_SPACE_CUSTOMPOINTS:
 443                 case COLOR_SPACE_UNKNOWN:
 444                         /* do nothing */
 445                         break;
 446                 }
 447                 if (enc110->se_mask->DP_DYN_RANGE && enc110->se_mask->DP_YCBCR_RANGE)
 448                         REG_UPDATE_2(
 449                                 DP_PIXEL_FORMAT,
 450                                 DP_DYN_RANGE, dynamic_range_rgb,
 451                                 DP_YCBCR_RANGE, dynamic_range_ycbcr);
 452
 453 #if defined(CONFIG_DRM_AMD_DC_DCN1_0)
 454                 if (REG(DP_MSA_COLORIMETRY))
 455                         REG_SET(DP_MSA_COLORIMETRY, 0, DP_MSA_MISC0, misc0);
 456
 457                 if (REG(DP_MSA_MISC))
 458                         REG_WRITE(DP_MSA_MISC, misc1);   /* MSA_MISC1 */
 459
 460         /* dcn new register
 461          * dc_crtc_timing is vesa dmt struct. data from edid
 462          */
 463                 if (REG(DP_MSA_TIMING_PARAM1))
 464                         REG_SET_2(DP_MSA_TIMING_PARAM1, 0,
 465                                         DP_MSA_HTOTAL, hw_crtc_timing.h_total,
 466                                         DP_MSA_VTOTAL, hw_crtc_timing.v_total);
 467 #endif
 468
 469                 /* calcuate from vesa timing parameters
 470                  * h_active_start related to leading edge of sync
 471                  */
 472
 473                 h_blank = hw_crtc_timing.h_total - hw_crtc_timing.h_border_left -
 474                                 hw_crtc_timing.h_addressable - hw_crtc_timing.h_border_right;
 475
 476                 h_back_porch = h_blank - hw_crtc_timing.h_front_porch -
 477                                 hw_crtc_timing.h_sync_width;
 478
 479                 /* start at begining of left border */
 480                 h_active_start = hw_crtc_timing.h_sync_width + h_back_porch;
 481
 482
 483                 v_active_start = hw_crtc_timing.v_total - hw_crtc_timing.v_border_top -
 484                                 hw_crtc_timing.v_addressable - hw_crtc_timing.v_border_bottom -
 485                                 hw_crtc_timing.v_front_porch;
 486
 487
 488 #if defined(CONFIG_DRM_AMD_DC_DCN1_0)
 489                 /* start at begining of left border */
 490                 if (REG(DP_MSA_TIMING_PARAM2))
 491                         REG_SET_2(DP_MSA_TIMING_PARAM2, 0,
 492                                 DP_MSA_HSTART, h_active_start,
 493                                 DP_MSA_VSTART, v_active_start);
 494
 495                 if (REG(DP_MSA_TIMING_PARAM3))
 496                         REG_SET_4(DP_MSA_TIMING_PARAM3, 0,
 497                                         DP_MSA_HSYNCWIDTH,
 498                                         hw_crtc_timing.h_sync_width,
 499                                         DP_MSA_HSYNCPOLARITY,
 500                                         !hw_crtc_timing.flags.HSYNC_POSITIVE_POLARITY,
 501                                         DP_MSA_VSYNCWIDTH,
 502                                         hw_crtc_timing.v_sync_width,
 503                                         DP_MSA_VSYNCPOLARITY,
 504                                         !hw_crtc_timing.flags.VSYNC_POSITIVE_POLARITY);
 505
 506                 /* HWDITH include border or overscan */
 507                 if (REG(DP_MSA_TIMING_PARAM4))
 508                         REG_SET_2(DP_MSA_TIMING_PARAM4, 0,
 509                                 DP_MSA_HWIDTH, hw_crtc_timing.h_border_left +
 510                                 hw_crtc_timing.h_addressable + hw_crtc_timing.h_border_right,
 511                                 DP_MSA_VHEIGHT, hw_crtc_timing.v_border_top +
 512                                 hw_crtc_timing.v_addressable + hw_crtc_timing.v_border_bottom);
 513 #endif
 514         }
 515 #endif
 516 }
 517
 518 static void dce110_stream_encoder_set_stream_attribute_helper(
 519                 struct dce110_stream_encoder *enc110,
 520                 struct dc_crtc_timing *crtc_timing)
 521 {
 522         if (enc110->regs->TMDS_CNTL) {
 523                 switch (crtc_timing->pixel_encoding) {
 524                 case PIXEL_ENCODING_YCBCR422:
 525                         REG_UPDATE(TMDS_CNTL, TMDS_PIXEL_ENCODING, 1);
 526                         break;
 527                 default:
 528                         REG_UPDATE(TMDS_CNTL, TMDS_PIXEL_ENCODING, 0);
 529                         break;
 530                 }
 531                 REG_UPDATE(TMDS_CNTL, TMDS_COLOR_FORMAT, 0);
 532         } else if (enc110->regs->DIG_FE_CNTL) {
 533                 switch (crtc_timing->pixel_encoding) {
 534                 case PIXEL_ENCODING_YCBCR422:
 535                         REG_UPDATE(DIG_FE_CNTL, TMDS_PIXEL_ENCODING, 1);
 536                         break;
 537                 default:
 538                         REG_UPDATE(DIG_FE_CNTL, TMDS_PIXEL_ENCODING, 0);
 539                         break;
 540                 }
 541                 REG_UPDATE(DIG_FE_CNTL, TMDS_COLOR_FORMAT, 0);
 542         }
 543
 544 }
 545
 546 /* setup stream encoder in hdmi mode */
 547 static void dce110_stream_encoder_hdmi_set_stream_attribute(
 548         struct stream_encoder *enc,
 549         struct dc_crtc_timing *crtc_timing,
 550         int actual_pix_clk_khz,
 551         bool enable_audio)
 552 {
 553         struct dce110_stream_encoder *enc110 = DCE110STRENC_FROM_STRENC(enc);
 554         struct bp_encoder_control cntl = {0};
 555
 556         cntl.action = ENCODER_CONTROL_SETUP;
 557         cntl.engine_id = enc110->base.id;
 558         cntl.signal = SIGNAL_TYPE_HDMI_TYPE_A;
 559         cntl.enable_dp_audio = enable_audio;
 560         cntl.pixel_clock = actual_pix_clk_khz;
 561         cntl.lanes_number = LANE_COUNT_FOUR;
 562
 563         if (enc110->base.bp->funcs->encoder_control(
 564                         enc110->base.bp, &cntl) != BP_RESULT_OK)
 565                 return;
 566
 567         dce110_stream_encoder_set_stream_attribute_helper(enc110, crtc_timing);
 568
 569         /* setup HDMI engine */
 570         if (!enc110->se_mask->HDMI_DATA_SCRAMBLE_EN) {
 571                 REG_UPDATE_3(HDMI_CONTROL,
 572                         HDMI_PACKET_GEN_VERSION, 1,
 573                         HDMI_KEEPOUT_MODE, 1,
 574                         HDMI_DEEP_COLOR_ENABLE, 0);
 575         } else if (enc110->regs->DIG_FE_CNTL) {
 576                 REG_UPDATE_5(HDMI_CONTROL,
 577                         HDMI_PACKET_GEN_VERSION, 1,
 578                         HDMI_KEEPOUT_MODE, 1,
 579                         HDMI_DEEP_COLOR_ENABLE, 0,
 580                         HDMI_DATA_SCRAMBLE_EN, 0,
 581                         HDMI_CLOCK_CHANNEL_RATE, 0);
 582         }
 583
 584         switch (crtc_timing->display_color_depth) {
 585         case COLOR_DEPTH_888:
 586                 REG_UPDATE(HDMI_CONTROL, HDMI_DEEP_COLOR_DEPTH, 0);
 587                 break;
 588         case COLOR_DEPTH_101010:
 589                 if (crtc_timing->pixel_encoding == PIXEL_ENCODING_YCBCR422) {
 590                         REG_UPDATE_2(HDMI_CONTROL,
 591                                         HDMI_DEEP_COLOR_DEPTH, 1,
 592                                         HDMI_DEEP_COLOR_ENABLE, 0);
 593                 } else {
 594                         REG_UPDATE_2(HDMI_CONTROL,
 595                                         HDMI_DEEP_COLOR_DEPTH, 1,
 596                                         HDMI_DEEP_COLOR_ENABLE, 1);
 597                         }
 598                 break;
 599         case COLOR_DEPTH_121212:
 600                 if (crtc_timing->pixel_encoding == PIXEL_ENCODING_YCBCR422) {
 601                         REG_UPDATE_2(HDMI_CONTROL,
 602                                         HDMI_DEEP_COLOR_DEPTH, 2,
 603                                         HDMI_DEEP_COLOR_ENABLE, 0);
 604                 } else {
 605                         REG_UPDATE_2(HDMI_CONTROL,
 606                                         HDMI_DEEP_COLOR_DEPTH, 2,
 607                                         HDMI_DEEP_COLOR_ENABLE, 1);
 608                         }
 609                 break;
 610         case COLOR_DEPTH_161616:
 611                 REG_UPDATE_2(HDMI_CONTROL,
 612                                 HDMI_DEEP_COLOR_DEPTH, 3,
 613                                 HDMI_DEEP_COLOR_ENABLE, 1);
 614                 break;
 615         default:
 616                 break;
 617         }
 618
 619         if (enc110->se_mask->HDMI_DATA_SCRAMBLE_EN) {
 620                 if (actual_pix_clk_khz >= HDMI_CLOCK_CHANNEL_RATE_MORE_340M) {
 621                         /* enable HDMI data scrambler
 622                          * HDMI_CLOCK_CHANNEL_RATE_MORE_340M
 623                          * Clock channel frequency is 1/4 of character rate.
 624                          */
 625                         REG_UPDATE_2(HDMI_CONTROL,
 626                                 HDMI_DATA_SCRAMBLE_EN, 1,
 627                                 HDMI_CLOCK_CHANNEL_RATE, 1);
 628                 } else if (crtc_timing->flags.LTE_340MCSC_SCRAMBLE) {
 629
 630                         /* TODO: New feature for DCE11, still need to implement */
 631
 632                         /* enable HDMI data scrambler
 633                          * HDMI_CLOCK_CHANNEL_FREQ_EQUAL_TO_CHAR_RATE
 634                          * Clock channel frequency is the same
 635                          * as character rate
 636                          */
 637                         REG_UPDATE_2(HDMI_CONTROL,
 638                                 HDMI_DATA_SCRAMBLE_EN, 1,
 639                                 HDMI_CLOCK_CHANNEL_RATE, 0);
 640                 }
 641         }
 642
 643         REG_UPDATE_3(HDMI_VBI_PACKET_CONTROL,
 644                 HDMI_GC_CONT, 1,
 645                 HDMI_GC_SEND, 1,
 646                 HDMI_NULL_SEND, 1);
 647
 648         /* following belongs to audio */
 649         REG_UPDATE(HDMI_INFOFRAME_CONTROL0, HDMI_AUDIO_INFO_SEND, 1);
 650
 651         REG_UPDATE(AFMT_INFOFRAME_CONTROL0, AFMT_AUDIO_INFO_UPDATE, 1);
 652
 653         REG_UPDATE(HDMI_INFOFRAME_CONTROL1, HDMI_AUDIO_INFO_LINE,
 654                                 VBI_LINE_0 + 2);
 655
 656         REG_UPDATE(HDMI_GC, HDMI_GC_AVMUTE, 0);
 657
 658 }
 659
 660 /* setup stream encoder in dvi mode */
 661 static void dce110_stream_encoder_dvi_set_stream_attribute(
 662         struct stream_encoder *enc,
 663         struct dc_crtc_timing *crtc_timing,
 664         bool is_dual_link)
 665 {
 666         struct dce110_stream_encoder *enc110 = DCE110STRENC_FROM_STRENC(enc);
 667         struct bp_encoder_control cntl = {0};
 668
 669         cntl.action = ENCODER_CONTROL_SETUP;
 670         cntl.engine_id = enc110->base.id;
 671         cntl.signal = is_dual_link ?
 672                         SIGNAL_TYPE_DVI_DUAL_LINK : SIGNAL_TYPE_DVI_SINGLE_LINK;
 673         cntl.enable_dp_audio = false;
 674         cntl.pixel_clock = crtc_timing->pix_clk_100hz / 10;
 675         cntl.lanes_number = (is_dual_link) ? LANE_COUNT_EIGHT : LANE_COUNT_FOUR;
 676
 677         if (enc110->base.bp->funcs->encoder_control(
 678                         enc110->base.bp, &cntl) != BP_RESULT_OK)
 679                 return;
 680
 681         ASSERT(crtc_timing->pixel_encoding == PIXEL_ENCODING_RGB);
 682         ASSERT(crtc_timing->display_color_depth == COLOR_DEPTH_888);
 683         dce110_stream_encoder_set_stream_attribute_helper(enc110, crtc_timing);
 684 }
 685
 686 /* setup stream encoder in LVDS mode */
 687 static void dce110_stream_encoder_lvds_set_stream_attribute(
 688         struct stream_encoder *enc,
 689         struct dc_crtc_timing *crtc_timing)
 690 {
 691         struct dce110_stream_encoder *enc110 = DCE110STRENC_FROM_STRENC(enc);
 692         struct bp_encoder_control cntl = {0};
 693
 694         cntl.action = ENCODER_CONTROL_SETUP;
 695         cntl.engine_id = enc110->base.id;
 696         cntl.signal = SIGNAL_TYPE_LVDS;
 697         cntl.enable_dp_audio = false;
 698         cntl.pixel_clock = crtc_timing->pix_clk_100hz / 10;
 699         cntl.lanes_number = LANE_COUNT_FOUR;
 700
 701         if (enc110->base.bp->funcs->encoder_control(
 702                         enc110->base.bp, &cntl) != BP_RESULT_OK)
 703                 return;
 704
 705         ASSERT(crtc_timing->pixel_encoding == PIXEL_ENCODING_RGB);
 706 }
 707
 708 static void dce110_stream_encoder_set_mst_bandwidth(
 709         struct stream_encoder *enc,
 710         struct fixed31_32 avg_time_slots_per_mtp)
 711 {
 712         struct dce110_stream_encoder *enc110 = DCE110STRENC_FROM_STRENC(enc);
 713         uint32_t x = dc_fixpt_floor(
 714                 avg_time_slots_per_mtp);
 715         uint32_t y = dc_fixpt_ceil(
 716                 dc_fixpt_shl(
 717                         dc_fixpt_sub_int(
 718                                 avg_time_slots_per_mtp,
 719                                 x),
 720                         26));
 721
 722         {
 723                 REG_SET_2(DP_MSE_RATE_CNTL, 0,
 724                         DP_MSE_RATE_X, x,
 725                         DP_MSE_RATE_Y, y);
 726         }
 727
 728         /* wait for update to be completed on the link */
 729         /* i.e. DP_MSE_RATE_UPDATE_PENDING field (read only) */
 730         /* is reset to 0 (not pending) */
 731         REG_WAIT(DP_MSE_RATE_UPDATE, DP_MSE_RATE_UPDATE_PENDING,
 732                         0,
 733                         10, DP_MST_UPDATE_MAX_RETRY);
 734 }
 735
 736 static void dce110_stream_encoder_update_hdmi_info_packets(
 737         struct stream_encoder *enc,
 738         const struct encoder_info_frame *info_frame)
 739 {
 740         struct dce110_stream_encoder *enc110 = DCE110STRENC_FROM_STRENC(enc);
 741
 742         if (enc110->se_mask->HDMI_AVI_INFO_CONT &&
 743                         enc110->se_mask->HDMI_AVI_INFO_SEND) {
 744
 745                 if (info_frame->avi.valid) {
 746                         const uint32_t *content =
 747                                 (const uint32_t *) &info_frame->avi.sb[0];
 748                         /*we need turn on clock before programming AFMT block*/
 749                         if (REG(AFMT_CNTL))
 750                                 REG_UPDATE(AFMT_CNTL, AFMT_AUDIO_CLOCK_EN, 1);
 751
 752                         REG_WRITE(AFMT_AVI_INFO0, content[0]);
 753
 754                         REG_WRITE(AFMT_AVI_INFO1, content[1]);
 755
 756                         REG_WRITE(AFMT_AVI_INFO2, content[2]);
 757
 758                         REG_WRITE(AFMT_AVI_INFO3, content[3]);
 759
 760                         REG_UPDATE(AFMT_AVI_INFO3, AFMT_AVI_INFO_VERSION,
 761                                                 info_frame->avi.hb1);
 762
 763                         REG_UPDATE_2(HDMI_INFOFRAME_CONTROL0,
 764                                         HDMI_AVI_INFO_SEND, 1,
 765                                         HDMI_AVI_INFO_CONT, 1);
 766
 767                         REG_UPDATE(HDMI_INFOFRAME_CONTROL1, HDMI_AVI_INFO_LINE,
 768                                                         VBI_LINE_0 + 2);
 769
 770                 } else {
 771                         REG_UPDATE_2(HDMI_INFOFRAME_CONTROL0,
 772                                 HDMI_AVI_INFO_SEND, 0,
 773                                 HDMI_AVI_INFO_CONT, 0);
 774                 }
 775         }
 776
 777         if (enc110->se_mask->HDMI_AVI_INFO_CONT &&
 778                         enc110->se_mask->HDMI_AVI_INFO_SEND) {
 779                 dce110_update_hdmi_info_packet(enc110, 0, &info_frame->vendor);
 780                 dce110_update_hdmi_info_packet(enc110, 1, &info_frame->gamut);
 781                 dce110_update_hdmi_info_packet(enc110, 2, &info_frame->spd);
 782                 dce110_update_hdmi_info_packet(enc110, 3, &info_frame->hdrsmd);
 783         }
 784
 785 #if defined(CONFIG_DRM_AMD_DC_DCN1_0)
 786         if (enc110->se_mask->HDMI_DB_DISABLE) {
 787                 /* for bring up, disable dp double  TODO */
 788                 if (REG(HDMI_DB_CONTROL))
 789                         REG_UPDATE(HDMI_DB_CONTROL, HDMI_DB_DISABLE, 1);
 790
 791                 dce110_update_hdmi_info_packet(enc110, 0, &info_frame->avi);
 792                 dce110_update_hdmi_info_packet(enc110, 1, &info_frame->vendor);
 793                 dce110_update_hdmi_info_packet(enc110, 2, &info_frame->gamut);
 794                 dce110_update_hdmi_info_packet(enc110, 3, &info_frame->spd);
 795                 dce110_update_hdmi_info_packet(enc110, 4, &info_frame->hdrsmd);
 796         }
 797 #endif
 798 }
 799
 800 static void dce110_stream_encoder_stop_hdmi_info_packets(
 801         struct stream_encoder *enc)
 802 {
 803         struct dce110_stream_encoder *enc110 = DCE110STRENC_FROM_STRENC(enc);
 804
 805         /* stop generic packets 0 & 1 on HDMI */
 806         REG_SET_6(HDMI_GENERIC_PACKET_CONTROL0, 0,
 807                 HDMI_GENERIC1_CONT, 0,
 808                 HDMI_GENERIC1_LINE, 0,
 809                 HDMI_GENERIC1_SEND, 0,
 810                 HDMI_GENERIC0_CONT, 0,
 811                 HDMI_GENERIC0_LINE, 0,
 812                 HDMI_GENERIC0_SEND, 0);
 813
 814         /* stop generic packets 2 & 3 on HDMI */
 815         REG_SET_6(HDMI_GENERIC_PACKET_CONTROL1, 0,
 816                 HDMI_GENERIC0_CONT, 0,
 817                 HDMI_GENERIC0_LINE, 0,
 818                 HDMI_GENERIC0_SEND, 0,
 819                 HDMI_GENERIC1_CONT, 0,
 820                 HDMI_GENERIC1_LINE, 0,
 821                 HDMI_GENERIC1_SEND, 0);
 822
 823 #if defined(CONFIG_DRM_AMD_DC_DCN1_0)
 824         /* stop generic packets 2 & 3 on HDMI */
 825         if (REG(HDMI_GENERIC_PACKET_CONTROL2))
 826                 REG_SET_6(HDMI_GENERIC_PACKET_CONTROL2, 0,
 827                         HDMI_GENERIC0_CONT, 0,
 828                         HDMI_GENERIC0_LINE, 0,
 829                         HDMI_GENERIC0_SEND, 0,
 830                         HDMI_GENERIC1_CONT, 0,
 831                         HDMI_GENERIC1_LINE, 0,
 832                         HDMI_GENERIC1_SEND, 0);
 833
 834         if (REG(HDMI_GENERIC_PACKET_CONTROL3))
 835                 REG_SET_6(HDMI_GENERIC_PACKET_CONTROL3, 0,
 836                         HDMI_GENERIC0_CONT, 0,
 837                         HDMI_GENERIC0_LINE, 0,
 838                         HDMI_GENERIC0_SEND, 0,
 839                         HDMI_GENERIC1_CONT, 0,
 840                         HDMI_GENERIC1_LINE, 0,
 841                         HDMI_GENERIC1_SEND, 0);
 842 #endif
 843 }
 844
 845 static void dce110_stream_encoder_update_dp_info_packets(
 846         struct stream_encoder *enc,
 847         const struct encoder_info_frame *info_frame)
 848 {
 849         struct dce110_stream_encoder *enc110 = DCE110STRENC_FROM_STRENC(enc);
 850         uint32_t value = 0;
 851
 852         if (info_frame->vsc.valid)
 853                 dce110_update_generic_info_packet(
 854                                         enc110,
 855                                         0,  /* packetIndex */
 856                                         &info_frame->vsc);
 857
 858         if (info_frame->spd.valid)
 859                 dce110_update_generic_info_packet(
 860                                 enc110,
 861                                 2,  /* packetIndex */
 862                                 &info_frame->spd);
 863
 864         if (info_frame->hdrsmd.valid)
 865                 dce110_update_generic_info_packet(
 866                                 enc110,
 867                                 3,  /* packetIndex */
 868                                 &info_frame->hdrsmd);
 869
 870         /* enable/disable transmission of packet(s).
 871         *  If enabled, packet transmission begins on the next frame
 872         */
 873         REG_UPDATE(DP_SEC_CNTL, DP_SEC_GSP0_ENABLE, info_frame->vsc.valid);
 874         REG_UPDATE(DP_SEC_CNTL, DP_SEC_GSP2_ENABLE, info_frame->spd.valid);
 875         REG_UPDATE(DP_SEC_CNTL, DP_SEC_GSP3_ENABLE, info_frame->hdrsmd.valid);
 876
 877         /* This bit is the master enable bit.
 878         * When enabling secondary stream engine,
 879         * this master bit must also be set.
 880         * This register shared with audio info frame.
 881         * Therefore we need to enable master bit
 882         * if at least on of the fields is not 0
 883         */
 884         value = REG_READ(DP_SEC_CNTL);
 885         if (value)
 886                 REG_UPDATE(DP_SEC_CNTL, DP_SEC_STREAM_ENABLE, 1);
 887 }
 888
 889 static void dce110_stream_encoder_stop_dp_info_packets(
 890         struct stream_encoder *enc)
 891 {
 892         /* stop generic packets on DP */
 893         struct dce110_stream_encoder *enc110 = DCE110STRENC_FROM_STRENC(enc);
 894         uint32_t value = 0;
 895
 896         if (enc110->se_mask->DP_SEC_AVI_ENABLE) {
 897                 REG_SET_7(DP_SEC_CNTL, 0,
 898                         DP_SEC_GSP0_ENABLE, 0,
 899                         DP_SEC_GSP1_ENABLE, 0,
 900                         DP_SEC_GSP2_ENABLE, 0,
 901                         DP_SEC_GSP3_ENABLE, 0,
 902                         DP_SEC_AVI_ENABLE, 0,
 903                         DP_SEC_MPG_ENABLE, 0,
 904                         DP_SEC_STREAM_ENABLE, 0);
 905         }
 906
 907         /* this register shared with audio info frame.
 908          * therefore we need to keep master enabled
 909          * if at least one of the fields is not 0 */
 910         value = REG_READ(DP_SEC_CNTL);
 911         if (value)
 912                 REG_UPDATE(DP_SEC_CNTL, DP_SEC_STREAM_ENABLE, 1);
 913
 914 }
 915
 916 static void dce110_stream_encoder_dp_blank(
 917         struct stream_encoder *enc)
 918 {
 919         struct dce110_stream_encoder *enc110 = DCE110STRENC_FROM_STRENC(enc);
 920         uint32_t  reg1 = 0;
 921         uint32_t max_retries = DP_BLANK_MAX_RETRY * 10;
 922
 923         /* Note: For CZ, we are changing driver default to disable
 924          * stream deferred to next VBLANK. If results are positive, we
 925          * will make the same change to all DCE versions. There are a
 926          * handful of panels that cannot handle disable stream at
 927          * HBLANK and will result in a white line flash across the
 928          * screen on stream disable. */
 929         REG_GET(DP_VID_STREAM_CNTL, DP_VID_STREAM_ENABLE, &reg1);
 930         if ((reg1 & 0x1) == 0)
 931                 /*stream not enabled*/
 932                 return;
 933         /* Specify the video stream disable point
 934          * (2 = start of the next vertical blank) */
 935         REG_UPDATE(DP_VID_STREAM_CNTL, DP_VID_STREAM_DIS_DEFER, 2);
 936         /* Larger delay to wait until VBLANK - use max retry of
 937          * 10us*3000=30ms. This covers 16.6ms of typical 60 Hz mode +
 938          * a little more because we may not trust delay accuracy.
 939          */
 940         max_retries = DP_BLANK_MAX_RETRY * 150;
 941
 942         /* disable DP stream */
 943         REG_UPDATE(DP_VID_STREAM_CNTL, DP_VID_STREAM_ENABLE, 0);
 944
 945         /* the encoder stops sending the video stream
 946          * at the start of the vertical blanking.
 947          * Poll for DP_VID_STREAM_STATUS == 0
 948          */
 949
 950         REG_WAIT(DP_VID_STREAM_CNTL, DP_VID_STREAM_STATUS,
 951                         0,
 952                         10, max_retries);
 953
 954         /* Tell the DP encoder to ignore timing from CRTC, must be done after
 955          * the polling. If we set DP_STEER_FIFO_RESET before DP stream blank is
 956          * complete, stream status will be stuck in video stream enabled state,
 957          * i.e. DP_VID_STREAM_STATUS stuck at 1.
 958          */
 959
 960         REG_UPDATE(DP_STEER_FIFO, DP_STEER_FIFO_RESET, true);
 961 }
 962
 963 /* output video stream to link encoder */
 964 static void dce110_stream_encoder_dp_unblank(
 965         struct stream_encoder *enc,
 966         const struct encoder_unblank_param *param)
 967 {
 968         struct dce110_stream_encoder *enc110 = DCE110STRENC_FROM_STRENC(enc);
 969
 970         if (param->link_settings.link_rate != LINK_RATE_UNKNOWN) {
 971                 uint32_t n_vid = 0x8000;
 972                 uint32_t m_vid;
 973
 974                 /* M / N = Fstream / Flink
 975                 * m_vid / n_vid = pixel rate / link rate
 976                 */
 977
 978                 uint64_t m_vid_l = n_vid;
 979
 980                 m_vid_l *= param->timing.pix_clk_100hz / 10;
 981                 m_vid_l = div_u64(m_vid_l,
 982                         param->link_settings.link_rate
 983                                 * LINK_RATE_REF_FREQ_IN_KHZ);
 984
 985                 m_vid = (uint32_t) m_vid_l;
 986
 987                 /* enable auto measurement */
 988
 989                 REG_UPDATE(DP_VID_TIMING, DP_VID_M_N_GEN_EN, 0);
 990
 991                 /* auto measurement need 1 full 0x8000 symbol cycle to kick in,
 992                  * therefore program initial value for Mvid and Nvid
 993                  */
 994
 995                 REG_UPDATE(DP_VID_N, DP_VID_N, n_vid);
 996
 997                 REG_UPDATE(DP_VID_M, DP_VID_M, m_vid);
 998
 999                 REG_UPDATE(DP_VID_TIMING, DP_VID_M_N_GEN_EN, 1);
1000         }
1001
1002         /* set DIG_START to 0x1 to resync FIFO */
1003
1004         REG_UPDATE(DIG_FE_CNTL, DIG_START, 1);
1005
1006         /* switch DP encoder to CRTC data */
1007
1008         REG_UPDATE(DP_STEER_FIFO, DP_STEER_FIFO_RESET, 0);
1009
1010         /* wait 100us for DIG/DP logic to prime
1011         * (i.e. a few video lines)
1012         */
1013         udelay(100);
1014
1015         /* the hardware would start sending video at the start of the next DP
1016         * frame (i.e. rising edge of the vblank).
1017         * NOTE: We used to program DP_VID_STREAM_DIS_DEFER = 2 here, but this
1018         * register has no effect on enable transition! HW always guarantees
1019         * VID_STREAM enable at start of next frame, and this is not
1020         * programmable
1021         */
1022
1023         REG_UPDATE(DP_VID_STREAM_CNTL, DP_VID_STREAM_ENABLE, true);
1024 }
1025
1026 static void dce110_stream_encoder_set_avmute(
1027         struct stream_encoder *enc,
1028         bool enable)
1029 {
1030         struct dce110_stream_encoder *enc110 = DCE110STRENC_FROM_STRENC(enc);
1031         unsigned int value = enable ? 1 : 0;
1032
1033         REG_UPDATE(HDMI_GC, HDMI_GC_AVMUTE, value);
1034 }
1035
1036
1037 #define DP_SEC_AUD_N__DP_SEC_AUD_N__DEFAULT 0x8000
1038 #define DP_SEC_TIMESTAMP__DP_SEC_TIMESTAMP_MODE__AUTO_CALC 1
1039
1040 #include "include/audio_types.h"
1041
1042 /**
1043 * speakersToChannels
1044 *
1045 * @brief
1046 *  translate speakers to channels
1047 *
1048 *  FL  - Front Left
1049 *  FR  - Front Right
1050 *  RL  - Rear Left
1051 *  RR  - Rear Right
1052 *  RC  - Rear Center
1053 *  FC  - Front Center
1054 *  FLC - Front Left Center
1055 *  FRC - Front Right Center
1056 *  RLC - Rear Left Center
1057 *  RRC - Rear Right Center
1058 *  LFE - Low Freq Effect
1059 *
1060 *               FC
1061 *          FLC      FRC
1062 *    FL                    FR
1063 *
1064 *                    LFE
1065 *              ()
1066 *
1067 *
1068 *    RL                    RR
1069 *          RLC      RRC
1070 *               RC
1071 *
1072 *             ch  8   7   6   5   4   3   2   1
1073 * 0b00000011      -   -   -   -   -   -   FR  FL
1074 * 0b00000111      -   -   -   -   -   LFE FR  FL
1075 * 0b00001011      -   -   -   -   FC  -   FR  FL
1076 * 0b00001111      -   -   -   -   FC  LFE FR  FL
1077 * 0b00010011      -   -   -   RC  -   -   FR  FL
1078 * 0b00010111      -   -   -   RC  -   LFE FR  FL
1079 * 0b00011011      -   -   -   RC  FC  -   FR  FL
1080 * 0b00011111      -   -   -   RC  FC  LFE FR  FL
1081 * 0b00110011      -   -   RR  RL  -   -   FR  FL
1082 * 0b00110111      -   -   RR  RL  -   LFE FR  FL
1083 * 0b00111011      -   -   RR  RL  FC  -   FR  FL
1084 * 0b00111111      -   -   RR  RL  FC  LFE FR  FL
1085 * 0b01110011      -   RC  RR  RL  -   -   FR  FL
1086 * 0b01110111      -   RC  RR  RL  -   LFE FR  FL
1087 * 0b01111011      -   RC  RR  RL  FC  -   FR  FL
1088 * 0b01111111      -   RC  RR  RL  FC  LFE FR  FL
1089 * 0b11110011      RRC RLC RR  RL  -   -   FR  FL
1090 * 0b11110111      RRC RLC RR  RL  -   LFE FR  FL
1091 * 0b11111011      RRC RLC RR  RL  FC  -   FR  FL
1092 * 0b11111111      RRC RLC RR  RL  FC  LFE FR  FL
1093 * 0b11000011      FRC FLC -   -   -   -   FR  FL
1094 * 0b11000111      FRC FLC -   -   -   LFE FR  FL
1095 * 0b11001011      FRC FLC -   -   FC  -   FR  FL
1096 * 0b11001111      FRC FLC -   -   FC  LFE FR  FL
1097 * 0b11010011      FRC FLC -   RC  -   -   FR  FL
1098 * 0b11010111      FRC FLC -   RC  -   LFE FR  FL
1099 * 0b11011011      FRC FLC -   RC  FC  -   FR  FL
1100 * 0b11011111      FRC FLC -   RC  FC  LFE FR  FL
1101 * 0b11110011      FRC FLC RR  RL  -   -   FR  FL
1102 * 0b11110111      FRC FLC RR  RL  -   LFE FR  FL
1103 * 0b11111011      FRC FLC RR  RL  FC  -   FR  FL
1104 * 0b11111111      FRC FLC RR  RL  FC  LFE FR  FL
1105 *
1106 * @param
1107 *  speakers - speaker information as it comes from CEA audio block
1108 */
1109 /* translate speakers to channels */
1110
1111 union audio_cea_channels {
1112         uint8_t all;
1113         struct audio_cea_channels_bits {
1114                 uint32_t FL:1;
1115                 uint32_t FR:1;
1116                 uint32_t LFE:1;
1117                 uint32_t FC:1;
1118                 uint32_t RL_RC:1;
1119                 uint32_t RR:1;
1120                 uint32_t RC_RLC_FLC:1;
1121                 uint32_t RRC_FRC:1;
1122         } channels;
1123 };
1124
1125 struct audio_clock_info {
1126         /* pixel clock frequency*/
1127         uint32_t pixel_clock_in_10khz;
1128         /* N - 32KHz audio */
1129         uint32_t n_32khz;
1130         /* CTS - 32KHz audio*/
1131         uint32_t cts_32khz;
1132         uint32_t n_44khz;
1133         uint32_t cts_44khz;
1134         uint32_t n_48khz;
1135         uint32_t cts_48khz;
1136 };
1137
1138 /* 25.2MHz/1.001*/
1139 /* 25.2MHz/1.001*/
1140 /* 25.2MHz*/
1141 /* 27MHz */
1142 /* 27MHz*1.001*/
1143 /* 27MHz*1.001*/
1144 /* 54MHz*/
1145 /* 54MHz*1.001*/
1146 /* 74.25MHz/1.001*/
1147 /* 74.25MHz*/
1148 /* 148.5MHz/1.001*/
1149 /* 148.5MHz*/
1150
1151 static const struct audio_clock_info audio_clock_info_table[16] = {
1152         {2517, 4576, 28125, 7007, 31250, 6864, 28125},
1153         {2518, 4576, 28125, 7007, 31250, 6864, 28125},
1154         {2520, 4096, 25200, 6272, 28000, 6144, 25200},
1155         {2700, 4096, 27000, 6272, 30000, 6144, 27000},
1156         {2702, 4096, 27027, 6272, 30030, 6144, 27027},
1157         {2703, 4096, 27027, 6272, 30030, 6144, 27027},
1158         {5400, 4096, 54000, 6272, 60000, 6144, 54000},
1159         {5405, 4096, 54054, 6272, 60060, 6144, 54054},
1160         {7417, 11648, 210937, 17836, 234375, 11648, 140625},
1161         {7425, 4096, 74250, 6272, 82500, 6144, 74250},
1162         {14835, 11648, 421875, 8918, 234375, 5824, 140625},
1163         {14850, 4096, 148500, 6272, 165000, 6144, 148500},
1164         {29670, 5824, 421875, 4459, 234375, 5824, 281250},
1165         {29700, 3072, 222750, 4704, 247500, 5120, 247500},
1166         {59340, 5824, 843750, 8918, 937500, 5824, 562500},
1167         {59400, 3072, 445500, 9408, 990000, 6144, 594000}
1168 };
1169
1170 static const struct audio_clock_info audio_clock_info_table_36bpc[14] = {
1171         {2517,  9152,  84375,  7007,  48875,  9152,  56250},
1172         {2518,  9152,  84375,  7007,  48875,  9152,  56250},
1173         {2520,  4096,  37800,  6272,  42000,  6144,  37800},
1174         {2700,  4096,  40500,  6272,  45000,  6144,  40500},
1175         {2702,  8192,  81081,  6272,  45045,  8192,  54054},
1176         {2703,  8192,  81081,  6272,  45045,  8192,  54054},
1177         {5400,  4096,  81000,  6272,  90000,  6144,  81000},
1178         {5405,  4096,  81081,  6272,  90090,  6144,  81081},
1179         {7417, 11648, 316406, 17836, 351562, 11648, 210937},
1180         {7425, 4096, 111375,  6272, 123750,  6144, 111375},
1181         {14835, 11648, 632812, 17836, 703125, 11648, 421875},
1182         {14850, 4096, 222750,  6272, 247500,  6144, 222750},
1183         {29670, 5824, 632812,  8918, 703125,  5824, 421875},
1184         {29700, 4096, 445500,  4704, 371250,  5120, 371250}
1185 };
1186
1187 static const struct audio_clock_info audio_clock_info_table_48bpc[14] = {
1188         {2517,  4576,  56250,  7007,  62500,  6864,  56250},
1189         {2518,  4576,  56250,  7007,  62500,  6864,  56250},
1190         {2520,  4096,  50400,  6272,  56000,  6144,  50400},
1191         {2700,  4096,  54000,  6272,  60000,  6144,  54000},
1192         {2702,  4096,  54054,  6267,  60060,  8192,  54054},
1193         {2703,  4096,  54054,  6272,  60060,  8192,  54054},
1194         {5400,  4096, 108000,  6272, 120000,  6144, 108000},
1195         {5405,  4096, 108108,  6272, 120120,  6144, 108108},
1196         {7417, 11648, 421875, 17836, 468750, 11648, 281250},
1197         {7425,  4096, 148500,  6272, 165000,  6144, 148500},
1198         {14835, 11648, 843750,  8918, 468750, 11648, 281250},
1199         {14850, 4096, 297000,  6272, 330000,  6144, 297000},
1200         {29670, 5824, 843750,  4459, 468750,  5824, 562500},
1201         {29700, 3072, 445500,  4704, 495000,  5120, 495000}
1202
1203
1204 };
1205
1206 static union audio_cea_channels speakers_to_channels(
1207         struct audio_speaker_flags speaker_flags)
1208 {
1209         union audio_cea_channels cea_channels = {0};
1210
1211         /* these are one to one */
1212         cea_channels.channels.FL = speaker_flags.FL_FR;
1213         cea_channels.channels.FR = speaker_flags.FL_FR;
1214         cea_channels.channels.LFE = speaker_flags.LFE;
1215         cea_channels.channels.FC = speaker_flags.FC;
1216
1217         /* if Rear Left and Right exist move RC speaker to channel 7
1218          * otherwise to channel 5
1219          */
1220         if (speaker_flags.RL_RR) {
1221                 cea_channels.channels.RL_RC = speaker_flags.RL_RR;
1222                 cea_channels.channels.RR = speaker_flags.RL_RR;
1223                 cea_channels.channels.RC_RLC_FLC = speaker_flags.RC;
1224         } else {
1225                 cea_channels.channels.RL_RC = speaker_flags.RC;
1226         }
1227
1228         /* FRONT Left Right Center and REAR Left Right Center are exclusive */
1229         if (speaker_flags.FLC_FRC) {
1230                 cea_channels.channels.RC_RLC_FLC = speaker_flags.FLC_FRC;
1231                 cea_channels.channels.RRC_FRC = speaker_flags.FLC_FRC;
1232         } else {
1233                 cea_channels.channels.RC_RLC_FLC = speaker_flags.RLC_RRC;
1234                 cea_channels.channels.RRC_FRC = speaker_flags.RLC_RRC;
1235         }
1236
1237         return cea_channels;
1238 }
1239
1240 static uint32_t calc_max_audio_packets_per_line(
1241         const struct audio_crtc_info *crtc_info)
1242 {
1243         uint32_t max_packets_per_line;
1244
1245         max_packets_per_line =
1246                 crtc_info->h_total - crtc_info->h_active;
1247
1248         if (crtc_info->pixel_repetition)
1249                 max_packets_per_line *= crtc_info->pixel_repetition;
1250
1251         /* for other hdmi features */
1252         max_packets_per_line -= 58;
1253         /* for Control Period */
1254         max_packets_per_line -= 16;
1255         /* Number of Audio Packets per Line */
1256         max_packets_per_line /= 32;
1257
1258         return max_packets_per_line;
1259 }
1260
1261 static void get_audio_clock_info(
1262         enum dc_color_depth color_depth,
1263         uint32_t crtc_pixel_clock_in_khz,
1264         uint32_t actual_pixel_clock_in_khz,
1265         struct audio_clock_info *audio_clock_info)
1266 {
1267         const struct audio_clock_info *clock_info;
1268         uint32_t index;
1269         uint32_t crtc_pixel_clock_in_10khz = crtc_pixel_clock_in_khz / 10;
1270         uint32_t audio_array_size;
1271
1272         switch (color_depth) {
1273         case COLOR_DEPTH_161616:
1274                 clock_info = audio_clock_info_table_48bpc;
1275                 audio_array_size = ARRAY_SIZE(
1276                                 audio_clock_info_table_48bpc);
1277                 break;
1278         case COLOR_DEPTH_121212:
1279                 clock_info = audio_clock_info_table_36bpc;
1280                 audio_array_size = ARRAY_SIZE(
1281                                 audio_clock_info_table_36bpc);
1282                 break;
1283         default:
1284                 clock_info = audio_clock_info_table;
1285                 audio_array_size = ARRAY_SIZE(
1286                                 audio_clock_info_table);
1287                 break;
1288         }
1289
1290         if (clock_info != NULL) {
1291                 /* search for exact pixel clock in table */
1292                 for (index = 0; index < audio_array_size; index++) {
1293                         if (clock_info[index].pixel_clock_in_10khz >
1294                                 crtc_pixel_clock_in_10khz)
1295                                 break;  /* not match */
1296                         else if (clock_info[index].pixel_clock_in_10khz ==
1297                                         crtc_pixel_clock_in_10khz) {
1298                                 /* match found */
1299                                 *audio_clock_info = clock_info[index];
1300                                 return;
1301                         }
1302                 }
1303         }
1304
1305         /* not found */
1306         if (actual_pixel_clock_in_khz == 0)
1307                 actual_pixel_clock_in_khz = crtc_pixel_clock_in_khz;
1308
1309         /* See HDMI spec  the table entry under
1310          *  pixel clock of "Other". */
1311         audio_clock_info->pixel_clock_in_10khz =
1312                         actual_pixel_clock_in_khz / 10;
1313         audio_clock_info->cts_32khz = actual_pixel_clock_in_khz;
1314         audio_clock_info->cts_44khz = actual_pixel_clock_in_khz;
1315         audio_clock_info->cts_48khz = actual_pixel_clock_in_khz;
1316
1317         audio_clock_info->n_32khz = 4096;
1318         audio_clock_info->n_44khz = 6272;
1319         audio_clock_info->n_48khz = 6144;
1320 }
1321
1322 static void dce110_se_audio_setup(
1323         struct stream_encoder *enc,
1324         unsigned int az_inst,
1325         struct audio_info *audio_info)
1326 {
1327         struct dce110_stream_encoder *enc110 = DCE110STRENC_FROM_STRENC(enc);
1328
1329         uint32_t speakers = 0;
1330         uint32_t channels = 0;
1331
1332         ASSERT(audio_info);
1333         if (audio_info == NULL)
1334                 /* This should not happen.it does so we don't get BSOD*/
1335                 return;
1336
1337         speakers = audio_info->flags.info.ALLSPEAKERS;
1338         channels = speakers_to_channels(audio_info->flags.speaker_flags).all;
1339
1340         /* setup the audio stream source select (audio -> dig mapping) */
1341         REG_SET(AFMT_AUDIO_SRC_CONTROL, 0, AFMT_AUDIO_SRC_SELECT, az_inst);
1342
1343         /* Channel allocation */
1344         REG_UPDATE(AFMT_AUDIO_PACKET_CONTROL2, AFMT_AUDIO_CHANNEL_ENABLE, channels);
1345 }
1346
1347 static void dce110_se_setup_hdmi_audio(
1348         struct stream_encoder *enc,
1349         const struct audio_crtc_info *crtc_info)
1350 {
1351         struct dce110_stream_encoder *enc110 = DCE110STRENC_FROM_STRENC(enc);
1352
1353         struct audio_clock_info audio_clock_info = {0};
1354         uint32_t max_packets_per_line;
1355
1356         /* For now still do calculation, although this field is ignored when
1357         above HDMI_PACKET_GEN_VERSION set to 1 */
1358         max_packets_per_line = calc_max_audio_packets_per_line(crtc_info);
1359
1360         /* HDMI_AUDIO_PACKET_CONTROL */
1361         REG_UPDATE_2(HDMI_AUDIO_PACKET_CONTROL,
1362                         HDMI_AUDIO_PACKETS_PER_LINE, max_packets_per_line,
1363                         HDMI_AUDIO_DELAY_EN, 1);
1364
1365         /* AFMT_AUDIO_PACKET_CONTROL */
1366         REG_UPDATE(AFMT_AUDIO_PACKET_CONTROL, AFMT_60958_CS_UPDATE, 1);
1367
1368         /* AFMT_AUDIO_PACKET_CONTROL2 */
1369         REG_UPDATE_2(AFMT_AUDIO_PACKET_CONTROL2,
1370                         AFMT_AUDIO_LAYOUT_OVRD, 0,
1371                         AFMT_60958_OSF_OVRD, 0);
1372
1373         /* HDMI_ACR_PACKET_CONTROL */
1374         REG_UPDATE_3(HDMI_ACR_PACKET_CONTROL,
1375                         HDMI_ACR_AUTO_SEND, 1,
1376                         HDMI_ACR_SOURCE, 0,
1377                         HDMI_ACR_AUDIO_PRIORITY, 0);
1378
1379         /* Program audio clock sample/regeneration parameters */
1380         get_audio_clock_info(crtc_info->color_depth,
1381                              crtc_info->requested_pixel_clock,
1382                              crtc_info->calculated_pixel_clock,
1383                              &audio_clock_info);
1384         DC_LOG_HW_AUDIO(
1385                         "\n%s:Input::requested_pixel_clock = %d"        \
1386                         "calculated_pixel_clock = %d \n", __func__,     \
1387                         crtc_info->requested_pixel_clock,               \
1388                         crtc_info->calculated_pixel_clock);
1389
1390         /* HDMI_ACR_32_0__HDMI_ACR_CTS_32_MASK */
1391         REG_UPDATE(HDMI_ACR_32_0, HDMI_ACR_CTS_32, audio_clock_info.cts_32khz);
1392
1393         /* HDMI_ACR_32_1__HDMI_ACR_N_32_MASK */
1394         REG_UPDATE(HDMI_ACR_32_1, HDMI_ACR_N_32, audio_clock_info.n_32khz);
1395
1396         /* HDMI_ACR_44_0__HDMI_ACR_CTS_44_MASK */
1397         REG_UPDATE(HDMI_ACR_44_0, HDMI_ACR_CTS_44, audio_clock_info.cts_44khz);
1398
1399         /* HDMI_ACR_44_1__HDMI_ACR_N_44_MASK */
1400         REG_UPDATE(HDMI_ACR_44_1, HDMI_ACR_N_44, audio_clock_info.n_44khz);
1401
1402         /* HDMI_ACR_48_0__HDMI_ACR_CTS_48_MASK */
1403         REG_UPDATE(HDMI_ACR_48_0, HDMI_ACR_CTS_48, audio_clock_info.cts_48khz);
1404
1405         /* HDMI_ACR_48_1__HDMI_ACR_N_48_MASK */
1406         REG_UPDATE(HDMI_ACR_48_1, HDMI_ACR_N_48, audio_clock_info.n_48khz);
1407
1408         /* Video driver cannot know in advance which sample rate will
1409            be used by HD Audio driver
1410            HDMI_ACR_PACKET_CONTROL__HDMI_ACR_N_MULTIPLE field is
1411            programmed below in interruppt callback */
1412
1413         /* AFMT_60958_0__AFMT_60958_CS_CHANNEL_NUMBER_L_MASK &
1414         AFMT_60958_0__AFMT_60958_CS_CLOCK_ACCURACY_MASK */
1415         REG_UPDATE_2(AFMT_60958_0,
1416                         AFMT_60958_CS_CHANNEL_NUMBER_L, 1,
1417                         AFMT_60958_CS_CLOCK_ACCURACY, 0);
1418
1419         /* AFMT_60958_1 AFMT_60958_CS_CHALNNEL_NUMBER_R */
1420         REG_UPDATE(AFMT_60958_1, AFMT_60958_CS_CHANNEL_NUMBER_R, 2);
1421
1422         /*AFMT_60958_2 now keep this settings until
1423          *  Programming guide comes out*/
1424         REG_UPDATE_6(AFMT_60958_2,
1425                         AFMT_60958_CS_CHANNEL_NUMBER_2, 3,
1426                         AFMT_60958_CS_CHANNEL_NUMBER_3, 4,
1427                         AFMT_60958_CS_CHANNEL_NUMBER_4, 5,
1428                         AFMT_60958_CS_CHANNEL_NUMBER_5, 6,
1429                         AFMT_60958_CS_CHANNEL_NUMBER_6, 7,
1430                         AFMT_60958_CS_CHANNEL_NUMBER_7, 8);
1431 }
1432
1433 static void dce110_se_setup_dp_audio(
1434         struct stream_encoder *enc)
1435 {
1436         struct dce110_stream_encoder *enc110 = DCE110STRENC_FROM_STRENC(enc);
1437
1438         /* --- DP Audio packet configurations --- */
1439
1440         /* ATP Configuration */
1441         REG_SET(DP_SEC_AUD_N, 0,
1442                         DP_SEC_AUD_N, DP_SEC_AUD_N__DP_SEC_AUD_N__DEFAULT);
1443
1444         /* Async/auto-calc timestamp mode */
1445         REG_SET(DP_SEC_TIMESTAMP, 0, DP_SEC_TIMESTAMP_MODE,
1446                         DP_SEC_TIMESTAMP__DP_SEC_TIMESTAMP_MODE__AUTO_CALC);
1447
1448         /* --- The following are the registers
1449          *  copied from the SetupHDMI --- */
1450
1451         /* AFMT_AUDIO_PACKET_CONTROL */
1452         REG_UPDATE(AFMT_AUDIO_PACKET_CONTROL, AFMT_60958_CS_UPDATE, 1);
1453
1454         /* AFMT_AUDIO_PACKET_CONTROL2 */
1455         /* Program the ATP and AIP next */
1456         REG_UPDATE_2(AFMT_AUDIO_PACKET_CONTROL2,
1457                         AFMT_AUDIO_LAYOUT_OVRD, 0,
1458                         AFMT_60958_OSF_OVRD, 0);
1459
1460         /* AFMT_INFOFRAME_CONTROL0 */
1461         REG_UPDATE(AFMT_INFOFRAME_CONTROL0, AFMT_AUDIO_INFO_UPDATE, 1);
1462
1463         /* AFMT_60958_0__AFMT_60958_CS_CLOCK_ACCURACY_MASK */
1464         REG_UPDATE(AFMT_60958_0, AFMT_60958_CS_CLOCK_ACCURACY, 0);
1465 }
1466
1467 static void dce110_se_enable_audio_clock(
1468         struct stream_encoder *enc,
1469         bool enable)
1470 {
1471         struct dce110_stream_encoder *enc110 = DCE110STRENC_FROM_STRENC(enc);
1472
1473         if (REG(AFMT_CNTL) == 0)
1474                 return;   /* DCE8/10 does not have this register */
1475
1476         REG_UPDATE(AFMT_CNTL, AFMT_AUDIO_CLOCK_EN, !!enable);
1477
1478         /* wait for AFMT clock to turn on,
1479          * expectation: this should complete in 1-2 reads
1480          *
1481          * REG_WAIT(AFMT_CNTL, AFMT_AUDIO_CLOCK_ON, !!enable, 1, 10);
1482          *
1483          * TODO: wait for clock_on does not work well. May need HW
1484          * program sequence. But audio seems work normally even without wait
1485          * for clock_on status change
1486          */
1487 }
1488
1489 static void dce110_se_enable_dp_audio(
1490         struct stream_encoder *enc)
1491 {
1492         struct dce110_stream_encoder *enc110 = DCE110STRENC_FROM_STRENC(enc);
1493
1494         /* Enable Audio packets */
1495         REG_UPDATE(DP_SEC_CNTL, DP_SEC_ASP_ENABLE, 1);
1496
1497         /* Program the ATP and AIP next */
1498         REG_UPDATE_2(DP_SEC_CNTL,
1499                         DP_SEC_ATP_ENABLE, 1,
1500                         DP_SEC_AIP_ENABLE, 1);
1501
1502         /* Program STREAM_ENABLE after all the other enables. */
1503         REG_UPDATE(DP_SEC_CNTL, DP_SEC_STREAM_ENABLE, 1);
1504 }
1505
1506 static void dce110_se_disable_dp_audio(
1507         struct stream_encoder *enc)
1508 {
1509         struct dce110_stream_encoder *enc110 = DCE110STRENC_FROM_STRENC(enc);
1510         uint32_t value = 0;
1511
1512         /* Disable Audio packets */
1513         REG_UPDATE_5(DP_SEC_CNTL,
1514                         DP_SEC_ASP_ENABLE, 0,
1515                         DP_SEC_ATP_ENABLE, 0,
1516                         DP_SEC_AIP_ENABLE, 0,
1517                         DP_SEC_ACM_ENABLE, 0,
1518                         DP_SEC_STREAM_ENABLE, 0);
1519
1520         /* This register shared with encoder info frame. Therefore we need to
1521         keep master enabled if at least on of the fields is not 0 */
1522         value = REG_READ(DP_SEC_CNTL);
1523         if (value != 0)
1524                 REG_UPDATE(DP_SEC_CNTL, DP_SEC_STREAM_ENABLE, 1);
1525
1526 }
1527
1528 void dce110_se_audio_mute_control(
1529         struct stream_encoder *enc,
1530         bool mute)
1531 {
1532         struct dce110_stream_encoder *enc110 = DCE110STRENC_FROM_STRENC(enc);
1533
1534         REG_UPDATE(AFMT_AUDIO_PACKET_CONTROL, AFMT_AUDIO_SAMPLE_SEND, !mute);
1535 }
1536
1537 void dce110_se_dp_audio_setup(
1538         struct stream_encoder *enc,
1539         unsigned int az_inst,
1540         struct audio_info *info)
1541 {
1542         dce110_se_audio_setup(enc, az_inst, info);
1543 }
1544
1545 void dce110_se_dp_audio_enable(
1546         struct stream_encoder *enc)
1547 {
1548         dce110_se_enable_audio_clock(enc, true);
1549         dce110_se_setup_dp_audio(enc);
1550         dce110_se_enable_dp_audio(enc);
1551 }
1552
1553 void dce110_se_dp_audio_disable(
1554         struct stream_encoder *enc)
1555 {
1556         dce110_se_disable_dp_audio(enc);
1557         dce110_se_enable_audio_clock(enc, false);
1558 }
1559
1560 void dce110_se_hdmi_audio_setup(
1561         struct stream_encoder *enc,
1562         unsigned int az_inst,
1563         struct audio_info *info,
1564         struct audio_crtc_info *audio_crtc_info)
1565 {
1566         dce110_se_enable_audio_clock(enc, true);
1567         dce110_se_setup_hdmi_audio(enc, audio_crtc_info);
1568         dce110_se_audio_setup(enc, az_inst, info);
1569 }
1570
1571 void dce110_se_hdmi_audio_disable(
1572         struct stream_encoder *enc)
1573 {
1574         dce110_se_enable_audio_clock(enc, false);
1575 }
1576
1577
1578 static void setup_stereo_sync(
1579         struct stream_encoder *enc,
1580         int tg_inst, bool enable)
1581 {
1582         struct dce110_stream_encoder *enc110 = DCE110STRENC_FROM_STRENC(enc);
1583         REG_UPDATE(DIG_FE_CNTL, DIG_STEREOSYNC_SELECT, tg_inst);
1584         REG_UPDATE(DIG_FE_CNTL, DIG_STEREOSYNC_GATE_EN, !enable);
1585 }
1586
1587 static void dig_connect_to_otg(
1588         struct stream_encoder *enc,
1589         int tg_inst)
1590 {
1591         struct dce110_stream_encoder *enc110 = DCE110STRENC_FROM_STRENC(enc);
1592
1593         REG_UPDATE(DIG_FE_CNTL, DIG_SOURCE_SELECT, tg_inst);
1594 }
1595
1596 static const struct stream_encoder_funcs dce110_str_enc_funcs = {
1597         .dp_set_stream_attribute =
1598                 dce110_stream_encoder_dp_set_stream_attribute,
1599         .hdmi_set_stream_attribute =
1600                 dce110_stream_encoder_hdmi_set_stream_attribute,
1601         .dvi_set_stream_attribute =
1602                 dce110_stream_encoder_dvi_set_stream_attribute,
1603         .lvds_set_stream_attribute =
1604                 dce110_stream_encoder_lvds_set_stream_attribute,
1605         .set_mst_bandwidth =
1606                 dce110_stream_encoder_set_mst_bandwidth,
1607         .update_hdmi_info_packets =
1608                 dce110_stream_encoder_update_hdmi_info_packets,
1609         .stop_hdmi_info_packets =
1610                 dce110_stream_encoder_stop_hdmi_info_packets,
1611         .update_dp_info_packets =
1612                 dce110_stream_encoder_update_dp_info_packets,
1613         .stop_dp_info_packets =
1614                 dce110_stream_encoder_stop_dp_info_packets,
1615         .dp_blank =
1616                 dce110_stream_encoder_dp_blank,
1617         .dp_unblank =
1618                 dce110_stream_encoder_dp_unblank,
1619         .audio_mute_control = dce110_se_audio_mute_control,
1620
1621         .dp_audio_setup = dce110_se_dp_audio_setup,
1622         .dp_audio_enable = dce110_se_dp_audio_enable,
1623         .dp_audio_disable = dce110_se_dp_audio_disable,
1624
1625         .hdmi_audio_setup = dce110_se_hdmi_audio_setup,
1626         .hdmi_audio_disable = dce110_se_hdmi_audio_disable,
1627         .setup_stereo_sync  = setup_stereo_sync,
1628         .set_avmute = dce110_stream_encoder_set_avmute,
1629         .dig_connect_to_otg  = dig_connect_to_otg,
1630 };
1631
1632 void dce110_stream_encoder_construct(
1633         struct dce110_stream_encoder *enc110,
1634         struct dc_context *ctx,
1635         struct dc_bios *bp,
1636         enum engine_id eng_id,
1637         const struct dce110_stream_enc_registers *regs,
1638         const struct dce_stream_encoder_shift *se_shift,
1639         const struct dce_stream_encoder_mask *se_mask)
1640 {
1641         enc110->base.funcs = &dce110_str_enc_funcs;
1642         enc110->base.ctx = ctx;
1643         enc110->base.id = eng_id;
1644         enc110->base.bp = bp;
1645         enc110->regs = regs;
1646         enc110->se_shift = se_shift;
1647         enc110->se_mask = se_mask;
1648 }