2 * Copyright 2012-15 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
26 #include "dc_bios_types.h"
27 #include "dce_stream_encoder.h"
28 #include "reg_helper.h"
29 #include "hw_shared.h"
32 enc110->base.ctx->logger
39 #define FN(reg_name, field_name) \
40 enc110->se_shift->field_name, enc110->se_mask->field_name
43 #define DP_BLANK_MAX_RETRY 20
44 #define HDMI_CLOCK_CHANNEL_RATE_MORE_340M 340000
46 #ifndef TMDS_CNTL__TMDS_PIXEL_ENCODING_MASK
47 #define TMDS_CNTL__TMDS_PIXEL_ENCODING_MASK 0x00000010L
48 #define TMDS_CNTL__TMDS_COLOR_FORMAT_MASK 0x00000300L
49 #define TMDS_CNTL__TMDS_PIXEL_ENCODING__SHIFT 0x00000004
50 #define TMDS_CNTL__TMDS_COLOR_FORMAT__SHIFT 0x00000008
54 DP_MST_UPDATE_MAX_RETRY = 50
57 #define DCE110_SE(audio)\
58 container_of(audio, struct dce110_stream_encoder, base)
63 static void dce110_update_generic_info_packet(
64 struct dce110_stream_encoder *enc110,
65 uint32_t packet_index,
66 const struct dc_info_packet *info_packet)
69 /* TODOFPGA Figure out a proper number for max_retries polling for lock
72 uint32_t max_retries = 50;
74 /*we need turn on clock before programming AFMT block*/
75 REG_UPDATE(AFMT_CNTL, AFMT_AUDIO_CLOCK_EN, 1);
77 if (REG(AFMT_VBI_PACKET_CONTROL1)) {
78 if (packet_index >= 8)
81 /* poll dig_update_lock is not locked -> asic internal signal
82 * assume otg master lock will unlock it
84 /* REG_WAIT(AFMT_VBI_PACKET_CONTROL, AFMT_GENERIC_LOCK_STATUS,
85 0, 10, max_retries);*/
87 /* check if HW reading GSP memory */
88 REG_WAIT(AFMT_VBI_PACKET_CONTROL, AFMT_GENERIC_CONFLICT,
91 /* HW does is not reading GSP memory not reading too long ->
92 * something wrong. clear GPS memory access and notify?
93 * hw SW is writing to GSP memory
95 REG_UPDATE(AFMT_VBI_PACKET_CONTROL, AFMT_GENERIC_CONFLICT_CLR, 1);
97 /* choose which generic packet to use */
99 regval = REG_READ(AFMT_VBI_PACKET_CONTROL);
100 REG_UPDATE(AFMT_VBI_PACKET_CONTROL,
101 AFMT_GENERIC_INDEX, packet_index);
104 /* write generic packet header
105 * (4th byte is for GENERIC0 only) */
107 REG_SET_4(AFMT_GENERIC_HDR, 0,
108 AFMT_GENERIC_HB0, info_packet->hb0,
109 AFMT_GENERIC_HB1, info_packet->hb1,
110 AFMT_GENERIC_HB2, info_packet->hb2,
111 AFMT_GENERIC_HB3, info_packet->hb3);
114 /* write generic packet contents
115 * (we never use last 4 bytes)
116 * there are 8 (0-7) mmDIG0_AFMT_GENERIC0_x registers */
118 const uint32_t *content =
119 (const uint32_t *) &info_packet->sb[0];
121 REG_WRITE(AFMT_GENERIC_0, *content++);
122 REG_WRITE(AFMT_GENERIC_1, *content++);
123 REG_WRITE(AFMT_GENERIC_2, *content++);
124 REG_WRITE(AFMT_GENERIC_3, *content++);
125 REG_WRITE(AFMT_GENERIC_4, *content++);
126 REG_WRITE(AFMT_GENERIC_5, *content++);
127 REG_WRITE(AFMT_GENERIC_6, *content++);
128 REG_WRITE(AFMT_GENERIC_7, *content);
131 if (!REG(AFMT_VBI_PACKET_CONTROL1)) {
132 /* force double-buffered packet update */
133 REG_UPDATE_2(AFMT_VBI_PACKET_CONTROL,
134 AFMT_GENERIC0_UPDATE, (packet_index == 0),
135 AFMT_GENERIC2_UPDATE, (packet_index == 2));
137 #if defined(CONFIG_DRM_AMD_DC_DCN1_0)
138 if (REG(AFMT_VBI_PACKET_CONTROL1)) {
139 switch (packet_index) {
141 REG_UPDATE(AFMT_VBI_PACKET_CONTROL1,
142 AFMT_GENERIC0_FRAME_UPDATE, 1);
145 REG_UPDATE(AFMT_VBI_PACKET_CONTROL1,
146 AFMT_GENERIC1_FRAME_UPDATE, 1);
149 REG_UPDATE(AFMT_VBI_PACKET_CONTROL1,
150 AFMT_GENERIC2_FRAME_UPDATE, 1);
153 REG_UPDATE(AFMT_VBI_PACKET_CONTROL1,
154 AFMT_GENERIC3_FRAME_UPDATE, 1);
157 REG_UPDATE(AFMT_VBI_PACKET_CONTROL1,
158 AFMT_GENERIC4_FRAME_UPDATE, 1);
161 REG_UPDATE(AFMT_VBI_PACKET_CONTROL1,
162 AFMT_GENERIC5_FRAME_UPDATE, 1);
165 REG_UPDATE(AFMT_VBI_PACKET_CONTROL1,
166 AFMT_GENERIC6_FRAME_UPDATE, 1);
169 REG_UPDATE(AFMT_VBI_PACKET_CONTROL1,
170 AFMT_GENERIC7_FRAME_UPDATE, 1);
179 static void dce110_update_hdmi_info_packet(
180 struct dce110_stream_encoder *enc110,
181 uint32_t packet_index,
182 const struct dc_info_packet *info_packet)
184 uint32_t cont, send, line;
186 if (info_packet->valid) {
187 dce110_update_generic_info_packet(
192 /* enable transmission of packet(s) -
193 * packet transmission begins on the next frame */
195 /* send packet(s) every frame */
197 /* select line number to send packets on */
205 /* choose which generic packet control to use */
206 switch (packet_index) {
208 REG_UPDATE_3(HDMI_GENERIC_PACKET_CONTROL0,
209 HDMI_GENERIC0_CONT, cont,
210 HDMI_GENERIC0_SEND, send,
211 HDMI_GENERIC0_LINE, line);
214 REG_UPDATE_3(HDMI_GENERIC_PACKET_CONTROL0,
215 HDMI_GENERIC1_CONT, cont,
216 HDMI_GENERIC1_SEND, send,
217 HDMI_GENERIC1_LINE, line);
220 REG_UPDATE_3(HDMI_GENERIC_PACKET_CONTROL1,
221 HDMI_GENERIC0_CONT, cont,
222 HDMI_GENERIC0_SEND, send,
223 HDMI_GENERIC0_LINE, line);
226 REG_UPDATE_3(HDMI_GENERIC_PACKET_CONTROL1,
227 HDMI_GENERIC1_CONT, cont,
228 HDMI_GENERIC1_SEND, send,
229 HDMI_GENERIC1_LINE, line);
231 #if defined(CONFIG_DRM_AMD_DC_DCN1_0)
233 if (REG(HDMI_GENERIC_PACKET_CONTROL2))
234 REG_UPDATE_3(HDMI_GENERIC_PACKET_CONTROL2,
235 HDMI_GENERIC0_CONT, cont,
236 HDMI_GENERIC0_SEND, send,
237 HDMI_GENERIC0_LINE, line);
240 if (REG(HDMI_GENERIC_PACKET_CONTROL2))
241 REG_UPDATE_3(HDMI_GENERIC_PACKET_CONTROL2,
242 HDMI_GENERIC1_CONT, cont,
243 HDMI_GENERIC1_SEND, send,
244 HDMI_GENERIC1_LINE, line);
247 if (REG(HDMI_GENERIC_PACKET_CONTROL3))
248 REG_UPDATE_3(HDMI_GENERIC_PACKET_CONTROL3,
249 HDMI_GENERIC0_CONT, cont,
250 HDMI_GENERIC0_SEND, send,
251 HDMI_GENERIC0_LINE, line);
254 if (REG(HDMI_GENERIC_PACKET_CONTROL3))
255 REG_UPDATE_3(HDMI_GENERIC_PACKET_CONTROL3,
256 HDMI_GENERIC1_CONT, cont,
257 HDMI_GENERIC1_SEND, send,
258 HDMI_GENERIC1_LINE, line);
262 /* invalid HW packet index */
264 "Invalid HW packet index: %s()\n",
270 /* setup stream encoder in dp mode */
271 static void dce110_stream_encoder_dp_set_stream_attribute(
272 struct stream_encoder *enc,
273 struct dc_crtc_timing *crtc_timing,
274 enum dc_color_space output_color_space)
276 #if defined(CONFIG_DRM_AMD_DC_DCN1_0)
277 uint32_t h_active_start;
278 uint32_t v_active_start;
282 uint32_t h_back_porch;
283 uint8_t synchronous_clock = 0; /* asynchronous mode */
284 uint8_t colorimetry_bpc;
285 uint8_t dynamic_range_rgb = 0; /*full range*/
286 uint8_t dynamic_range_ycbcr = 1; /*bt709*/
289 struct dce110_stream_encoder *enc110 = DCE110STRENC_FROM_STRENC(enc);
291 #if defined(CONFIG_DRM_AMD_DC_DCN1_0)
293 REG_UPDATE(DP_DB_CNTL, DP_DB_DISABLE, 1);
296 /* set pixel encoding */
297 switch (crtc_timing->pixel_encoding) {
298 case PIXEL_ENCODING_YCBCR422:
299 REG_UPDATE(DP_PIXEL_FORMAT, DP_PIXEL_ENCODING,
300 DP_PIXEL_ENCODING_TYPE_YCBCR422);
302 case PIXEL_ENCODING_YCBCR444:
303 REG_UPDATE(DP_PIXEL_FORMAT, DP_PIXEL_ENCODING,
304 DP_PIXEL_ENCODING_TYPE_YCBCR444);
306 if (crtc_timing->flags.Y_ONLY)
307 if (crtc_timing->display_color_depth != COLOR_DEPTH_666)
308 /* HW testing only, no use case yet.
309 * Color depth of Y-only could be
310 * 8, 10, 12, 16 bits */
311 REG_UPDATE(DP_PIXEL_FORMAT, DP_PIXEL_ENCODING,
312 DP_PIXEL_ENCODING_TYPE_Y_ONLY);
313 /* Note: DP_MSA_MISC1 bit 7 is the indicator
315 * This bit is set in HW if register
316 * DP_PIXEL_ENCODING is programmed to 0x4 */
318 case PIXEL_ENCODING_YCBCR420:
319 REG_UPDATE(DP_PIXEL_FORMAT, DP_PIXEL_ENCODING,
320 DP_PIXEL_ENCODING_TYPE_YCBCR420);
321 if (enc110->se_mask->DP_VID_M_DOUBLE_VALUE_EN)
322 REG_UPDATE(DP_VID_TIMING, DP_VID_M_DOUBLE_VALUE_EN, 1);
324 #if defined(CONFIG_DRM_AMD_DC_DCN1_0)
325 if (enc110->se_mask->DP_VID_N_MUL)
326 REG_UPDATE(DP_VID_TIMING, DP_VID_N_MUL, 1);
330 REG_UPDATE(DP_PIXEL_FORMAT, DP_PIXEL_ENCODING,
331 DP_PIXEL_ENCODING_TYPE_RGB444);
335 #if defined(CONFIG_DRM_AMD_DC_DCN1_0)
336 if (REG(DP_MSA_MISC))
337 misc1 = REG_READ(DP_MSA_MISC);
340 /* set color depth */
342 switch (crtc_timing->display_color_depth) {
343 case COLOR_DEPTH_666:
344 REG_UPDATE(DP_PIXEL_FORMAT, DP_COMPONENT_DEPTH,
347 case COLOR_DEPTH_888:
348 REG_UPDATE(DP_PIXEL_FORMAT, DP_COMPONENT_DEPTH,
349 DP_COMPONENT_PIXEL_DEPTH_8BPC);
351 case COLOR_DEPTH_101010:
352 REG_UPDATE(DP_PIXEL_FORMAT, DP_COMPONENT_DEPTH,
353 DP_COMPONENT_PIXEL_DEPTH_10BPC);
356 case COLOR_DEPTH_121212:
357 REG_UPDATE(DP_PIXEL_FORMAT, DP_COMPONENT_DEPTH,
358 DP_COMPONENT_PIXEL_DEPTH_12BPC);
361 REG_UPDATE(DP_PIXEL_FORMAT, DP_COMPONENT_DEPTH,
362 DP_COMPONENT_PIXEL_DEPTH_6BPC);
366 /* set dynamic range and YCbCr range */
369 #if defined(CONFIG_DRM_AMD_DC_DCN1_0)
370 switch (crtc_timing->display_color_depth) {
371 case COLOR_DEPTH_666:
374 case COLOR_DEPTH_888:
377 case COLOR_DEPTH_101010:
380 case COLOR_DEPTH_121212:
388 misc0 = misc0 | synchronous_clock;
389 misc0 = colorimetry_bpc << 5;
391 if (REG(DP_MSA_TIMING_PARAM1)) {
392 switch (output_color_space) {
393 case COLOR_SPACE_SRGB:
395 misc1 = misc1 & ~0x80; /* bit7 = 0*/
396 dynamic_range_rgb = 0; /*full range*/
398 case COLOR_SPACE_SRGB_LIMITED:
399 misc0 = misc0 | 0x8; /* bit3=1 */
400 misc1 = misc1 & ~0x80; /* bit7 = 0*/
401 dynamic_range_rgb = 1; /*limited range*/
403 case COLOR_SPACE_YCBCR601:
404 case COLOR_SPACE_YCBCR601_LIMITED:
405 misc0 = misc0 | 0x8; /* bit3=1, bit4=0 */
406 misc1 = misc1 & ~0x80; /* bit7 = 0*/
407 dynamic_range_ycbcr = 0; /*bt601*/
408 if (crtc_timing->pixel_encoding == PIXEL_ENCODING_YCBCR422)
409 misc0 = misc0 | 0x2; /* bit2=0, bit1=1 */
410 else if (crtc_timing->pixel_encoding == PIXEL_ENCODING_YCBCR444)
411 misc0 = misc0 | 0x4; /* bit2=1, bit1=0 */
413 case COLOR_SPACE_YCBCR709:
414 case COLOR_SPACE_YCBCR709_LIMITED:
415 misc0 = misc0 | 0x18; /* bit3=1, bit4=1 */
416 misc1 = misc1 & ~0x80; /* bit7 = 0*/
417 dynamic_range_ycbcr = 1; /*bt709*/
418 if (crtc_timing->pixel_encoding == PIXEL_ENCODING_YCBCR422)
419 misc0 = misc0 | 0x2; /* bit2=0, bit1=1 */
420 else if (crtc_timing->pixel_encoding == PIXEL_ENCODING_YCBCR444)
421 misc0 = misc0 | 0x4; /* bit2=1, bit1=0 */
423 case COLOR_SPACE_2020_RGB_LIMITEDRANGE:
424 dynamic_range_rgb = 1; /*limited range*/
426 case COLOR_SPACE_2020_RGB_FULLRANGE:
427 case COLOR_SPACE_2020_YCBCR:
428 case COLOR_SPACE_XR_RGB:
429 case COLOR_SPACE_MSREF_SCRGB:
430 case COLOR_SPACE_ADOBERGB:
431 case COLOR_SPACE_DCIP3:
432 case COLOR_SPACE_XV_YCC_709:
433 case COLOR_SPACE_XV_YCC_601:
434 case COLOR_SPACE_DISPLAYNATIVE:
435 case COLOR_SPACE_DOLBYVISION:
436 case COLOR_SPACE_APPCTRL:
437 case COLOR_SPACE_CUSTOMPOINTS:
438 case COLOR_SPACE_UNKNOWN:
442 if (enc110->se_mask->DP_DYN_RANGE && enc110->se_mask->DP_YCBCR_RANGE)
445 DP_DYN_RANGE, dynamic_range_rgb,
446 DP_YCBCR_RANGE, dynamic_range_ycbcr);
448 #if defined(CONFIG_DRM_AMD_DC_DCN1_0)
449 if (REG(DP_MSA_COLORIMETRY))
450 REG_SET(DP_MSA_COLORIMETRY, 0, DP_MSA_MISC0, misc0);
452 if (REG(DP_MSA_MISC))
453 REG_WRITE(DP_MSA_MISC, misc1); /* MSA_MISC1 */
456 * dc_crtc_timing is vesa dmt struct. data from edid
458 if (REG(DP_MSA_TIMING_PARAM1))
459 REG_SET_2(DP_MSA_TIMING_PARAM1, 0,
460 DP_MSA_HTOTAL, crtc_timing->h_total,
461 DP_MSA_VTOTAL, crtc_timing->v_total);
464 /* calcuate from vesa timing parameters
465 * h_active_start related to leading edge of sync
468 h_blank = crtc_timing->h_total - crtc_timing->h_border_left -
469 crtc_timing->h_addressable - crtc_timing->h_border_right;
471 h_back_porch = h_blank - crtc_timing->h_front_porch -
472 crtc_timing->h_sync_width;
474 /* start at begining of left border */
475 h_active_start = crtc_timing->h_sync_width + h_back_porch;
478 v_active_start = crtc_timing->v_total - crtc_timing->v_border_top -
479 crtc_timing->v_addressable - crtc_timing->v_border_bottom -
480 crtc_timing->v_front_porch;
483 #if defined(CONFIG_DRM_AMD_DC_DCN1_0)
484 /* start at begining of left border */
485 if (REG(DP_MSA_TIMING_PARAM2))
486 REG_SET_2(DP_MSA_TIMING_PARAM2, 0,
487 DP_MSA_HSTART, h_active_start,
488 DP_MSA_VSTART, v_active_start);
490 if (REG(DP_MSA_TIMING_PARAM3))
491 REG_SET_4(DP_MSA_TIMING_PARAM3, 0,
493 crtc_timing->h_sync_width,
494 DP_MSA_HSYNCPOLARITY,
495 !crtc_timing->flags.HSYNC_POSITIVE_POLARITY,
497 crtc_timing->v_sync_width,
498 DP_MSA_VSYNCPOLARITY,
499 !crtc_timing->flags.VSYNC_POSITIVE_POLARITY);
501 /* HWDITH include border or overscan */
502 if (REG(DP_MSA_TIMING_PARAM4))
503 REG_SET_2(DP_MSA_TIMING_PARAM4, 0,
504 DP_MSA_HWIDTH, crtc_timing->h_border_left +
505 crtc_timing->h_addressable + crtc_timing->h_border_right,
506 DP_MSA_VHEIGHT, crtc_timing->v_border_top +
507 crtc_timing->v_addressable + crtc_timing->v_border_bottom);
513 static void dce110_stream_encoder_set_stream_attribute_helper(
514 struct dce110_stream_encoder *enc110,
515 struct dc_crtc_timing *crtc_timing)
517 if (enc110->regs->TMDS_CNTL) {
518 switch (crtc_timing->pixel_encoding) {
519 case PIXEL_ENCODING_YCBCR422:
520 REG_UPDATE(TMDS_CNTL, TMDS_PIXEL_ENCODING, 1);
523 REG_UPDATE(TMDS_CNTL, TMDS_PIXEL_ENCODING, 0);
526 REG_UPDATE(TMDS_CNTL, TMDS_COLOR_FORMAT, 0);
527 } else if (enc110->regs->DIG_FE_CNTL) {
528 switch (crtc_timing->pixel_encoding) {
529 case PIXEL_ENCODING_YCBCR422:
530 REG_UPDATE(DIG_FE_CNTL, TMDS_PIXEL_ENCODING, 1);
533 REG_UPDATE(DIG_FE_CNTL, TMDS_PIXEL_ENCODING, 0);
536 REG_UPDATE(DIG_FE_CNTL, TMDS_COLOR_FORMAT, 0);
541 /* setup stream encoder in hdmi mode */
542 static void dce110_stream_encoder_hdmi_set_stream_attribute(
543 struct stream_encoder *enc,
544 struct dc_crtc_timing *crtc_timing,
545 int actual_pix_clk_khz,
548 struct dce110_stream_encoder *enc110 = DCE110STRENC_FROM_STRENC(enc);
549 struct bp_encoder_control cntl = {0};
551 cntl.action = ENCODER_CONTROL_SETUP;
552 cntl.engine_id = enc110->base.id;
553 cntl.signal = SIGNAL_TYPE_HDMI_TYPE_A;
554 cntl.enable_dp_audio = enable_audio;
555 cntl.pixel_clock = actual_pix_clk_khz;
556 cntl.lanes_number = LANE_COUNT_FOUR;
558 if (enc110->base.bp->funcs->encoder_control(
559 enc110->base.bp, &cntl) != BP_RESULT_OK)
562 dce110_stream_encoder_set_stream_attribute_helper(enc110, crtc_timing);
564 /* setup HDMI engine */
565 if (!enc110->se_mask->HDMI_DATA_SCRAMBLE_EN) {
566 REG_UPDATE_3(HDMI_CONTROL,
567 HDMI_PACKET_GEN_VERSION, 1,
568 HDMI_KEEPOUT_MODE, 1,
569 HDMI_DEEP_COLOR_ENABLE, 0);
570 } else if (enc110->regs->DIG_FE_CNTL) {
571 REG_UPDATE_5(HDMI_CONTROL,
572 HDMI_PACKET_GEN_VERSION, 1,
573 HDMI_KEEPOUT_MODE, 1,
574 HDMI_DEEP_COLOR_ENABLE, 0,
575 HDMI_DATA_SCRAMBLE_EN, 0,
576 HDMI_CLOCK_CHANNEL_RATE, 0);
579 switch (crtc_timing->display_color_depth) {
580 case COLOR_DEPTH_888:
581 REG_UPDATE(HDMI_CONTROL, HDMI_DEEP_COLOR_DEPTH, 0);
583 case COLOR_DEPTH_101010:
584 if (crtc_timing->pixel_encoding == PIXEL_ENCODING_YCBCR422) {
585 REG_UPDATE_2(HDMI_CONTROL,
586 HDMI_DEEP_COLOR_DEPTH, 1,
587 HDMI_DEEP_COLOR_ENABLE, 0);
589 REG_UPDATE_2(HDMI_CONTROL,
590 HDMI_DEEP_COLOR_DEPTH, 1,
591 HDMI_DEEP_COLOR_ENABLE, 1);
594 case COLOR_DEPTH_121212:
595 if (crtc_timing->pixel_encoding == PIXEL_ENCODING_YCBCR422) {
596 REG_UPDATE_2(HDMI_CONTROL,
597 HDMI_DEEP_COLOR_DEPTH, 2,
598 HDMI_DEEP_COLOR_ENABLE, 0);
600 REG_UPDATE_2(HDMI_CONTROL,
601 HDMI_DEEP_COLOR_DEPTH, 2,
602 HDMI_DEEP_COLOR_ENABLE, 1);
605 case COLOR_DEPTH_161616:
606 REG_UPDATE_2(HDMI_CONTROL,
607 HDMI_DEEP_COLOR_DEPTH, 3,
608 HDMI_DEEP_COLOR_ENABLE, 1);
614 if (enc110->se_mask->HDMI_DATA_SCRAMBLE_EN) {
615 if (actual_pix_clk_khz >= HDMI_CLOCK_CHANNEL_RATE_MORE_340M) {
616 /* enable HDMI data scrambler
617 * HDMI_CLOCK_CHANNEL_RATE_MORE_340M
618 * Clock channel frequency is 1/4 of character rate.
620 REG_UPDATE_2(HDMI_CONTROL,
621 HDMI_DATA_SCRAMBLE_EN, 1,
622 HDMI_CLOCK_CHANNEL_RATE, 1);
623 } else if (crtc_timing->flags.LTE_340MCSC_SCRAMBLE) {
625 /* TODO: New feature for DCE11, still need to implement */
627 /* enable HDMI data scrambler
628 * HDMI_CLOCK_CHANNEL_FREQ_EQUAL_TO_CHAR_RATE
629 * Clock channel frequency is the same
632 REG_UPDATE_2(HDMI_CONTROL,
633 HDMI_DATA_SCRAMBLE_EN, 1,
634 HDMI_CLOCK_CHANNEL_RATE, 0);
638 REG_UPDATE_3(HDMI_VBI_PACKET_CONTROL,
643 /* following belongs to audio */
644 REG_UPDATE(HDMI_INFOFRAME_CONTROL0, HDMI_AUDIO_INFO_SEND, 1);
646 REG_UPDATE(AFMT_INFOFRAME_CONTROL0, AFMT_AUDIO_INFO_UPDATE, 1);
648 REG_UPDATE(HDMI_INFOFRAME_CONTROL1, HDMI_AUDIO_INFO_LINE,
651 REG_UPDATE(HDMI_GC, HDMI_GC_AVMUTE, 0);
655 /* setup stream encoder in dvi mode */
656 static void dce110_stream_encoder_dvi_set_stream_attribute(
657 struct stream_encoder *enc,
658 struct dc_crtc_timing *crtc_timing,
661 struct dce110_stream_encoder *enc110 = DCE110STRENC_FROM_STRENC(enc);
662 struct bp_encoder_control cntl = {0};
664 cntl.action = ENCODER_CONTROL_SETUP;
665 cntl.engine_id = enc110->base.id;
666 cntl.signal = is_dual_link ?
667 SIGNAL_TYPE_DVI_DUAL_LINK : SIGNAL_TYPE_DVI_SINGLE_LINK;
668 cntl.enable_dp_audio = false;
669 cntl.pixel_clock = crtc_timing->pix_clk_khz;
670 cntl.lanes_number = (is_dual_link) ? LANE_COUNT_EIGHT : LANE_COUNT_FOUR;
672 if (enc110->base.bp->funcs->encoder_control(
673 enc110->base.bp, &cntl) != BP_RESULT_OK)
676 ASSERT(crtc_timing->pixel_encoding == PIXEL_ENCODING_RGB);
677 ASSERT(crtc_timing->display_color_depth == COLOR_DEPTH_888);
678 dce110_stream_encoder_set_stream_attribute_helper(enc110, crtc_timing);
681 static void dce110_stream_encoder_set_mst_bandwidth(
682 struct stream_encoder *enc,
683 struct fixed31_32 avg_time_slots_per_mtp)
685 struct dce110_stream_encoder *enc110 = DCE110STRENC_FROM_STRENC(enc);
686 uint32_t x = dc_fixpt_floor(
687 avg_time_slots_per_mtp);
688 uint32_t y = dc_fixpt_ceil(
691 avg_time_slots_per_mtp,
696 REG_SET_2(DP_MSE_RATE_CNTL, 0,
701 /* wait for update to be completed on the link */
702 /* i.e. DP_MSE_RATE_UPDATE_PENDING field (read only) */
703 /* is reset to 0 (not pending) */
704 REG_WAIT(DP_MSE_RATE_UPDATE, DP_MSE_RATE_UPDATE_PENDING,
706 10, DP_MST_UPDATE_MAX_RETRY);
709 static void dce110_stream_encoder_update_hdmi_info_packets(
710 struct stream_encoder *enc,
711 const struct encoder_info_frame *info_frame)
713 struct dce110_stream_encoder *enc110 = DCE110STRENC_FROM_STRENC(enc);
715 if (enc110->se_mask->HDMI_AVI_INFO_CONT &&
716 enc110->se_mask->HDMI_AVI_INFO_SEND) {
718 if (info_frame->avi.valid) {
719 const uint32_t *content =
720 (const uint32_t *) &info_frame->avi.sb[0];
721 /*we need turn on clock before programming AFMT block*/
722 REG_UPDATE(AFMT_CNTL, AFMT_AUDIO_CLOCK_EN, 1);
724 REG_WRITE(AFMT_AVI_INFO0, content[0]);
726 REG_WRITE(AFMT_AVI_INFO1, content[1]);
728 REG_WRITE(AFMT_AVI_INFO2, content[2]);
730 REG_WRITE(AFMT_AVI_INFO3, content[3]);
732 REG_UPDATE(AFMT_AVI_INFO3, AFMT_AVI_INFO_VERSION,
733 info_frame->avi.hb1);
735 REG_UPDATE_2(HDMI_INFOFRAME_CONTROL0,
736 HDMI_AVI_INFO_SEND, 1,
737 HDMI_AVI_INFO_CONT, 1);
739 REG_UPDATE(HDMI_INFOFRAME_CONTROL1, HDMI_AVI_INFO_LINE,
743 REG_UPDATE_2(HDMI_INFOFRAME_CONTROL0,
744 HDMI_AVI_INFO_SEND, 0,
745 HDMI_AVI_INFO_CONT, 0);
749 if (enc110->se_mask->HDMI_AVI_INFO_CONT &&
750 enc110->se_mask->HDMI_AVI_INFO_SEND) {
751 dce110_update_hdmi_info_packet(enc110, 0, &info_frame->vendor);
752 dce110_update_hdmi_info_packet(enc110, 1, &info_frame->gamut);
753 dce110_update_hdmi_info_packet(enc110, 2, &info_frame->spd);
754 dce110_update_hdmi_info_packet(enc110, 3, &info_frame->hdrsmd);
757 #if defined(CONFIG_DRM_AMD_DC_DCN1_0)
758 if (enc110->se_mask->HDMI_DB_DISABLE) {
759 /* for bring up, disable dp double TODO */
760 if (REG(HDMI_DB_CONTROL))
761 REG_UPDATE(HDMI_DB_CONTROL, HDMI_DB_DISABLE, 1);
763 dce110_update_hdmi_info_packet(enc110, 0, &info_frame->avi);
764 dce110_update_hdmi_info_packet(enc110, 1, &info_frame->vendor);
765 dce110_update_hdmi_info_packet(enc110, 2, &info_frame->gamut);
766 dce110_update_hdmi_info_packet(enc110, 3, &info_frame->spd);
767 dce110_update_hdmi_info_packet(enc110, 4, &info_frame->hdrsmd);
772 static void dce110_stream_encoder_stop_hdmi_info_packets(
773 struct stream_encoder *enc)
775 struct dce110_stream_encoder *enc110 = DCE110STRENC_FROM_STRENC(enc);
777 /* stop generic packets 0 & 1 on HDMI */
778 REG_SET_6(HDMI_GENERIC_PACKET_CONTROL0, 0,
779 HDMI_GENERIC1_CONT, 0,
780 HDMI_GENERIC1_LINE, 0,
781 HDMI_GENERIC1_SEND, 0,
782 HDMI_GENERIC0_CONT, 0,
783 HDMI_GENERIC0_LINE, 0,
784 HDMI_GENERIC0_SEND, 0);
786 /* stop generic packets 2 & 3 on HDMI */
787 REG_SET_6(HDMI_GENERIC_PACKET_CONTROL1, 0,
788 HDMI_GENERIC0_CONT, 0,
789 HDMI_GENERIC0_LINE, 0,
790 HDMI_GENERIC0_SEND, 0,
791 HDMI_GENERIC1_CONT, 0,
792 HDMI_GENERIC1_LINE, 0,
793 HDMI_GENERIC1_SEND, 0);
795 #if defined(CONFIG_DRM_AMD_DC_DCN1_0)
796 /* stop generic packets 2 & 3 on HDMI */
797 if (REG(HDMI_GENERIC_PACKET_CONTROL2))
798 REG_SET_6(HDMI_GENERIC_PACKET_CONTROL2, 0,
799 HDMI_GENERIC0_CONT, 0,
800 HDMI_GENERIC0_LINE, 0,
801 HDMI_GENERIC0_SEND, 0,
802 HDMI_GENERIC1_CONT, 0,
803 HDMI_GENERIC1_LINE, 0,
804 HDMI_GENERIC1_SEND, 0);
806 if (REG(HDMI_GENERIC_PACKET_CONTROL3))
807 REG_SET_6(HDMI_GENERIC_PACKET_CONTROL3, 0,
808 HDMI_GENERIC0_CONT, 0,
809 HDMI_GENERIC0_LINE, 0,
810 HDMI_GENERIC0_SEND, 0,
811 HDMI_GENERIC1_CONT, 0,
812 HDMI_GENERIC1_LINE, 0,
813 HDMI_GENERIC1_SEND, 0);
817 static void dce110_stream_encoder_update_dp_info_packets(
818 struct stream_encoder *enc,
819 const struct encoder_info_frame *info_frame)
821 struct dce110_stream_encoder *enc110 = DCE110STRENC_FROM_STRENC(enc);
824 if (info_frame->vsc.valid)
825 dce110_update_generic_info_packet(
830 if (info_frame->spd.valid)
831 dce110_update_generic_info_packet(
836 if (info_frame->hdrsmd.valid)
837 dce110_update_generic_info_packet(
840 &info_frame->hdrsmd);
842 /* enable/disable transmission of packet(s).
843 * If enabled, packet transmission begins on the next frame
845 REG_UPDATE(DP_SEC_CNTL, DP_SEC_GSP0_ENABLE, info_frame->vsc.valid);
846 REG_UPDATE(DP_SEC_CNTL, DP_SEC_GSP2_ENABLE, info_frame->spd.valid);
847 REG_UPDATE(DP_SEC_CNTL, DP_SEC_GSP3_ENABLE, info_frame->hdrsmd.valid);
849 /* This bit is the master enable bit.
850 * When enabling secondary stream engine,
851 * this master bit must also be set.
852 * This register shared with audio info frame.
853 * Therefore we need to enable master bit
854 * if at least on of the fields is not 0
856 value = REG_READ(DP_SEC_CNTL);
858 REG_UPDATE(DP_SEC_CNTL, DP_SEC_STREAM_ENABLE, 1);
861 static void dce110_stream_encoder_stop_dp_info_packets(
862 struct stream_encoder *enc)
864 /* stop generic packets on DP */
865 struct dce110_stream_encoder *enc110 = DCE110STRENC_FROM_STRENC(enc);
868 if (enc110->se_mask->DP_SEC_AVI_ENABLE) {
869 REG_SET_7(DP_SEC_CNTL, 0,
870 DP_SEC_GSP0_ENABLE, 0,
871 DP_SEC_GSP1_ENABLE, 0,
872 DP_SEC_GSP2_ENABLE, 0,
873 DP_SEC_GSP3_ENABLE, 0,
874 DP_SEC_AVI_ENABLE, 0,
875 DP_SEC_MPG_ENABLE, 0,
876 DP_SEC_STREAM_ENABLE, 0);
879 /* this register shared with audio info frame.
880 * therefore we need to keep master enabled
881 * if at least one of the fields is not 0 */
882 value = REG_READ(DP_SEC_CNTL);
884 REG_UPDATE(DP_SEC_CNTL, DP_SEC_STREAM_ENABLE, 1);
888 static void dce110_stream_encoder_dp_blank(
889 struct stream_encoder *enc)
891 struct dce110_stream_encoder *enc110 = DCE110STRENC_FROM_STRENC(enc);
892 uint32_t retries = 0;
894 uint32_t max_retries = DP_BLANK_MAX_RETRY * 10;
896 /* Note: For CZ, we are changing driver default to disable
897 * stream deferred to next VBLANK. If results are positive, we
898 * will make the same change to all DCE versions. There are a
899 * handful of panels that cannot handle disable stream at
900 * HBLANK and will result in a white line flash across the
901 * screen on stream disable. */
902 REG_GET(DP_VID_STREAM_CNTL, DP_VID_STREAM_ENABLE, ®1);
903 if ((reg1 & 0x1) == 0)
904 /*stream not enabled*/
906 /* Specify the video stream disable point
907 * (2 = start of the next vertical blank) */
908 REG_UPDATE(DP_VID_STREAM_CNTL, DP_VID_STREAM_DIS_DEFER, 2);
909 /* Larger delay to wait until VBLANK - use max retry of
910 * 10us*3000=30ms. This covers 16.6ms of typical 60 Hz mode +
911 * a little more because we may not trust delay accuracy.
913 max_retries = DP_BLANK_MAX_RETRY * 150;
915 /* disable DP stream */
916 REG_UPDATE(DP_VID_STREAM_CNTL, DP_VID_STREAM_ENABLE, 0);
918 /* the encoder stops sending the video stream
919 * at the start of the vertical blanking.
920 * Poll for DP_VID_STREAM_STATUS == 0
923 REG_WAIT(DP_VID_STREAM_CNTL, DP_VID_STREAM_STATUS,
927 ASSERT(retries <= max_retries);
929 /* Tell the DP encoder to ignore timing from CRTC, must be done after
930 * the polling. If we set DP_STEER_FIFO_RESET before DP stream blank is
931 * complete, stream status will be stuck in video stream enabled state,
932 * i.e. DP_VID_STREAM_STATUS stuck at 1.
935 REG_UPDATE(DP_STEER_FIFO, DP_STEER_FIFO_RESET, true);
938 /* output video stream to link encoder */
939 static void dce110_stream_encoder_dp_unblank(
940 struct stream_encoder *enc,
941 const struct encoder_unblank_param *param)
943 struct dce110_stream_encoder *enc110 = DCE110STRENC_FROM_STRENC(enc);
945 if (param->link_settings.link_rate != LINK_RATE_UNKNOWN) {
946 uint32_t n_vid = 0x8000;
949 /* M / N = Fstream / Flink
950 * m_vid / n_vid = pixel rate / link rate
953 uint64_t m_vid_l = n_vid;
955 m_vid_l *= param->pixel_clk_khz;
956 m_vid_l = div_u64(m_vid_l,
957 param->link_settings.link_rate
958 * LINK_RATE_REF_FREQ_IN_KHZ);
960 m_vid = (uint32_t) m_vid_l;
962 /* enable auto measurement */
964 REG_UPDATE(DP_VID_TIMING, DP_VID_M_N_GEN_EN, 0);
966 /* auto measurement need 1 full 0x8000 symbol cycle to kick in,
967 * therefore program initial value for Mvid and Nvid
970 REG_UPDATE(DP_VID_N, DP_VID_N, n_vid);
972 REG_UPDATE(DP_VID_M, DP_VID_M, m_vid);
974 REG_UPDATE(DP_VID_TIMING, DP_VID_M_N_GEN_EN, 1);
977 /* set DIG_START to 0x1 to resync FIFO */
979 REG_UPDATE(DIG_FE_CNTL, DIG_START, 1);
981 /* switch DP encoder to CRTC data */
983 REG_UPDATE(DP_STEER_FIFO, DP_STEER_FIFO_RESET, 0);
985 /* wait 100us for DIG/DP logic to prime
986 * (i.e. a few video lines)
990 /* the hardware would start sending video at the start of the next DP
991 * frame (i.e. rising edge of the vblank).
992 * NOTE: We used to program DP_VID_STREAM_DIS_DEFER = 2 here, but this
993 * register has no effect on enable transition! HW always guarantees
994 * VID_STREAM enable at start of next frame, and this is not
998 REG_UPDATE(DP_VID_STREAM_CNTL, DP_VID_STREAM_ENABLE, true);
1001 static void dce110_stream_encoder_set_avmute(
1002 struct stream_encoder *enc,
1005 struct dce110_stream_encoder *enc110 = DCE110STRENC_FROM_STRENC(enc);
1006 unsigned int value = enable ? 1 : 0;
1008 REG_UPDATE(HDMI_GC, HDMI_GC_AVMUTE, value);
1012 #define DP_SEC_AUD_N__DP_SEC_AUD_N__DEFAULT 0x8000
1013 #define DP_SEC_TIMESTAMP__DP_SEC_TIMESTAMP_MODE__AUTO_CALC 1
1015 #include "include/audio_types.h"
1018 * speakersToChannels
1021 * translate speakers to channels
1029 * FLC - Front Left Center
1030 * FRC - Front Right Center
1031 * RLC - Rear Left Center
1032 * RRC - Rear Right Center
1033 * LFE - Low Freq Effect
1047 * ch 8 7 6 5 4 3 2 1
1048 * 0b00000011 - - - - - - FR FL
1049 * 0b00000111 - - - - - LFE FR FL
1050 * 0b00001011 - - - - FC - FR FL
1051 * 0b00001111 - - - - FC LFE FR FL
1052 * 0b00010011 - - - RC - - FR FL
1053 * 0b00010111 - - - RC - LFE FR FL
1054 * 0b00011011 - - - RC FC - FR FL
1055 * 0b00011111 - - - RC FC LFE FR FL
1056 * 0b00110011 - - RR RL - - FR FL
1057 * 0b00110111 - - RR RL - LFE FR FL
1058 * 0b00111011 - - RR RL FC - FR FL
1059 * 0b00111111 - - RR RL FC LFE FR FL
1060 * 0b01110011 - RC RR RL - - FR FL
1061 * 0b01110111 - RC RR RL - LFE FR FL
1062 * 0b01111011 - RC RR RL FC - FR FL
1063 * 0b01111111 - RC RR RL FC LFE FR FL
1064 * 0b11110011 RRC RLC RR RL - - FR FL
1065 * 0b11110111 RRC RLC RR RL - LFE FR FL
1066 * 0b11111011 RRC RLC RR RL FC - FR FL
1067 * 0b11111111 RRC RLC RR RL FC LFE FR FL
1068 * 0b11000011 FRC FLC - - - - FR FL
1069 * 0b11000111 FRC FLC - - - LFE FR FL
1070 * 0b11001011 FRC FLC - - FC - FR FL
1071 * 0b11001111 FRC FLC - - FC LFE FR FL
1072 * 0b11010011 FRC FLC - RC - - FR FL
1073 * 0b11010111 FRC FLC - RC - LFE FR FL
1074 * 0b11011011 FRC FLC - RC FC - FR FL
1075 * 0b11011111 FRC FLC - RC FC LFE FR FL
1076 * 0b11110011 FRC FLC RR RL - - FR FL
1077 * 0b11110111 FRC FLC RR RL - LFE FR FL
1078 * 0b11111011 FRC FLC RR RL FC - FR FL
1079 * 0b11111111 FRC FLC RR RL FC LFE FR FL
1082 * speakers - speaker information as it comes from CEA audio block
1084 /* translate speakers to channels */
1086 union audio_cea_channels {
1088 struct audio_cea_channels_bits {
1095 uint32_t RC_RLC_FLC:1;
1100 struct audio_clock_info {
1101 /* pixel clock frequency*/
1102 uint32_t pixel_clock_in_10khz;
1103 /* N - 32KHz audio */
1105 /* CTS - 32KHz audio*/
1126 static const struct audio_clock_info audio_clock_info_table[16] = {
1127 {2517, 4576, 28125, 7007, 31250, 6864, 28125},
1128 {2518, 4576, 28125, 7007, 31250, 6864, 28125},
1129 {2520, 4096, 25200, 6272, 28000, 6144, 25200},
1130 {2700, 4096, 27000, 6272, 30000, 6144, 27000},
1131 {2702, 4096, 27027, 6272, 30030, 6144, 27027},
1132 {2703, 4096, 27027, 6272, 30030, 6144, 27027},
1133 {5400, 4096, 54000, 6272, 60000, 6144, 54000},
1134 {5405, 4096, 54054, 6272, 60060, 6144, 54054},
1135 {7417, 11648, 210937, 17836, 234375, 11648, 140625},
1136 {7425, 4096, 74250, 6272, 82500, 6144, 74250},
1137 {14835, 11648, 421875, 8918, 234375, 5824, 140625},
1138 {14850, 4096, 148500, 6272, 165000, 6144, 148500},
1139 {29670, 5824, 421875, 4459, 234375, 5824, 281250},
1140 {29700, 3072, 222750, 4704, 247500, 5120, 247500},
1141 {59340, 5824, 843750, 8918, 937500, 5824, 562500},
1142 {59400, 3072, 445500, 9408, 990000, 6144, 594000}
1145 static const struct audio_clock_info audio_clock_info_table_36bpc[14] = {
1146 {2517, 9152, 84375, 7007, 48875, 9152, 56250},
1147 {2518, 9152, 84375, 7007, 48875, 9152, 56250},
1148 {2520, 4096, 37800, 6272, 42000, 6144, 37800},
1149 {2700, 4096, 40500, 6272, 45000, 6144, 40500},
1150 {2702, 8192, 81081, 6272, 45045, 8192, 54054},
1151 {2703, 8192, 81081, 6272, 45045, 8192, 54054},
1152 {5400, 4096, 81000, 6272, 90000, 6144, 81000},
1153 {5405, 4096, 81081, 6272, 90090, 6144, 81081},
1154 {7417, 11648, 316406, 17836, 351562, 11648, 210937},
1155 {7425, 4096, 111375, 6272, 123750, 6144, 111375},
1156 {14835, 11648, 632812, 17836, 703125, 11648, 421875},
1157 {14850, 4096, 222750, 6272, 247500, 6144, 222750},
1158 {29670, 5824, 632812, 8918, 703125, 5824, 421875},
1159 {29700, 4096, 445500, 4704, 371250, 5120, 371250}
1162 static const struct audio_clock_info audio_clock_info_table_48bpc[14] = {
1163 {2517, 4576, 56250, 7007, 62500, 6864, 56250},
1164 {2518, 4576, 56250, 7007, 62500, 6864, 56250},
1165 {2520, 4096, 50400, 6272, 56000, 6144, 50400},
1166 {2700, 4096, 54000, 6272, 60000, 6144, 54000},
1167 {2702, 4096, 54054, 6267, 60060, 8192, 54054},
1168 {2703, 4096, 54054, 6272, 60060, 8192, 54054},
1169 {5400, 4096, 108000, 6272, 120000, 6144, 108000},
1170 {5405, 4096, 108108, 6272, 120120, 6144, 108108},
1171 {7417, 11648, 421875, 17836, 468750, 11648, 281250},
1172 {7425, 4096, 148500, 6272, 165000, 6144, 148500},
1173 {14835, 11648, 843750, 8918, 468750, 11648, 281250},
1174 {14850, 4096, 297000, 6272, 330000, 6144, 297000},
1175 {29670, 5824, 843750, 4459, 468750, 5824, 562500},
1176 {29700, 3072, 445500, 4704, 495000, 5120, 495000}
1181 static union audio_cea_channels speakers_to_channels(
1182 struct audio_speaker_flags speaker_flags)
1184 union audio_cea_channels cea_channels = {0};
1186 /* these are one to one */
1187 cea_channels.channels.FL = speaker_flags.FL_FR;
1188 cea_channels.channels.FR = speaker_flags.FL_FR;
1189 cea_channels.channels.LFE = speaker_flags.LFE;
1190 cea_channels.channels.FC = speaker_flags.FC;
1192 /* if Rear Left and Right exist move RC speaker to channel 7
1193 * otherwise to channel 5
1195 if (speaker_flags.RL_RR) {
1196 cea_channels.channels.RL_RC = speaker_flags.RL_RR;
1197 cea_channels.channels.RR = speaker_flags.RL_RR;
1198 cea_channels.channels.RC_RLC_FLC = speaker_flags.RC;
1200 cea_channels.channels.RL_RC = speaker_flags.RC;
1203 /* FRONT Left Right Center and REAR Left Right Center are exclusive */
1204 if (speaker_flags.FLC_FRC) {
1205 cea_channels.channels.RC_RLC_FLC = speaker_flags.FLC_FRC;
1206 cea_channels.channels.RRC_FRC = speaker_flags.FLC_FRC;
1208 cea_channels.channels.RC_RLC_FLC = speaker_flags.RLC_RRC;
1209 cea_channels.channels.RRC_FRC = speaker_flags.RLC_RRC;
1212 return cea_channels;
1215 static uint32_t calc_max_audio_packets_per_line(
1216 const struct audio_crtc_info *crtc_info)
1218 uint32_t max_packets_per_line;
1220 max_packets_per_line =
1221 crtc_info->h_total - crtc_info->h_active;
1223 if (crtc_info->pixel_repetition)
1224 max_packets_per_line *= crtc_info->pixel_repetition;
1226 /* for other hdmi features */
1227 max_packets_per_line -= 58;
1228 /* for Control Period */
1229 max_packets_per_line -= 16;
1230 /* Number of Audio Packets per Line */
1231 max_packets_per_line /= 32;
1233 return max_packets_per_line;
1236 static void get_audio_clock_info(
1237 enum dc_color_depth color_depth,
1238 uint32_t crtc_pixel_clock_in_khz,
1239 uint32_t actual_pixel_clock_in_khz,
1240 struct audio_clock_info *audio_clock_info)
1242 const struct audio_clock_info *clock_info;
1244 uint32_t crtc_pixel_clock_in_10khz = crtc_pixel_clock_in_khz / 10;
1245 uint32_t audio_array_size;
1247 switch (color_depth) {
1248 case COLOR_DEPTH_161616:
1249 clock_info = audio_clock_info_table_48bpc;
1250 audio_array_size = ARRAY_SIZE(
1251 audio_clock_info_table_48bpc);
1253 case COLOR_DEPTH_121212:
1254 clock_info = audio_clock_info_table_36bpc;
1255 audio_array_size = ARRAY_SIZE(
1256 audio_clock_info_table_36bpc);
1259 clock_info = audio_clock_info_table;
1260 audio_array_size = ARRAY_SIZE(
1261 audio_clock_info_table);
1265 if (clock_info != NULL) {
1266 /* search for exact pixel clock in table */
1267 for (index = 0; index < audio_array_size; index++) {
1268 if (clock_info[index].pixel_clock_in_10khz >
1269 crtc_pixel_clock_in_10khz)
1270 break; /* not match */
1271 else if (clock_info[index].pixel_clock_in_10khz ==
1272 crtc_pixel_clock_in_10khz) {
1274 *audio_clock_info = clock_info[index];
1281 if (actual_pixel_clock_in_khz == 0)
1282 actual_pixel_clock_in_khz = crtc_pixel_clock_in_khz;
1284 /* See HDMI spec the table entry under
1285 * pixel clock of "Other". */
1286 audio_clock_info->pixel_clock_in_10khz =
1287 actual_pixel_clock_in_khz / 10;
1288 audio_clock_info->cts_32khz = actual_pixel_clock_in_khz;
1289 audio_clock_info->cts_44khz = actual_pixel_clock_in_khz;
1290 audio_clock_info->cts_48khz = actual_pixel_clock_in_khz;
1292 audio_clock_info->n_32khz = 4096;
1293 audio_clock_info->n_44khz = 6272;
1294 audio_clock_info->n_48khz = 6144;
1297 static void dce110_se_audio_setup(
1298 struct stream_encoder *enc,
1299 unsigned int az_inst,
1300 struct audio_info *audio_info)
1302 struct dce110_stream_encoder *enc110 = DCE110STRENC_FROM_STRENC(enc);
1304 uint32_t speakers = 0;
1305 uint32_t channels = 0;
1308 if (audio_info == NULL)
1309 /* This should not happen.it does so we don't get BSOD*/
1312 speakers = audio_info->flags.info.ALLSPEAKERS;
1313 channels = speakers_to_channels(audio_info->flags.speaker_flags).all;
1315 /* setup the audio stream source select (audio -> dig mapping) */
1316 REG_SET(AFMT_AUDIO_SRC_CONTROL, 0, AFMT_AUDIO_SRC_SELECT, az_inst);
1318 /* Channel allocation */
1319 REG_UPDATE(AFMT_AUDIO_PACKET_CONTROL2, AFMT_AUDIO_CHANNEL_ENABLE, channels);
1322 static void dce110_se_setup_hdmi_audio(
1323 struct stream_encoder *enc,
1324 const struct audio_crtc_info *crtc_info)
1326 struct dce110_stream_encoder *enc110 = DCE110STRENC_FROM_STRENC(enc);
1328 struct audio_clock_info audio_clock_info = {0};
1329 uint32_t max_packets_per_line;
1331 /* For now still do calculation, although this field is ignored when
1332 above HDMI_PACKET_GEN_VERSION set to 1 */
1333 max_packets_per_line = calc_max_audio_packets_per_line(crtc_info);
1335 /* HDMI_AUDIO_PACKET_CONTROL */
1336 REG_UPDATE_2(HDMI_AUDIO_PACKET_CONTROL,
1337 HDMI_AUDIO_PACKETS_PER_LINE, max_packets_per_line,
1338 HDMI_AUDIO_DELAY_EN, 1);
1340 /* AFMT_AUDIO_PACKET_CONTROL */
1341 REG_UPDATE(AFMT_AUDIO_PACKET_CONTROL, AFMT_60958_CS_UPDATE, 1);
1343 /* AFMT_AUDIO_PACKET_CONTROL2 */
1344 REG_UPDATE_2(AFMT_AUDIO_PACKET_CONTROL2,
1345 AFMT_AUDIO_LAYOUT_OVRD, 0,
1346 AFMT_60958_OSF_OVRD, 0);
1348 /* HDMI_ACR_PACKET_CONTROL */
1349 REG_UPDATE_3(HDMI_ACR_PACKET_CONTROL,
1350 HDMI_ACR_AUTO_SEND, 1,
1352 HDMI_ACR_AUDIO_PRIORITY, 0);
1354 /* Program audio clock sample/regeneration parameters */
1355 get_audio_clock_info(crtc_info->color_depth,
1356 crtc_info->requested_pixel_clock,
1357 crtc_info->calculated_pixel_clock,
1360 "\n%s:Input::requested_pixel_clock = %d" \
1361 "calculated_pixel_clock = %d \n", __func__, \
1362 crtc_info->requested_pixel_clock, \
1363 crtc_info->calculated_pixel_clock);
1365 /* HDMI_ACR_32_0__HDMI_ACR_CTS_32_MASK */
1366 REG_UPDATE(HDMI_ACR_32_0, HDMI_ACR_CTS_32, audio_clock_info.cts_32khz);
1368 /* HDMI_ACR_32_1__HDMI_ACR_N_32_MASK */
1369 REG_UPDATE(HDMI_ACR_32_1, HDMI_ACR_N_32, audio_clock_info.n_32khz);
1371 /* HDMI_ACR_44_0__HDMI_ACR_CTS_44_MASK */
1372 REG_UPDATE(HDMI_ACR_44_0, HDMI_ACR_CTS_44, audio_clock_info.cts_44khz);
1374 /* HDMI_ACR_44_1__HDMI_ACR_N_44_MASK */
1375 REG_UPDATE(HDMI_ACR_44_1, HDMI_ACR_N_44, audio_clock_info.n_44khz);
1377 /* HDMI_ACR_48_0__HDMI_ACR_CTS_48_MASK */
1378 REG_UPDATE(HDMI_ACR_48_0, HDMI_ACR_CTS_48, audio_clock_info.cts_48khz);
1380 /* HDMI_ACR_48_1__HDMI_ACR_N_48_MASK */
1381 REG_UPDATE(HDMI_ACR_48_1, HDMI_ACR_N_48, audio_clock_info.n_48khz);
1383 /* Video driver cannot know in advance which sample rate will
1384 be used by HD Audio driver
1385 HDMI_ACR_PACKET_CONTROL__HDMI_ACR_N_MULTIPLE field is
1386 programmed below in interruppt callback */
1388 /* AFMT_60958_0__AFMT_60958_CS_CHANNEL_NUMBER_L_MASK &
1389 AFMT_60958_0__AFMT_60958_CS_CLOCK_ACCURACY_MASK */
1390 REG_UPDATE_2(AFMT_60958_0,
1391 AFMT_60958_CS_CHANNEL_NUMBER_L, 1,
1392 AFMT_60958_CS_CLOCK_ACCURACY, 0);
1394 /* AFMT_60958_1 AFMT_60958_CS_CHALNNEL_NUMBER_R */
1395 REG_UPDATE(AFMT_60958_1, AFMT_60958_CS_CHANNEL_NUMBER_R, 2);
1397 /*AFMT_60958_2 now keep this settings until
1398 * Programming guide comes out*/
1399 REG_UPDATE_6(AFMT_60958_2,
1400 AFMT_60958_CS_CHANNEL_NUMBER_2, 3,
1401 AFMT_60958_CS_CHANNEL_NUMBER_3, 4,
1402 AFMT_60958_CS_CHANNEL_NUMBER_4, 5,
1403 AFMT_60958_CS_CHANNEL_NUMBER_5, 6,
1404 AFMT_60958_CS_CHANNEL_NUMBER_6, 7,
1405 AFMT_60958_CS_CHANNEL_NUMBER_7, 8);
1408 static void dce110_se_setup_dp_audio(
1409 struct stream_encoder *enc)
1411 struct dce110_stream_encoder *enc110 = DCE110STRENC_FROM_STRENC(enc);
1413 /* --- DP Audio packet configurations --- */
1415 /* ATP Configuration */
1416 REG_SET(DP_SEC_AUD_N, 0,
1417 DP_SEC_AUD_N, DP_SEC_AUD_N__DP_SEC_AUD_N__DEFAULT);
1419 /* Async/auto-calc timestamp mode */
1420 REG_SET(DP_SEC_TIMESTAMP, 0, DP_SEC_TIMESTAMP_MODE,
1421 DP_SEC_TIMESTAMP__DP_SEC_TIMESTAMP_MODE__AUTO_CALC);
1423 /* --- The following are the registers
1424 * copied from the SetupHDMI --- */
1426 /* AFMT_AUDIO_PACKET_CONTROL */
1427 REG_UPDATE(AFMT_AUDIO_PACKET_CONTROL, AFMT_60958_CS_UPDATE, 1);
1429 /* AFMT_AUDIO_PACKET_CONTROL2 */
1430 /* Program the ATP and AIP next */
1431 REG_UPDATE_2(AFMT_AUDIO_PACKET_CONTROL2,
1432 AFMT_AUDIO_LAYOUT_OVRD, 0,
1433 AFMT_60958_OSF_OVRD, 0);
1435 /* AFMT_INFOFRAME_CONTROL0 */
1436 REG_UPDATE(AFMT_INFOFRAME_CONTROL0, AFMT_AUDIO_INFO_UPDATE, 1);
1438 /* AFMT_60958_0__AFMT_60958_CS_CLOCK_ACCURACY_MASK */
1439 REG_UPDATE(AFMT_60958_0, AFMT_60958_CS_CLOCK_ACCURACY, 0);
1442 static void dce110_se_enable_audio_clock(
1443 struct stream_encoder *enc,
1446 struct dce110_stream_encoder *enc110 = DCE110STRENC_FROM_STRENC(enc);
1448 if (REG(AFMT_CNTL) == 0)
1449 return; /* DCE8/10 does not have this register */
1451 REG_UPDATE(AFMT_CNTL, AFMT_AUDIO_CLOCK_EN, !!enable);
1453 /* wait for AFMT clock to turn on,
1454 * expectation: this should complete in 1-2 reads
1456 * REG_WAIT(AFMT_CNTL, AFMT_AUDIO_CLOCK_ON, !!enable, 1, 10);
1458 * TODO: wait for clock_on does not work well. May need HW
1459 * program sequence. But audio seems work normally even without wait
1460 * for clock_on status change
1464 static void dce110_se_enable_dp_audio(
1465 struct stream_encoder *enc)
1467 struct dce110_stream_encoder *enc110 = DCE110STRENC_FROM_STRENC(enc);
1469 /* Enable Audio packets */
1470 REG_UPDATE(DP_SEC_CNTL, DP_SEC_ASP_ENABLE, 1);
1472 /* Program the ATP and AIP next */
1473 REG_UPDATE_2(DP_SEC_CNTL,
1474 DP_SEC_ATP_ENABLE, 1,
1475 DP_SEC_AIP_ENABLE, 1);
1477 /* Program STREAM_ENABLE after all the other enables. */
1478 REG_UPDATE(DP_SEC_CNTL, DP_SEC_STREAM_ENABLE, 1);
1481 static void dce110_se_disable_dp_audio(
1482 struct stream_encoder *enc)
1484 struct dce110_stream_encoder *enc110 = DCE110STRENC_FROM_STRENC(enc);
1487 /* Disable Audio packets */
1488 REG_UPDATE_5(DP_SEC_CNTL,
1489 DP_SEC_ASP_ENABLE, 0,
1490 DP_SEC_ATP_ENABLE, 0,
1491 DP_SEC_AIP_ENABLE, 0,
1492 DP_SEC_ACM_ENABLE, 0,
1493 DP_SEC_STREAM_ENABLE, 0);
1495 /* This register shared with encoder info frame. Therefore we need to
1496 keep master enabled if at least on of the fields is not 0 */
1497 value = REG_READ(DP_SEC_CNTL);
1499 REG_UPDATE(DP_SEC_CNTL, DP_SEC_STREAM_ENABLE, 1);
1503 void dce110_se_audio_mute_control(
1504 struct stream_encoder *enc,
1507 struct dce110_stream_encoder *enc110 = DCE110STRENC_FROM_STRENC(enc);
1509 REG_UPDATE(AFMT_AUDIO_PACKET_CONTROL, AFMT_AUDIO_SAMPLE_SEND, !mute);
1512 void dce110_se_dp_audio_setup(
1513 struct stream_encoder *enc,
1514 unsigned int az_inst,
1515 struct audio_info *info)
1517 dce110_se_audio_setup(enc, az_inst, info);
1520 void dce110_se_dp_audio_enable(
1521 struct stream_encoder *enc)
1523 dce110_se_enable_audio_clock(enc, true);
1524 dce110_se_setup_dp_audio(enc);
1525 dce110_se_enable_dp_audio(enc);
1528 void dce110_se_dp_audio_disable(
1529 struct stream_encoder *enc)
1531 dce110_se_disable_dp_audio(enc);
1532 dce110_se_enable_audio_clock(enc, false);
1535 void dce110_se_hdmi_audio_setup(
1536 struct stream_encoder *enc,
1537 unsigned int az_inst,
1538 struct audio_info *info,
1539 struct audio_crtc_info *audio_crtc_info)
1541 dce110_se_enable_audio_clock(enc, true);
1542 dce110_se_setup_hdmi_audio(enc, audio_crtc_info);
1543 dce110_se_audio_setup(enc, az_inst, info);
1546 void dce110_se_hdmi_audio_disable(
1547 struct stream_encoder *enc)
1549 dce110_se_enable_audio_clock(enc, false);
1553 static void setup_stereo_sync(
1554 struct stream_encoder *enc,
1555 int tg_inst, bool enable)
1557 struct dce110_stream_encoder *enc110 = DCE110STRENC_FROM_STRENC(enc);
1558 REG_UPDATE(DIG_FE_CNTL, DIG_STEREOSYNC_SELECT, tg_inst);
1559 REG_UPDATE(DIG_FE_CNTL, DIG_STEREOSYNC_GATE_EN, !enable);
1563 static const struct stream_encoder_funcs dce110_str_enc_funcs = {
1564 .dp_set_stream_attribute =
1565 dce110_stream_encoder_dp_set_stream_attribute,
1566 .hdmi_set_stream_attribute =
1567 dce110_stream_encoder_hdmi_set_stream_attribute,
1568 .dvi_set_stream_attribute =
1569 dce110_stream_encoder_dvi_set_stream_attribute,
1570 .set_mst_bandwidth =
1571 dce110_stream_encoder_set_mst_bandwidth,
1572 .update_hdmi_info_packets =
1573 dce110_stream_encoder_update_hdmi_info_packets,
1574 .stop_hdmi_info_packets =
1575 dce110_stream_encoder_stop_hdmi_info_packets,
1576 .update_dp_info_packets =
1577 dce110_stream_encoder_update_dp_info_packets,
1578 .stop_dp_info_packets =
1579 dce110_stream_encoder_stop_dp_info_packets,
1581 dce110_stream_encoder_dp_blank,
1583 dce110_stream_encoder_dp_unblank,
1584 .audio_mute_control = dce110_se_audio_mute_control,
1586 .dp_audio_setup = dce110_se_dp_audio_setup,
1587 .dp_audio_enable = dce110_se_dp_audio_enable,
1588 .dp_audio_disable = dce110_se_dp_audio_disable,
1590 .hdmi_audio_setup = dce110_se_hdmi_audio_setup,
1591 .hdmi_audio_disable = dce110_se_hdmi_audio_disable,
1592 .setup_stereo_sync = setup_stereo_sync,
1593 .set_avmute = dce110_stream_encoder_set_avmute,
1597 void dce110_stream_encoder_construct(
1598 struct dce110_stream_encoder *enc110,
1599 struct dc_context *ctx,
1601 enum engine_id eng_id,
1602 const struct dce110_stream_enc_registers *regs,
1603 const struct dce_stream_encoder_shift *se_shift,
1604 const struct dce_stream_encoder_mask *se_mask)
1606 enc110->base.funcs = &dce110_str_enc_funcs;
1607 enc110->base.ctx = ctx;
1608 enc110->base.id = eng_id;
1609 enc110->base.bp = bp;
1610 enc110->regs = regs;
1611 enc110->se_shift = se_shift;
1612 enc110->se_mask = se_mask;