drivers/gpu/drm/amd/display/dc/dce110/dce110_compressor.c

   1 /*
   2  * Copyright 2012-15 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: AMD
  23  *
  24  */
  25
  26 #include "dm_services.h"
  27
  28 #include "dce/dce_11_0_d.h"
  29 #include "dce/dce_11_0_sh_mask.h"
  30 #include "gmc/gmc_8_2_sh_mask.h"
  31 #include "gmc/gmc_8_2_d.h"
  32
  33 #include "include/logger_interface.h"
  34
  35 #include "dce110_compressor.h"
  36
  37 #define DC_LOGGER \
  38                 cp110->base.ctx->logger
  39 #define DCP_REG(reg)\
  40         (reg + cp110->offsets.dcp_offset)
  41 #define DMIF_REG(reg)\
  42         (reg + cp110->offsets.dmif_offset)
  43
  44 static const struct dce110_compressor_reg_offsets reg_offsets[] = {
  45 {
  46         .dcp_offset = (mmDCP0_GRPH_CONTROL - mmDCP0_GRPH_CONTROL),
  47         .dmif_offset =
  48                 (mmDMIF_PG0_DPG_PIPE_DPM_CONTROL
  49                         - mmDMIF_PG0_DPG_PIPE_DPM_CONTROL),
  50 },
  51 {
  52         .dcp_offset = (mmDCP1_GRPH_CONTROL - mmDCP0_GRPH_CONTROL),
  53         .dmif_offset =
  54                 (mmDMIF_PG1_DPG_PIPE_DPM_CONTROL
  55                         - mmDMIF_PG0_DPG_PIPE_DPM_CONTROL),
  56 },
  57 {
  58         .dcp_offset = (mmDCP2_GRPH_CONTROL - mmDCP0_GRPH_CONTROL),
  59         .dmif_offset =
  60                 (mmDMIF_PG2_DPG_PIPE_DPM_CONTROL
  61                         - mmDMIF_PG0_DPG_PIPE_DPM_CONTROL),
  62 }
  63 };
  64
  65 static const uint32_t dce11_one_lpt_channel_max_resolution = 2560 * 1600;
  66
  67 enum fbc_idle_force {
  68         /* Bit 0 - Display registers updated */
  69         FBC_IDLE_FORCE_DISPLAY_REGISTER_UPDATE = 0x00000001,
  70
  71         /* Bit 2 - FBC_GRPH_COMP_EN register updated */
  72         FBC_IDLE_FORCE_GRPH_COMP_EN = 0x00000002,
  73         /* Bit 3 - FBC_SRC_SEL register updated */
  74         FBC_IDLE_FORCE_SRC_SEL_CHANGE = 0x00000004,
  75         /* Bit 4 - FBC_MIN_COMPRESSION register updated */
  76         FBC_IDLE_FORCE_MIN_COMPRESSION_CHANGE = 0x00000008,
  77         /* Bit 5 - FBC_ALPHA_COMP_EN register updated */
  78         FBC_IDLE_FORCE_ALPHA_COMP_EN = 0x00000010,
  79         /* Bit 6 - FBC_ZERO_ALPHA_CHUNK_SKIP_EN register updated */
  80         FBC_IDLE_FORCE_ZERO_ALPHA_CHUNK_SKIP_EN = 0x00000020,
  81         /* Bit 7 - FBC_FORCE_COPY_TO_COMP_BUF register updated */
  82         FBC_IDLE_FORCE_FORCE_COPY_TO_COMP_BUF = 0x00000040,
  83
  84         /* Bit 24 - Memory write to region 0 defined by MC registers. */
  85         FBC_IDLE_FORCE_MEMORY_WRITE_TO_REGION0 = 0x01000000,
  86         /* Bit 25 - Memory write to region 1 defined by MC registers */
  87         FBC_IDLE_FORCE_MEMORY_WRITE_TO_REGION1 = 0x02000000,
  88         /* Bit 26 - Memory write to region 2 defined by MC registers */
  89         FBC_IDLE_FORCE_MEMORY_WRITE_TO_REGION2 = 0x04000000,
  90         /* Bit 27 - Memory write to region 3 defined by MC registers. */
  91         FBC_IDLE_FORCE_MEMORY_WRITE_TO_REGION3 = 0x08000000,
  92
  93         /* Bit 28 - Memory write from any client other than MCIF */
  94         FBC_IDLE_FORCE_MEMORY_WRITE_OTHER_THAN_MCIF = 0x10000000,
  95         /* Bit 29 - CG statics screen signal is inactive */
  96         FBC_IDLE_FORCE_CG_STATIC_SCREEN_IS_INACTIVE = 0x20000000,
  97 };
  98
  99
 100 static uint32_t align_to_chunks_number_per_line(uint32_t pixels)
 101 {
 102         return 256 * ((pixels + 255) / 256);
 103 }
 104
 105 static void wait_for_fbc_state_changed(
 106         struct dce110_compressor *cp110,
 107         bool enabled)
 108 {
 109         uint8_t counter = 0;
 110         uint32_t addr = mmFBC_STATUS;
 111         uint32_t value;
 112
 113         while (counter < 10) {
 114                 value = dm_read_reg(cp110->base.ctx, addr);
 115                 if (get_reg_field_value(
 116                         value,
 117                         FBC_STATUS,
 118                         FBC_ENABLE_STATUS) == enabled)
 119                         break;
 120                 msleep(10);
 121                 counter++;
 122         }
 123
 124         if (counter == 10) {
 125                 DC_LOG_WARNING("%s: wait counter exceeded, changes to HW not applied",
 126                         __func__);
 127         } else {
 128                 DC_LOG_SYNC("FBC status changed to %d", enabled);
 129         }
 130
 131
 132 }
 133
 134 void dce110_compressor_power_up_fbc(struct compressor *compressor)
 135 {
 136         uint32_t value;
 137         uint32_t addr;
 138
 139         addr = mmFBC_CNTL;
 140         value = dm_read_reg(compressor->ctx, addr);
 141         set_reg_field_value(value, 0, FBC_CNTL, FBC_GRPH_COMP_EN);
 142         set_reg_field_value(value, 1, FBC_CNTL, FBC_EN);
 143         set_reg_field_value(value, 2, FBC_CNTL, FBC_COHERENCY_MODE);
 144         if (compressor->options.bits.CLK_GATING_DISABLED == 1) {
 145                 /* HW needs to do power measurement comparison. */
 146                 set_reg_field_value(
 147                         value,
 148                         0,
 149                         FBC_CNTL,
 150                         FBC_COMP_CLK_GATE_EN);
 151         }
 152         dm_write_reg(compressor->ctx, addr, value);
 153
 154         addr = mmFBC_COMP_MODE;
 155         value = dm_read_reg(compressor->ctx, addr);
 156         set_reg_field_value(value, 1, FBC_COMP_MODE, FBC_RLE_EN);
 157         set_reg_field_value(value, 1, FBC_COMP_MODE, FBC_DPCM4_RGB_EN);
 158         set_reg_field_value(value, 1, FBC_COMP_MODE, FBC_IND_EN);
 159         dm_write_reg(compressor->ctx, addr, value);
 160
 161         addr = mmFBC_COMP_CNTL;
 162         value = dm_read_reg(compressor->ctx, addr);
 163         set_reg_field_value(value, 1, FBC_COMP_CNTL, FBC_DEPTH_RGB08_EN);
 164         dm_write_reg(compressor->ctx, addr, value);
 165         /*FBC_MIN_COMPRESSION 0 ==> 2:1 */
 166         /*                    1 ==> 4:1 */
 167         /*                    2 ==> 8:1 */
 168         /*                  0xF ==> 1:1 */
 169         set_reg_field_value(value, 0xF, FBC_COMP_CNTL, FBC_MIN_COMPRESSION);
 170         dm_write_reg(compressor->ctx, addr, value);
 171         compressor->min_compress_ratio = FBC_COMPRESS_RATIO_1TO1;
 172
 173         value = 0;
 174         dm_write_reg(compressor->ctx, mmFBC_IND_LUT0, value);
 175
 176         value = 0xFFFFFF;
 177         dm_write_reg(compressor->ctx, mmFBC_IND_LUT1, value);
 178 }
 179
 180 void dce110_compressor_enable_fbc(
 181         struct compressor *compressor,
 182         struct compr_addr_and_pitch_params *params)
 183 {
 184         struct dce110_compressor *cp110 = TO_DCE110_COMPRESSOR(compressor);
 185
 186         if (compressor->options.bits.FBC_SUPPORT &&
 187                 (!dce110_compressor_is_fbc_enabled_in_hw(compressor, NULL))) {
 188
 189                 uint32_t addr;
 190                 uint32_t value, misc_value;
 191
 192
 193                 addr = mmFBC_CNTL;
 194                 value = dm_read_reg(compressor->ctx, addr);
 195                 set_reg_field_value(value, 1, FBC_CNTL, FBC_GRPH_COMP_EN);
 196                 set_reg_field_value(
 197                         value,
 198                         params->inst,
 199                         FBC_CNTL, FBC_SRC_SEL);
 200                 dm_write_reg(compressor->ctx, addr, value);
 201
 202                 /* Keep track of enum controller_id FBC is attached to */
 203                 compressor->is_enabled = true;
 204                 compressor->attached_inst = params->inst;
 205                 cp110->offsets = reg_offsets[params->inst];
 206
 207                 /* Toggle it as there is bug in HW */
 208                 set_reg_field_value(value, 0, FBC_CNTL, FBC_GRPH_COMP_EN);
 209                 dm_write_reg(compressor->ctx, addr, value);
 210
 211                 /* FBC usage with scatter & gather for dce110 */
 212                 misc_value = dm_read_reg(compressor->ctx, mmFBC_MISC);
 213
 214                 set_reg_field_value(misc_value, 1,
 215                                 FBC_MISC, FBC_INVALIDATE_ON_ERROR);
 216                 set_reg_field_value(misc_value, 1,
 217                                 FBC_MISC, FBC_DECOMPRESS_ERROR_CLEAR);
 218                 set_reg_field_value(misc_value, 0x14,
 219                                 FBC_MISC, FBC_SLOW_REQ_INTERVAL);
 220
 221                 dm_write_reg(compressor->ctx, mmFBC_MISC, misc_value);
 222
 223                 /* Enable FBC */
 224                 set_reg_field_value(value, 1, FBC_CNTL, FBC_GRPH_COMP_EN);
 225                 dm_write_reg(compressor->ctx, addr, value);
 226
 227                 wait_for_fbc_state_changed(cp110, true);
 228         }
 229 }
 230
 231 void dce110_compressor_disable_fbc(struct compressor *compressor)
 232 {
 233         struct dce110_compressor *cp110 = TO_DCE110_COMPRESSOR(compressor);
 234
 235         if (compressor->options.bits.FBC_SUPPORT &&
 236                 dce110_compressor_is_fbc_enabled_in_hw(compressor, NULL)) {
 237                 uint32_t reg_data;
 238                 /* Turn off compression */
 239                 reg_data = dm_read_reg(compressor->ctx, mmFBC_CNTL);
 240                 set_reg_field_value(reg_data, 0, FBC_CNTL, FBC_GRPH_COMP_EN);
 241                 dm_write_reg(compressor->ctx, mmFBC_CNTL, reg_data);
 242
 243                 /* Reset enum controller_id to undefined */
 244                 compressor->attached_inst = 0;
 245                 compressor->is_enabled = false;
 246
 247                 wait_for_fbc_state_changed(cp110, false);
 248         }
 249 }
 250
 251 bool dce110_compressor_is_fbc_enabled_in_hw(
 252         struct compressor *compressor,
 253         uint32_t *inst)
 254 {
 255         /* Check the hardware register */
 256         uint32_t value;
 257
 258         value = dm_read_reg(compressor->ctx, mmFBC_STATUS);
 259         if (get_reg_field_value(value, FBC_STATUS, FBC_ENABLE_STATUS)) {
 260                 if (inst != NULL)
 261                         *inst = compressor->attached_inst;
 262                 return true;
 263         }
 264
 265         value = dm_read_reg(compressor->ctx, mmFBC_MISC);
 266         if (get_reg_field_value(value, FBC_MISC, FBC_STOP_ON_HFLIP_EVENT)) {
 267                 value = dm_read_reg(compressor->ctx, mmFBC_CNTL);
 268
 269                 if (get_reg_field_value(value, FBC_CNTL, FBC_GRPH_COMP_EN)) {
 270                         if (inst != NULL)
 271                                 *inst =
 272                                         compressor->attached_inst;
 273                         return true;
 274                 }
 275         }
 276         return false;
 277 }
 278
 279
 280 void dce110_compressor_program_compressed_surface_address_and_pitch(
 281         struct compressor *compressor,
 282         struct compr_addr_and_pitch_params *params)
 283 {
 284         struct dce110_compressor *cp110 = TO_DCE110_COMPRESSOR(compressor);
 285         uint32_t value = 0;
 286         uint32_t fbc_pitch = 0;
 287         uint32_t compressed_surf_address_low_part =
 288                 compressor->compr_surface_address.addr.low_part;
 289
 290         /* Clear content first. */
 291         dm_write_reg(
 292                 compressor->ctx,
 293                 DCP_REG(mmGRPH_COMPRESS_SURFACE_ADDRESS_HIGH),
 294                 0);
 295         dm_write_reg(compressor->ctx,
 296                 DCP_REG(mmGRPH_COMPRESS_SURFACE_ADDRESS), 0);
 297
 298         /* Write address, HIGH has to be first. */
 299         dm_write_reg(compressor->ctx,
 300                 DCP_REG(mmGRPH_COMPRESS_SURFACE_ADDRESS_HIGH),
 301                 compressor->compr_surface_address.addr.high_part);
 302         dm_write_reg(compressor->ctx,
 303                 DCP_REG(mmGRPH_COMPRESS_SURFACE_ADDRESS),
 304                 compressed_surf_address_low_part);
 305
 306         fbc_pitch = align_to_chunks_number_per_line(params->source_view_width);
 307
 308         if (compressor->min_compress_ratio == FBC_COMPRESS_RATIO_1TO1)
 309                 fbc_pitch = fbc_pitch / 8;
 310         else
 311                 DC_LOG_WARNING("%s: Unexpected DCE11 compression ratio",
 312                         __func__);
 313
 314         /* Clear content first. */
 315         dm_write_reg(compressor->ctx, DCP_REG(mmGRPH_COMPRESS_PITCH), 0);
 316
 317         /* Write FBC Pitch. */
 318         set_reg_field_value(
 319                 value,
 320                 fbc_pitch,
 321                 GRPH_COMPRESS_PITCH,
 322                 GRPH_COMPRESS_PITCH);
 323         dm_write_reg(compressor->ctx, DCP_REG(mmGRPH_COMPRESS_PITCH), value);
 324
 325 }
 326
 327 void dce110_compressor_set_fbc_invalidation_triggers(
 328         struct compressor *compressor,
 329         uint32_t fbc_trigger)
 330 {
 331         /* Disable region hit event, FBC_MEMORY_REGION_MASK = 0 (bits 16-19)
 332          * for DCE 11 regions cannot be used - does not work with S/G
 333          */
 334         uint32_t addr = mmFBC_CLIENT_REGION_MASK;
 335         uint32_t value = dm_read_reg(compressor->ctx, addr);
 336
 337         set_reg_field_value(
 338                 value,
 339                 0,
 340                 FBC_CLIENT_REGION_MASK,
 341                 FBC_MEMORY_REGION_MASK);
 342         dm_write_reg(compressor->ctx, addr, value);
 343
 344         /* Setup events when to clear all CSM entries (effectively marking
 345          * current compressed data invalid)
 346          * For DCE 11 CSM metadata 11111 means - "Not Compressed"
 347          * Used as the initial value of the metadata sent to the compressor
 348          * after invalidation, to indicate that the compressor should attempt
 349          * to compress all chunks on the current pass.  Also used when the chunk
 350          * is not successfully written to memory.
 351          * When this CSM value is detected, FBC reads from the uncompressed
 352          * buffer. Set events according to passed in value, these events are
 353          * valid for DCE11:
 354          *     - bit  0 - display register updated
 355          *     - bit 28 - memory write from any client except from MCIF
 356          *     - bit 29 - CG static screen signal is inactive
 357          * In addition, DCE11.1 also needs to set new DCE11.1 specific events
 358          * that are used to trigger invalidation on certain register changes,
 359          * for example enabling of Alpha Compression may trigger invalidation of
 360          * FBC once bit is set. These events are as follows:
 361          *      - Bit 2 - FBC_GRPH_COMP_EN register updated
 362          *      - Bit 3 - FBC_SRC_SEL register updated
 363          *      - Bit 4 - FBC_MIN_COMPRESSION register updated
 364          *      - Bit 5 - FBC_ALPHA_COMP_EN register updated
 365          *      - Bit 6 - FBC_ZERO_ALPHA_CHUNK_SKIP_EN register updated
 366          *      - Bit 7 - FBC_FORCE_COPY_TO_COMP_BUF register updated
 367          */
 368         addr = mmFBC_IDLE_FORCE_CLEAR_MASK;
 369         value = dm_read_reg(compressor->ctx, addr);
 370         set_reg_field_value(
 371                 value,
 372                 fbc_trigger |
 373                 FBC_IDLE_FORCE_GRPH_COMP_EN |
 374                 FBC_IDLE_FORCE_SRC_SEL_CHANGE |
 375                 FBC_IDLE_FORCE_MIN_COMPRESSION_CHANGE |
 376                 FBC_IDLE_FORCE_ALPHA_COMP_EN |
 377                 FBC_IDLE_FORCE_ZERO_ALPHA_CHUNK_SKIP_EN |
 378                 FBC_IDLE_FORCE_FORCE_COPY_TO_COMP_BUF,
 379                 FBC_IDLE_FORCE_CLEAR_MASK,
 380                 FBC_IDLE_FORCE_CLEAR_MASK);
 381         dm_write_reg(compressor->ctx, addr, value);
 382 }
 383
 384 struct compressor *dce110_compressor_create(struct dc_context *ctx)
 385 {
 386         struct dce110_compressor *cp110 =
 387                 kzalloc(sizeof(struct dce110_compressor), GFP_KERNEL);
 388
 389         if (!cp110)
 390                 return NULL;
 391
 392         dce110_compressor_construct(cp110, ctx);
 393         return &cp110->base;
 394 }
 395
 396 void dce110_compressor_destroy(struct compressor **compressor)
 397 {
 398         kfree(TO_DCE110_COMPRESSOR(*compressor));
 399         *compressor = NULL;
 400 }
 401
 402 bool dce110_get_required_compressed_surfacesize(struct fbc_input_info fbc_input_info,
 403                                                 struct fbc_requested_compressed_size size)
 404 {
 405         bool result = false;
 406
 407         unsigned int max_x = FBC_MAX_X, max_y = FBC_MAX_Y;
 408
 409         get_max_support_fbc_buffersize(&max_x, &max_y);
 410
 411         if (fbc_input_info.dynamic_fbc_buffer_alloc == 0) {
 412                 /*
 413                  * For DCE11 here use Max HW supported size:  HW Support up to 3840x2400 resolution
 414                  * or 18000 chunks.
 415                  */
 416                 size.preferred_size = size.min_size = align_to_chunks_number_per_line(max_x) * max_y * 4;  /* (For FBC when LPT not supported). */
 417                 size.preferred_size_alignment = size.min_size_alignment = 0x100;       /* For FBC when LPT not supported */
 418                 size.bits.preferred_must_be_framebuffer_pool = 1;
 419                 size.bits.min_must_be_framebuffer_pool = 1;
 420
 421                 result = true;
 422         }
 423         /*
 424          * Maybe to add registry key support with optional size here to override above
 425          * for debugging purposes
 426          */
 427
 428         return result;
 429 }
 430
 431
 432 void get_max_support_fbc_buffersize(unsigned int *max_x, unsigned int *max_y)
 433 {
 434         *max_x = FBC_MAX_X;
 435         *max_y = FBC_MAX_Y;
 436
 437         /* if (m_smallLocalFrameBufferMemory == 1)
 438          * {
 439          *      *max_x = FBC_MAX_X_SG;
 440          *      *max_y = FBC_MAX_Y_SG;
 441          * }
 442          */
 443 }
 444
 445
 446 unsigned int controller_id_to_index(enum controller_id controller_id)
 447 {
 448         unsigned int index = 0;
 449
 450         switch (controller_id) {
 451         case CONTROLLER_ID_D0:
 452                 index = 0;
 453                 break;
 454         case CONTROLLER_ID_D1:
 455                 index = 1;
 456                 break;
 457         case CONTROLLER_ID_D2:
 458                 index = 2;
 459                 break;
 460         case CONTROLLER_ID_D3:
 461                 index = 3;
 462                 break;
 463         default:
 464                 break;
 465         }
 466         return index;
 467 }
 468
 469
 470 static const struct compressor_funcs dce110_compressor_funcs = {
 471         .power_up_fbc = dce110_compressor_power_up_fbc,
 472         .enable_fbc = dce110_compressor_enable_fbc,
 473         .disable_fbc = dce110_compressor_disable_fbc,
 474         .set_fbc_invalidation_triggers = dce110_compressor_set_fbc_invalidation_triggers,
 475         .surface_address_and_pitch = dce110_compressor_program_compressed_surface_address_and_pitch,
 476         .is_fbc_enabled_in_hw = dce110_compressor_is_fbc_enabled_in_hw
 477 };
 478
 479
 480 void dce110_compressor_construct(struct dce110_compressor *compressor,
 481         struct dc_context *ctx)
 482 {
 483
 484         compressor->base.options.raw = 0;
 485         compressor->base.options.bits.FBC_SUPPORT = true;
 486
 487         /* for dce 11 always use one dram channel for lpt */
 488         compressor->base.lpt_channels_num = 1;
 489         compressor->base.options.bits.DUMMY_BACKEND = false;
 490
 491         /*
 492          * check if this system has more than 1 dram channel; if only 1 then lpt
 493          * should not be supported
 494          */
 495
 496
 497         compressor->base.options.bits.CLK_GATING_DISABLED = false;
 498
 499         compressor->base.ctx = ctx;
 500         compressor->base.embedded_panel_h_size = 0;
 501         compressor->base.embedded_panel_v_size = 0;
 502         compressor->base.memory_bus_width = ctx->asic_id.vram_width;
 503         compressor->base.allocated_size = 0;
 504         compressor->base.preferred_requested_size = 0;
 505         compressor->base.min_compress_ratio = FBC_COMPRESS_RATIO_INVALID;
 506         compressor->base.banks_num = 0;
 507         compressor->base.raw_size = 0;
 508         compressor->base.channel_interleave_size = 0;
 509         compressor->base.dram_channels_num = 0;
 510         compressor->base.lpt_channels_num = 0;
 511         compressor->base.attached_inst = 0;
 512         compressor->base.is_enabled = false;
 513 #if defined(CONFIG_DRM_AMD_DC_FBC)
 514         compressor->base.funcs = &dce110_compressor_funcs;
 515
 516 #endif
 517 }
 518