drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c

   1 /*
   2  * Copyright 2015 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: AMD
  23  *
  24  */
  25 #include "dm_services.h"
  26 #include "dc.h"
  27 #include "dc_bios_types.h"
  28 #include "core_types.h"
  29 #include "core_status.h"
  30 #include "resource.h"
  31 #include "dm_helpers.h"
  32 #include "dce110_hw_sequencer.h"
  33 #include "dce110_timing_generator.h"
  34 #include "dce/dce_hwseq.h"
  35 #include "gpio_service_interface.h"
  36
  37 #if defined(CONFIG_DRM_AMD_DC_FBC)
  38 #include "dce110_compressor.h"
  39 #endif
  40
  41 #include "bios/bios_parser_helper.h"
  42 #include "timing_generator.h"
  43 #include "mem_input.h"
  44 #include "opp.h"
  45 #include "ipp.h"
  46 #include "transform.h"
  47 #include "stream_encoder.h"
  48 #include "link_encoder.h"
  49 #include "link_hwss.h"
  50 #include "clock_source.h"
  51 #include "abm.h"
  52 #include "audio.h"
  53 #include "reg_helper.h"
  54
  55 /* include DCE11 register header files */
  56 #include "dce/dce_11_0_d.h"
  57 #include "dce/dce_11_0_sh_mask.h"
  58 #include "custom_float.h"
  59
  60 #include "atomfirmware.h"
  61
  62 /*
  63  * All values are in milliseconds;
  64  * For eDP, after power-up/power/down,
  65  * 300/500 msec max. delay from LCDVCC to black video generation
  66  */
  67 #define PANEL_POWER_UP_TIMEOUT 300
  68 #define PANEL_POWER_DOWN_TIMEOUT 500
  69 #define HPD_CHECK_INTERVAL 10
  70
  71 #define CTX \
  72         hws->ctx
  73 #define DC_LOGGER \
  74         ctx->logger
  75 #define REG(reg)\
  76         hws->regs->reg
  77
  78 #undef FN
  79 #define FN(reg_name, field_name) \
  80         hws->shifts->field_name, hws->masks->field_name
  81
  82 struct dce110_hw_seq_reg_offsets {
  83         uint32_t crtc;
  84 };
  85
  86 static const struct dce110_hw_seq_reg_offsets reg_offsets[] = {
  87 {
  88         .crtc = (mmCRTC0_CRTC_GSL_CONTROL - mmCRTC_GSL_CONTROL),
  89 },
  90 {
  91         .crtc = (mmCRTC1_CRTC_GSL_CONTROL - mmCRTC_GSL_CONTROL),
  92 },
  93 {
  94         .crtc = (mmCRTC2_CRTC_GSL_CONTROL - mmCRTC_GSL_CONTROL),
  95 },
  96 {
  97         .crtc = (mmCRTCV_GSL_CONTROL - mmCRTC_GSL_CONTROL),
  98 }
  99 };
 100
 101 #define HW_REG_BLND(reg, id)\
 102         (reg + reg_offsets[id].blnd)
 103
 104 #define HW_REG_CRTC(reg, id)\
 105         (reg + reg_offsets[id].crtc)
 106
 107 #define MAX_WATERMARK 0xFFFF
 108 #define SAFE_NBP_MARK 0x7FFF
 109
 110 /*******************************************************************************
 111  * Private definitions
 112  ******************************************************************************/
 113 /***************************PIPE_CONTROL***********************************/
 114 static void dce110_init_pte(struct dc_context *ctx)
 115 {
 116         uint32_t addr;
 117         uint32_t value = 0;
 118         uint32_t chunk_int = 0;
 119         uint32_t chunk_mul = 0;
 120
 121         addr = mmUNP_DVMM_PTE_CONTROL;
 122         value = dm_read_reg(ctx, addr);
 123
 124         set_reg_field_value(
 125                 value,
 126                 0,
 127                 DVMM_PTE_CONTROL,
 128                 DVMM_USE_SINGLE_PTE);
 129
 130         set_reg_field_value(
 131                 value,
 132                 1,
 133                 DVMM_PTE_CONTROL,
 134                 DVMM_PTE_BUFFER_MODE0);
 135
 136         set_reg_field_value(
 137                 value,
 138                 1,
 139                 DVMM_PTE_CONTROL,
 140                 DVMM_PTE_BUFFER_MODE1);
 141
 142         dm_write_reg(ctx, addr, value);
 143
 144         addr = mmDVMM_PTE_REQ;
 145         value = dm_read_reg(ctx, addr);
 146
 147         chunk_int = get_reg_field_value(
 148                 value,
 149                 DVMM_PTE_REQ,
 150                 HFLIP_PTEREQ_PER_CHUNK_INT);
 151
 152         chunk_mul = get_reg_field_value(
 153                 value,
 154                 DVMM_PTE_REQ,
 155                 HFLIP_PTEREQ_PER_CHUNK_MULTIPLIER);
 156
 157         if (chunk_int != 0x4 || chunk_mul != 0x4) {
 158
 159                 set_reg_field_value(
 160                         value,
 161                         255,
 162                         DVMM_PTE_REQ,
 163                         MAX_PTEREQ_TO_ISSUE);
 164
 165                 set_reg_field_value(
 166                         value,
 167                         4,
 168                         DVMM_PTE_REQ,
 169                         HFLIP_PTEREQ_PER_CHUNK_INT);
 170
 171                 set_reg_field_value(
 172                         value,
 173                         4,
 174                         DVMM_PTE_REQ,
 175                         HFLIP_PTEREQ_PER_CHUNK_MULTIPLIER);
 176
 177                 dm_write_reg(ctx, addr, value);
 178         }
 179 }
 180 /**************************************************************************/
 181
 182 static void enable_display_pipe_clock_gating(
 183         struct dc_context *ctx,
 184         bool clock_gating)
 185 {
 186         /*TODO*/
 187 }
 188
 189 static bool dce110_enable_display_power_gating(
 190         struct dc *dc,
 191         uint8_t controller_id,
 192         struct dc_bios *dcb,
 193         enum pipe_gating_control power_gating)
 194 {
 195         enum bp_result bp_result = BP_RESULT_OK;
 196         enum bp_pipe_control_action cntl;
 197         struct dc_context *ctx = dc->ctx;
 198         unsigned int underlay_idx = dc->res_pool->underlay_pipe_index;
 199
 200         if (IS_FPGA_MAXIMUS_DC(ctx->dce_environment))
 201                 return true;
 202
 203         if (power_gating == PIPE_GATING_CONTROL_INIT)
 204                 cntl = ASIC_PIPE_INIT;
 205         else if (power_gating == PIPE_GATING_CONTROL_ENABLE)
 206                 cntl = ASIC_PIPE_ENABLE;
 207         else
 208                 cntl = ASIC_PIPE_DISABLE;
 209
 210         if (controller_id == underlay_idx)
 211                 controller_id = CONTROLLER_ID_UNDERLAY0 - 1;
 212
 213         if (power_gating != PIPE_GATING_CONTROL_INIT || controller_id == 0){
 214
 215                 bp_result = dcb->funcs->enable_disp_power_gating(
 216                                                 dcb, controller_id + 1, cntl);
 217
 218                 /* Revert MASTER_UPDATE_MODE to 0 because bios sets it 2
 219                  * by default when command table is called
 220                  *
 221                  * Bios parser accepts controller_id = 6 as indicative of
 222                  * underlay pipe in dce110. But we do not support more
 223                  * than 3.
 224                  */
 225                 if (controller_id < CONTROLLER_ID_MAX - 1)
 226                         dm_write_reg(ctx,
 227                                 HW_REG_CRTC(mmCRTC_MASTER_UPDATE_MODE, controller_id),
 228                                 0);
 229         }
 230
 231         if (power_gating != PIPE_GATING_CONTROL_ENABLE)
 232                 dce110_init_pte(ctx);
 233
 234         if (bp_result == BP_RESULT_OK)
 235                 return true;
 236         else
 237                 return false;
 238 }
 239
 240 static void build_prescale_params(struct ipp_prescale_params *prescale_params,
 241                 const struct dc_plane_state *plane_state)
 242 {
 243         prescale_params->mode = IPP_PRESCALE_MODE_FIXED_UNSIGNED;
 244
 245         switch (plane_state->format) {
 246         case SURFACE_PIXEL_FORMAT_GRPH_ARGB8888:
 247         case SURFACE_PIXEL_FORMAT_GRPH_ABGR8888:
 248                 prescale_params->scale = 0x2020;
 249                 break;
 250         case SURFACE_PIXEL_FORMAT_GRPH_ARGB2101010:
 251         case SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010:
 252                 prescale_params->scale = 0x2008;
 253                 break;
 254         case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616:
 255         case SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616F:
 256                 prescale_params->scale = 0x2000;
 257                 break;
 258         default:
 259                 ASSERT(false);
 260                 break;
 261         }
 262 }
 263
 264 static bool
 265 dce110_set_input_transfer_func(struct pipe_ctx *pipe_ctx,
 266                                const struct dc_plane_state *plane_state)
 267 {
 268         struct input_pixel_processor *ipp = pipe_ctx->plane_res.ipp;
 269         const struct dc_transfer_func *tf = NULL;
 270         struct ipp_prescale_params prescale_params = { 0 };
 271         bool result = true;
 272
 273         if (ipp == NULL)
 274                 return false;
 275
 276         if (plane_state->in_transfer_func)
 277                 tf = plane_state->in_transfer_func;
 278
 279         build_prescale_params(&prescale_params, plane_state);
 280         ipp->funcs->ipp_program_prescale(ipp, &prescale_params);
 281
 282         if (plane_state->gamma_correction && dce_use_lut(plane_state->format))
 283                 ipp->funcs->ipp_program_input_lut(ipp, plane_state->gamma_correction);
 284
 285         if (tf == NULL) {
 286                 /* Default case if no input transfer function specified */
 287                 ipp->funcs->ipp_set_degamma(ipp, IPP_DEGAMMA_MODE_HW_sRGB);
 288         } else if (tf->type == TF_TYPE_PREDEFINED) {
 289                 switch (tf->tf) {
 290                 case TRANSFER_FUNCTION_SRGB:
 291                         ipp->funcs->ipp_set_degamma(ipp, IPP_DEGAMMA_MODE_HW_sRGB);
 292                         break;
 293                 case TRANSFER_FUNCTION_BT709:
 294                         ipp->funcs->ipp_set_degamma(ipp, IPP_DEGAMMA_MODE_HW_xvYCC);
 295                         break;
 296                 case TRANSFER_FUNCTION_LINEAR:
 297                         ipp->funcs->ipp_set_degamma(ipp, IPP_DEGAMMA_MODE_BYPASS);
 298                         break;
 299                 case TRANSFER_FUNCTION_PQ:
 300                 default:
 301                         result = false;
 302                         break;
 303                 }
 304         } else if (tf->type == TF_TYPE_BYPASS) {
 305                 ipp->funcs->ipp_set_degamma(ipp, IPP_DEGAMMA_MODE_BYPASS);
 306         } else {
 307                 /*TF_TYPE_DISTRIBUTED_POINTS - Not supported in DCE 11*/
 308                 result = false;
 309         }
 310
 311         return result;
 312 }
 313
 314 static bool convert_to_custom_float(struct pwl_result_data *rgb_resulted,
 315                                     struct curve_points *arr_points,
 316                                     uint32_t hw_points_num)
 317 {
 318         struct custom_float_format fmt;
 319
 320         struct pwl_result_data *rgb = rgb_resulted;
 321
 322         uint32_t i = 0;
 323
 324         fmt.exponenta_bits = 6;
 325         fmt.mantissa_bits = 12;
 326         fmt.sign = true;
 327
 328         if (!convert_to_custom_float_format(arr_points[0].x, &fmt,
 329                                             &arr_points[0].custom_float_x)) {
 330                 BREAK_TO_DEBUGGER();
 331                 return false;
 332         }
 333
 334         if (!convert_to_custom_float_format(arr_points[0].offset, &fmt,
 335                                             &arr_points[0].custom_float_offset)) {
 336                 BREAK_TO_DEBUGGER();
 337                 return false;
 338         }
 339
 340         if (!convert_to_custom_float_format(arr_points[0].slope, &fmt,
 341                                             &arr_points[0].custom_float_slope)) {
 342                 BREAK_TO_DEBUGGER();
 343                 return false;
 344         }
 345
 346         fmt.mantissa_bits = 10;
 347         fmt.sign = false;
 348
 349         if (!convert_to_custom_float_format(arr_points[1].x, &fmt,
 350                                             &arr_points[1].custom_float_x)) {
 351                 BREAK_TO_DEBUGGER();
 352                 return false;
 353         }
 354
 355         if (!convert_to_custom_float_format(arr_points[1].y, &fmt,
 356                                             &arr_points[1].custom_float_y)) {
 357                 BREAK_TO_DEBUGGER();
 358                 return false;
 359         }
 360
 361         if (!convert_to_custom_float_format(arr_points[1].slope, &fmt,
 362                                             &arr_points[1].custom_float_slope)) {
 363                 BREAK_TO_DEBUGGER();
 364                 return false;
 365         }
 366
 367         fmt.mantissa_bits = 12;
 368         fmt.sign = true;
 369
 370         while (i != hw_points_num) {
 371                 if (!convert_to_custom_float_format(rgb->red, &fmt,
 372                                                     &rgb->red_reg)) {
 373                         BREAK_TO_DEBUGGER();
 374                         return false;
 375                 }
 376
 377                 if (!convert_to_custom_float_format(rgb->green, &fmt,
 378                                                     &rgb->green_reg)) {
 379                         BREAK_TO_DEBUGGER();
 380                         return false;
 381                 }
 382
 383                 if (!convert_to_custom_float_format(rgb->blue, &fmt,
 384                                                     &rgb->blue_reg)) {
 385                         BREAK_TO_DEBUGGER();
 386                         return false;
 387                 }
 388
 389                 if (!convert_to_custom_float_format(rgb->delta_red, &fmt,
 390                                                     &rgb->delta_red_reg)) {
 391                         BREAK_TO_DEBUGGER();
 392                         return false;
 393                 }
 394
 395                 if (!convert_to_custom_float_format(rgb->delta_green, &fmt,
 396                                                     &rgb->delta_green_reg)) {
 397                         BREAK_TO_DEBUGGER();
 398                         return false;
 399                 }
 400
 401                 if (!convert_to_custom_float_format(rgb->delta_blue, &fmt,
 402                                                     &rgb->delta_blue_reg)) {
 403                         BREAK_TO_DEBUGGER();
 404                         return false;
 405                 }
 406
 407                 ++rgb;
 408                 ++i;
 409         }
 410
 411         return true;
 412 }
 413
 414 #define MAX_LOW_POINT      25
 415 #define NUMBER_REGIONS     16
 416 #define NUMBER_SW_SEGMENTS 16
 417
 418 static bool
 419 dce110_translate_regamma_to_hw_format(const struct dc_transfer_func *output_tf,
 420                                       struct pwl_params *regamma_params)
 421 {
 422         struct curve_points *arr_points;
 423         struct pwl_result_data *rgb_resulted;
 424         struct pwl_result_data *rgb;
 425         struct pwl_result_data *rgb_plus_1;
 426         struct fixed31_32 y_r;
 427         struct fixed31_32 y_g;
 428         struct fixed31_32 y_b;
 429         struct fixed31_32 y1_min;
 430         struct fixed31_32 y3_max;
 431
 432         int32_t region_start, region_end;
 433         uint32_t i, j, k, seg_distr[NUMBER_REGIONS], increment, start_index, hw_points;
 434
 435         if (output_tf == NULL || regamma_params == NULL || output_tf->type == TF_TYPE_BYPASS)
 436                 return false;
 437
 438         arr_points = regamma_params->arr_points;
 439         rgb_resulted = regamma_params->rgb_resulted;
 440         hw_points = 0;
 441
 442         memset(regamma_params, 0, sizeof(struct pwl_params));
 443
 444         if (output_tf->tf == TRANSFER_FUNCTION_PQ) {
 445                 /* 16 segments
 446                  * segments are from 2^-11 to 2^5
 447                  */
 448                 region_start = -11;
 449                 region_end = region_start + NUMBER_REGIONS;
 450
 451                 for (i = 0; i < NUMBER_REGIONS; i++)
 452                         seg_distr[i] = 4;
 453
 454         } else {
 455                 /* 10 segments
 456                  * segment is from 2^-10 to 2^0
 457                  */
 458                 region_start = -10;
 459                 region_end = 0;
 460
 461                 seg_distr[0] = 4;
 462                 seg_distr[1] = 4;
 463                 seg_distr[2] = 4;
 464                 seg_distr[3] = 4;
 465                 seg_distr[4] = 4;
 466                 seg_distr[5] = 4;
 467                 seg_distr[6] = 4;
 468                 seg_distr[7] = 4;
 469                 seg_distr[8] = 4;
 470                 seg_distr[9] = 4;
 471                 seg_distr[10] = -1;
 472                 seg_distr[11] = -1;
 473                 seg_distr[12] = -1;
 474                 seg_distr[13] = -1;
 475                 seg_distr[14] = -1;
 476                 seg_distr[15] = -1;
 477         }
 478
 479         for (k = 0; k < 16; k++) {
 480                 if (seg_distr[k] != -1)
 481                         hw_points += (1 << seg_distr[k]);
 482         }
 483
 484         j = 0;
 485         for (k = 0; k < (region_end - region_start); k++) {
 486                 increment = NUMBER_SW_SEGMENTS / (1 << seg_distr[k]);
 487                 start_index = (region_start + k + MAX_LOW_POINT) *
 488                                 NUMBER_SW_SEGMENTS;
 489                 for (i = start_index; i < start_index + NUMBER_SW_SEGMENTS;
 490                                 i += increment) {
 491                         if (j == hw_points - 1)
 492                                 break;
 493                         rgb_resulted[j].red = output_tf->tf_pts.red[i];
 494                         rgb_resulted[j].green = output_tf->tf_pts.green[i];
 495                         rgb_resulted[j].blue = output_tf->tf_pts.blue[i];
 496                         j++;
 497                 }
 498         }
 499
 500         /* last point */
 501         start_index = (region_end + MAX_LOW_POINT) * NUMBER_SW_SEGMENTS;
 502         rgb_resulted[hw_points - 1].red = output_tf->tf_pts.red[start_index];
 503         rgb_resulted[hw_points - 1].green = output_tf->tf_pts.green[start_index];
 504         rgb_resulted[hw_points - 1].blue = output_tf->tf_pts.blue[start_index];
 505
 506         arr_points[0].x = dal_fixed31_32_pow(dal_fixed31_32_from_int(2),
 507                                              dal_fixed31_32_from_int(region_start));
 508         arr_points[1].x = dal_fixed31_32_pow(dal_fixed31_32_from_int(2),
 509                                              dal_fixed31_32_from_int(region_end));
 510
 511         y_r = rgb_resulted[0].red;
 512         y_g = rgb_resulted[0].green;
 513         y_b = rgb_resulted[0].blue;
 514
 515         y1_min = dal_fixed31_32_min(y_r, dal_fixed31_32_min(y_g, y_b));
 516
 517         arr_points[0].y = y1_min;
 518         arr_points[0].slope = dal_fixed31_32_div(arr_points[0].y,
 519                                                  arr_points[0].x);
 520
 521         y_r = rgb_resulted[hw_points - 1].red;
 522         y_g = rgb_resulted[hw_points - 1].green;
 523         y_b = rgb_resulted[hw_points - 1].blue;
 524
 525         /* see comment above, m_arrPoints[1].y should be the Y value for the
 526          * region end (m_numOfHwPoints), not last HW point(m_numOfHwPoints - 1)
 527          */
 528         y3_max = dal_fixed31_32_max(y_r, dal_fixed31_32_max(y_g, y_b));
 529
 530         arr_points[1].y = y3_max;
 531
 532         arr_points[1].slope = dal_fixed31_32_zero;
 533
 534         if (output_tf->tf == TRANSFER_FUNCTION_PQ) {
 535                 /* for PQ, we want to have a straight line from last HW X point,
 536                  * and the slope to be such that we hit 1.0 at 10000 nits.
 537                  */
 538                 const struct fixed31_32 end_value = dal_fixed31_32_from_int(125);
 539
 540                 arr_points[1].slope = dal_fixed31_32_div(
 541                                 dal_fixed31_32_sub(dal_fixed31_32_one, arr_points[1].y),
 542                                 dal_fixed31_32_sub(end_value, arr_points[1].x));
 543         }
 544
 545         regamma_params->hw_points_num = hw_points;
 546
 547         i = 1;
 548         for (k = 0; k < 16 && i < 16; k++) {
 549                 if (seg_distr[k] != -1) {
 550                         regamma_params->arr_curve_points[k].segments_num = seg_distr[k];
 551                         regamma_params->arr_curve_points[i].offset =
 552                                         regamma_params->arr_curve_points[k].offset + (1 << seg_distr[k]);
 553                 }
 554                 i++;
 555         }
 556
 557         if (seg_distr[k] != -1)
 558                 regamma_params->arr_curve_points[k].segments_num = seg_distr[k];
 559
 560         rgb = rgb_resulted;
 561         rgb_plus_1 = rgb_resulted + 1;
 562
 563         i = 1;
 564
 565         while (i != hw_points + 1) {
 566                 if (dal_fixed31_32_lt(rgb_plus_1->red, rgb->red))
 567                         rgb_plus_1->red = rgb->red;
 568                 if (dal_fixed31_32_lt(rgb_plus_1->green, rgb->green))
 569                         rgb_plus_1->green = rgb->green;
 570                 if (dal_fixed31_32_lt(rgb_plus_1->blue, rgb->blue))
 571                         rgb_plus_1->blue = rgb->blue;
 572
 573                 rgb->delta_red = dal_fixed31_32_sub(rgb_plus_1->red, rgb->red);
 574                 rgb->delta_green = dal_fixed31_32_sub(rgb_plus_1->green, rgb->green);
 575                 rgb->delta_blue = dal_fixed31_32_sub(rgb_plus_1->blue, rgb->blue);
 576
 577                 ++rgb_plus_1;
 578                 ++rgb;
 579                 ++i;
 580         }
 581
 582         convert_to_custom_float(rgb_resulted, arr_points, hw_points);
 583
 584         return true;
 585 }
 586
 587 static bool
 588 dce110_set_output_transfer_func(struct pipe_ctx *pipe_ctx,
 589                                 const struct dc_stream_state *stream)
 590 {
 591         struct transform *xfm = pipe_ctx->plane_res.xfm;
 592
 593         xfm->funcs->opp_power_on_regamma_lut(xfm, true);
 594         xfm->regamma_params.hw_points_num = GAMMA_HW_POINTS_NUM;
 595
 596         if (stream->out_transfer_func &&
 597             stream->out_transfer_func->type == TF_TYPE_PREDEFINED &&
 598             stream->out_transfer_func->tf == TRANSFER_FUNCTION_SRGB) {
 599                 xfm->funcs->opp_set_regamma_mode(xfm, OPP_REGAMMA_SRGB);
 600         } else if (dce110_translate_regamma_to_hw_format(stream->out_transfer_func,
 601                                                          &xfm->regamma_params)) {
 602                 xfm->funcs->opp_program_regamma_pwl(xfm, &xfm->regamma_params);
 603                 xfm->funcs->opp_set_regamma_mode(xfm, OPP_REGAMMA_USER);
 604         } else {
 605                 xfm->funcs->opp_set_regamma_mode(xfm, OPP_REGAMMA_BYPASS);
 606         }
 607
 608         xfm->funcs->opp_power_on_regamma_lut(xfm, false);
 609
 610         return true;
 611 }
 612
 613 static enum dc_status bios_parser_crtc_source_select(
 614                 struct pipe_ctx *pipe_ctx)
 615 {
 616         struct dc_bios *dcb;
 617         /* call VBIOS table to set CRTC source for the HW
 618          * encoder block
 619          * note: video bios clears all FMT setting here. */
 620         struct bp_crtc_source_select crtc_source_select = {0};
 621         const struct dc_sink *sink = pipe_ctx->stream->sink;
 622
 623         crtc_source_select.engine_id = pipe_ctx->stream_res.stream_enc->id;
 624         crtc_source_select.controller_id = pipe_ctx->stream_res.tg->inst + 1;
 625         /*TODO: Need to un-hardcode color depth, dp_audio and account for
 626          * the case where signal and sink signal is different (translator
 627          * encoder)*/
 628         crtc_source_select.signal = pipe_ctx->stream->signal;
 629         crtc_source_select.enable_dp_audio = false;
 630         crtc_source_select.sink_signal = pipe_ctx->stream->signal;
 631
 632         switch (pipe_ctx->stream->timing.display_color_depth) {
 633         case COLOR_DEPTH_666:
 634                 crtc_source_select.display_output_bit_depth = PANEL_6BIT_COLOR;
 635                 break;
 636         case COLOR_DEPTH_888:
 637                 crtc_source_select.display_output_bit_depth = PANEL_8BIT_COLOR;
 638                 break;
 639         case COLOR_DEPTH_101010:
 640                 crtc_source_select.display_output_bit_depth = PANEL_10BIT_COLOR;
 641                 break;
 642         case COLOR_DEPTH_121212:
 643                 crtc_source_select.display_output_bit_depth = PANEL_12BIT_COLOR;
 644                 break;
 645         default:
 646                 BREAK_TO_DEBUGGER();
 647                 crtc_source_select.display_output_bit_depth = PANEL_8BIT_COLOR;
 648                 break;
 649         }
 650
 651         dcb = sink->ctx->dc_bios;
 652
 653         if (BP_RESULT_OK != dcb->funcs->crtc_source_select(
 654                 dcb,
 655                 &crtc_source_select)) {
 656                 return DC_ERROR_UNEXPECTED;
 657         }
 658
 659         return DC_OK;
 660 }
 661
 662 void dce110_update_info_frame(struct pipe_ctx *pipe_ctx)
 663 {
 664         ASSERT(pipe_ctx->stream);
 665
 666         if (pipe_ctx->stream_res.stream_enc == NULL)
 667                 return;  /* this is not root pipe */
 668
 669         if (dc_is_hdmi_signal(pipe_ctx->stream->signal))
 670                 pipe_ctx->stream_res.stream_enc->funcs->update_hdmi_info_packets(
 671                         pipe_ctx->stream_res.stream_enc,
 672                         &pipe_ctx->stream_res.encoder_info_frame);
 673         else if (dc_is_dp_signal(pipe_ctx->stream->signal))
 674                 pipe_ctx->stream_res.stream_enc->funcs->update_dp_info_packets(
 675                         pipe_ctx->stream_res.stream_enc,
 676                         &pipe_ctx->stream_res.encoder_info_frame);
 677 }
 678
 679 void dce110_enable_stream(struct pipe_ctx *pipe_ctx)
 680 {
 681         enum dc_lane_count lane_count =
 682                 pipe_ctx->stream->sink->link->cur_link_settings.lane_count;
 683
 684         struct dc_crtc_timing *timing = &pipe_ctx->stream->timing;
 685         struct dc_link *link = pipe_ctx->stream->sink->link;
 686
 687         /* 1. update AVI info frame (HDMI, DP)
 688          * we always need to update info frame
 689         */
 690         uint32_t active_total_with_borders;
 691         uint32_t early_control = 0;
 692         struct timing_generator *tg = pipe_ctx->stream_res.tg;
 693
 694         /* TODOFPGA may change to hwss.update_info_frame */
 695         dce110_update_info_frame(pipe_ctx);
 696         /* enable early control to avoid corruption on DP monitor*/
 697         active_total_with_borders =
 698                         timing->h_addressable
 699                                 + timing->h_border_left
 700                                 + timing->h_border_right;
 701
 702         if (lane_count != 0)
 703                 early_control = active_total_with_borders % lane_count;
 704
 705         if (early_control == 0)
 706                 early_control = lane_count;
 707
 708         tg->funcs->set_early_control(tg, early_control);
 709
 710         /* enable audio only within mode set */
 711         if (pipe_ctx->stream_res.audio != NULL) {
 712                 if (dc_is_dp_signal(pipe_ctx->stream->signal))
 713                         pipe_ctx->stream_res.stream_enc->funcs->dp_audio_enable(pipe_ctx->stream_res.stream_enc);
 714         }
 715
 716         /* For MST, there are multiply stream go to only one link.
 717          * connect DIG back_end to front_end while enable_stream and
 718          * disconnect them during disable_stream
 719          * BY this, it is logic clean to separate stream and link */
 720         link->link_enc->funcs->connect_dig_be_to_fe(link->link_enc,
 721                                                     pipe_ctx->stream_res.stream_enc->id, true);
 722
 723 }
 724
 725 /*todo: cloned in stream enc, fix*/
 726 static bool is_panel_backlight_on(struct dce_hwseq *hws)
 727 {
 728         uint32_t value;
 729
 730         REG_GET(LVTMA_PWRSEQ_CNTL, LVTMA_BLON, &value);
 731
 732         return value;
 733 }
 734
 735 static bool is_panel_powered_on(struct dce_hwseq *hws)
 736 {
 737         uint32_t value;
 738
 739         REG_GET(LVTMA_PWRSEQ_STATE, LVTMA_PWRSEQ_TARGET_STATE_R, &value);
 740         return value == 1;
 741 }
 742
 743 static enum bp_result link_transmitter_control(
 744                 struct dc_bios *bios,
 745         struct bp_transmitter_control *cntl)
 746 {
 747         enum bp_result result;
 748
 749         result = bios->funcs->transmitter_control(bios, cntl);
 750
 751         return result;
 752 }
 753
 754 /*
 755  * @brief
 756  * eDP only.
 757  */
 758 void hwss_edp_wait_for_hpd_ready(
 759                 struct dc_link *link,
 760                 bool power_up)
 761 {
 762         struct dc_context *ctx = link->ctx;
 763         struct graphics_object_id connector = link->link_enc->connector;
 764         struct gpio *hpd;
 765         bool edp_hpd_high = false;
 766         uint32_t time_elapsed = 0;
 767         uint32_t timeout = power_up ?
 768                 PANEL_POWER_UP_TIMEOUT : PANEL_POWER_DOWN_TIMEOUT;
 769
 770         if (dal_graphics_object_id_get_connector_id(connector)
 771                         != CONNECTOR_ID_EDP) {
 772                 BREAK_TO_DEBUGGER();
 773                 return;
 774         }
 775
 776         if (!power_up)
 777                 /*
 778                  * From KV, we will not HPD low after turning off VCC -
 779                  * instead, we will check the SW timer in power_up().
 780                  */
 781                 return;
 782
 783         /*
 784          * When we power on/off the eDP panel,
 785          * we need to wait until SENSE bit is high/low.
 786          */
 787
 788         /* obtain HPD */
 789         /* TODO what to do with this? */
 790         hpd = get_hpd_gpio(ctx->dc_bios, connector, ctx->gpio_service);
 791
 792         if (!hpd) {
 793                 BREAK_TO_DEBUGGER();
 794                 return;
 795         }
 796
 797         dal_gpio_open(hpd, GPIO_MODE_INTERRUPT);
 798
 799         /* wait until timeout or panel detected */
 800
 801         do {
 802                 uint32_t detected = 0;
 803
 804                 dal_gpio_get_value(hpd, &detected);
 805
 806                 if (!(detected ^ power_up)) {
 807                         edp_hpd_high = true;
 808                         break;
 809                 }
 810
 811                 msleep(HPD_CHECK_INTERVAL);
 812
 813                 time_elapsed += HPD_CHECK_INTERVAL;
 814         } while (time_elapsed < timeout);
 815
 816         dal_gpio_close(hpd);
 817
 818         dal_gpio_destroy_irq(&hpd);
 819
 820         if (false == edp_hpd_high) {
 821                 DC_LOG_ERROR(
 822                                 "%s: wait timed out!\n", __func__);
 823         }
 824 }
 825
 826 void hwss_edp_power_control(
 827                 struct dc_link *link,
 828                 bool power_up)
 829 {
 830         struct dc_context *ctx = link->ctx;
 831         struct dce_hwseq *hwseq = ctx->dc->hwseq;
 832         struct bp_transmitter_control cntl = { 0 };
 833         enum bp_result bp_result;
 834
 835
 836         if (dal_graphics_object_id_get_connector_id(link->link_enc->connector)
 837                         != CONNECTOR_ID_EDP) {
 838                 BREAK_TO_DEBUGGER();
 839                 return;
 840         }
 841
 842         if (power_up != is_panel_powered_on(hwseq)) {
 843                 /* Send VBIOS command to prompt eDP panel power */
 844
 845                 DC_LOG_HW_RESUME_S3(
 846                                 "%s: Panel Power action: %s\n",
 847                                 __func__, (power_up ? "On":"Off"));
 848
 849                 cntl.action = power_up ?
 850                         TRANSMITTER_CONTROL_POWER_ON :
 851                         TRANSMITTER_CONTROL_POWER_OFF;
 852                 cntl.transmitter = link->link_enc->transmitter;
 853                 cntl.connector_obj_id = link->link_enc->connector;
 854                 cntl.coherent = false;
 855                 cntl.lanes_number = LANE_COUNT_FOUR;
 856                 cntl.hpd_sel = link->link_enc->hpd_source;
 857
 858                 bp_result = link_transmitter_control(ctx->dc_bios, &cntl);
 859
 860                 if (bp_result != BP_RESULT_OK)
 861                         DC_LOG_ERROR(
 862                                         "%s: Panel Power bp_result: %d\n",
 863                                         __func__, bp_result);
 864         } else {
 865                 DC_LOG_HW_RESUME_S3(
 866                                 "%s: Skipping Panel Power action: %s\n",
 867                                 __func__, (power_up ? "On":"Off"));
 868         }
 869 }
 870
 871 /*todo: cloned in stream enc, fix*/
 872 /*
 873  * @brief
 874  * eDP only. Control the backlight of the eDP panel
 875  */
 876 void hwss_edp_backlight_control(
 877                 struct dc_link *link,
 878                 bool enable)
 879 {
 880         struct dc_context *ctx = link->ctx;
 881         struct dce_hwseq *hws = ctx->dc->hwseq;
 882         struct bp_transmitter_control cntl = { 0 };
 883
 884         if (dal_graphics_object_id_get_connector_id(link->link_enc->connector)
 885                 != CONNECTOR_ID_EDP) {
 886                 BREAK_TO_DEBUGGER();
 887                 return;
 888         }
 889
 890         if (enable && is_panel_backlight_on(hws)) {
 891                 DC_LOG_HW_RESUME_S3(
 892                                 "%s: panel already powered up. Do nothing.\n",
 893                                 __func__);
 894                 return;
 895         }
 896
 897         /* Send VBIOS command to control eDP panel backlight */
 898
 899         DC_LOG_HW_RESUME_S3(
 900                         "%s: backlight action: %s\n",
 901                         __func__, (enable ? "On":"Off"));
 902
 903         cntl.action = enable ?
 904                 TRANSMITTER_CONTROL_BACKLIGHT_ON :
 905                 TRANSMITTER_CONTROL_BACKLIGHT_OFF;
 906
 907         /*cntl.engine_id = ctx->engine;*/
 908         cntl.transmitter = link->link_enc->transmitter;
 909         cntl.connector_obj_id = link->link_enc->connector;
 910         /*todo: unhardcode*/
 911         cntl.lanes_number = LANE_COUNT_FOUR;
 912         cntl.hpd_sel = link->link_enc->hpd_source;
 913         cntl.signal = SIGNAL_TYPE_EDP;
 914
 915         /* For eDP, the following delays might need to be considered
 916          * after link training completed:
 917          * idle period - min. accounts for required BS-Idle pattern,
 918          * max. allows for source frame synchronization);
 919          * 50 msec max. delay from valid video data from source
 920          * to video on dislpay or backlight enable.
 921          *
 922          * Disable the delay for now.
 923          * Enable it in the future if necessary.
 924          */
 925         /* dc_service_sleep_in_milliseconds(50); */
 926                 /*edp 1.2*/
 927         if (cntl.action == TRANSMITTER_CONTROL_BACKLIGHT_ON)
 928                 edp_receiver_ready_T7(link);
 929         link_transmitter_control(ctx->dc_bios, &cntl);
 930         /*edp 1.2*/
 931         if (cntl.action == TRANSMITTER_CONTROL_BACKLIGHT_OFF)
 932                 edp_receiver_ready_T9(link);
 933 }
 934
 935 void dce110_disable_stream(struct pipe_ctx *pipe_ctx, int option)
 936 {
 937         struct dc_stream_state *stream = pipe_ctx->stream;
 938         struct dc_link *link = stream->sink->link;
 939         struct dc *dc = pipe_ctx->stream->ctx->dc;
 940
 941         if (dc_is_hdmi_signal(pipe_ctx->stream->signal))
 942                 pipe_ctx->stream_res.stream_enc->funcs->stop_hdmi_info_packets(
 943                         pipe_ctx->stream_res.stream_enc);
 944
 945         if (dc_is_dp_signal(pipe_ctx->stream->signal))
 946                 pipe_ctx->stream_res.stream_enc->funcs->stop_dp_info_packets(
 947                         pipe_ctx->stream_res.stream_enc);
 948
 949         pipe_ctx->stream_res.stream_enc->funcs->audio_mute_control(
 950                         pipe_ctx->stream_res.stream_enc, true);
 951         if (pipe_ctx->stream_res.audio) {
 952                 if (option != KEEP_ACQUIRED_RESOURCE ||
 953                                 !dc->debug.az_endpoint_mute_only) {
 954                         /*only disalbe az_endpoint if power down or free*/
 955                         pipe_ctx->stream_res.audio->funcs->az_disable(pipe_ctx->stream_res.audio);
 956                 }
 957
 958                 if (dc_is_dp_signal(pipe_ctx->stream->signal))
 959                         pipe_ctx->stream_res.stream_enc->funcs->dp_audio_disable(
 960                                         pipe_ctx->stream_res.stream_enc);
 961                 else
 962                         pipe_ctx->stream_res.stream_enc->funcs->hdmi_audio_disable(
 963                                         pipe_ctx->stream_res.stream_enc);
 964                 /*don't free audio if it is from retrain or internal disable stream*/
 965                 if (option == FREE_ACQUIRED_RESOURCE && dc->caps.dynamic_audio == true) {
 966                         /*we have to dynamic arbitrate the audio endpoints*/
 967                         pipe_ctx->stream_res.audio = NULL;
 968                         /*we free the resource, need reset is_audio_acquired*/
 969                         update_audio_usage(&dc->current_state->res_ctx, dc->res_pool, pipe_ctx->stream_res.audio, false);
 970                 }
 971
 972                 /* TODO: notify audio driver for if audio modes list changed
 973                  * add audio mode list change flag */
 974                 /* dal_audio_disable_azalia_audio_jack_presence(stream->audio,
 975                  * stream->stream_engine_id);
 976                  */
 977         }
 978
 979
 980         link->link_enc->funcs->connect_dig_be_to_fe(
 981                         link->link_enc,
 982                         pipe_ctx->stream_res.stream_enc->id,
 983                         false);
 984
 985 }
 986
 987 void dce110_unblank_stream(struct pipe_ctx *pipe_ctx,
 988                 struct dc_link_settings *link_settings)
 989 {
 990         struct encoder_unblank_param params = { { 0 } };
 991         struct dc_stream_state *stream = pipe_ctx->stream;
 992         struct dc_link *link = stream->sink->link;
 993
 994         /* only 3 items below are used by unblank */
 995         params.pixel_clk_khz =
 996                 pipe_ctx->stream->timing.pix_clk_khz;
 997         params.link_settings.link_rate = link_settings->link_rate;
 998
 999         if (dc_is_dp_signal(pipe_ctx->stream->signal))
1000                 pipe_ctx->stream_res.stream_enc->funcs->dp_unblank(pipe_ctx->stream_res.stream_enc, &params);
1001
1002         if (link->local_sink && link->local_sink->sink_signal == SIGNAL_TYPE_EDP)
1003                 link->dc->hwss.edp_backlight_control(link, true);
1004 }
1005 void dce110_blank_stream(struct pipe_ctx *pipe_ctx)
1006 {
1007         struct dc_stream_state *stream = pipe_ctx->stream;
1008         struct dc_link *link = stream->sink->link;
1009
1010         if (link->local_sink && link->local_sink->sink_signal == SIGNAL_TYPE_EDP)
1011                 link->dc->hwss.edp_backlight_control(link, false);
1012
1013         if (dc_is_dp_signal(pipe_ctx->stream->signal))
1014                 pipe_ctx->stream_res.stream_enc->funcs->dp_blank(pipe_ctx->stream_res.stream_enc);
1015 }
1016
1017
1018 void dce110_set_avmute(struct pipe_ctx *pipe_ctx, bool enable)
1019 {
1020         if (pipe_ctx != NULL && pipe_ctx->stream_res.stream_enc != NULL)
1021                 pipe_ctx->stream_res.stream_enc->funcs->set_avmute(pipe_ctx->stream_res.stream_enc, enable);
1022 }
1023
1024 static enum audio_dto_source translate_to_dto_source(enum controller_id crtc_id)
1025 {
1026         switch (crtc_id) {
1027         case CONTROLLER_ID_D0:
1028                 return DTO_SOURCE_ID0;
1029         case CONTROLLER_ID_D1:
1030                 return DTO_SOURCE_ID1;
1031         case CONTROLLER_ID_D2:
1032                 return DTO_SOURCE_ID2;
1033         case CONTROLLER_ID_D3:
1034                 return DTO_SOURCE_ID3;
1035         case CONTROLLER_ID_D4:
1036                 return DTO_SOURCE_ID4;
1037         case CONTROLLER_ID_D5:
1038                 return DTO_SOURCE_ID5;
1039         default:
1040                 return DTO_SOURCE_UNKNOWN;
1041         }
1042 }
1043
1044 static void build_audio_output(
1045         struct dc_state *state,
1046         const struct pipe_ctx *pipe_ctx,
1047         struct audio_output *audio_output)
1048 {
1049         const struct dc_stream_state *stream = pipe_ctx->stream;
1050         audio_output->engine_id = pipe_ctx->stream_res.stream_enc->id;
1051
1052         audio_output->signal = pipe_ctx->stream->signal;
1053
1054         /* audio_crtc_info  */
1055
1056         audio_output->crtc_info.h_total =
1057                 stream->timing.h_total;
1058
1059         /*
1060          * Audio packets are sent during actual CRTC blank physical signal, we
1061          * need to specify actual active signal portion
1062          */
1063         audio_output->crtc_info.h_active =
1064                         stream->timing.h_addressable
1065                         + stream->timing.h_border_left
1066                         + stream->timing.h_border_right;
1067
1068         audio_output->crtc_info.v_active =
1069                         stream->timing.v_addressable
1070                         + stream->timing.v_border_top
1071                         + stream->timing.v_border_bottom;
1072
1073         audio_output->crtc_info.pixel_repetition = 1;
1074
1075         audio_output->crtc_info.interlaced =
1076                         stream->timing.flags.INTERLACE;
1077
1078         audio_output->crtc_info.refresh_rate =
1079                 (stream->timing.pix_clk_khz*1000)/
1080                 (stream->timing.h_total*stream->timing.v_total);
1081
1082         audio_output->crtc_info.color_depth =
1083                 stream->timing.display_color_depth;
1084
1085         audio_output->crtc_info.requested_pixel_clock =
1086                         pipe_ctx->stream_res.pix_clk_params.requested_pix_clk;
1087
1088         audio_output->crtc_info.calculated_pixel_clock =
1089                         pipe_ctx->stream_res.pix_clk_params.requested_pix_clk;
1090
1091 /*for HDMI, audio ACR is with deep color ratio factor*/
1092         if (dc_is_hdmi_signal(pipe_ctx->stream->signal) &&
1093                 audio_output->crtc_info.requested_pixel_clock ==
1094                                 stream->timing.pix_clk_khz) {
1095                 if (pipe_ctx->stream_res.pix_clk_params.pixel_encoding == PIXEL_ENCODING_YCBCR420) {
1096                         audio_output->crtc_info.requested_pixel_clock =
1097                                         audio_output->crtc_info.requested_pixel_clock/2;
1098                         audio_output->crtc_info.calculated_pixel_clock =
1099                                         pipe_ctx->stream_res.pix_clk_params.requested_pix_clk/2;
1100
1101                 }
1102         }
1103
1104         if (pipe_ctx->stream->signal == SIGNAL_TYPE_DISPLAY_PORT ||
1105                         pipe_ctx->stream->signal == SIGNAL_TYPE_DISPLAY_PORT_MST) {
1106                 audio_output->pll_info.dp_dto_source_clock_in_khz =
1107                                 state->dis_clk->funcs->get_dp_ref_clk_frequency(
1108                                                 state->dis_clk);
1109         }
1110
1111         audio_output->pll_info.feed_back_divider =
1112                         pipe_ctx->pll_settings.feedback_divider;
1113
1114         audio_output->pll_info.dto_source =
1115                 translate_to_dto_source(
1116                         pipe_ctx->stream_res.tg->inst + 1);
1117
1118         /* TODO hard code to enable for now. Need get from stream */
1119         audio_output->pll_info.ss_enabled = true;
1120
1121         audio_output->pll_info.ss_percentage =
1122                         pipe_ctx->pll_settings.ss_percentage;
1123 }
1124
1125 static void get_surface_visual_confirm_color(const struct pipe_ctx *pipe_ctx,
1126                 struct tg_color *color)
1127 {
1128         uint32_t color_value = MAX_TG_COLOR_VALUE * (4 - pipe_ctx->pipe_idx) / 4;
1129
1130         switch (pipe_ctx->plane_res.scl_data.format) {
1131         case PIXEL_FORMAT_ARGB8888:
1132                 /* set boarder color to red */
1133                 color->color_r_cr = color_value;
1134                 break;
1135
1136         case PIXEL_FORMAT_ARGB2101010:
1137                 /* set boarder color to blue */
1138                 color->color_b_cb = color_value;
1139                 break;
1140         case PIXEL_FORMAT_420BPP8:
1141                 /* set boarder color to green */
1142                 color->color_g_y = color_value;
1143                 break;
1144         case PIXEL_FORMAT_420BPP10:
1145                 /* set boarder color to yellow */
1146                 color->color_g_y = color_value;
1147                 color->color_r_cr = color_value;
1148                 break;
1149         case PIXEL_FORMAT_FP16:
1150                 /* set boarder color to white */
1151                 color->color_r_cr = color_value;
1152                 color->color_b_cb = color_value;
1153                 color->color_g_y = color_value;
1154                 break;
1155         default:
1156                 break;
1157         }
1158 }
1159
1160 static void program_scaler(const struct dc *dc,
1161                 const struct pipe_ctx *pipe_ctx)
1162 {
1163         struct tg_color color = {0};
1164
1165 #if defined(CONFIG_DRM_AMD_DC_DCN1_0)
1166         /* TOFPGA */
1167         if (pipe_ctx->plane_res.xfm->funcs->transform_set_pixel_storage_depth == NULL)
1168                 return;
1169 #endif
1170
1171         if (dc->debug.surface_visual_confirm)
1172                 get_surface_visual_confirm_color(pipe_ctx, &color);
1173         else
1174                 color_space_to_black_color(dc,
1175                                 pipe_ctx->stream->output_color_space,
1176                                 &color);
1177
1178         pipe_ctx->plane_res.xfm->funcs->transform_set_pixel_storage_depth(
1179                 pipe_ctx->plane_res.xfm,
1180                 pipe_ctx->plane_res.scl_data.lb_params.depth,
1181                 &pipe_ctx->stream->bit_depth_params);
1182
1183         if (pipe_ctx->stream_res.tg->funcs->set_overscan_blank_color)
1184                 pipe_ctx->stream_res.tg->funcs->set_overscan_blank_color(
1185                                 pipe_ctx->stream_res.tg,
1186                                 &color);
1187
1188         pipe_ctx->plane_res.xfm->funcs->transform_set_scaler(pipe_ctx->plane_res.xfm,
1189                 &pipe_ctx->plane_res.scl_data);
1190 }
1191
1192 static enum dc_status dce110_prog_pixclk_crtc_otg(
1193                 struct pipe_ctx *pipe_ctx,
1194                 struct dc_state *context,
1195                 struct dc *dc)
1196 {
1197         struct dc_stream_state *stream = pipe_ctx->stream;
1198         struct pipe_ctx *pipe_ctx_old = &dc->current_state->res_ctx.
1199                         pipe_ctx[pipe_ctx->pipe_idx];
1200         struct tg_color black_color = {0};
1201
1202         if (!pipe_ctx_old->stream) {
1203
1204                 /* program blank color */
1205                 color_space_to_black_color(dc,
1206                                 stream->output_color_space, &black_color);
1207                 pipe_ctx->stream_res.tg->funcs->set_blank_color(
1208                                 pipe_ctx->stream_res.tg,
1209                                 &black_color);
1210
1211                 /*
1212                  * Must blank CRTC after disabling power gating and before any
1213                  * programming, otherwise CRTC will be hung in bad state
1214                  */
1215                 pipe_ctx->stream_res.tg->funcs->set_blank(pipe_ctx->stream_res.tg, true);
1216
1217                 if (false == pipe_ctx->clock_source->funcs->program_pix_clk(
1218                                 pipe_ctx->clock_source,
1219                                 &pipe_ctx->stream_res.pix_clk_params,
1220                                 &pipe_ctx->pll_settings)) {
1221                         BREAK_TO_DEBUGGER();
1222                         return DC_ERROR_UNEXPECTED;
1223                 }
1224
1225                 pipe_ctx->stream_res.tg->funcs->program_timing(
1226                                 pipe_ctx->stream_res.tg,
1227                                 &stream->timing,
1228                                 true);
1229
1230                 pipe_ctx->stream_res.tg->funcs->set_static_screen_control(
1231                                 pipe_ctx->stream_res.tg,
1232                                 0x182);
1233         }
1234
1235         if (!pipe_ctx_old->stream) {
1236                 if (false == pipe_ctx->stream_res.tg->funcs->enable_crtc(
1237                                 pipe_ctx->stream_res.tg)) {
1238                         BREAK_TO_DEBUGGER();
1239                         return DC_ERROR_UNEXPECTED;
1240                 }
1241         }
1242
1243
1244
1245         return DC_OK;
1246 }
1247
1248 static enum dc_status apply_single_controller_ctx_to_hw(
1249                 struct pipe_ctx *pipe_ctx,
1250                 struct dc_state *context,
1251                 struct dc *dc)
1252 {
1253         struct dc_stream_state *stream = pipe_ctx->stream;
1254         struct pipe_ctx *pipe_ctx_old = &dc->current_state->res_ctx.
1255                         pipe_ctx[pipe_ctx->pipe_idx];
1256
1257         /*  */
1258         dc->hwss.prog_pixclk_crtc_otg(pipe_ctx, context, dc);
1259
1260         /* FPGA does not program backend */
1261         if (IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) {
1262                 pipe_ctx->stream_res.opp->funcs->opp_set_dyn_expansion(
1263                 pipe_ctx->stream_res.opp,
1264                 COLOR_SPACE_YCBCR601,
1265                 stream->timing.display_color_depth,
1266                 pipe_ctx->stream->signal);
1267
1268                 pipe_ctx->stream_res.opp->funcs->opp_program_fmt(
1269                         pipe_ctx->stream_res.opp,
1270                         &stream->bit_depth_params,
1271                         &stream->clamping);
1272                 return DC_OK;
1273         }
1274         /* TODO: move to stream encoder */
1275         if (pipe_ctx->stream->signal != SIGNAL_TYPE_VIRTUAL)
1276                 if (DC_OK != bios_parser_crtc_source_select(pipe_ctx)) {
1277                         BREAK_TO_DEBUGGER();
1278                         return DC_ERROR_UNEXPECTED;
1279                 }
1280         pipe_ctx->stream_res.opp->funcs->opp_set_dyn_expansion(
1281                         pipe_ctx->stream_res.opp,
1282                         COLOR_SPACE_YCBCR601,
1283                         stream->timing.display_color_depth,
1284                         pipe_ctx->stream->signal);
1285
1286         if (pipe_ctx->stream->signal != SIGNAL_TYPE_VIRTUAL)
1287                 stream->sink->link->link_enc->funcs->setup(
1288                         stream->sink->link->link_enc,
1289                         pipe_ctx->stream->signal);
1290
1291         if (pipe_ctx->stream->signal != SIGNAL_TYPE_VIRTUAL)
1292                 pipe_ctx->stream_res.stream_enc->funcs->setup_stereo_sync(
1293                 pipe_ctx->stream_res.stream_enc,
1294                 pipe_ctx->stream_res.tg->inst,
1295                 stream->timing.timing_3d_format != TIMING_3D_FORMAT_NONE);
1296
1297
1298         pipe_ctx->stream_res.opp->funcs->opp_program_fmt(
1299                 pipe_ctx->stream_res.opp,
1300                 &stream->bit_depth_params,
1301                 &stream->clamping);
1302
1303         if (dc_is_dp_signal(pipe_ctx->stream->signal))
1304                 pipe_ctx->stream_res.stream_enc->funcs->dp_set_stream_attribute(
1305                         pipe_ctx->stream_res.stream_enc,
1306                         &stream->timing,
1307                         stream->output_color_space);
1308
1309         if (dc_is_hdmi_signal(pipe_ctx->stream->signal))
1310                 pipe_ctx->stream_res.stream_enc->funcs->hdmi_set_stream_attribute(
1311                         pipe_ctx->stream_res.stream_enc,
1312                         &stream->timing,
1313                         stream->phy_pix_clk,
1314                         pipe_ctx->stream_res.audio != NULL);
1315
1316         if (dc_is_dvi_signal(pipe_ctx->stream->signal))
1317                 pipe_ctx->stream_res.stream_enc->funcs->dvi_set_stream_attribute(
1318                         pipe_ctx->stream_res.stream_enc,
1319                         &stream->timing,
1320                         (pipe_ctx->stream->signal == SIGNAL_TYPE_DVI_DUAL_LINK) ?
1321                         true : false);
1322
1323         resource_build_info_frame(pipe_ctx);
1324         dce110_update_info_frame(pipe_ctx);
1325         if (!pipe_ctx_old->stream)
1326                 core_link_enable_stream(context, pipe_ctx);
1327
1328         pipe_ctx->plane_res.scl_data.lb_params.alpha_en = pipe_ctx->bottom_pipe != 0;
1329
1330         pipe_ctx->stream->sink->link->psr_enabled = false;
1331
1332         return DC_OK;
1333 }
1334
1335 /******************************************************************************/
1336
1337 static void power_down_encoders(struct dc *dc)
1338 {
1339         int i;
1340         enum connector_id connector_id;
1341         enum signal_type signal = SIGNAL_TYPE_NONE;
1342
1343         /* do not know BIOS back-front mapping, simply blank all. It will not
1344          * hurt for non-DP
1345          */
1346         for (i = 0; i < dc->res_pool->stream_enc_count; i++) {
1347                 dc->res_pool->stream_enc[i]->funcs->dp_blank(
1348                                         dc->res_pool->stream_enc[i]);
1349         }
1350
1351         for (i = 0; i < dc->link_count; i++) {
1352                 connector_id = dal_graphics_object_id_get_connector_id(dc->links[i]->link_id);
1353                 if ((connector_id == CONNECTOR_ID_DISPLAY_PORT) ||
1354                         (connector_id == CONNECTOR_ID_EDP)) {
1355
1356                         if (!dc->links[i]->wa_flags.dp_keep_receiver_powered)
1357                                 dp_receiver_power_ctrl(dc->links[i], false);
1358                         if (connector_id == CONNECTOR_ID_EDP)
1359                                 signal = SIGNAL_TYPE_EDP;
1360                 }
1361
1362                 dc->links[i]->link_enc->funcs->disable_output(
1363                                 dc->links[i]->link_enc, signal);
1364         }
1365 }
1366
1367 static void power_down_controllers(struct dc *dc)
1368 {
1369         int i;
1370
1371         for (i = 0; i < dc->res_pool->pipe_count; i++) {
1372                 dc->res_pool->timing_generators[i]->funcs->disable_crtc(
1373                                 dc->res_pool->timing_generators[i]);
1374         }
1375 }
1376
1377 static void power_down_clock_sources(struct dc *dc)
1378 {
1379         int i;
1380
1381         if (dc->res_pool->dp_clock_source->funcs->cs_power_down(
1382                 dc->res_pool->dp_clock_source) == false)
1383                 dm_error("Failed to power down pll! (dp clk src)\n");
1384
1385         for (i = 0; i < dc->res_pool->clk_src_count; i++) {
1386                 if (dc->res_pool->clock_sources[i]->funcs->cs_power_down(
1387                                 dc->res_pool->clock_sources[i]) == false)
1388                         dm_error("Failed to power down pll! (clk src index=%d)\n", i);
1389         }
1390 }
1391
1392 static void power_down_all_hw_blocks(struct dc *dc)
1393 {
1394         power_down_encoders(dc);
1395
1396         power_down_controllers(dc);
1397
1398         power_down_clock_sources(dc);
1399
1400 #if defined(CONFIG_DRM_AMD_DC_FBC)
1401         if (dc->fbc_compressor)
1402                 dc->fbc_compressor->funcs->disable_fbc(dc->fbc_compressor);
1403 #endif
1404 }
1405
1406 static void disable_vga_and_power_gate_all_controllers(
1407                 struct dc *dc)
1408 {
1409         int i;
1410         struct timing_generator *tg;
1411         struct dc_context *ctx = dc->ctx;
1412
1413         for (i = 0; i < dc->res_pool->pipe_count; i++) {
1414                 tg = dc->res_pool->timing_generators[i];
1415
1416                 if (tg->funcs->disable_vga)
1417                         tg->funcs->disable_vga(tg);
1418
1419                 /* Enable CLOCK gating for each pipe BEFORE controller
1420                  * powergating. */
1421                 enable_display_pipe_clock_gating(ctx,
1422                                 true);
1423
1424                 dc->current_state->res_ctx.pipe_ctx[i].pipe_idx = i;
1425                 dc->hwss.disable_plane(dc,
1426                         &dc->current_state->res_ctx.pipe_ctx[i]);
1427         }
1428 }
1429
1430 static struct dc_link *get_link_for_edp_not_in_use(
1431                 struct dc *dc,
1432                 struct dc_state *context)
1433 {
1434         int i;
1435         struct dc_link *link = NULL;
1436
1437         /* check if eDP panel is suppose to be set mode, if yes, no need to disable */
1438         for (i = 0; i < context->stream_count; i++) {
1439                 if (context->streams[i]->signal == SIGNAL_TYPE_EDP)
1440                         return NULL;
1441         }
1442
1443         /* check if there is an eDP panel not in use */
1444         for (i = 0; i < dc->link_count; i++) {
1445                 if (dc->links[i]->local_sink &&
1446                         dc->links[i]->local_sink->sink_signal == SIGNAL_TYPE_EDP) {
1447                         link = dc->links[i];
1448                         break;
1449                 }
1450         }
1451
1452         return link;
1453 }
1454
1455 /**
1456  * When ASIC goes from VBIOS/VGA mode to driver/accelerated mode we need:
1457  *  1. Power down all DC HW blocks
1458  *  2. Disable VGA engine on all controllers
1459  *  3. Enable power gating for controller
1460  *  4. Set acc_mode_change bit (VBIOS will clear this bit when going to FSDOS)
1461  */
1462 void dce110_enable_accelerated_mode(struct dc *dc, struct dc_state *context)
1463 {
1464         struct dc_bios *dcb = dc->ctx->dc_bios;
1465
1466         /* vbios already light up eDP, so we can leverage vbios and skip eDP
1467          * programming
1468          */
1469         bool can_eDP_fast_boot_optimize =
1470                         (dcb->funcs->get_vga_enabled_displays(dc->ctx->dc_bios) == ATOM_DISPLAY_LCD1_ACTIVE);
1471
1472         /* if OS doesn't light up eDP and eDP link is available, we want to disable */
1473         struct dc_link *edp_link_to_turnoff = NULL;
1474
1475         if (can_eDP_fast_boot_optimize) {
1476                 edp_link_to_turnoff = get_link_for_edp_not_in_use(dc, context);
1477
1478                 if (!edp_link_to_turnoff)
1479                         dc->apply_edp_fast_boot_optimization = true;
1480         }
1481
1482         if (!dc->apply_edp_fast_boot_optimization) {
1483                 if (edp_link_to_turnoff) {
1484                         /*turn off backlight before DP_blank and encoder powered down*/
1485                         dc->hwss.edp_backlight_control(edp_link_to_turnoff, false);
1486                 }
1487                 /*resume from S3, no vbios posting, no need to power down again*/
1488                 power_down_all_hw_blocks(dc);
1489                 disable_vga_and_power_gate_all_controllers(dc);
1490                 if (edp_link_to_turnoff)
1491                         dc->hwss.edp_power_control(edp_link_to_turnoff, false);
1492         }
1493         bios_set_scratch_acc_mode_change(dc->ctx->dc_bios);
1494 }
1495
1496 static uint32_t compute_pstate_blackout_duration(
1497         struct bw_fixed blackout_duration,
1498         const struct dc_stream_state *stream)
1499 {
1500         uint32_t total_dest_line_time_ns;
1501         uint32_t pstate_blackout_duration_ns;
1502
1503         pstate_blackout_duration_ns = 1000 * blackout_duration.value >> 24;
1504
1505         total_dest_line_time_ns = 1000000UL *
1506                 stream->timing.h_total /
1507                 stream->timing.pix_clk_khz +
1508                 pstate_blackout_duration_ns;
1509
1510         return total_dest_line_time_ns;
1511 }
1512
1513 static void dce110_set_displaymarks(
1514         const struct dc *dc,
1515         struct dc_state *context)
1516 {
1517         uint8_t i, num_pipes;
1518         unsigned int underlay_idx = dc->res_pool->underlay_pipe_index;
1519
1520         for (i = 0, num_pipes = 0; i < MAX_PIPES; i++) {
1521                 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
1522                 uint32_t total_dest_line_time_ns;
1523
1524                 if (pipe_ctx->stream == NULL)
1525                         continue;
1526
1527                 total_dest_line_time_ns = compute_pstate_blackout_duration(
1528                         dc->bw_vbios->blackout_duration, pipe_ctx->stream);
1529                 pipe_ctx->plane_res.mi->funcs->mem_input_program_display_marks(
1530                         pipe_ctx->plane_res.mi,
1531                         context->bw.dce.nbp_state_change_wm_ns[num_pipes],
1532                         context->bw.dce.stutter_exit_wm_ns[num_pipes],
1533                         context->bw.dce.urgent_wm_ns[num_pipes],
1534                         total_dest_line_time_ns);
1535                 if (i == underlay_idx) {
1536                         num_pipes++;
1537                         pipe_ctx->plane_res.mi->funcs->mem_input_program_chroma_display_marks(
1538                                 pipe_ctx->plane_res.mi,
1539                                 context->bw.dce.nbp_state_change_wm_ns[num_pipes],
1540                                 context->bw.dce.stutter_exit_wm_ns[num_pipes],
1541                                 context->bw.dce.urgent_wm_ns[num_pipes],
1542                                 total_dest_line_time_ns);
1543                 }
1544                 num_pipes++;
1545         }
1546 }
1547
1548 static void set_safe_displaymarks(
1549                 struct resource_context *res_ctx,
1550                 const struct resource_pool *pool)
1551 {
1552         int i;
1553         int underlay_idx = pool->underlay_pipe_index;
1554         struct dce_watermarks max_marks = {
1555                 MAX_WATERMARK, MAX_WATERMARK, MAX_WATERMARK, MAX_WATERMARK };
1556         struct dce_watermarks nbp_marks = {
1557                 SAFE_NBP_MARK, SAFE_NBP_MARK, SAFE_NBP_MARK, SAFE_NBP_MARK };
1558
1559         for (i = 0; i < MAX_PIPES; i++) {
1560                 if (res_ctx->pipe_ctx[i].stream == NULL || res_ctx->pipe_ctx[i].plane_res.mi == NULL)
1561                         continue;
1562
1563                 res_ctx->pipe_ctx[i].plane_res.mi->funcs->mem_input_program_display_marks(
1564                                 res_ctx->pipe_ctx[i].plane_res.mi,
1565                                 nbp_marks,
1566                                 max_marks,
1567                                 max_marks,
1568                                 MAX_WATERMARK);
1569
1570                 if (i == underlay_idx)
1571                         res_ctx->pipe_ctx[i].plane_res.mi->funcs->mem_input_program_chroma_display_marks(
1572                                 res_ctx->pipe_ctx[i].plane_res.mi,
1573                                 nbp_marks,
1574                                 max_marks,
1575                                 max_marks,
1576                                 MAX_WATERMARK);
1577
1578         }
1579 }
1580
1581 /*******************************************************************************
1582  * Public functions
1583  ******************************************************************************/
1584
1585 static void set_drr(struct pipe_ctx **pipe_ctx,
1586                 int num_pipes, int vmin, int vmax)
1587 {
1588         int i = 0;
1589         struct drr_params params = {0};
1590
1591         params.vertical_total_max = vmax;
1592         params.vertical_total_min = vmin;
1593
1594         /* TODO: If multiple pipes are to be supported, you need
1595          * some GSL stuff
1596          */
1597
1598         for (i = 0; i < num_pipes; i++) {
1599                 pipe_ctx[i]->stream_res.tg->funcs->set_drr(pipe_ctx[i]->stream_res.tg, &params);
1600         }
1601 }
1602
1603 static void get_position(struct pipe_ctx **pipe_ctx,
1604                 int num_pipes,
1605                 struct crtc_position *position)
1606 {
1607         int i = 0;
1608
1609         /* TODO: handle pipes > 1
1610          */
1611         for (i = 0; i < num_pipes; i++)
1612                 pipe_ctx[i]->stream_res.tg->funcs->get_position(pipe_ctx[i]->stream_res.tg, position);
1613 }
1614
1615 static void set_static_screen_control(struct pipe_ctx **pipe_ctx,
1616                 int num_pipes, const struct dc_static_screen_events *events)
1617 {
1618         unsigned int i;
1619         unsigned int value = 0;
1620
1621         if (events->overlay_update)
1622                 value |= 0x100;
1623         if (events->surface_update)
1624                 value |= 0x80;
1625         if (events->cursor_update)
1626                 value |= 0x2;
1627         if (events->force_trigger)
1628                 value |= 0x1;
1629
1630 #if defined(CONFIG_DRM_AMD_DC_FBC)
1631         value |= 0x84;
1632 #endif
1633
1634         for (i = 0; i < num_pipes; i++)
1635                 pipe_ctx[i]->stream_res.tg->funcs->
1636                         set_static_screen_control(pipe_ctx[i]->stream_res.tg, value);
1637 }
1638
1639 /* unit: in_khz before mode set, get pixel clock from context. ASIC register
1640  * may not be programmed yet.
1641  * TODO: after mode set, pre_mode_set = false,
1642  * may read PLL register to get pixel clock
1643  */
1644 static uint32_t get_max_pixel_clock_for_all_paths(
1645         struct dc *dc,
1646         struct dc_state *context,
1647         bool pre_mode_set)
1648 {
1649         uint32_t max_pix_clk = 0;
1650         int i;
1651
1652         if (!pre_mode_set) {
1653                 /* TODO: read ASIC register to get pixel clock */
1654                 ASSERT(0);
1655         }
1656
1657         for (i = 0; i < MAX_PIPES; i++) {
1658                 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
1659
1660                 if (pipe_ctx->stream == NULL)
1661                         continue;
1662
1663                 /* do not check under lay */
1664                 if (pipe_ctx->top_pipe)
1665                         continue;
1666
1667                 if (pipe_ctx->stream_res.pix_clk_params.requested_pix_clk > max_pix_clk)
1668                         max_pix_clk =
1669                                 pipe_ctx->stream_res.pix_clk_params.requested_pix_clk;
1670         }
1671
1672         if (max_pix_clk == 0)
1673                 ASSERT(0);
1674
1675         return max_pix_clk;
1676 }
1677
1678 /*
1679  * Find clock state based on clock requested. if clock value is 0, simply
1680  * set clock state as requested without finding clock state by clock value
1681  */
1682
1683 static void apply_min_clocks(
1684         struct dc *dc,
1685         struct dc_state *context,
1686         enum dm_pp_clocks_state *clocks_state,
1687         bool pre_mode_set)
1688 {
1689         struct state_dependent_clocks req_clocks = {0};
1690
1691         if (!pre_mode_set) {
1692                 /* set clock_state without verification */
1693                 if (context->dis_clk->funcs->set_min_clocks_state) {
1694                         context->dis_clk->funcs->set_min_clocks_state(
1695                                                 context->dis_clk, *clocks_state);
1696                         return;
1697                 }
1698
1699                 /* TODO: This is incorrect. Figure out how to fix. */
1700                 context->dis_clk->funcs->apply_clock_voltage_request(
1701                                 context->dis_clk,
1702                                 DM_PP_CLOCK_TYPE_DISPLAY_CLK,
1703                                 context->dis_clk->cur_clocks_value.dispclk_in_khz,
1704                                 pre_mode_set,
1705                                 false);
1706
1707                 context->dis_clk->funcs->apply_clock_voltage_request(
1708                                 context->dis_clk,
1709                                 DM_PP_CLOCK_TYPE_PIXELCLK,
1710                                 context->dis_clk->cur_clocks_value.max_pixelclk_in_khz,
1711                                 pre_mode_set,
1712                                 false);
1713
1714                 context->dis_clk->funcs->apply_clock_voltage_request(
1715                                 context->dis_clk,
1716                                 DM_PP_CLOCK_TYPE_DISPLAYPHYCLK,
1717                                 context->dis_clk->cur_clocks_value.max_non_dp_phyclk_in_khz,
1718                                 pre_mode_set,
1719                                 false);
1720                 return;
1721         }
1722
1723         /* get the required state based on state dependent clocks:
1724          * display clock and pixel clock
1725          */
1726         req_clocks.display_clk_khz = context->bw.dce.dispclk_khz;
1727
1728         req_clocks.pixel_clk_khz = get_max_pixel_clock_for_all_paths(
1729                         dc, context, true);
1730
1731         if (context->dis_clk->funcs->get_required_clocks_state) {
1732                 *clocks_state = context->dis_clk->funcs->get_required_clocks_state(
1733                                 context->dis_clk, &req_clocks);
1734                 context->dis_clk->funcs->set_min_clocks_state(
1735                         context->dis_clk, *clocks_state);
1736         } else {
1737                 context->dis_clk->funcs->apply_clock_voltage_request(
1738                                 context->dis_clk,
1739                                 DM_PP_CLOCK_TYPE_DISPLAY_CLK,
1740                                 req_clocks.display_clk_khz,
1741                                 pre_mode_set,
1742                                 false);
1743
1744                 context->dis_clk->funcs->apply_clock_voltage_request(
1745                                 context->dis_clk,
1746                                 DM_PP_CLOCK_TYPE_PIXELCLK,
1747                                 req_clocks.pixel_clk_khz,
1748                                 pre_mode_set,
1749                                 false);
1750
1751                 context->dis_clk->funcs->apply_clock_voltage_request(
1752                                 context->dis_clk,
1753                                 DM_PP_CLOCK_TYPE_DISPLAYPHYCLK,
1754                                 req_clocks.pixel_clk_khz,
1755                                 pre_mode_set,
1756                                 false);
1757         }
1758 }
1759
1760 #if defined(CONFIG_DRM_AMD_DC_FBC)
1761
1762 /*
1763  *  Check if FBC can be enabled
1764  */
1765 static bool should_enable_fbc(struct dc *dc,
1766                               struct dc_state *context,
1767                               uint32_t *pipe_idx)
1768 {
1769         uint32_t i;
1770         struct pipe_ctx *pipe_ctx = NULL;
1771         struct resource_context *res_ctx = &context->res_ctx;
1772
1773
1774         ASSERT(dc->fbc_compressor);
1775
1776         /* FBC memory should be allocated */
1777         if (!dc->ctx->fbc_gpu_addr)
1778                 return false;
1779
1780         /* Only supports single display */
1781         if (context->stream_count != 1)
1782                 return false;
1783
1784         for (i = 0; i < dc->res_pool->pipe_count; i++) {
1785                 if (res_ctx->pipe_ctx[i].stream) {
1786                         pipe_ctx = &res_ctx->pipe_ctx[i];
1787                         *pipe_idx = i;
1788                         break;
1789                 }
1790         }
1791
1792         /* Only supports eDP */
1793         if (pipe_ctx->stream->sink->link->connector_signal != SIGNAL_TYPE_EDP)
1794                 return false;
1795
1796         /* PSR should not be enabled */
1797         if (pipe_ctx->stream->sink->link->psr_enabled)
1798                 return false;
1799
1800         /* Nothing to compress */
1801         if (!pipe_ctx->plane_state)
1802                 return false;
1803
1804         /* Only for non-linear tiling */
1805         if (pipe_ctx->plane_state->tiling_info.gfx8.array_mode == DC_ARRAY_LINEAR_GENERAL)
1806                 return false;
1807
1808         return true;
1809 }
1810
1811 /*
1812  *  Enable FBC
1813  */
1814 static void enable_fbc(struct dc *dc,
1815                        struct dc_state *context)
1816 {
1817         uint32_t pipe_idx = 0;
1818
1819         if (should_enable_fbc(dc, context, &pipe_idx)) {
1820                 /* Program GRPH COMPRESSED ADDRESS and PITCH */
1821                 struct compr_addr_and_pitch_params params = {0, 0, 0};
1822                 struct compressor *compr = dc->fbc_compressor;
1823                 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[pipe_idx];
1824
1825
1826                 params.source_view_width = pipe_ctx->stream->timing.h_addressable;
1827                 params.source_view_height = pipe_ctx->stream->timing.v_addressable;
1828
1829                 compr->compr_surface_address.quad_part = dc->ctx->fbc_gpu_addr;
1830
1831                 compr->funcs->surface_address_and_pitch(compr, &params);
1832                 compr->funcs->set_fbc_invalidation_triggers(compr, 1);
1833
1834                 compr->funcs->enable_fbc(compr, &params);
1835         }
1836 }
1837 #endif
1838
1839 static void dce110_reset_hw_ctx_wrap(
1840                 struct dc *dc,
1841                 struct dc_state *context)
1842 {
1843         int i;
1844
1845         /* Reset old context */
1846         /* look up the targets that have been removed since last commit */
1847         for (i = 0; i < MAX_PIPES; i++) {
1848                 struct pipe_ctx *pipe_ctx_old =
1849                         &dc->current_state->res_ctx.pipe_ctx[i];
1850                 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
1851
1852                 /* Note: We need to disable output if clock sources change,
1853                  * since bios does optimization and doesn't apply if changing
1854                  * PHY when not already disabled.
1855                  */
1856
1857                 /* Skip underlay pipe since it will be handled in commit surface*/
1858                 if (!pipe_ctx_old->stream || pipe_ctx_old->top_pipe)
1859                         continue;
1860
1861                 if (!pipe_ctx->stream ||
1862                                 pipe_need_reprogram(pipe_ctx_old, pipe_ctx)) {
1863                         struct clock_source *old_clk = pipe_ctx_old->clock_source;
1864
1865                         /* Disable if new stream is null. O/w, if stream is
1866                          * disabled already, no need to disable again.
1867                          */
1868                         if (!pipe_ctx->stream || !pipe_ctx->stream->dpms_off)
1869                                 core_link_disable_stream(pipe_ctx_old, FREE_ACQUIRED_RESOURCE);
1870
1871                         pipe_ctx_old->stream_res.tg->funcs->set_blank(pipe_ctx_old->stream_res.tg, true);
1872                         if (!hwss_wait_for_blank_complete(pipe_ctx_old->stream_res.tg)) {
1873                                 dm_error("DC: failed to blank crtc!\n");
1874                                 BREAK_TO_DEBUGGER();
1875                         }
1876                         pipe_ctx_old->stream_res.tg->funcs->disable_crtc(pipe_ctx_old->stream_res.tg);
1877                         pipe_ctx_old->plane_res.mi->funcs->free_mem_input(
1878                                         pipe_ctx_old->plane_res.mi, dc->current_state->stream_count);
1879
1880                         if (old_clk)
1881                                 old_clk->funcs->cs_power_down(old_clk);
1882
1883                         dc->hwss.disable_plane(dc, pipe_ctx_old);
1884
1885                         pipe_ctx_old->stream = NULL;
1886                 }
1887         }
1888 }
1889
1890
1891 enum dc_status dce110_apply_ctx_to_hw(
1892                 struct dc *dc,
1893                 struct dc_state *context)
1894 {
1895         struct dc_bios *dcb = dc->ctx->dc_bios;
1896         enum dc_status status;
1897         int i;
1898         enum dm_pp_clocks_state clocks_state = DM_PP_CLOCKS_STATE_INVALID;
1899
1900         /* Reset old context */
1901         /* look up the targets that have been removed since last commit */
1902         dc->hwss.reset_hw_ctx_wrap(dc, context);
1903
1904         /* Skip applying if no targets */
1905         if (context->stream_count <= 0)
1906                 return DC_OK;
1907
1908         /* Apply new context */
1909         dcb->funcs->set_scratch_critical_state(dcb, true);
1910
1911         /* below is for real asic only */
1912         for (i = 0; i < dc->res_pool->pipe_count; i++) {
1913                 struct pipe_ctx *pipe_ctx_old =
1914                                         &dc->current_state->res_ctx.pipe_ctx[i];
1915                 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
1916
1917                 if (pipe_ctx->stream == NULL || pipe_ctx->top_pipe)
1918                         continue;
1919
1920                 if (pipe_ctx->stream == pipe_ctx_old->stream) {
1921                         if (pipe_ctx_old->clock_source != pipe_ctx->clock_source)
1922                                 dce_crtc_switch_to_clk_src(dc->hwseq,
1923                                                 pipe_ctx->clock_source, i);
1924                         continue;
1925                 }
1926
1927                 dc->hwss.enable_display_power_gating(
1928                                 dc, i, dc->ctx->dc_bios,
1929                                 PIPE_GATING_CONTROL_DISABLE);
1930         }
1931
1932         set_safe_displaymarks(&context->res_ctx, dc->res_pool);
1933
1934 #if defined(CONFIG_DRM_AMD_DC_FBC)
1935         if (dc->fbc_compressor)
1936                 dc->fbc_compressor->funcs->disable_fbc(dc->fbc_compressor);
1937 #endif
1938         /*TODO: when pplib works*/
1939         apply_min_clocks(dc, context, &clocks_state, true);
1940
1941 #if defined(CONFIG_DRM_AMD_DC_DCN1_0)
1942         if (dc->ctx->dce_version >= DCN_VERSION_1_0) {
1943                 if (context->bw.dcn.calc_clk.fclk_khz
1944                                 > dc->current_state->bw.dcn.cur_clk.fclk_khz) {
1945                         struct dm_pp_clock_for_voltage_req clock;
1946
1947                         clock.clk_type = DM_PP_CLOCK_TYPE_FCLK;
1948                         clock.clocks_in_khz = context->bw.dcn.calc_clk.fclk_khz;
1949                         dm_pp_apply_clock_for_voltage_request(dc->ctx, &clock);
1950                         dc->current_state->bw.dcn.cur_clk.fclk_khz = clock.clocks_in_khz;
1951                         context->bw.dcn.cur_clk.fclk_khz = clock.clocks_in_khz;
1952                 }
1953                 if (context->bw.dcn.calc_clk.dcfclk_khz
1954                                 > dc->current_state->bw.dcn.cur_clk.dcfclk_khz) {
1955                         struct dm_pp_clock_for_voltage_req clock;
1956
1957                         clock.clk_type = DM_PP_CLOCK_TYPE_DCFCLK;
1958                         clock.clocks_in_khz = context->bw.dcn.calc_clk.dcfclk_khz;
1959                         dm_pp_apply_clock_for_voltage_request(dc->ctx, &clock);
1960                         dc->current_state->bw.dcn.cur_clk.dcfclk_khz = clock.clocks_in_khz;
1961                         context->bw.dcn.cur_clk.dcfclk_khz = clock.clocks_in_khz;
1962                 }
1963                 if (context->bw.dcn.calc_clk.dispclk_khz
1964                                 > dc->current_state->bw.dcn.cur_clk.dispclk_khz) {
1965                         dc->res_pool->display_clock->funcs->set_clock(
1966                                         dc->res_pool->display_clock,
1967                                         context->bw.dcn.calc_clk.dispclk_khz);
1968                         dc->current_state->bw.dcn.cur_clk.dispclk_khz =
1969                                         context->bw.dcn.calc_clk.dispclk_khz;
1970                         context->bw.dcn.cur_clk.dispclk_khz =
1971                                         context->bw.dcn.calc_clk.dispclk_khz;
1972                 }
1973         } else
1974 #endif
1975         if (context->bw.dce.dispclk_khz
1976                         > dc->current_state->bw.dce.dispclk_khz) {
1977                 dc->res_pool->display_clock->funcs->set_clock(
1978                                 dc->res_pool->display_clock,
1979                                 context->bw.dce.dispclk_khz * 115 / 100);
1980         }
1981         /* program audio wall clock. use HDMI as clock source if HDMI
1982          * audio active. Otherwise, use DP as clock source
1983          * first, loop to find any HDMI audio, if not, loop find DP audio
1984          */
1985         /* Setup audio rate clock source */
1986         /* Issue:
1987         * Audio lag happened on DP monitor when unplug a HDMI monitor
1988         *
1989         * Cause:
1990         * In case of DP and HDMI connected or HDMI only, DCCG_AUDIO_DTO_SEL
1991         * is set to either dto0 or dto1, audio should work fine.
1992         * In case of DP connected only, DCCG_AUDIO_DTO_SEL should be dto1,
1993         * set to dto0 will cause audio lag.
1994         *
1995         * Solution:
1996         * Not optimized audio wall dto setup. When mode set, iterate pipe_ctx,
1997         * find first available pipe with audio, setup audio wall DTO per topology
1998         * instead of per pipe.
1999         */
2000         for (i = 0; i < dc->res_pool->pipe_count; i++) {
2001                 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
2002
2003                 if (pipe_ctx->stream == NULL)
2004                         continue;
2005
2006                 if (pipe_ctx->top_pipe)
2007                         continue;
2008
2009                 if (pipe_ctx->stream->signal != SIGNAL_TYPE_HDMI_TYPE_A)
2010                         continue;
2011
2012                 if (pipe_ctx->stream_res.audio != NULL) {
2013                         struct audio_output audio_output;
2014
2015                         build_audio_output(context, pipe_ctx, &audio_output);
2016
2017                         pipe_ctx->stream_res.audio->funcs->wall_dto_setup(
2018                                 pipe_ctx->stream_res.audio,
2019                                 pipe_ctx->stream->signal,
2020                                 &audio_output.crtc_info,
2021                                 &audio_output.pll_info);
2022                         break;
2023                 }
2024         }
2025
2026         /* no HDMI audio is found, try DP audio */
2027         if (i == dc->res_pool->pipe_count) {
2028                 for (i = 0; i < dc->res_pool->pipe_count; i++) {
2029                         struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
2030
2031                         if (pipe_ctx->stream == NULL)
2032                                 continue;
2033
2034                         if (pipe_ctx->top_pipe)
2035                                 continue;
2036
2037                         if (!dc_is_dp_signal(pipe_ctx->stream->signal))
2038                                 continue;
2039
2040                         if (pipe_ctx->stream_res.audio != NULL) {
2041                                 struct audio_output audio_output;
2042
2043                                 build_audio_output(context, pipe_ctx, &audio_output);
2044
2045                                 pipe_ctx->stream_res.audio->funcs->wall_dto_setup(
2046                                         pipe_ctx->stream_res.audio,
2047                                         pipe_ctx->stream->signal,
2048                                         &audio_output.crtc_info,
2049                                         &audio_output.pll_info);
2050                                 break;
2051                         }
2052                 }
2053         }
2054
2055         for (i = 0; i < dc->res_pool->pipe_count; i++) {
2056                 struct pipe_ctx *pipe_ctx_old =
2057                                         &dc->current_state->res_ctx.pipe_ctx[i];
2058                 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
2059
2060                 if (pipe_ctx->stream == NULL)
2061                         continue;
2062
2063                 if (pipe_ctx->stream == pipe_ctx_old->stream)
2064                         continue;
2065
2066                 if (pipe_ctx_old->stream && !pipe_need_reprogram(pipe_ctx_old, pipe_ctx))
2067                         continue;
2068
2069                 if (pipe_ctx->top_pipe)
2070                         continue;
2071
2072                 if (context->res_ctx.pipe_ctx[i].stream_res.audio != NULL) {
2073
2074                         struct audio_output audio_output;
2075
2076                         build_audio_output(context, pipe_ctx, &audio_output);
2077
2078                         if (dc_is_dp_signal(pipe_ctx->stream->signal))
2079                                 pipe_ctx->stream_res.stream_enc->funcs->dp_audio_setup(
2080                                                 pipe_ctx->stream_res.stream_enc,
2081                                                 pipe_ctx->stream_res.audio->inst,
2082                                                 &pipe_ctx->stream->audio_info);
2083                         else
2084                                 pipe_ctx->stream_res.stream_enc->funcs->hdmi_audio_setup(
2085                                                 pipe_ctx->stream_res.stream_enc,
2086                                                 pipe_ctx->stream_res.audio->inst,
2087                                                 &pipe_ctx->stream->audio_info,
2088                                                 &audio_output.crtc_info);
2089
2090                         pipe_ctx->stream_res.audio->funcs->az_configure(
2091                                         pipe_ctx->stream_res.audio,
2092                                         pipe_ctx->stream->signal,
2093                                         &audio_output.crtc_info,
2094                                         &pipe_ctx->stream->audio_info);
2095                 }
2096
2097                 status = apply_single_controller_ctx_to_hw(
2098                                 pipe_ctx,
2099                                 context,
2100                                 dc);
2101
2102                 if (DC_OK != status)
2103                         return status;
2104         }
2105
2106         /* pplib is notified if disp_num changed */
2107         dc->hwss.set_bandwidth(dc, context, true);
2108
2109         /* to save power */
2110         apply_min_clocks(dc, context, &clocks_state, false);
2111
2112         dcb->funcs->set_scratch_critical_state(dcb, false);
2113
2114 #if defined(CONFIG_DRM_AMD_DC_FBC)
2115         if (dc->fbc_compressor)
2116                 enable_fbc(dc, context);
2117
2118 #endif
2119
2120         return DC_OK;
2121 }
2122
2123 /*******************************************************************************
2124  * Front End programming
2125  ******************************************************************************/
2126 static void set_default_colors(struct pipe_ctx *pipe_ctx)
2127 {
2128         struct default_adjustment default_adjust = { 0 };
2129
2130         default_adjust.force_hw_default = false;
2131         default_adjust.in_color_space = pipe_ctx->plane_state->color_space;
2132         default_adjust.out_color_space = pipe_ctx->stream->output_color_space;
2133         default_adjust.csc_adjust_type = GRAPHICS_CSC_ADJUST_TYPE_SW;
2134         default_adjust.surface_pixel_format = pipe_ctx->plane_res.scl_data.format;
2135
2136         /* display color depth */
2137         default_adjust.color_depth =
2138                 pipe_ctx->stream->timing.display_color_depth;
2139
2140         /* Lb color depth */
2141         default_adjust.lb_color_depth = pipe_ctx->plane_res.scl_data.lb_params.depth;
2142
2143         pipe_ctx->plane_res.xfm->funcs->opp_set_csc_default(
2144                                         pipe_ctx->plane_res.xfm, &default_adjust);
2145 }
2146
2147
2148 /*******************************************************************************
2149  * In order to turn on/off specific surface we will program
2150  * Blender + CRTC
2151  *
2152  * In case that we have two surfaces and they have a different visibility
2153  * we can't turn off the CRTC since it will turn off the entire display
2154  *
2155  * |----------------------------------------------- |
2156  * |bottom pipe|curr pipe  |              |         |
2157  * |Surface    |Surface    | Blender      |  CRCT   |
2158  * |visibility |visibility | Configuration|         |
2159  * |------------------------------------------------|
2160  * |   off     |    off    | CURRENT_PIPE | blank   |
2161  * |   off     |    on     | CURRENT_PIPE | unblank |
2162  * |   on      |    off    | OTHER_PIPE   | unblank |
2163  * |   on      |    on     | BLENDING     | unblank |
2164  * -------------------------------------------------|
2165  *
2166  ******************************************************************************/
2167 static void program_surface_visibility(const struct dc *dc,
2168                 struct pipe_ctx *pipe_ctx)
2169 {
2170         enum blnd_mode blender_mode = BLND_MODE_CURRENT_PIPE;
2171         bool blank_target = false;
2172
2173         if (pipe_ctx->bottom_pipe) {
2174
2175                 /* For now we are supporting only two pipes */
2176                 ASSERT(pipe_ctx->bottom_pipe->bottom_pipe == NULL);
2177
2178                 if (pipe_ctx->bottom_pipe->plane_state->visible) {
2179                         if (pipe_ctx->plane_state->visible)
2180                                 blender_mode = BLND_MODE_BLENDING;
2181                         else
2182                                 blender_mode = BLND_MODE_OTHER_PIPE;
2183
2184                 } else if (!pipe_ctx->plane_state->visible)
2185                         blank_target = true;
2186
2187         } else if (!pipe_ctx->plane_state->visible)
2188                 blank_target = true;
2189
2190         dce_set_blender_mode(dc->hwseq, pipe_ctx->stream_res.tg->inst, blender_mode);
2191         pipe_ctx->stream_res.tg->funcs->set_blank(pipe_ctx->stream_res.tg, blank_target);
2192
2193 }
2194
2195 static void program_gamut_remap(struct pipe_ctx *pipe_ctx)
2196 {
2197         int i = 0;
2198         struct xfm_grph_csc_adjustment adjust;
2199         memset(&adjust, 0, sizeof(adjust));
2200         adjust.gamut_adjust_type = GRAPHICS_GAMUT_ADJUST_TYPE_BYPASS;
2201
2202
2203         if (pipe_ctx->stream->gamut_remap_matrix.enable_remap == true) {
2204                 adjust.gamut_adjust_type = GRAPHICS_GAMUT_ADJUST_TYPE_SW;
2205
2206                 for (i = 0; i < CSC_TEMPERATURE_MATRIX_SIZE; i++)
2207                         adjust.temperature_matrix[i] =
2208                                 pipe_ctx->stream->gamut_remap_matrix.matrix[i];
2209         }
2210
2211         pipe_ctx->plane_res.xfm->funcs->transform_set_gamut_remap(pipe_ctx->plane_res.xfm, &adjust);
2212 }
2213
2214 /**
2215  * TODO REMOVE, USE UPDATE INSTEAD
2216  */
2217 static void set_plane_config(
2218         const struct dc *dc,
2219         struct pipe_ctx *pipe_ctx,
2220         struct resource_context *res_ctx)
2221 {
2222         struct mem_input *mi = pipe_ctx->plane_res.mi;
2223         struct dc_plane_state *plane_state = pipe_ctx->plane_state;
2224         struct xfm_grph_csc_adjustment adjust;
2225         struct out_csc_color_matrix tbl_entry;
2226         unsigned int i;
2227
2228         memset(&adjust, 0, sizeof(adjust));
2229         memset(&tbl_entry, 0, sizeof(tbl_entry));
2230         adjust.gamut_adjust_type = GRAPHICS_GAMUT_ADJUST_TYPE_BYPASS;
2231
2232         dce_enable_fe_clock(dc->hwseq, mi->inst, true);
2233
2234         set_default_colors(pipe_ctx);
2235         if (pipe_ctx->stream->csc_color_matrix.enable_adjustment == true) {
2236                 tbl_entry.color_space =
2237                         pipe_ctx->stream->output_color_space;
2238
2239                 for (i = 0; i < 12; i++)
2240                         tbl_entry.regval[i] =
2241                         pipe_ctx->stream->csc_color_matrix.matrix[i];
2242
2243                 pipe_ctx->plane_res.xfm->funcs->opp_set_csc_adjustment
2244                                 (pipe_ctx->plane_res.xfm, &tbl_entry);
2245         }
2246
2247         if (pipe_ctx->stream->gamut_remap_matrix.enable_remap == true) {
2248                 adjust.gamut_adjust_type = GRAPHICS_GAMUT_ADJUST_TYPE_SW;
2249
2250                 for (i = 0; i < CSC_TEMPERATURE_MATRIX_SIZE; i++)
2251                         adjust.temperature_matrix[i] =
2252                                 pipe_ctx->stream->gamut_remap_matrix.matrix[i];
2253         }
2254
2255         pipe_ctx->plane_res.xfm->funcs->transform_set_gamut_remap(pipe_ctx->plane_res.xfm, &adjust);
2256
2257         pipe_ctx->plane_res.scl_data.lb_params.alpha_en = pipe_ctx->bottom_pipe != 0;
2258         program_scaler(dc, pipe_ctx);
2259
2260         program_surface_visibility(dc, pipe_ctx);
2261
2262         mi->funcs->mem_input_program_surface_config(
2263                         mi,
2264                         plane_state->format,
2265                         &plane_state->tiling_info,
2266                         &plane_state->plane_size,
2267                         plane_state->rotation,
2268                         NULL,
2269                         false);
2270         if (mi->funcs->set_blank)
2271                 mi->funcs->set_blank(mi, pipe_ctx->plane_state->visible);
2272
2273         if (dc->config.gpu_vm_support)
2274                 mi->funcs->mem_input_program_pte_vm(
2275                                 pipe_ctx->plane_res.mi,
2276                                 plane_state->format,
2277                                 &plane_state->tiling_info,
2278                                 plane_state->rotation);
2279 }
2280
2281 static void update_plane_addr(const struct dc *dc,
2282                 struct pipe_ctx *pipe_ctx)
2283 {
2284         struct dc_plane_state *plane_state = pipe_ctx->plane_state;
2285
2286         if (plane_state == NULL)
2287                 return;
2288
2289         pipe_ctx->plane_res.mi->funcs->mem_input_program_surface_flip_and_addr(
2290                         pipe_ctx->plane_res.mi,
2291                         &plane_state->address,
2292                         plane_state->flip_immediate);
2293
2294         plane_state->status.requested_address = plane_state->address;
2295 }
2296
2297 static void dce110_update_pending_status(struct pipe_ctx *pipe_ctx)
2298 {
2299         struct dc_plane_state *plane_state = pipe_ctx->plane_state;
2300
2301         if (plane_state == NULL)
2302                 return;
2303
2304         plane_state->status.is_flip_pending =
2305                         pipe_ctx->plane_res.mi->funcs->mem_input_is_flip_pending(
2306                                         pipe_ctx->plane_res.mi);
2307
2308         if (plane_state->status.is_flip_pending && !plane_state->visible)
2309                 pipe_ctx->plane_res.mi->current_address = pipe_ctx->plane_res.mi->request_address;
2310
2311         plane_state->status.current_address = pipe_ctx->plane_res.mi->current_address;
2312         if (pipe_ctx->plane_res.mi->current_address.type == PLN_ADDR_TYPE_GRPH_STEREO &&
2313                         pipe_ctx->stream_res.tg->funcs->is_stereo_left_eye) {
2314                 plane_state->status.is_right_eye =\
2315                                 !pipe_ctx->stream_res.tg->funcs->is_stereo_left_eye(pipe_ctx->stream_res.tg);
2316         }
2317 }
2318
2319 void dce110_power_down(struct dc *dc)
2320 {
2321         power_down_all_hw_blocks(dc);
2322         disable_vga_and_power_gate_all_controllers(dc);
2323 }
2324
2325 static bool wait_for_reset_trigger_to_occur(
2326         struct dc_context *dc_ctx,
2327         struct timing_generator *tg)
2328 {
2329         bool rc = false;
2330
2331         /* To avoid endless loop we wait at most
2332          * frames_to_wait_on_triggered_reset frames for the reset to occur. */
2333         const uint32_t frames_to_wait_on_triggered_reset = 10;
2334         uint32_t i;
2335
2336         for (i = 0; i < frames_to_wait_on_triggered_reset; i++) {
2337
2338                 if (!tg->funcs->is_counter_moving(tg)) {
2339                         DC_ERROR("TG counter is not moving!\n");
2340                         break;
2341                 }
2342
2343                 if (tg->funcs->did_triggered_reset_occur(tg)) {
2344                         rc = true;
2345                         /* usually occurs at i=1 */
2346                         DC_SYNC_INFO("GSL: reset occurred at wait count: %d\n",
2347                                         i);
2348                         break;
2349                 }
2350
2351                 /* Wait for one frame. */
2352                 tg->funcs->wait_for_state(tg, CRTC_STATE_VACTIVE);
2353                 tg->funcs->wait_for_state(tg, CRTC_STATE_VBLANK);
2354         }
2355
2356         if (false == rc)
2357                 DC_ERROR("GSL: Timeout on reset trigger!\n");
2358
2359         return rc;
2360 }
2361
2362 /* Enable timing synchronization for a group of Timing Generators. */
2363 static void dce110_enable_timing_synchronization(
2364                 struct dc *dc,
2365                 int group_index,
2366                 int group_size,
2367                 struct pipe_ctx *grouped_pipes[])
2368 {
2369         struct dc_context *dc_ctx = dc->ctx;
2370         struct dcp_gsl_params gsl_params = { 0 };
2371         int i;
2372
2373         DC_SYNC_INFO("GSL: Setting-up...\n");
2374
2375         /* Designate a single TG in the group as a master.
2376          * Since HW doesn't care which one, we always assign
2377          * the 1st one in the group. */
2378         gsl_params.gsl_group = 0;
2379         gsl_params.gsl_master = grouped_pipes[0]->stream_res.tg->inst;
2380
2381         for (i = 0; i < group_size; i++)
2382                 grouped_pipes[i]->stream_res.tg->funcs->setup_global_swap_lock(
2383                                         grouped_pipes[i]->stream_res.tg, &gsl_params);
2384
2385         /* Reset slave controllers on master VSync */
2386         DC_SYNC_INFO("GSL: enabling trigger-reset\n");
2387
2388         for (i = 1 /* skip the master */; i < group_size; i++)
2389                 grouped_pipes[i]->stream_res.tg->funcs->enable_reset_trigger(
2390                                 grouped_pipes[i]->stream_res.tg,
2391                                 gsl_params.gsl_group);
2392
2393         for (i = 1 /* skip the master */; i < group_size; i++) {
2394                 DC_SYNC_INFO("GSL: waiting for reset to occur.\n");
2395                 wait_for_reset_trigger_to_occur(dc_ctx, grouped_pipes[i]->stream_res.tg);
2396                 grouped_pipes[i]->stream_res.tg->funcs->disable_reset_trigger(
2397                                 grouped_pipes[i]->stream_res.tg);
2398         }
2399
2400         /* GSL Vblank synchronization is a one time sync mechanism, assumption
2401          * is that the sync'ed displays will not drift out of sync over time*/
2402         DC_SYNC_INFO("GSL: Restoring register states.\n");
2403         for (i = 0; i < group_size; i++)
2404                 grouped_pipes[i]->stream_res.tg->funcs->tear_down_global_swap_lock(grouped_pipes[i]->stream_res.tg);
2405
2406         DC_SYNC_INFO("GSL: Set-up complete.\n");
2407 }
2408
2409 static void dce110_enable_per_frame_crtc_position_reset(
2410                 struct dc *dc,
2411                 int group_size,
2412                 struct pipe_ctx *grouped_pipes[])
2413 {
2414         struct dc_context *dc_ctx = dc->ctx;
2415         struct dcp_gsl_params gsl_params = { 0 };
2416         int i;
2417
2418         gsl_params.gsl_group = 0;
2419         gsl_params.gsl_master = grouped_pipes[0]->stream->triggered_crtc_reset.event_source->status.primary_otg_inst;
2420
2421         for (i = 0; i < group_size; i++)
2422                 grouped_pipes[i]->stream_res.tg->funcs->setup_global_swap_lock(
2423                                         grouped_pipes[i]->stream_res.tg, &gsl_params);
2424
2425         DC_SYNC_INFO("GSL: enabling trigger-reset\n");
2426
2427         for (i = 1; i < group_size; i++)
2428                 grouped_pipes[i]->stream_res.tg->funcs->enable_crtc_reset(
2429                                 grouped_pipes[i]->stream_res.tg,
2430                                 gsl_params.gsl_master,
2431                                 &grouped_pipes[i]->stream->triggered_crtc_reset);
2432
2433         DC_SYNC_INFO("GSL: waiting for reset to occur.\n");
2434         for (i = 1; i < group_size; i++)
2435                 wait_for_reset_trigger_to_occur(dc_ctx, grouped_pipes[i]->stream_res.tg);
2436
2437         for (i = 0; i < group_size; i++)
2438                 grouped_pipes[i]->stream_res.tg->funcs->tear_down_global_swap_lock(grouped_pipes[i]->stream_res.tg);
2439
2440 }
2441
2442 static void init_hw(struct dc *dc)
2443 {
2444         int i;
2445         struct dc_bios *bp;
2446         struct transform *xfm;
2447         struct abm *abm;
2448
2449         bp = dc->ctx->dc_bios;
2450         for (i = 0; i < dc->res_pool->pipe_count; i++) {
2451                 xfm = dc->res_pool->transforms[i];
2452                 xfm->funcs->transform_reset(xfm);
2453
2454                 dc->hwss.enable_display_power_gating(
2455                                 dc, i, bp,
2456                                 PIPE_GATING_CONTROL_INIT);
2457                 dc->hwss.enable_display_power_gating(
2458                                 dc, i, bp,
2459                                 PIPE_GATING_CONTROL_DISABLE);
2460                 dc->hwss.enable_display_pipe_clock_gating(
2461                         dc->ctx,
2462                         true);
2463         }
2464
2465         dce_clock_gating_power_up(dc->hwseq, false);
2466         /***************************************/
2467
2468         for (i = 0; i < dc->link_count; i++) {
2469                 /****************************************/
2470                 /* Power up AND update implementation according to the
2471                  * required signal (which may be different from the
2472                  * default signal on connector). */
2473                 struct dc_link *link = dc->links[i];
2474
2475                 if (link->link_enc->connector.id == CONNECTOR_ID_EDP)
2476                         dc->hwss.edp_power_control(link, true);
2477
2478                 link->link_enc->funcs->hw_init(link->link_enc);
2479         }
2480
2481         for (i = 0; i < dc->res_pool->pipe_count; i++) {
2482                 struct timing_generator *tg = dc->res_pool->timing_generators[i];
2483
2484                 tg->funcs->disable_vga(tg);
2485
2486                 /* Blank controller using driver code instead of
2487                  * command table. */
2488                 tg->funcs->set_blank(tg, true);
2489                 hwss_wait_for_blank_complete(tg);
2490         }
2491
2492         for (i = 0; i < dc->res_pool->audio_count; i++) {
2493                 struct audio *audio = dc->res_pool->audios[i];
2494                 audio->funcs->hw_init(audio);
2495         }
2496
2497         abm = dc->res_pool->abm;
2498         if (abm != NULL) {
2499                 abm->funcs->init_backlight(abm);
2500                 abm->funcs->abm_init(abm);
2501         }
2502 #if defined(CONFIG_DRM_AMD_DC_FBC)
2503         if (dc->fbc_compressor)
2504                 dc->fbc_compressor->funcs->power_up_fbc(dc->fbc_compressor);
2505 #endif
2506
2507 }
2508
2509 void dce110_fill_display_configs(
2510         const struct dc_state *context,
2511         struct dm_pp_display_configuration *pp_display_cfg)
2512 {
2513         int j;
2514         int num_cfgs = 0;
2515
2516         for (j = 0; j < context->stream_count; j++) {
2517                 int k;
2518
2519                 const struct dc_stream_state *stream = context->streams[j];
2520                 struct dm_pp_single_disp_config *cfg =
2521                         &pp_display_cfg->disp_configs[num_cfgs];
2522                 const struct pipe_ctx *pipe_ctx = NULL;
2523
2524                 for (k = 0; k < MAX_PIPES; k++)
2525                         if (stream == context->res_ctx.pipe_ctx[k].stream) {
2526                                 pipe_ctx = &context->res_ctx.pipe_ctx[k];
2527                                 break;
2528                         }
2529
2530                 ASSERT(pipe_ctx != NULL);
2531
2532                 /* only notify active stream */
2533                 if (stream->dpms_off)
2534                         continue;
2535
2536                 num_cfgs++;
2537                 cfg->signal = pipe_ctx->stream->signal;
2538                 cfg->pipe_idx = pipe_ctx->stream_res.tg->inst;
2539                 cfg->src_height = stream->src.height;
2540                 cfg->src_width = stream->src.width;
2541                 cfg->ddi_channel_mapping =
2542                         stream->sink->link->ddi_channel_mapping.raw;
2543                 cfg->transmitter =
2544                         stream->sink->link->link_enc->transmitter;
2545                 cfg->link_settings.lane_count =
2546                         stream->sink->link->cur_link_settings.lane_count;
2547                 cfg->link_settings.link_rate =
2548                         stream->sink->link->cur_link_settings.link_rate;
2549                 cfg->link_settings.link_spread =
2550                         stream->sink->link->cur_link_settings.link_spread;
2551                 cfg->sym_clock = stream->phy_pix_clk;
2552                 /* Round v_refresh*/
2553                 cfg->v_refresh = stream->timing.pix_clk_khz * 1000;
2554                 cfg->v_refresh /= stream->timing.h_total;
2555                 cfg->v_refresh = (cfg->v_refresh + stream->timing.v_total / 2)
2556                                                         / stream->timing.v_total;
2557         }
2558
2559         pp_display_cfg->display_count = num_cfgs;
2560 }
2561
2562 uint32_t dce110_get_min_vblank_time_us(const struct dc_state *context)
2563 {
2564         uint8_t j;
2565         uint32_t min_vertical_blank_time = -1;
2566
2567         for (j = 0; j < context->stream_count; j++) {
2568                 struct dc_stream_state *stream = context->streams[j];
2569                 uint32_t vertical_blank_in_pixels = 0;
2570                 uint32_t vertical_blank_time = 0;
2571
2572                 vertical_blank_in_pixels = stream->timing.h_total *
2573                         (stream->timing.v_total
2574                          - stream->timing.v_addressable);
2575
2576                 vertical_blank_time = vertical_blank_in_pixels
2577                         * 1000 / stream->timing.pix_clk_khz;
2578
2579                 if (min_vertical_blank_time > vertical_blank_time)
2580                         min_vertical_blank_time = vertical_blank_time;
2581         }
2582
2583         return min_vertical_blank_time;
2584 }
2585
2586 static int determine_sclk_from_bounding_box(
2587                 const struct dc *dc,
2588                 int required_sclk)
2589 {
2590         int i;
2591
2592         /*
2593          * Some asics do not give us sclk levels, so we just report the actual
2594          * required sclk
2595          */
2596         if (dc->sclk_lvls.num_levels == 0)
2597                 return required_sclk;
2598
2599         for (i = 0; i < dc->sclk_lvls.num_levels; i++) {
2600                 if (dc->sclk_lvls.clocks_in_khz[i] >= required_sclk)
2601                         return dc->sclk_lvls.clocks_in_khz[i];
2602         }
2603         /*
2604          * even maximum level could not satisfy requirement, this
2605          * is unexpected at this stage, should have been caught at
2606          * validation time
2607          */
2608         ASSERT(0);
2609         return dc->sclk_lvls.clocks_in_khz[dc->sclk_lvls.num_levels - 1];
2610 }
2611
2612 static void pplib_apply_display_requirements(
2613         struct dc *dc,
2614         struct dc_state *context)
2615 {
2616         struct dm_pp_display_configuration *pp_display_cfg = &context->pp_display_cfg;
2617
2618         pp_display_cfg->all_displays_in_sync =
2619                 context->bw.dce.all_displays_in_sync;
2620         pp_display_cfg->nb_pstate_switch_disable =
2621                         context->bw.dce.nbp_state_change_enable == false;
2622         pp_display_cfg->cpu_cc6_disable =
2623                         context->bw.dce.cpuc_state_change_enable == false;
2624         pp_display_cfg->cpu_pstate_disable =
2625                         context->bw.dce.cpup_state_change_enable == false;
2626         pp_display_cfg->cpu_pstate_separation_time =
2627                         context->bw.dce.blackout_recovery_time_us;
2628
2629         pp_display_cfg->min_memory_clock_khz = context->bw.dce.yclk_khz
2630                 / MEMORY_TYPE_MULTIPLIER;
2631
2632         pp_display_cfg->min_engine_clock_khz = determine_sclk_from_bounding_box(
2633                         dc,
2634                         context->bw.dce.sclk_khz);
2635
2636         pp_display_cfg->min_engine_clock_deep_sleep_khz
2637                         = context->bw.dce.sclk_deep_sleep_khz;
2638
2639         pp_display_cfg->avail_mclk_switch_time_us =
2640                                                 dce110_get_min_vblank_time_us(context);
2641         /* TODO: dce11.2*/
2642         pp_display_cfg->avail_mclk_switch_time_in_disp_active_us = 0;
2643
2644         pp_display_cfg->disp_clk_khz = context->bw.dce.dispclk_khz;
2645
2646         dce110_fill_display_configs(context, pp_display_cfg);
2647
2648         /* TODO: is this still applicable?*/
2649         if (pp_display_cfg->display_count == 1) {
2650                 const struct dc_crtc_timing *timing =
2651                         &context->streams[0]->timing;
2652
2653                 pp_display_cfg->crtc_index =
2654                         pp_display_cfg->disp_configs[0].pipe_idx;
2655                 pp_display_cfg->line_time_in_us = timing->h_total * 1000
2656                                                         / timing->pix_clk_khz;
2657         }
2658
2659         if (memcmp(&dc->prev_display_config, pp_display_cfg, sizeof(
2660                         struct dm_pp_display_configuration)) !=  0)
2661                 dm_pp_apply_display_requirements(dc->ctx, pp_display_cfg);
2662
2663         dc->prev_display_config = *pp_display_cfg;
2664 }
2665
2666 static void dce110_set_bandwidth(
2667                 struct dc *dc,
2668                 struct dc_state *context,
2669                 bool decrease_allowed)
2670 {
2671         dce110_set_displaymarks(dc, context);
2672
2673         if (decrease_allowed || context->bw.dce.dispclk_khz > dc->current_state->bw.dce.dispclk_khz) {
2674                 dc->res_pool->display_clock->funcs->set_clock(
2675                                 dc->res_pool->display_clock,
2676                                 context->bw.dce.dispclk_khz * 115 / 100);
2677                 dc->current_state->bw.dce.dispclk_khz = context->bw.dce.dispclk_khz;
2678         }
2679
2680         pplib_apply_display_requirements(dc, context);
2681 }
2682
2683 static void dce110_program_front_end_for_pipe(
2684                 struct dc *dc, struct pipe_ctx *pipe_ctx)
2685 {
2686         struct mem_input *mi = pipe_ctx->plane_res.mi;
2687         struct pipe_ctx *old_pipe = NULL;
2688         struct dc_plane_state *plane_state = pipe_ctx->plane_state;
2689         struct xfm_grph_csc_adjustment adjust;
2690         struct out_csc_color_matrix tbl_entry;
2691         unsigned int i;
2692         struct dc_context *ctx = dc->ctx;
2693         memset(&tbl_entry, 0, sizeof(tbl_entry));
2694
2695         if (dc->current_state)
2696                 old_pipe = &dc->current_state->res_ctx.pipe_ctx[pipe_ctx->pipe_idx];
2697
2698         memset(&adjust, 0, sizeof(adjust));
2699         adjust.gamut_adjust_type = GRAPHICS_GAMUT_ADJUST_TYPE_BYPASS;
2700
2701         dce_enable_fe_clock(dc->hwseq, mi->inst, true);
2702
2703         set_default_colors(pipe_ctx);
2704         if (pipe_ctx->stream->csc_color_matrix.enable_adjustment
2705                         == true) {
2706                 tbl_entry.color_space =
2707                         pipe_ctx->stream->output_color_space;
2708
2709                 for (i = 0; i < 12; i++)
2710                         tbl_entry.regval[i] =
2711                         pipe_ctx->stream->csc_color_matrix.matrix[i];
2712
2713                 pipe_ctx->plane_res.xfm->funcs->opp_set_csc_adjustment
2714                                 (pipe_ctx->plane_res.xfm, &tbl_entry);
2715         }
2716
2717         if (pipe_ctx->stream->gamut_remap_matrix.enable_remap == true) {
2718                 adjust.gamut_adjust_type = GRAPHICS_GAMUT_ADJUST_TYPE_SW;
2719
2720                 for (i = 0; i < CSC_TEMPERATURE_MATRIX_SIZE; i++)
2721                         adjust.temperature_matrix[i] =
2722                                 pipe_ctx->stream->gamut_remap_matrix.matrix[i];
2723         }
2724
2725         pipe_ctx->plane_res.xfm->funcs->transform_set_gamut_remap(pipe_ctx->plane_res.xfm, &adjust);
2726
2727         pipe_ctx->plane_res.scl_data.lb_params.alpha_en = pipe_ctx->bottom_pipe != 0;
2728
2729         program_scaler(dc, pipe_ctx);
2730
2731 #if defined(CONFIG_DRM_AMD_DC_FBC)
2732         if (dc->fbc_compressor && old_pipe->stream) {
2733                 if (plane_state->tiling_info.gfx8.array_mode == DC_ARRAY_LINEAR_GENERAL)
2734                         dc->fbc_compressor->funcs->disable_fbc(dc->fbc_compressor);
2735                 else
2736                         enable_fbc(dc, dc->current_state);
2737         }
2738 #endif
2739
2740         mi->funcs->mem_input_program_surface_config(
2741                         mi,
2742                         plane_state->format,
2743                         &plane_state->tiling_info,
2744                         &plane_state->plane_size,
2745                         plane_state->rotation,
2746                         NULL,
2747                         false);
2748         if (mi->funcs->set_blank)
2749                 mi->funcs->set_blank(mi, pipe_ctx->plane_state->visible);
2750
2751         if (dc->config.gpu_vm_support)
2752                 mi->funcs->mem_input_program_pte_vm(
2753                                 pipe_ctx->plane_res.mi,
2754                                 plane_state->format,
2755                                 &plane_state->tiling_info,
2756                                 plane_state->rotation);
2757
2758         /* Moved programming gamma from dc to hwss */
2759         if (pipe_ctx->plane_state->update_flags.bits.full_update ||
2760                         pipe_ctx->plane_state->update_flags.bits.in_transfer_func_change ||
2761                         pipe_ctx->plane_state->update_flags.bits.gamma_change)
2762                 dc->hwss.set_input_transfer_func(pipe_ctx, pipe_ctx->plane_state);
2763
2764         if (pipe_ctx->plane_state->update_flags.bits.full_update)
2765                 dc->hwss.set_output_transfer_func(pipe_ctx, pipe_ctx->stream);
2766
2767         DC_LOG_SURFACE(
2768                         "Pipe:%d 0x%x: addr hi:0x%x, "
2769                         "addr low:0x%x, "
2770                         "src: %d, %d, %d,"
2771                         " %d; dst: %d, %d, %d, %d;"
2772                         "clip: %d, %d, %d, %d\n",
2773                         pipe_ctx->pipe_idx,
2774                         pipe_ctx->plane_state,
2775                         pipe_ctx->plane_state->address.grph.addr.high_part,
2776                         pipe_ctx->plane_state->address.grph.addr.low_part,
2777                         pipe_ctx->plane_state->src_rect.x,
2778                         pipe_ctx->plane_state->src_rect.y,
2779                         pipe_ctx->plane_state->src_rect.width,
2780                         pipe_ctx->plane_state->src_rect.height,
2781                         pipe_ctx->plane_state->dst_rect.x,
2782                         pipe_ctx->plane_state->dst_rect.y,
2783                         pipe_ctx->plane_state->dst_rect.width,
2784                         pipe_ctx->plane_state->dst_rect.height,
2785                         pipe_ctx->plane_state->clip_rect.x,
2786                         pipe_ctx->plane_state->clip_rect.y,
2787                         pipe_ctx->plane_state->clip_rect.width,
2788                         pipe_ctx->plane_state->clip_rect.height);
2789
2790         DC_LOG_SURFACE(
2791                         "Pipe %d: width, height, x, y\n"
2792                         "viewport:%d, %d, %d, %d\n"
2793                         "recout:  %d, %d, %d, %d\n",
2794                         pipe_ctx->pipe_idx,
2795                         pipe_ctx->plane_res.scl_data.viewport.width,
2796                         pipe_ctx->plane_res.scl_data.viewport.height,
2797                         pipe_ctx->plane_res.scl_data.viewport.x,
2798                         pipe_ctx->plane_res.scl_data.viewport.y,
2799                         pipe_ctx->plane_res.scl_data.recout.width,
2800                         pipe_ctx->plane_res.scl_data.recout.height,
2801                         pipe_ctx->plane_res.scl_data.recout.x,
2802                         pipe_ctx->plane_res.scl_data.recout.y);
2803 }
2804
2805 static void dce110_apply_ctx_for_surface(
2806                 struct dc *dc,
2807                 const struct dc_stream_state *stream,
2808                 int num_planes,
2809                 struct dc_state *context)
2810 {
2811         int i;
2812
2813         if (num_planes == 0)
2814                 return;
2815
2816         for (i = 0; i < dc->res_pool->pipe_count; i++) {
2817                 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
2818                 struct pipe_ctx *old_pipe_ctx = &dc->current_state->res_ctx.pipe_ctx[i];
2819
2820                 if (stream == pipe_ctx->stream) {
2821                         if (!pipe_ctx->top_pipe &&
2822                                 (pipe_ctx->plane_state || old_pipe_ctx->plane_state))
2823                                 dc->hwss.pipe_control_lock(dc, pipe_ctx, true);
2824                 }
2825         }
2826
2827         for (i = 0; i < dc->res_pool->pipe_count; i++) {
2828                 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
2829
2830                 if (pipe_ctx->stream != stream)
2831                         continue;
2832
2833                 /* Need to allocate mem before program front end for Fiji */
2834                 pipe_ctx->plane_res.mi->funcs->allocate_mem_input(
2835                                 pipe_ctx->plane_res.mi,
2836                                 pipe_ctx->stream->timing.h_total,
2837                                 pipe_ctx->stream->timing.v_total,
2838                                 pipe_ctx->stream->timing.pix_clk_khz,
2839                                 context->stream_count);
2840
2841                 dce110_program_front_end_for_pipe(dc, pipe_ctx);
2842
2843                 dc->hwss.update_plane_addr(dc, pipe_ctx);
2844
2845                 program_surface_visibility(dc, pipe_ctx);
2846
2847         }
2848
2849         for (i = 0; i < dc->res_pool->pipe_count; i++) {
2850                 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
2851                 struct pipe_ctx *old_pipe_ctx = &dc->current_state->res_ctx.pipe_ctx[i];
2852
2853                 if ((stream == pipe_ctx->stream) &&
2854                         (!pipe_ctx->top_pipe) &&
2855                         (pipe_ctx->plane_state || old_pipe_ctx->plane_state))
2856                         dc->hwss.pipe_control_lock(dc, pipe_ctx, false);
2857         }
2858 }
2859
2860 static void dce110_power_down_fe(struct dc *dc, struct pipe_ctx *pipe_ctx)
2861 {
2862         int fe_idx = pipe_ctx->plane_res.mi ?
2863                 pipe_ctx->plane_res.mi->inst : pipe_ctx->pipe_idx;
2864
2865         /* Do not power down fe when stream is active on dce*/
2866         if (dc->current_state->res_ctx.pipe_ctx[fe_idx].stream)
2867                 return;
2868
2869         dc->hwss.enable_display_power_gating(
2870                 dc, fe_idx, dc->ctx->dc_bios, PIPE_GATING_CONTROL_ENABLE);
2871
2872         dc->res_pool->transforms[fe_idx]->funcs->transform_reset(
2873                                 dc->res_pool->transforms[fe_idx]);
2874 }
2875
2876 static void dce110_wait_for_mpcc_disconnect(
2877                 struct dc *dc,
2878                 struct resource_pool *res_pool,
2879                 struct pipe_ctx *pipe_ctx)
2880 {
2881         /* do nothing*/
2882 }
2883
2884 static void program_csc_matrix(struct pipe_ctx *pipe_ctx,
2885                 enum dc_color_space colorspace,
2886                 uint16_t *matrix)
2887 {
2888         int i;
2889         struct out_csc_color_matrix tbl_entry;
2890
2891         if (pipe_ctx->stream->csc_color_matrix.enable_adjustment
2892                                 == true) {
2893                         enum dc_color_space color_space =
2894                                 pipe_ctx->stream->output_color_space;
2895
2896                         //uint16_t matrix[12];
2897                         for (i = 0; i < 12; i++)
2898                                 tbl_entry.regval[i] = pipe_ctx->stream->csc_color_matrix.matrix[i];
2899
2900                         tbl_entry.color_space = color_space;
2901                         //tbl_entry.regval = matrix;
2902                         pipe_ctx->plane_res.xfm->funcs->opp_set_csc_adjustment(pipe_ctx->plane_res.xfm, &tbl_entry);
2903         }
2904 }
2905
2906 void dce110_set_cursor_position(struct pipe_ctx *pipe_ctx)
2907 {
2908         struct dc_cursor_position pos_cpy = pipe_ctx->stream->cursor_position;
2909         struct input_pixel_processor *ipp = pipe_ctx->plane_res.ipp;
2910         struct mem_input *mi = pipe_ctx->plane_res.mi;
2911         struct dc_cursor_mi_param param = {
2912                 .pixel_clk_khz = pipe_ctx->stream->timing.pix_clk_khz,
2913                 .ref_clk_khz = pipe_ctx->stream->ctx->dc->res_pool->ref_clock_inKhz,
2914                 .viewport_x_start = pipe_ctx->plane_res.scl_data.viewport.x,
2915                 .viewport_width = pipe_ctx->plane_res.scl_data.viewport.width,
2916                 .h_scale_ratio = pipe_ctx->plane_res.scl_data.ratios.horz
2917         };
2918
2919         if (pipe_ctx->plane_state->address.type
2920                         == PLN_ADDR_TYPE_VIDEO_PROGRESSIVE)
2921                 pos_cpy.enable = false;
2922
2923         if (pipe_ctx->top_pipe && pipe_ctx->plane_state != pipe_ctx->top_pipe->plane_state)
2924                 pos_cpy.enable = false;
2925
2926         if (ipp->funcs->ipp_cursor_set_position)
2927                 ipp->funcs->ipp_cursor_set_position(ipp, &pos_cpy, &param);
2928         if (mi->funcs->set_cursor_position)
2929                 mi->funcs->set_cursor_position(mi, &pos_cpy, &param);
2930 }
2931
2932 void dce110_set_cursor_attribute(struct pipe_ctx *pipe_ctx)
2933 {
2934         struct dc_cursor_attributes *attributes = &pipe_ctx->stream->cursor_attributes;
2935
2936         if (pipe_ctx->plane_res.ipp->funcs->ipp_cursor_set_attributes)
2937                 pipe_ctx->plane_res.ipp->funcs->ipp_cursor_set_attributes(
2938                                 pipe_ctx->plane_res.ipp, attributes);
2939
2940         if (pipe_ctx->plane_res.mi->funcs->set_cursor_attributes)
2941                 pipe_ctx->plane_res.mi->funcs->set_cursor_attributes(
2942                                 pipe_ctx->plane_res.mi, attributes);
2943
2944         if (pipe_ctx->plane_res.xfm->funcs->set_cursor_attributes)
2945                 pipe_ctx->plane_res.xfm->funcs->set_cursor_attributes(
2946                                 pipe_ctx->plane_res.xfm, attributes);
2947 }
2948
2949 static void ready_shared_resources(struct dc *dc, struct dc_state *context) {}
2950
2951 static void optimize_shared_resources(struct dc *dc) {}
2952
2953 static const struct hw_sequencer_funcs dce110_funcs = {
2954         .program_gamut_remap = program_gamut_remap,
2955         .program_csc_matrix = program_csc_matrix,
2956         .init_hw = init_hw,
2957         .apply_ctx_to_hw = dce110_apply_ctx_to_hw,
2958         .apply_ctx_for_surface = dce110_apply_ctx_for_surface,
2959         .set_plane_config = set_plane_config,
2960         .update_plane_addr = update_plane_addr,
2961         .update_pending_status = dce110_update_pending_status,
2962         .set_input_transfer_func = dce110_set_input_transfer_func,
2963         .set_output_transfer_func = dce110_set_output_transfer_func,
2964         .power_down = dce110_power_down,
2965         .enable_accelerated_mode = dce110_enable_accelerated_mode,
2966         .enable_timing_synchronization = dce110_enable_timing_synchronization,
2967         .enable_per_frame_crtc_position_reset = dce110_enable_per_frame_crtc_position_reset,
2968         .update_info_frame = dce110_update_info_frame,
2969         .enable_stream = dce110_enable_stream,
2970         .disable_stream = dce110_disable_stream,
2971         .unblank_stream = dce110_unblank_stream,
2972         .blank_stream = dce110_blank_stream,
2973         .enable_display_pipe_clock_gating = enable_display_pipe_clock_gating,
2974         .enable_display_power_gating = dce110_enable_display_power_gating,
2975         .disable_plane = dce110_power_down_fe,
2976         .pipe_control_lock = dce_pipe_control_lock,
2977         .set_bandwidth = dce110_set_bandwidth,
2978         .set_drr = set_drr,
2979         .get_position = get_position,
2980         .set_static_screen_control = set_static_screen_control,
2981         .reset_hw_ctx_wrap = dce110_reset_hw_ctx_wrap,
2982         .prog_pixclk_crtc_otg = dce110_prog_pixclk_crtc_otg,
2983         .setup_stereo = NULL,
2984         .set_avmute = dce110_set_avmute,
2985         .wait_for_mpcc_disconnect = dce110_wait_for_mpcc_disconnect,
2986         .ready_shared_resources = ready_shared_resources,
2987         .optimize_shared_resources = optimize_shared_resources,
2988         .pplib_apply_display_requirements = pplib_apply_display_requirements,
2989         .edp_backlight_control = hwss_edp_backlight_control,
2990         .edp_power_control = hwss_edp_power_control,
2991         .edp_wait_for_hpd_ready = hwss_edp_wait_for_hpd_ready,
2992         .set_cursor_position = dce110_set_cursor_position,
2993         .set_cursor_attribute = dce110_set_cursor_attribute
2994 };
2995
2996 void dce110_hw_sequencer_construct(struct dc *dc)
2997 {
2998         dc->hwss = dce110_funcs;
2999 }
3000