drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c

   1 /*
   2 * Copyright 2012-15 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: AMD
  23  *
  24  */
  25
  26 #include "../dce/dce_dccg.h"
  27 #include "dm_services.h"
  28
  29 #include "link_encoder.h"
  30 #include "stream_encoder.h"
  31
  32 #include "resource.h"
  33 #include "include/irq_service_interface.h"
  34 #include "dce110/dce110_resource.h"
  35 #include "dce110/dce110_timing_generator.h"
  36
  37 #include "irq/dce110/irq_service_dce110.h"
  38
  39 #include "dce/dce_mem_input.h"
  40 #include "dce/dce_transform.h"
  41 #include "dce/dce_link_encoder.h"
  42 #include "dce/dce_stream_encoder.h"
  43 #include "dce/dce_audio.h"
  44 #include "dce/dce_opp.h"
  45 #include "dce/dce_ipp.h"
  46 #include "dce/dce_clock_source.h"
  47
  48 #include "dce/dce_hwseq.h"
  49 #include "dce112/dce112_hw_sequencer.h"
  50 #include "dce/dce_abm.h"
  51 #include "dce/dce_dmcu.h"
  52 #include "dce/dce_aux.h"
  53 #include "dce/dce_i2c.h"
  54
  55 #include "reg_helper.h"
  56
  57 #include "dce/dce_11_2_d.h"
  58 #include "dce/dce_11_2_sh_mask.h"
  59
  60 #include "dce100/dce100_resource.h"
  61 #define DC_LOGGER \
  62                 dc->ctx->logger
  63
  64 #ifndef mmDP_DPHY_INTERNAL_CTRL
  65         #define mmDP_DPHY_INTERNAL_CTRL 0x4aa7
  66         #define mmDP0_DP_DPHY_INTERNAL_CTRL 0x4aa7
  67         #define mmDP1_DP_DPHY_INTERNAL_CTRL 0x4ba7
  68         #define mmDP2_DP_DPHY_INTERNAL_CTRL 0x4ca7
  69         #define mmDP3_DP_DPHY_INTERNAL_CTRL 0x4da7
  70         #define mmDP4_DP_DPHY_INTERNAL_CTRL 0x4ea7
  71         #define mmDP5_DP_DPHY_INTERNAL_CTRL 0x4fa7
  72         #define mmDP6_DP_DPHY_INTERNAL_CTRL 0x54a7
  73         #define mmDP7_DP_DPHY_INTERNAL_CTRL 0x56a7
  74         #define mmDP8_DP_DPHY_INTERNAL_CTRL 0x57a7
  75 #endif
  76
  77 #ifndef mmBIOS_SCRATCH_2
  78         #define mmBIOS_SCRATCH_2 0x05CB
  79         #define mmBIOS_SCRATCH_6 0x05CF
  80 #endif
  81
  82 #ifndef mmDP_DPHY_BS_SR_SWAP_CNTL
  83         #define mmDP_DPHY_BS_SR_SWAP_CNTL                       0x4ADC
  84         #define mmDP0_DP_DPHY_BS_SR_SWAP_CNTL                   0x4ADC
  85         #define mmDP1_DP_DPHY_BS_SR_SWAP_CNTL                   0x4BDC
  86         #define mmDP2_DP_DPHY_BS_SR_SWAP_CNTL                   0x4CDC
  87         #define mmDP3_DP_DPHY_BS_SR_SWAP_CNTL                   0x4DDC
  88         #define mmDP4_DP_DPHY_BS_SR_SWAP_CNTL                   0x4EDC
  89         #define mmDP5_DP_DPHY_BS_SR_SWAP_CNTL                   0x4FDC
  90         #define mmDP6_DP_DPHY_BS_SR_SWAP_CNTL                   0x54DC
  91 #endif
  92
  93 #ifndef mmDP_DPHY_FAST_TRAINING
  94         #define mmDP_DPHY_FAST_TRAINING                         0x4ABC
  95         #define mmDP0_DP_DPHY_FAST_TRAINING                     0x4ABC
  96         #define mmDP1_DP_DPHY_FAST_TRAINING                     0x4BBC
  97         #define mmDP2_DP_DPHY_FAST_TRAINING                     0x4CBC
  98         #define mmDP3_DP_DPHY_FAST_TRAINING                     0x4DBC
  99         #define mmDP4_DP_DPHY_FAST_TRAINING                     0x4EBC
 100         #define mmDP5_DP_DPHY_FAST_TRAINING                     0x4FBC
 101         #define mmDP6_DP_DPHY_FAST_TRAINING                     0x54BC
 102 #endif
 103
 104 enum dce112_clk_src_array_id {
 105         DCE112_CLK_SRC_PLL0,
 106         DCE112_CLK_SRC_PLL1,
 107         DCE112_CLK_SRC_PLL2,
 108         DCE112_CLK_SRC_PLL3,
 109         DCE112_CLK_SRC_PLL4,
 110         DCE112_CLK_SRC_PLL5,
 111
 112         DCE112_CLK_SRC_TOTAL
 113 };
 114
 115 static const struct dce110_timing_generator_offsets dce112_tg_offsets[] = {
 116         {
 117                 .crtc = (mmCRTC0_CRTC_CONTROL - mmCRTC_CONTROL),
 118                 .dcp =  (mmDCP0_GRPH_CONTROL - mmGRPH_CONTROL),
 119         },
 120         {
 121                 .crtc = (mmCRTC1_CRTC_CONTROL - mmCRTC_CONTROL),
 122                 .dcp = (mmDCP1_GRPH_CONTROL - mmGRPH_CONTROL),
 123         },
 124         {
 125                 .crtc = (mmCRTC2_CRTC_CONTROL - mmCRTC_CONTROL),
 126                 .dcp = (mmDCP2_GRPH_CONTROL - mmGRPH_CONTROL),
 127         },
 128         {
 129                 .crtc = (mmCRTC3_CRTC_CONTROL - mmCRTC_CONTROL),
 130                 .dcp = (mmDCP3_GRPH_CONTROL - mmGRPH_CONTROL),
 131         },
 132         {
 133                 .crtc = (mmCRTC4_CRTC_CONTROL - mmCRTC_CONTROL),
 134                 .dcp = (mmDCP4_GRPH_CONTROL - mmGRPH_CONTROL),
 135         },
 136         {
 137                 .crtc = (mmCRTC5_CRTC_CONTROL - mmCRTC_CONTROL),
 138                 .dcp = (mmDCP5_GRPH_CONTROL - mmGRPH_CONTROL),
 139         }
 140 };
 141
 142 /* set register offset */
 143 #define SR(reg_name)\
 144         .reg_name = mm ## reg_name
 145
 146 /* set register offset with instance */
 147 #define SRI(reg_name, block, id)\
 148         .reg_name = mm ## block ## id ## _ ## reg_name
 149
 150
 151 static const struct dccg_registers disp_clk_regs = {
 152                 CLK_COMMON_REG_LIST_DCE_BASE()
 153 };
 154
 155 static const struct dccg_shift disp_clk_shift = {
 156                 CLK_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(__SHIFT)
 157 };
 158
 159 static const struct dccg_mask disp_clk_mask = {
 160                 CLK_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(_MASK)
 161 };
 162
 163 static const struct dce_dmcu_registers dmcu_regs = {
 164                 DMCU_DCE110_COMMON_REG_LIST()
 165 };
 166
 167 static const struct dce_dmcu_shift dmcu_shift = {
 168                 DMCU_MASK_SH_LIST_DCE110(__SHIFT)
 169 };
 170
 171 static const struct dce_dmcu_mask dmcu_mask = {
 172                 DMCU_MASK_SH_LIST_DCE110(_MASK)
 173 };
 174
 175 static const struct dce_abm_registers abm_regs = {
 176                 ABM_DCE110_COMMON_REG_LIST()
 177 };
 178
 179 static const struct dce_abm_shift abm_shift = {
 180                 ABM_MASK_SH_LIST_DCE110(__SHIFT)
 181 };
 182
 183 static const struct dce_abm_mask abm_mask = {
 184                 ABM_MASK_SH_LIST_DCE110(_MASK)
 185 };
 186
 187 #define ipp_regs(id)\
 188 [id] = {\
 189                 IPP_DCE110_REG_LIST_DCE_BASE(id)\
 190 }
 191
 192 static const struct dce_ipp_registers ipp_regs[] = {
 193                 ipp_regs(0),
 194                 ipp_regs(1),
 195                 ipp_regs(2),
 196                 ipp_regs(3),
 197                 ipp_regs(4),
 198                 ipp_regs(5)
 199 };
 200
 201 static const struct dce_ipp_shift ipp_shift = {
 202                 IPP_DCE100_MASK_SH_LIST_DCE_COMMON_BASE(__SHIFT)
 203 };
 204
 205 static const struct dce_ipp_mask ipp_mask = {
 206                 IPP_DCE100_MASK_SH_LIST_DCE_COMMON_BASE(_MASK)
 207 };
 208
 209 #define transform_regs(id)\
 210 [id] = {\
 211                 XFM_COMMON_REG_LIST_DCE110(id)\
 212 }
 213
 214 static const struct dce_transform_registers xfm_regs[] = {
 215                 transform_regs(0),
 216                 transform_regs(1),
 217                 transform_regs(2),
 218                 transform_regs(3),
 219                 transform_regs(4),
 220                 transform_regs(5)
 221 };
 222
 223 static const struct dce_transform_shift xfm_shift = {
 224                 XFM_COMMON_MASK_SH_LIST_DCE110(__SHIFT)
 225 };
 226
 227 static const struct dce_transform_mask xfm_mask = {
 228                 XFM_COMMON_MASK_SH_LIST_DCE110(_MASK)
 229 };
 230
 231 #define aux_regs(id)\
 232 [id] = {\
 233         AUX_REG_LIST(id)\
 234 }
 235
 236 static const struct dce110_link_enc_aux_registers link_enc_aux_regs[] = {
 237                 aux_regs(0),
 238                 aux_regs(1),
 239                 aux_regs(2),
 240                 aux_regs(3),
 241                 aux_regs(4),
 242                 aux_regs(5)
 243 };
 244
 245 #define hpd_regs(id)\
 246 [id] = {\
 247         HPD_REG_LIST(id)\
 248 }
 249
 250 static const struct dce110_link_enc_hpd_registers link_enc_hpd_regs[] = {
 251                 hpd_regs(0),
 252                 hpd_regs(1),
 253                 hpd_regs(2),
 254                 hpd_regs(3),
 255                 hpd_regs(4),
 256                 hpd_regs(5)
 257 };
 258
 259 #define link_regs(id)\
 260 [id] = {\
 261         LE_DCE110_REG_LIST(id)\
 262 }
 263
 264 static const struct dce110_link_enc_registers link_enc_regs[] = {
 265         link_regs(0),
 266         link_regs(1),
 267         link_regs(2),
 268         link_regs(3),
 269         link_regs(4),
 270         link_regs(5),
 271         link_regs(6),
 272 };
 273
 274 #define stream_enc_regs(id)\
 275 [id] = {\
 276         SE_COMMON_REG_LIST(id),\
 277         .TMDS_CNTL = 0,\
 278 }
 279
 280 static const struct dce110_stream_enc_registers stream_enc_regs[] = {
 281         stream_enc_regs(0),
 282         stream_enc_regs(1),
 283         stream_enc_regs(2),
 284         stream_enc_regs(3),
 285         stream_enc_regs(4),
 286         stream_enc_regs(5)
 287 };
 288
 289 static const struct dce_stream_encoder_shift se_shift = {
 290                 SE_COMMON_MASK_SH_LIST_DCE112(__SHIFT)
 291 };
 292
 293 static const struct dce_stream_encoder_mask se_mask = {
 294                 SE_COMMON_MASK_SH_LIST_DCE112(_MASK)
 295 };
 296
 297 #define opp_regs(id)\
 298 [id] = {\
 299         OPP_DCE_112_REG_LIST(id),\
 300 }
 301
 302 static const struct dce_opp_registers opp_regs[] = {
 303         opp_regs(0),
 304         opp_regs(1),
 305         opp_regs(2),
 306         opp_regs(3),
 307         opp_regs(4),
 308         opp_regs(5)
 309 };
 310
 311 static const struct dce_opp_shift opp_shift = {
 312         OPP_COMMON_MASK_SH_LIST_DCE_112(__SHIFT)
 313 };
 314
 315 static const struct dce_opp_mask opp_mask = {
 316         OPP_COMMON_MASK_SH_LIST_DCE_112(_MASK)
 317 };
 318
 319 #define aux_engine_regs(id)\
 320 [id] = {\
 321         AUX_COMMON_REG_LIST(id), \
 322         .AUX_RESET_MASK = 0 \
 323 }
 324
 325 static const struct dce110_aux_registers aux_engine_regs[] = {
 326                 aux_engine_regs(0),
 327                 aux_engine_regs(1),
 328                 aux_engine_regs(2),
 329                 aux_engine_regs(3),
 330                 aux_engine_regs(4),
 331                 aux_engine_regs(5)
 332 };
 333
 334 #define audio_regs(id)\
 335 [id] = {\
 336         AUD_COMMON_REG_LIST(id)\
 337 }
 338
 339 static const struct dce_audio_registers audio_regs[] = {
 340         audio_regs(0),
 341         audio_regs(1),
 342         audio_regs(2),
 343         audio_regs(3),
 344         audio_regs(4),
 345         audio_regs(5)
 346 };
 347
 348 static const struct dce_audio_shift audio_shift = {
 349                 AUD_COMMON_MASK_SH_LIST(__SHIFT)
 350 };
 351
 352 static const struct dce_aduio_mask audio_mask = {
 353                 AUD_COMMON_MASK_SH_LIST(_MASK)
 354 };
 355
 356 #define clk_src_regs(index, id)\
 357 [index] = {\
 358         CS_COMMON_REG_LIST_DCE_112(id),\
 359 }
 360
 361 static const struct dce110_clk_src_regs clk_src_regs[] = {
 362         clk_src_regs(0, A),
 363         clk_src_regs(1, B),
 364         clk_src_regs(2, C),
 365         clk_src_regs(3, D),
 366         clk_src_regs(4, E),
 367         clk_src_regs(5, F)
 368 };
 369
 370 static const struct dce110_clk_src_shift cs_shift = {
 371                 CS_COMMON_MASK_SH_LIST_DCE_112(__SHIFT)
 372 };
 373
 374 static const struct dce110_clk_src_mask cs_mask = {
 375                 CS_COMMON_MASK_SH_LIST_DCE_112(_MASK)
 376 };
 377
 378 static const struct bios_registers bios_regs = {
 379         .BIOS_SCRATCH_6 = mmBIOS_SCRATCH_6
 380 };
 381
 382 static const struct resource_caps polaris_10_resource_cap = {
 383                 .num_timing_generator = 6,
 384                 .num_audio = 6,
 385                 .num_stream_encoder = 6,
 386                 .num_pll = 8, /* why 8? 6 combo PHY PLL + 2 regular PLLs? */
 387                 .num_ddc = 6,
 388 };
 389
 390 static const struct resource_caps polaris_11_resource_cap = {
 391                 .num_timing_generator = 5,
 392                 .num_audio = 5,
 393                 .num_stream_encoder = 5,
 394                 .num_pll = 8, /* why 8? 6 combo PHY PLL + 2 regular PLLs? */
 395                 .num_ddc = 5,
 396 };
 397
 398 #define CTX  ctx
 399 #define REG(reg) mm ## reg
 400
 401 #ifndef mmCC_DC_HDMI_STRAPS
 402 #define mmCC_DC_HDMI_STRAPS 0x4819
 403 #define CC_DC_HDMI_STRAPS__HDMI_DISABLE_MASK 0x40
 404 #define CC_DC_HDMI_STRAPS__HDMI_DISABLE__SHIFT 0x6
 405 #define CC_DC_HDMI_STRAPS__AUDIO_STREAM_NUMBER_MASK 0x700
 406 #define CC_DC_HDMI_STRAPS__AUDIO_STREAM_NUMBER__SHIFT 0x8
 407 #endif
 408
 409 static void read_dce_straps(
 410         struct dc_context *ctx,
 411         struct resource_straps *straps)
 412 {
 413         REG_GET_2(CC_DC_HDMI_STRAPS,
 414                         HDMI_DISABLE, &straps->hdmi_disable,
 415                         AUDIO_STREAM_NUMBER, &straps->audio_stream_number);
 416
 417         REG_GET(DC_PINSTRAPS, DC_PINSTRAPS_AUDIO, &straps->dc_pinstraps_audio);
 418 }
 419
 420 static struct audio *create_audio(
 421                 struct dc_context *ctx, unsigned int inst)
 422 {
 423         return dce_audio_create(ctx, inst,
 424                         &audio_regs[inst], &audio_shift, &audio_mask);
 425 }
 426
 427
 428 static struct timing_generator *dce112_timing_generator_create(
 429                 struct dc_context *ctx,
 430                 uint32_t instance,
 431                 const struct dce110_timing_generator_offsets *offsets)
 432 {
 433         struct dce110_timing_generator *tg110 =
 434                 kzalloc(sizeof(struct dce110_timing_generator), GFP_KERNEL);
 435
 436         if (!tg110)
 437                 return NULL;
 438
 439         dce110_timing_generator_construct(tg110, ctx, instance, offsets);
 440         return &tg110->base;
 441 }
 442
 443 static struct stream_encoder *dce112_stream_encoder_create(
 444         enum engine_id eng_id,
 445         struct dc_context *ctx)
 446 {
 447         struct dce110_stream_encoder *enc110 =
 448                 kzalloc(sizeof(struct dce110_stream_encoder), GFP_KERNEL);
 449
 450         if (!enc110)
 451                 return NULL;
 452
 453         dce110_stream_encoder_construct(enc110, ctx, ctx->dc_bios, eng_id,
 454                                         &stream_enc_regs[eng_id],
 455                                         &se_shift, &se_mask);
 456         return &enc110->base;
 457 }
 458
 459 #define SRII(reg_name, block, id)\
 460         .reg_name[id] = mm ## block ## id ## _ ## reg_name
 461
 462 static const struct dce_hwseq_registers hwseq_reg = {
 463                 HWSEQ_DCE112_REG_LIST()
 464 };
 465
 466 static const struct dce_hwseq_shift hwseq_shift = {
 467                 HWSEQ_DCE112_MASK_SH_LIST(__SHIFT)
 468 };
 469
 470 static const struct dce_hwseq_mask hwseq_mask = {
 471                 HWSEQ_DCE112_MASK_SH_LIST(_MASK)
 472 };
 473
 474 static struct dce_hwseq *dce112_hwseq_create(
 475         struct dc_context *ctx)
 476 {
 477         struct dce_hwseq *hws = kzalloc(sizeof(struct dce_hwseq), GFP_KERNEL);
 478
 479         if (hws) {
 480                 hws->ctx = ctx;
 481                 hws->regs = &hwseq_reg;
 482                 hws->shifts = &hwseq_shift;
 483                 hws->masks = &hwseq_mask;
 484         }
 485         return hws;
 486 }
 487
 488 static const struct resource_create_funcs res_create_funcs = {
 489         .read_dce_straps = read_dce_straps,
 490         .create_audio = create_audio,
 491         .create_stream_encoder = dce112_stream_encoder_create,
 492         .create_hwseq = dce112_hwseq_create,
 493 };
 494
 495 #define mi_inst_regs(id) { MI_DCE11_2_REG_LIST(id) }
 496 static const struct dce_mem_input_registers mi_regs[] = {
 497                 mi_inst_regs(0),
 498                 mi_inst_regs(1),
 499                 mi_inst_regs(2),
 500                 mi_inst_regs(3),
 501                 mi_inst_regs(4),
 502                 mi_inst_regs(5),
 503 };
 504
 505 static const struct dce_mem_input_shift mi_shifts = {
 506                 MI_DCE11_2_MASK_SH_LIST(__SHIFT)
 507 };
 508
 509 static const struct dce_mem_input_mask mi_masks = {
 510                 MI_DCE11_2_MASK_SH_LIST(_MASK)
 511 };
 512
 513 static struct mem_input *dce112_mem_input_create(
 514         struct dc_context *ctx,
 515         uint32_t inst)
 516 {
 517         struct dce_mem_input *dce_mi = kzalloc(sizeof(struct dce_mem_input),
 518                                                GFP_KERNEL);
 519
 520         if (!dce_mi) {
 521                 BREAK_TO_DEBUGGER();
 522                 return NULL;
 523         }
 524
 525         dce112_mem_input_construct(dce_mi, ctx, inst, &mi_regs[inst], &mi_shifts, &mi_masks);
 526         return &dce_mi->base;
 527 }
 528
 529 static void dce112_transform_destroy(struct transform **xfm)
 530 {
 531         kfree(TO_DCE_TRANSFORM(*xfm));
 532         *xfm = NULL;
 533 }
 534
 535 static struct transform *dce112_transform_create(
 536         struct dc_context *ctx,
 537         uint32_t inst)
 538 {
 539         struct dce_transform *transform =
 540                 kzalloc(sizeof(struct dce_transform), GFP_KERNEL);
 541
 542         if (!transform)
 543                 return NULL;
 544
 545         dce_transform_construct(transform, ctx, inst,
 546                                 &xfm_regs[inst], &xfm_shift, &xfm_mask);
 547         transform->lb_memory_size = 0x1404; /*5124*/
 548         return &transform->base;
 549 }
 550
 551 static const struct encoder_feature_support link_enc_feature = {
 552                 .max_hdmi_deep_color = COLOR_DEPTH_121212,
 553                 .max_hdmi_pixel_clock = 600000,
 554                 .hdmi_ycbcr420_supported = true,
 555                 .dp_ycbcr420_supported = false,
 556                 .flags.bits.IS_HBR2_CAPABLE = true,
 557                 .flags.bits.IS_HBR3_CAPABLE = true,
 558                 .flags.bits.IS_TPS3_CAPABLE = true,
 559                 .flags.bits.IS_TPS4_CAPABLE = true
 560 };
 561
 562 struct link_encoder *dce112_link_encoder_create(
 563         const struct encoder_init_data *enc_init_data)
 564 {
 565         struct dce110_link_encoder *enc110 =
 566                 kzalloc(sizeof(struct dce110_link_encoder), GFP_KERNEL);
 567
 568         if (!enc110)
 569                 return NULL;
 570
 571         dce110_link_encoder_construct(enc110,
 572                                       enc_init_data,
 573                                       &link_enc_feature,
 574                                       &link_enc_regs[enc_init_data->transmitter],
 575                                       &link_enc_aux_regs[enc_init_data->channel - 1],
 576                                       &link_enc_hpd_regs[enc_init_data->hpd_source]);
 577         return &enc110->base;
 578 }
 579
 580 static struct input_pixel_processor *dce112_ipp_create(
 581         struct dc_context *ctx, uint32_t inst)
 582 {
 583         struct dce_ipp *ipp = kzalloc(sizeof(struct dce_ipp), GFP_KERNEL);
 584
 585         if (!ipp) {
 586                 BREAK_TO_DEBUGGER();
 587                 return NULL;
 588         }
 589
 590         dce_ipp_construct(ipp, ctx, inst,
 591                         &ipp_regs[inst], &ipp_shift, &ipp_mask);
 592         return &ipp->base;
 593 }
 594
 595 struct output_pixel_processor *dce112_opp_create(
 596         struct dc_context *ctx,
 597         uint32_t inst)
 598 {
 599         struct dce110_opp *opp =
 600                 kzalloc(sizeof(struct dce110_opp), GFP_KERNEL);
 601
 602         if (!opp)
 603                 return NULL;
 604
 605         dce110_opp_construct(opp,
 606                              ctx, inst, &opp_regs[inst], &opp_shift, &opp_mask);
 607         return &opp->base;
 608 }
 609
 610 struct aux_engine *dce112_aux_engine_create(
 611         struct dc_context *ctx,
 612         uint32_t inst)
 613 {
 614         struct aux_engine_dce110 *aux_engine =
 615                 kzalloc(sizeof(struct aux_engine_dce110), GFP_KERNEL);
 616
 617         if (!aux_engine)
 618                 return NULL;
 619
 620         dce110_aux_engine_construct(aux_engine, ctx, inst,
 621                                     SW_AUX_TIMEOUT_PERIOD_MULTIPLIER * AUX_TIMEOUT_PERIOD,
 622                                     &aux_engine_regs[inst]);
 623
 624         return &aux_engine->base;
 625 }
 626 #define i2c_inst_regs(id) { I2C_HW_ENGINE_COMMON_REG_LIST(id) }
 627
 628 static const struct dce_i2c_registers i2c_hw_regs[] = {
 629                 i2c_inst_regs(1),
 630                 i2c_inst_regs(2),
 631                 i2c_inst_regs(3),
 632                 i2c_inst_regs(4),
 633                 i2c_inst_regs(5),
 634                 i2c_inst_regs(6),
 635 };
 636
 637 static const struct dce_i2c_shift i2c_shifts = {
 638                 I2C_COMMON_MASK_SH_LIST_DCE110(__SHIFT)
 639 };
 640
 641 static const struct dce_i2c_mask i2c_masks = {
 642                 I2C_COMMON_MASK_SH_LIST_DCE110(_MASK)
 643 };
 644
 645 struct dce_i2c_hw *dce112_i2c_hw_create(
 646         struct dc_context *ctx,
 647         uint32_t inst)
 648 {
 649         struct dce_i2c_hw *dce_i2c_hw =
 650                 kzalloc(sizeof(struct dce_i2c_hw), GFP_KERNEL);
 651
 652         if (!dce_i2c_hw)
 653                 return NULL;
 654
 655         dce112_i2c_hw_construct(dce_i2c_hw, ctx, inst,
 656                                     &i2c_hw_regs[inst], &i2c_shifts, &i2c_masks);
 657
 658         return dce_i2c_hw;
 659 }
 660 struct clock_source *dce112_clock_source_create(
 661         struct dc_context *ctx,
 662         struct dc_bios *bios,
 663         enum clock_source_id id,
 664         const struct dce110_clk_src_regs *regs,
 665         bool dp_clk_src)
 666 {
 667         struct dce110_clk_src *clk_src =
 668                 kzalloc(sizeof(struct dce110_clk_src), GFP_KERNEL);
 669
 670         if (!clk_src)
 671                 return NULL;
 672
 673         if (dce112_clk_src_construct(clk_src, ctx, bios, id,
 674                         regs, &cs_shift, &cs_mask)) {
 675                 clk_src->base.dp_clk_src = dp_clk_src;
 676                 return &clk_src->base;
 677         }
 678
 679         BREAK_TO_DEBUGGER();
 680         return NULL;
 681 }
 682
 683 void dce112_clock_source_destroy(struct clock_source **clk_src)
 684 {
 685         kfree(TO_DCE110_CLK_SRC(*clk_src));
 686         *clk_src = NULL;
 687 }
 688
 689 static void destruct(struct dce110_resource_pool *pool)
 690 {
 691         unsigned int i;
 692
 693         for (i = 0; i < pool->base.pipe_count; i++) {
 694                 if (pool->base.opps[i] != NULL)
 695                         dce110_opp_destroy(&pool->base.opps[i]);
 696
 697                 if (pool->base.transforms[i] != NULL)
 698                         dce112_transform_destroy(&pool->base.transforms[i]);
 699
 700                 if (pool->base.ipps[i] != NULL)
 701                         dce_ipp_destroy(&pool->base.ipps[i]);
 702
 703                 if (pool->base.mis[i] != NULL) {
 704                         kfree(TO_DCE_MEM_INPUT(pool->base.mis[i]));
 705                         pool->base.mis[i] = NULL;
 706                 }
 707
 708                 if (pool->base.timing_generators[i] != NULL) {
 709                         kfree(DCE110TG_FROM_TG(pool->base.timing_generators[i]));
 710                         pool->base.timing_generators[i] = NULL;
 711                 }
 712         }
 713
 714         for (i = 0; i < pool->base.res_cap->num_ddc; i++) {
 715                 if (pool->base.engines[i] != NULL)
 716                         dce110_engine_destroy(&pool->base.engines[i]);
 717                 if (pool->base.hw_i2cs[i] != NULL) {
 718                         kfree(pool->base.hw_i2cs[i]);
 719                         pool->base.hw_i2cs[i] = NULL;
 720                 }
 721                 if (pool->base.sw_i2cs[i] != NULL) {
 722                         kfree(pool->base.sw_i2cs[i]);
 723                         pool->base.sw_i2cs[i] = NULL;
 724                 }
 725         }
 726
 727         for (i = 0; i < pool->base.stream_enc_count; i++) {
 728                 if (pool->base.stream_enc[i] != NULL)
 729                         kfree(DCE110STRENC_FROM_STRENC(pool->base.stream_enc[i]));
 730         }
 731
 732         for (i = 0; i < pool->base.clk_src_count; i++) {
 733                 if (pool->base.clock_sources[i] != NULL) {
 734                         dce112_clock_source_destroy(&pool->base.clock_sources[i]);
 735                 }
 736         }
 737
 738         if (pool->base.dp_clock_source != NULL)
 739                 dce112_clock_source_destroy(&pool->base.dp_clock_source);
 740
 741         for (i = 0; i < pool->base.audio_count; i++)    {
 742                 if (pool->base.audios[i] != NULL) {
 743                         dce_aud_destroy(&pool->base.audios[i]);
 744                 }
 745         }
 746
 747         if (pool->base.abm != NULL)
 748                 dce_abm_destroy(&pool->base.abm);
 749
 750         if (pool->base.dmcu != NULL)
 751                 dce_dmcu_destroy(&pool->base.dmcu);
 752
 753         if (pool->base.dccg != NULL)
 754                 dce_dccg_destroy(&pool->base.dccg);
 755
 756         if (pool->base.irqs != NULL) {
 757                 dal_irq_service_destroy(&pool->base.irqs);
 758         }
 759 }
 760
 761 static struct clock_source *find_matching_pll(
 762                 struct resource_context *res_ctx,
 763                 const struct resource_pool *pool,
 764                 const struct dc_stream_state *const stream)
 765 {
 766         switch (stream->sink->link->link_enc->transmitter) {
 767         case TRANSMITTER_UNIPHY_A:
 768                 return pool->clock_sources[DCE112_CLK_SRC_PLL0];
 769         case TRANSMITTER_UNIPHY_B:
 770                 return pool->clock_sources[DCE112_CLK_SRC_PLL1];
 771         case TRANSMITTER_UNIPHY_C:
 772                 return pool->clock_sources[DCE112_CLK_SRC_PLL2];
 773         case TRANSMITTER_UNIPHY_D:
 774                 return pool->clock_sources[DCE112_CLK_SRC_PLL3];
 775         case TRANSMITTER_UNIPHY_E:
 776                 return pool->clock_sources[DCE112_CLK_SRC_PLL4];
 777         case TRANSMITTER_UNIPHY_F:
 778                 return pool->clock_sources[DCE112_CLK_SRC_PLL5];
 779         default:
 780                 return NULL;
 781         };
 782
 783         return 0;
 784 }
 785
 786 static enum dc_status build_mapped_resource(
 787                 const struct dc *dc,
 788                 struct dc_state *context,
 789                 struct dc_stream_state *stream)
 790 {
 791         struct pipe_ctx *pipe_ctx = resource_get_head_pipe_for_stream(&context->res_ctx, stream);
 792
 793         if (!pipe_ctx)
 794                 return DC_ERROR_UNEXPECTED;
 795
 796         dce110_resource_build_pipe_hw_param(pipe_ctx);
 797
 798         resource_build_info_frame(pipe_ctx);
 799
 800         return DC_OK;
 801 }
 802
 803 bool dce112_validate_bandwidth(
 804         struct dc *dc,
 805         struct dc_state *context)
 806 {
 807         bool result = false;
 808
 809         DC_LOG_BANDWIDTH_CALCS(
 810                 "%s: start",
 811                 __func__);
 812
 813         if (bw_calcs(
 814                         dc->ctx,
 815                         dc->bw_dceip,
 816                         dc->bw_vbios,
 817                         context->res_ctx.pipe_ctx,
 818                         dc->res_pool->pipe_count,
 819                         &context->bw.dce))
 820                 result = true;
 821
 822         if (!result)
 823                 DC_LOG_BANDWIDTH_VALIDATION(
 824                         "%s: Bandwidth validation failed!",
 825                         __func__);
 826
 827         if (memcmp(&dc->current_state->bw.dce,
 828                         &context->bw.dce, sizeof(context->bw.dce))) {
 829
 830                 DC_LOG_BANDWIDTH_CALCS(
 831                         "%s: finish,\n"
 832                         "nbpMark_b: %d nbpMark_a: %d urgentMark_b: %d urgentMark_a: %d\n"
 833                         "stutMark_b: %d stutMark_a: %d\n"
 834                         "nbpMark_b: %d nbpMark_a: %d urgentMark_b: %d urgentMark_a: %d\n"
 835                         "stutMark_b: %d stutMark_a: %d\n"
 836                         "nbpMark_b: %d nbpMark_a: %d urgentMark_b: %d urgentMark_a: %d\n"
 837                         "stutMark_b: %d stutMark_a: %d stutter_mode_enable: %d\n"
 838                         "cstate: %d pstate: %d nbpstate: %d sync: %d dispclk: %d\n"
 839                         "sclk: %d sclk_sleep: %d yclk: %d blackout_recovery_time_us: %d\n"
 840                         ,
 841                         __func__,
 842                         context->bw.dce.nbp_state_change_wm_ns[0].b_mark,
 843                         context->bw.dce.nbp_state_change_wm_ns[0].a_mark,
 844                         context->bw.dce.urgent_wm_ns[0].b_mark,
 845                         context->bw.dce.urgent_wm_ns[0].a_mark,
 846                         context->bw.dce.stutter_exit_wm_ns[0].b_mark,
 847                         context->bw.dce.stutter_exit_wm_ns[0].a_mark,
 848                         context->bw.dce.nbp_state_change_wm_ns[1].b_mark,
 849                         context->bw.dce.nbp_state_change_wm_ns[1].a_mark,
 850                         context->bw.dce.urgent_wm_ns[1].b_mark,
 851                         context->bw.dce.urgent_wm_ns[1].a_mark,
 852                         context->bw.dce.stutter_exit_wm_ns[1].b_mark,
 853                         context->bw.dce.stutter_exit_wm_ns[1].a_mark,
 854                         context->bw.dce.nbp_state_change_wm_ns[2].b_mark,
 855                         context->bw.dce.nbp_state_change_wm_ns[2].a_mark,
 856                         context->bw.dce.urgent_wm_ns[2].b_mark,
 857                         context->bw.dce.urgent_wm_ns[2].a_mark,
 858                         context->bw.dce.stutter_exit_wm_ns[2].b_mark,
 859                         context->bw.dce.stutter_exit_wm_ns[2].a_mark,
 860                         context->bw.dce.stutter_mode_enable,
 861                         context->bw.dce.cpuc_state_change_enable,
 862                         context->bw.dce.cpup_state_change_enable,
 863                         context->bw.dce.nbp_state_change_enable,
 864                         context->bw.dce.all_displays_in_sync,
 865                         context->bw.dce.dispclk_khz,
 866                         context->bw.dce.sclk_khz,
 867                         context->bw.dce.sclk_deep_sleep_khz,
 868                         context->bw.dce.yclk_khz,
 869                         context->bw.dce.blackout_recovery_time_us);
 870         }
 871         return result;
 872 }
 873
 874 enum dc_status resource_map_phy_clock_resources(
 875                 const struct dc *dc,
 876                 struct dc_state *context,
 877                 struct dc_stream_state *stream)
 878 {
 879
 880         /* acquire new resources */
 881         struct pipe_ctx *pipe_ctx = resource_get_head_pipe_for_stream(
 882                         &context->res_ctx, stream);
 883
 884         if (!pipe_ctx)
 885                 return DC_ERROR_UNEXPECTED;
 886
 887         if (dc_is_dp_signal(pipe_ctx->stream->signal)
 888                 || pipe_ctx->stream->signal == SIGNAL_TYPE_VIRTUAL)
 889                 pipe_ctx->clock_source =
 890                                 dc->res_pool->dp_clock_source;
 891         else
 892                 pipe_ctx->clock_source = find_matching_pll(
 893                         &context->res_ctx, dc->res_pool,
 894                         stream);
 895
 896         if (pipe_ctx->clock_source == NULL)
 897                 return DC_NO_CLOCK_SOURCE_RESOURCE;
 898
 899         resource_reference_clock_source(
 900                 &context->res_ctx,
 901                 dc->res_pool,
 902                 pipe_ctx->clock_source);
 903
 904         return DC_OK;
 905 }
 906
 907 static bool dce112_validate_surface_sets(
 908                 struct dc_state *context)
 909 {
 910         int i;
 911
 912         for (i = 0; i < context->stream_count; i++) {
 913                 if (context->stream_status[i].plane_count == 0)
 914                         continue;
 915
 916                 if (context->stream_status[i].plane_count > 1)
 917                         return false;
 918
 919                 if (context->stream_status[i].plane_states[0]->format
 920                                 >= SURFACE_PIXEL_FORMAT_VIDEO_BEGIN)
 921                         return false;
 922         }
 923
 924         return true;
 925 }
 926
 927 enum dc_status dce112_add_stream_to_ctx(
 928                 struct dc *dc,
 929                 struct dc_state *new_ctx,
 930                 struct dc_stream_state *dc_stream)
 931 {
 932         enum dc_status result = DC_ERROR_UNEXPECTED;
 933
 934         result = resource_map_pool_resources(dc, new_ctx, dc_stream);
 935
 936         if (result == DC_OK)
 937                 result = resource_map_phy_clock_resources(dc, new_ctx, dc_stream);
 938
 939
 940         if (result == DC_OK)
 941                 result = build_mapped_resource(dc, new_ctx, dc_stream);
 942
 943         return result;
 944 }
 945
 946 enum dc_status dce112_validate_global(
 947                 struct dc *dc,
 948                 struct dc_state *context)
 949 {
 950         if (!dce112_validate_surface_sets(context))
 951                 return DC_FAIL_SURFACE_VALIDATE;
 952
 953         return DC_OK;
 954 }
 955
 956 static void dce112_destroy_resource_pool(struct resource_pool **pool)
 957 {
 958         struct dce110_resource_pool *dce110_pool = TO_DCE110_RES_POOL(*pool);
 959
 960         destruct(dce110_pool);
 961         kfree(dce110_pool);
 962         *pool = NULL;
 963 }
 964
 965 static const struct resource_funcs dce112_res_pool_funcs = {
 966         .destroy = dce112_destroy_resource_pool,
 967         .link_enc_create = dce112_link_encoder_create,
 968         .validate_bandwidth = dce112_validate_bandwidth,
 969         .validate_plane = dce100_validate_plane,
 970         .add_stream_to_ctx = dce112_add_stream_to_ctx,
 971         .validate_global = dce112_validate_global
 972 };
 973
 974 static void bw_calcs_data_update_from_pplib(struct dc *dc)
 975 {
 976         struct dm_pp_clock_levels_with_latency eng_clks = {0};
 977         struct dm_pp_clock_levels_with_latency mem_clks = {0};
 978         struct dm_pp_wm_sets_with_clock_ranges clk_ranges = {0};
 979         struct dm_pp_clock_levels clks = {0};
 980
 981         /*do system clock  TODO PPLIB: after PPLIB implement,
 982          * then remove old way
 983          */
 984         if (!dm_pp_get_clock_levels_by_type_with_latency(
 985                         dc->ctx,
 986                         DM_PP_CLOCK_TYPE_ENGINE_CLK,
 987                         &eng_clks)) {
 988
 989                 /* This is only for temporary */
 990                 dm_pp_get_clock_levels_by_type(
 991                                 dc->ctx,
 992                                 DM_PP_CLOCK_TYPE_ENGINE_CLK,
 993                                 &clks);
 994                 /* convert all the clock fro kHz to fix point mHz */
 995                 dc->bw_vbios->high_sclk = bw_frc_to_fixed(
 996                                 clks.clocks_in_khz[clks.num_levels-1], 1000);
 997                 dc->bw_vbios->mid1_sclk  = bw_frc_to_fixed(
 998                                 clks.clocks_in_khz[clks.num_levels/8], 1000);
 999                 dc->bw_vbios->mid2_sclk  = bw_frc_to_fixed(
1000                                 clks.clocks_in_khz[clks.num_levels*2/8], 1000);
1001                 dc->bw_vbios->mid3_sclk  = bw_frc_to_fixed(
1002                                 clks.clocks_in_khz[clks.num_levels*3/8], 1000);
1003                 dc->bw_vbios->mid4_sclk  = bw_frc_to_fixed(
1004                                 clks.clocks_in_khz[clks.num_levels*4/8], 1000);
1005                 dc->bw_vbios->mid5_sclk  = bw_frc_to_fixed(
1006                                 clks.clocks_in_khz[clks.num_levels*5/8], 1000);
1007                 dc->bw_vbios->mid6_sclk  = bw_frc_to_fixed(
1008                                 clks.clocks_in_khz[clks.num_levels*6/8], 1000);
1009                 dc->bw_vbios->low_sclk  = bw_frc_to_fixed(
1010                                 clks.clocks_in_khz[0], 1000);
1011
1012                 /*do memory clock*/
1013                 dm_pp_get_clock_levels_by_type(
1014                                 dc->ctx,
1015                                 DM_PP_CLOCK_TYPE_MEMORY_CLK,
1016                                 &clks);
1017
1018                 dc->bw_vbios->low_yclk = bw_frc_to_fixed(
1019                         clks.clocks_in_khz[0] * MEMORY_TYPE_MULTIPLIER_CZ, 1000);
1020                 dc->bw_vbios->mid_yclk = bw_frc_to_fixed(
1021                         clks.clocks_in_khz[clks.num_levels>>1] * MEMORY_TYPE_MULTIPLIER_CZ,
1022                         1000);
1023                 dc->bw_vbios->high_yclk = bw_frc_to_fixed(
1024                         clks.clocks_in_khz[clks.num_levels-1] * MEMORY_TYPE_MULTIPLIER_CZ,
1025                         1000);
1026
1027                 return;
1028         }
1029
1030         /* convert all the clock fro kHz to fix point mHz  TODO: wloop data */
1031         dc->bw_vbios->high_sclk = bw_frc_to_fixed(
1032                 eng_clks.data[eng_clks.num_levels-1].clocks_in_khz, 1000);
1033         dc->bw_vbios->mid1_sclk  = bw_frc_to_fixed(
1034                 eng_clks.data[eng_clks.num_levels/8].clocks_in_khz, 1000);
1035         dc->bw_vbios->mid2_sclk  = bw_frc_to_fixed(
1036                 eng_clks.data[eng_clks.num_levels*2/8].clocks_in_khz, 1000);
1037         dc->bw_vbios->mid3_sclk  = bw_frc_to_fixed(
1038                 eng_clks.data[eng_clks.num_levels*3/8].clocks_in_khz, 1000);
1039         dc->bw_vbios->mid4_sclk  = bw_frc_to_fixed(
1040                 eng_clks.data[eng_clks.num_levels*4/8].clocks_in_khz, 1000);
1041         dc->bw_vbios->mid5_sclk  = bw_frc_to_fixed(
1042                 eng_clks.data[eng_clks.num_levels*5/8].clocks_in_khz, 1000);
1043         dc->bw_vbios->mid6_sclk  = bw_frc_to_fixed(
1044                 eng_clks.data[eng_clks.num_levels*6/8].clocks_in_khz, 1000);
1045         dc->bw_vbios->low_sclk  = bw_frc_to_fixed(
1046                         eng_clks.data[0].clocks_in_khz, 1000);
1047
1048         /*do memory clock*/
1049         dm_pp_get_clock_levels_by_type_with_latency(
1050                         dc->ctx,
1051                         DM_PP_CLOCK_TYPE_MEMORY_CLK,
1052                         &mem_clks);
1053
1054         /* we don't need to call PPLIB for validation clock since they
1055          * also give us the highest sclk and highest mclk (UMA clock).
1056          * ALSO always convert UMA clock (from PPLIB)  to YCLK (HW formula):
1057          * YCLK = UMACLK*m_memoryTypeMultiplier
1058          */
1059         dc->bw_vbios->low_yclk = bw_frc_to_fixed(
1060                 mem_clks.data[0].clocks_in_khz * MEMORY_TYPE_MULTIPLIER_CZ, 1000);
1061         dc->bw_vbios->mid_yclk = bw_frc_to_fixed(
1062                 mem_clks.data[mem_clks.num_levels>>1].clocks_in_khz * MEMORY_TYPE_MULTIPLIER_CZ,
1063                 1000);
1064         dc->bw_vbios->high_yclk = bw_frc_to_fixed(
1065                 mem_clks.data[mem_clks.num_levels-1].clocks_in_khz * MEMORY_TYPE_MULTIPLIER_CZ,
1066                 1000);
1067
1068         /* Now notify PPLib/SMU about which Watermarks sets they should select
1069          * depending on DPM state they are in. And update BW MGR GFX Engine and
1070          * Memory clock member variables for Watermarks calculations for each
1071          * Watermark Set
1072          */
1073         clk_ranges.num_wm_sets = 4;
1074         clk_ranges.wm_clk_ranges[0].wm_set_id = WM_SET_A;
1075         clk_ranges.wm_clk_ranges[0].wm_min_eng_clk_in_khz =
1076                         eng_clks.data[0].clocks_in_khz;
1077         clk_ranges.wm_clk_ranges[0].wm_max_eng_clk_in_khz =
1078                         eng_clks.data[eng_clks.num_levels*3/8].clocks_in_khz - 1;
1079         clk_ranges.wm_clk_ranges[0].wm_min_mem_clk_in_khz =
1080                         mem_clks.data[0].clocks_in_khz;
1081         clk_ranges.wm_clk_ranges[0].wm_max_mem_clk_in_khz =
1082                         mem_clks.data[mem_clks.num_levels>>1].clocks_in_khz - 1;
1083
1084         clk_ranges.wm_clk_ranges[1].wm_set_id = WM_SET_B;
1085         clk_ranges.wm_clk_ranges[1].wm_min_eng_clk_in_khz =
1086                         eng_clks.data[eng_clks.num_levels*3/8].clocks_in_khz;
1087         /* 5 GHz instead of data[7].clockInKHz to cover Overdrive */
1088         clk_ranges.wm_clk_ranges[1].wm_max_eng_clk_in_khz = 5000000;
1089         clk_ranges.wm_clk_ranges[1].wm_min_mem_clk_in_khz =
1090                         mem_clks.data[0].clocks_in_khz;
1091         clk_ranges.wm_clk_ranges[1].wm_max_mem_clk_in_khz =
1092                         mem_clks.data[mem_clks.num_levels>>1].clocks_in_khz - 1;
1093
1094         clk_ranges.wm_clk_ranges[2].wm_set_id = WM_SET_C;
1095         clk_ranges.wm_clk_ranges[2].wm_min_eng_clk_in_khz =
1096                         eng_clks.data[0].clocks_in_khz;
1097         clk_ranges.wm_clk_ranges[2].wm_max_eng_clk_in_khz =
1098                         eng_clks.data[eng_clks.num_levels*3/8].clocks_in_khz - 1;
1099         clk_ranges.wm_clk_ranges[2].wm_min_mem_clk_in_khz =
1100                         mem_clks.data[mem_clks.num_levels>>1].clocks_in_khz;
1101         /* 5 GHz instead of data[2].clockInKHz to cover Overdrive */
1102         clk_ranges.wm_clk_ranges[2].wm_max_mem_clk_in_khz = 5000000;
1103
1104         clk_ranges.wm_clk_ranges[3].wm_set_id = WM_SET_D;
1105         clk_ranges.wm_clk_ranges[3].wm_min_eng_clk_in_khz =
1106                         eng_clks.data[eng_clks.num_levels*3/8].clocks_in_khz;
1107         /* 5 GHz instead of data[7].clockInKHz to cover Overdrive */
1108         clk_ranges.wm_clk_ranges[3].wm_max_eng_clk_in_khz = 5000000;
1109         clk_ranges.wm_clk_ranges[3].wm_min_mem_clk_in_khz =
1110                         mem_clks.data[mem_clks.num_levels>>1].clocks_in_khz;
1111         /* 5 GHz instead of data[2].clockInKHz to cover Overdrive */
1112         clk_ranges.wm_clk_ranges[3].wm_max_mem_clk_in_khz = 5000000;
1113
1114         /* Notify PP Lib/SMU which Watermarks to use for which clock ranges */
1115         dm_pp_notify_wm_clock_changes(dc->ctx, &clk_ranges);
1116 }
1117
1118 const struct resource_caps *dce112_resource_cap(
1119         struct hw_asic_id *asic_id)
1120 {
1121         if (ASIC_REV_IS_POLARIS11_M(asic_id->hw_internal_rev) ||
1122             ASIC_REV_IS_POLARIS12_V(asic_id->hw_internal_rev))
1123                 return &polaris_11_resource_cap;
1124         else
1125                 return &polaris_10_resource_cap;
1126 }
1127
1128 static bool construct(
1129         uint8_t num_virtual_links,
1130         struct dc *dc,
1131         struct dce110_resource_pool *pool)
1132 {
1133         unsigned int i;
1134         struct dc_context *ctx = dc->ctx;
1135
1136         ctx->dc_bios->regs = &bios_regs;
1137
1138         pool->base.res_cap = dce112_resource_cap(&ctx->asic_id);
1139         pool->base.funcs = &dce112_res_pool_funcs;
1140
1141         /*************************************************
1142          *  Resource + asic cap harcoding                *
1143          *************************************************/
1144         pool->base.underlay_pipe_index = NO_UNDERLAY_PIPE;
1145         pool->base.pipe_count = pool->base.res_cap->num_timing_generator;
1146         pool->base.timing_generator_count = pool->base.res_cap->num_timing_generator;
1147         dc->caps.max_downscale_ratio = 200;
1148         dc->caps.i2c_speed_in_khz = 100;
1149         dc->caps.max_cursor_size = 128;
1150         dc->caps.dual_link_dvi = true;
1151
1152
1153         /*************************************************
1154          *  Create resources                             *
1155          *************************************************/
1156
1157         pool->base.clock_sources[DCE112_CLK_SRC_PLL0] =
1158                         dce112_clock_source_create(
1159                                 ctx, ctx->dc_bios,
1160                                 CLOCK_SOURCE_COMBO_PHY_PLL0,
1161                                 &clk_src_regs[0], false);
1162         pool->base.clock_sources[DCE112_CLK_SRC_PLL1] =
1163                         dce112_clock_source_create(
1164                                 ctx, ctx->dc_bios,
1165                                 CLOCK_SOURCE_COMBO_PHY_PLL1,
1166                                 &clk_src_regs[1], false);
1167         pool->base.clock_sources[DCE112_CLK_SRC_PLL2] =
1168                         dce112_clock_source_create(
1169                                 ctx, ctx->dc_bios,
1170                                 CLOCK_SOURCE_COMBO_PHY_PLL2,
1171                                 &clk_src_regs[2], false);
1172         pool->base.clock_sources[DCE112_CLK_SRC_PLL3] =
1173                         dce112_clock_source_create(
1174                                 ctx, ctx->dc_bios,
1175                                 CLOCK_SOURCE_COMBO_PHY_PLL3,
1176                                 &clk_src_regs[3], false);
1177         pool->base.clock_sources[DCE112_CLK_SRC_PLL4] =
1178                         dce112_clock_source_create(
1179                                 ctx, ctx->dc_bios,
1180                                 CLOCK_SOURCE_COMBO_PHY_PLL4,
1181                                 &clk_src_regs[4], false);
1182         pool->base.clock_sources[DCE112_CLK_SRC_PLL5] =
1183                         dce112_clock_source_create(
1184                                 ctx, ctx->dc_bios,
1185                                 CLOCK_SOURCE_COMBO_PHY_PLL5,
1186                                 &clk_src_regs[5], false);
1187         pool->base.clk_src_count = DCE112_CLK_SRC_TOTAL;
1188
1189         pool->base.dp_clock_source =  dce112_clock_source_create(
1190                 ctx, ctx->dc_bios,
1191                 CLOCK_SOURCE_ID_DP_DTO, &clk_src_regs[0], true);
1192
1193
1194         for (i = 0; i < pool->base.clk_src_count; i++) {
1195                 if (pool->base.clock_sources[i] == NULL) {
1196                         dm_error("DC: failed to create clock sources!\n");
1197                         BREAK_TO_DEBUGGER();
1198                         goto res_create_fail;
1199                 }
1200         }
1201
1202         pool->base.dccg = dce112_dccg_create(ctx,
1203                         &disp_clk_regs,
1204                         &disp_clk_shift,
1205                         &disp_clk_mask);
1206         if (pool->base.dccg == NULL) {
1207                 dm_error("DC: failed to create display clock!\n");
1208                 BREAK_TO_DEBUGGER();
1209                 goto res_create_fail;
1210         }
1211
1212         pool->base.dmcu = dce_dmcu_create(ctx,
1213                         &dmcu_regs,
1214                         &dmcu_shift,
1215                         &dmcu_mask);
1216         if (pool->base.dmcu == NULL) {
1217                 dm_error("DC: failed to create dmcu!\n");
1218                 BREAK_TO_DEBUGGER();
1219                 goto res_create_fail;
1220         }
1221
1222         pool->base.abm = dce_abm_create(ctx,
1223                         &abm_regs,
1224                         &abm_shift,
1225                         &abm_mask);
1226         if (pool->base.abm == NULL) {
1227                 dm_error("DC: failed to create abm!\n");
1228                 BREAK_TO_DEBUGGER();
1229                 goto res_create_fail;
1230         }
1231
1232         {
1233                 struct irq_service_init_data init_data;
1234                 init_data.ctx = dc->ctx;
1235                 pool->base.irqs = dal_irq_service_dce110_create(&init_data);
1236                 if (!pool->base.irqs)
1237                         goto res_create_fail;
1238         }
1239
1240         for (i = 0; i < pool->base.pipe_count; i++) {
1241                 pool->base.timing_generators[i] =
1242                                 dce112_timing_generator_create(
1243                                         ctx,
1244                                         i,
1245                                         &dce112_tg_offsets[i]);
1246                 if (pool->base.timing_generators[i] == NULL) {
1247                         BREAK_TO_DEBUGGER();
1248                         dm_error("DC: failed to create tg!\n");
1249                         goto res_create_fail;
1250                 }
1251
1252                 pool->base.mis[i] = dce112_mem_input_create(ctx, i);
1253                 if (pool->base.mis[i] == NULL) {
1254                         BREAK_TO_DEBUGGER();
1255                         dm_error(
1256                                 "DC: failed to create memory input!\n");
1257                         goto res_create_fail;
1258                 }
1259
1260                 pool->base.ipps[i] = dce112_ipp_create(ctx, i);
1261                 if (pool->base.ipps[i] == NULL) {
1262                         BREAK_TO_DEBUGGER();
1263                         dm_error(
1264                                 "DC:failed to create input pixel processor!\n");
1265                         goto res_create_fail;
1266                 }
1267
1268                 pool->base.transforms[i] = dce112_transform_create(ctx, i);
1269                 if (pool->base.transforms[i] == NULL) {
1270                         BREAK_TO_DEBUGGER();
1271                         dm_error(
1272                                 "DC: failed to create transform!\n");
1273                         goto res_create_fail;
1274                 }
1275
1276                 pool->base.opps[i] = dce112_opp_create(
1277                         ctx,
1278                         i);
1279                 if (pool->base.opps[i] == NULL) {
1280                         BREAK_TO_DEBUGGER();
1281                         dm_error(
1282                                 "DC:failed to create output pixel processor!\n");
1283                         goto res_create_fail;
1284                 }
1285         }
1286
1287         for (i = 0; i < pool->base.res_cap->num_ddc; i++) {
1288                 pool->base.engines[i] = dce112_aux_engine_create(ctx, i);
1289                 if (pool->base.engines[i] == NULL) {
1290                         BREAK_TO_DEBUGGER();
1291                         dm_error(
1292                                 "DC:failed to create aux engine!!\n");
1293                         goto res_create_fail;
1294                 }
1295                 pool->base.hw_i2cs[i] = dce112_i2c_hw_create(ctx, i);
1296                 if (pool->base.hw_i2cs[i] == NULL) {
1297                         BREAK_TO_DEBUGGER();
1298                         dm_error(
1299                                 "DC:failed to create i2c engine!!\n");
1300                         goto res_create_fail;
1301                 }
1302                 pool->base.sw_i2cs[i] = NULL;
1303         }
1304
1305         if (!resource_construct(num_virtual_links, dc, &pool->base,
1306                           &res_create_funcs))
1307                 goto res_create_fail;
1308
1309         dc->caps.max_planes =  pool->base.pipe_count;
1310
1311         /* Create hardware sequencer */
1312         dce112_hw_sequencer_construct(dc);
1313
1314         bw_calcs_init(dc->bw_dceip, dc->bw_vbios, dc->ctx->asic_id);
1315
1316         bw_calcs_data_update_from_pplib(dc);
1317
1318         return true;
1319
1320 res_create_fail:
1321         destruct(pool);
1322         return false;
1323 }
1324
1325 struct resource_pool *dce112_create_resource_pool(
1326         uint8_t num_virtual_links,
1327         struct dc *dc)
1328 {
1329         struct dce110_resource_pool *pool =
1330                 kzalloc(sizeof(struct dce110_resource_pool), GFP_KERNEL);
1331
1332         if (!pool)
1333                 return NULL;
1334
1335         if (construct(num_virtual_links, dc, pool))
1336                 return &pool->base;
1337
1338         BREAK_TO_DEBUGGER();
1339         return NULL;
1340 }