drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c

   1 /*
   2 * Copyright 2012-15 Advanced Micro Devices, Inc.cls
   3 *
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the "Software"),
   7  * to deal in the Software without restriction, including without limitation
   8  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   9  * and/or sell copies of the Software, and to permit persons to whom the
  10  * Software is furnished to do so, subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice shall be included in
  13  * all copies or substantial portions of the Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  19  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  20  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  21  * OTHER DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors: AMD
  24  *
  25  */
  26
  27 #include "dm_services.h"
  28
  29
  30 #include "stream_encoder.h"
  31 #include "resource.h"
  32 #include "include/irq_service_interface.h"
  33 #include "dce120_resource.h"
  34 #include "dce112/dce112_resource.h"
  35
  36 #include "dce110/dce110_resource.h"
  37 #include "../virtual/virtual_stream_encoder.h"
  38 #include "dce120_timing_generator.h"
  39 #include "irq/dce120/irq_service_dce120.h"
  40 #include "dce/dce_opp.h"
  41 #include "dce/dce_clock_source.h"
  42 #include "dce/dce_clocks.h"
  43 #include "dce/dce_ipp.h"
  44 #include "dce/dce_mem_input.h"
  45
  46 #include "dce110/dce110_hw_sequencer.h"
  47 #include "dce120/dce120_hw_sequencer.h"
  48 #include "dce/dce_transform.h"
  49
  50 #include "dce/dce_audio.h"
  51 #include "dce/dce_link_encoder.h"
  52 #include "dce/dce_stream_encoder.h"
  53 #include "dce/dce_hwseq.h"
  54 #include "dce/dce_abm.h"
  55 #include "dce/dce_dmcu.h"
  56 #include "dce/dce_aux.h"
  57 #include "dce/dce_i2c.h"
  58
  59 #include "dce/dce_12_0_offset.h"
  60 #include "dce/dce_12_0_sh_mask.h"
  61 #include "soc15_hw_ip.h"
  62 #include "vega10_ip_offset.h"
  63 #include "nbio/nbio_6_1_offset.h"
  64 #include "reg_helper.h"
  65
  66 #include "dce100/dce100_resource.h"
  67
  68 #ifndef mmDP0_DP_DPHY_INTERNAL_CTRL
  69         #define mmDP0_DP_DPHY_INTERNAL_CTRL             0x210f
  70         #define mmDP0_DP_DPHY_INTERNAL_CTRL_BASE_IDX    2
  71         #define mmDP1_DP_DPHY_INTERNAL_CTRL             0x220f
  72         #define mmDP1_DP_DPHY_INTERNAL_CTRL_BASE_IDX    2
  73         #define mmDP2_DP_DPHY_INTERNAL_CTRL             0x230f
  74         #define mmDP2_DP_DPHY_INTERNAL_CTRL_BASE_IDX    2
  75         #define mmDP3_DP_DPHY_INTERNAL_CTRL             0x240f
  76         #define mmDP3_DP_DPHY_INTERNAL_CTRL_BASE_IDX    2
  77         #define mmDP4_DP_DPHY_INTERNAL_CTRL             0x250f
  78         #define mmDP4_DP_DPHY_INTERNAL_CTRL_BASE_IDX    2
  79         #define mmDP5_DP_DPHY_INTERNAL_CTRL             0x260f
  80         #define mmDP5_DP_DPHY_INTERNAL_CTRL_BASE_IDX    2
  81         #define mmDP6_DP_DPHY_INTERNAL_CTRL             0x270f
  82         #define mmDP6_DP_DPHY_INTERNAL_CTRL_BASE_IDX    2
  83 #endif
  84
  85 enum dce120_clk_src_array_id {
  86         DCE120_CLK_SRC_PLL0,
  87         DCE120_CLK_SRC_PLL1,
  88         DCE120_CLK_SRC_PLL2,
  89         DCE120_CLK_SRC_PLL3,
  90         DCE120_CLK_SRC_PLL4,
  91         DCE120_CLK_SRC_PLL5,
  92
  93         DCE120_CLK_SRC_TOTAL
  94 };
  95
  96 static const struct dce110_timing_generator_offsets dce120_tg_offsets[] = {
  97         {
  98                 .crtc = (mmCRTC0_CRTC_CONTROL - mmCRTC0_CRTC_CONTROL),
  99         },
 100         {
 101                 .crtc = (mmCRTC1_CRTC_CONTROL - mmCRTC0_CRTC_CONTROL),
 102         },
 103         {
 104                 .crtc = (mmCRTC2_CRTC_CONTROL - mmCRTC0_CRTC_CONTROL),
 105         },
 106         {
 107                 .crtc = (mmCRTC3_CRTC_CONTROL - mmCRTC0_CRTC_CONTROL),
 108         },
 109         {
 110                 .crtc = (mmCRTC4_CRTC_CONTROL - mmCRTC0_CRTC_CONTROL),
 111         },
 112         {
 113                 .crtc = (mmCRTC5_CRTC_CONTROL - mmCRTC0_CRTC_CONTROL),
 114         }
 115 };
 116
 117 /* begin *********************
 118  * macros to expend register list macro defined in HW object header file */
 119
 120 #define BASE_INNER(seg) \
 121         DCE_BASE__INST0_SEG ## seg
 122
 123 #define NBIO_BASE_INNER(seg) \
 124         NBIF_BASE__INST0_SEG ## seg
 125
 126 #define NBIO_BASE(seg) \
 127         NBIO_BASE_INNER(seg)
 128
 129 /* compile time expand base address. */
 130 #define BASE(seg) \
 131         BASE_INNER(seg)
 132
 133 #define SR(reg_name)\
 134                 .reg_name = BASE(mm ## reg_name ## _BASE_IDX) +  \
 135                                         mm ## reg_name
 136
 137 #define SRI(reg_name, block, id)\
 138         .reg_name = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
 139                                         mm ## block ## id ## _ ## reg_name
 140
 141 /* macros to expend register list macro defined in HW object header file
 142  * end *********************/
 143
 144
 145 static const struct dce_dmcu_registers dmcu_regs = {
 146                 DMCU_DCE110_COMMON_REG_LIST()
 147 };
 148
 149 static const struct dce_dmcu_shift dmcu_shift = {
 150                 DMCU_MASK_SH_LIST_DCE110(__SHIFT)
 151 };
 152
 153 static const struct dce_dmcu_mask dmcu_mask = {
 154                 DMCU_MASK_SH_LIST_DCE110(_MASK)
 155 };
 156
 157 static const struct dce_abm_registers abm_regs = {
 158                 ABM_DCE110_COMMON_REG_LIST()
 159 };
 160
 161 static const struct dce_abm_shift abm_shift = {
 162                 ABM_MASK_SH_LIST_DCE110(__SHIFT)
 163 };
 164
 165 static const struct dce_abm_mask abm_mask = {
 166                 ABM_MASK_SH_LIST_DCE110(_MASK)
 167 };
 168
 169 #define ipp_regs(id)\
 170 [id] = {\
 171                 IPP_DCE110_REG_LIST_DCE_BASE(id)\
 172 }
 173
 174 static const struct dce_ipp_registers ipp_regs[] = {
 175                 ipp_regs(0),
 176                 ipp_regs(1),
 177                 ipp_regs(2),
 178                 ipp_regs(3),
 179                 ipp_regs(4),
 180                 ipp_regs(5)
 181 };
 182
 183 static const struct dce_ipp_shift ipp_shift = {
 184                 IPP_DCE120_MASK_SH_LIST_SOC_BASE(__SHIFT)
 185 };
 186
 187 static const struct dce_ipp_mask ipp_mask = {
 188                 IPP_DCE120_MASK_SH_LIST_SOC_BASE(_MASK)
 189 };
 190
 191 #define transform_regs(id)\
 192 [id] = {\
 193                 XFM_COMMON_REG_LIST_DCE110(id)\
 194 }
 195
 196 static const struct dce_transform_registers xfm_regs[] = {
 197                 transform_regs(0),
 198                 transform_regs(1),
 199                 transform_regs(2),
 200                 transform_regs(3),
 201                 transform_regs(4),
 202                 transform_regs(5)
 203 };
 204
 205 static const struct dce_transform_shift xfm_shift = {
 206                 XFM_COMMON_MASK_SH_LIST_SOC_BASE(__SHIFT)
 207 };
 208
 209 static const struct dce_transform_mask xfm_mask = {
 210                 XFM_COMMON_MASK_SH_LIST_SOC_BASE(_MASK)
 211 };
 212
 213 #define aux_regs(id)\
 214 [id] = {\
 215         AUX_REG_LIST(id)\
 216 }
 217
 218 static const struct dce110_link_enc_aux_registers link_enc_aux_regs[] = {
 219                 aux_regs(0),
 220                 aux_regs(1),
 221                 aux_regs(2),
 222                 aux_regs(3),
 223                 aux_regs(4),
 224                 aux_regs(5)
 225 };
 226
 227 #define hpd_regs(id)\
 228 [id] = {\
 229         HPD_REG_LIST(id)\
 230 }
 231
 232 static const struct dce110_link_enc_hpd_registers link_enc_hpd_regs[] = {
 233                 hpd_regs(0),
 234                 hpd_regs(1),
 235                 hpd_regs(2),
 236                 hpd_regs(3),
 237                 hpd_regs(4),
 238                 hpd_regs(5)
 239 };
 240
 241 #define link_regs(id)\
 242 [id] = {\
 243         LE_DCE120_REG_LIST(id), \
 244         SRI(DP_DPHY_INTERNAL_CTRL, DP, id) \
 245 }
 246
 247 static const struct dce110_link_enc_registers link_enc_regs[] = {
 248         link_regs(0),
 249         link_regs(1),
 250         link_regs(2),
 251         link_regs(3),
 252         link_regs(4),
 253         link_regs(5),
 254         link_regs(6),
 255 };
 256
 257
 258 #define stream_enc_regs(id)\
 259 [id] = {\
 260         SE_COMMON_REG_LIST(id),\
 261         .TMDS_CNTL = 0,\
 262 }
 263
 264 static const struct dce110_stream_enc_registers stream_enc_regs[] = {
 265         stream_enc_regs(0),
 266         stream_enc_regs(1),
 267         stream_enc_regs(2),
 268         stream_enc_regs(3),
 269         stream_enc_regs(4),
 270         stream_enc_regs(5)
 271 };
 272
 273 static const struct dce_stream_encoder_shift se_shift = {
 274                 SE_COMMON_MASK_SH_LIST_DCE120(__SHIFT)
 275 };
 276
 277 static const struct dce_stream_encoder_mask se_mask = {
 278                 SE_COMMON_MASK_SH_LIST_DCE120(_MASK)
 279 };
 280
 281 #define opp_regs(id)\
 282 [id] = {\
 283         OPP_DCE_120_REG_LIST(id),\
 284 }
 285
 286 static const struct dce_opp_registers opp_regs[] = {
 287         opp_regs(0),
 288         opp_regs(1),
 289         opp_regs(2),
 290         opp_regs(3),
 291         opp_regs(4),
 292         opp_regs(5)
 293 };
 294
 295 static const struct dce_opp_shift opp_shift = {
 296         OPP_COMMON_MASK_SH_LIST_DCE_120(__SHIFT)
 297 };
 298
 299 static const struct dce_opp_mask opp_mask = {
 300         OPP_COMMON_MASK_SH_LIST_DCE_120(_MASK)
 301 };
 302  #define aux_engine_regs(id)\
 303 [id] = {\
 304         AUX_COMMON_REG_LIST(id), \
 305         .AUX_RESET_MASK = 0 \
 306 }
 307
 308 static const struct dce110_aux_registers aux_engine_regs[] = {
 309                 aux_engine_regs(0),
 310                 aux_engine_regs(1),
 311                 aux_engine_regs(2),
 312                 aux_engine_regs(3),
 313                 aux_engine_regs(4),
 314                 aux_engine_regs(5)
 315 };
 316
 317 #define audio_regs(id)\
 318 [id] = {\
 319         AUD_COMMON_REG_LIST(id)\
 320 }
 321
 322 static const struct dce_audio_registers audio_regs[] = {
 323         audio_regs(0),
 324         audio_regs(1),
 325         audio_regs(2),
 326         audio_regs(3),
 327         audio_regs(4),
 328         audio_regs(5)
 329 };
 330
 331 #define DCE120_AUD_COMMON_MASK_SH_LIST(mask_sh)\
 332                 SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_INDEX, AZALIA_ENDPOINT_REG_INDEX, mask_sh),\
 333                 SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_DATA, AZALIA_ENDPOINT_REG_DATA, mask_sh),\
 334                 AUD_COMMON_MASK_SH_LIST_BASE(mask_sh)
 335
 336 static const struct dce_audio_shift audio_shift = {
 337                 DCE120_AUD_COMMON_MASK_SH_LIST(__SHIFT)
 338 };
 339
 340 static const struct dce_aduio_mask audio_mask = {
 341                 DCE120_AUD_COMMON_MASK_SH_LIST(_MASK)
 342 };
 343
 344 #define clk_src_regs(index, id)\
 345 [index] = {\
 346         CS_COMMON_REG_LIST_DCE_112(id),\
 347 }
 348
 349 static const struct dce110_clk_src_regs clk_src_regs[] = {
 350         clk_src_regs(0, A),
 351         clk_src_regs(1, B),
 352         clk_src_regs(2, C),
 353         clk_src_regs(3, D),
 354         clk_src_regs(4, E),
 355         clk_src_regs(5, F)
 356 };
 357
 358 static const struct dce110_clk_src_shift cs_shift = {
 359                 CS_COMMON_MASK_SH_LIST_DCE_112(__SHIFT)
 360 };
 361
 362 static const struct dce110_clk_src_mask cs_mask = {
 363                 CS_COMMON_MASK_SH_LIST_DCE_112(_MASK)
 364 };
 365
 366 struct output_pixel_processor *dce120_opp_create(
 367         struct dc_context *ctx,
 368         uint32_t inst)
 369 {
 370         struct dce110_opp *opp =
 371                 kzalloc(sizeof(struct dce110_opp), GFP_KERNEL);
 372
 373         if (!opp)
 374                 return NULL;
 375
 376         dce110_opp_construct(opp,
 377                              ctx, inst, &opp_regs[inst], &opp_shift, &opp_mask);
 378         return &opp->base;
 379 }
 380 struct aux_engine *dce120_aux_engine_create(
 381         struct dc_context *ctx,
 382         uint32_t inst)
 383 {
 384         struct aux_engine_dce110 *aux_engine =
 385                 kzalloc(sizeof(struct aux_engine_dce110), GFP_KERNEL);
 386
 387         if (!aux_engine)
 388                 return NULL;
 389
 390         dce110_aux_engine_construct(aux_engine, ctx, inst,
 391                                     SW_AUX_TIMEOUT_PERIOD_MULTIPLIER * AUX_TIMEOUT_PERIOD,
 392                                     &aux_engine_regs[inst]);
 393
 394         return &aux_engine->base;
 395 }
 396 #define i2c_inst_regs(id) { I2C_HW_ENGINE_COMMON_REG_LIST(id) }
 397
 398 static const struct dce_i2c_registers i2c_hw_regs[] = {
 399                 i2c_inst_regs(1),
 400                 i2c_inst_regs(2),
 401                 i2c_inst_regs(3),
 402                 i2c_inst_regs(4),
 403                 i2c_inst_regs(5),
 404                 i2c_inst_regs(6),
 405 };
 406
 407 static const struct dce_i2c_shift i2c_shifts = {
 408                 I2C_COMMON_MASK_SH_LIST_DCE110(__SHIFT)
 409 };
 410
 411 static const struct dce_i2c_mask i2c_masks = {
 412                 I2C_COMMON_MASK_SH_LIST_DCE110(_MASK)
 413 };
 414
 415 struct dce_i2c_hw *dce120_i2c_hw_create(
 416         struct dc_context *ctx,
 417         uint32_t inst)
 418 {
 419         struct dce_i2c_hw *dce_i2c_hw =
 420                 kzalloc(sizeof(struct dce_i2c_hw), GFP_KERNEL);
 421
 422         if (!dce_i2c_hw)
 423                 return NULL;
 424
 425         dce112_i2c_hw_construct(dce_i2c_hw, ctx, inst,
 426                                     &i2c_hw_regs[inst], &i2c_shifts, &i2c_masks);
 427
 428         return dce_i2c_hw;
 429 }
 430 static const struct bios_registers bios_regs = {
 431         .BIOS_SCRATCH_6 = mmBIOS_SCRATCH_6 + NBIO_BASE(mmBIOS_SCRATCH_6_BASE_IDX)
 432 };
 433
 434 static const struct resource_caps res_cap = {
 435                 .num_timing_generator = 6,
 436                 .num_audio = 7,
 437                 .num_stream_encoder = 6,
 438                 .num_pll = 6,
 439                 .num_ddc = 6,
 440 };
 441
 442 static const struct dc_debug_options debug_defaults = {
 443                 .disable_clock_gate = true,
 444 };
 445
 446 struct clock_source *dce120_clock_source_create(
 447         struct dc_context *ctx,
 448         struct dc_bios *bios,
 449         enum clock_source_id id,
 450         const struct dce110_clk_src_regs *regs,
 451         bool dp_clk_src)
 452 {
 453         struct dce110_clk_src *clk_src =
 454                 kzalloc(sizeof(*clk_src), GFP_KERNEL);
 455
 456         if (!clk_src)
 457                 return NULL;
 458
 459         if (dce112_clk_src_construct(clk_src, ctx, bios, id,
 460                                      regs, &cs_shift, &cs_mask)) {
 461                 clk_src->base.dp_clk_src = dp_clk_src;
 462                 return &clk_src->base;
 463         }
 464
 465         BREAK_TO_DEBUGGER();
 466         return NULL;
 467 }
 468
 469 void dce120_clock_source_destroy(struct clock_source **clk_src)
 470 {
 471         kfree(TO_DCE110_CLK_SRC(*clk_src));
 472         *clk_src = NULL;
 473 }
 474
 475
 476 bool dce120_hw_sequencer_create(struct dc *dc)
 477 {
 478         /* All registers used by dce11.2 match those in dce11 in offset and
 479          * structure
 480          */
 481         dce120_hw_sequencer_construct(dc);
 482
 483         /*TODO  Move to separate file and Override what is needed */
 484
 485         return true;
 486 }
 487
 488 static struct timing_generator *dce120_timing_generator_create(
 489                 struct dc_context *ctx,
 490                 uint32_t instance,
 491                 const struct dce110_timing_generator_offsets *offsets)
 492 {
 493         struct dce110_timing_generator *tg110 =
 494                 kzalloc(sizeof(struct dce110_timing_generator), GFP_KERNEL);
 495
 496         if (!tg110)
 497                 return NULL;
 498
 499         dce120_timing_generator_construct(tg110, ctx, instance, offsets);
 500         return &tg110->base;
 501 }
 502
 503 static void dce120_transform_destroy(struct transform **xfm)
 504 {
 505         kfree(TO_DCE_TRANSFORM(*xfm));
 506         *xfm = NULL;
 507 }
 508
 509 static void destruct(struct dce110_resource_pool *pool)
 510 {
 511         unsigned int i;
 512
 513         for (i = 0; i < pool->base.pipe_count; i++) {
 514                 if (pool->base.opps[i] != NULL)
 515                         dce110_opp_destroy(&pool->base.opps[i]);
 516
 517                 if (pool->base.transforms[i] != NULL)
 518                         dce120_transform_destroy(&pool->base.transforms[i]);
 519
 520                 if (pool->base.ipps[i] != NULL)
 521                         dce_ipp_destroy(&pool->base.ipps[i]);
 522
 523                 if (pool->base.mis[i] != NULL) {
 524                         kfree(TO_DCE_MEM_INPUT(pool->base.mis[i]));
 525                         pool->base.mis[i] = NULL;
 526                 }
 527
 528                 if (pool->base.irqs != NULL) {
 529                         dal_irq_service_destroy(&pool->base.irqs);
 530                 }
 531
 532                 if (pool->base.timing_generators[i] != NULL) {
 533                         kfree(DCE110TG_FROM_TG(pool->base.timing_generators[i]));
 534                         pool->base.timing_generators[i] = NULL;
 535                 }
 536         }
 537
 538         for (i = 0; i < pool->base.res_cap->num_ddc; i++) {
 539                 if (pool->base.engines[i] != NULL)
 540                         dce110_engine_destroy(&pool->base.engines[i]);
 541                 if (pool->base.hw_i2cs[i] != NULL) {
 542                         kfree(pool->base.hw_i2cs[i]);
 543                         pool->base.hw_i2cs[i] = NULL;
 544                 }
 545                 if (pool->base.sw_i2cs[i] != NULL) {
 546                         kfree(pool->base.sw_i2cs[i]);
 547                         pool->base.sw_i2cs[i] = NULL;
 548                 }
 549         }
 550
 551         for (i = 0; i < pool->base.audio_count; i++) {
 552                 if (pool->base.audios[i])
 553                         dce_aud_destroy(&pool->base.audios[i]);
 554         }
 555
 556         for (i = 0; i < pool->base.stream_enc_count; i++) {
 557                 if (pool->base.stream_enc[i] != NULL)
 558                         kfree(DCE110STRENC_FROM_STRENC(pool->base.stream_enc[i]));
 559         }
 560
 561         for (i = 0; i < pool->base.clk_src_count; i++) {
 562                 if (pool->base.clock_sources[i] != NULL)
 563                         dce120_clock_source_destroy(
 564                                 &pool->base.clock_sources[i]);
 565         }
 566
 567         if (pool->base.dp_clock_source != NULL)
 568                 dce120_clock_source_destroy(&pool->base.dp_clock_source);
 569
 570         if (pool->base.abm != NULL)
 571                 dce_abm_destroy(&pool->base.abm);
 572
 573         if (pool->base.dmcu != NULL)
 574                 dce_dmcu_destroy(&pool->base.dmcu);
 575
 576         if (pool->base.dccg != NULL)
 577                 dce_dccg_destroy(&pool->base.dccg);
 578 }
 579
 580 static void read_dce_straps(
 581         struct dc_context *ctx,
 582         struct resource_straps *straps)
 583 {
 584         uint32_t reg_val = dm_read_reg_soc15(ctx, mmCC_DC_MISC_STRAPS, 0);
 585
 586         straps->audio_stream_number = get_reg_field_value(reg_val,
 587                                                           CC_DC_MISC_STRAPS,
 588                                                           AUDIO_STREAM_NUMBER);
 589         straps->hdmi_disable = get_reg_field_value(reg_val,
 590                                                    CC_DC_MISC_STRAPS,
 591                                                    HDMI_DISABLE);
 592
 593         reg_val = dm_read_reg_soc15(ctx, mmDC_PINSTRAPS, 0);
 594         straps->dc_pinstraps_audio = get_reg_field_value(reg_val,
 595                                                          DC_PINSTRAPS,
 596                                                          DC_PINSTRAPS_AUDIO);
 597 }
 598
 599 static struct audio *create_audio(
 600                 struct dc_context *ctx, unsigned int inst)
 601 {
 602         return dce_audio_create(ctx, inst,
 603                         &audio_regs[inst], &audio_shift, &audio_mask);
 604 }
 605
 606 static const struct encoder_feature_support link_enc_feature = {
 607                 .max_hdmi_deep_color = COLOR_DEPTH_121212,
 608                 .max_hdmi_pixel_clock = 600000,
 609                 .ycbcr420_supported = true,
 610                 .flags.bits.IS_HBR2_CAPABLE = true,
 611                 .flags.bits.IS_HBR3_CAPABLE = true,
 612                 .flags.bits.IS_TPS3_CAPABLE = true,
 613                 .flags.bits.IS_TPS4_CAPABLE = true,
 614 };
 615
 616 static struct link_encoder *dce120_link_encoder_create(
 617         const struct encoder_init_data *enc_init_data)
 618 {
 619         struct dce110_link_encoder *enc110 =
 620                 kzalloc(sizeof(struct dce110_link_encoder), GFP_KERNEL);
 621
 622         if (!enc110)
 623                 return NULL;
 624
 625         dce110_link_encoder_construct(enc110,
 626                                       enc_init_data,
 627                                       &link_enc_feature,
 628                                       &link_enc_regs[enc_init_data->transmitter],
 629                                       &link_enc_aux_regs[enc_init_data->channel - 1],
 630                                       &link_enc_hpd_regs[enc_init_data->hpd_source]);
 631
 632         return &enc110->base;
 633 }
 634
 635 static struct input_pixel_processor *dce120_ipp_create(
 636         struct dc_context *ctx, uint32_t inst)
 637 {
 638         struct dce_ipp *ipp = kzalloc(sizeof(struct dce_ipp), GFP_KERNEL);
 639
 640         if (!ipp) {
 641                 BREAK_TO_DEBUGGER();
 642                 return NULL;
 643         }
 644
 645         dce_ipp_construct(ipp, ctx, inst,
 646                         &ipp_regs[inst], &ipp_shift, &ipp_mask);
 647         return &ipp->base;
 648 }
 649
 650 static struct stream_encoder *dce120_stream_encoder_create(
 651         enum engine_id eng_id,
 652         struct dc_context *ctx)
 653 {
 654         struct dce110_stream_encoder *enc110 =
 655                 kzalloc(sizeof(struct dce110_stream_encoder), GFP_KERNEL);
 656
 657         if (!enc110)
 658                 return NULL;
 659
 660         dce110_stream_encoder_construct(enc110, ctx, ctx->dc_bios, eng_id,
 661                                         &stream_enc_regs[eng_id],
 662                                         &se_shift, &se_mask);
 663         return &enc110->base;
 664 }
 665
 666 #define SRII(reg_name, block, id)\
 667         .reg_name[id] = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
 668                                         mm ## block ## id ## _ ## reg_name
 669
 670 static const struct dce_hwseq_registers hwseq_reg = {
 671                 HWSEQ_DCE120_REG_LIST()
 672 };
 673
 674 static const struct dce_hwseq_shift hwseq_shift = {
 675                 HWSEQ_DCE12_MASK_SH_LIST(__SHIFT)
 676 };
 677
 678 static const struct dce_hwseq_mask hwseq_mask = {
 679                 HWSEQ_DCE12_MASK_SH_LIST(_MASK)
 680 };
 681
 682 static struct dce_hwseq *dce120_hwseq_create(
 683         struct dc_context *ctx)
 684 {
 685         struct dce_hwseq *hws = kzalloc(sizeof(struct dce_hwseq), GFP_KERNEL);
 686
 687         if (hws) {
 688                 hws->ctx = ctx;
 689                 hws->regs = &hwseq_reg;
 690                 hws->shifts = &hwseq_shift;
 691                 hws->masks = &hwseq_mask;
 692         }
 693         return hws;
 694 }
 695
 696 static const struct resource_create_funcs res_create_funcs = {
 697         .read_dce_straps = read_dce_straps,
 698         .create_audio = create_audio,
 699         .create_stream_encoder = dce120_stream_encoder_create,
 700         .create_hwseq = dce120_hwseq_create,
 701 };
 702
 703 #define mi_inst_regs(id) { MI_DCE12_REG_LIST(id) }
 704 static const struct dce_mem_input_registers mi_regs[] = {
 705                 mi_inst_regs(0),
 706                 mi_inst_regs(1),
 707                 mi_inst_regs(2),
 708                 mi_inst_regs(3),
 709                 mi_inst_regs(4),
 710                 mi_inst_regs(5),
 711 };
 712
 713 static const struct dce_mem_input_shift mi_shifts = {
 714                 MI_DCE12_MASK_SH_LIST(__SHIFT)
 715 };
 716
 717 static const struct dce_mem_input_mask mi_masks = {
 718                 MI_DCE12_MASK_SH_LIST(_MASK)
 719 };
 720
 721 static struct mem_input *dce120_mem_input_create(
 722         struct dc_context *ctx,
 723         uint32_t inst)
 724 {
 725         struct dce_mem_input *dce_mi = kzalloc(sizeof(struct dce_mem_input),
 726                                                GFP_KERNEL);
 727
 728         if (!dce_mi) {
 729                 BREAK_TO_DEBUGGER();
 730                 return NULL;
 731         }
 732
 733         dce120_mem_input_construct(dce_mi, ctx, inst, &mi_regs[inst], &mi_shifts, &mi_masks);
 734         return &dce_mi->base;
 735 }
 736
 737 static struct transform *dce120_transform_create(
 738         struct dc_context *ctx,
 739         uint32_t inst)
 740 {
 741         struct dce_transform *transform =
 742                 kzalloc(sizeof(struct dce_transform), GFP_KERNEL);
 743
 744         if (!transform)
 745                 return NULL;
 746
 747         dce_transform_construct(transform, ctx, inst,
 748                                 &xfm_regs[inst], &xfm_shift, &xfm_mask);
 749         transform->lb_memory_size = 0x1404; /*5124*/
 750         return &transform->base;
 751 }
 752
 753 static void dce120_destroy_resource_pool(struct resource_pool **pool)
 754 {
 755         struct dce110_resource_pool *dce110_pool = TO_DCE110_RES_POOL(*pool);
 756
 757         destruct(dce110_pool);
 758         kfree(dce110_pool);
 759         *pool = NULL;
 760 }
 761
 762 static const struct resource_funcs dce120_res_pool_funcs = {
 763         .destroy = dce120_destroy_resource_pool,
 764         .link_enc_create = dce120_link_encoder_create,
 765         .validate_bandwidth = dce112_validate_bandwidth,
 766         .validate_plane = dce100_validate_plane,
 767         .add_stream_to_ctx = dce112_add_stream_to_ctx
 768 };
 769
 770 static void bw_calcs_data_update_from_pplib(struct dc *dc)
 771 {
 772         struct dm_pp_clock_levels_with_latency eng_clks = {0};
 773         struct dm_pp_clock_levels_with_latency mem_clks = {0};
 774         struct dm_pp_wm_sets_with_clock_ranges clk_ranges = {0};
 775         int i;
 776         unsigned int clk;
 777         unsigned int latency;
 778
 779         /*do system clock*/
 780         if (!dm_pp_get_clock_levels_by_type_with_latency(
 781                                 dc->ctx,
 782                                 DM_PP_CLOCK_TYPE_ENGINE_CLK,
 783                                 &eng_clks) || eng_clks.num_levels == 0) {
 784
 785                 eng_clks.num_levels = 8;
 786                 clk = 300000;
 787
 788                 for (i = 0; i < eng_clks.num_levels; i++) {
 789                         eng_clks.data[i].clocks_in_khz = clk;
 790                         clk += 100000;
 791                 }
 792         }
 793
 794         /* convert all the clock fro kHz to fix point mHz  TODO: wloop data */
 795         dc->bw_vbios->high_sclk = bw_frc_to_fixed(
 796                 eng_clks.data[eng_clks.num_levels-1].clocks_in_khz, 1000);
 797         dc->bw_vbios->mid1_sclk  = bw_frc_to_fixed(
 798                 eng_clks.data[eng_clks.num_levels/8].clocks_in_khz, 1000);
 799         dc->bw_vbios->mid2_sclk  = bw_frc_to_fixed(
 800                 eng_clks.data[eng_clks.num_levels*2/8].clocks_in_khz, 1000);
 801         dc->bw_vbios->mid3_sclk  = bw_frc_to_fixed(
 802                 eng_clks.data[eng_clks.num_levels*3/8].clocks_in_khz, 1000);
 803         dc->bw_vbios->mid4_sclk  = bw_frc_to_fixed(
 804                 eng_clks.data[eng_clks.num_levels*4/8].clocks_in_khz, 1000);
 805         dc->bw_vbios->mid5_sclk  = bw_frc_to_fixed(
 806                 eng_clks.data[eng_clks.num_levels*5/8].clocks_in_khz, 1000);
 807         dc->bw_vbios->mid6_sclk  = bw_frc_to_fixed(
 808                 eng_clks.data[eng_clks.num_levels*6/8].clocks_in_khz, 1000);
 809         dc->bw_vbios->low_sclk  = bw_frc_to_fixed(
 810                         eng_clks.data[0].clocks_in_khz, 1000);
 811
 812         /*do memory clock*/
 813         if (!dm_pp_get_clock_levels_by_type_with_latency(
 814                         dc->ctx,
 815                         DM_PP_CLOCK_TYPE_MEMORY_CLK,
 816                         &mem_clks) || mem_clks.num_levels == 0) {
 817
 818                 mem_clks.num_levels = 3;
 819                 clk = 250000;
 820                 latency = 45;
 821
 822                 for (i = 0; i < eng_clks.num_levels; i++) {
 823                         mem_clks.data[i].clocks_in_khz = clk;
 824                         mem_clks.data[i].latency_in_us = latency;
 825                         clk += 500000;
 826                         latency -= 5;
 827                 }
 828
 829         }
 830
 831         /* we don't need to call PPLIB for validation clock since they
 832          * also give us the highest sclk and highest mclk (UMA clock).
 833          * ALSO always convert UMA clock (from PPLIB)  to YCLK (HW formula):
 834          * YCLK = UMACLK*m_memoryTypeMultiplier
 835          */
 836         dc->bw_vbios->low_yclk = bw_frc_to_fixed(
 837                 mem_clks.data[0].clocks_in_khz * MEMORY_TYPE_MULTIPLIER, 1000);
 838         dc->bw_vbios->mid_yclk = bw_frc_to_fixed(
 839                 mem_clks.data[mem_clks.num_levels>>1].clocks_in_khz * MEMORY_TYPE_MULTIPLIER,
 840                 1000);
 841         dc->bw_vbios->high_yclk = bw_frc_to_fixed(
 842                 mem_clks.data[mem_clks.num_levels-1].clocks_in_khz * MEMORY_TYPE_MULTIPLIER,
 843                 1000);
 844
 845         /* Now notify PPLib/SMU about which Watermarks sets they should select
 846          * depending on DPM state they are in. And update BW MGR GFX Engine and
 847          * Memory clock member variables for Watermarks calculations for each
 848          * Watermark Set
 849          */
 850         clk_ranges.num_wm_sets = 4;
 851         clk_ranges.wm_clk_ranges[0].wm_set_id = WM_SET_A;
 852         clk_ranges.wm_clk_ranges[0].wm_min_eng_clk_in_khz =
 853                         eng_clks.data[0].clocks_in_khz;
 854         clk_ranges.wm_clk_ranges[0].wm_max_eng_clk_in_khz =
 855                         eng_clks.data[eng_clks.num_levels*3/8].clocks_in_khz - 1;
 856         clk_ranges.wm_clk_ranges[0].wm_min_mem_clk_in_khz =
 857                         mem_clks.data[0].clocks_in_khz;
 858         clk_ranges.wm_clk_ranges[0].wm_max_mem_clk_in_khz =
 859                         mem_clks.data[mem_clks.num_levels>>1].clocks_in_khz - 1;
 860
 861         clk_ranges.wm_clk_ranges[1].wm_set_id = WM_SET_B;
 862         clk_ranges.wm_clk_ranges[1].wm_min_eng_clk_in_khz =
 863                         eng_clks.data[eng_clks.num_levels*3/8].clocks_in_khz;
 864         /* 5 GHz instead of data[7].clockInKHz to cover Overdrive */
 865         clk_ranges.wm_clk_ranges[1].wm_max_eng_clk_in_khz = 5000000;
 866         clk_ranges.wm_clk_ranges[1].wm_min_mem_clk_in_khz =
 867                         mem_clks.data[0].clocks_in_khz;
 868         clk_ranges.wm_clk_ranges[1].wm_max_mem_clk_in_khz =
 869                         mem_clks.data[mem_clks.num_levels>>1].clocks_in_khz - 1;
 870
 871         clk_ranges.wm_clk_ranges[2].wm_set_id = WM_SET_C;
 872         clk_ranges.wm_clk_ranges[2].wm_min_eng_clk_in_khz =
 873                         eng_clks.data[0].clocks_in_khz;
 874         clk_ranges.wm_clk_ranges[2].wm_max_eng_clk_in_khz =
 875                         eng_clks.data[eng_clks.num_levels*3/8].clocks_in_khz - 1;
 876         clk_ranges.wm_clk_ranges[2].wm_min_mem_clk_in_khz =
 877                         mem_clks.data[mem_clks.num_levels>>1].clocks_in_khz;
 878         /* 5 GHz instead of data[2].clockInKHz to cover Overdrive */
 879         clk_ranges.wm_clk_ranges[2].wm_max_mem_clk_in_khz = 5000000;
 880
 881         clk_ranges.wm_clk_ranges[3].wm_set_id = WM_SET_D;
 882         clk_ranges.wm_clk_ranges[3].wm_min_eng_clk_in_khz =
 883                         eng_clks.data[eng_clks.num_levels*3/8].clocks_in_khz;
 884         /* 5 GHz instead of data[7].clockInKHz to cover Overdrive */
 885         clk_ranges.wm_clk_ranges[3].wm_max_eng_clk_in_khz = 5000000;
 886         clk_ranges.wm_clk_ranges[3].wm_min_mem_clk_in_khz =
 887                         mem_clks.data[mem_clks.num_levels>>1].clocks_in_khz;
 888         /* 5 GHz instead of data[2].clockInKHz to cover Overdrive */
 889         clk_ranges.wm_clk_ranges[3].wm_max_mem_clk_in_khz = 5000000;
 890
 891         /* Notify PP Lib/SMU which Watermarks to use for which clock ranges */
 892         dm_pp_notify_wm_clock_changes(dc->ctx, &clk_ranges);
 893 }
 894
 895 static uint32_t read_pipe_fuses(struct dc_context *ctx)
 896 {
 897         uint32_t value = dm_read_reg_soc15(ctx, mmCC_DC_PIPE_DIS, 0);
 898         /* VG20 support max 6 pipes */
 899         value = value & 0x3f;
 900         return value;
 901 }
 902
 903 static bool construct(
 904         uint8_t num_virtual_links,
 905         struct dc *dc,
 906         struct dce110_resource_pool *pool)
 907 {
 908         unsigned int i;
 909         int j;
 910         struct dc_context *ctx = dc->ctx;
 911         struct irq_service_init_data irq_init_data;
 912         bool harvest_enabled = ASICREV_IS_VEGA20_P(ctx->asic_id.hw_internal_rev);
 913         uint32_t pipe_fuses;
 914
 915         ctx->dc_bios->regs = &bios_regs;
 916
 917         pool->base.res_cap = &res_cap;
 918         pool->base.funcs = &dce120_res_pool_funcs;
 919
 920         /* TODO: Fill more data from GreenlandAsicCapability.cpp */
 921         pool->base.pipe_count = res_cap.num_timing_generator;
 922         pool->base.timing_generator_count = pool->base.res_cap->num_timing_generator;
 923         pool->base.underlay_pipe_index = NO_UNDERLAY_PIPE;
 924
 925         dc->caps.max_downscale_ratio = 200;
 926         dc->caps.i2c_speed_in_khz = 100;
 927         dc->caps.max_cursor_size = 128;
 928         dc->caps.dual_link_dvi = true;
 929         dc->caps.psp_setup_panel_mode = true;
 930
 931         dc->debug = debug_defaults;
 932
 933         /*************************************************
 934          *  Create resources                             *
 935          *************************************************/
 936
 937         pool->base.clock_sources[DCE120_CLK_SRC_PLL0] =
 938                         dce120_clock_source_create(ctx, ctx->dc_bios,
 939                                 CLOCK_SOURCE_COMBO_PHY_PLL0,
 940                                 &clk_src_regs[0], false);
 941         pool->base.clock_sources[DCE120_CLK_SRC_PLL1] =
 942                         dce120_clock_source_create(ctx, ctx->dc_bios,
 943                                 CLOCK_SOURCE_COMBO_PHY_PLL1,
 944                                 &clk_src_regs[1], false);
 945         pool->base.clock_sources[DCE120_CLK_SRC_PLL2] =
 946                         dce120_clock_source_create(ctx, ctx->dc_bios,
 947                                 CLOCK_SOURCE_COMBO_PHY_PLL2,
 948                                 &clk_src_regs[2], false);
 949         pool->base.clock_sources[DCE120_CLK_SRC_PLL3] =
 950                         dce120_clock_source_create(ctx, ctx->dc_bios,
 951                                 CLOCK_SOURCE_COMBO_PHY_PLL3,
 952                                 &clk_src_regs[3], false);
 953         pool->base.clock_sources[DCE120_CLK_SRC_PLL4] =
 954                         dce120_clock_source_create(ctx, ctx->dc_bios,
 955                                 CLOCK_SOURCE_COMBO_PHY_PLL4,
 956                                 &clk_src_regs[4], false);
 957         pool->base.clock_sources[DCE120_CLK_SRC_PLL5] =
 958                         dce120_clock_source_create(ctx, ctx->dc_bios,
 959                                 CLOCK_SOURCE_COMBO_PHY_PLL5,
 960                                 &clk_src_regs[5], false);
 961         pool->base.clk_src_count = DCE120_CLK_SRC_TOTAL;
 962
 963         pool->base.dp_clock_source =
 964                         dce120_clock_source_create(ctx, ctx->dc_bios,
 965                                 CLOCK_SOURCE_ID_DP_DTO,
 966                                 &clk_src_regs[0], true);
 967
 968         for (i = 0; i < pool->base.clk_src_count; i++) {
 969                 if (pool->base.clock_sources[i] == NULL) {
 970                         dm_error("DC: failed to create clock sources!\n");
 971                         BREAK_TO_DEBUGGER();
 972                         goto clk_src_create_fail;
 973                 }
 974         }
 975
 976         pool->base.dccg = dce120_dccg_create(ctx);
 977         if (pool->base.dccg == NULL) {
 978                 dm_error("DC: failed to create display clock!\n");
 979                 BREAK_TO_DEBUGGER();
 980                 goto dccg_create_fail;
 981         }
 982
 983         pool->base.dmcu = dce_dmcu_create(ctx,
 984                         &dmcu_regs,
 985                         &dmcu_shift,
 986                         &dmcu_mask);
 987         if (pool->base.dmcu == NULL) {
 988                 dm_error("DC: failed to create dmcu!\n");
 989                 BREAK_TO_DEBUGGER();
 990                 goto res_create_fail;
 991         }
 992
 993         pool->base.abm = dce_abm_create(ctx,
 994                         &abm_regs,
 995                         &abm_shift,
 996                         &abm_mask);
 997         if (pool->base.abm == NULL) {
 998                 dm_error("DC: failed to create abm!\n");
 999                 BREAK_TO_DEBUGGER();
1000                 goto res_create_fail;
1001         }
1002
1003
1004         irq_init_data.ctx = dc->ctx;
1005         pool->base.irqs = dal_irq_service_dce120_create(&irq_init_data);
1006         if (!pool->base.irqs)
1007                 goto irqs_create_fail;
1008
1009         /* retrieve valid pipe fuses */
1010         if (harvest_enabled)
1011                 pipe_fuses = read_pipe_fuses(ctx);
1012
1013         /* index to valid pipe resource */
1014         j = 0;
1015         for (i = 0; i < pool->base.pipe_count; i++) {
1016                 if (harvest_enabled) {
1017                         if ((pipe_fuses & (1 << i)) != 0) {
1018                                 dm_error("DC: skip invalid pipe %d!\n", i);
1019                                 continue;
1020                         }
1021                 }
1022
1023                 pool->base.timing_generators[j] =
1024                                 dce120_timing_generator_create(
1025                                         ctx,
1026                                         i,
1027                                         &dce120_tg_offsets[i]);
1028                 if (pool->base.timing_generators[j] == NULL) {
1029                         BREAK_TO_DEBUGGER();
1030                         dm_error("DC: failed to create tg!\n");
1031                         goto controller_create_fail;
1032                 }
1033
1034                 pool->base.mis[j] = dce120_mem_input_create(ctx, i);
1035
1036                 if (pool->base.mis[j] == NULL) {
1037                         BREAK_TO_DEBUGGER();
1038                         dm_error(
1039                                 "DC: failed to create memory input!\n");
1040                         goto controller_create_fail;
1041                 }
1042
1043                 pool->base.ipps[j] = dce120_ipp_create(ctx, i);
1044                 if (pool->base.ipps[i] == NULL) {
1045                         BREAK_TO_DEBUGGER();
1046                         dm_error(
1047                                 "DC: failed to create input pixel processor!\n");
1048                         goto controller_create_fail;
1049                 }
1050
1051                 pool->base.transforms[j] = dce120_transform_create(ctx, i);
1052                 if (pool->base.transforms[i] == NULL) {
1053                         BREAK_TO_DEBUGGER();
1054                         dm_error(
1055                                 "DC: failed to create transform!\n");
1056                         goto res_create_fail;
1057                 }
1058
1059                 pool->base.opps[j] = dce120_opp_create(
1060                         ctx,
1061                         i);
1062                 if (pool->base.opps[j] == NULL) {
1063                         BREAK_TO_DEBUGGER();
1064                         dm_error(
1065                                 "DC: failed to create output pixel processor!\n");
1066                 }
1067
1068                 /* check next valid pipe */
1069                 j++;
1070         }
1071
1072         for (i = 0; i < pool->base.res_cap->num_ddc; i++) {
1073                 pool->base.engines[i] = dce120_aux_engine_create(ctx, i);
1074                 if (pool->base.engines[i] == NULL) {
1075                         BREAK_TO_DEBUGGER();
1076                         dm_error(
1077                                 "DC:failed to create aux engine!!\n");
1078                         goto res_create_fail;
1079                 }
1080                 pool->base.hw_i2cs[i] = dce120_i2c_hw_create(ctx, i);
1081                 if (pool->base.hw_i2cs[i] == NULL) {
1082                         BREAK_TO_DEBUGGER();
1083                         dm_error(
1084                                 "DC:failed to create i2c engine!!\n");
1085                         goto res_create_fail;
1086                 }
1087                 pool->base.sw_i2cs[i] = NULL;
1088         }
1089
1090         /* valid pipe num */
1091         pool->base.pipe_count = j;
1092         pool->base.timing_generator_count = j;
1093
1094         if (!resource_construct(num_virtual_links, dc, &pool->base,
1095                          &res_create_funcs))
1096                 goto res_create_fail;
1097
1098         /* Create hardware sequencer */
1099         if (!dce120_hw_sequencer_create(dc))
1100                 goto controller_create_fail;
1101
1102         dc->caps.max_planes =  pool->base.pipe_count;
1103
1104         bw_calcs_init(dc->bw_dceip, dc->bw_vbios, dc->ctx->asic_id);
1105
1106         bw_calcs_data_update_from_pplib(dc);
1107
1108         return true;
1109
1110 irqs_create_fail:
1111 controller_create_fail:
1112 dccg_create_fail:
1113 clk_src_create_fail:
1114 res_create_fail:
1115
1116         destruct(pool);
1117
1118         return false;
1119 }
1120
1121 struct resource_pool *dce120_create_resource_pool(
1122         uint8_t num_virtual_links,
1123         struct dc *dc)
1124 {
1125         struct dce110_resource_pool *pool =
1126                 kzalloc(sizeof(struct dce110_resource_pool), GFP_KERNEL);
1127
1128         if (!pool)
1129                 return NULL;
1130
1131         if (construct(num_virtual_links, dc, pool))
1132                 return &pool->base;
1133
1134         BREAK_TO_DEBUGGER();
1135         return NULL;
1136 }