drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c

   1 /*
   2  * Copyright 2016 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: AMD
  23  *
  24  */
  25
  26 #include "dm_services.h"
  27
  28 #include "core_types.h"
  29
  30 #include "reg_helper.h"
  31 #include "dcn10_dpp.h"
  32 #include "basics/conversion.h"
  33 #include "dcn10_cm_common.h"
  34
  35 #define NUM_PHASES    64
  36 #define HORZ_MAX_TAPS 8
  37 #define VERT_MAX_TAPS 8
  38
  39 #define BLACK_OFFSET_RGB_Y 0x0
  40 #define BLACK_OFFSET_CBCR  0x8000
  41
  42 #define REG(reg)\
  43         dpp->tf_regs->reg
  44
  45 #define CTX \
  46         dpp->base.ctx
  47
  48 #undef FN
  49 #define FN(reg_name, field_name) \
  50         dpp->tf_shift->field_name, dpp->tf_mask->field_name
  51
  52 struct dcn10_input_csc_matrix {
  53         enum dc_color_space color_space;
  54         uint16_t regval[12];
  55 };
  56
  57 enum dcn10_coef_filter_type_sel {
  58         SCL_COEF_LUMA_VERT_FILTER = 0,
  59         SCL_COEF_LUMA_HORZ_FILTER = 1,
  60         SCL_COEF_CHROMA_VERT_FILTER = 2,
  61         SCL_COEF_CHROMA_HORZ_FILTER = 3,
  62         SCL_COEF_ALPHA_VERT_FILTER = 4,
  63         SCL_COEF_ALPHA_HORZ_FILTER = 5
  64 };
  65
  66 enum dscl_autocal_mode {
  67         AUTOCAL_MODE_OFF = 0,
  68
  69         /* Autocal calculate the scaling ratio and initial phase and the
  70          * DSCL_MODE_SEL must be set to 1
  71          */
  72         AUTOCAL_MODE_AUTOSCALE = 1,
  73         /* Autocal perform auto centering without replication and the
  74          * DSCL_MODE_SEL must be set to 0
  75          */
  76         AUTOCAL_MODE_AUTOCENTER = 2,
  77         /* Autocal perform auto centering and auto replication and the
  78          * DSCL_MODE_SEL must be set to 0
  79          */
  80         AUTOCAL_MODE_AUTOREPLICATE = 3
  81 };
  82
  83 enum dscl_mode_sel {
  84         DSCL_MODE_SCALING_444_BYPASS = 0,
  85         DSCL_MODE_SCALING_444_RGB_ENABLE = 1,
  86         DSCL_MODE_SCALING_444_YCBCR_ENABLE = 2,
  87         DSCL_MODE_SCALING_420_YCBCR_ENABLE = 3,
  88         DSCL_MODE_SCALING_420_LUMA_BYPASS = 4,
  89         DSCL_MODE_SCALING_420_CHROMA_BYPASS = 5,
  90         DSCL_MODE_DSCL_BYPASS = 6
  91 };
  92
  93 enum gamut_remap_select {
  94         GAMUT_REMAP_BYPASS = 0,
  95         GAMUT_REMAP_COEFF,
  96         GAMUT_REMAP_COMA_COEFF,
  97         GAMUT_REMAP_COMB_COEFF
  98 };
  99
 100 static const struct dcn10_input_csc_matrix dcn10_input_csc_matrix[] = {
 101         {COLOR_SPACE_SRGB,
 102                 {0x2000, 0, 0, 0, 0, 0x2000, 0, 0, 0, 0, 0x2000, 0} },
 103         {COLOR_SPACE_SRGB_LIMITED,
 104                 {0x2000, 0, 0, 0, 0, 0x2000, 0, 0, 0, 0, 0x2000, 0} },
 105         {COLOR_SPACE_YCBCR601,
 106                 {0x2cdd, 0x2000, 0, 0xe991, 0xe926, 0x2000, 0xf4fd, 0x10ef,
 107                                                 0, 0x2000, 0x38b4, 0xe3a6} },
 108         {COLOR_SPACE_YCBCR601_LIMITED,
 109                 {0x3353, 0x2568, 0, 0xe400, 0xe5dc, 0x2568, 0xf367, 0x1108,
 110                                                 0, 0x2568, 0x40de, 0xdd3a} },
 111         {COLOR_SPACE_YCBCR709,
 112                 {0x3265, 0x2000, 0, 0xe6ce, 0xf105, 0x2000, 0xfa01, 0xa7d, 0,
 113                                                 0x2000, 0x3b61, 0xe24f} },
 114
 115         {COLOR_SPACE_YCBCR709_LIMITED,
 116                 {0x39a6, 0x2568, 0, 0xe0d6, 0xeedd, 0x2568, 0xf925, 0x9a8, 0,
 117                                                 0x2568, 0x43ee, 0xdbb2} }
 118 };
 119
 120
 121
 122 static void program_gamut_remap(
 123                 struct dcn10_dpp *dpp,
 124                 const uint16_t *regval,
 125                 enum gamut_remap_select select)
 126 {
 127         uint16_t selection = 0;
 128         struct color_matrices_reg gam_regs;
 129
 130         if (regval == NULL || select == GAMUT_REMAP_BYPASS) {
 131                 REG_SET(CM_GAMUT_REMAP_CONTROL, 0,
 132                                 CM_GAMUT_REMAP_MODE, 0);
 133                 return;
 134         }
 135         switch (select) {
 136         case GAMUT_REMAP_COEFF:
 137                 selection = 1;
 138                 break;
 139         case GAMUT_REMAP_COMA_COEFF:
 140                 selection = 2;
 141                 break;
 142         case GAMUT_REMAP_COMB_COEFF:
 143                 selection = 3;
 144                 break;
 145         default:
 146                 break;
 147         }
 148
 149         gam_regs.shifts.csc_c11 = dpp->tf_shift->CM_GAMUT_REMAP_C11;
 150         gam_regs.masks.csc_c11  = dpp->tf_mask->CM_GAMUT_REMAP_C11;
 151         gam_regs.shifts.csc_c12 = dpp->tf_shift->CM_GAMUT_REMAP_C12;
 152         gam_regs.masks.csc_c12 = dpp->tf_mask->CM_GAMUT_REMAP_C12;
 153
 154
 155         if (select == GAMUT_REMAP_COEFF) {
 156                 gam_regs.csc_c11_c12 = REG(CM_GAMUT_REMAP_C11_C12);
 157                 gam_regs.csc_c33_c34 = REG(CM_GAMUT_REMAP_C33_C34);
 158
 159                 cm_helper_program_color_matrices(
 160                                 dpp->base.ctx,
 161                                 regval,
 162                                 &gam_regs);
 163
 164         } else  if (select == GAMUT_REMAP_COMA_COEFF) {
 165
 166                 gam_regs.csc_c11_c12 = REG(CM_COMA_C11_C12);
 167                 gam_regs.csc_c33_c34 = REG(CM_COMA_C33_C34);
 168
 169                 cm_helper_program_color_matrices(
 170                                 dpp->base.ctx,
 171                                 regval,
 172                                 &gam_regs);
 173
 174         } else {
 175
 176                 gam_regs.csc_c11_c12 = REG(CM_COMB_C11_C12);
 177                 gam_regs.csc_c33_c34 = REG(CM_COMB_C33_C34);
 178
 179                 cm_helper_program_color_matrices(
 180                                 dpp->base.ctx,
 181                                 regval,
 182                                 &gam_regs);
 183         }
 184
 185         REG_SET(
 186                         CM_GAMUT_REMAP_CONTROL, 0,
 187                         CM_GAMUT_REMAP_MODE, selection);
 188
 189 }
 190
 191 void dpp1_cm_set_gamut_remap(
 192         struct dpp *dpp_base,
 193         const struct dpp_grph_csc_adjustment *adjust)
 194 {
 195         struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base);
 196
 197         if (adjust->gamut_adjust_type != GRAPHICS_GAMUT_ADJUST_TYPE_SW)
 198                 /* Bypass if type is bypass or hw */
 199                 program_gamut_remap(dpp, NULL, GAMUT_REMAP_BYPASS);
 200         else {
 201                 struct fixed31_32 arr_matrix[12];
 202                 uint16_t arr_reg_val[12];
 203
 204                 arr_matrix[0] = adjust->temperature_matrix[0];
 205                 arr_matrix[1] = adjust->temperature_matrix[1];
 206                 arr_matrix[2] = adjust->temperature_matrix[2];
 207                 arr_matrix[3] = dal_fixed31_32_zero;
 208
 209                 arr_matrix[4] = adjust->temperature_matrix[3];
 210                 arr_matrix[5] = adjust->temperature_matrix[4];
 211                 arr_matrix[6] = adjust->temperature_matrix[5];
 212                 arr_matrix[7] = dal_fixed31_32_zero;
 213
 214                 arr_matrix[8] = adjust->temperature_matrix[6];
 215                 arr_matrix[9] = adjust->temperature_matrix[7];
 216                 arr_matrix[10] = adjust->temperature_matrix[8];
 217                 arr_matrix[11] = dal_fixed31_32_zero;
 218
 219                 convert_float_matrix(
 220                         arr_reg_val, arr_matrix, 12);
 221
 222                 program_gamut_remap(dpp, arr_reg_val, GAMUT_REMAP_COEFF);
 223         }
 224 }
 225
 226 void dpp1_cm_set_output_csc_default(
 227                 struct dpp *dpp_base,
 228                 const struct default_adjustment *default_adjust)
 229 {
 230
 231         struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base);
 232         uint32_t ocsc_mode = 0;
 233
 234         if (default_adjust != NULL) {
 235                 switch (default_adjust->out_color_space) {
 236                 case COLOR_SPACE_SRGB:
 237                 case COLOR_SPACE_2020_RGB_FULLRANGE:
 238                         ocsc_mode = 0;
 239                         break;
 240                 case COLOR_SPACE_SRGB_LIMITED:
 241                 case COLOR_SPACE_2020_RGB_LIMITEDRANGE:
 242                         ocsc_mode = 1;
 243                         break;
 244                 case COLOR_SPACE_YCBCR601:
 245                 case COLOR_SPACE_YCBCR601_LIMITED:
 246                         ocsc_mode = 2;
 247                         break;
 248                 case COLOR_SPACE_YCBCR709:
 249                 case COLOR_SPACE_YCBCR709_LIMITED:
 250                 case COLOR_SPACE_2020_YCBCR:
 251                         ocsc_mode = 3;
 252                         break;
 253                 case COLOR_SPACE_UNKNOWN:
 254                 default:
 255                         break;
 256                 }
 257         }
 258
 259         REG_SET(CM_OCSC_CONTROL, 0, CM_OCSC_MODE, ocsc_mode);
 260
 261 }
 262
 263 static void dpp1_cm_get_reg_field(
 264                 struct dcn10_dpp *dpp,
 265                 struct xfer_func_reg *reg)
 266 {
 267         reg->shifts.exp_region0_lut_offset = dpp->tf_shift->CM_RGAM_RAMA_EXP_REGION0_LUT_OFFSET;
 268         reg->masks.exp_region0_lut_offset = dpp->tf_mask->CM_RGAM_RAMA_EXP_REGION0_LUT_OFFSET;
 269         reg->shifts.exp_region0_num_segments = dpp->tf_shift->CM_RGAM_RAMA_EXP_REGION0_NUM_SEGMENTS;
 270         reg->masks.exp_region0_num_segments = dpp->tf_mask->CM_RGAM_RAMA_EXP_REGION0_NUM_SEGMENTS;
 271         reg->shifts.exp_region1_lut_offset = dpp->tf_shift->CM_RGAM_RAMA_EXP_REGION1_LUT_OFFSET;
 272         reg->masks.exp_region1_lut_offset = dpp->tf_mask->CM_RGAM_RAMA_EXP_REGION1_LUT_OFFSET;
 273         reg->shifts.exp_region1_num_segments = dpp->tf_shift->CM_RGAM_RAMA_EXP_REGION1_NUM_SEGMENTS;
 274         reg->masks.exp_region1_num_segments = dpp->tf_mask->CM_RGAM_RAMA_EXP_REGION1_NUM_SEGMENTS;
 275
 276         reg->shifts.field_region_end = dpp->tf_shift->CM_RGAM_RAMB_EXP_REGION_END_B;
 277         reg->masks.field_region_end = dpp->tf_mask->CM_RGAM_RAMB_EXP_REGION_END_B;
 278         reg->shifts.field_region_end_slope = dpp->tf_shift->CM_RGAM_RAMB_EXP_REGION_END_SLOPE_B;
 279         reg->masks.field_region_end_slope = dpp->tf_mask->CM_RGAM_RAMB_EXP_REGION_END_SLOPE_B;
 280         reg->shifts.field_region_end_base = dpp->tf_shift->CM_RGAM_RAMB_EXP_REGION_END_BASE_B;
 281         reg->masks.field_region_end_base = dpp->tf_mask->CM_RGAM_RAMB_EXP_REGION_END_BASE_B;
 282         reg->shifts.field_region_linear_slope = dpp->tf_shift->CM_RGAM_RAMB_EXP_REGION_LINEAR_SLOPE_B;
 283         reg->masks.field_region_linear_slope = dpp->tf_mask->CM_RGAM_RAMB_EXP_REGION_LINEAR_SLOPE_B;
 284         reg->shifts.exp_region_start = dpp->tf_shift->CM_RGAM_RAMB_EXP_REGION_START_B;
 285         reg->masks.exp_region_start = dpp->tf_mask->CM_RGAM_RAMB_EXP_REGION_START_B;
 286         reg->shifts.exp_resion_start_segment = dpp->tf_shift->CM_RGAM_RAMB_EXP_REGION_START_SEGMENT_B;
 287         reg->masks.exp_resion_start_segment = dpp->tf_mask->CM_RGAM_RAMB_EXP_REGION_START_SEGMENT_B;
 288 }
 289
 290 static void dpp1_cm_program_color_matrix(
 291                 struct dcn10_dpp *dpp,
 292                 const struct out_csc_color_matrix *tbl_entry)
 293 {
 294         uint32_t mode;
 295         struct color_matrices_reg gam_regs;
 296
 297         REG_GET(CM_OCSC_CONTROL, CM_OCSC_MODE, &mode);
 298
 299         if (tbl_entry == NULL) {
 300                 BREAK_TO_DEBUGGER();
 301                 return;
 302         }
 303
 304         gam_regs.shifts.csc_c11 = dpp->tf_shift->CM_OCSC_C11;
 305         gam_regs.masks.csc_c11  = dpp->tf_mask->CM_OCSC_C11;
 306         gam_regs.shifts.csc_c12 = dpp->tf_shift->CM_OCSC_C12;
 307         gam_regs.masks.csc_c12 = dpp->tf_mask->CM_OCSC_C12;
 308
 309         if (mode == 4) {
 310
 311                 gam_regs.csc_c11_c12 = REG(CM_OCSC_C11_C12);
 312                 gam_regs.csc_c33_c34 = REG(CM_OCSC_C33_C34);
 313
 314                 cm_helper_program_color_matrices(
 315                                 dpp->base.ctx,
 316                                 tbl_entry->regval,
 317                                 &gam_regs);
 318
 319         } else {
 320
 321                 gam_regs.csc_c11_c12 = REG(CM_COMB_C11_C12);
 322                 gam_regs.csc_c33_c34 = REG(CM_COMB_C33_C34);
 323
 324                 cm_helper_program_color_matrices(
 325                                 dpp->base.ctx,
 326                                 tbl_entry->regval,
 327                                 &gam_regs);
 328         }
 329 }
 330
 331 void dpp1_cm_set_output_csc_adjustment(
 332                 struct dpp *dpp_base,
 333                 const struct out_csc_color_matrix *tbl_entry)
 334 {
 335         struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base);
 336         //enum csc_color_mode config = CSC_COLOR_MODE_GRAPHICS_OUTPUT_CSC;
 337         uint32_t ocsc_mode = 4;
 338
 339         /**
 340         *if (tbl_entry != NULL) {
 341         *       switch (tbl_entry->color_space) {
 342         *       case COLOR_SPACE_SRGB:
 343         *       case COLOR_SPACE_2020_RGB_FULLRANGE:
 344         *               ocsc_mode = 0;
 345         *               break;
 346         *       case COLOR_SPACE_SRGB_LIMITED:
 347         *       case COLOR_SPACE_2020_RGB_LIMITEDRANGE:
 348         *               ocsc_mode = 1;
 349         *               break;
 350         *       case COLOR_SPACE_YCBCR601:
 351         *       case COLOR_SPACE_YCBCR601_LIMITED:
 352         *               ocsc_mode = 2;
 353         *               break;
 354         *       case COLOR_SPACE_YCBCR709:
 355         *       case COLOR_SPACE_YCBCR709_LIMITED:
 356         *       case COLOR_SPACE_2020_YCBCR:
 357         *               ocsc_mode = 3;
 358         *               break;
 359         *       case COLOR_SPACE_UNKNOWN:
 360         *       default:
 361         *               break;
 362         *       }
 363         *}
 364         */
 365
 366         REG_SET(CM_OCSC_CONTROL, 0, CM_OCSC_MODE, ocsc_mode);
 367         dpp1_cm_program_color_matrix(dpp, tbl_entry);
 368 }
 369
 370 void dpp1_cm_power_on_regamma_lut(
 371         struct dpp *dpp_base,
 372         bool power_on)
 373 {
 374         struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base);
 375         REG_SET(CM_MEM_PWR_CTRL, 0,
 376                         RGAM_MEM_PWR_FORCE, power_on == true ? 0:1);
 377
 378 }
 379
 380 void dpp1_cm_program_regamma_lut(
 381                 struct dpp *dpp_base,
 382                 const struct pwl_result_data *rgb,
 383                 uint32_t num)
 384 {
 385         uint32_t i;
 386         struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base);
 387         for (i = 0 ; i < num; i++) {
 388                 REG_SET(CM_RGAM_LUT_DATA, 0, CM_RGAM_LUT_DATA, rgb[i].red_reg);
 389                 REG_SET(CM_RGAM_LUT_DATA, 0, CM_RGAM_LUT_DATA, rgb[i].green_reg);
 390                 REG_SET(CM_RGAM_LUT_DATA, 0, CM_RGAM_LUT_DATA, rgb[i].blue_reg);
 391
 392                 REG_SET(CM_RGAM_LUT_DATA, 0,
 393                                 CM_RGAM_LUT_DATA, rgb[i].delta_red_reg);
 394                 REG_SET(CM_RGAM_LUT_DATA, 0,
 395                                 CM_RGAM_LUT_DATA, rgb[i].delta_green_reg);
 396                 REG_SET(CM_RGAM_LUT_DATA, 0,
 397                                 CM_RGAM_LUT_DATA, rgb[i].delta_blue_reg);
 398
 399         }
 400
 401 }
 402
 403 void dpp1_cm_configure_regamma_lut(
 404                 struct dpp *dpp_base,
 405                 bool is_ram_a)
 406 {
 407         struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base);
 408
 409         REG_UPDATE(CM_RGAM_LUT_WRITE_EN_MASK,
 410                         CM_RGAM_LUT_WRITE_EN_MASK, 7);
 411         REG_UPDATE(CM_RGAM_LUT_WRITE_EN_MASK,
 412                         CM_RGAM_LUT_WRITE_SEL, is_ram_a == true ? 0:1);
 413         REG_SET(CM_RGAM_LUT_INDEX, 0, CM_RGAM_LUT_INDEX, 0);
 414 }
 415
 416 /*program re gamma RAM A*/
 417 void dpp1_cm_program_regamma_luta_settings(
 418                 struct dpp *dpp_base,
 419                 const struct pwl_params *params)
 420 {
 421         struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base);
 422         struct xfer_func_reg gam_regs;
 423
 424         dpp1_cm_get_reg_field(dpp, &gam_regs);
 425
 426         gam_regs.start_cntl_b = REG(CM_RGAM_RAMA_START_CNTL_B);
 427         gam_regs.start_cntl_g = REG(CM_RGAM_RAMA_START_CNTL_G);
 428         gam_regs.start_cntl_r = REG(CM_RGAM_RAMA_START_CNTL_R);
 429         gam_regs.start_slope_cntl_b = REG(CM_RGAM_RAMA_SLOPE_CNTL_B);
 430         gam_regs.start_slope_cntl_g = REG(CM_RGAM_RAMA_SLOPE_CNTL_G);
 431         gam_regs.start_slope_cntl_r = REG(CM_RGAM_RAMA_SLOPE_CNTL_R);
 432         gam_regs.start_end_cntl1_b = REG(CM_RGAM_RAMA_END_CNTL1_B);
 433         gam_regs.start_end_cntl2_b = REG(CM_RGAM_RAMA_END_CNTL2_B);
 434         gam_regs.start_end_cntl1_g = REG(CM_RGAM_RAMA_END_CNTL1_G);
 435         gam_regs.start_end_cntl2_g = REG(CM_RGAM_RAMA_END_CNTL2_G);
 436         gam_regs.start_end_cntl1_r = REG(CM_RGAM_RAMA_END_CNTL1_R);
 437         gam_regs.start_end_cntl2_r = REG(CM_RGAM_RAMA_END_CNTL2_R);
 438         gam_regs.region_start = REG(CM_RGAM_RAMA_REGION_0_1);
 439         gam_regs.region_end = REG(CM_RGAM_RAMA_REGION_32_33);
 440
 441         cm_helper_program_xfer_func(dpp->base.ctx, params, &gam_regs);
 442
 443 }
 444
 445 /*program re gamma RAM B*/
 446 void dpp1_cm_program_regamma_lutb_settings(
 447                 struct dpp *dpp_base,
 448                 const struct pwl_params *params)
 449 {
 450         struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base);
 451         struct xfer_func_reg gam_regs;
 452
 453         dpp1_cm_get_reg_field(dpp, &gam_regs);
 454
 455         gam_regs.start_cntl_b = REG(CM_RGAM_RAMB_START_CNTL_B);
 456         gam_regs.start_cntl_g = REG(CM_RGAM_RAMB_START_CNTL_G);
 457         gam_regs.start_cntl_r = REG(CM_RGAM_RAMB_START_CNTL_R);
 458         gam_regs.start_slope_cntl_b = REG(CM_RGAM_RAMB_SLOPE_CNTL_B);
 459         gam_regs.start_slope_cntl_g = REG(CM_RGAM_RAMB_SLOPE_CNTL_G);
 460         gam_regs.start_slope_cntl_r = REG(CM_RGAM_RAMB_SLOPE_CNTL_R);
 461         gam_regs.start_end_cntl1_b = REG(CM_RGAM_RAMB_END_CNTL1_B);
 462         gam_regs.start_end_cntl2_b = REG(CM_RGAM_RAMB_END_CNTL2_B);
 463         gam_regs.start_end_cntl1_g = REG(CM_RGAM_RAMB_END_CNTL1_G);
 464         gam_regs.start_end_cntl2_g = REG(CM_RGAM_RAMB_END_CNTL2_G);
 465         gam_regs.start_end_cntl1_r = REG(CM_RGAM_RAMB_END_CNTL1_R);
 466         gam_regs.start_end_cntl2_r = REG(CM_RGAM_RAMB_END_CNTL2_R);
 467         gam_regs.region_start = REG(CM_RGAM_RAMB_REGION_0_1);
 468         gam_regs.region_end = REG(CM_RGAM_RAMB_REGION_32_33);
 469
 470         cm_helper_program_xfer_func(dpp->base.ctx, params, &gam_regs);
 471 }
 472
 473 void dpp1_program_input_csc(
 474                 struct dpp *dpp_base,
 475                 enum dc_color_space color_space,
 476                 enum dcn10_input_csc_select select)
 477 {
 478         struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base);
 479         int i;
 480         int arr_size = sizeof(dcn10_input_csc_matrix)/sizeof(struct dcn10_input_csc_matrix);
 481         const uint16_t *regval = NULL;
 482         uint32_t selection = 1;
 483         struct color_matrices_reg gam_regs;
 484
 485         if (select == INPUT_CSC_SELECT_BYPASS) {
 486                 REG_SET(CM_ICSC_CONTROL, 0, CM_ICSC_MODE, 0);
 487                 return;
 488         }
 489
 490         for (i = 0; i < arr_size; i++)
 491                 if (dcn10_input_csc_matrix[i].color_space == color_space) {
 492                         regval = dcn10_input_csc_matrix[i].regval;
 493                         break;
 494                 }
 495
 496         if (regval == NULL) {
 497                 BREAK_TO_DEBUGGER();
 498                 return;
 499         }
 500
 501         if (select == INPUT_CSC_SELECT_COMA)
 502                 selection = 2;
 503         REG_SET(CM_ICSC_CONTROL, 0,
 504                         CM_ICSC_MODE, selection);
 505
 506         gam_regs.shifts.csc_c11 = dpp->tf_shift->CM_ICSC_C11;
 507         gam_regs.masks.csc_c11  = dpp->tf_mask->CM_ICSC_C11;
 508         gam_regs.shifts.csc_c12 = dpp->tf_shift->CM_ICSC_C12;
 509         gam_regs.masks.csc_c12 = dpp->tf_mask->CM_ICSC_C12;
 510
 511
 512         if (select == INPUT_CSC_SELECT_ICSC) {
 513
 514                 gam_regs.csc_c11_c12 = REG(CM_ICSC_C11_C12);
 515                 gam_regs.csc_c33_c34 = REG(CM_ICSC_C33_C34);
 516
 517                 cm_helper_program_color_matrices(
 518                                 dpp->base.ctx,
 519                                 regval,
 520                                 &gam_regs);
 521         } else {
 522
 523                 gam_regs.csc_c11_c12 = REG(CM_COMA_C11_C12);
 524                 gam_regs.csc_c33_c34 = REG(CM_COMA_C33_C34);
 525
 526                 cm_helper_program_color_matrices(
 527                                 dpp->base.ctx,
 528                                 regval,
 529                                 &gam_regs);
 530         }
 531 }
 532
 533 /*program de gamma RAM B*/
 534 void dpp1_program_degamma_lutb_settings(
 535                 struct dpp *dpp_base,
 536                 const struct pwl_params *params)
 537 {
 538         struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base);
 539         struct xfer_func_reg gam_regs;
 540
 541         dpp1_cm_get_reg_field(dpp, &gam_regs);
 542
 543         gam_regs.start_cntl_b = REG(CM_DGAM_RAMB_START_CNTL_B);
 544         gam_regs.start_cntl_g = REG(CM_DGAM_RAMB_START_CNTL_G);
 545         gam_regs.start_cntl_r = REG(CM_DGAM_RAMB_START_CNTL_R);
 546         gam_regs.start_slope_cntl_b = REG(CM_DGAM_RAMB_SLOPE_CNTL_B);
 547         gam_regs.start_slope_cntl_g = REG(CM_DGAM_RAMB_SLOPE_CNTL_G);
 548         gam_regs.start_slope_cntl_r = REG(CM_DGAM_RAMB_SLOPE_CNTL_R);
 549         gam_regs.start_end_cntl1_b = REG(CM_DGAM_RAMB_END_CNTL1_B);
 550         gam_regs.start_end_cntl2_b = REG(CM_DGAM_RAMB_END_CNTL2_B);
 551         gam_regs.start_end_cntl1_g = REG(CM_DGAM_RAMB_END_CNTL1_G);
 552         gam_regs.start_end_cntl2_g = REG(CM_DGAM_RAMB_END_CNTL2_G);
 553         gam_regs.start_end_cntl1_r = REG(CM_DGAM_RAMB_END_CNTL1_R);
 554         gam_regs.start_end_cntl2_r = REG(CM_DGAM_RAMB_END_CNTL2_R);
 555         gam_regs.region_start = REG(CM_DGAM_RAMB_REGION_0_1);
 556         gam_regs.region_end = REG(CM_DGAM_RAMB_REGION_14_15);
 557
 558
 559         cm_helper_program_xfer_func(dpp->base.ctx, params, &gam_regs);
 560 }
 561
 562 /*program de gamma RAM A*/
 563 void dpp1_program_degamma_luta_settings(
 564                 struct dpp *dpp_base,
 565                 const struct pwl_params *params)
 566 {
 567         struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base);
 568         struct xfer_func_reg gam_regs;
 569
 570         dpp1_cm_get_reg_field(dpp, &gam_regs);
 571
 572         gam_regs.start_cntl_b = REG(CM_DGAM_RAMA_START_CNTL_B);
 573         gam_regs.start_cntl_g = REG(CM_DGAM_RAMA_START_CNTL_G);
 574         gam_regs.start_cntl_r = REG(CM_DGAM_RAMA_START_CNTL_R);
 575         gam_regs.start_slope_cntl_b = REG(CM_DGAM_RAMA_SLOPE_CNTL_B);
 576         gam_regs.start_slope_cntl_g = REG(CM_DGAM_RAMA_SLOPE_CNTL_G);
 577         gam_regs.start_slope_cntl_r = REG(CM_DGAM_RAMA_SLOPE_CNTL_R);
 578         gam_regs.start_end_cntl1_b = REG(CM_DGAM_RAMA_END_CNTL1_B);
 579         gam_regs.start_end_cntl2_b = REG(CM_DGAM_RAMA_END_CNTL2_B);
 580         gam_regs.start_end_cntl1_g = REG(CM_DGAM_RAMA_END_CNTL1_G);
 581         gam_regs.start_end_cntl2_g = REG(CM_DGAM_RAMA_END_CNTL2_G);
 582         gam_regs.start_end_cntl1_r = REG(CM_DGAM_RAMA_END_CNTL1_R);
 583         gam_regs.start_end_cntl2_r = REG(CM_DGAM_RAMA_END_CNTL2_R);
 584         gam_regs.region_start = REG(CM_DGAM_RAMA_REGION_0_1);
 585         gam_regs.region_end = REG(CM_DGAM_RAMA_REGION_14_15);
 586
 587         cm_helper_program_xfer_func(dpp->base.ctx, params, &gam_regs);
 588 }
 589
 590 void dpp1_power_on_degamma_lut(
 591                 struct dpp *dpp_base,
 592         bool power_on)
 593 {
 594         struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base);
 595
 596         REG_SET(CM_MEM_PWR_CTRL, 0,
 597                         SHARED_MEM_PWR_DIS, power_on == true ? 0:1);
 598
 599 }
 600
 601 static void dpp1_enable_cm_block(
 602                 struct dpp *dpp_base)
 603 {
 604         struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base);
 605
 606         REG_UPDATE(CM_CMOUT_CONTROL, CM_CMOUT_ROUND_TRUNC_MODE, 8);
 607         REG_UPDATE(CM_CONTROL, CM_BYPASS_EN, 0);
 608 }
 609
 610 void dpp1_set_degamma(
 611                 struct dpp *dpp_base,
 612                 enum ipp_degamma_mode mode)
 613 {
 614         struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base);
 615         dpp1_enable_cm_block(dpp_base);
 616
 617         switch (mode) {
 618         case IPP_DEGAMMA_MODE_BYPASS:
 619                 /* Setting de gamma bypass for now */
 620                 REG_UPDATE(CM_DGAM_CONTROL, CM_DGAM_LUT_MODE, 0);
 621                 break;
 622         case IPP_DEGAMMA_MODE_HW_sRGB:
 623                 REG_UPDATE(CM_DGAM_CONTROL, CM_DGAM_LUT_MODE, 1);
 624                 break;
 625         case IPP_DEGAMMA_MODE_HW_xvYCC:
 626                 REG_UPDATE(CM_DGAM_CONTROL, CM_DGAM_LUT_MODE, 2);
 627                         break;
 628         default:
 629                 BREAK_TO_DEBUGGER();
 630                 break;
 631         }
 632 }
 633
 634 void dpp1_degamma_ram_select(
 635                 struct dpp *dpp_base,
 636                                                         bool use_ram_a)
 637 {
 638         struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base);
 639
 640         if (use_ram_a)
 641                 REG_UPDATE(CM_DGAM_CONTROL, CM_DGAM_LUT_MODE, 3);
 642         else
 643                 REG_UPDATE(CM_DGAM_CONTROL, CM_DGAM_LUT_MODE, 4);
 644
 645 }
 646
 647 static bool dpp1_degamma_ram_inuse(
 648                 struct dpp *dpp_base,
 649                                                         bool *ram_a_inuse)
 650 {
 651         bool ret = false;
 652         uint32_t status_reg = 0;
 653         struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base);
 654
 655         REG_GET(CM_IGAM_LUT_RW_CONTROL, CM_IGAM_DGAM_CONFIG_STATUS,
 656                         &status_reg);
 657
 658         if (status_reg == 9) {
 659                 *ram_a_inuse = true;
 660                 ret = true;
 661         } else if (status_reg == 10) {
 662                 *ram_a_inuse = false;
 663                 ret = true;
 664         }
 665         return ret;
 666 }
 667
 668 void dpp1_program_degamma_lut(
 669                 struct dpp *dpp_base,
 670                 const struct pwl_result_data *rgb,
 671                 uint32_t num,
 672                 bool is_ram_a)
 673 {
 674         uint32_t i;
 675
 676         struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base);
 677         REG_UPDATE(CM_IGAM_LUT_RW_CONTROL, CM_IGAM_LUT_HOST_EN, 0);
 678         REG_UPDATE(CM_DGAM_LUT_WRITE_EN_MASK,
 679                                    CM_DGAM_LUT_WRITE_EN_MASK, 7);
 680         REG_UPDATE(CM_DGAM_LUT_WRITE_EN_MASK, CM_DGAM_LUT_WRITE_SEL,
 681                                         is_ram_a == true ? 0:1);
 682
 683         REG_SET(CM_DGAM_LUT_INDEX, 0, CM_DGAM_LUT_INDEX, 0);
 684         for (i = 0 ; i < num; i++) {
 685                 REG_SET(CM_DGAM_LUT_DATA, 0, CM_DGAM_LUT_DATA, rgb[i].red_reg);
 686                 REG_SET(CM_DGAM_LUT_DATA, 0, CM_DGAM_LUT_DATA, rgb[i].green_reg);
 687                 REG_SET(CM_DGAM_LUT_DATA, 0, CM_DGAM_LUT_DATA, rgb[i].blue_reg);
 688
 689                 REG_SET(CM_DGAM_LUT_DATA, 0,
 690                                 CM_DGAM_LUT_DATA, rgb[i].delta_red_reg);
 691                 REG_SET(CM_DGAM_LUT_DATA, 0,
 692                                 CM_DGAM_LUT_DATA, rgb[i].delta_green_reg);
 693                 REG_SET(CM_DGAM_LUT_DATA, 0,
 694                                 CM_DGAM_LUT_DATA, rgb[i].delta_blue_reg);
 695         }
 696 }
 697
 698 void dpp1_set_degamma_pwl(struct dpp *dpp_base,
 699                                                                  const struct pwl_params *params)
 700 {
 701         bool is_ram_a = true;
 702
 703         dpp1_power_on_degamma_lut(dpp_base, true);
 704         dpp1_enable_cm_block(dpp_base);
 705         dpp1_degamma_ram_inuse(dpp_base, &is_ram_a);
 706         if (is_ram_a == true)
 707                 dpp1_program_degamma_lutb_settings(dpp_base, params);
 708         else
 709                 dpp1_program_degamma_luta_settings(dpp_base, params);
 710
 711         dpp1_program_degamma_lut(dpp_base, params->rgb_resulted,
 712                                                         params->hw_points_num, !is_ram_a);
 713         dpp1_degamma_ram_select(dpp_base, !is_ram_a);
 714 }
 715
 716 void dpp1_full_bypass(struct dpp *dpp_base)
 717 {
 718         struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base);
 719
 720         /* Input pixel format: ARGB8888 */
 721         REG_SET(CNVC_SURFACE_PIXEL_FORMAT, 0,
 722                         CNVC_SURFACE_PIXEL_FORMAT, 0x8);
 723
 724         /* Zero expansion */
 725         REG_SET_3(FORMAT_CONTROL, 0,
 726                         CNVC_BYPASS, 0,
 727                         FORMAT_CONTROL__ALPHA_EN, 0,
 728                         FORMAT_EXPANSION_MODE, 0);
 729
 730         /* COLOR_KEYER_CONTROL.COLOR_KEYER_EN = 0 this should be default */
 731         if (dpp->tf_mask->CM_BYPASS_EN)
 732                 REG_SET(CM_CONTROL, 0, CM_BYPASS_EN, 1);
 733
 734         /* Setting degamma bypass for now */
 735         REG_SET(CM_DGAM_CONTROL, 0, CM_DGAM_LUT_MODE, 0);
 736 }
 737
 738 static bool dpp1_ingamma_ram_inuse(struct dpp *dpp_base,
 739                                                         bool *ram_a_inuse)
 740 {
 741         bool in_use = false;
 742         uint32_t status_reg = 0;
 743         struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base);
 744
 745         REG_GET(CM_IGAM_LUT_RW_CONTROL, CM_IGAM_DGAM_CONFIG_STATUS,
 746                                 &status_reg);
 747
 748         // 1 => IGAM_RAMA, 3 => IGAM_RAMA & DGAM_ROMA, 4 => IGAM_RAMA & DGAM_ROMB
 749         if (status_reg == 1 || status_reg == 3 || status_reg == 4) {
 750                 *ram_a_inuse = true;
 751                 in_use = true;
 752         // 2 => IGAM_RAMB, 5 => IGAM_RAMB & DGAM_ROMA, 6 => IGAM_RAMB & DGAM_ROMB
 753         } else if (status_reg == 2 || status_reg == 5 || status_reg == 6) {
 754                 *ram_a_inuse = false;
 755                 in_use = true;
 756         }
 757         return in_use;
 758 }
 759
 760 /*
 761  * Input gamma LUT currently supports 256 values only. This means input color
 762  * can have a maximum of 8 bits per channel (= 256 possible values) in order to
 763  * have a one-to-one mapping with the LUT. Truncation will occur with color
 764  * values greater than 8 bits.
 765  *
 766  * In the future, this function should support additional input gamma methods,
 767  * such as piecewise linear mapping, and input gamma bypass.
 768  */
 769 void dpp1_program_input_lut(
 770                 struct dpp *dpp_base,
 771                 const struct dc_gamma *gamma)
 772 {
 773         int i;
 774         struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base);
 775         bool rama_occupied = false;
 776         uint32_t ram_num;
 777         // Power on LUT memory.
 778         REG_SET(CM_MEM_PWR_CTRL, 0, SHARED_MEM_PWR_DIS, 1);
 779         dpp1_enable_cm_block(dpp_base);
 780         // Determine whether to use RAM A or RAM B
 781         dpp1_ingamma_ram_inuse(dpp_base, &rama_occupied);
 782         if (!rama_occupied)
 783                 REG_UPDATE(CM_IGAM_LUT_RW_CONTROL, CM_IGAM_LUT_SEL, 0);
 784         else
 785                 REG_UPDATE(CM_IGAM_LUT_RW_CONTROL, CM_IGAM_LUT_SEL, 1);
 786         // RW mode is 256-entry LUT
 787         REG_UPDATE(CM_IGAM_LUT_RW_CONTROL, CM_IGAM_LUT_RW_MODE, 0);
 788         // IGAM Input format should be 8 bits per channel.
 789         REG_UPDATE(CM_IGAM_CONTROL, CM_IGAM_INPUT_FORMAT, 0);
 790         // Do not mask any R,G,B values
 791         REG_UPDATE(CM_IGAM_LUT_RW_CONTROL, CM_IGAM_LUT_WRITE_EN_MASK, 7);
 792         // LUT-256, unsigned, integer, new u0.12 format
 793         REG_UPDATE_3(
 794                 CM_IGAM_CONTROL,
 795                 CM_IGAM_LUT_FORMAT_R, 3,
 796                 CM_IGAM_LUT_FORMAT_G, 3,
 797                 CM_IGAM_LUT_FORMAT_B, 3);
 798         // Start at index 0 of IGAM LUT
 799         REG_UPDATE(CM_IGAM_LUT_RW_INDEX, CM_IGAM_LUT_RW_INDEX, 0);
 800         for (i = 0; i < gamma->num_entries; i++) {
 801                 REG_SET(CM_IGAM_LUT_SEQ_COLOR, 0, CM_IGAM_LUT_SEQ_COLOR,
 802                                 dal_fixed31_32_round(
 803                                         gamma->entries.red[i]));
 804                 REG_SET(CM_IGAM_LUT_SEQ_COLOR, 0, CM_IGAM_LUT_SEQ_COLOR,
 805                                 dal_fixed31_32_round(
 806                                         gamma->entries.green[i]));
 807                 REG_SET(CM_IGAM_LUT_SEQ_COLOR, 0, CM_IGAM_LUT_SEQ_COLOR,
 808                                 dal_fixed31_32_round(
 809                                         gamma->entries.blue[i]));
 810         }
 811         // Power off LUT memory
 812         REG_SET(CM_MEM_PWR_CTRL, 0, SHARED_MEM_PWR_DIS, 0);
 813         // Enable IGAM LUT on ram we just wrote to. 2 => RAMA, 3 => RAMB
 814         REG_UPDATE(CM_IGAM_CONTROL, CM_IGAM_LUT_MODE, rama_occupied ? 3 : 2);
 815         REG_GET(CM_IGAM_CONTROL, CM_IGAM_LUT_MODE, &ram_num);
 816 }