drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

   1 /*
   2  * Copyright 2016 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: AMD
  23  *
  24  */
  25
  26 #include "dm_services.h"
  27 #include "core_types.h"
  28 #include "resource.h"
  29 #include "custom_float.h"
  30 #include "dcn10_hw_sequencer.h"
  31 #include "dce110/dce110_hw_sequencer.h"
  32 #include "dce/dce_hwseq.h"
  33 #include "abm.h"
  34 #include "dmcu.h"
  35 #include "dcn10_optc.h"
  36 #include "dcn10/dcn10_dpp.h"
  37 #include "dcn10/dcn10_mpc.h"
  38 #include "timing_generator.h"
  39 #include "opp.h"
  40 #include "ipp.h"
  41 #include "mpc.h"
  42 #include "reg_helper.h"
  43 #include "custom_float.h"
  44 #include "dcn10_hubp.h"
  45 #include "dcn10_hubbub.h"
  46 #include "dcn10_cm_common.h"
  47
  48 #define DC_LOGGER \
  49         ctx->logger
  50 #define CTX \
  51         hws->ctx
  52 #define REG(reg)\
  53         hws->regs->reg
  54
  55 #undef FN
  56 #define FN(reg_name, field_name) \
  57         hws->shifts->field_name, hws->masks->field_name
  58
  59 #define DTN_INFO_MICRO_SEC(ref_cycle) \
  60         print_microsec(dc_ctx, ref_cycle)
  61
  62 void print_microsec(struct dc_context *dc_ctx, uint32_t ref_cycle)
  63 {
  64         static const uint32_t ref_clk_mhz = 48;
  65         static const unsigned int frac = 10;
  66         uint32_t us_x10 = (ref_cycle * frac) / ref_clk_mhz;
  67
  68         DTN_INFO("%d.%d \t ",
  69                         us_x10 / frac,
  70                         us_x10 % frac);
  71 }
  72
  73
  74 static void log_mpc_crc(struct dc *dc)
  75 {
  76         struct dc_context *dc_ctx = dc->ctx;
  77         struct dce_hwseq *hws = dc->hwseq;
  78
  79         if (REG(MPC_CRC_RESULT_GB))
  80                 DTN_INFO("MPC_CRC_RESULT_GB:%d MPC_CRC_RESULT_C:%d MPC_CRC_RESULT_AR:%d\n",
  81                 REG_READ(MPC_CRC_RESULT_GB), REG_READ(MPC_CRC_RESULT_C), REG_READ(MPC_CRC_RESULT_AR));
  82         if (REG(DPP_TOP0_DPP_CRC_VAL_B_A))
  83                 DTN_INFO("DPP_TOP0_DPP_CRC_VAL_B_A:%d DPP_TOP0_DPP_CRC_VAL_R_G:%d\n",
  84                 REG_READ(DPP_TOP0_DPP_CRC_VAL_B_A), REG_READ(DPP_TOP0_DPP_CRC_VAL_R_G));
  85 }
  86
  87 void dcn10_log_hubbub_state(struct dc *dc)
  88 {
  89         struct dc_context *dc_ctx = dc->ctx;
  90         struct dcn_hubbub_wm wm;
  91         int i;
  92
  93         hubbub1_wm_read_state(dc->res_pool->hubbub, &wm);
  94
  95         DTN_INFO("HUBBUB WM: \t data_urgent \t pte_meta_urgent \t "
  96                         "sr_enter \t sr_exit \t dram_clk_change \n");
  97
  98         for (i = 0; i < 4; i++) {
  99                 struct dcn_hubbub_wm_set *s;
 100
 101                 s = &wm.sets[i];
 102                 DTN_INFO("WM_Set[%d]:\t ", s->wm_set);
 103                 DTN_INFO_MICRO_SEC(s->data_urgent);
 104                 DTN_INFO_MICRO_SEC(s->pte_meta_urgent);
 105                 DTN_INFO_MICRO_SEC(s->sr_enter);
 106                 DTN_INFO_MICRO_SEC(s->sr_exit);
 107                 DTN_INFO_MICRO_SEC(s->dram_clk_chanage);
 108                 DTN_INFO("\n");
 109         }
 110
 111         DTN_INFO("\n");
 112 }
 113
 114 void dcn10_log_hw_state(struct dc *dc)
 115 {
 116         struct dc_context *dc_ctx = dc->ctx;
 117         struct resource_pool *pool = dc->res_pool;
 118         int i;
 119
 120         DTN_INFO_BEGIN();
 121
 122         dcn10_log_hubbub_state(dc);
 123
 124         DTN_INFO("HUBP:\t format \t addr_hi \t width \t height \t "
 125                         "rotation \t mirror \t  sw_mode \t "
 126                         "dcc_en \t blank_en \t ttu_dis \t underflow \t "
 127                         "min_ttu_vblank \t qos_low_wm \t qos_high_wm \n");
 128
 129         for (i = 0; i < pool->pipe_count; i++) {
 130                 struct hubp *hubp = pool->hubps[i];
 131                 struct dcn_hubp_state s;
 132
 133                 hubp1_read_state(TO_DCN10_HUBP(hubp), &s);
 134
 135                 DTN_INFO("[%d]:\t %xh \t %xh \t %d \t %d \t "
 136                                 "%xh \t %xh \t %xh \t "
 137                                 "%d \t %d \t %d \t %xh \t",
 138                                 hubp->inst,
 139                                 s.pixel_format,
 140                                 s.inuse_addr_hi,
 141                                 s.viewport_width,
 142                                 s.viewport_height,
 143                                 s.rotation_angle,
 144                                 s.h_mirror_en,
 145                                 s.sw_mode,
 146                                 s.dcc_en,
 147                                 s.blank_en,
 148                                 s.ttu_disable,
 149                                 s.underflow_status);
 150                 DTN_INFO_MICRO_SEC(s.min_ttu_vblank);
 151                 DTN_INFO_MICRO_SEC(s.qos_level_low_wm);
 152                 DTN_INFO_MICRO_SEC(s.qos_level_high_wm);
 153                 DTN_INFO("\n");
 154         }
 155         DTN_INFO("\n");
 156
 157         DTN_INFO("OTG:\t v_bs \t v_be \t v_ss \t v_se \t vpol \t vmax \t vmin \t "
 158                         "h_bs \t h_be \t h_ss \t h_se \t hpol \t htot \t vtot \t underflow\n");
 159
 160         for (i = 0; i < pool->timing_generator_count; i++) {
 161                 struct timing_generator *tg = pool->timing_generators[i];
 162                 struct dcn_otg_state s = {0};
 163
 164                 optc1_read_otg_state(DCN10TG_FROM_TG(tg), &s);
 165
 166                 //only print if OTG master is enabled
 167                 if ((s.otg_enabled & 1) == 0)
 168                         continue;
 169
 170                 DTN_INFO("[%d]:\t %d \t %d \t %d \t %d \t "
 171                                 "%d \t %d \t %d \t %d \t %d \t %d \t "
 172                                 "%d \t %d \t %d \t %d \t %d \t ",
 173                                 tg->inst,
 174                                 s.v_blank_start,
 175                                 s.v_blank_end,
 176                                 s.v_sync_a_start,
 177                                 s.v_sync_a_end,
 178                                 s.v_sync_a_pol,
 179                                 s.v_total_max,
 180                                 s.v_total_min,
 181                                 s.h_blank_start,
 182                                 s.h_blank_end,
 183                                 s.h_sync_a_start,
 184                                 s.h_sync_a_end,
 185                                 s.h_sync_a_pol,
 186                                 s.h_total,
 187                                 s.v_total,
 188                                 s.underflow_occurred_status);
 189                 DTN_INFO("\n");
 190         }
 191         DTN_INFO("\n");
 192
 193         log_mpc_crc(dc);
 194
 195         DTN_INFO_END();
 196 }
 197
 198 static void enable_power_gating_plane(
 199         struct dce_hwseq *hws,
 200         bool enable)
 201 {
 202         bool force_on = 1; /* disable power gating */
 203
 204         if (enable)
 205                 force_on = 0;
 206
 207         /* DCHUBP0/1/2/3 */
 208         REG_UPDATE(DOMAIN0_PG_CONFIG, DOMAIN0_POWER_FORCEON, force_on);
 209         REG_UPDATE(DOMAIN2_PG_CONFIG, DOMAIN2_POWER_FORCEON, force_on);
 210         REG_UPDATE(DOMAIN4_PG_CONFIG, DOMAIN4_POWER_FORCEON, force_on);
 211         REG_UPDATE(DOMAIN6_PG_CONFIG, DOMAIN6_POWER_FORCEON, force_on);
 212
 213         /* DPP0/1/2/3 */
 214         REG_UPDATE(DOMAIN1_PG_CONFIG, DOMAIN1_POWER_FORCEON, force_on);
 215         REG_UPDATE(DOMAIN3_PG_CONFIG, DOMAIN3_POWER_FORCEON, force_on);
 216         REG_UPDATE(DOMAIN5_PG_CONFIG, DOMAIN5_POWER_FORCEON, force_on);
 217         REG_UPDATE(DOMAIN7_PG_CONFIG, DOMAIN7_POWER_FORCEON, force_on);
 218 }
 219
 220 static void disable_vga(
 221         struct dce_hwseq *hws)
 222 {
 223         REG_WRITE(D1VGA_CONTROL, 0);
 224         REG_WRITE(D2VGA_CONTROL, 0);
 225         REG_WRITE(D3VGA_CONTROL, 0);
 226         REG_WRITE(D4VGA_CONTROL, 0);
 227 }
 228
 229 static void dpp_pg_control(
 230                 struct dce_hwseq *hws,
 231                 unsigned int dpp_inst,
 232                 bool power_on)
 233 {
 234         uint32_t power_gate = power_on ? 0 : 1;
 235         uint32_t pwr_status = power_on ? 0 : 2;
 236
 237         if (hws->ctx->dc->debug.disable_dpp_power_gate)
 238                 return;
 239
 240         switch (dpp_inst) {
 241         case 0: /* DPP0 */
 242                 REG_UPDATE(DOMAIN1_PG_CONFIG,
 243                                 DOMAIN1_POWER_GATE, power_gate);
 244
 245                 REG_WAIT(DOMAIN1_PG_STATUS,
 246                                 DOMAIN1_PGFSM_PWR_STATUS, pwr_status,
 247                                 1, 1000);
 248                 break;
 249         case 1: /* DPP1 */
 250                 REG_UPDATE(DOMAIN3_PG_CONFIG,
 251                                 DOMAIN3_POWER_GATE, power_gate);
 252
 253                 REG_WAIT(DOMAIN3_PG_STATUS,
 254                                 DOMAIN3_PGFSM_PWR_STATUS, pwr_status,
 255                                 1, 1000);
 256                 break;
 257         case 2: /* DPP2 */
 258                 REG_UPDATE(DOMAIN5_PG_CONFIG,
 259                                 DOMAIN5_POWER_GATE, power_gate);
 260
 261                 REG_WAIT(DOMAIN5_PG_STATUS,
 262                                 DOMAIN5_PGFSM_PWR_STATUS, pwr_status,
 263                                 1, 1000);
 264                 break;
 265         case 3: /* DPP3 */
 266                 REG_UPDATE(DOMAIN7_PG_CONFIG,
 267                                 DOMAIN7_POWER_GATE, power_gate);
 268
 269                 REG_WAIT(DOMAIN7_PG_STATUS,
 270                                 DOMAIN7_PGFSM_PWR_STATUS, pwr_status,
 271                                 1, 1000);
 272                 break;
 273         default:
 274                 BREAK_TO_DEBUGGER();
 275                 break;
 276         }
 277 }
 278
 279 static void hubp_pg_control(
 280                 struct dce_hwseq *hws,
 281                 unsigned int hubp_inst,
 282                 bool power_on)
 283 {
 284         uint32_t power_gate = power_on ? 0 : 1;
 285         uint32_t pwr_status = power_on ? 0 : 2;
 286
 287         if (hws->ctx->dc->debug.disable_hubp_power_gate)
 288                 return;
 289
 290         switch (hubp_inst) {
 291         case 0: /* DCHUBP0 */
 292                 REG_UPDATE(DOMAIN0_PG_CONFIG,
 293                                 DOMAIN0_POWER_GATE, power_gate);
 294
 295                 REG_WAIT(DOMAIN0_PG_STATUS,
 296                                 DOMAIN0_PGFSM_PWR_STATUS, pwr_status,
 297                                 1, 1000);
 298                 break;
 299         case 1: /* DCHUBP1 */
 300                 REG_UPDATE(DOMAIN2_PG_CONFIG,
 301                                 DOMAIN2_POWER_GATE, power_gate);
 302
 303                 REG_WAIT(DOMAIN2_PG_STATUS,
 304                                 DOMAIN2_PGFSM_PWR_STATUS, pwr_status,
 305                                 1, 1000);
 306                 break;
 307         case 2: /* DCHUBP2 */
 308                 REG_UPDATE(DOMAIN4_PG_CONFIG,
 309                                 DOMAIN4_POWER_GATE, power_gate);
 310
 311                 REG_WAIT(DOMAIN4_PG_STATUS,
 312                                 DOMAIN4_PGFSM_PWR_STATUS, pwr_status,
 313                                 1, 1000);
 314                 break;
 315         case 3: /* DCHUBP3 */
 316                 REG_UPDATE(DOMAIN6_PG_CONFIG,
 317                                 DOMAIN6_POWER_GATE, power_gate);
 318
 319                 REG_WAIT(DOMAIN6_PG_STATUS,
 320                                 DOMAIN6_PGFSM_PWR_STATUS, pwr_status,
 321                                 1, 1000);
 322                 break;
 323         default:
 324                 BREAK_TO_DEBUGGER();
 325                 break;
 326         }
 327 }
 328
 329 static void power_on_plane(
 330         struct dce_hwseq *hws,
 331         int plane_id)
 332 {
 333         struct dc_context *ctx = hws->ctx;
 334         if (REG(DC_IP_REQUEST_CNTL)) {
 335                 REG_SET(DC_IP_REQUEST_CNTL, 0,
 336                                 IP_REQUEST_EN, 1);
 337                 dpp_pg_control(hws, plane_id, true);
 338                 hubp_pg_control(hws, plane_id, true);
 339                 REG_SET(DC_IP_REQUEST_CNTL, 0,
 340                                 IP_REQUEST_EN, 0);
 341                 DC_LOG_DEBUG(
 342                                 "Un-gated front end for pipe %d\n", plane_id);
 343         }
 344 }
 345
 346 static void undo_DEGVIDCN10_253_wa(struct dc *dc)
 347 {
 348         struct dce_hwseq *hws = dc->hwseq;
 349         struct hubp *hubp = dc->res_pool->hubps[0];
 350
 351         if (!hws->wa_state.DEGVIDCN10_253_applied)
 352                 return;
 353
 354         hubp->funcs->set_blank(hubp, true);
 355
 356         REG_SET(DC_IP_REQUEST_CNTL, 0,
 357                         IP_REQUEST_EN, 1);
 358
 359         hubp_pg_control(hws, 0, false);
 360         REG_SET(DC_IP_REQUEST_CNTL, 0,
 361                         IP_REQUEST_EN, 0);
 362
 363         hws->wa_state.DEGVIDCN10_253_applied = false;
 364 }
 365
 366 static void apply_DEGVIDCN10_253_wa(struct dc *dc)
 367 {
 368         struct dce_hwseq *hws = dc->hwseq;
 369         struct hubp *hubp = dc->res_pool->hubps[0];
 370         int i;
 371
 372         if (dc->debug.disable_stutter)
 373                 return;
 374
 375         if (!hws->wa.DEGVIDCN10_253)
 376                 return;
 377
 378         for (i = 0; i < dc->res_pool->pipe_count; i++) {
 379                 if (!dc->res_pool->hubps[i]->power_gated)
 380                         return;
 381         }
 382
 383         /* all pipe power gated, apply work around to enable stutter. */
 384
 385         REG_SET(DC_IP_REQUEST_CNTL, 0,
 386                         IP_REQUEST_EN, 1);
 387
 388         hubp_pg_control(hws, 0, true);
 389         REG_SET(DC_IP_REQUEST_CNTL, 0,
 390                         IP_REQUEST_EN, 0);
 391
 392         hubp->funcs->set_hubp_blank_en(hubp, false);
 393         hws->wa_state.DEGVIDCN10_253_applied = true;
 394 }
 395
 396 static void bios_golden_init(struct dc *dc)
 397 {
 398         struct dc_bios *bp = dc->ctx->dc_bios;
 399         int i;
 400
 401         /* initialize dcn global */
 402         bp->funcs->enable_disp_power_gating(bp,
 403                         CONTROLLER_ID_D0, ASIC_PIPE_INIT);
 404
 405         for (i = 0; i < dc->res_pool->pipe_count; i++) {
 406                 /* initialize dcn per pipe */
 407                 bp->funcs->enable_disp_power_gating(bp,
 408                                 CONTROLLER_ID_D0 + i, ASIC_PIPE_DISABLE);
 409         }
 410 }
 411
 412 static void false_optc_underflow_wa(
 413                 struct dc *dc,
 414                 const struct dc_stream_state *stream,
 415                 struct timing_generator *tg)
 416 {
 417         int i;
 418         bool underflow;
 419
 420         if (!dc->hwseq->wa.false_optc_underflow)
 421                 return;
 422
 423         underflow = tg->funcs->is_optc_underflow_occurred(tg);
 424
 425         for (i = 0; i < dc->res_pool->pipe_count; i++) {
 426                 struct pipe_ctx *old_pipe_ctx = &dc->current_state->res_ctx.pipe_ctx[i];
 427
 428                 if (old_pipe_ctx->stream != stream)
 429                         continue;
 430
 431                 dc->hwss.wait_for_mpcc_disconnect(dc, dc->res_pool, old_pipe_ctx);
 432         }
 433
 434         tg->funcs->set_blank_data_double_buffer(tg, true);
 435
 436         if (tg->funcs->is_optc_underflow_occurred(tg) && !underflow)
 437                 tg->funcs->clear_optc_underflow(tg);
 438 }
 439
 440 static enum dc_status dcn10_prog_pixclk_crtc_otg(
 441                 struct pipe_ctx *pipe_ctx,
 442                 struct dc_state *context,
 443                 struct dc *dc)
 444 {
 445         struct dc_stream_state *stream = pipe_ctx->stream;
 446         enum dc_color_space color_space;
 447         struct tg_color black_color = {0};
 448
 449         /* by upper caller loop, pipe0 is parent pipe and be called first.
 450          * back end is set up by for pipe0. Other children pipe share back end
 451          * with pipe 0. No program is needed.
 452          */
 453         if (pipe_ctx->top_pipe != NULL)
 454                 return DC_OK;
 455
 456         /* TODO check if timing_changed, disable stream if timing changed */
 457
 458         /* HW program guide assume display already disable
 459          * by unplug sequence. OTG assume stop.
 460          */
 461         pipe_ctx->stream_res.tg->funcs->enable_optc_clock(pipe_ctx->stream_res.tg, true);
 462
 463         if (false == pipe_ctx->clock_source->funcs->program_pix_clk(
 464                         pipe_ctx->clock_source,
 465                         &pipe_ctx->stream_res.pix_clk_params,
 466                         &pipe_ctx->pll_settings)) {
 467                 BREAK_TO_DEBUGGER();
 468                 return DC_ERROR_UNEXPECTED;
 469         }
 470         pipe_ctx->stream_res.tg->dlg_otg_param.vready_offset = pipe_ctx->pipe_dlg_param.vready_offset;
 471         pipe_ctx->stream_res.tg->dlg_otg_param.vstartup_start = pipe_ctx->pipe_dlg_param.vstartup_start;
 472         pipe_ctx->stream_res.tg->dlg_otg_param.vupdate_offset = pipe_ctx->pipe_dlg_param.vupdate_offset;
 473         pipe_ctx->stream_res.tg->dlg_otg_param.vupdate_width = pipe_ctx->pipe_dlg_param.vupdate_width;
 474
 475         pipe_ctx->stream_res.tg->dlg_otg_param.signal =  pipe_ctx->stream->signal;
 476
 477         pipe_ctx->stream_res.tg->funcs->program_timing(
 478                         pipe_ctx->stream_res.tg,
 479                         &stream->timing,
 480                         true);
 481
 482 #if 0 /* move to after enable_crtc */
 483         /* TODO: OPP FMT, ABM. etc. should be done here. */
 484         /* or FPGA now. instance 0 only. TODO: move to opp.c */
 485
 486         inst_offset = reg_offsets[pipe_ctx->stream_res.tg->inst].fmt;
 487
 488         pipe_ctx->stream_res.opp->funcs->opp_program_fmt(
 489                                 pipe_ctx->stream_res.opp,
 490                                 &stream->bit_depth_params,
 491                                 &stream->clamping);
 492 #endif
 493         /* program otg blank color */
 494         color_space = stream->output_color_space;
 495         color_space_to_black_color(dc, color_space, &black_color);
 496
 497         if (pipe_ctx->stream_res.tg->funcs->set_blank_color)
 498                 pipe_ctx->stream_res.tg->funcs->set_blank_color(
 499                                 pipe_ctx->stream_res.tg,
 500                                 &black_color);
 501
 502         if (pipe_ctx->stream_res.tg->funcs->is_blanked &&
 503                         !pipe_ctx->stream_res.tg->funcs->is_blanked(pipe_ctx->stream_res.tg)) {
 504                 pipe_ctx->stream_res.tg->funcs->set_blank(pipe_ctx->stream_res.tg, true);
 505                 hwss_wait_for_blank_complete(pipe_ctx->stream_res.tg);
 506                 false_optc_underflow_wa(dc, pipe_ctx->stream, pipe_ctx->stream_res.tg);
 507         }
 508
 509         /* VTG is  within DCHUB command block. DCFCLK is always on */
 510         if (false == pipe_ctx->stream_res.tg->funcs->enable_crtc(pipe_ctx->stream_res.tg)) {
 511                 BREAK_TO_DEBUGGER();
 512                 return DC_ERROR_UNEXPECTED;
 513         }
 514
 515         /* TODO program crtc source select for non-virtual signal*/
 516         /* TODO program FMT */
 517         /* TODO setup link_enc */
 518         /* TODO set stream attributes */
 519         /* TODO program audio */
 520         /* TODO enable stream if timing changed */
 521         /* TODO unblank stream if DP */
 522
 523         return DC_OK;
 524 }
 525
 526 static void reset_back_end_for_pipe(
 527                 struct dc *dc,
 528                 struct pipe_ctx *pipe_ctx,
 529                 struct dc_state *context)
 530 {
 531         int i;
 532         struct dc_context *ctx = dc->ctx;
 533         if (pipe_ctx->stream_res.stream_enc == NULL) {
 534                 pipe_ctx->stream = NULL;
 535                 return;
 536         }
 537
 538         if (!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) {
 539                 /* DPMS may already disable */
 540                 if (!pipe_ctx->stream->dpms_off)
 541                         core_link_disable_stream(pipe_ctx, FREE_ACQUIRED_RESOURCE);
 542                 else if (pipe_ctx->stream_res.audio) {
 543                         /*
 544                          * if stream is already disabled outside of commit streams path,
 545                          * audio disable was skipped. Need to do it here
 546                          */
 547                         pipe_ctx->stream_res.audio->funcs->az_disable(pipe_ctx->stream_res.audio);
 548
 549                         if (dc->caps.dynamic_audio == true) {
 550                                 /*we have to dynamic arbitrate the audio endpoints*/
 551                                 pipe_ctx->stream_res.audio = NULL;
 552                                 /*we free the resource, need reset is_audio_acquired*/
 553                                 update_audio_usage(&dc->current_state->res_ctx, dc->res_pool, pipe_ctx->stream_res.audio, false);
 554                         }
 555
 556                 }
 557
 558         }
 559
 560         /* by upper caller loop, parent pipe: pipe0, will be reset last.
 561          * back end share by all pipes and will be disable only when disable
 562          * parent pipe.
 563          */
 564         if (pipe_ctx->top_pipe == NULL) {
 565                 pipe_ctx->stream_res.tg->funcs->disable_crtc(pipe_ctx->stream_res.tg);
 566
 567                 pipe_ctx->stream_res.tg->funcs->enable_optc_clock(pipe_ctx->stream_res.tg, false);
 568         }
 569
 570         for (i = 0; i < dc->res_pool->pipe_count; i++)
 571                 if (&dc->current_state->res_ctx.pipe_ctx[i] == pipe_ctx)
 572                         break;
 573
 574         if (i == dc->res_pool->pipe_count)
 575                 return;
 576
 577         pipe_ctx->stream = NULL;
 578         DC_LOG_DEBUG("Reset back end for pipe %d, tg:%d\n",
 579                                         pipe_ctx->pipe_idx, pipe_ctx->stream_res.tg->inst);
 580 }
 581
 582 static void dcn10_verify_allow_pstate_change_high(struct dc *dc)
 583 {
 584         static bool should_log_hw_state; /* prevent hw state log by default */
 585
 586         if (!hubbub1_verify_allow_pstate_change_high(dc->res_pool->hubbub)) {
 587                 if (should_log_hw_state) {
 588                         dcn10_log_hw_state(dc);
 589                 }
 590
 591                 BREAK_TO_DEBUGGER();
 592         }
 593 }
 594
 595 /* trigger HW to start disconnect plane from stream on the next vsync */
 596 static void plane_atomic_disconnect(struct dc *dc, struct pipe_ctx *pipe_ctx)
 597 {
 598         struct hubp *hubp = pipe_ctx->plane_res.hubp;
 599         int dpp_id = pipe_ctx->plane_res.dpp->inst;
 600         struct mpc *mpc = dc->res_pool->mpc;
 601         struct mpc_tree *mpc_tree_params;
 602         struct mpcc *mpcc_to_remove = NULL;
 603         struct output_pixel_processor *opp = pipe_ctx->stream_res.opp;
 604
 605         mpc_tree_params = &(opp->mpc_tree_params);
 606         mpcc_to_remove = mpc->funcs->get_mpcc_for_dpp(mpc_tree_params, dpp_id);
 607
 608         /*Already reset*/
 609         if (mpcc_to_remove == NULL)
 610                 return;
 611
 612         mpc->funcs->remove_mpcc(mpc, mpc_tree_params, mpcc_to_remove);
 613         opp->mpcc_disconnect_pending[pipe_ctx->plane_res.mpcc_inst] = true;
 614
 615         dc->optimized_required = true;
 616
 617         if (hubp->funcs->hubp_disconnect)
 618                 hubp->funcs->hubp_disconnect(hubp);
 619
 620         if (dc->debug.sanity_checks)
 621                 dcn10_verify_allow_pstate_change_high(dc);
 622 }
 623
 624 static void plane_atomic_power_down(struct dc *dc, struct pipe_ctx *pipe_ctx)
 625 {
 626         struct dce_hwseq *hws = dc->hwseq;
 627         struct dpp *dpp = pipe_ctx->plane_res.dpp;
 628         struct dc_context *ctx = dc->ctx;
 629
 630         if (REG(DC_IP_REQUEST_CNTL)) {
 631                 REG_SET(DC_IP_REQUEST_CNTL, 0,
 632                                 IP_REQUEST_EN, 1);
 633                 dpp_pg_control(hws, dpp->inst, false);
 634                 hubp_pg_control(hws, pipe_ctx->plane_res.hubp->inst, false);
 635                 dpp->funcs->dpp_reset(dpp);
 636                 REG_SET(DC_IP_REQUEST_CNTL, 0,
 637                                 IP_REQUEST_EN, 0);
 638                 DC_LOG_DEBUG(
 639                                 "Power gated front end %d\n", pipe_ctx->pipe_idx);
 640         }
 641 }
 642
 643 /* disable HW used by plane.
 644  * note:  cannot disable until disconnect is complete
 645  */
 646 static void plane_atomic_disable(struct dc *dc, struct pipe_ctx *pipe_ctx)
 647 {
 648         struct hubp *hubp = pipe_ctx->plane_res.hubp;
 649         struct dpp *dpp = pipe_ctx->plane_res.dpp;
 650         int opp_id = hubp->opp_id;
 651
 652         dc->hwss.wait_for_mpcc_disconnect(dc, dc->res_pool, pipe_ctx);
 653
 654         hubp->funcs->hubp_clk_cntl(hubp, false);
 655
 656         dpp->funcs->dpp_dppclk_control(dpp, false, false);
 657
 658         if (opp_id != 0xf && pipe_ctx->stream_res.opp->mpc_tree_params.opp_list == NULL)
 659                 pipe_ctx->stream_res.opp->funcs->opp_pipe_clock_control(
 660                                 pipe_ctx->stream_res.opp,
 661                                 false);
 662
 663         hubp->power_gated = true;
 664         dc->optimized_required = false; /* We're powering off, no need to optimize */
 665
 666         plane_atomic_power_down(dc, pipe_ctx);
 667
 668         pipe_ctx->stream = NULL;
 669         memset(&pipe_ctx->stream_res, 0, sizeof(pipe_ctx->stream_res));
 670         memset(&pipe_ctx->plane_res, 0, sizeof(pipe_ctx->plane_res));
 671         pipe_ctx->top_pipe = NULL;
 672         pipe_ctx->bottom_pipe = NULL;
 673         pipe_ctx->plane_state = NULL;
 674 }
 675
 676 static void dcn10_disable_plane(struct dc *dc, struct pipe_ctx *pipe_ctx)
 677 {
 678         struct dc_context *ctx = dc->ctx;
 679
 680         if (!pipe_ctx->plane_res.hubp || pipe_ctx->plane_res.hubp->power_gated)
 681                 return;
 682
 683         plane_atomic_disable(dc, pipe_ctx);
 684
 685         apply_DEGVIDCN10_253_wa(dc);
 686
 687         DC_LOG_DC("Power down front end %d\n",
 688                                         pipe_ctx->pipe_idx);
 689 }
 690
 691 static void dcn10_init_hw(struct dc *dc)
 692 {
 693         int i;
 694         struct abm *abm = dc->res_pool->abm;
 695         struct dmcu *dmcu = dc->res_pool->dmcu;
 696         struct dce_hwseq *hws = dc->hwseq;
 697         struct dc_bios *dcb = dc->ctx->dc_bios;
 698         struct dc_state  *context = dc->current_state;
 699
 700         if (IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) {
 701                 REG_WRITE(REFCLK_CNTL, 0);
 702                 REG_UPDATE(DCHUBBUB_GLOBAL_TIMER_CNTL, DCHUBBUB_GLOBAL_TIMER_ENABLE, 1);
 703                 REG_WRITE(DIO_MEM_PWR_CTRL, 0);
 704
 705                 if (!dc->debug.disable_clock_gate) {
 706                         /* enable all DCN clock gating */
 707                         REG_WRITE(DCCG_GATE_DISABLE_CNTL, 0);
 708
 709                         REG_WRITE(DCCG_GATE_DISABLE_CNTL2, 0);
 710
 711                         REG_UPDATE(DCFCLK_CNTL, DCFCLK_GATE_DIS, 0);
 712                 }
 713
 714                 enable_power_gating_plane(dc->hwseq, true);
 715         } else {
 716
 717                 if (!dcb->funcs->is_accelerated_mode(dcb)) {
 718                         bios_golden_init(dc);
 719                         disable_vga(dc->hwseq);
 720                 }
 721
 722                 for (i = 0; i < dc->link_count; i++) {
 723                         /* Power up AND update implementation according to the
 724                          * required signal (which may be different from the
 725                          * default signal on connector).
 726                          */
 727                         struct dc_link *link = dc->links[i];
 728
 729                         if (link->link_enc->connector.id == CONNECTOR_ID_EDP)
 730                                 dc->hwss.edp_power_control(link, true);
 731
 732                         link->link_enc->funcs->hw_init(link->link_enc);
 733                 }
 734         }
 735
 736         for (i = 0; i < dc->res_pool->pipe_count; i++) {
 737                 struct timing_generator *tg = dc->res_pool->timing_generators[i];
 738
 739                 if (tg->funcs->is_tg_enabled(tg))
 740                         tg->funcs->lock(tg);
 741         }
 742
 743         /* Blank controller using driver code instead of
 744          * command table.
 745          */
 746         for (i = 0; i < dc->res_pool->pipe_count; i++) {
 747                 struct timing_generator *tg = dc->res_pool->timing_generators[i];
 748
 749                 if (tg->funcs->is_tg_enabled(tg)) {
 750                         tg->funcs->set_blank(tg, true);
 751                         hwss_wait_for_blank_complete(tg);
 752                 }
 753         }
 754
 755         /* Reset all MPCC muxes */
 756         dc->res_pool->mpc->funcs->mpc_init(dc->res_pool->mpc);
 757
 758         for (i = 0; i < dc->res_pool->pipe_count; i++) {
 759                 struct timing_generator *tg = dc->res_pool->timing_generators[i];
 760                 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
 761                 struct hubp *hubp = dc->res_pool->hubps[i];
 762                 struct dpp *dpp = dc->res_pool->dpps[i];
 763
 764                 pipe_ctx->stream_res.tg = tg;
 765                 pipe_ctx->pipe_idx = i;
 766
 767                 pipe_ctx->plane_res.hubp = hubp;
 768                 pipe_ctx->plane_res.dpp = dpp;
 769                 pipe_ctx->plane_res.mpcc_inst = dpp->inst;
 770                 hubp->mpcc_id = dpp->inst;
 771                 hubp->opp_id = 0xf;
 772                 hubp->power_gated = false;
 773
 774                 dc->res_pool->opps[i]->mpc_tree_params.opp_id = dc->res_pool->opps[i]->inst;
 775                 dc->res_pool->opps[i]->mpc_tree_params.opp_list = NULL;
 776                 dc->res_pool->opps[i]->mpcc_disconnect_pending[pipe_ctx->plane_res.mpcc_inst] = true;
 777                 pipe_ctx->stream_res.opp = dc->res_pool->opps[i];
 778
 779                 plane_atomic_disconnect(dc, pipe_ctx);
 780         }
 781
 782         for (i = 0; i < dc->res_pool->pipe_count; i++) {
 783                 struct timing_generator *tg = dc->res_pool->timing_generators[i];
 784
 785                 if (tg->funcs->is_tg_enabled(tg))
 786                         tg->funcs->unlock(tg);
 787         }
 788
 789         for (i = 0; i < dc->res_pool->pipe_count; i++) {
 790                 struct timing_generator *tg = dc->res_pool->timing_generators[i];
 791                 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
 792
 793                 dcn10_disable_plane(dc, pipe_ctx);
 794
 795                 pipe_ctx->stream_res.tg = NULL;
 796                 pipe_ctx->plane_res.hubp = NULL;
 797
 798                 tg->funcs->tg_init(tg);
 799         }
 800
 801         /* end of FPGA. Below if real ASIC */
 802         if (IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment))
 803                 return;
 804
 805         for (i = 0; i < dc->res_pool->audio_count; i++) {
 806                 struct audio *audio = dc->res_pool->audios[i];
 807
 808                 audio->funcs->hw_init(audio);
 809         }
 810
 811         if (abm != NULL) {
 812                 abm->funcs->init_backlight(abm);
 813                 abm->funcs->abm_init(abm);
 814         }
 815
 816         if (dmcu != NULL)
 817                 dmcu->funcs->dmcu_init(dmcu);
 818
 819         /* power AFMT HDMI memory TODO: may move to dis/en output save power*/
 820         REG_WRITE(DIO_MEM_PWR_CTRL, 0);
 821
 822         if (!dc->debug.disable_clock_gate) {
 823                 /* enable all DCN clock gating */
 824                 REG_WRITE(DCCG_GATE_DISABLE_CNTL, 0);
 825
 826                 REG_WRITE(DCCG_GATE_DISABLE_CNTL2, 0);
 827
 828                 REG_UPDATE(DCFCLK_CNTL, DCFCLK_GATE_DIS, 0);
 829         }
 830
 831         enable_power_gating_plane(dc->hwseq, true);
 832 }
 833
 834 static void reset_hw_ctx_wrap(
 835                 struct dc *dc,
 836                 struct dc_state *context)
 837 {
 838         int i;
 839
 840         /* Reset Back End*/
 841         for (i = dc->res_pool->pipe_count - 1; i >= 0 ; i--) {
 842                 struct pipe_ctx *pipe_ctx_old =
 843                         &dc->current_state->res_ctx.pipe_ctx[i];
 844                 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
 845
 846                 if (!pipe_ctx_old->stream)
 847                         continue;
 848
 849                 if (pipe_ctx_old->top_pipe)
 850                         continue;
 851
 852                 if (!pipe_ctx->stream ||
 853                                 pipe_need_reprogram(pipe_ctx_old, pipe_ctx)) {
 854                         struct clock_source *old_clk = pipe_ctx_old->clock_source;
 855
 856                         reset_back_end_for_pipe(dc, pipe_ctx_old, dc->current_state);
 857                         if (old_clk)
 858                                 old_clk->funcs->cs_power_down(old_clk);
 859                 }
 860         }
 861
 862 }
 863
 864 static bool patch_address_for_sbs_tb_stereo(
 865                 struct pipe_ctx *pipe_ctx, PHYSICAL_ADDRESS_LOC *addr)
 866 {
 867         struct dc_plane_state *plane_state = pipe_ctx->plane_state;
 868         bool sec_split = pipe_ctx->top_pipe &&
 869                         pipe_ctx->top_pipe->plane_state == pipe_ctx->plane_state;
 870         if (sec_split && plane_state->address.type == PLN_ADDR_TYPE_GRPH_STEREO &&
 871                 (pipe_ctx->stream->timing.timing_3d_format ==
 872                  TIMING_3D_FORMAT_SIDE_BY_SIDE ||
 873                  pipe_ctx->stream->timing.timing_3d_format ==
 874                  TIMING_3D_FORMAT_TOP_AND_BOTTOM)) {
 875                 *addr = plane_state->address.grph_stereo.left_addr;
 876                 plane_state->address.grph_stereo.left_addr =
 877                 plane_state->address.grph_stereo.right_addr;
 878                 return true;
 879         } else {
 880                 if (pipe_ctx->stream->view_format != VIEW_3D_FORMAT_NONE &&
 881                         plane_state->address.type != PLN_ADDR_TYPE_GRPH_STEREO) {
 882                         plane_state->address.type = PLN_ADDR_TYPE_GRPH_STEREO;
 883                         plane_state->address.grph_stereo.right_addr =
 884                         plane_state->address.grph_stereo.left_addr;
 885                 }
 886         }
 887         return false;
 888 }
 889
 890
 891
 892 static void dcn10_update_plane_addr(const struct dc *dc, struct pipe_ctx *pipe_ctx)
 893 {
 894         bool addr_patched = false;
 895         PHYSICAL_ADDRESS_LOC addr;
 896         struct dc_plane_state *plane_state = pipe_ctx->plane_state;
 897
 898         if (plane_state == NULL)
 899                 return;
 900         addr_patched = patch_address_for_sbs_tb_stereo(pipe_ctx, &addr);
 901         pipe_ctx->plane_res.hubp->funcs->hubp_program_surface_flip_and_addr(
 902                         pipe_ctx->plane_res.hubp,
 903                         &plane_state->address,
 904                         plane_state->flip_immediate);
 905         plane_state->status.requested_address = plane_state->address;
 906         if (addr_patched)
 907                 pipe_ctx->plane_state->address.grph_stereo.left_addr = addr;
 908 }
 909
 910 static bool dcn10_set_input_transfer_func(struct pipe_ctx *pipe_ctx,
 911                                           const struct dc_plane_state *plane_state)
 912 {
 913         struct dpp *dpp_base = pipe_ctx->plane_res.dpp;
 914         const struct dc_transfer_func *tf = NULL;
 915         bool result = true;
 916
 917         if (dpp_base == NULL)
 918                 return false;
 919
 920         if (plane_state->in_transfer_func)
 921                 tf = plane_state->in_transfer_func;
 922
 923         if (plane_state->gamma_correction &&
 924                 plane_state->gamma_correction->is_identity)
 925                 dpp_base->funcs->dpp_set_degamma(dpp_base, IPP_DEGAMMA_MODE_BYPASS);
 926         else if (plane_state->gamma_correction && dce_use_lut(plane_state->format))
 927                 dpp_base->funcs->dpp_program_input_lut(dpp_base, plane_state->gamma_correction);
 928
 929         if (tf == NULL)
 930                 dpp_base->funcs->dpp_set_degamma(dpp_base, IPP_DEGAMMA_MODE_BYPASS);
 931         else if (tf->type == TF_TYPE_PREDEFINED) {
 932                 switch (tf->tf) {
 933                 case TRANSFER_FUNCTION_SRGB:
 934                         dpp_base->funcs->dpp_set_degamma(dpp_base, IPP_DEGAMMA_MODE_HW_sRGB);
 935                         break;
 936                 case TRANSFER_FUNCTION_BT709:
 937                         dpp_base->funcs->dpp_set_degamma(dpp_base, IPP_DEGAMMA_MODE_HW_xvYCC);
 938                         break;
 939                 case TRANSFER_FUNCTION_LINEAR:
 940                         dpp_base->funcs->dpp_set_degamma(dpp_base, IPP_DEGAMMA_MODE_BYPASS);
 941                         break;
 942                 case TRANSFER_FUNCTION_PQ:
 943                 default:
 944                         result = false;
 945                         break;
 946                 }
 947         } else if (tf->type == TF_TYPE_BYPASS) {
 948                 dpp_base->funcs->dpp_set_degamma(dpp_base, IPP_DEGAMMA_MODE_BYPASS);
 949         } else {
 950                 /*TF_TYPE_DISTRIBUTED_POINTS*/
 951                 result = false;
 952         }
 953
 954         return result;
 955 }
 956
 957
 958
 959
 960
 961 static bool
 962 dcn10_set_output_transfer_func(struct pipe_ctx *pipe_ctx,
 963                                const struct dc_stream_state *stream)
 964 {
 965         struct dpp *dpp = pipe_ctx->plane_res.dpp;
 966
 967         if (dpp == NULL)
 968                 return false;
 969
 970         dpp->regamma_params.hw_points_num = GAMMA_HW_POINTS_NUM;
 971
 972         if (stream->out_transfer_func &&
 973             stream->out_transfer_func->type == TF_TYPE_PREDEFINED &&
 974             stream->out_transfer_func->tf == TRANSFER_FUNCTION_SRGB)
 975                 dpp->funcs->dpp_program_regamma_pwl(dpp, NULL, OPP_REGAMMA_SRGB);
 976
 977         /* dcn10_translate_regamma_to_hw_format takes 750us, only do it when full
 978          * update.
 979          */
 980         else if (cm_helper_translate_curve_to_hw_format(
 981                         stream->out_transfer_func,
 982                         &dpp->regamma_params, false)) {
 983                 dpp->funcs->dpp_program_regamma_pwl(
 984                                 dpp,
 985                                 &dpp->regamma_params, OPP_REGAMMA_USER);
 986         } else
 987                 dpp->funcs->dpp_program_regamma_pwl(dpp, NULL, OPP_REGAMMA_BYPASS);
 988
 989         return true;
 990 }
 991
 992 static void dcn10_pipe_control_lock(
 993         struct dc *dc,
 994         struct pipe_ctx *pipe,
 995         bool lock)
 996 {
 997         /* use TG master update lock to lock everything on the TG
 998          * therefore only top pipe need to lock
 999          */
1000         if (pipe->top_pipe)
1001                 return;
1002
1003         if (dc->debug.sanity_checks)
1004                 dcn10_verify_allow_pstate_change_high(dc);
1005
1006         if (lock)
1007                 pipe->stream_res.tg->funcs->lock(pipe->stream_res.tg);
1008         else
1009                 pipe->stream_res.tg->funcs->unlock(pipe->stream_res.tg);
1010
1011         if (dc->debug.sanity_checks)
1012                 dcn10_verify_allow_pstate_change_high(dc);
1013 }
1014
1015 static bool wait_for_reset_trigger_to_occur(
1016         struct dc_context *dc_ctx,
1017         struct timing_generator *tg)
1018 {
1019         bool rc = false;
1020
1021         /* To avoid endless loop we wait at most
1022          * frames_to_wait_on_triggered_reset frames for the reset to occur. */
1023         const uint32_t frames_to_wait_on_triggered_reset = 10;
1024         int i;
1025
1026         for (i = 0; i < frames_to_wait_on_triggered_reset; i++) {
1027
1028                 if (!tg->funcs->is_counter_moving(tg)) {
1029                         DC_ERROR("TG counter is not moving!\n");
1030                         break;
1031                 }
1032
1033                 if (tg->funcs->did_triggered_reset_occur(tg)) {
1034                         rc = true;
1035                         /* usually occurs at i=1 */
1036                         DC_SYNC_INFO("GSL: reset occurred at wait count: %d\n",
1037                                         i);
1038                         break;
1039                 }
1040
1041                 /* Wait for one frame. */
1042                 tg->funcs->wait_for_state(tg, CRTC_STATE_VACTIVE);
1043                 tg->funcs->wait_for_state(tg, CRTC_STATE_VBLANK);
1044         }
1045
1046         if (false == rc)
1047                 DC_ERROR("GSL: Timeout on reset trigger!\n");
1048
1049         return rc;
1050 }
1051
1052 static void dcn10_enable_timing_synchronization(
1053         struct dc *dc,
1054         int group_index,
1055         int group_size,
1056         struct pipe_ctx *grouped_pipes[])
1057 {
1058         struct dc_context *dc_ctx = dc->ctx;
1059         int i;
1060
1061         DC_SYNC_INFO("Setting up OTG reset trigger\n");
1062
1063         for (i = 1; i < group_size; i++)
1064                 grouped_pipes[i]->stream_res.tg->funcs->enable_reset_trigger(
1065                                 grouped_pipes[i]->stream_res.tg,
1066                                 grouped_pipes[0]->stream_res.tg->inst);
1067
1068         DC_SYNC_INFO("Waiting for trigger\n");
1069
1070         /* Need to get only check 1 pipe for having reset as all the others are
1071          * synchronized. Look at last pipe programmed to reset.
1072          */
1073
1074         wait_for_reset_trigger_to_occur(dc_ctx, grouped_pipes[1]->stream_res.tg);
1075         for (i = 1; i < group_size; i++)
1076                 grouped_pipes[i]->stream_res.tg->funcs->disable_reset_trigger(
1077                                 grouped_pipes[i]->stream_res.tg);
1078
1079         DC_SYNC_INFO("Sync complete\n");
1080 }
1081
1082 static void dcn10_enable_per_frame_crtc_position_reset(
1083         struct dc *dc,
1084         int group_size,
1085         struct pipe_ctx *grouped_pipes[])
1086 {
1087         struct dc_context *dc_ctx = dc->ctx;
1088         int i;
1089
1090         DC_SYNC_INFO("Setting up\n");
1091         for (i = 0; i < group_size; i++)
1092                 grouped_pipes[i]->stream_res.tg->funcs->enable_crtc_reset(
1093                                 grouped_pipes[i]->stream_res.tg,
1094                                 grouped_pipes[i]->stream->triggered_crtc_reset.event_source->status.primary_otg_inst,
1095                                 &grouped_pipes[i]->stream->triggered_crtc_reset);
1096
1097         DC_SYNC_INFO("Waiting for trigger\n");
1098
1099         for (i = 0; i < group_size; i++)
1100                 wait_for_reset_trigger_to_occur(dc_ctx, grouped_pipes[i]->stream_res.tg);
1101
1102         DC_SYNC_INFO("Multi-display sync is complete\n");
1103 }
1104
1105 /*static void print_rq_dlg_ttu(
1106                 struct dc *core_dc,
1107                 struct pipe_ctx *pipe_ctx)
1108 {
1109         DC_LOG_BANDWIDTH_CALCS(core_dc->ctx->logger,
1110                         "\n============== DML TTU Output parameters [%d] ==============\n"
1111                         "qos_level_low_wm: %d, \n"
1112                         "qos_level_high_wm: %d, \n"
1113                         "min_ttu_vblank: %d, \n"
1114                         "qos_level_flip: %d, \n"
1115                         "refcyc_per_req_delivery_l: %d, \n"
1116                         "qos_level_fixed_l: %d, \n"
1117                         "qos_ramp_disable_l: %d, \n"
1118                         "refcyc_per_req_delivery_pre_l: %d, \n"
1119                         "refcyc_per_req_delivery_c: %d, \n"
1120                         "qos_level_fixed_c: %d, \n"
1121                         "qos_ramp_disable_c: %d, \n"
1122                         "refcyc_per_req_delivery_pre_c: %d\n"
1123                         "=============================================================\n",
1124                         pipe_ctx->pipe_idx,
1125                         pipe_ctx->ttu_regs.qos_level_low_wm,
1126                         pipe_ctx->ttu_regs.qos_level_high_wm,
1127                         pipe_ctx->ttu_regs.min_ttu_vblank,
1128                         pipe_ctx->ttu_regs.qos_level_flip,
1129                         pipe_ctx->ttu_regs.refcyc_per_req_delivery_l,
1130                         pipe_ctx->ttu_regs.qos_level_fixed_l,
1131                         pipe_ctx->ttu_regs.qos_ramp_disable_l,
1132                         pipe_ctx->ttu_regs.refcyc_per_req_delivery_pre_l,
1133                         pipe_ctx->ttu_regs.refcyc_per_req_delivery_c,
1134                         pipe_ctx->ttu_regs.qos_level_fixed_c,
1135                         pipe_ctx->ttu_regs.qos_ramp_disable_c,
1136                         pipe_ctx->ttu_regs.refcyc_per_req_delivery_pre_c
1137                         );
1138
1139         DC_LOG_BANDWIDTH_CALCS(core_dc->ctx->logger,
1140                         "\n============== DML DLG Output parameters [%d] ==============\n"
1141                         "refcyc_h_blank_end: %d, \n"
1142                         "dlg_vblank_end: %d, \n"
1143                         "min_dst_y_next_start: %d, \n"
1144                         "refcyc_per_htotal: %d, \n"
1145                         "refcyc_x_after_scaler: %d, \n"
1146                         "dst_y_after_scaler: %d, \n"
1147                         "dst_y_prefetch: %d, \n"
1148                         "dst_y_per_vm_vblank: %d, \n"
1149                         "dst_y_per_row_vblank: %d, \n"
1150                         "ref_freq_to_pix_freq: %d, \n"
1151                         "vratio_prefetch: %d, \n"
1152                         "refcyc_per_pte_group_vblank_l: %d, \n"
1153                         "refcyc_per_meta_chunk_vblank_l: %d, \n"
1154                         "dst_y_per_pte_row_nom_l: %d, \n"
1155                         "refcyc_per_pte_group_nom_l: %d, \n",
1156                         pipe_ctx->pipe_idx,
1157                         pipe_ctx->dlg_regs.refcyc_h_blank_end,
1158                         pipe_ctx->dlg_regs.dlg_vblank_end,
1159                         pipe_ctx->dlg_regs.min_dst_y_next_start,
1160                         pipe_ctx->dlg_regs.refcyc_per_htotal,
1161                         pipe_ctx->dlg_regs.refcyc_x_after_scaler,
1162                         pipe_ctx->dlg_regs.dst_y_after_scaler,
1163                         pipe_ctx->dlg_regs.dst_y_prefetch,
1164                         pipe_ctx->dlg_regs.dst_y_per_vm_vblank,
1165                         pipe_ctx->dlg_regs.dst_y_per_row_vblank,
1166                         pipe_ctx->dlg_regs.ref_freq_to_pix_freq,
1167                         pipe_ctx->dlg_regs.vratio_prefetch,
1168                         pipe_ctx->dlg_regs.refcyc_per_pte_group_vblank_l,
1169                         pipe_ctx->dlg_regs.refcyc_per_meta_chunk_vblank_l,
1170                         pipe_ctx->dlg_regs.dst_y_per_pte_row_nom_l,
1171                         pipe_ctx->dlg_regs.refcyc_per_pte_group_nom_l
1172                         );
1173
1174         DC_LOG_BANDWIDTH_CALCS(core_dc->ctx->logger,
1175                         "\ndst_y_per_meta_row_nom_l: %d, \n"
1176                         "refcyc_per_meta_chunk_nom_l: %d, \n"
1177                         "refcyc_per_line_delivery_pre_l: %d, \n"
1178                         "refcyc_per_line_delivery_l: %d, \n"
1179                         "vratio_prefetch_c: %d, \n"
1180                         "refcyc_per_pte_group_vblank_c: %d, \n"
1181                         "refcyc_per_meta_chunk_vblank_c: %d, \n"
1182                         "dst_y_per_pte_row_nom_c: %d, \n"
1183                         "refcyc_per_pte_group_nom_c: %d, \n"
1184                         "dst_y_per_meta_row_nom_c: %d, \n"
1185                         "refcyc_per_meta_chunk_nom_c: %d, \n"
1186                         "refcyc_per_line_delivery_pre_c: %d, \n"
1187                         "refcyc_per_line_delivery_c: %d \n"
1188                         "========================================================\n",
1189                         pipe_ctx->dlg_regs.dst_y_per_meta_row_nom_l,
1190                         pipe_ctx->dlg_regs.refcyc_per_meta_chunk_nom_l,
1191                         pipe_ctx->dlg_regs.refcyc_per_line_delivery_pre_l,
1192                         pipe_ctx->dlg_regs.refcyc_per_line_delivery_l,
1193                         pipe_ctx->dlg_regs.vratio_prefetch_c,
1194                         pipe_ctx->dlg_regs.refcyc_per_pte_group_vblank_c,
1195                         pipe_ctx->dlg_regs.refcyc_per_meta_chunk_vblank_c,
1196                         pipe_ctx->dlg_regs.dst_y_per_pte_row_nom_c,
1197                         pipe_ctx->dlg_regs.refcyc_per_pte_group_nom_c,
1198                         pipe_ctx->dlg_regs.dst_y_per_meta_row_nom_c,
1199                         pipe_ctx->dlg_regs.refcyc_per_meta_chunk_nom_c,
1200                         pipe_ctx->dlg_regs.refcyc_per_line_delivery_pre_c,
1201                         pipe_ctx->dlg_regs.refcyc_per_line_delivery_c
1202                         );
1203
1204         DC_LOG_BANDWIDTH_CALCS(core_dc->ctx->logger,
1205                         "\n============== DML RQ Output parameters [%d] ==============\n"
1206                         "chunk_size: %d \n"
1207                         "min_chunk_size: %d \n"
1208                         "meta_chunk_size: %d \n"
1209                         "min_meta_chunk_size: %d \n"
1210                         "dpte_group_size: %d \n"
1211                         "mpte_group_size: %d \n"
1212                         "swath_height: %d \n"
1213                         "pte_row_height_linear: %d \n"
1214                         "========================================================\n",
1215                         pipe_ctx->pipe_idx,
1216                         pipe_ctx->rq_regs.rq_regs_l.chunk_size,
1217                         pipe_ctx->rq_regs.rq_regs_l.min_chunk_size,
1218                         pipe_ctx->rq_regs.rq_regs_l.meta_chunk_size,
1219                         pipe_ctx->rq_regs.rq_regs_l.min_meta_chunk_size,
1220                         pipe_ctx->rq_regs.rq_regs_l.dpte_group_size,
1221                         pipe_ctx->rq_regs.rq_regs_l.mpte_group_size,
1222                         pipe_ctx->rq_regs.rq_regs_l.swath_height,
1223                         pipe_ctx->rq_regs.rq_regs_l.pte_row_height_linear
1224                         );
1225 }
1226 */
1227
1228 static void mmhub_read_vm_system_aperture_settings(struct dcn10_hubp *hubp1,
1229                 struct vm_system_aperture_param *apt,
1230                 struct dce_hwseq *hws)
1231 {
1232         PHYSICAL_ADDRESS_LOC physical_page_number;
1233         uint32_t logical_addr_low;
1234         uint32_t logical_addr_high;
1235
1236         REG_GET(MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB,
1237                         PHYSICAL_PAGE_NUMBER_MSB, &physical_page_number.high_part);
1238         REG_GET(MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB,
1239                         PHYSICAL_PAGE_NUMBER_LSB, &physical_page_number.low_part);
1240
1241         REG_GET(MC_VM_SYSTEM_APERTURE_LOW_ADDR,
1242                         LOGICAL_ADDR, &logical_addr_low);
1243
1244         REG_GET(MC_VM_SYSTEM_APERTURE_HIGH_ADDR,
1245                         LOGICAL_ADDR, &logical_addr_high);
1246
1247         apt->sys_default.quad_part =  physical_page_number.quad_part << 12;
1248         apt->sys_low.quad_part =  (int64_t)logical_addr_low << 18;
1249         apt->sys_high.quad_part =  (int64_t)logical_addr_high << 18;
1250 }
1251
1252 /* Temporary read settings, future will get values from kmd directly */
1253 static void mmhub_read_vm_context0_settings(struct dcn10_hubp *hubp1,
1254                 struct vm_context0_param *vm0,
1255                 struct dce_hwseq *hws)
1256 {
1257         PHYSICAL_ADDRESS_LOC fb_base;
1258         PHYSICAL_ADDRESS_LOC fb_offset;
1259         uint32_t fb_base_value;
1260         uint32_t fb_offset_value;
1261
1262         REG_GET(DCHUBBUB_SDPIF_FB_BASE, SDPIF_FB_BASE, &fb_base_value);
1263         REG_GET(DCHUBBUB_SDPIF_FB_OFFSET, SDPIF_FB_OFFSET, &fb_offset_value);
1264
1265         REG_GET(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32,
1266                         PAGE_DIRECTORY_ENTRY_HI32, &vm0->pte_base.high_part);
1267         REG_GET(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32,
1268                         PAGE_DIRECTORY_ENTRY_LO32, &vm0->pte_base.low_part);
1269
1270         REG_GET(VM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32,
1271                         LOGICAL_PAGE_NUMBER_HI4, &vm0->pte_start.high_part);
1272         REG_GET(VM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32,
1273                         LOGICAL_PAGE_NUMBER_LO32, &vm0->pte_start.low_part);
1274
1275         REG_GET(VM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32,
1276                         LOGICAL_PAGE_NUMBER_HI4, &vm0->pte_end.high_part);
1277         REG_GET(VM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32,
1278                         LOGICAL_PAGE_NUMBER_LO32, &vm0->pte_end.low_part);
1279
1280         REG_GET(VM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32,
1281                         PHYSICAL_PAGE_ADDR_HI4, &vm0->fault_default.high_part);
1282         REG_GET(VM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32,
1283                         PHYSICAL_PAGE_ADDR_LO32, &vm0->fault_default.low_part);
1284
1285         /*
1286          * The values in VM_CONTEXT0_PAGE_TABLE_BASE_ADDR is in UMA space.
1287          * Therefore we need to do
1288          * DCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR = VM_CONTEXT0_PAGE_TABLE_BASE_ADDR
1289          * - DCHUBBUB_SDPIF_FB_OFFSET + DCHUBBUB_SDPIF_FB_BASE
1290          */
1291         fb_base.quad_part = (uint64_t)fb_base_value << 24;
1292         fb_offset.quad_part = (uint64_t)fb_offset_value << 24;
1293         vm0->pte_base.quad_part += fb_base.quad_part;
1294         vm0->pte_base.quad_part -= fb_offset.quad_part;
1295 }
1296
1297
1298 static void dcn10_program_pte_vm(struct dce_hwseq *hws, struct hubp *hubp)
1299 {
1300         struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp);
1301         struct vm_system_aperture_param apt = { {{ 0 } } };
1302         struct vm_context0_param vm0 = { { { 0 } } };
1303
1304         mmhub_read_vm_system_aperture_settings(hubp1, &apt, hws);
1305         mmhub_read_vm_context0_settings(hubp1, &vm0, hws);
1306
1307         hubp->funcs->hubp_set_vm_system_aperture_settings(hubp, &apt);
1308         hubp->funcs->hubp_set_vm_context0_settings(hubp, &vm0);
1309 }
1310
1311 static void dcn10_enable_plane(
1312         struct dc *dc,
1313         struct pipe_ctx *pipe_ctx,
1314         struct dc_state *context)
1315 {
1316         struct dce_hwseq *hws = dc->hwseq;
1317
1318         if (dc->debug.sanity_checks) {
1319                 dcn10_verify_allow_pstate_change_high(dc);
1320         }
1321
1322         undo_DEGVIDCN10_253_wa(dc);
1323
1324         power_on_plane(dc->hwseq,
1325                 pipe_ctx->plane_res.hubp->inst);
1326
1327         /* enable DCFCLK current DCHUB */
1328         pipe_ctx->plane_res.hubp->funcs->hubp_clk_cntl(pipe_ctx->plane_res.hubp, true);
1329
1330         /* make sure OPP_PIPE_CLOCK_EN = 1 */
1331         pipe_ctx->stream_res.opp->funcs->opp_pipe_clock_control(
1332                         pipe_ctx->stream_res.opp,
1333                         true);
1334
1335 /* TODO: enable/disable in dm as per update type.
1336         if (plane_state) {
1337                 DC_LOG_DC(dc->ctx->logger,
1338                                 "Pipe:%d 0x%x: addr hi:0x%x, "
1339                                 "addr low:0x%x, "
1340                                 "src: %d, %d, %d,"
1341                                 " %d; dst: %d, %d, %d, %d;\n",
1342                                 pipe_ctx->pipe_idx,
1343                                 plane_state,
1344                                 plane_state->address.grph.addr.high_part,
1345                                 plane_state->address.grph.addr.low_part,
1346                                 plane_state->src_rect.x,
1347                                 plane_state->src_rect.y,
1348                                 plane_state->src_rect.width,
1349                                 plane_state->src_rect.height,
1350                                 plane_state->dst_rect.x,
1351                                 plane_state->dst_rect.y,
1352                                 plane_state->dst_rect.width,
1353                                 plane_state->dst_rect.height);
1354
1355                 DC_LOG_DC(dc->ctx->logger,
1356                                 "Pipe %d: width, height, x, y         format:%d\n"
1357                                 "viewport:%d, %d, %d, %d\n"
1358                                 "recout:  %d, %d, %d, %d\n",
1359                                 pipe_ctx->pipe_idx,
1360                                 plane_state->format,
1361                                 pipe_ctx->plane_res.scl_data.viewport.width,
1362                                 pipe_ctx->plane_res.scl_data.viewport.height,
1363                                 pipe_ctx->plane_res.scl_data.viewport.x,
1364                                 pipe_ctx->plane_res.scl_data.viewport.y,
1365                                 pipe_ctx->plane_res.scl_data.recout.width,
1366                                 pipe_ctx->plane_res.scl_data.recout.height,
1367                                 pipe_ctx->plane_res.scl_data.recout.x,
1368                                 pipe_ctx->plane_res.scl_data.recout.y);
1369                 print_rq_dlg_ttu(dc, pipe_ctx);
1370         }
1371 */
1372         if (dc->config.gpu_vm_support)
1373                 dcn10_program_pte_vm(hws, pipe_ctx->plane_res.hubp);
1374
1375         if (dc->debug.sanity_checks) {
1376                 dcn10_verify_allow_pstate_change_high(dc);
1377         }
1378 }
1379
1380 static void program_gamut_remap(struct pipe_ctx *pipe_ctx)
1381 {
1382         int i = 0;
1383         struct dpp_grph_csc_adjustment adjust;
1384         memset(&adjust, 0, sizeof(adjust));
1385         adjust.gamut_adjust_type = GRAPHICS_GAMUT_ADJUST_TYPE_BYPASS;
1386
1387
1388         if (pipe_ctx->stream->gamut_remap_matrix.enable_remap == true) {
1389                 adjust.gamut_adjust_type = GRAPHICS_GAMUT_ADJUST_TYPE_SW;
1390                 for (i = 0; i < CSC_TEMPERATURE_MATRIX_SIZE; i++)
1391                         adjust.temperature_matrix[i] =
1392                                 pipe_ctx->stream->gamut_remap_matrix.matrix[i];
1393         }
1394
1395         pipe_ctx->plane_res.dpp->funcs->dpp_set_gamut_remap(pipe_ctx->plane_res.dpp, &adjust);
1396 }
1397
1398
1399 static void program_csc_matrix(struct pipe_ctx *pipe_ctx,
1400                 enum dc_color_space colorspace,
1401                 uint16_t *matrix)
1402 {
1403         if (pipe_ctx->stream->csc_color_matrix.enable_adjustment == true) {
1404                         if (pipe_ctx->plane_res.dpp->funcs->dpp_set_csc_adjustment != NULL)
1405                                 pipe_ctx->plane_res.dpp->funcs->dpp_set_csc_adjustment(pipe_ctx->plane_res.dpp, matrix);
1406         } else {
1407                 if (pipe_ctx->plane_res.dpp->funcs->dpp_set_csc_default != NULL)
1408                         pipe_ctx->plane_res.dpp->funcs->dpp_set_csc_default(pipe_ctx->plane_res.dpp, colorspace);
1409         }
1410 }
1411
1412 static void program_output_csc(struct dc *dc,
1413                 struct pipe_ctx *pipe_ctx,
1414                 enum dc_color_space colorspace,
1415                 uint16_t *matrix,
1416                 int opp_id)
1417 {
1418         if (pipe_ctx->plane_res.dpp->funcs->dpp_set_csc_adjustment != NULL)
1419                 program_csc_matrix(pipe_ctx,
1420                                 colorspace,
1421                                 matrix);
1422 }
1423
1424 static bool is_lower_pipe_tree_visible(struct pipe_ctx *pipe_ctx)
1425 {
1426         if (pipe_ctx->plane_state->visible)
1427                 return true;
1428         if (pipe_ctx->bottom_pipe && is_lower_pipe_tree_visible(pipe_ctx->bottom_pipe))
1429                 return true;
1430         return false;
1431 }
1432
1433 static bool is_upper_pipe_tree_visible(struct pipe_ctx *pipe_ctx)
1434 {
1435         if (pipe_ctx->plane_state->visible)
1436                 return true;
1437         if (pipe_ctx->top_pipe && is_upper_pipe_tree_visible(pipe_ctx->top_pipe))
1438                 return true;
1439         return false;
1440 }
1441
1442 static bool is_pipe_tree_visible(struct pipe_ctx *pipe_ctx)
1443 {
1444         if (pipe_ctx->plane_state->visible)
1445                 return true;
1446         if (pipe_ctx->top_pipe && is_upper_pipe_tree_visible(pipe_ctx->top_pipe))
1447                 return true;
1448         if (pipe_ctx->bottom_pipe && is_lower_pipe_tree_visible(pipe_ctx->bottom_pipe))
1449                 return true;
1450         return false;
1451 }
1452
1453 bool is_rgb_cspace(enum dc_color_space output_color_space)
1454 {
1455         switch (output_color_space) {
1456         case COLOR_SPACE_SRGB:
1457         case COLOR_SPACE_SRGB_LIMITED:
1458         case COLOR_SPACE_2020_RGB_FULLRANGE:
1459         case COLOR_SPACE_2020_RGB_LIMITEDRANGE:
1460         case COLOR_SPACE_ADOBERGB:
1461                 return true;
1462         case COLOR_SPACE_YCBCR601:
1463         case COLOR_SPACE_YCBCR709:
1464         case COLOR_SPACE_YCBCR601_LIMITED:
1465         case COLOR_SPACE_YCBCR709_LIMITED:
1466         case COLOR_SPACE_2020_YCBCR:
1467                 return false;
1468         default:
1469                 /* Add a case to switch */
1470                 BREAK_TO_DEBUGGER();
1471                 return false;
1472         }
1473 }
1474
1475 static void dcn10_get_surface_visual_confirm_color(
1476                 const struct pipe_ctx *pipe_ctx,
1477                 struct tg_color *color)
1478 {
1479         uint32_t color_value = MAX_TG_COLOR_VALUE;
1480
1481         switch (pipe_ctx->plane_res.scl_data.format) {
1482         case PIXEL_FORMAT_ARGB8888:
1483                 /* set boarder color to red */
1484                 color->color_r_cr = color_value;
1485                 break;
1486
1487         case PIXEL_FORMAT_ARGB2101010:
1488                 /* set boarder color to blue */
1489                 color->color_b_cb = color_value;
1490                 break;
1491         case PIXEL_FORMAT_420BPP8:
1492                 /* set boarder color to green */
1493                 color->color_g_y = color_value;
1494                 break;
1495         case PIXEL_FORMAT_420BPP10:
1496                 /* set boarder color to yellow */
1497                 color->color_g_y = color_value;
1498                 color->color_r_cr = color_value;
1499                 break;
1500         case PIXEL_FORMAT_FP16:
1501                 /* set boarder color to white */
1502                 color->color_r_cr = color_value;
1503                 color->color_b_cb = color_value;
1504                 color->color_g_y = color_value;
1505                 break;
1506         default:
1507                 break;
1508         }
1509 }
1510
1511 static uint16_t fixed_point_to_int_frac(
1512         struct fixed31_32 arg,
1513         uint8_t integer_bits,
1514         uint8_t fractional_bits)
1515 {
1516         int32_t numerator;
1517         int32_t divisor = 1 << fractional_bits;
1518
1519         uint16_t result;
1520
1521         uint16_t d = (uint16_t)dal_fixed31_32_floor(
1522                 dal_fixed31_32_abs(
1523                         arg));
1524
1525         if (d <= (uint16_t)(1 << integer_bits) - (1 / (uint16_t)divisor))
1526                 numerator = (uint16_t)dal_fixed31_32_floor(
1527                         dal_fixed31_32_mul_int(
1528                                 arg,
1529                                 divisor));
1530         else {
1531                 numerator = dal_fixed31_32_floor(
1532                         dal_fixed31_32_sub(
1533                                 dal_fixed31_32_from_int(
1534                                         1LL << integer_bits),
1535                                 dal_fixed31_32_recip(
1536                                         dal_fixed31_32_from_int(
1537                                                 divisor))));
1538         }
1539
1540         if (numerator >= 0)
1541                 result = (uint16_t)numerator;
1542         else
1543                 result = (uint16_t)(
1544                 (1 << (integer_bits + fractional_bits + 1)) + numerator);
1545
1546         if ((result != 0) && dal_fixed31_32_lt(
1547                 arg, dal_fixed31_32_zero))
1548                 result |= 1 << (integer_bits + fractional_bits);
1549
1550         return result;
1551 }
1552
1553 void build_prescale_params(struct  dc_bias_and_scale *bias_and_scale,
1554                 const struct dc_plane_state *plane_state)
1555 {
1556         if (plane_state->format >= SURFACE_PIXEL_FORMAT_VIDEO_BEGIN
1557                         && plane_state->format != SURFACE_PIXEL_FORMAT_INVALID
1558                         && plane_state->input_csc_color_matrix.enable_adjustment
1559                         && plane_state->coeff_reduction_factor.value != 0) {
1560                 bias_and_scale->scale_blue = fixed_point_to_int_frac(
1561                         dal_fixed31_32_mul(plane_state->coeff_reduction_factor,
1562                                         dal_fixed31_32_from_fraction(256, 255)),
1563                                 2,
1564                                 13);
1565                 bias_and_scale->scale_red = bias_and_scale->scale_blue;
1566                 bias_and_scale->scale_green = bias_and_scale->scale_blue;
1567         } else {
1568                 bias_and_scale->scale_blue = 0x2000;
1569                 bias_and_scale->scale_red = 0x2000;
1570                 bias_and_scale->scale_green = 0x2000;
1571         }
1572 }
1573
1574 static void update_dpp(struct dpp *dpp, struct dc_plane_state *plane_state)
1575 {
1576         struct dc_bias_and_scale bns_params = {0};
1577
1578         // program the input csc
1579         dpp->funcs->dpp_setup(dpp,
1580                         plane_state->format,
1581                         EXPANSION_MODE_ZERO,
1582                         plane_state->input_csc_color_matrix,
1583                         COLOR_SPACE_YCBCR601_LIMITED);
1584
1585         //set scale and bias registers
1586         build_prescale_params(&bns_params, plane_state);
1587         if (dpp->funcs->dpp_program_bias_and_scale)
1588                 dpp->funcs->dpp_program_bias_and_scale(dpp, &bns_params);
1589 }
1590
1591
1592 static void update_mpcc(struct dc *dc, struct pipe_ctx *pipe_ctx)
1593 {
1594         struct hubp *hubp = pipe_ctx->plane_res.hubp;
1595         struct mpcc_blnd_cfg blnd_cfg;
1596         bool per_pixel_alpha = pipe_ctx->plane_state->per_pixel_alpha && pipe_ctx->bottom_pipe;
1597         int mpcc_id;
1598         struct mpcc *new_mpcc;
1599         struct mpc *mpc = dc->res_pool->mpc;
1600         struct mpc_tree *mpc_tree_params = &(pipe_ctx->stream_res.opp->mpc_tree_params);
1601
1602         /* TODO: proper fix once fpga works */
1603
1604         if (dc->debug.surface_visual_confirm)
1605                 dcn10_get_surface_visual_confirm_color(
1606                                 pipe_ctx, &blnd_cfg.black_color);
1607         else
1608                 color_space_to_black_color(
1609                         dc, pipe_ctx->stream->output_color_space,
1610                         &blnd_cfg.black_color);
1611
1612         if (per_pixel_alpha)
1613                 blnd_cfg.alpha_mode = MPCC_ALPHA_BLEND_MODE_PER_PIXEL_ALPHA;
1614         else
1615                 blnd_cfg.alpha_mode = MPCC_ALPHA_BLEND_MODE_GLOBAL_ALPHA;
1616
1617         blnd_cfg.overlap_only = false;
1618         blnd_cfg.global_alpha = 0xff;
1619         blnd_cfg.global_gain = 0xff;
1620
1621         /* DCN1.0 has output CM before MPC which seems to screw with
1622          * pre-multiplied alpha.
1623          */
1624         blnd_cfg.pre_multiplied_alpha = is_rgb_cspace(
1625                         pipe_ctx->stream->output_color_space)
1626                                         && per_pixel_alpha;
1627
1628         /*
1629          * TODO: remove hack
1630          * Note: currently there is a bug in init_hw such that
1631          * on resume from hibernate, BIOS sets up MPCC0, and
1632          * we do mpcc_remove but the mpcc cannot go to idle
1633          * after remove. This cause us to pick mpcc1 here,
1634          * which causes a pstate hang for yet unknown reason.
1635          */
1636         mpcc_id = hubp->inst;
1637
1638         /* check if this MPCC is already being used */
1639         new_mpcc = mpc->funcs->get_mpcc_for_dpp(mpc_tree_params, mpcc_id);
1640         /* remove MPCC if being used */
1641         if (new_mpcc != NULL)
1642                 mpc->funcs->remove_mpcc(mpc, mpc_tree_params, new_mpcc);
1643         else
1644                 if (dc->debug.sanity_checks)
1645                         mpc->funcs->assert_mpcc_idle_before_connect(
1646                                         dc->res_pool->mpc, mpcc_id);
1647
1648         /* Call MPC to insert new plane */
1649         new_mpcc = mpc->funcs->insert_plane(dc->res_pool->mpc,
1650                         mpc_tree_params,
1651                         &blnd_cfg,
1652                         NULL,
1653                         NULL,
1654                         hubp->inst,
1655                         mpcc_id);
1656
1657         ASSERT(new_mpcc != NULL);
1658
1659         hubp->opp_id = pipe_ctx->stream_res.opp->inst;
1660         hubp->mpcc_id = mpcc_id;
1661 }
1662
1663 static void update_scaler(struct pipe_ctx *pipe_ctx)
1664 {
1665         bool per_pixel_alpha =
1666                         pipe_ctx->plane_state->per_pixel_alpha && pipe_ctx->bottom_pipe;
1667
1668         /* TODO: proper fix once fpga works */
1669
1670         pipe_ctx->plane_res.scl_data.lb_params.alpha_en = per_pixel_alpha;
1671         pipe_ctx->plane_res.scl_data.lb_params.depth = LB_PIXEL_DEPTH_30BPP;
1672         /* scaler configuration */
1673         pipe_ctx->plane_res.dpp->funcs->dpp_set_scaler(
1674                         pipe_ctx->plane_res.dpp, &pipe_ctx->plane_res.scl_data);
1675 }
1676
1677 static void update_dchubp_dpp(
1678         struct dc *dc,
1679         struct pipe_ctx *pipe_ctx,
1680         struct dc_state *context)
1681 {
1682         struct hubp *hubp = pipe_ctx->plane_res.hubp;
1683         struct dpp *dpp = pipe_ctx->plane_res.dpp;
1684         struct dc_plane_state *plane_state = pipe_ctx->plane_state;
1685         union plane_size size = plane_state->plane_size;
1686
1687         /* depends on DML calculation, DPP clock value may change dynamically */
1688         if (plane_state->update_flags.bits.full_update) {
1689                 dpp->funcs->dpp_dppclk_control(
1690                                 dpp,
1691                                 context->bw.dcn.calc_clk.max_dppclk_khz <
1692                                                 context->bw.dcn.calc_clk.dispclk_khz,
1693                                 true);
1694
1695                 dc->current_state->bw.dcn.cur_clk.max_dppclk_khz =
1696                                 context->bw.dcn.calc_clk.max_dppclk_khz;
1697                 context->bw.dcn.cur_clk.max_dppclk_khz = context->bw.dcn.calc_clk.max_dppclk_khz;
1698         }
1699
1700         /* TODO: Need input parameter to tell current DCHUB pipe tie to which OTG
1701          * VTG is within DCHUBBUB which is commond block share by each pipe HUBP.
1702          * VTG is 1:1 mapping with OTG. Each pipe HUBP will select which VTG
1703          */
1704         if (plane_state->update_flags.bits.full_update) {
1705                 hubp->funcs->hubp_vtg_sel(hubp, pipe_ctx->stream_res.tg->inst);
1706
1707                 hubp->funcs->hubp_setup(
1708                         hubp,
1709                         &pipe_ctx->dlg_regs,
1710                         &pipe_ctx->ttu_regs,
1711                         &pipe_ctx->rq_regs,
1712                         &pipe_ctx->pipe_dlg_param);
1713         }
1714
1715         size.grph.surface_size = pipe_ctx->plane_res.scl_data.viewport;
1716
1717         if (plane_state->update_flags.bits.full_update ||
1718                 plane_state->update_flags.bits.bpp_change)
1719                 update_dpp(dpp, plane_state);
1720
1721         if (plane_state->update_flags.bits.full_update ||
1722                 plane_state->update_flags.bits.per_pixel_alpha_change)
1723                 update_mpcc(dc, pipe_ctx);
1724
1725         if (plane_state->update_flags.bits.full_update ||
1726                 plane_state->update_flags.bits.per_pixel_alpha_change ||
1727                 plane_state->update_flags.bits.scaling_change ||
1728                 plane_state->update_flags.bits.position_change) {
1729                 update_scaler(pipe_ctx);
1730         }
1731
1732         if (plane_state->update_flags.bits.full_update ||
1733                 plane_state->update_flags.bits.scaling_change ||
1734                 plane_state->update_flags.bits.position_change) {
1735                 hubp->funcs->mem_program_viewport(
1736                         hubp,
1737                         &pipe_ctx->plane_res.scl_data.viewport,
1738                         &pipe_ctx->plane_res.scl_data.viewport_c);
1739         }
1740
1741         if (pipe_ctx->stream->cursor_attributes.address.quad_part != 0) {
1742                 dc->hwss.set_cursor_position(pipe_ctx);
1743                 dc->hwss.set_cursor_attribute(pipe_ctx);
1744         }
1745
1746         if (plane_state->update_flags.bits.full_update) {
1747                 /*gamut remap*/
1748                 program_gamut_remap(pipe_ctx);
1749
1750                 program_output_csc(dc,
1751                                 pipe_ctx,
1752                                 pipe_ctx->stream->output_color_space,
1753                                 pipe_ctx->stream->csc_color_matrix.matrix,
1754                                 hubp->opp_id);
1755         }
1756
1757         if (plane_state->update_flags.bits.full_update ||
1758                 plane_state->update_flags.bits.pixel_format_change ||
1759                 plane_state->update_flags.bits.horizontal_mirror_change ||
1760                 plane_state->update_flags.bits.rotation_change ||
1761                 plane_state->update_flags.bits.swizzle_change ||
1762                 plane_state->update_flags.bits.dcc_change ||
1763                 plane_state->update_flags.bits.bpp_change ||
1764                 plane_state->update_flags.bits.scaling_change) {
1765                 hubp->funcs->hubp_program_surface_config(
1766                         hubp,
1767                         plane_state->format,
1768                         &plane_state->tiling_info,
1769                         &size,
1770                         plane_state->rotation,
1771                         &plane_state->dcc,
1772                         plane_state->horizontal_mirror);
1773         }
1774
1775         hubp->power_gated = false;
1776
1777         dc->hwss.update_plane_addr(dc, pipe_ctx);
1778
1779         if (is_pipe_tree_visible(pipe_ctx))
1780                 hubp->funcs->set_blank(hubp, false);
1781 }
1782
1783
1784 static void program_all_pipe_in_tree(
1785                 struct dc *dc,
1786                 struct pipe_ctx *pipe_ctx,
1787                 struct dc_state *context)
1788 {
1789
1790         if (pipe_ctx->top_pipe == NULL) {
1791
1792                 pipe_ctx->stream_res.tg->dlg_otg_param.vready_offset = pipe_ctx->pipe_dlg_param.vready_offset;
1793                 pipe_ctx->stream_res.tg->dlg_otg_param.vstartup_start = pipe_ctx->pipe_dlg_param.vstartup_start;
1794                 pipe_ctx->stream_res.tg->dlg_otg_param.vupdate_offset = pipe_ctx->pipe_dlg_param.vupdate_offset;
1795                 pipe_ctx->stream_res.tg->dlg_otg_param.vupdate_width = pipe_ctx->pipe_dlg_param.vupdate_width;
1796                 pipe_ctx->stream_res.tg->dlg_otg_param.signal =  pipe_ctx->stream->signal;
1797
1798                 pipe_ctx->stream_res.tg->funcs->program_global_sync(
1799                                 pipe_ctx->stream_res.tg);
1800
1801                 if (pipe_ctx->stream_res.tg->funcs->set_blank)
1802                         pipe_ctx->stream_res.tg->funcs->set_blank(
1803                                         pipe_ctx->stream_res.tg,
1804                                         !is_pipe_tree_visible(pipe_ctx));
1805         }
1806
1807         if (pipe_ctx->plane_state != NULL) {
1808                 if (pipe_ctx->plane_state->update_flags.bits.full_update)
1809                         dcn10_enable_plane(dc, pipe_ctx, context);
1810
1811                 update_dchubp_dpp(dc, pipe_ctx, context);
1812
1813                 if (pipe_ctx->plane_state->update_flags.bits.full_update ||
1814                                 pipe_ctx->plane_state->update_flags.bits.in_transfer_func_change ||
1815                                 pipe_ctx->plane_state->update_flags.bits.gamma_change)
1816                         dc->hwss.set_input_transfer_func(pipe_ctx, pipe_ctx->plane_state);
1817
1818                 /* dcn10_translate_regamma_to_hw_format takes 750us to finish
1819                  * only do gamma programming for full update.
1820                  * TODO: This can be further optimized/cleaned up
1821                  * Always call this for now since it does memcmp inside before
1822                  * doing heavy calculation and programming
1823                  */
1824                 if (pipe_ctx->plane_state->update_flags.bits.full_update)
1825                         dc->hwss.set_output_transfer_func(pipe_ctx, pipe_ctx->stream);
1826         }
1827
1828         if (pipe_ctx->bottom_pipe != NULL && pipe_ctx->bottom_pipe != pipe_ctx) {
1829                 program_all_pipe_in_tree(dc, pipe_ctx->bottom_pipe, context);
1830         }
1831 }
1832
1833 static void dcn10_pplib_apply_display_requirements(
1834         struct dc *dc,
1835         struct dc_state *context)
1836 {
1837         struct dm_pp_display_configuration *pp_display_cfg = &context->pp_display_cfg;
1838
1839         pp_display_cfg->all_displays_in_sync = false;/*todo*/
1840         pp_display_cfg->nb_pstate_switch_disable = false;
1841         pp_display_cfg->min_engine_clock_khz = context->bw.dcn.cur_clk.dcfclk_khz;
1842         pp_display_cfg->min_memory_clock_khz = context->bw.dcn.cur_clk.fclk_khz;
1843         pp_display_cfg->min_engine_clock_deep_sleep_khz = context->bw.dcn.cur_clk.dcfclk_deep_sleep_khz;
1844         pp_display_cfg->min_dcfc_deep_sleep_clock_khz = context->bw.dcn.cur_clk.dcfclk_deep_sleep_khz;
1845         pp_display_cfg->avail_mclk_switch_time_us =
1846                         context->bw.dcn.cur_clk.dram_ccm_us > 0 ? context->bw.dcn.cur_clk.dram_ccm_us : 0;
1847         pp_display_cfg->avail_mclk_switch_time_in_disp_active_us =
1848                         context->bw.dcn.cur_clk.min_active_dram_ccm_us > 0 ? context->bw.dcn.cur_clk.min_active_dram_ccm_us : 0;
1849         pp_display_cfg->min_dcfclock_khz = context->bw.dcn.cur_clk.dcfclk_khz;
1850         pp_display_cfg->disp_clk_khz = context->bw.dcn.cur_clk.dispclk_khz;
1851         dce110_fill_display_configs(context, pp_display_cfg);
1852
1853         if (memcmp(&dc->prev_display_config, pp_display_cfg, sizeof(
1854                         struct dm_pp_display_configuration)) !=  0)
1855                 dm_pp_apply_display_requirements(dc->ctx, pp_display_cfg);
1856
1857         dc->prev_display_config = *pp_display_cfg;
1858 }
1859
1860 static void optimize_shared_resources(struct dc *dc)
1861 {
1862         if (dc->current_state->stream_count == 0) {
1863                 /* S0i2 message */
1864                 dcn10_pplib_apply_display_requirements(dc, dc->current_state);
1865         }
1866
1867         if (dc->debug.pplib_wm_report_mode == WM_REPORT_OVERRIDE)
1868                 dcn_bw_notify_pplib_of_wm_ranges(dc);
1869 }
1870
1871 static void ready_shared_resources(struct dc *dc, struct dc_state *context)
1872 {
1873         /* S0i2 message */
1874         if (dc->current_state->stream_count == 0 &&
1875                         context->stream_count != 0)
1876                 dcn10_pplib_apply_display_requirements(dc, context);
1877 }
1878
1879 static struct pipe_ctx *find_top_pipe_for_stream(
1880                 struct dc *dc,
1881                 struct dc_state *context,
1882                 const struct dc_stream_state *stream)
1883 {
1884         int i;
1885
1886         for (i = 0; i < dc->res_pool->pipe_count; i++) {
1887                 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
1888                 struct pipe_ctx *old_pipe_ctx =
1889                                 &dc->current_state->res_ctx.pipe_ctx[i];
1890
1891                 if (!pipe_ctx->plane_state && !old_pipe_ctx->plane_state)
1892                         continue;
1893
1894                 if (pipe_ctx->stream != stream)
1895                         continue;
1896
1897                 if (!pipe_ctx->top_pipe)
1898                         return pipe_ctx;
1899         }
1900         return NULL;
1901 }
1902
1903 static void dcn10_apply_ctx_for_surface(
1904                 struct dc *dc,
1905                 const struct dc_stream_state *stream,
1906                 int num_planes,
1907                 struct dc_state *context)
1908 {
1909         int i;
1910         struct timing_generator *tg;
1911         struct output_pixel_processor *opp;
1912         bool removed_pipe[4] = { false };
1913         unsigned int ref_clk_mhz = dc->res_pool->ref_clock_inKhz/1000;
1914         bool program_water_mark = false;
1915         struct dc_context *ctx = dc->ctx;
1916
1917         struct pipe_ctx *top_pipe_to_program =
1918                         find_top_pipe_for_stream(dc, context, stream);
1919
1920         if (!top_pipe_to_program)
1921                 return;
1922
1923         opp = top_pipe_to_program->stream_res.opp;
1924
1925         tg = top_pipe_to_program->stream_res.tg;
1926
1927         dcn10_pipe_control_lock(dc, top_pipe_to_program, true);
1928
1929         if (num_planes == 0) {
1930
1931                 /* OTG blank before remove all front end */
1932                 if (tg->funcs->set_blank)
1933                         tg->funcs->set_blank(tg, true);
1934         }
1935
1936         /* Disconnect unused mpcc */
1937         for (i = 0; i < dc->res_pool->pipe_count; i++) {
1938                 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
1939                 struct pipe_ctx *old_pipe_ctx =
1940                                 &dc->current_state->res_ctx.pipe_ctx[i];
1941                 /*
1942                  * Powergate reused pipes that are not powergated
1943                  * fairly hacky right now, using opp_id as indicator
1944                  * TODO: After move dc_post to dc_update, this will
1945                  * be removed.
1946                  */
1947                 if (pipe_ctx->plane_state && !old_pipe_ctx->plane_state) {
1948                         if (old_pipe_ctx->stream_res.tg == tg &&
1949                                 old_pipe_ctx->plane_res.hubp &&
1950                                 old_pipe_ctx->plane_res.hubp->opp_id != 0xf) {
1951                                 dcn10_disable_plane(dc, old_pipe_ctx);
1952                                 /*
1953                                  * power down fe will unlock when calling reset, need
1954                                  * to lock it back here. Messy, need rework.
1955                                  */
1956                                 pipe_ctx->stream_res.tg->funcs->lock(pipe_ctx->stream_res.tg);
1957                         }
1958                 }
1959
1960                 if (!pipe_ctx->plane_state &&
1961                         old_pipe_ctx->plane_state &&
1962                         old_pipe_ctx->stream_res.tg == tg) {
1963
1964                         plane_atomic_disconnect(dc, old_pipe_ctx);
1965                         removed_pipe[i] = true;
1966
1967                         DC_LOG_DC(
1968                                         "Reset mpcc for pipe %d\n",
1969                                         old_pipe_ctx->pipe_idx);
1970                 }
1971         }
1972
1973         if (num_planes > 0)
1974                 program_all_pipe_in_tree(dc, top_pipe_to_program, context);
1975
1976         dcn10_pipe_control_lock(dc, top_pipe_to_program, false);
1977
1978         if (num_planes == 0)
1979                 false_optc_underflow_wa(dc, stream, tg);
1980
1981         for (i = 0; i < dc->res_pool->pipe_count; i++) {
1982                 struct pipe_ctx *old_pipe_ctx =
1983                                 &dc->current_state->res_ctx.pipe_ctx[i];
1984                 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
1985
1986                 if (pipe_ctx->stream == stream &&
1987                                 pipe_ctx->plane_state &&
1988                         pipe_ctx->plane_state->update_flags.bits.full_update)
1989                         program_water_mark = true;
1990
1991                 if (removed_pipe[i])
1992                         dcn10_disable_plane(dc, old_pipe_ctx);
1993         }
1994
1995         if (program_water_mark) {
1996                 if (dc->debug.sanity_checks) {
1997                         /* pstate stuck check after watermark update */
1998                         dcn10_verify_allow_pstate_change_high(dc);
1999                 }
2000
2001                 /* watermark is for all pipes */
2002                 hubbub1_program_watermarks(dc->res_pool->hubbub,
2003                                 &context->bw.dcn.watermarks, ref_clk_mhz);
2004
2005                 if (dc->debug.sanity_checks) {
2006                         /* pstate stuck check after watermark update */
2007                         dcn10_verify_allow_pstate_change_high(dc);
2008                 }
2009         }
2010 /*      DC_LOG_BANDWIDTH_CALCS(dc->ctx->logger,
2011                         "\n============== Watermark parameters ==============\n"
2012                         "a.urgent_ns: %d \n"
2013                         "a.cstate_enter_plus_exit: %d \n"
2014                         "a.cstate_exit: %d \n"
2015                         "a.pstate_change: %d \n"
2016                         "a.pte_meta_urgent: %d \n"
2017                         "b.urgent_ns: %d \n"
2018                         "b.cstate_enter_plus_exit: %d \n"
2019                         "b.cstate_exit: %d \n"
2020                         "b.pstate_change: %d \n"
2021                         "b.pte_meta_urgent: %d \n",
2022                         context->bw.dcn.watermarks.a.urgent_ns,
2023                         context->bw.dcn.watermarks.a.cstate_pstate.cstate_enter_plus_exit_ns,
2024                         context->bw.dcn.watermarks.a.cstate_pstate.cstate_exit_ns,
2025                         context->bw.dcn.watermarks.a.cstate_pstate.pstate_change_ns,
2026                         context->bw.dcn.watermarks.a.pte_meta_urgent_ns,
2027                         context->bw.dcn.watermarks.b.urgent_ns,
2028                         context->bw.dcn.watermarks.b.cstate_pstate.cstate_enter_plus_exit_ns,
2029                         context->bw.dcn.watermarks.b.cstate_pstate.cstate_exit_ns,
2030                         context->bw.dcn.watermarks.b.cstate_pstate.pstate_change_ns,
2031                         context->bw.dcn.watermarks.b.pte_meta_urgent_ns
2032                         );
2033         DC_LOG_BANDWIDTH_CALCS(dc->ctx->logger,
2034                         "\nc.urgent_ns: %d \n"
2035                         "c.cstate_enter_plus_exit: %d \n"
2036                         "c.cstate_exit: %d \n"
2037                         "c.pstate_change: %d \n"
2038                         "c.pte_meta_urgent: %d \n"
2039                         "d.urgent_ns: %d \n"
2040                         "d.cstate_enter_plus_exit: %d \n"
2041                         "d.cstate_exit: %d \n"
2042                         "d.pstate_change: %d \n"
2043                         "d.pte_meta_urgent: %d \n"
2044                         "========================================================\n",
2045                         context->bw.dcn.watermarks.c.urgent_ns,
2046                         context->bw.dcn.watermarks.c.cstate_pstate.cstate_enter_plus_exit_ns,
2047                         context->bw.dcn.watermarks.c.cstate_pstate.cstate_exit_ns,
2048                         context->bw.dcn.watermarks.c.cstate_pstate.pstate_change_ns,
2049                         context->bw.dcn.watermarks.c.pte_meta_urgent_ns,
2050                         context->bw.dcn.watermarks.d.urgent_ns,
2051                         context->bw.dcn.watermarks.d.cstate_pstate.cstate_enter_plus_exit_ns,
2052                         context->bw.dcn.watermarks.d.cstate_pstate.cstate_exit_ns,
2053                         context->bw.dcn.watermarks.d.cstate_pstate.pstate_change_ns,
2054                         context->bw.dcn.watermarks.d.pte_meta_urgent_ns
2055                         );
2056 */
2057 }
2058
2059 static void dcn10_set_bandwidth(
2060                 struct dc *dc,
2061                 struct dc_state *context,
2062                 bool decrease_allowed)
2063 {
2064         struct pp_smu_display_requirement_rv *smu_req_cur =
2065                         &dc->res_pool->pp_smu_req;
2066         struct pp_smu_display_requirement_rv smu_req = *smu_req_cur;
2067         struct pp_smu_funcs_rv *pp_smu = dc->res_pool->pp_smu;
2068
2069         if (dc->debug.sanity_checks) {
2070                 dcn10_verify_allow_pstate_change_high(dc);
2071         }
2072
2073         if (IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment))
2074                 return;
2075
2076         if (decrease_allowed || context->bw.dcn.calc_clk.dispclk_khz
2077                         > dc->current_state->bw.dcn.cur_clk.dispclk_khz) {
2078                 dc->res_pool->display_clock->funcs->set_clock(
2079                                 dc->res_pool->display_clock,
2080                                 context->bw.dcn.calc_clk.dispclk_khz);
2081                 context->bw.dcn.cur_clk.dispclk_khz =
2082                                 context->bw.dcn.calc_clk.dispclk_khz;
2083         }
2084         if (decrease_allowed || context->bw.dcn.calc_clk.dcfclk_khz
2085                         > dc->current_state->bw.dcn.cur_clk.dcfclk_khz) {
2086                 context->bw.dcn.cur_clk.dcfclk_khz =
2087                                 context->bw.dcn.calc_clk.dcfclk_khz;
2088                 smu_req.hard_min_dcefclk_khz =
2089                                 context->bw.dcn.calc_clk.dcfclk_khz;
2090         }
2091         if (decrease_allowed || context->bw.dcn.calc_clk.fclk_khz
2092                         > dc->current_state->bw.dcn.cur_clk.fclk_khz) {
2093                 context->bw.dcn.cur_clk.fclk_khz =
2094                                 context->bw.dcn.calc_clk.fclk_khz;
2095                 smu_req.hard_min_fclk_khz = context->bw.dcn.calc_clk.fclk_khz;
2096         }
2097         if (decrease_allowed || context->bw.dcn.calc_clk.dcfclk_deep_sleep_khz
2098                         > dc->current_state->bw.dcn.cur_clk.dcfclk_deep_sleep_khz) {
2099                 context->bw.dcn.cur_clk.dcfclk_deep_sleep_khz =
2100                                 context->bw.dcn.calc_clk.dcfclk_deep_sleep_khz;
2101         }
2102
2103         smu_req.display_count = context->stream_count;
2104
2105         if (pp_smu->set_display_requirement)
2106                 pp_smu->set_display_requirement(&pp_smu->pp_smu, &smu_req);
2107
2108         *smu_req_cur = smu_req;
2109
2110         /* Decrease in freq is increase in period so opposite comparison for dram_ccm */
2111         if (decrease_allowed || context->bw.dcn.calc_clk.dram_ccm_us
2112                         < dc->current_state->bw.dcn.cur_clk.dram_ccm_us) {
2113                 context->bw.dcn.cur_clk.dram_ccm_us =
2114                                 context->bw.dcn.calc_clk.dram_ccm_us;
2115         }
2116         if (decrease_allowed || context->bw.dcn.calc_clk.min_active_dram_ccm_us
2117                         < dc->current_state->bw.dcn.cur_clk.min_active_dram_ccm_us) {
2118                 context->bw.dcn.cur_clk.min_active_dram_ccm_us =
2119                                 context->bw.dcn.calc_clk.min_active_dram_ccm_us;
2120         }
2121         dcn10_pplib_apply_display_requirements(dc, context);
2122
2123         if (dc->debug.sanity_checks) {
2124                 dcn10_verify_allow_pstate_change_high(dc);
2125         }
2126
2127         /* need to fix this function.  not doing the right thing here */
2128 }
2129
2130 static void set_drr(struct pipe_ctx **pipe_ctx,
2131                 int num_pipes, int vmin, int vmax)
2132 {
2133         int i = 0;
2134         struct drr_params params = {0};
2135
2136         params.vertical_total_max = vmax;
2137         params.vertical_total_min = vmin;
2138
2139         /* TODO: If multiple pipes are to be supported, you need
2140          * some GSL stuff
2141          */
2142         for (i = 0; i < num_pipes; i++) {
2143                 pipe_ctx[i]->stream_res.tg->funcs->set_drr(pipe_ctx[i]->stream_res.tg, &params);
2144         }
2145 }
2146
2147 static void get_position(struct pipe_ctx **pipe_ctx,
2148                 int num_pipes,
2149                 struct crtc_position *position)
2150 {
2151         int i = 0;
2152
2153         /* TODO: handle pipes > 1
2154          */
2155         for (i = 0; i < num_pipes; i++)
2156                 pipe_ctx[i]->stream_res.tg->funcs->get_position(pipe_ctx[i]->stream_res.tg, position);
2157 }
2158
2159 static void set_static_screen_control(struct pipe_ctx **pipe_ctx,
2160                 int num_pipes, const struct dc_static_screen_events *events)
2161 {
2162         unsigned int i;
2163         unsigned int value = 0;
2164
2165         if (events->surface_update)
2166                 value |= 0x80;
2167         if (events->cursor_update)
2168                 value |= 0x2;
2169         if (events->force_trigger)
2170                 value |= 0x1;
2171
2172         for (i = 0; i < num_pipes; i++)
2173                 pipe_ctx[i]->stream_res.tg->funcs->
2174                         set_static_screen_control(pipe_ctx[i]->stream_res.tg, value);
2175 }
2176
2177 static void set_plane_config(
2178         const struct dc *dc,
2179         struct pipe_ctx *pipe_ctx,
2180         struct resource_context *res_ctx)
2181 {
2182         /* TODO */
2183         program_gamut_remap(pipe_ctx);
2184 }
2185
2186 static void dcn10_config_stereo_parameters(
2187                 struct dc_stream_state *stream, struct crtc_stereo_flags *flags)
2188 {
2189         enum view_3d_format view_format = stream->view_format;
2190         enum dc_timing_3d_format timing_3d_format =\
2191                         stream->timing.timing_3d_format;
2192         bool non_stereo_timing = false;
2193
2194         if (timing_3d_format == TIMING_3D_FORMAT_NONE ||
2195                 timing_3d_format == TIMING_3D_FORMAT_SIDE_BY_SIDE ||
2196                 timing_3d_format == TIMING_3D_FORMAT_TOP_AND_BOTTOM)
2197                 non_stereo_timing = true;
2198
2199         if (non_stereo_timing == false &&
2200                 view_format == VIEW_3D_FORMAT_FRAME_SEQUENTIAL) {
2201
2202                 flags->PROGRAM_STEREO         = 1;
2203                 flags->PROGRAM_POLARITY       = 1;
2204                 if (timing_3d_format == TIMING_3D_FORMAT_INBAND_FA ||
2205                         timing_3d_format == TIMING_3D_FORMAT_DP_HDMI_INBAND_FA ||
2206                         timing_3d_format == TIMING_3D_FORMAT_SIDEBAND_FA) {
2207                         enum display_dongle_type dongle = \
2208                                         stream->sink->link->ddc->dongle_type;
2209                         if (dongle == DISPLAY_DONGLE_DP_VGA_CONVERTER ||
2210                                 dongle == DISPLAY_DONGLE_DP_DVI_CONVERTER ||
2211                                 dongle == DISPLAY_DONGLE_DP_HDMI_CONVERTER)
2212                                 flags->DISABLE_STEREO_DP_SYNC = 1;
2213                 }
2214                 flags->RIGHT_EYE_POLARITY =\
2215                                 stream->timing.flags.RIGHT_EYE_3D_POLARITY;
2216                 if (timing_3d_format == TIMING_3D_FORMAT_HW_FRAME_PACKING)
2217                         flags->FRAME_PACKED = 1;
2218         }
2219
2220         return;
2221 }
2222
2223 static void dcn10_setup_stereo(struct pipe_ctx *pipe_ctx, struct dc *dc)
2224 {
2225         struct crtc_stereo_flags flags = { 0 };
2226         struct dc_stream_state *stream = pipe_ctx->stream;
2227
2228         dcn10_config_stereo_parameters(stream, &flags);
2229
2230         pipe_ctx->stream_res.opp->funcs->opp_program_stereo(
2231                 pipe_ctx->stream_res.opp,
2232                 flags.PROGRAM_STEREO == 1 ? true:false,
2233                 &stream->timing);
2234
2235         pipe_ctx->stream_res.tg->funcs->program_stereo(
2236                 pipe_ctx->stream_res.tg,
2237                 &stream->timing,
2238                 &flags);
2239
2240         return;
2241 }
2242
2243 static struct hubp *get_hubp_by_inst(struct resource_pool *res_pool, int mpcc_inst)
2244 {
2245         int i;
2246
2247         for (i = 0; i < res_pool->pipe_count; i++) {
2248                 if (res_pool->hubps[i]->inst == mpcc_inst)
2249                         return res_pool->hubps[i];
2250         }
2251         ASSERT(false);
2252         return NULL;
2253 }
2254
2255 static void dcn10_wait_for_mpcc_disconnect(
2256                 struct dc *dc,
2257                 struct resource_pool *res_pool,
2258                 struct pipe_ctx *pipe_ctx)
2259 {
2260         int mpcc_inst;
2261
2262         if (dc->debug.sanity_checks) {
2263                 dcn10_verify_allow_pstate_change_high(dc);
2264         }
2265
2266         if (!pipe_ctx->stream_res.opp)
2267                 return;
2268
2269         for (mpcc_inst = 0; mpcc_inst < MAX_PIPES; mpcc_inst++) {
2270                 if (pipe_ctx->stream_res.opp->mpcc_disconnect_pending[mpcc_inst]) {
2271                         struct hubp *hubp = get_hubp_by_inst(res_pool, mpcc_inst);
2272
2273                         res_pool->mpc->funcs->wait_for_idle(res_pool->mpc, mpcc_inst);
2274                         pipe_ctx->stream_res.opp->mpcc_disconnect_pending[mpcc_inst] = false;
2275                         hubp->funcs->set_blank(hubp, true);
2276                         /*DC_LOG_ERROR(dc->ctx->logger,
2277                                         "[debug_mpo: wait_for_mpcc finished waiting on mpcc %d]\n",
2278                                         i);*/
2279                 }
2280         }
2281
2282         if (dc->debug.sanity_checks) {
2283                 dcn10_verify_allow_pstate_change_high(dc);
2284         }
2285
2286 }
2287
2288 static bool dcn10_dummy_display_power_gating(
2289         struct dc *dc,
2290         uint8_t controller_id,
2291         struct dc_bios *dcb,
2292         enum pipe_gating_control power_gating)
2293 {
2294         return true;
2295 }
2296
2297 static void dcn10_update_pending_status(struct pipe_ctx *pipe_ctx)
2298 {
2299         struct dc_plane_state *plane_state = pipe_ctx->plane_state;
2300         struct timing_generator *tg = pipe_ctx->stream_res.tg;
2301
2302         if (plane_state == NULL)
2303                 return;
2304
2305         plane_state->status.is_flip_pending =
2306                         pipe_ctx->plane_res.hubp->funcs->hubp_is_flip_pending(
2307                                         pipe_ctx->plane_res.hubp);
2308
2309         plane_state->status.current_address = pipe_ctx->plane_res.hubp->current_address;
2310         if (pipe_ctx->plane_res.hubp->current_address.type == PLN_ADDR_TYPE_GRPH_STEREO &&
2311                         tg->funcs->is_stereo_left_eye) {
2312                 plane_state->status.is_right_eye =
2313                                 !tg->funcs->is_stereo_left_eye(pipe_ctx->stream_res.tg);
2314         }
2315 }
2316
2317 static void dcn10_update_dchub(struct dce_hwseq *hws, struct dchub_init_data *dh_data)
2318 {
2319         if (hws->ctx->dc->res_pool->hubbub != NULL)
2320                 hubbub1_update_dchub(hws->ctx->dc->res_pool->hubbub, dh_data);
2321 }
2322
2323 static void dcn10_set_cursor_position(struct pipe_ctx *pipe_ctx)
2324 {
2325         struct dc_cursor_position pos_cpy = pipe_ctx->stream->cursor_position;
2326         struct hubp *hubp = pipe_ctx->plane_res.hubp;
2327         struct dpp *dpp = pipe_ctx->plane_res.dpp;
2328         struct dc_cursor_mi_param param = {
2329                 .pixel_clk_khz = pipe_ctx->stream->timing.pix_clk_khz,
2330                 .ref_clk_khz = pipe_ctx->stream->ctx->dc->res_pool->ref_clock_inKhz,
2331                 .viewport_x_start = pipe_ctx->plane_res.scl_data.viewport.x,
2332                 .viewport_width = pipe_ctx->plane_res.scl_data.viewport.width,
2333                 .h_scale_ratio = pipe_ctx->plane_res.scl_data.ratios.horz
2334         };
2335
2336         if (pipe_ctx->plane_state->address.type
2337                         == PLN_ADDR_TYPE_VIDEO_PROGRESSIVE)
2338                 pos_cpy.enable = false;
2339
2340         if (pipe_ctx->top_pipe && pipe_ctx->plane_state != pipe_ctx->top_pipe->plane_state)
2341                 pos_cpy.enable = false;
2342
2343         hubp->funcs->set_cursor_position(hubp, &pos_cpy, &param);
2344         dpp->funcs->set_cursor_position(dpp, &pos_cpy, &param, hubp->curs_attr.width);
2345 }
2346
2347 static void dcn10_set_cursor_attribute(struct pipe_ctx *pipe_ctx)
2348 {
2349         struct dc_cursor_attributes *attributes = &pipe_ctx->stream->cursor_attributes;
2350
2351         pipe_ctx->plane_res.hubp->funcs->set_cursor_attributes(
2352                         pipe_ctx->plane_res.hubp, attributes);
2353         pipe_ctx->plane_res.dpp->funcs->set_cursor_attributes(
2354                 pipe_ctx->plane_res.dpp, attributes->color_format);
2355 }
2356
2357 static const struct hw_sequencer_funcs dcn10_funcs = {
2358         .program_gamut_remap = program_gamut_remap,
2359         .program_csc_matrix = program_csc_matrix,
2360         .init_hw = dcn10_init_hw,
2361         .apply_ctx_to_hw = dce110_apply_ctx_to_hw,
2362         .apply_ctx_for_surface = dcn10_apply_ctx_for_surface,
2363         .set_plane_config = set_plane_config,
2364         .update_plane_addr = dcn10_update_plane_addr,
2365         .update_dchub = dcn10_update_dchub,
2366         .update_pending_status = dcn10_update_pending_status,
2367         .set_input_transfer_func = dcn10_set_input_transfer_func,
2368         .set_output_transfer_func = dcn10_set_output_transfer_func,
2369         .power_down = dce110_power_down,
2370         .enable_accelerated_mode = dce110_enable_accelerated_mode,
2371         .enable_timing_synchronization = dcn10_enable_timing_synchronization,
2372         .enable_per_frame_crtc_position_reset = dcn10_enable_per_frame_crtc_position_reset,
2373         .update_info_frame = dce110_update_info_frame,
2374         .enable_stream = dce110_enable_stream,
2375         .disable_stream = dce110_disable_stream,
2376         .unblank_stream = dce110_unblank_stream,
2377         .blank_stream = dce110_blank_stream,
2378         .enable_display_power_gating = dcn10_dummy_display_power_gating,
2379         .disable_plane = dcn10_disable_plane,
2380         .pipe_control_lock = dcn10_pipe_control_lock,
2381         .set_bandwidth = dcn10_set_bandwidth,
2382         .reset_hw_ctx_wrap = reset_hw_ctx_wrap,
2383         .prog_pixclk_crtc_otg = dcn10_prog_pixclk_crtc_otg,
2384         .set_drr = set_drr,
2385         .get_position = get_position,
2386         .set_static_screen_control = set_static_screen_control,
2387         .setup_stereo = dcn10_setup_stereo,
2388         .set_avmute = dce110_set_avmute,
2389         .log_hw_state = dcn10_log_hw_state,
2390         .wait_for_mpcc_disconnect = dcn10_wait_for_mpcc_disconnect,
2391         .ready_shared_resources = ready_shared_resources,
2392         .optimize_shared_resources = optimize_shared_resources,
2393         .pplib_apply_display_requirements =
2394                         dcn10_pplib_apply_display_requirements,
2395         .edp_backlight_control = hwss_edp_backlight_control,
2396         .edp_power_control = hwss_edp_power_control,
2397         .edp_wait_for_hpd_ready = hwss_edp_wait_for_hpd_ready,
2398         .set_cursor_position = dcn10_set_cursor_position,
2399         .set_cursor_attribute = dcn10_set_cursor_attribute
2400 };
2401
2402
2403 void dcn10_hw_sequencer_construct(struct dc *dc)
2404 {
2405         dc->hwss = dcn10_funcs;
2406 }
2407