drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

   1 /*
   2  * Copyright 2016 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: AMD
  23  *
  24  */
  25
  26 #include "dm_services.h"
  27 #include "core_types.h"
  28 #include "resource.h"
  29 #include "custom_float.h"
  30 #include "dcn10_hw_sequencer.h"
  31 #include "dce110/dce110_hw_sequencer.h"
  32 #include "dce/dce_hwseq.h"
  33 #include "abm.h"
  34 #include "dmcu.h"
  35 #include "dcn10_optc.h"
  36 #include "dcn10/dcn10_dpp.h"
  37 #include "dcn10/dcn10_mpc.h"
  38 #include "timing_generator.h"
  39 #include "opp.h"
  40 #include "ipp.h"
  41 #include "mpc.h"
  42 #include "reg_helper.h"
  43 #include "custom_float.h"
  44 #include "dcn10_hubp.h"
  45 #include "dcn10_hubbub.h"
  46 #include "dcn10_cm_common.h"
  47
  48 #define CTX \
  49         hws->ctx
  50 #define REG(reg)\
  51         hws->regs->reg
  52
  53 #undef FN
  54 #define FN(reg_name, field_name) \
  55         hws->shifts->field_name, hws->masks->field_name
  56
  57 #define DTN_INFO_MICRO_SEC(ref_cycle) \
  58         print_microsec(dc_ctx, ref_cycle)
  59
  60 void print_microsec(struct dc_context *dc_ctx, uint32_t ref_cycle)
  61 {
  62         static const uint32_t ref_clk_mhz = 48;
  63         static const unsigned int frac = 10;
  64         uint32_t us_x10 = (ref_cycle * frac) / ref_clk_mhz;
  65
  66         DTN_INFO("%d.%d \t ",
  67                         us_x10 / frac,
  68                         us_x10 % frac);
  69 }
  70
  71
  72 static void log_mpc_crc(struct dc *dc)
  73 {
  74         struct dc_context *dc_ctx = dc->ctx;
  75         struct dce_hwseq *hws = dc->hwseq;
  76
  77         if (REG(MPC_CRC_RESULT_GB))
  78                 DTN_INFO("MPC_CRC_RESULT_GB:%d MPC_CRC_RESULT_C:%d MPC_CRC_RESULT_AR:%d\n",
  79                 REG_READ(MPC_CRC_RESULT_GB), REG_READ(MPC_CRC_RESULT_C), REG_READ(MPC_CRC_RESULT_AR));
  80         if (REG(DPP_TOP0_DPP_CRC_VAL_B_A))
  81                 DTN_INFO("DPP_TOP0_DPP_CRC_VAL_B_A:%d DPP_TOP0_DPP_CRC_VAL_R_G:%d\n",
  82                 REG_READ(DPP_TOP0_DPP_CRC_VAL_B_A), REG_READ(DPP_TOP0_DPP_CRC_VAL_R_G));
  83 }
  84
  85 void dcn10_log_hubbub_state(struct dc *dc)
  86 {
  87         struct dc_context *dc_ctx = dc->ctx;
  88         struct dcn_hubbub_wm wm;
  89         int i;
  90
  91         hubbub1_wm_read_state(dc->res_pool->hubbub, &wm);
  92
  93         DTN_INFO("HUBBUB WM: \t data_urgent \t pte_meta_urgent \t "
  94                         "sr_enter \t sr_exit \t dram_clk_change \n");
  95
  96         for (i = 0; i < 4; i++) {
  97                 struct dcn_hubbub_wm_set *s;
  98
  99                 s = &wm.sets[i];
 100                 DTN_INFO("WM_Set[%d]:\t ", s->wm_set);
 101                 DTN_INFO_MICRO_SEC(s->data_urgent);
 102                 DTN_INFO_MICRO_SEC(s->pte_meta_urgent);
 103                 DTN_INFO_MICRO_SEC(s->sr_enter);
 104                 DTN_INFO_MICRO_SEC(s->sr_exit);
 105                 DTN_INFO_MICRO_SEC(s->dram_clk_chanage);
 106                 DTN_INFO("\n");
 107         }
 108
 109         DTN_INFO("\n");
 110 }
 111
 112 void dcn10_log_hw_state(struct dc *dc)
 113 {
 114         struct dc_context *dc_ctx = dc->ctx;
 115         struct resource_pool *pool = dc->res_pool;
 116         int i;
 117
 118         DTN_INFO_BEGIN();
 119
 120         dcn10_log_hubbub_state(dc);
 121
 122         DTN_INFO("HUBP:\t format \t addr_hi \t width \t height \t "
 123                         "rotation \t mirror \t  sw_mode \t "
 124                         "dcc_en \t blank_en \t ttu_dis \t underflow \t "
 125                         "min_ttu_vblank \t qos_low_wm \t qos_high_wm \n");
 126
 127         for (i = 0; i < pool->pipe_count; i++) {
 128                 struct hubp *hubp = pool->hubps[i];
 129                 struct dcn_hubp_state s;
 130
 131                 hubp1_read_state(TO_DCN10_HUBP(hubp), &s);
 132
 133                 DTN_INFO("[%d]:\t %xh \t %xh \t %d \t %d \t "
 134                                 "%xh \t %xh \t %xh \t "
 135                                 "%d \t %d \t %d \t %xh \t",
 136                                 i,
 137                                 s.pixel_format,
 138                                 s.inuse_addr_hi,
 139                                 s.viewport_width,
 140                                 s.viewport_height,
 141                                 s.rotation_angle,
 142                                 s.h_mirror_en,
 143                                 s.sw_mode,
 144                                 s.dcc_en,
 145                                 s.blank_en,
 146                                 s.ttu_disable,
 147                                 s.underflow_status);
 148                 DTN_INFO_MICRO_SEC(s.min_ttu_vblank);
 149                 DTN_INFO_MICRO_SEC(s.qos_level_low_wm);
 150                 DTN_INFO_MICRO_SEC(s.qos_level_high_wm);
 151                 DTN_INFO("\n");
 152         }
 153         DTN_INFO("\n");
 154
 155         DTN_INFO("OTG:\t v_bs \t v_be \t v_ss \t v_se \t vpol \t vmax \t vmin \t "
 156                         "h_bs \t h_be \t h_ss \t h_se \t hpol \t htot \t vtot \t underflow\n");
 157
 158         for (i = 0; i < pool->res_cap->num_timing_generator; i++) {
 159                 struct timing_generator *tg = pool->timing_generators[i];
 160                 struct dcn_otg_state s = {0};
 161
 162                 optc1_read_otg_state(DCN10TG_FROM_TG(tg), &s);
 163
 164                 //only print if OTG master is enabled
 165                 if ((s.otg_enabled & 1) == 0)
 166                         continue;
 167
 168                 DTN_INFO("[%d]:\t %d \t %d \t %d \t %d \t "
 169                                 "%d \t %d \t %d \t %d \t %d \t %d \t "
 170                                 "%d \t %d \t %d \t %d \t %d \t ",
 171                                 i,
 172                                 s.v_blank_start,
 173                                 s.v_blank_end,
 174                                 s.v_sync_a_start,
 175                                 s.v_sync_a_end,
 176                                 s.v_sync_a_pol,
 177                                 s.v_total_max,
 178                                 s.v_total_min,
 179                                 s.h_blank_start,
 180                                 s.h_blank_end,
 181                                 s.h_sync_a_start,
 182                                 s.h_sync_a_end,
 183                                 s.h_sync_a_pol,
 184                                 s.h_total,
 185                                 s.v_total,
 186                                 s.underflow_occurred_status);
 187                 DTN_INFO("\n");
 188         }
 189         DTN_INFO("\n");
 190
 191         log_mpc_crc(dc);
 192
 193         DTN_INFO_END();
 194 }
 195
 196 static void enable_dppclk(
 197         struct dce_hwseq *hws,
 198         uint8_t plane_id,
 199         uint32_t requested_pix_clk,
 200         bool dppclk_div)
 201 {
 202         dm_logger_write(hws->ctx->logger, LOG_SURFACE,
 203                         "dppclk_rate_control for pipe %d programed to %d\n",
 204                         plane_id,
 205                         dppclk_div);
 206
 207         if (hws->shifts->DPPCLK_RATE_CONTROL)
 208                 REG_UPDATE_2(DPP_CONTROL[plane_id],
 209                         DPPCLK_RATE_CONTROL, dppclk_div,
 210                         DPP_CLOCK_ENABLE, 1);
 211         else
 212                 REG_UPDATE(DPP_CONTROL[plane_id],
 213                         DPP_CLOCK_ENABLE, 1);
 214 }
 215
 216 static void enable_power_gating_plane(
 217         struct dce_hwseq *hws,
 218         bool enable)
 219 {
 220         bool force_on = 1; /* disable power gating */
 221
 222         if (enable)
 223                 force_on = 0;
 224
 225         /* DCHUBP0/1/2/3 */
 226         REG_UPDATE(DOMAIN0_PG_CONFIG, DOMAIN0_POWER_FORCEON, force_on);
 227         REG_UPDATE(DOMAIN2_PG_CONFIG, DOMAIN2_POWER_FORCEON, force_on);
 228         REG_UPDATE(DOMAIN4_PG_CONFIG, DOMAIN4_POWER_FORCEON, force_on);
 229         REG_UPDATE(DOMAIN6_PG_CONFIG, DOMAIN6_POWER_FORCEON, force_on);
 230
 231         /* DPP0/1/2/3 */
 232         REG_UPDATE(DOMAIN1_PG_CONFIG, DOMAIN1_POWER_FORCEON, force_on);
 233         REG_UPDATE(DOMAIN3_PG_CONFIG, DOMAIN3_POWER_FORCEON, force_on);
 234         REG_UPDATE(DOMAIN5_PG_CONFIG, DOMAIN5_POWER_FORCEON, force_on);
 235         REG_UPDATE(DOMAIN7_PG_CONFIG, DOMAIN7_POWER_FORCEON, force_on);
 236 }
 237
 238 static void disable_vga(
 239         struct dce_hwseq *hws)
 240 {
 241         REG_WRITE(D1VGA_CONTROL, 0);
 242         REG_WRITE(D2VGA_CONTROL, 0);
 243         REG_WRITE(D3VGA_CONTROL, 0);
 244         REG_WRITE(D4VGA_CONTROL, 0);
 245
 246         /* HW Engineer's Notes:
 247          *  During switch from vga->extended, if we set the VGA_TEST_ENABLE and
 248          *  then hit the VGA_TEST_RENDER_START, then the DCHUBP timing gets updated correctly.
 249          *
 250          *  Then vBIOS will have it poll for the VGA_TEST_RENDER_DONE and unset
 251          *  VGA_TEST_ENABLE, to leave it in the same state as before.
 252          */
 253         REG_UPDATE(VGA_TEST_CONTROL, VGA_TEST_ENABLE, 1);
 254         REG_UPDATE(VGA_TEST_CONTROL, VGA_TEST_RENDER_START, 1);
 255 }
 256
 257 static void dpp_pg_control(
 258                 struct dce_hwseq *hws,
 259                 unsigned int dpp_inst,
 260                 bool power_on)
 261 {
 262         uint32_t power_gate = power_on ? 0 : 1;
 263         uint32_t pwr_status = power_on ? 0 : 2;
 264
 265         if (hws->ctx->dc->debug.disable_dpp_power_gate)
 266                 return;
 267
 268         switch (dpp_inst) {
 269         case 0: /* DPP0 */
 270                 REG_UPDATE(DOMAIN1_PG_CONFIG,
 271                                 DOMAIN1_POWER_GATE, power_gate);
 272
 273                 REG_WAIT(DOMAIN1_PG_STATUS,
 274                                 DOMAIN1_PGFSM_PWR_STATUS, pwr_status,
 275                                 1, 1000);
 276                 break;
 277         case 1: /* DPP1 */
 278                 REG_UPDATE(DOMAIN3_PG_CONFIG,
 279                                 DOMAIN3_POWER_GATE, power_gate);
 280
 281                 REG_WAIT(DOMAIN3_PG_STATUS,
 282                                 DOMAIN3_PGFSM_PWR_STATUS, pwr_status,
 283                                 1, 1000);
 284                 break;
 285         case 2: /* DPP2 */
 286                 REG_UPDATE(DOMAIN5_PG_CONFIG,
 287                                 DOMAIN5_POWER_GATE, power_gate);
 288
 289                 REG_WAIT(DOMAIN5_PG_STATUS,
 290                                 DOMAIN5_PGFSM_PWR_STATUS, pwr_status,
 291                                 1, 1000);
 292                 break;
 293         case 3: /* DPP3 */
 294                 REG_UPDATE(DOMAIN7_PG_CONFIG,
 295                                 DOMAIN7_POWER_GATE, power_gate);
 296
 297                 REG_WAIT(DOMAIN7_PG_STATUS,
 298                                 DOMAIN7_PGFSM_PWR_STATUS, pwr_status,
 299                                 1, 1000);
 300                 break;
 301         default:
 302                 BREAK_TO_DEBUGGER();
 303                 break;
 304         }
 305 }
 306
 307 static void hubp_pg_control(
 308                 struct dce_hwseq *hws,
 309                 unsigned int hubp_inst,
 310                 bool power_on)
 311 {
 312         uint32_t power_gate = power_on ? 0 : 1;
 313         uint32_t pwr_status = power_on ? 0 : 2;
 314
 315         if (hws->ctx->dc->debug.disable_hubp_power_gate)
 316                 return;
 317
 318         switch (hubp_inst) {
 319         case 0: /* DCHUBP0 */
 320                 REG_UPDATE(DOMAIN0_PG_CONFIG,
 321                                 DOMAIN0_POWER_GATE, power_gate);
 322
 323                 REG_WAIT(DOMAIN0_PG_STATUS,
 324                                 DOMAIN0_PGFSM_PWR_STATUS, pwr_status,
 325                                 1, 1000);
 326                 break;
 327         case 1: /* DCHUBP1 */
 328                 REG_UPDATE(DOMAIN2_PG_CONFIG,
 329                                 DOMAIN2_POWER_GATE, power_gate);
 330
 331                 REG_WAIT(DOMAIN2_PG_STATUS,
 332                                 DOMAIN2_PGFSM_PWR_STATUS, pwr_status,
 333                                 1, 1000);
 334                 break;
 335         case 2: /* DCHUBP2 */
 336                 REG_UPDATE(DOMAIN4_PG_CONFIG,
 337                                 DOMAIN4_POWER_GATE, power_gate);
 338
 339                 REG_WAIT(DOMAIN4_PG_STATUS,
 340                                 DOMAIN4_PGFSM_PWR_STATUS, pwr_status,
 341                                 1, 1000);
 342                 break;
 343         case 3: /* DCHUBP3 */
 344                 REG_UPDATE(DOMAIN6_PG_CONFIG,
 345                                 DOMAIN6_POWER_GATE, power_gate);
 346
 347                 REG_WAIT(DOMAIN6_PG_STATUS,
 348                                 DOMAIN6_PGFSM_PWR_STATUS, pwr_status,
 349                                 1, 1000);
 350                 break;
 351         default:
 352                 BREAK_TO_DEBUGGER();
 353                 break;
 354         }
 355 }
 356
 357 static void power_on_plane(
 358         struct dce_hwseq *hws,
 359         int plane_id)
 360 {
 361         if (REG(DC_IP_REQUEST_CNTL)) {
 362                 REG_SET(DC_IP_REQUEST_CNTL, 0,
 363                                 IP_REQUEST_EN, 1);
 364                 dpp_pg_control(hws, plane_id, true);
 365                 hubp_pg_control(hws, plane_id, true);
 366                 REG_SET(DC_IP_REQUEST_CNTL, 0,
 367                                 IP_REQUEST_EN, 0);
 368                 dm_logger_write(hws->ctx->logger, LOG_DEBUG,
 369                                 "Un-gated front end for pipe %d\n", plane_id);
 370         }
 371 }
 372
 373 static void undo_DEGVIDCN10_253_wa(struct dc *dc)
 374 {
 375         struct dce_hwseq *hws = dc->hwseq;
 376         struct hubp *hubp = dc->res_pool->hubps[0];
 377
 378         if (!hws->wa_state.DEGVIDCN10_253_applied)
 379                 return;
 380
 381         hubp->funcs->set_blank(hubp, true);
 382
 383         REG_SET(DC_IP_REQUEST_CNTL, 0,
 384                         IP_REQUEST_EN, 1);
 385
 386         hubp_pg_control(hws, 0, false);
 387         REG_SET(DC_IP_REQUEST_CNTL, 0,
 388                         IP_REQUEST_EN, 0);
 389
 390         hws->wa_state.DEGVIDCN10_253_applied = false;
 391 }
 392
 393 static void apply_DEGVIDCN10_253_wa(struct dc *dc)
 394 {
 395         struct dce_hwseq *hws = dc->hwseq;
 396         struct hubp *hubp = dc->res_pool->hubps[0];
 397         int i;
 398
 399         if (dc->debug.disable_stutter)
 400                 return;
 401
 402         if (!hws->wa.DEGVIDCN10_253)
 403                 return;
 404
 405         for (i = 0; i < dc->res_pool->pipe_count; i++) {
 406                 if (!dc->res_pool->hubps[i]->power_gated)
 407                         return;
 408         }
 409
 410         /* all pipe power gated, apply work around to enable stutter. */
 411
 412         REG_SET(DC_IP_REQUEST_CNTL, 0,
 413                         IP_REQUEST_EN, 1);
 414
 415         hubp_pg_control(hws, 0, true);
 416         REG_SET(DC_IP_REQUEST_CNTL, 0,
 417                         IP_REQUEST_EN, 0);
 418
 419         hubp->funcs->set_hubp_blank_en(hubp, false);
 420         hws->wa_state.DEGVIDCN10_253_applied = true;
 421 }
 422
 423 static void bios_golden_init(struct dc *dc)
 424 {
 425         struct dc_bios *bp = dc->ctx->dc_bios;
 426         int i;
 427
 428         /* initialize dcn global */
 429         bp->funcs->enable_disp_power_gating(bp,
 430                         CONTROLLER_ID_D0, ASIC_PIPE_INIT);
 431
 432         for (i = 0; i < dc->res_pool->pipe_count; i++) {
 433                 /* initialize dcn per pipe */
 434                 bp->funcs->enable_disp_power_gating(bp,
 435                                 CONTROLLER_ID_D0 + i, ASIC_PIPE_DISABLE);
 436         }
 437 }
 438
 439 static void false_optc_underflow_wa(
 440                 struct dc *dc,
 441                 const struct dc_stream_state *stream,
 442                 struct timing_generator *tg)
 443 {
 444         int i;
 445         bool underflow;
 446
 447         if (!dc->hwseq->wa.false_optc_underflow)
 448                 return;
 449
 450         underflow = tg->funcs->is_optc_underflow_occurred(tg);
 451
 452         for (i = 0; i < dc->res_pool->pipe_count; i++) {
 453                 struct pipe_ctx *old_pipe_ctx = &dc->current_state->res_ctx.pipe_ctx[i];
 454
 455                 if (old_pipe_ctx->stream != stream)
 456                         continue;
 457
 458                 dc->hwss.wait_for_mpcc_disconnect(dc, dc->res_pool, old_pipe_ctx);
 459         }
 460
 461         tg->funcs->set_blank_data_double_buffer(tg, true);
 462
 463         if (tg->funcs->is_optc_underflow_occurred(tg) && !underflow)
 464                 tg->funcs->clear_optc_underflow(tg);
 465 }
 466
 467 static enum dc_status dcn10_prog_pixclk_crtc_otg(
 468                 struct pipe_ctx *pipe_ctx,
 469                 struct dc_state *context,
 470                 struct dc *dc)
 471 {
 472         struct dc_stream_state *stream = pipe_ctx->stream;
 473         enum dc_color_space color_space;
 474         struct tg_color black_color = {0};
 475
 476         /* by upper caller loop, pipe0 is parent pipe and be called first.
 477          * back end is set up by for pipe0. Other children pipe share back end
 478          * with pipe 0. No program is needed.
 479          */
 480         if (pipe_ctx->top_pipe != NULL)
 481                 return DC_OK;
 482
 483         /* TODO check if timing_changed, disable stream if timing changed */
 484
 485         /* HW program guide assume display already disable
 486          * by unplug sequence. OTG assume stop.
 487          */
 488         pipe_ctx->stream_res.tg->funcs->enable_optc_clock(pipe_ctx->stream_res.tg, true);
 489
 490         if (false == pipe_ctx->clock_source->funcs->program_pix_clk(
 491                         pipe_ctx->clock_source,
 492                         &pipe_ctx->stream_res.pix_clk_params,
 493                         &pipe_ctx->pll_settings)) {
 494                 BREAK_TO_DEBUGGER();
 495                 return DC_ERROR_UNEXPECTED;
 496         }
 497         pipe_ctx->stream_res.tg->dlg_otg_param.vready_offset = pipe_ctx->pipe_dlg_param.vready_offset;
 498         pipe_ctx->stream_res.tg->dlg_otg_param.vstartup_start = pipe_ctx->pipe_dlg_param.vstartup_start;
 499         pipe_ctx->stream_res.tg->dlg_otg_param.vupdate_offset = pipe_ctx->pipe_dlg_param.vupdate_offset;
 500         pipe_ctx->stream_res.tg->dlg_otg_param.vupdate_width = pipe_ctx->pipe_dlg_param.vupdate_width;
 501
 502         pipe_ctx->stream_res.tg->dlg_otg_param.signal =  pipe_ctx->stream->signal;
 503
 504         pipe_ctx->stream_res.tg->funcs->program_timing(
 505                         pipe_ctx->stream_res.tg,
 506                         &stream->timing,
 507                         true);
 508
 509 #if 0 /* move to after enable_crtc */
 510         /* TODO: OPP FMT, ABM. etc. should be done here. */
 511         /* or FPGA now. instance 0 only. TODO: move to opp.c */
 512
 513         inst_offset = reg_offsets[pipe_ctx->stream_res.tg->inst].fmt;
 514
 515         pipe_ctx->stream_res.opp->funcs->opp_program_fmt(
 516                                 pipe_ctx->stream_res.opp,
 517                                 &stream->bit_depth_params,
 518                                 &stream->clamping);
 519 #endif
 520         /* program otg blank color */
 521         color_space = stream->output_color_space;
 522         color_space_to_black_color(dc, color_space, &black_color);
 523
 524         if (pipe_ctx->stream_res.tg->funcs->set_blank_color)
 525                 pipe_ctx->stream_res.tg->funcs->set_blank_color(
 526                                 pipe_ctx->stream_res.tg,
 527                                 &black_color);
 528
 529         if (pipe_ctx->stream_res.tg->funcs->is_blanked &&
 530                         !pipe_ctx->stream_res.tg->funcs->is_blanked(pipe_ctx->stream_res.tg)) {
 531                 pipe_ctx->stream_res.tg->funcs->set_blank(pipe_ctx->stream_res.tg, true);
 532                 hwss_wait_for_blank_complete(pipe_ctx->stream_res.tg);
 533                 false_optc_underflow_wa(dc, pipe_ctx->stream, pipe_ctx->stream_res.tg);
 534         }
 535
 536         /* VTG is  within DCHUB command block. DCFCLK is always on */
 537         if (false == pipe_ctx->stream_res.tg->funcs->enable_crtc(pipe_ctx->stream_res.tg)) {
 538                 BREAK_TO_DEBUGGER();
 539                 return DC_ERROR_UNEXPECTED;
 540         }
 541
 542         /* TODO program crtc source select for non-virtual signal*/
 543         /* TODO program FMT */
 544         /* TODO setup link_enc */
 545         /* TODO set stream attributes */
 546         /* TODO program audio */
 547         /* TODO enable stream if timing changed */
 548         /* TODO unblank stream if DP */
 549
 550         return DC_OK;
 551 }
 552
 553 static void reset_back_end_for_pipe(
 554                 struct dc *dc,
 555                 struct pipe_ctx *pipe_ctx,
 556                 struct dc_state *context)
 557 {
 558         int i;
 559
 560         if (pipe_ctx->stream_res.stream_enc == NULL) {
 561                 pipe_ctx->stream = NULL;
 562                 return;
 563         }
 564
 565         if (!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) {
 566                 /* DPMS may already disable */
 567                 if (!pipe_ctx->stream->dpms_off)
 568                         core_link_disable_stream(pipe_ctx, FREE_ACQUIRED_RESOURCE);
 569         }
 570
 571         /* by upper caller loop, parent pipe: pipe0, will be reset last.
 572          * back end share by all pipes and will be disable only when disable
 573          * parent pipe.
 574          */
 575         if (pipe_ctx->top_pipe == NULL) {
 576                 pipe_ctx->stream_res.tg->funcs->disable_crtc(pipe_ctx->stream_res.tg);
 577
 578                 pipe_ctx->stream_res.tg->funcs->enable_optc_clock(pipe_ctx->stream_res.tg, false);
 579         }
 580
 581         for (i = 0; i < dc->res_pool->pipe_count; i++)
 582                 if (&dc->current_state->res_ctx.pipe_ctx[i] == pipe_ctx)
 583                         break;
 584
 585         if (i == dc->res_pool->pipe_count)
 586                 return;
 587
 588         pipe_ctx->stream = NULL;
 589         dm_logger_write(dc->ctx->logger, LOG_DEBUG,
 590                                         "Reset back end for pipe %d, tg:%d\n",
 591                                         pipe_ctx->pipe_idx, pipe_ctx->stream_res.tg->inst);
 592 }
 593
 594 static void dcn10_verify_allow_pstate_change_high(struct dc *dc)
 595 {
 596         static bool should_log_hw_state; /* prevent hw state log by default */
 597
 598         if (!hubbub1_verify_allow_pstate_change_high(dc->res_pool->hubbub)) {
 599                 if (should_log_hw_state) {
 600                         dcn10_log_hw_state(dc);
 601                 }
 602
 603                 BREAK_TO_DEBUGGER();
 604         }
 605 }
 606
 607 /* trigger HW to start disconnect plane from stream on the next vsync */
 608 static void plane_atomic_disconnect(struct dc *dc, struct pipe_ctx *pipe_ctx)
 609 {
 610         int fe_idx = pipe_ctx->pipe_idx;
 611         struct hubp *hubp = dc->res_pool->hubps[fe_idx];
 612         struct mpc *mpc = dc->res_pool->mpc;
 613         int opp_id;
 614         struct mpc_tree *mpc_tree_params;
 615         struct mpcc *mpcc_to_remove = NULL;
 616
 617         /* look at tree rather than mi here to know if we already reset */
 618         for (opp_id = 0; opp_id < dc->res_pool->pipe_count; opp_id++) {
 619                 struct output_pixel_processor *opp = dc->res_pool->opps[opp_id];
 620
 621                 mpc_tree_params = &(opp->mpc_tree_params);
 622                 mpcc_to_remove = mpc->funcs->get_mpcc_for_dpp(mpc_tree_params, fe_idx);
 623                 if (mpcc_to_remove != NULL)
 624                         break;
 625         }
 626
 627         /*Already reset*/
 628         if (opp_id == dc->res_pool->pipe_count)
 629                 return;
 630
 631         mpc->funcs->remove_mpcc(mpc, mpc_tree_params, mpcc_to_remove);
 632         dc->res_pool->opps[opp_id]->mpcc_disconnect_pending[fe_idx] = true;
 633
 634         dc->optimized_required = true;
 635
 636         if (hubp->funcs->hubp_disconnect)
 637                 hubp->funcs->hubp_disconnect(hubp);
 638
 639         if (dc->debug.sanity_checks)
 640                 dcn10_verify_allow_pstate_change_high(dc);
 641 }
 642
 643 static void plane_atomic_power_down(struct dc *dc, int fe_idx)
 644 {
 645         struct dce_hwseq *hws = dc->hwseq;
 646         struct dpp *dpp = dc->res_pool->dpps[fe_idx];
 647
 648         if (REG(DC_IP_REQUEST_CNTL)) {
 649                 REG_SET(DC_IP_REQUEST_CNTL, 0,
 650                                 IP_REQUEST_EN, 1);
 651                 dpp_pg_control(hws, fe_idx, false);
 652                 hubp_pg_control(hws, fe_idx, false);
 653                 dpp->funcs->dpp_reset(dpp);
 654                 REG_SET(DC_IP_REQUEST_CNTL, 0,
 655                                 IP_REQUEST_EN, 0);
 656                 dm_logger_write(dc->ctx->logger, LOG_DEBUG,
 657                                 "Power gated front end %d\n", fe_idx);
 658         }
 659 }
 660
 661 /* disable HW used by plane.
 662  * note:  cannot disable until disconnect is complete
 663  */
 664 static void plane_atomic_disable(struct dc *dc, struct pipe_ctx *pipe_ctx)
 665 {
 666         int fe_idx = pipe_ctx->pipe_idx;
 667         struct dce_hwseq *hws = dc->hwseq;
 668         struct hubp *hubp = dc->res_pool->hubps[fe_idx];
 669         int opp_id = hubp->opp_id;
 670
 671         dc->hwss.wait_for_mpcc_disconnect(dc, dc->res_pool, pipe_ctx);
 672
 673         REG_UPDATE(HUBP_CLK_CNTL[fe_idx],
 674                         HUBP_CLOCK_ENABLE, 0);
 675         REG_UPDATE(DPP_CONTROL[fe_idx],
 676                         DPP_CLOCK_ENABLE, 0);
 677
 678         if (opp_id != 0xf && dc->res_pool->opps[opp_id]->mpc_tree_params.opp_list == NULL)
 679                 REG_UPDATE(OPP_PIPE_CONTROL[opp_id],
 680                                 OPP_PIPE_CLOCK_EN, 0);
 681
 682         hubp->power_gated = true;
 683         dc->optimized_required = false; /* We're powering off, no need to optimize */
 684
 685         plane_atomic_power_down(dc, fe_idx);
 686
 687         pipe_ctx->stream = NULL;
 688         memset(&pipe_ctx->stream_res, 0, sizeof(pipe_ctx->stream_res));
 689         memset(&pipe_ctx->plane_res, 0, sizeof(pipe_ctx->plane_res));
 690         pipe_ctx->top_pipe = NULL;
 691         pipe_ctx->bottom_pipe = NULL;
 692         pipe_ctx->plane_state = NULL;
 693 }
 694
 695 static void dcn10_disable_plane(struct dc *dc, struct pipe_ctx *pipe_ctx)
 696 {
 697         if (dc->res_pool->hubps[pipe_ctx->pipe_idx]->power_gated)
 698                 return;
 699
 700         plane_atomic_disable(dc, pipe_ctx);
 701
 702         apply_DEGVIDCN10_253_wa(dc);
 703
 704         dm_logger_write(dc->ctx->logger, LOG_DC,
 705                                         "Power down front end %d\n",
 706                                         pipe_ctx->pipe_idx);
 707 }
 708
 709 static void dcn10_init_hw(struct dc *dc)
 710 {
 711         int i;
 712         struct abm *abm = dc->res_pool->abm;
 713         struct dmcu *dmcu = dc->res_pool->dmcu;
 714         struct dce_hwseq *hws = dc->hwseq;
 715         struct dc_bios *dcb = dc->ctx->dc_bios;
 716         struct dc_state  *context = dc->current_state;
 717
 718         if (IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) {
 719                 REG_WRITE(REFCLK_CNTL, 0);
 720                 REG_UPDATE(DCHUBBUB_GLOBAL_TIMER_CNTL, DCHUBBUB_GLOBAL_TIMER_ENABLE, 1);
 721                 REG_WRITE(DIO_MEM_PWR_CTRL, 0);
 722
 723                 if (!dc->debug.disable_clock_gate) {
 724                         /* enable all DCN clock gating */
 725                         REG_WRITE(DCCG_GATE_DISABLE_CNTL, 0);
 726
 727                         REG_WRITE(DCCG_GATE_DISABLE_CNTL2, 0);
 728
 729                         REG_UPDATE(DCFCLK_CNTL, DCFCLK_GATE_DIS, 0);
 730                 }
 731
 732                 enable_power_gating_plane(dc->hwseq, true);
 733                 return;
 734         }
 735         /* end of FPGA. Below if real ASIC */
 736
 737         if (!dcb->funcs->is_accelerated_mode(dcb)) {
 738                 bios_golden_init(dc);
 739                 disable_vga(dc->hwseq);
 740         }
 741
 742         for (i = 0; i < dc->link_count; i++) {
 743                 /* Power up AND update implementation according to the
 744                  * required signal (which may be different from the
 745                  * default signal on connector).
 746                  */
 747                 struct dc_link *link = dc->links[i];
 748
 749                 if (link->link_enc->connector.id == CONNECTOR_ID_EDP)
 750                         dc->hwss.edp_power_control(link, true);
 751
 752                 link->link_enc->funcs->hw_init(link->link_enc);
 753         }
 754
 755         for (i = 0; i < dc->res_pool->pipe_count; i++) {
 756                 struct timing_generator *tg = dc->res_pool->timing_generators[i];
 757
 758                 if (tg->funcs->is_tg_enabled(tg))
 759                         tg->funcs->lock(tg);
 760         }
 761
 762         /* Blank controller using driver code instead of
 763          * command table.
 764          */
 765         for (i = 0; i < dc->res_pool->pipe_count; i++) {
 766                 struct timing_generator *tg = dc->res_pool->timing_generators[i];
 767
 768                 if (tg->funcs->is_tg_enabled(tg)) {
 769                         tg->funcs->set_blank(tg, true);
 770                         hwss_wait_for_blank_complete(tg);
 771                 }
 772         }
 773
 774         /* Reset all MPCC muxes */
 775         dc->res_pool->mpc->funcs->mpc_init(dc->res_pool->mpc);
 776
 777         for (i = 0; i < dc->res_pool->pipe_count; i++) {
 778                 struct timing_generator *tg = dc->res_pool->timing_generators[i];
 779                 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
 780                 struct hubp *hubp = dc->res_pool->hubps[i];
 781
 782                 pipe_ctx->stream_res.tg = tg;
 783                 pipe_ctx->pipe_idx = i;
 784
 785                 pipe_ctx->plane_res.hubp = hubp;
 786                 hubp->mpcc_id = i;
 787                 hubp->opp_id = 0xf;
 788                 hubp->power_gated = false;
 789
 790                 dc->res_pool->opps[i]->mpc_tree_params.opp_id = dc->res_pool->opps[i]->inst;
 791                 dc->res_pool->opps[i]->mpc_tree_params.opp_list = NULL;
 792                 dc->res_pool->opps[i]->mpcc_disconnect_pending[i] = true;
 793                 pipe_ctx->stream_res.opp = dc->res_pool->opps[i];
 794
 795                 plane_atomic_disconnect(dc, pipe_ctx);
 796         }
 797
 798         for (i = 0; i < dc->res_pool->pipe_count; i++) {
 799                 struct timing_generator *tg = dc->res_pool->timing_generators[i];
 800
 801                 if (tg->funcs->is_tg_enabled(tg))
 802                         tg->funcs->unlock(tg);
 803         }
 804
 805         for (i = 0; i < dc->res_pool->pipe_count; i++) {
 806                 struct timing_generator *tg = dc->res_pool->timing_generators[i];
 807                 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
 808
 809                 dcn10_disable_plane(dc, pipe_ctx);
 810
 811                 pipe_ctx->stream_res.tg = NULL;
 812                 pipe_ctx->plane_res.hubp = NULL;
 813
 814                 tg->funcs->tg_init(tg);
 815         }
 816
 817         for (i = 0; i < dc->res_pool->audio_count; i++) {
 818                 struct audio *audio = dc->res_pool->audios[i];
 819
 820                 audio->funcs->hw_init(audio);
 821         }
 822
 823         if (abm != NULL) {
 824                 abm->funcs->init_backlight(abm);
 825                 abm->funcs->abm_init(abm);
 826         }
 827
 828         if (dmcu != NULL)
 829                 dmcu->funcs->dmcu_init(dmcu);
 830
 831         /* power AFMT HDMI memory TODO: may move to dis/en output save power*/
 832         REG_WRITE(DIO_MEM_PWR_CTRL, 0);
 833
 834         if (!dc->debug.disable_clock_gate) {
 835                 /* enable all DCN clock gating */
 836                 REG_WRITE(DCCG_GATE_DISABLE_CNTL, 0);
 837
 838                 REG_WRITE(DCCG_GATE_DISABLE_CNTL2, 0);
 839
 840                 REG_UPDATE(DCFCLK_CNTL, DCFCLK_GATE_DIS, 0);
 841         }
 842
 843         enable_power_gating_plane(dc->hwseq, true);
 844 }
 845
 846 static void reset_hw_ctx_wrap(
 847                 struct dc *dc,
 848                 struct dc_state *context)
 849 {
 850         int i;
 851
 852         /* Reset Back End*/
 853         for (i = dc->res_pool->pipe_count - 1; i >= 0 ; i--) {
 854                 struct pipe_ctx *pipe_ctx_old =
 855                         &dc->current_state->res_ctx.pipe_ctx[i];
 856                 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
 857
 858                 if (!pipe_ctx_old->stream)
 859                         continue;
 860
 861                 if (pipe_ctx_old->top_pipe)
 862                         continue;
 863
 864                 if (!pipe_ctx->stream ||
 865                                 pipe_need_reprogram(pipe_ctx_old, pipe_ctx)) {
 866                         struct clock_source *old_clk = pipe_ctx_old->clock_source;
 867
 868                         reset_back_end_for_pipe(dc, pipe_ctx_old, dc->current_state);
 869                         if (old_clk)
 870                                 old_clk->funcs->cs_power_down(old_clk);
 871                 }
 872         }
 873
 874 }
 875
 876 static bool patch_address_for_sbs_tb_stereo(
 877                 struct pipe_ctx *pipe_ctx, PHYSICAL_ADDRESS_LOC *addr)
 878 {
 879         struct dc_plane_state *plane_state = pipe_ctx->plane_state;
 880         bool sec_split = pipe_ctx->top_pipe &&
 881                         pipe_ctx->top_pipe->plane_state == pipe_ctx->plane_state;
 882         if (sec_split && plane_state->address.type == PLN_ADDR_TYPE_GRPH_STEREO &&
 883                 (pipe_ctx->stream->timing.timing_3d_format ==
 884                  TIMING_3D_FORMAT_SIDE_BY_SIDE ||
 885                  pipe_ctx->stream->timing.timing_3d_format ==
 886                  TIMING_3D_FORMAT_TOP_AND_BOTTOM)) {
 887                 *addr = plane_state->address.grph_stereo.left_addr;
 888                 plane_state->address.grph_stereo.left_addr =
 889                 plane_state->address.grph_stereo.right_addr;
 890                 return true;
 891         } else {
 892                 if (pipe_ctx->stream->view_format != VIEW_3D_FORMAT_NONE &&
 893                         plane_state->address.type != PLN_ADDR_TYPE_GRPH_STEREO) {
 894                         plane_state->address.type = PLN_ADDR_TYPE_GRPH_STEREO;
 895                         plane_state->address.grph_stereo.right_addr =
 896                         plane_state->address.grph_stereo.left_addr;
 897                 }
 898         }
 899         return false;
 900 }
 901
 902
 903
 904 static void dcn10_update_plane_addr(const struct dc *dc, struct pipe_ctx *pipe_ctx)
 905 {
 906         bool addr_patched = false;
 907         PHYSICAL_ADDRESS_LOC addr;
 908         struct dc_plane_state *plane_state = pipe_ctx->plane_state;
 909
 910         if (plane_state == NULL)
 911                 return;
 912         addr_patched = patch_address_for_sbs_tb_stereo(pipe_ctx, &addr);
 913         pipe_ctx->plane_res.hubp->funcs->hubp_program_surface_flip_and_addr(
 914                         pipe_ctx->plane_res.hubp,
 915                         &plane_state->address,
 916                         plane_state->flip_immediate);
 917         plane_state->status.requested_address = plane_state->address;
 918         if (addr_patched)
 919                 pipe_ctx->plane_state->address.grph_stereo.left_addr = addr;
 920 }
 921
 922 static bool dcn10_set_input_transfer_func(struct pipe_ctx *pipe_ctx,
 923                                           const struct dc_plane_state *plane_state)
 924 {
 925         struct dpp *dpp_base = pipe_ctx->plane_res.dpp;
 926         const struct dc_transfer_func *tf = NULL;
 927         bool result = true;
 928
 929         if (dpp_base == NULL)
 930                 return false;
 931
 932         if (plane_state->in_transfer_func)
 933                 tf = plane_state->in_transfer_func;
 934
 935         if (plane_state->gamma_correction && dce_use_lut(plane_state))
 936                 dpp_base->funcs->dpp_program_input_lut(dpp_base, plane_state->gamma_correction);
 937
 938         if (tf == NULL)
 939                 dpp_base->funcs->dpp_set_degamma(dpp_base, IPP_DEGAMMA_MODE_BYPASS);
 940         else if (tf->type == TF_TYPE_PREDEFINED) {
 941                 switch (tf->tf) {
 942                 case TRANSFER_FUNCTION_SRGB:
 943                         dpp_base->funcs->dpp_set_degamma(dpp_base, IPP_DEGAMMA_MODE_HW_sRGB);
 944                         break;
 945                 case TRANSFER_FUNCTION_BT709:
 946                         dpp_base->funcs->dpp_set_degamma(dpp_base, IPP_DEGAMMA_MODE_HW_xvYCC);
 947                         break;
 948                 case TRANSFER_FUNCTION_LINEAR:
 949                         dpp_base->funcs->dpp_set_degamma(dpp_base, IPP_DEGAMMA_MODE_BYPASS);
 950                         break;
 951                 case TRANSFER_FUNCTION_PQ:
 952                 default:
 953                         result = false;
 954                         break;
 955                 }
 956         } else if (tf->type == TF_TYPE_BYPASS) {
 957                 dpp_base->funcs->dpp_set_degamma(dpp_base, IPP_DEGAMMA_MODE_BYPASS);
 958         } else {
 959                 /*TF_TYPE_DISTRIBUTED_POINTS*/
 960                 result = false;
 961         }
 962
 963         return result;
 964 }
 965
 966
 967
 968
 969
 970 static bool
 971 dcn10_set_output_transfer_func(struct pipe_ctx *pipe_ctx,
 972                                const struct dc_stream_state *stream)
 973 {
 974         struct dpp *dpp = pipe_ctx->plane_res.dpp;
 975
 976         if (dpp == NULL)
 977                 return false;
 978
 979         dpp->regamma_params.hw_points_num = GAMMA_HW_POINTS_NUM;
 980
 981         if (stream->out_transfer_func &&
 982             stream->out_transfer_func->type == TF_TYPE_PREDEFINED &&
 983             stream->out_transfer_func->tf == TRANSFER_FUNCTION_SRGB)
 984                 dpp->funcs->dpp_program_regamma_pwl(dpp, NULL, OPP_REGAMMA_SRGB);
 985
 986         /* dcn10_translate_regamma_to_hw_format takes 750us, only do it when full
 987          * update.
 988          */
 989         else if (cm_helper_translate_curve_to_hw_format(
 990                         stream->out_transfer_func,
 991                         &dpp->regamma_params, false)) {
 992                 dpp->funcs->dpp_program_regamma_pwl(
 993                                 dpp,
 994                                 &dpp->regamma_params, OPP_REGAMMA_USER);
 995         } else
 996                 dpp->funcs->dpp_program_regamma_pwl(dpp, NULL, OPP_REGAMMA_BYPASS);
 997
 998         return true;
 999 }
1000
1001 static void dcn10_pipe_control_lock(
1002         struct dc *dc,
1003         struct pipe_ctx *pipe,
1004         bool lock)
1005 {
1006         struct hubp *hubp = NULL;
1007         hubp = dc->res_pool->hubps[pipe->pipe_idx];
1008         /* use TG master update lock to lock everything on the TG
1009          * therefore only top pipe need to lock
1010          */
1011         if (pipe->top_pipe)
1012                 return;
1013
1014         if (dc->debug.sanity_checks)
1015                 dcn10_verify_allow_pstate_change_high(dc);
1016
1017         if (lock)
1018                 pipe->stream_res.tg->funcs->lock(pipe->stream_res.tg);
1019         else
1020                 pipe->stream_res.tg->funcs->unlock(pipe->stream_res.tg);
1021
1022         if (dc->debug.sanity_checks)
1023                 dcn10_verify_allow_pstate_change_high(dc);
1024 }
1025
1026 static bool wait_for_reset_trigger_to_occur(
1027         struct dc_context *dc_ctx,
1028         struct timing_generator *tg)
1029 {
1030         bool rc = false;
1031
1032         /* To avoid endless loop we wait at most
1033          * frames_to_wait_on_triggered_reset frames for the reset to occur. */
1034         const uint32_t frames_to_wait_on_triggered_reset = 10;
1035         int i;
1036
1037         for (i = 0; i < frames_to_wait_on_triggered_reset; i++) {
1038
1039                 if (!tg->funcs->is_counter_moving(tg)) {
1040                         DC_ERROR("TG counter is not moving!\n");
1041                         break;
1042                 }
1043
1044                 if (tg->funcs->did_triggered_reset_occur(tg)) {
1045                         rc = true;
1046                         /* usually occurs at i=1 */
1047                         DC_SYNC_INFO("GSL: reset occurred at wait count: %d\n",
1048                                         i);
1049                         break;
1050                 }
1051
1052                 /* Wait for one frame. */
1053                 tg->funcs->wait_for_state(tg, CRTC_STATE_VACTIVE);
1054                 tg->funcs->wait_for_state(tg, CRTC_STATE_VBLANK);
1055         }
1056
1057         if (false == rc)
1058                 DC_ERROR("GSL: Timeout on reset trigger!\n");
1059
1060         return rc;
1061 }
1062
1063 static void dcn10_enable_timing_synchronization(
1064         struct dc *dc,
1065         int group_index,
1066         int group_size,
1067         struct pipe_ctx *grouped_pipes[])
1068 {
1069         struct dc_context *dc_ctx = dc->ctx;
1070         int i;
1071
1072         DC_SYNC_INFO("Setting up OTG reset trigger\n");
1073
1074         for (i = 1; i < group_size; i++)
1075                 grouped_pipes[i]->stream_res.tg->funcs->enable_reset_trigger(
1076                                 grouped_pipes[i]->stream_res.tg,
1077                                 grouped_pipes[0]->stream_res.tg->inst);
1078
1079         DC_SYNC_INFO("Waiting for trigger\n");
1080
1081         /* Need to get only check 1 pipe for having reset as all the others are
1082          * synchronized. Look at last pipe programmed to reset.
1083          */
1084
1085         wait_for_reset_trigger_to_occur(dc_ctx, grouped_pipes[1]->stream_res.tg);
1086         for (i = 1; i < group_size; i++)
1087                 grouped_pipes[i]->stream_res.tg->funcs->disable_reset_trigger(
1088                                 grouped_pipes[i]->stream_res.tg);
1089
1090         DC_SYNC_INFO("Sync complete\n");
1091 }
1092
1093 static void dcn10_enable_per_frame_crtc_position_reset(
1094         struct dc *dc,
1095         int group_size,
1096         struct pipe_ctx *grouped_pipes[])
1097 {
1098         struct dc_context *dc_ctx = dc->ctx;
1099         int i;
1100
1101         DC_SYNC_INFO("Setting up\n");
1102         for (i = 0; i < group_size; i++)
1103                 grouped_pipes[i]->stream_res.tg->funcs->enable_crtc_reset(
1104                                 grouped_pipes[i]->stream_res.tg,
1105                                 grouped_pipes[i]->stream->triggered_crtc_reset.event_source->status.primary_otg_inst,
1106                                 &grouped_pipes[i]->stream->triggered_crtc_reset);
1107
1108         DC_SYNC_INFO("Waiting for trigger\n");
1109
1110         for (i = 1; i < group_size; i++)
1111                 wait_for_reset_trigger_to_occur(dc_ctx, grouped_pipes[i]->stream_res.tg);
1112
1113         DC_SYNC_INFO("Multi-display sync is complete\n");
1114 }
1115
1116 /*static void print_rq_dlg_ttu(
1117                 struct dc *core_dc,
1118                 struct pipe_ctx *pipe_ctx)
1119 {
1120         dm_logger_write(core_dc->ctx->logger, LOG_BANDWIDTH_CALCS,
1121                         "\n============== DML TTU Output parameters [%d] ==============\n"
1122                         "qos_level_low_wm: %d, \n"
1123                         "qos_level_high_wm: %d, \n"
1124                         "min_ttu_vblank: %d, \n"
1125                         "qos_level_flip: %d, \n"
1126                         "refcyc_per_req_delivery_l: %d, \n"
1127                         "qos_level_fixed_l: %d, \n"
1128                         "qos_ramp_disable_l: %d, \n"
1129                         "refcyc_per_req_delivery_pre_l: %d, \n"
1130                         "refcyc_per_req_delivery_c: %d, \n"
1131                         "qos_level_fixed_c: %d, \n"
1132                         "qos_ramp_disable_c: %d, \n"
1133                         "refcyc_per_req_delivery_pre_c: %d\n"
1134                         "=============================================================\n",
1135                         pipe_ctx->pipe_idx,
1136                         pipe_ctx->ttu_regs.qos_level_low_wm,
1137                         pipe_ctx->ttu_regs.qos_level_high_wm,
1138                         pipe_ctx->ttu_regs.min_ttu_vblank,
1139                         pipe_ctx->ttu_regs.qos_level_flip,
1140                         pipe_ctx->ttu_regs.refcyc_per_req_delivery_l,
1141                         pipe_ctx->ttu_regs.qos_level_fixed_l,
1142                         pipe_ctx->ttu_regs.qos_ramp_disable_l,
1143                         pipe_ctx->ttu_regs.refcyc_per_req_delivery_pre_l,
1144                         pipe_ctx->ttu_regs.refcyc_per_req_delivery_c,
1145                         pipe_ctx->ttu_regs.qos_level_fixed_c,
1146                         pipe_ctx->ttu_regs.qos_ramp_disable_c,
1147                         pipe_ctx->ttu_regs.refcyc_per_req_delivery_pre_c
1148                         );
1149
1150         dm_logger_write(core_dc->ctx->logger, LOG_BANDWIDTH_CALCS,
1151                         "\n============== DML DLG Output parameters [%d] ==============\n"
1152                         "refcyc_h_blank_end: %d, \n"
1153                         "dlg_vblank_end: %d, \n"
1154                         "min_dst_y_next_start: %d, \n"
1155                         "refcyc_per_htotal: %d, \n"
1156                         "refcyc_x_after_scaler: %d, \n"
1157                         "dst_y_after_scaler: %d, \n"
1158                         "dst_y_prefetch: %d, \n"
1159                         "dst_y_per_vm_vblank: %d, \n"
1160                         "dst_y_per_row_vblank: %d, \n"
1161                         "ref_freq_to_pix_freq: %d, \n"
1162                         "vratio_prefetch: %d, \n"
1163                         "refcyc_per_pte_group_vblank_l: %d, \n"
1164                         "refcyc_per_meta_chunk_vblank_l: %d, \n"
1165                         "dst_y_per_pte_row_nom_l: %d, \n"
1166                         "refcyc_per_pte_group_nom_l: %d, \n",
1167                         pipe_ctx->pipe_idx,
1168                         pipe_ctx->dlg_regs.refcyc_h_blank_end,
1169                         pipe_ctx->dlg_regs.dlg_vblank_end,
1170                         pipe_ctx->dlg_regs.min_dst_y_next_start,
1171                         pipe_ctx->dlg_regs.refcyc_per_htotal,
1172                         pipe_ctx->dlg_regs.refcyc_x_after_scaler,
1173                         pipe_ctx->dlg_regs.dst_y_after_scaler,
1174                         pipe_ctx->dlg_regs.dst_y_prefetch,
1175                         pipe_ctx->dlg_regs.dst_y_per_vm_vblank,
1176                         pipe_ctx->dlg_regs.dst_y_per_row_vblank,
1177                         pipe_ctx->dlg_regs.ref_freq_to_pix_freq,
1178                         pipe_ctx->dlg_regs.vratio_prefetch,
1179                         pipe_ctx->dlg_regs.refcyc_per_pte_group_vblank_l,
1180                         pipe_ctx->dlg_regs.refcyc_per_meta_chunk_vblank_l,
1181                         pipe_ctx->dlg_regs.dst_y_per_pte_row_nom_l,
1182                         pipe_ctx->dlg_regs.refcyc_per_pte_group_nom_l
1183                         );
1184
1185         dm_logger_write(core_dc->ctx->logger, LOG_BANDWIDTH_CALCS,
1186                         "\ndst_y_per_meta_row_nom_l: %d, \n"
1187                         "refcyc_per_meta_chunk_nom_l: %d, \n"
1188                         "refcyc_per_line_delivery_pre_l: %d, \n"
1189                         "refcyc_per_line_delivery_l: %d, \n"
1190                         "vratio_prefetch_c: %d, \n"
1191                         "refcyc_per_pte_group_vblank_c: %d, \n"
1192                         "refcyc_per_meta_chunk_vblank_c: %d, \n"
1193                         "dst_y_per_pte_row_nom_c: %d, \n"
1194                         "refcyc_per_pte_group_nom_c: %d, \n"
1195                         "dst_y_per_meta_row_nom_c: %d, \n"
1196                         "refcyc_per_meta_chunk_nom_c: %d, \n"
1197                         "refcyc_per_line_delivery_pre_c: %d, \n"
1198                         "refcyc_per_line_delivery_c: %d \n"
1199                         "========================================================\n",
1200                         pipe_ctx->dlg_regs.dst_y_per_meta_row_nom_l,
1201                         pipe_ctx->dlg_regs.refcyc_per_meta_chunk_nom_l,
1202                         pipe_ctx->dlg_regs.refcyc_per_line_delivery_pre_l,
1203                         pipe_ctx->dlg_regs.refcyc_per_line_delivery_l,
1204                         pipe_ctx->dlg_regs.vratio_prefetch_c,
1205                         pipe_ctx->dlg_regs.refcyc_per_pte_group_vblank_c,
1206                         pipe_ctx->dlg_regs.refcyc_per_meta_chunk_vblank_c,
1207                         pipe_ctx->dlg_regs.dst_y_per_pte_row_nom_c,
1208                         pipe_ctx->dlg_regs.refcyc_per_pte_group_nom_c,
1209                         pipe_ctx->dlg_regs.dst_y_per_meta_row_nom_c,
1210                         pipe_ctx->dlg_regs.refcyc_per_meta_chunk_nom_c,
1211                         pipe_ctx->dlg_regs.refcyc_per_line_delivery_pre_c,
1212                         pipe_ctx->dlg_regs.refcyc_per_line_delivery_c
1213                         );
1214
1215         dm_logger_write(core_dc->ctx->logger, LOG_BANDWIDTH_CALCS,
1216                         "\n============== DML RQ Output parameters [%d] ==============\n"
1217                         "chunk_size: %d \n"
1218                         "min_chunk_size: %d \n"
1219                         "meta_chunk_size: %d \n"
1220                         "min_meta_chunk_size: %d \n"
1221                         "dpte_group_size: %d \n"
1222                         "mpte_group_size: %d \n"
1223                         "swath_height: %d \n"
1224                         "pte_row_height_linear: %d \n"
1225                         "========================================================\n",
1226                         pipe_ctx->pipe_idx,
1227                         pipe_ctx->rq_regs.rq_regs_l.chunk_size,
1228                         pipe_ctx->rq_regs.rq_regs_l.min_chunk_size,
1229                         pipe_ctx->rq_regs.rq_regs_l.meta_chunk_size,
1230                         pipe_ctx->rq_regs.rq_regs_l.min_meta_chunk_size,
1231                         pipe_ctx->rq_regs.rq_regs_l.dpte_group_size,
1232                         pipe_ctx->rq_regs.rq_regs_l.mpte_group_size,
1233                         pipe_ctx->rq_regs.rq_regs_l.swath_height,
1234                         pipe_ctx->rq_regs.rq_regs_l.pte_row_height_linear
1235                         );
1236 }
1237 */
1238
1239 static void mmhub_read_vm_system_aperture_settings(struct dcn10_hubp *hubp1,
1240                 struct vm_system_aperture_param *apt,
1241                 struct dce_hwseq *hws)
1242 {
1243         PHYSICAL_ADDRESS_LOC physical_page_number;
1244         uint32_t logical_addr_low;
1245         uint32_t logical_addr_high;
1246
1247         REG_GET(MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB,
1248                         PHYSICAL_PAGE_NUMBER_MSB, &physical_page_number.high_part);
1249         REG_GET(MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB,
1250                         PHYSICAL_PAGE_NUMBER_LSB, &physical_page_number.low_part);
1251
1252         REG_GET(MC_VM_SYSTEM_APERTURE_LOW_ADDR,
1253                         LOGICAL_ADDR, &logical_addr_low);
1254
1255         REG_GET(MC_VM_SYSTEM_APERTURE_HIGH_ADDR,
1256                         LOGICAL_ADDR, &logical_addr_high);
1257
1258         apt->sys_default.quad_part =  physical_page_number.quad_part << 12;
1259         apt->sys_low.quad_part =  (int64_t)logical_addr_low << 18;
1260         apt->sys_high.quad_part =  (int64_t)logical_addr_high << 18;
1261 }
1262
1263 /* Temporary read settings, future will get values from kmd directly */
1264 static void mmhub_read_vm_context0_settings(struct dcn10_hubp *hubp1,
1265                 struct vm_context0_param *vm0,
1266                 struct dce_hwseq *hws)
1267 {
1268         PHYSICAL_ADDRESS_LOC fb_base;
1269         PHYSICAL_ADDRESS_LOC fb_offset;
1270         uint32_t fb_base_value;
1271         uint32_t fb_offset_value;
1272
1273         REG_GET(DCHUBBUB_SDPIF_FB_BASE, SDPIF_FB_BASE, &fb_base_value);
1274         REG_GET(DCHUBBUB_SDPIF_FB_OFFSET, SDPIF_FB_OFFSET, &fb_offset_value);
1275
1276         REG_GET(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32,
1277                         PAGE_DIRECTORY_ENTRY_HI32, &vm0->pte_base.high_part);
1278         REG_GET(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32,
1279                         PAGE_DIRECTORY_ENTRY_LO32, &vm0->pte_base.low_part);
1280
1281         REG_GET(VM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32,
1282                         LOGICAL_PAGE_NUMBER_HI4, &vm0->pte_start.high_part);
1283         REG_GET(VM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32,
1284                         LOGICAL_PAGE_NUMBER_LO32, &vm0->pte_start.low_part);
1285
1286         REG_GET(VM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32,
1287                         LOGICAL_PAGE_NUMBER_HI4, &vm0->pte_end.high_part);
1288         REG_GET(VM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32,
1289                         LOGICAL_PAGE_NUMBER_LO32, &vm0->pte_end.low_part);
1290
1291         REG_GET(VM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32,
1292                         PHYSICAL_PAGE_ADDR_HI4, &vm0->fault_default.high_part);
1293         REG_GET(VM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32,
1294                         PHYSICAL_PAGE_ADDR_LO32, &vm0->fault_default.low_part);
1295
1296         /*
1297          * The values in VM_CONTEXT0_PAGE_TABLE_BASE_ADDR is in UMA space.
1298          * Therefore we need to do
1299          * DCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR = VM_CONTEXT0_PAGE_TABLE_BASE_ADDR
1300          * - DCHUBBUB_SDPIF_FB_OFFSET + DCHUBBUB_SDPIF_FB_BASE
1301          */
1302         fb_base.quad_part = (uint64_t)fb_base_value << 24;
1303         fb_offset.quad_part = (uint64_t)fb_offset_value << 24;
1304         vm0->pte_base.quad_part += fb_base.quad_part;
1305         vm0->pte_base.quad_part -= fb_offset.quad_part;
1306 }
1307
1308
1309 static void dcn10_program_pte_vm(struct dce_hwseq *hws, struct hubp *hubp)
1310 {
1311         struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp);
1312         struct vm_system_aperture_param apt = { {{ 0 } } };
1313         struct vm_context0_param vm0 = { { { 0 } } };
1314
1315         mmhub_read_vm_system_aperture_settings(hubp1, &apt, hws);
1316         mmhub_read_vm_context0_settings(hubp1, &vm0, hws);
1317
1318         hubp->funcs->hubp_set_vm_system_aperture_settings(hubp, &apt);
1319         hubp->funcs->hubp_set_vm_context0_settings(hubp, &vm0);
1320 }
1321
1322 static void dcn10_enable_plane(
1323         struct dc *dc,
1324         struct pipe_ctx *pipe_ctx,
1325         struct dc_state *context)
1326 {
1327         struct dce_hwseq *hws = dc->hwseq;
1328
1329         if (dc->debug.sanity_checks) {
1330                 dcn10_verify_allow_pstate_change_high(dc);
1331         }
1332
1333         undo_DEGVIDCN10_253_wa(dc);
1334
1335         power_on_plane(dc->hwseq,
1336                 pipe_ctx->pipe_idx);
1337
1338         /* enable DCFCLK current DCHUB */
1339         REG_UPDATE(HUBP_CLK_CNTL[pipe_ctx->pipe_idx],
1340                         HUBP_CLOCK_ENABLE, 1);
1341
1342         /* make sure OPP_PIPE_CLOCK_EN = 1 */
1343         REG_UPDATE(OPP_PIPE_CONTROL[pipe_ctx->stream_res.tg->inst],
1344                         OPP_PIPE_CLOCK_EN, 1);
1345
1346 /* TODO: enable/disable in dm as per update type.
1347         if (plane_state) {
1348                 dm_logger_write(dc->ctx->logger, LOG_DC,
1349                                 "Pipe:%d 0x%x: addr hi:0x%x, "
1350                                 "addr low:0x%x, "
1351                                 "src: %d, %d, %d,"
1352                                 " %d; dst: %d, %d, %d, %d;\n",
1353                                 pipe_ctx->pipe_idx,
1354                                 plane_state,
1355                                 plane_state->address.grph.addr.high_part,
1356                                 plane_state->address.grph.addr.low_part,
1357                                 plane_state->src_rect.x,
1358                                 plane_state->src_rect.y,
1359                                 plane_state->src_rect.width,
1360                                 plane_state->src_rect.height,
1361                                 plane_state->dst_rect.x,
1362                                 plane_state->dst_rect.y,
1363                                 plane_state->dst_rect.width,
1364                                 plane_state->dst_rect.height);
1365
1366                 dm_logger_write(dc->ctx->logger, LOG_DC,
1367                                 "Pipe %d: width, height, x, y         format:%d\n"
1368                                 "viewport:%d, %d, %d, %d\n"
1369                                 "recout:  %d, %d, %d, %d\n",
1370                                 pipe_ctx->pipe_idx,
1371                                 plane_state->format,
1372                                 pipe_ctx->plane_res.scl_data.viewport.width,
1373                                 pipe_ctx->plane_res.scl_data.viewport.height,
1374                                 pipe_ctx->plane_res.scl_data.viewport.x,
1375                                 pipe_ctx->plane_res.scl_data.viewport.y,
1376                                 pipe_ctx->plane_res.scl_data.recout.width,
1377                                 pipe_ctx->plane_res.scl_data.recout.height,
1378                                 pipe_ctx->plane_res.scl_data.recout.x,
1379                                 pipe_ctx->plane_res.scl_data.recout.y);
1380                 print_rq_dlg_ttu(dc, pipe_ctx);
1381         }
1382 */
1383         if (dc->config.gpu_vm_support)
1384                 dcn10_program_pte_vm(hws, pipe_ctx->plane_res.hubp);
1385
1386         if (dc->debug.sanity_checks) {
1387                 dcn10_verify_allow_pstate_change_high(dc);
1388         }
1389 }
1390
1391 static void program_gamut_remap(struct pipe_ctx *pipe_ctx)
1392 {
1393         struct dpp_grph_csc_adjustment adjust;
1394         memset(&adjust, 0, sizeof(adjust));
1395         adjust.gamut_adjust_type = GRAPHICS_GAMUT_ADJUST_TYPE_BYPASS;
1396
1397
1398         if (pipe_ctx->stream->gamut_remap_matrix.enable_remap == true) {
1399                 adjust.gamut_adjust_type = GRAPHICS_GAMUT_ADJUST_TYPE_SW;
1400                 adjust.temperature_matrix[0] =
1401                                 pipe_ctx->stream->
1402                                 gamut_remap_matrix.matrix[0];
1403                 adjust.temperature_matrix[1] =
1404                                 pipe_ctx->stream->
1405                                 gamut_remap_matrix.matrix[1];
1406                 adjust.temperature_matrix[2] =
1407                                 pipe_ctx->stream->
1408                                 gamut_remap_matrix.matrix[2];
1409                 adjust.temperature_matrix[3] =
1410                                 pipe_ctx->stream->
1411                                 gamut_remap_matrix.matrix[4];
1412                 adjust.temperature_matrix[4] =
1413                                 pipe_ctx->stream->
1414                                 gamut_remap_matrix.matrix[5];
1415                 adjust.temperature_matrix[5] =
1416                                 pipe_ctx->stream->
1417                                 gamut_remap_matrix.matrix[6];
1418                 adjust.temperature_matrix[6] =
1419                                 pipe_ctx->stream->
1420                                 gamut_remap_matrix.matrix[8];
1421                 adjust.temperature_matrix[7] =
1422                                 pipe_ctx->stream->
1423                                 gamut_remap_matrix.matrix[9];
1424                 adjust.temperature_matrix[8] =
1425                                 pipe_ctx->stream->
1426                                 gamut_remap_matrix.matrix[10];
1427         }
1428
1429         pipe_ctx->plane_res.dpp->funcs->dpp_set_gamut_remap(pipe_ctx->plane_res.dpp, &adjust);
1430 }
1431
1432
1433 static void program_csc_matrix(struct pipe_ctx *pipe_ctx,
1434                 enum dc_color_space colorspace,
1435                 uint16_t *matrix)
1436 {
1437         if (pipe_ctx->stream->csc_color_matrix.enable_adjustment == true) {
1438                         if (pipe_ctx->plane_res.dpp->funcs->dpp_set_csc_adjustment != NULL)
1439                                 pipe_ctx->plane_res.dpp->funcs->dpp_set_csc_adjustment(pipe_ctx->plane_res.dpp, matrix);
1440         } else {
1441                 if (pipe_ctx->plane_res.dpp->funcs->dpp_set_csc_default != NULL)
1442                         pipe_ctx->plane_res.dpp->funcs->dpp_set_csc_default(pipe_ctx->plane_res.dpp, colorspace);
1443         }
1444 }
1445
1446 static void program_output_csc(struct dc *dc,
1447                 struct pipe_ctx *pipe_ctx,
1448                 enum dc_color_space colorspace,
1449                 uint16_t *matrix,
1450                 int opp_id)
1451 {
1452         if (pipe_ctx->plane_res.dpp->funcs->dpp_set_csc_adjustment != NULL)
1453                 program_csc_matrix(pipe_ctx,
1454                                 colorspace,
1455                                 matrix);
1456 }
1457
1458 static bool is_lower_pipe_tree_visible(struct pipe_ctx *pipe_ctx)
1459 {
1460         if (pipe_ctx->plane_state->visible)
1461                 return true;
1462         if (pipe_ctx->bottom_pipe && is_lower_pipe_tree_visible(pipe_ctx->bottom_pipe))
1463                 return true;
1464         return false;
1465 }
1466
1467 static bool is_upper_pipe_tree_visible(struct pipe_ctx *pipe_ctx)
1468 {
1469         if (pipe_ctx->plane_state->visible)
1470                 return true;
1471         if (pipe_ctx->top_pipe && is_upper_pipe_tree_visible(pipe_ctx->top_pipe))
1472                 return true;
1473         return false;
1474 }
1475
1476 static bool is_pipe_tree_visible(struct pipe_ctx *pipe_ctx)
1477 {
1478         if (pipe_ctx->plane_state->visible)
1479                 return true;
1480         if (pipe_ctx->top_pipe && is_upper_pipe_tree_visible(pipe_ctx->top_pipe))
1481                 return true;
1482         if (pipe_ctx->bottom_pipe && is_lower_pipe_tree_visible(pipe_ctx->bottom_pipe))
1483                 return true;
1484         return false;
1485 }
1486
1487 static bool is_rgb_cspace(enum dc_color_space output_color_space)
1488 {
1489         switch (output_color_space) {
1490         case COLOR_SPACE_SRGB:
1491         case COLOR_SPACE_SRGB_LIMITED:
1492         case COLOR_SPACE_2020_RGB_FULLRANGE:
1493         case COLOR_SPACE_2020_RGB_LIMITEDRANGE:
1494         case COLOR_SPACE_ADOBERGB:
1495                 return true;
1496         case COLOR_SPACE_YCBCR601:
1497         case COLOR_SPACE_YCBCR709:
1498         case COLOR_SPACE_YCBCR601_LIMITED:
1499         case COLOR_SPACE_YCBCR709_LIMITED:
1500         case COLOR_SPACE_2020_YCBCR:
1501                 return false;
1502         default:
1503                 /* Add a case to switch */
1504                 BREAK_TO_DEBUGGER();
1505                 return false;
1506         }
1507 }
1508
1509 static void dcn10_get_surface_visual_confirm_color(
1510                 const struct pipe_ctx *pipe_ctx,
1511                 struct tg_color *color)
1512 {
1513         uint32_t color_value = MAX_TG_COLOR_VALUE;
1514
1515         switch (pipe_ctx->plane_res.scl_data.format) {
1516         case PIXEL_FORMAT_ARGB8888:
1517                 /* set boarder color to red */
1518                 color->color_r_cr = color_value;
1519                 break;
1520
1521         case PIXEL_FORMAT_ARGB2101010:
1522                 /* set boarder color to blue */
1523                 color->color_b_cb = color_value;
1524                 break;
1525         case PIXEL_FORMAT_420BPP8:
1526                 /* set boarder color to green */
1527                 color->color_g_y = color_value;
1528                 break;
1529         case PIXEL_FORMAT_420BPP10:
1530                 /* set boarder color to yellow */
1531                 color->color_g_y = color_value;
1532                 color->color_r_cr = color_value;
1533                 break;
1534         case PIXEL_FORMAT_FP16:
1535                 /* set boarder color to white */
1536                 color->color_r_cr = color_value;
1537                 color->color_b_cb = color_value;
1538                 color->color_g_y = color_value;
1539                 break;
1540         default:
1541                 break;
1542         }
1543 }
1544
1545 static uint16_t fixed_point_to_int_frac(
1546         struct fixed31_32 arg,
1547         uint8_t integer_bits,
1548         uint8_t fractional_bits)
1549 {
1550         int32_t numerator;
1551         int32_t divisor = 1 << fractional_bits;
1552
1553         uint16_t result;
1554
1555         uint16_t d = (uint16_t)dal_fixed31_32_floor(
1556                 dal_fixed31_32_abs(
1557                         arg));
1558
1559         if (d <= (uint16_t)(1 << integer_bits) - (1 / (uint16_t)divisor))
1560                 numerator = (uint16_t)dal_fixed31_32_floor(
1561                         dal_fixed31_32_mul_int(
1562                                 arg,
1563                                 divisor));
1564         else {
1565                 numerator = dal_fixed31_32_floor(
1566                         dal_fixed31_32_sub(
1567                                 dal_fixed31_32_from_int(
1568                                         1LL << integer_bits),
1569                                 dal_fixed31_32_recip(
1570                                         dal_fixed31_32_from_int(
1571                                                 divisor))));
1572         }
1573
1574         if (numerator >= 0)
1575                 result = (uint16_t)numerator;
1576         else
1577                 result = (uint16_t)(
1578                 (1 << (integer_bits + fractional_bits + 1)) + numerator);
1579
1580         if ((result != 0) && dal_fixed31_32_lt(
1581                 arg, dal_fixed31_32_zero))
1582                 result |= 1 << (integer_bits + fractional_bits);
1583
1584         return result;
1585 }
1586
1587 void build_prescale_params(struct  dc_bias_and_scale *bias_and_scale,
1588                 const struct dc_plane_state *plane_state)
1589 {
1590         if (plane_state->format >= SURFACE_PIXEL_FORMAT_VIDEO_BEGIN
1591                         && plane_state->format != SURFACE_PIXEL_FORMAT_INVALID
1592                         && plane_state->input_csc_color_matrix.enable_adjustment
1593                         && plane_state->coeff_reduction_factor.value != 0) {
1594                 bias_and_scale->scale_blue = fixed_point_to_int_frac(
1595                         dal_fixed31_32_mul(plane_state->coeff_reduction_factor,
1596                                         dal_fixed31_32_from_fraction(256, 255)),
1597                                 2,
1598                                 13);
1599                 bias_and_scale->scale_red = bias_and_scale->scale_blue;
1600                 bias_and_scale->scale_green = bias_and_scale->scale_blue;
1601         } else {
1602                 bias_and_scale->scale_blue = 0x2000;
1603                 bias_and_scale->scale_red = 0x2000;
1604                 bias_and_scale->scale_green = 0x2000;
1605         }
1606 }
1607
1608 static void update_dpp(struct dpp *dpp, struct dc_plane_state *plane_state)
1609 {
1610         struct dc_bias_and_scale bns_params = {0};
1611
1612         // program the input csc
1613         dpp->funcs->dpp_setup(dpp,
1614                         plane_state->format,
1615                         EXPANSION_MODE_ZERO,
1616                         plane_state->input_csc_color_matrix,
1617                         COLOR_SPACE_YCBCR601_LIMITED);
1618
1619         //set scale and bias registers
1620         build_prescale_params(&bns_params, plane_state);
1621         if (dpp->funcs->dpp_program_bias_and_scale)
1622                 dpp->funcs->dpp_program_bias_and_scale(dpp, &bns_params);
1623 }
1624
1625 static void update_mpcc(struct dc *dc, struct pipe_ctx *pipe_ctx)
1626 {
1627         struct hubp *hubp = pipe_ctx->plane_res.hubp;
1628         struct mpcc_blnd_cfg blnd_cfg;
1629         bool per_pixel_alpha = pipe_ctx->plane_state->per_pixel_alpha && pipe_ctx->bottom_pipe;
1630         int mpcc_id;
1631         struct mpcc *new_mpcc;
1632         struct mpc *mpc = dc->res_pool->mpc;
1633         struct mpc_tree *mpc_tree_params = &(pipe_ctx->stream_res.opp->mpc_tree_params);
1634
1635         /* TODO: proper fix once fpga works */
1636
1637         if (dc->debug.surface_visual_confirm)
1638                 dcn10_get_surface_visual_confirm_color(
1639                                 pipe_ctx, &blnd_cfg.black_color);
1640         else
1641                 color_space_to_black_color(
1642                         dc, pipe_ctx->stream->output_color_space,
1643                         &blnd_cfg.black_color);
1644
1645         if (per_pixel_alpha)
1646                 blnd_cfg.alpha_mode = MPCC_ALPHA_BLEND_MODE_PER_PIXEL_ALPHA;
1647         else
1648                 blnd_cfg.alpha_mode = MPCC_ALPHA_BLEND_MODE_GLOBAL_ALPHA;
1649
1650         blnd_cfg.overlap_only = false;
1651         blnd_cfg.global_alpha = 0xff;
1652         blnd_cfg.global_gain = 0xff;
1653
1654         /* DCN1.0 has output CM before MPC which seems to screw with
1655          * pre-multiplied alpha.
1656          */
1657         blnd_cfg.pre_multiplied_alpha = is_rgb_cspace(
1658                         pipe_ctx->stream->output_color_space)
1659                                         && per_pixel_alpha;
1660
1661         /*
1662          * TODO: remove hack
1663          * Note: currently there is a bug in init_hw such that
1664          * on resume from hibernate, BIOS sets up MPCC0, and
1665          * we do mpcc_remove but the mpcc cannot go to idle
1666          * after remove. This cause us to pick mpcc1 here,
1667          * which causes a pstate hang for yet unknown reason.
1668          */
1669         mpcc_id = hubp->inst;
1670
1671         /* check if this MPCC is already being used */
1672         new_mpcc = mpc->funcs->get_mpcc_for_dpp(mpc_tree_params, mpcc_id);
1673         /* remove MPCC if being used */
1674         if (new_mpcc != NULL)
1675                 mpc->funcs->remove_mpcc(mpc, mpc_tree_params, new_mpcc);
1676         else
1677                 if (dc->debug.sanity_checks)
1678                         mpc->funcs->assert_mpcc_idle_before_connect(
1679                                         dc->res_pool->mpc, mpcc_id);
1680
1681         /* Call MPC to insert new plane */
1682         new_mpcc = mpc->funcs->insert_plane(dc->res_pool->mpc,
1683                         mpc_tree_params,
1684                         &blnd_cfg,
1685                         NULL,
1686                         NULL,
1687                         hubp->inst,
1688                         mpcc_id);
1689
1690         ASSERT(new_mpcc != NULL);
1691
1692         hubp->opp_id = pipe_ctx->stream_res.opp->inst;
1693         hubp->mpcc_id = mpcc_id;
1694 }
1695
1696 static void update_scaler(struct pipe_ctx *pipe_ctx)
1697 {
1698         bool per_pixel_alpha =
1699                         pipe_ctx->plane_state->per_pixel_alpha && pipe_ctx->bottom_pipe;
1700
1701         /* TODO: proper fix once fpga works */
1702
1703         pipe_ctx->plane_res.scl_data.lb_params.alpha_en = per_pixel_alpha;
1704         pipe_ctx->plane_res.scl_data.lb_params.depth = LB_PIXEL_DEPTH_30BPP;
1705         /* scaler configuration */
1706         pipe_ctx->plane_res.dpp->funcs->dpp_set_scaler(
1707                         pipe_ctx->plane_res.dpp, &pipe_ctx->plane_res.scl_data);
1708 }
1709
1710 static void update_dchubp_dpp(
1711         struct dc *dc,
1712         struct pipe_ctx *pipe_ctx,
1713         struct dc_state *context)
1714 {
1715         struct dce_hwseq *hws = dc->hwseq;
1716         struct hubp *hubp = pipe_ctx->plane_res.hubp;
1717         struct dpp *dpp = pipe_ctx->plane_res.dpp;
1718         struct dc_plane_state *plane_state = pipe_ctx->plane_state;
1719         union plane_size size = plane_state->plane_size;
1720
1721         /* depends on DML calculation, DPP clock value may change dynamically */
1722         if (plane_state->update_flags.bits.full_update) {
1723                 enable_dppclk(
1724                         dc->hwseq,
1725                         pipe_ctx->pipe_idx,
1726                         pipe_ctx->stream_res.pix_clk_params.requested_pix_clk,
1727                         context->bw.dcn.calc_clk.dppclk_div);
1728                 dc->current_state->bw.dcn.cur_clk.dppclk_div =
1729                                 context->bw.dcn.calc_clk.dppclk_div;
1730                 context->bw.dcn.cur_clk.dppclk_div = context->bw.dcn.calc_clk.dppclk_div;
1731         }
1732
1733         /* TODO: Need input parameter to tell current DCHUB pipe tie to which OTG
1734          * VTG is within DCHUBBUB which is commond block share by each pipe HUBP.
1735          * VTG is 1:1 mapping with OTG. Each pipe HUBP will select which VTG
1736          */
1737         if (plane_state->update_flags.bits.full_update) {
1738                 REG_UPDATE(DCHUBP_CNTL[pipe_ctx->pipe_idx], HUBP_VTG_SEL, pipe_ctx->stream_res.tg->inst);
1739
1740                 hubp->funcs->hubp_setup(
1741                         hubp,
1742                         &pipe_ctx->dlg_regs,
1743                         &pipe_ctx->ttu_regs,
1744                         &pipe_ctx->rq_regs,
1745                         &pipe_ctx->pipe_dlg_param);
1746         }
1747
1748         size.grph.surface_size = pipe_ctx->plane_res.scl_data.viewport;
1749
1750         if (plane_state->update_flags.bits.full_update ||
1751                 plane_state->update_flags.bits.bpp_change)
1752                 update_dpp(dpp, plane_state);
1753
1754         if (plane_state->update_flags.bits.full_update ||
1755                 plane_state->update_flags.bits.per_pixel_alpha_change)
1756                 update_mpcc(dc, pipe_ctx);
1757
1758         if (plane_state->update_flags.bits.full_update ||
1759                 plane_state->update_flags.bits.per_pixel_alpha_change ||
1760                 plane_state->update_flags.bits.scaling_change ||
1761                 plane_state->update_flags.bits.position_change) {
1762                 update_scaler(pipe_ctx);
1763         }
1764
1765         if (plane_state->update_flags.bits.full_update ||
1766                 plane_state->update_flags.bits.scaling_change ||
1767                 plane_state->update_flags.bits.position_change) {
1768                 hubp->funcs->mem_program_viewport(
1769                         hubp,
1770                         &pipe_ctx->plane_res.scl_data.viewport,
1771                         &pipe_ctx->plane_res.scl_data.viewport_c);
1772         }
1773
1774         if (pipe_ctx->stream->cursor_attributes.address.quad_part != 0) {
1775                 dc->hwss.set_cursor_position(pipe_ctx);
1776                 dc->hwss.set_cursor_attribute(pipe_ctx);
1777         }
1778
1779         if (plane_state->update_flags.bits.full_update) {
1780                 /*gamut remap*/
1781                 program_gamut_remap(pipe_ctx);
1782
1783                 program_output_csc(dc,
1784                                 pipe_ctx,
1785                                 pipe_ctx->stream->output_color_space,
1786                                 pipe_ctx->stream->csc_color_matrix.matrix,
1787                                 hubp->opp_id);
1788         }
1789
1790         if (plane_state->update_flags.bits.full_update ||
1791                 plane_state->update_flags.bits.horizontal_mirror_change ||
1792                 plane_state->update_flags.bits.rotation_change ||
1793                 plane_state->update_flags.bits.swizzle_change ||
1794                 plane_state->update_flags.bits.dcc_change ||
1795                 plane_state->update_flags.bits.bpp_change ||
1796                 plane_state->update_flags.bits.scaling_change) {
1797                 hubp->funcs->hubp_program_surface_config(
1798                         hubp,
1799                         plane_state->format,
1800                         &plane_state->tiling_info,
1801                         &size,
1802                         plane_state->rotation,
1803                         &plane_state->dcc,
1804                         plane_state->horizontal_mirror);
1805         }
1806
1807         hubp->power_gated = false;
1808
1809         dc->hwss.update_plane_addr(dc, pipe_ctx);
1810
1811         if (is_pipe_tree_visible(pipe_ctx))
1812                 hubp->funcs->set_blank(hubp, false);
1813 }
1814
1815
1816 static void program_all_pipe_in_tree(
1817                 struct dc *dc,
1818                 struct pipe_ctx *pipe_ctx,
1819                 struct dc_state *context)
1820 {
1821
1822         if (pipe_ctx->top_pipe == NULL) {
1823
1824                 pipe_ctx->stream_res.tg->dlg_otg_param.vready_offset = pipe_ctx->pipe_dlg_param.vready_offset;
1825                 pipe_ctx->stream_res.tg->dlg_otg_param.vstartup_start = pipe_ctx->pipe_dlg_param.vstartup_start;
1826                 pipe_ctx->stream_res.tg->dlg_otg_param.vupdate_offset = pipe_ctx->pipe_dlg_param.vupdate_offset;
1827                 pipe_ctx->stream_res.tg->dlg_otg_param.vupdate_width = pipe_ctx->pipe_dlg_param.vupdate_width;
1828                 pipe_ctx->stream_res.tg->dlg_otg_param.signal =  pipe_ctx->stream->signal;
1829
1830                 pipe_ctx->stream_res.tg->funcs->program_global_sync(
1831                                 pipe_ctx->stream_res.tg);
1832
1833                 if (pipe_ctx->stream_res.tg->funcs->set_blank)
1834                         pipe_ctx->stream_res.tg->funcs->set_blank(
1835                                         pipe_ctx->stream_res.tg,
1836                                         !is_pipe_tree_visible(pipe_ctx));
1837         }
1838
1839         if (pipe_ctx->plane_state != NULL) {
1840                 struct pipe_ctx *cur_pipe_ctx =
1841                                 &dc->current_state->res_ctx.pipe_ctx[pipe_ctx->pipe_idx];
1842
1843                 if (pipe_ctx->plane_state->update_flags.bits.full_update)
1844                         dcn10_enable_plane(dc, pipe_ctx, context);
1845
1846                 update_dchubp_dpp(dc, pipe_ctx, context);
1847
1848                 if (cur_pipe_ctx->plane_state != pipe_ctx->plane_state)
1849                         dc->hwss.set_input_transfer_func(pipe_ctx, pipe_ctx->plane_state);
1850
1851                 /* dcn10_translate_regamma_to_hw_format takes 750us to finish
1852                  * only do gamma programming for full update.
1853                  * TODO: This can be further optimized/cleaned up
1854                  * Always call this for now since it does memcmp inside before
1855                  * doing heavy calculation and programming
1856                  */
1857                 if (pipe_ctx->plane_state->update_flags.bits.full_update)
1858                         dc->hwss.set_output_transfer_func(pipe_ctx, pipe_ctx->stream);
1859         }
1860
1861         if (pipe_ctx->bottom_pipe != NULL && pipe_ctx->bottom_pipe != pipe_ctx)
1862                 program_all_pipe_in_tree(dc, pipe_ctx->bottom_pipe, context);
1863 }
1864
1865 static void dcn10_pplib_apply_display_requirements(
1866         struct dc *dc,
1867         struct dc_state *context)
1868 {
1869         struct dm_pp_display_configuration *pp_display_cfg = &context->pp_display_cfg;
1870
1871         pp_display_cfg->all_displays_in_sync = false;/*todo*/
1872         pp_display_cfg->nb_pstate_switch_disable = false;
1873         pp_display_cfg->min_engine_clock_khz = context->bw.dcn.cur_clk.dcfclk_khz;
1874         pp_display_cfg->min_memory_clock_khz = context->bw.dcn.cur_clk.fclk_khz;
1875         pp_display_cfg->min_engine_clock_deep_sleep_khz = context->bw.dcn.cur_clk.dcfclk_deep_sleep_khz;
1876         pp_display_cfg->min_dcfc_deep_sleep_clock_khz = context->bw.dcn.cur_clk.dcfclk_deep_sleep_khz;
1877         pp_display_cfg->avail_mclk_switch_time_us =
1878                         context->bw.dcn.cur_clk.dram_ccm_us > 0 ? context->bw.dcn.cur_clk.dram_ccm_us : 0;
1879         pp_display_cfg->avail_mclk_switch_time_in_disp_active_us =
1880                         context->bw.dcn.cur_clk.min_active_dram_ccm_us > 0 ? context->bw.dcn.cur_clk.min_active_dram_ccm_us : 0;
1881         pp_display_cfg->min_dcfclock_khz = context->bw.dcn.cur_clk.dcfclk_khz;
1882         pp_display_cfg->disp_clk_khz = context->bw.dcn.cur_clk.dispclk_khz;
1883         dce110_fill_display_configs(context, pp_display_cfg);
1884
1885         if (memcmp(&dc->prev_display_config, pp_display_cfg, sizeof(
1886                         struct dm_pp_display_configuration)) !=  0)
1887                 dm_pp_apply_display_requirements(dc->ctx, pp_display_cfg);
1888
1889         dc->prev_display_config = *pp_display_cfg;
1890 }
1891
1892 static void optimize_shared_resources(struct dc *dc)
1893 {
1894         if (dc->current_state->stream_count == 0) {
1895                 /* S0i2 message */
1896                 dcn10_pplib_apply_display_requirements(dc, dc->current_state);
1897         }
1898
1899         if (dc->debug.pplib_wm_report_mode == WM_REPORT_OVERRIDE)
1900                 dcn_bw_notify_pplib_of_wm_ranges(dc);
1901 }
1902
1903 static void ready_shared_resources(struct dc *dc, struct dc_state *context)
1904 {
1905         /* S0i2 message */
1906         if (dc->current_state->stream_count == 0 &&
1907                         context->stream_count != 0)
1908                 dcn10_pplib_apply_display_requirements(dc, context);
1909 }
1910
1911 static struct pipe_ctx *find_top_pipe_for_stream(
1912                 struct dc *dc,
1913                 struct dc_state *context,
1914                 const struct dc_stream_state *stream)
1915 {
1916         int i;
1917
1918         for (i = 0; i < dc->res_pool->pipe_count; i++) {
1919                 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
1920                 struct pipe_ctx *old_pipe_ctx =
1921                                 &dc->current_state->res_ctx.pipe_ctx[i];
1922
1923                 if (!pipe_ctx->plane_state && !old_pipe_ctx->plane_state)
1924                         continue;
1925
1926                 if (pipe_ctx->stream != stream)
1927                         continue;
1928
1929                 if (!pipe_ctx->top_pipe)
1930                         return pipe_ctx;
1931         }
1932         return NULL;
1933 }
1934
1935 static void dcn10_apply_ctx_for_surface(
1936                 struct dc *dc,
1937                 const struct dc_stream_state *stream,
1938                 int num_planes,
1939                 struct dc_state *context)
1940 {
1941         int i;
1942         struct timing_generator *tg;
1943         struct output_pixel_processor *opp;
1944         bool removed_pipe[4] = { false };
1945         unsigned int ref_clk_mhz = dc->res_pool->ref_clock_inKhz/1000;
1946         bool program_water_mark = false;
1947
1948         struct pipe_ctx *top_pipe_to_program =
1949                         find_top_pipe_for_stream(dc, context, stream);
1950
1951         if (!top_pipe_to_program)
1952                 return;
1953
1954         opp = top_pipe_to_program->stream_res.opp;
1955
1956         tg = top_pipe_to_program->stream_res.tg;
1957
1958         tg->funcs->lock(tg);
1959
1960         if (num_planes == 0) {
1961
1962                 /* OTG blank before remove all front end */
1963                 if (tg->funcs->set_blank)
1964                         tg->funcs->set_blank(tg, true);
1965         }
1966
1967         /* Disconnect unused mpcc */
1968         for (i = 0; i < dc->res_pool->pipe_count; i++) {
1969                 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
1970                 struct pipe_ctx *old_pipe_ctx =
1971                                 &dc->current_state->res_ctx.pipe_ctx[i];
1972                 /*
1973                  * Powergate reused pipes that are not powergated
1974                  * fairly hacky right now, using opp_id as indicator
1975                  * TODO: After move dc_post to dc_update, this will
1976                  * be removed.
1977                  */
1978                 if (pipe_ctx->plane_state && !old_pipe_ctx->plane_state) {
1979                         if (old_pipe_ctx->stream_res.tg == tg &&
1980                                 old_pipe_ctx->plane_res.hubp &&
1981                                 old_pipe_ctx->plane_res.hubp->opp_id != 0xf) {
1982                                 dcn10_disable_plane(dc, pipe_ctx);
1983                                 /*
1984                                  * power down fe will unlock when calling reset, need
1985                                  * to lock it back here. Messy, need rework.
1986                                  */
1987                                 pipe_ctx->stream_res.tg->funcs->lock(pipe_ctx->stream_res.tg);
1988                         }
1989                 }
1990
1991                 if (!pipe_ctx->plane_state &&
1992                         old_pipe_ctx->plane_state &&
1993                         old_pipe_ctx->stream_res.tg == tg) {
1994
1995                         plane_atomic_disconnect(dc, old_pipe_ctx);
1996                         removed_pipe[i] = true;
1997
1998                         dm_logger_write(dc->ctx->logger, LOG_DC,
1999                                         "Reset mpcc for pipe %d\n",
2000                                         old_pipe_ctx->pipe_idx);
2001                 }
2002         }
2003
2004         if (num_planes > 0)
2005                 program_all_pipe_in_tree(dc, top_pipe_to_program, context);
2006
2007         tg->funcs->unlock(tg);
2008
2009         if (num_planes == 0)
2010                 false_optc_underflow_wa(dc, stream, tg);
2011
2012         for (i = 0; i < dc->res_pool->pipe_count; i++) {
2013                 struct pipe_ctx *old_pipe_ctx =
2014                                 &dc->current_state->res_ctx.pipe_ctx[i];
2015                 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
2016
2017                 if (pipe_ctx->stream == stream &&
2018                                 pipe_ctx->plane_state &&
2019                         pipe_ctx->plane_state->update_flags.bits.full_update)
2020                         program_water_mark = true;
2021
2022                 if (removed_pipe[i])
2023                         dcn10_disable_plane(dc, old_pipe_ctx);
2024         }
2025
2026         if (program_water_mark) {
2027                 if (dc->debug.sanity_checks) {
2028                         /* pstate stuck check after watermark update */
2029                         dcn10_verify_allow_pstate_change_high(dc);
2030                 }
2031
2032                 /* watermark is for all pipes */
2033                 hubbub1_program_watermarks(dc->res_pool->hubbub,
2034                                 &context->bw.dcn.watermarks, ref_clk_mhz);
2035
2036                 if (dc->debug.sanity_checks) {
2037                         /* pstate stuck check after watermark update */
2038                         dcn10_verify_allow_pstate_change_high(dc);
2039                 }
2040         }
2041 /*      dm_logger_write(dc->ctx->logger, LOG_BANDWIDTH_CALCS,
2042                         "\n============== Watermark parameters ==============\n"
2043                         "a.urgent_ns: %d \n"
2044                         "a.cstate_enter_plus_exit: %d \n"
2045                         "a.cstate_exit: %d \n"
2046                         "a.pstate_change: %d \n"
2047                         "a.pte_meta_urgent: %d \n"
2048                         "b.urgent_ns: %d \n"
2049                         "b.cstate_enter_plus_exit: %d \n"
2050                         "b.cstate_exit: %d \n"
2051                         "b.pstate_change: %d \n"
2052                         "b.pte_meta_urgent: %d \n",
2053                         context->bw.dcn.watermarks.a.urgent_ns,
2054                         context->bw.dcn.watermarks.a.cstate_pstate.cstate_enter_plus_exit_ns,
2055                         context->bw.dcn.watermarks.a.cstate_pstate.cstate_exit_ns,
2056                         context->bw.dcn.watermarks.a.cstate_pstate.pstate_change_ns,
2057                         context->bw.dcn.watermarks.a.pte_meta_urgent_ns,
2058                         context->bw.dcn.watermarks.b.urgent_ns,
2059                         context->bw.dcn.watermarks.b.cstate_pstate.cstate_enter_plus_exit_ns,
2060                         context->bw.dcn.watermarks.b.cstate_pstate.cstate_exit_ns,
2061                         context->bw.dcn.watermarks.b.cstate_pstate.pstate_change_ns,
2062                         context->bw.dcn.watermarks.b.pte_meta_urgent_ns
2063                         );
2064         dm_logger_write(dc->ctx->logger, LOG_BANDWIDTH_CALCS,
2065                         "\nc.urgent_ns: %d \n"
2066                         "c.cstate_enter_plus_exit: %d \n"
2067                         "c.cstate_exit: %d \n"
2068                         "c.pstate_change: %d \n"
2069                         "c.pte_meta_urgent: %d \n"
2070                         "d.urgent_ns: %d \n"
2071                         "d.cstate_enter_plus_exit: %d \n"
2072                         "d.cstate_exit: %d \n"
2073                         "d.pstate_change: %d \n"
2074                         "d.pte_meta_urgent: %d \n"
2075                         "========================================================\n",
2076                         context->bw.dcn.watermarks.c.urgent_ns,
2077                         context->bw.dcn.watermarks.c.cstate_pstate.cstate_enter_plus_exit_ns,
2078                         context->bw.dcn.watermarks.c.cstate_pstate.cstate_exit_ns,
2079                         context->bw.dcn.watermarks.c.cstate_pstate.pstate_change_ns,
2080                         context->bw.dcn.watermarks.c.pte_meta_urgent_ns,
2081                         context->bw.dcn.watermarks.d.urgent_ns,
2082                         context->bw.dcn.watermarks.d.cstate_pstate.cstate_enter_plus_exit_ns,
2083                         context->bw.dcn.watermarks.d.cstate_pstate.cstate_exit_ns,
2084                         context->bw.dcn.watermarks.d.cstate_pstate.pstate_change_ns,
2085                         context->bw.dcn.watermarks.d.pte_meta_urgent_ns
2086                         );
2087 */
2088 }
2089
2090 static void dcn10_set_bandwidth(
2091                 struct dc *dc,
2092                 struct dc_state *context,
2093                 bool decrease_allowed)
2094 {
2095         struct pp_smu_display_requirement_rv *smu_req_cur =
2096                         &dc->res_pool->pp_smu_req;
2097         struct pp_smu_display_requirement_rv smu_req = *smu_req_cur;
2098         struct pp_smu_funcs_rv *pp_smu = dc->res_pool->pp_smu;
2099
2100         if (dc->debug.sanity_checks) {
2101                 dcn10_verify_allow_pstate_change_high(dc);
2102         }
2103
2104         if (IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment))
2105                 return;
2106
2107         if (decrease_allowed || context->bw.dcn.calc_clk.dispclk_khz
2108                         > dc->current_state->bw.dcn.cur_clk.dispclk_khz) {
2109                 dc->res_pool->display_clock->funcs->set_clock(
2110                                 dc->res_pool->display_clock,
2111                                 context->bw.dcn.calc_clk.dispclk_khz);
2112                 dc->current_state->bw.dcn.cur_clk.dispclk_khz =
2113                                 context->bw.dcn.calc_clk.dispclk_khz;
2114         }
2115         if (decrease_allowed || context->bw.dcn.calc_clk.dcfclk_khz
2116                         > dc->current_state->bw.dcn.cur_clk.dcfclk_khz) {
2117                 smu_req.hard_min_dcefclk_khz =
2118                                 context->bw.dcn.calc_clk.dcfclk_khz;
2119         }
2120         if (decrease_allowed || context->bw.dcn.calc_clk.fclk_khz
2121                         > dc->current_state->bw.dcn.cur_clk.fclk_khz) {
2122                 smu_req.hard_min_fclk_khz = context->bw.dcn.calc_clk.fclk_khz;
2123         }
2124         if (decrease_allowed || context->bw.dcn.calc_clk.dcfclk_deep_sleep_khz
2125                         > dc->current_state->bw.dcn.cur_clk.dcfclk_deep_sleep_khz) {
2126                 dc->current_state->bw.dcn.calc_clk.dcfclk_deep_sleep_khz =
2127                                 context->bw.dcn.calc_clk.dcfclk_deep_sleep_khz;
2128                 context->bw.dcn.cur_clk.dcfclk_deep_sleep_khz =
2129                                 context->bw.dcn.calc_clk.dcfclk_deep_sleep_khz;
2130         }
2131
2132         smu_req.display_count = context->stream_count;
2133
2134         if (pp_smu->set_display_requirement)
2135                 pp_smu->set_display_requirement(&pp_smu->pp_smu, &smu_req);
2136
2137         *smu_req_cur = smu_req;
2138
2139         /* Decrease in freq is increase in period so opposite comparison for dram_ccm */
2140         if (decrease_allowed || context->bw.dcn.calc_clk.dram_ccm_us
2141                         < dc->current_state->bw.dcn.cur_clk.dram_ccm_us) {
2142                 dc->current_state->bw.dcn.calc_clk.dram_ccm_us =
2143                                 context->bw.dcn.calc_clk.dram_ccm_us;
2144                 context->bw.dcn.cur_clk.dram_ccm_us =
2145                                 context->bw.dcn.calc_clk.dram_ccm_us;
2146         }
2147         if (decrease_allowed || context->bw.dcn.calc_clk.min_active_dram_ccm_us
2148                         < dc->current_state->bw.dcn.cur_clk.min_active_dram_ccm_us) {
2149                 dc->current_state->bw.dcn.calc_clk.min_active_dram_ccm_us =
2150                                 context->bw.dcn.calc_clk.min_active_dram_ccm_us;
2151                 context->bw.dcn.cur_clk.min_active_dram_ccm_us =
2152                                 context->bw.dcn.calc_clk.min_active_dram_ccm_us;
2153         }
2154         dcn10_pplib_apply_display_requirements(dc, context);
2155
2156         if (dc->debug.sanity_checks) {
2157                 dcn10_verify_allow_pstate_change_high(dc);
2158         }
2159
2160         /* need to fix this function.  not doing the right thing here */
2161 }
2162
2163 static void set_drr(struct pipe_ctx **pipe_ctx,
2164                 int num_pipes, int vmin, int vmax)
2165 {
2166         int i = 0;
2167         struct drr_params params = {0};
2168
2169         params.vertical_total_max = vmax;
2170         params.vertical_total_min = vmin;
2171
2172         /* TODO: If multiple pipes are to be supported, you need
2173          * some GSL stuff
2174          */
2175         for (i = 0; i < num_pipes; i++) {
2176                 pipe_ctx[i]->stream_res.tg->funcs->set_drr(pipe_ctx[i]->stream_res.tg, &params);
2177         }
2178 }
2179
2180 static void get_position(struct pipe_ctx **pipe_ctx,
2181                 int num_pipes,
2182                 struct crtc_position *position)
2183 {
2184         int i = 0;
2185
2186         /* TODO: handle pipes > 1
2187          */
2188         for (i = 0; i < num_pipes; i++)
2189                 pipe_ctx[i]->stream_res.tg->funcs->get_position(pipe_ctx[i]->stream_res.tg, position);
2190 }
2191
2192 static void set_static_screen_control(struct pipe_ctx **pipe_ctx,
2193                 int num_pipes, const struct dc_static_screen_events *events)
2194 {
2195         unsigned int i;
2196         unsigned int value = 0;
2197
2198         if (events->surface_update)
2199                 value |= 0x80;
2200         if (events->cursor_update)
2201                 value |= 0x2;
2202
2203         for (i = 0; i < num_pipes; i++)
2204                 pipe_ctx[i]->stream_res.tg->funcs->
2205                         set_static_screen_control(pipe_ctx[i]->stream_res.tg, value);
2206 }
2207
2208 static void set_plane_config(
2209         const struct dc *dc,
2210         struct pipe_ctx *pipe_ctx,
2211         struct resource_context *res_ctx)
2212 {
2213         /* TODO */
2214         program_gamut_remap(pipe_ctx);
2215 }
2216
2217 static void dcn10_config_stereo_parameters(
2218                 struct dc_stream_state *stream, struct crtc_stereo_flags *flags)
2219 {
2220         enum view_3d_format view_format = stream->view_format;
2221         enum dc_timing_3d_format timing_3d_format =\
2222                         stream->timing.timing_3d_format;
2223         bool non_stereo_timing = false;
2224
2225         if (timing_3d_format == TIMING_3D_FORMAT_NONE ||
2226                 timing_3d_format == TIMING_3D_FORMAT_SIDE_BY_SIDE ||
2227                 timing_3d_format == TIMING_3D_FORMAT_TOP_AND_BOTTOM)
2228                 non_stereo_timing = true;
2229
2230         if (non_stereo_timing == false &&
2231                 view_format == VIEW_3D_FORMAT_FRAME_SEQUENTIAL) {
2232
2233                 flags->PROGRAM_STEREO         = 1;
2234                 flags->PROGRAM_POLARITY       = 1;
2235                 if (timing_3d_format == TIMING_3D_FORMAT_INBAND_FA ||
2236                         timing_3d_format == TIMING_3D_FORMAT_DP_HDMI_INBAND_FA ||
2237                         timing_3d_format == TIMING_3D_FORMAT_SIDEBAND_FA) {
2238                         enum display_dongle_type dongle = \
2239                                         stream->sink->link->ddc->dongle_type;
2240                         if (dongle == DISPLAY_DONGLE_DP_VGA_CONVERTER ||
2241                                 dongle == DISPLAY_DONGLE_DP_DVI_CONVERTER ||
2242                                 dongle == DISPLAY_DONGLE_DP_HDMI_CONVERTER)
2243                                 flags->DISABLE_STEREO_DP_SYNC = 1;
2244                 }
2245                 flags->RIGHT_EYE_POLARITY =\
2246                                 stream->timing.flags.RIGHT_EYE_3D_POLARITY;
2247                 if (timing_3d_format == TIMING_3D_FORMAT_HW_FRAME_PACKING)
2248                         flags->FRAME_PACKED = 1;
2249         }
2250
2251         return;
2252 }
2253
2254 static void dcn10_setup_stereo(struct pipe_ctx *pipe_ctx, struct dc *dc)
2255 {
2256         struct crtc_stereo_flags flags = { 0 };
2257         struct dc_stream_state *stream = pipe_ctx->stream;
2258
2259         dcn10_config_stereo_parameters(stream, &flags);
2260
2261         pipe_ctx->stream_res.opp->funcs->opp_program_stereo(
2262                 pipe_ctx->stream_res.opp,
2263                 flags.PROGRAM_STEREO == 1 ? true:false,
2264                 &stream->timing);
2265
2266         pipe_ctx->stream_res.tg->funcs->program_stereo(
2267                 pipe_ctx->stream_res.tg,
2268                 &stream->timing,
2269                 &flags);
2270
2271         return;
2272 }
2273
2274 static void dcn10_wait_for_mpcc_disconnect(
2275                 struct dc *dc,
2276                 struct resource_pool *res_pool,
2277                 struct pipe_ctx *pipe_ctx)
2278 {
2279         int i;
2280
2281         if (dc->debug.sanity_checks) {
2282                 dcn10_verify_allow_pstate_change_high(dc);
2283         }
2284
2285         if (!pipe_ctx->stream_res.opp)
2286                 return;
2287
2288         for (i = 0; i < MAX_PIPES; i++) {
2289                 if (pipe_ctx->stream_res.opp->mpcc_disconnect_pending[i]) {
2290                         res_pool->mpc->funcs->wait_for_idle(res_pool->mpc, i);
2291                         pipe_ctx->stream_res.opp->mpcc_disconnect_pending[i] = false;
2292                         res_pool->hubps[i]->funcs->set_blank(res_pool->hubps[i], true);
2293                         /*dm_logger_write(dc->ctx->logger, LOG_ERROR,
2294                                         "[debug_mpo: wait_for_mpcc finished waiting on mpcc %d]\n",
2295                                         i);*/
2296                 }
2297         }
2298
2299         if (dc->debug.sanity_checks) {
2300                 dcn10_verify_allow_pstate_change_high(dc);
2301         }
2302
2303 }
2304
2305 static bool dcn10_dummy_display_power_gating(
2306         struct dc *dc,
2307         uint8_t controller_id,
2308         struct dc_bios *dcb,
2309         enum pipe_gating_control power_gating)
2310 {
2311         return true;
2312 }
2313
2314 static void dcn10_update_pending_status(struct pipe_ctx *pipe_ctx)
2315 {
2316         struct dc_plane_state *plane_state = pipe_ctx->plane_state;
2317         struct timing_generator *tg = pipe_ctx->stream_res.tg;
2318
2319         if (plane_state == NULL)
2320                 return;
2321
2322         plane_state->status.is_flip_pending =
2323                         pipe_ctx->plane_res.hubp->funcs->hubp_is_flip_pending(
2324                                         pipe_ctx->plane_res.hubp);
2325
2326         plane_state->status.current_address = pipe_ctx->plane_res.hubp->current_address;
2327         if (pipe_ctx->plane_res.hubp->current_address.type == PLN_ADDR_TYPE_GRPH_STEREO &&
2328                         tg->funcs->is_stereo_left_eye) {
2329                 plane_state->status.is_right_eye =
2330                                 !tg->funcs->is_stereo_left_eye(pipe_ctx->stream_res.tg);
2331         }
2332 }
2333
2334 static void dcn10_update_dchub(struct dce_hwseq *hws, struct dchub_init_data *dh_data)
2335 {
2336         if (hws->ctx->dc->res_pool->hubbub != NULL)
2337                 hubbub1_update_dchub(hws->ctx->dc->res_pool->hubbub, dh_data);
2338 }
2339
2340 static void dcn10_set_cursor_position(struct pipe_ctx *pipe_ctx)
2341 {
2342         struct dc_cursor_position pos_cpy = pipe_ctx->stream->cursor_position;
2343         struct hubp *hubp = pipe_ctx->plane_res.hubp;
2344         struct dpp *dpp = pipe_ctx->plane_res.dpp;
2345         struct dc_cursor_mi_param param = {
2346                 .pixel_clk_khz = pipe_ctx->stream->timing.pix_clk_khz,
2347                 .ref_clk_khz = pipe_ctx->stream->ctx->dc->res_pool->ref_clock_inKhz,
2348                 .viewport_x_start = pipe_ctx->plane_res.scl_data.viewport.x,
2349                 .viewport_width = pipe_ctx->plane_res.scl_data.viewport.width,
2350                 .h_scale_ratio = pipe_ctx->plane_res.scl_data.ratios.horz
2351         };
2352
2353         if (pipe_ctx->plane_state->address.type
2354                         == PLN_ADDR_TYPE_VIDEO_PROGRESSIVE)
2355                 pos_cpy.enable = false;
2356
2357         if (pipe_ctx->top_pipe && pipe_ctx->plane_state != pipe_ctx->top_pipe->plane_state)
2358                 pos_cpy.enable = false;
2359
2360         hubp->funcs->set_cursor_position(hubp, &pos_cpy, &param);
2361         dpp->funcs->set_cursor_position(dpp, &pos_cpy, &param, hubp->curs_attr.width);
2362 }
2363
2364 static void dcn10_set_cursor_attribute(struct pipe_ctx *pipe_ctx)
2365 {
2366         struct dc_cursor_attributes *attributes = &pipe_ctx->stream->cursor_attributes;
2367
2368         pipe_ctx->plane_res.hubp->funcs->set_cursor_attributes(
2369                         pipe_ctx->plane_res.hubp, attributes);
2370         pipe_ctx->plane_res.dpp->funcs->set_cursor_attributes(
2371                 pipe_ctx->plane_res.dpp, attributes->color_format);
2372 }
2373
2374 static const struct hw_sequencer_funcs dcn10_funcs = {
2375         .program_gamut_remap = program_gamut_remap,
2376         .program_csc_matrix = program_csc_matrix,
2377         .init_hw = dcn10_init_hw,
2378         .apply_ctx_to_hw = dce110_apply_ctx_to_hw,
2379         .apply_ctx_for_surface = dcn10_apply_ctx_for_surface,
2380         .set_plane_config = set_plane_config,
2381         .update_plane_addr = dcn10_update_plane_addr,
2382         .update_dchub = dcn10_update_dchub,
2383         .update_pending_status = dcn10_update_pending_status,
2384         .set_input_transfer_func = dcn10_set_input_transfer_func,
2385         .set_output_transfer_func = dcn10_set_output_transfer_func,
2386         .power_down = dce110_power_down,
2387         .enable_accelerated_mode = dce110_enable_accelerated_mode,
2388         .enable_timing_synchronization = dcn10_enable_timing_synchronization,
2389         .enable_per_frame_crtc_position_reset = dcn10_enable_per_frame_crtc_position_reset,
2390         .update_info_frame = dce110_update_info_frame,
2391         .enable_stream = dce110_enable_stream,
2392         .disable_stream = dce110_disable_stream,
2393         .unblank_stream = dce110_unblank_stream,
2394         .enable_display_power_gating = dcn10_dummy_display_power_gating,
2395         .disable_plane = dcn10_disable_plane,
2396         .pipe_control_lock = dcn10_pipe_control_lock,
2397         .set_bandwidth = dcn10_set_bandwidth,
2398         .reset_hw_ctx_wrap = reset_hw_ctx_wrap,
2399         .prog_pixclk_crtc_otg = dcn10_prog_pixclk_crtc_otg,
2400         .set_drr = set_drr,
2401         .get_position = get_position,
2402         .set_static_screen_control = set_static_screen_control,
2403         .setup_stereo = dcn10_setup_stereo,
2404         .set_avmute = dce110_set_avmute,
2405         .log_hw_state = dcn10_log_hw_state,
2406         .wait_for_mpcc_disconnect = dcn10_wait_for_mpcc_disconnect,
2407         .ready_shared_resources = ready_shared_resources,
2408         .optimize_shared_resources = optimize_shared_resources,
2409         .pplib_apply_display_requirements =
2410                         dcn10_pplib_apply_display_requirements,
2411         .edp_backlight_control = hwss_edp_backlight_control,
2412         .edp_power_control = hwss_edp_power_control,
2413         .edp_wait_for_hpd_ready = hwss_edp_wait_for_hpd_ready,
2414         .set_cursor_position = dcn10_set_cursor_position,
2415         .set_cursor_attribute = dcn10_set_cursor_attribute
2416 };
2417
2418
2419 void dcn10_hw_sequencer_construct(struct dc *dc)
2420 {
2421         dc->hwss = dcn10_funcs;
2422 }
2423