2 * Copyright 2016 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
26 #include "dm_services.h"
30 #include "include/irq_service_interface.h"
31 #include "dcn10/dcn10_resource.h"
33 #include "dcn10/dcn10_ipp.h"
34 #include "dcn10/dcn10_mpc.h"
35 #include "irq/dcn10/irq_service_dcn10.h"
36 #include "dcn10/dcn10_dpp.h"
37 #include "dcn10_optc.h"
38 #include "dcn10/dcn10_hw_sequencer.h"
39 #include "dce110/dce110_hw_sequencer.h"
40 #include "dcn10/dcn10_opp.h"
41 #include "dcn10/dcn10_link_encoder.h"
42 #include "dcn10/dcn10_stream_encoder.h"
43 #include "dce/dce_clocks.h"
44 #include "dce/dce_clock_source.h"
45 #include "dce/dce_audio.h"
46 #include "dce/dce_hwseq.h"
47 #include "../virtual/virtual_stream_encoder.h"
48 #include "dce110/dce110_resource.h"
49 #include "dce112/dce112_resource.h"
50 #include "dcn10_hubp.h"
51 #include "dcn10_hubbub.h"
53 #include "soc15_hw_ip.h"
54 #include "vega10_ip_offset.h"
56 #include "dcn/dcn_1_0_offset.h"
57 #include "dcn/dcn_1_0_sh_mask.h"
59 #include "nbio/nbio_7_0_offset.h"
61 #include "mmhub/mmhub_9_1_offset.h"
62 #include "mmhub/mmhub_9_1_sh_mask.h"
64 #include "reg_helper.h"
65 #include "dce/dce_abm.h"
66 #include "dce/dce_dmcu.h"
67 #include "dce/dce_aux.h"
68 #include "dce/dce_i2c.h"
70 const struct _vcs_dpi_ip_params_st dcn1_0_ip = {
71 .rob_buffer_size_kbytes = 64,
72 .det_buffer_size_kbytes = 164,
73 .dpte_buffer_size_in_pte_reqs = 42,
74 .dpp_output_buffer_pixels = 2560,
75 .opp_output_buffer_lines = 1,
76 .pixel_chunk_size_kbytes = 8,
78 .pte_chunk_size_kbytes = 2,
79 .meta_chunk_size_kbytes = 2,
80 .writeback_chunk_size_kbytes = 2,
81 .line_buffer_size_bits = 589824,
82 .max_line_buffer_lines = 12,
83 .IsLineBufferBppFixed = 0,
84 .LineBufferFixedBpp = -1,
85 .writeback_luma_buffer_size_kbytes = 12,
86 .writeback_chroma_buffer_size_kbytes = 8,
89 .max_dchub_pscl_bw_pix_per_clk = 4,
90 .max_pscl_lb_bw_pix_per_clk = 2,
91 .max_lb_vscl_bw_pix_per_clk = 4,
92 .max_vscl_hscl_bw_pix_per_clk = 4,
99 .dispclk_ramp_margin_percent = 1,
100 .underscan_factor = 1.10,
101 .min_vblank_lines = 14,
102 .dppclk_delay_subtotal = 90,
103 .dispclk_delay_subtotal = 42,
104 .dcfclk_cstate_latency = 10,
105 .max_inter_dcn_tile_repeaters = 8,
106 .can_vstartup_lines_exceed_vsync_plus_back_porch_lines_minus_one = 0,
107 .bug_forcing_LC_req_same_size_fixed = 0,
110 const struct _vcs_dpi_soc_bounding_box_st dcn1_0_soc = {
111 .sr_exit_time_us = 9.0,
112 .sr_enter_plus_exit_time_us = 11.0,
113 .urgent_latency_us = 4.0,
114 .writeback_latency_us = 12.0,
115 .ideal_dram_bw_after_urgent_percent = 80.0,
116 .max_request_size_bytes = 256,
117 .downspread_percent = 0.5,
118 .dram_page_open_time_ns = 50.0,
119 .dram_rw_turnaround_time_ns = 17.5,
120 .dram_return_buffer_per_channel_bytes = 8192,
121 .round_trip_ping_latency_dcfclk_cycles = 128,
122 .urgent_out_of_order_return_per_channel_bytes = 256,
123 .channel_interleave_bytes = 256,
126 .vmm_page_size_bytes = 4096,
127 .dram_clock_change_latency_us = 17.0,
128 .writeback_dram_clock_change_latency_us = 23.0,
129 .return_bus_width_bytes = 64,
132 #ifndef mmDP0_DP_DPHY_INTERNAL_CTRL
133 #define mmDP0_DP_DPHY_INTERNAL_CTRL 0x210f
134 #define mmDP0_DP_DPHY_INTERNAL_CTRL_BASE_IDX 2
135 #define mmDP1_DP_DPHY_INTERNAL_CTRL 0x220f
136 #define mmDP1_DP_DPHY_INTERNAL_CTRL_BASE_IDX 2
137 #define mmDP2_DP_DPHY_INTERNAL_CTRL 0x230f
138 #define mmDP2_DP_DPHY_INTERNAL_CTRL_BASE_IDX 2
139 #define mmDP3_DP_DPHY_INTERNAL_CTRL 0x240f
140 #define mmDP3_DP_DPHY_INTERNAL_CTRL_BASE_IDX 2
141 #define mmDP4_DP_DPHY_INTERNAL_CTRL 0x250f
142 #define mmDP4_DP_DPHY_INTERNAL_CTRL_BASE_IDX 2
143 #define mmDP5_DP_DPHY_INTERNAL_CTRL 0x260f
144 #define mmDP5_DP_DPHY_INTERNAL_CTRL_BASE_IDX 2
145 #define mmDP6_DP_DPHY_INTERNAL_CTRL 0x270f
146 #define mmDP6_DP_DPHY_INTERNAL_CTRL_BASE_IDX 2
150 enum dcn10_clk_src_array_id {
156 #if defined(CONFIG_DRM_AMD_DC_DCN1_01)
157 DCN101_CLK_SRC_TOTAL = DCN10_CLK_SRC_PLL3
161 /* begin *********************
162 * macros to expend register list macro defined in HW object header file */
165 #define BASE_INNER(seg) \
166 DCE_BASE__INST0_SEG ## seg
171 #define SR(reg_name)\
172 .reg_name = BASE(mm ## reg_name ## _BASE_IDX) + \
175 #define SRI(reg_name, block, id)\
176 .reg_name = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
177 mm ## block ## id ## _ ## reg_name
180 #define SRII(reg_name, block, id)\
181 .reg_name[id] = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
182 mm ## block ## id ## _ ## reg_name
185 #define NBIO_BASE_INNER(seg) \
186 NBIF_BASE__INST0_SEG ## seg
188 #define NBIO_BASE(seg) \
191 #define NBIO_SR(reg_name)\
192 .reg_name = NBIO_BASE(mm ## reg_name ## _BASE_IDX) + \
196 #define MMHUB_BASE_INNER(seg) \
197 MMHUB_BASE__INST0_SEG ## seg
199 #define MMHUB_BASE(seg) \
200 MMHUB_BASE_INNER(seg)
202 #define MMHUB_SR(reg_name)\
203 .reg_name = MMHUB_BASE(mm ## reg_name ## _BASE_IDX) + \
206 /* macros to expend register list macro defined in HW object header file
207 * end *********************/
210 static const struct dce_dmcu_registers dmcu_regs = {
211 DMCU_DCN10_REG_LIST()
214 static const struct dce_dmcu_shift dmcu_shift = {
215 DMCU_MASK_SH_LIST_DCN10(__SHIFT)
218 static const struct dce_dmcu_mask dmcu_mask = {
219 DMCU_MASK_SH_LIST_DCN10(_MASK)
222 static const struct dce_abm_registers abm_regs = {
223 ABM_DCN10_REG_LIST(0)
226 static const struct dce_abm_shift abm_shift = {
227 ABM_MASK_SH_LIST_DCN10(__SHIFT)
230 static const struct dce_abm_mask abm_mask = {
231 ABM_MASK_SH_LIST_DCN10(_MASK)
234 #define stream_enc_regs(id)\
239 static const struct dcn10_stream_enc_registers stream_enc_regs[] = {
246 static const struct dcn10_stream_encoder_shift se_shift = {
247 SE_COMMON_MASK_SH_LIST_DCN10(__SHIFT)
250 static const struct dcn10_stream_encoder_mask se_mask = {
251 SE_COMMON_MASK_SH_LIST_DCN10(_MASK)
254 #define audio_regs(id)\
256 AUD_COMMON_REG_LIST(id)\
259 static const struct dce_audio_registers audio_regs[] = {
266 #define DCE120_AUD_COMMON_MASK_SH_LIST(mask_sh)\
267 SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_INDEX, AZALIA_ENDPOINT_REG_INDEX, mask_sh),\
268 SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_DATA, AZALIA_ENDPOINT_REG_DATA, mask_sh),\
269 AUD_COMMON_MASK_SH_LIST_BASE(mask_sh)
271 static const struct dce_audio_shift audio_shift = {
272 DCE120_AUD_COMMON_MASK_SH_LIST(__SHIFT)
275 static const struct dce_aduio_mask audio_mask = {
276 DCE120_AUD_COMMON_MASK_SH_LIST(_MASK)
279 #define aux_regs(id)\
284 static const struct dcn10_link_enc_aux_registers link_enc_aux_regs[] = {
291 #define hpd_regs(id)\
296 static const struct dcn10_link_enc_hpd_registers link_enc_hpd_regs[] = {
303 #define link_regs(id)\
305 LE_DCN10_REG_LIST(id), \
306 SRI(DP_DPHY_INTERNAL_CTRL, DP, id) \
309 static const struct dcn10_link_enc_registers link_enc_regs[] = {
316 static const struct dcn10_link_enc_shift le_shift = {
317 LINK_ENCODER_MASK_SH_LIST_DCN10(__SHIFT)
320 static const struct dcn10_link_enc_mask le_mask = {
321 LINK_ENCODER_MASK_SH_LIST_DCN10(_MASK)
324 #define ipp_regs(id)\
326 IPP_REG_LIST_DCN10(id),\
329 static const struct dcn10_ipp_registers ipp_regs[] = {
336 static const struct dcn10_ipp_shift ipp_shift = {
337 IPP_MASK_SH_LIST_DCN10(__SHIFT)
340 static const struct dcn10_ipp_mask ipp_mask = {
341 IPP_MASK_SH_LIST_DCN10(_MASK),
344 #define opp_regs(id)\
346 OPP_REG_LIST_DCN10(id),\
349 static const struct dcn10_opp_registers opp_regs[] = {
356 static const struct dcn10_opp_shift opp_shift = {
357 OPP_MASK_SH_LIST_DCN10(__SHIFT)
360 static const struct dcn10_opp_mask opp_mask = {
361 OPP_MASK_SH_LIST_DCN10(_MASK),
364 #define aux_engine_regs(id)\
366 AUX_COMMON_REG_LIST(id), \
367 .AUX_RESET_MASK = 0 \
370 static const struct dce110_aux_registers aux_engine_regs[] = {
381 TF_REG_LIST_DCN10(id),\
384 static const struct dcn_dpp_registers tf_regs[] = {
391 static const struct dcn_dpp_shift tf_shift = {
392 TF_REG_LIST_SH_MASK_DCN10(__SHIFT),
393 TF_DEBUG_REG_LIST_SH_DCN10
397 static const struct dcn_dpp_mask tf_mask = {
398 TF_REG_LIST_SH_MASK_DCN10(_MASK),
399 TF_DEBUG_REG_LIST_MASK_DCN10
402 static const struct dcn_mpc_registers mpc_regs = {
403 MPC_COMMON_REG_LIST_DCN1_0(0),
404 MPC_COMMON_REG_LIST_DCN1_0(1),
405 MPC_COMMON_REG_LIST_DCN1_0(2),
406 MPC_COMMON_REG_LIST_DCN1_0(3),
407 MPC_OUT_MUX_COMMON_REG_LIST_DCN1_0(0),
408 MPC_OUT_MUX_COMMON_REG_LIST_DCN1_0(1),
409 MPC_OUT_MUX_COMMON_REG_LIST_DCN1_0(2),
410 MPC_OUT_MUX_COMMON_REG_LIST_DCN1_0(3)
413 static const struct dcn_mpc_shift mpc_shift = {
414 MPC_COMMON_MASK_SH_LIST_DCN1_0(__SHIFT)
417 static const struct dcn_mpc_mask mpc_mask = {
418 MPC_COMMON_MASK_SH_LIST_DCN1_0(_MASK),
422 [id] = {TG_COMMON_REG_LIST_DCN1_0(id)}
424 static const struct dcn_optc_registers tg_regs[] = {
431 static const struct dcn_optc_shift tg_shift = {
432 TG_COMMON_MASK_SH_LIST_DCN1_0(__SHIFT)
435 static const struct dcn_optc_mask tg_mask = {
436 TG_COMMON_MASK_SH_LIST_DCN1_0(_MASK)
440 static const struct bios_registers bios_regs = {
441 NBIO_SR(BIOS_SCRATCH_3),
442 NBIO_SR(BIOS_SCRATCH_6)
445 #define hubp_regs(id)\
447 HUBP_REG_LIST_DCN10(id)\
451 static const struct dcn_mi_registers hubp_regs[] = {
458 static const struct dcn_mi_shift hubp_shift = {
459 HUBP_MASK_SH_LIST_DCN10(__SHIFT)
462 static const struct dcn_mi_mask hubp_mask = {
463 HUBP_MASK_SH_LIST_DCN10(_MASK)
467 static const struct dcn_hubbub_registers hubbub_reg = {
468 HUBBUB_REG_LIST_DCN10(0)
471 static const struct dcn_hubbub_shift hubbub_shift = {
472 HUBBUB_MASK_SH_LIST_DCN10(__SHIFT)
475 static const struct dcn_hubbub_mask hubbub_mask = {
476 HUBBUB_MASK_SH_LIST_DCN10(_MASK)
479 #define clk_src_regs(index, pllid)\
481 CS_COMMON_REG_LIST_DCN1_0(index, pllid),\
484 static const struct dce110_clk_src_regs clk_src_regs[] = {
491 static const struct dce110_clk_src_shift cs_shift = {
492 CS_COMMON_MASK_SH_LIST_DCN1_0(__SHIFT)
495 static const struct dce110_clk_src_mask cs_mask = {
496 CS_COMMON_MASK_SH_LIST_DCN1_0(_MASK)
500 static const struct resource_caps res_cap = {
501 .num_timing_generator = 4,
503 .num_video_plane = 4,
505 .num_stream_encoder = 4,
510 static const struct dc_debug_options debug_defaults_drv = {
511 .sanity_checks = true,
512 .disable_dmcu = true,
513 .force_abm_enable = false,
514 .timing_trace = false,
517 /* raven smu dones't allow 0 disp clk,
518 * smu min disp clk limit is 50Mhz
519 * keep min disp clk 100Mhz avoid smu hang
521 .min_disp_clk_khz = 100000,
523 .disable_pplib_clock_request = false,
524 .disable_pplib_wm_range = false,
525 .pplib_wm_report_mode = WM_REPORT_DEFAULT,
526 .pipe_split_policy = MPC_SPLIT_AVOID_MULT_DISP,
527 .force_single_disp_pipe_split = true,
528 .disable_dcc = DCC_ENABLE,
529 .voltage_align_fclk = true,
530 .disable_stereo_support = true,
532 .performance_trace = false,
533 .az_endpoint_mute_only = true,
534 .recovery_enabled = false, /*enable this by default after testing.*/
535 .max_downscale_src_width = 3840,
538 static const struct dc_debug_options debug_defaults_diags = {
539 .disable_dmcu = true,
540 .force_abm_enable = false,
541 .timing_trace = true,
543 .disable_stutter = true,
544 .disable_pplib_clock_request = true,
545 .disable_pplib_wm_range = true
548 static void dcn10_dpp_destroy(struct dpp **dpp)
550 kfree(TO_DCN10_DPP(*dpp));
554 static struct dpp *dcn10_dpp_create(
555 struct dc_context *ctx,
558 struct dcn10_dpp *dpp =
559 kzalloc(sizeof(struct dcn10_dpp), GFP_KERNEL);
564 dpp1_construct(dpp, ctx, inst,
565 &tf_regs[inst], &tf_shift, &tf_mask);
569 static struct input_pixel_processor *dcn10_ipp_create(
570 struct dc_context *ctx, uint32_t inst)
572 struct dcn10_ipp *ipp =
573 kzalloc(sizeof(struct dcn10_ipp), GFP_KERNEL);
580 dcn10_ipp_construct(ipp, ctx, inst,
581 &ipp_regs[inst], &ipp_shift, &ipp_mask);
586 static struct output_pixel_processor *dcn10_opp_create(
587 struct dc_context *ctx, uint32_t inst)
589 struct dcn10_opp *opp =
590 kzalloc(sizeof(struct dcn10_opp), GFP_KERNEL);
597 dcn10_opp_construct(opp, ctx, inst,
598 &opp_regs[inst], &opp_shift, &opp_mask);
602 struct aux_engine *dcn10_aux_engine_create(
603 struct dc_context *ctx,
606 struct aux_engine_dce110 *aux_engine =
607 kzalloc(sizeof(struct aux_engine_dce110), GFP_KERNEL);
612 dce110_aux_engine_construct(aux_engine, ctx, inst,
613 SW_AUX_TIMEOUT_PERIOD_MULTIPLIER * AUX_TIMEOUT_PERIOD,
614 &aux_engine_regs[inst]);
616 return &aux_engine->base;
618 #define i2c_inst_regs(id) { I2C_HW_ENGINE_COMMON_REG_LIST(id) }
620 static const struct dce_i2c_registers i2c_hw_regs[] = {
629 static const struct dce_i2c_shift i2c_shifts = {
630 I2C_COMMON_MASK_SH_LIST_DCE110(__SHIFT)
633 static const struct dce_i2c_mask i2c_masks = {
634 I2C_COMMON_MASK_SH_LIST_DCE110(_MASK)
637 struct dce_i2c_hw *dcn10_i2c_hw_create(
638 struct dc_context *ctx,
641 struct dce_i2c_hw *dce_i2c_hw =
642 kzalloc(sizeof(struct dce_i2c_hw), GFP_KERNEL);
647 dcn1_i2c_hw_construct(dce_i2c_hw, ctx, inst,
648 &i2c_hw_regs[inst], &i2c_shifts, &i2c_masks);
652 static struct mpc *dcn10_mpc_create(struct dc_context *ctx)
654 struct dcn10_mpc *mpc10 = kzalloc(sizeof(struct dcn10_mpc),
660 dcn10_mpc_construct(mpc10, ctx,
669 static struct hubbub *dcn10_hubbub_create(struct dc_context *ctx)
671 struct hubbub *hubbub = kzalloc(sizeof(struct hubbub),
677 hubbub1_construct(hubbub, ctx,
685 static struct timing_generator *dcn10_timing_generator_create(
686 struct dc_context *ctx,
690 kzalloc(sizeof(struct optc), GFP_KERNEL);
695 tgn10->base.inst = instance;
696 tgn10->base.ctx = ctx;
698 tgn10->tg_regs = &tg_regs[instance];
699 tgn10->tg_shift = &tg_shift;
700 tgn10->tg_mask = &tg_mask;
702 dcn10_timing_generator_init(tgn10);
707 static const struct encoder_feature_support link_enc_feature = {
708 .max_hdmi_deep_color = COLOR_DEPTH_121212,
709 .max_hdmi_pixel_clock = 600000,
710 .ycbcr420_supported = true,
711 .flags.bits.IS_HBR2_CAPABLE = true,
712 .flags.bits.IS_HBR3_CAPABLE = true,
713 .flags.bits.IS_TPS3_CAPABLE = true,
714 .flags.bits.IS_TPS4_CAPABLE = true,
715 .flags.bits.IS_YCBCR_CAPABLE = true
718 struct link_encoder *dcn10_link_encoder_create(
719 const struct encoder_init_data *enc_init_data)
721 struct dcn10_link_encoder *enc10 =
722 kzalloc(sizeof(struct dcn10_link_encoder), GFP_KERNEL);
727 dcn10_link_encoder_construct(enc10,
730 &link_enc_regs[enc_init_data->transmitter],
731 &link_enc_aux_regs[enc_init_data->channel - 1],
732 &link_enc_hpd_regs[enc_init_data->hpd_source],
739 struct clock_source *dcn10_clock_source_create(
740 struct dc_context *ctx,
741 struct dc_bios *bios,
742 enum clock_source_id id,
743 const struct dce110_clk_src_regs *regs,
746 struct dce110_clk_src *clk_src =
747 kzalloc(sizeof(struct dce110_clk_src), GFP_KERNEL);
752 if (dce112_clk_src_construct(clk_src, ctx, bios, id,
753 regs, &cs_shift, &cs_mask)) {
754 clk_src->base.dp_clk_src = dp_clk_src;
755 return &clk_src->base;
762 static void read_dce_straps(
763 struct dc_context *ctx,
764 struct resource_straps *straps)
766 generic_reg_get(ctx, mmDC_PINSTRAPS + BASE(mmDC_PINSTRAPS_BASE_IDX),
767 FN(DC_PINSTRAPS, DC_PINSTRAPS_AUDIO), &straps->dc_pinstraps_audio);
770 static struct audio *create_audio(
771 struct dc_context *ctx, unsigned int inst)
773 return dce_audio_create(ctx, inst,
774 &audio_regs[inst], &audio_shift, &audio_mask);
777 static struct stream_encoder *dcn10_stream_encoder_create(
778 enum engine_id eng_id,
779 struct dc_context *ctx)
781 struct dcn10_stream_encoder *enc1 =
782 kzalloc(sizeof(struct dcn10_stream_encoder), GFP_KERNEL);
787 dcn10_stream_encoder_construct(enc1, ctx, ctx->dc_bios, eng_id,
788 &stream_enc_regs[eng_id],
789 &se_shift, &se_mask);
793 static const struct dce_hwseq_registers hwseq_reg = {
794 HWSEQ_DCN1_REG_LIST()
797 static const struct dce_hwseq_shift hwseq_shift = {
798 HWSEQ_DCN1_MASK_SH_LIST(__SHIFT)
801 static const struct dce_hwseq_mask hwseq_mask = {
802 HWSEQ_DCN1_MASK_SH_LIST(_MASK)
805 static struct dce_hwseq *dcn10_hwseq_create(
806 struct dc_context *ctx)
808 struct dce_hwseq *hws = kzalloc(sizeof(struct dce_hwseq), GFP_KERNEL);
812 hws->regs = &hwseq_reg;
813 hws->shifts = &hwseq_shift;
814 hws->masks = &hwseq_mask;
815 hws->wa.DEGVIDCN10_253 = true;
816 hws->wa.false_optc_underflow = true;
817 hws->wa.DEGVIDCN10_254 = true;
822 static const struct resource_create_funcs res_create_funcs = {
823 .read_dce_straps = read_dce_straps,
824 .create_audio = create_audio,
825 .create_stream_encoder = dcn10_stream_encoder_create,
826 .create_hwseq = dcn10_hwseq_create,
829 static const struct resource_create_funcs res_create_maximus_funcs = {
830 .read_dce_straps = NULL,
831 .create_audio = NULL,
832 .create_stream_encoder = NULL,
833 .create_hwseq = dcn10_hwseq_create,
836 void dcn10_clock_source_destroy(struct clock_source **clk_src)
838 kfree(TO_DCE110_CLK_SRC(*clk_src));
842 static struct pp_smu_funcs_rv *dcn10_pp_smu_create(struct dc_context *ctx)
844 struct pp_smu_funcs_rv *pp_smu = kzalloc(sizeof(*pp_smu), GFP_KERNEL);
849 dm_pp_get_funcs_rv(ctx, pp_smu);
853 static void destruct(struct dcn10_resource_pool *pool)
857 for (i = 0; i < pool->base.stream_enc_count; i++) {
858 if (pool->base.stream_enc[i] != NULL) {
859 /* TODO: free dcn version of stream encoder once implemented
860 * rather than using virtual stream encoder
862 kfree(pool->base.stream_enc[i]);
863 pool->base.stream_enc[i] = NULL;
867 if (pool->base.mpc != NULL) {
868 kfree(TO_DCN10_MPC(pool->base.mpc));
869 pool->base.mpc = NULL;
872 if (pool->base.hubbub != NULL) {
873 kfree(pool->base.hubbub);
874 pool->base.hubbub = NULL;
877 for (i = 0; i < pool->base.pipe_count; i++) {
878 if (pool->base.opps[i] != NULL)
879 pool->base.opps[i]->funcs->opp_destroy(&pool->base.opps[i]);
881 if (pool->base.dpps[i] != NULL)
882 dcn10_dpp_destroy(&pool->base.dpps[i]);
884 if (pool->base.ipps[i] != NULL)
885 pool->base.ipps[i]->funcs->ipp_destroy(&pool->base.ipps[i]);
887 if (pool->base.hubps[i] != NULL) {
888 kfree(TO_DCN10_HUBP(pool->base.hubps[i]));
889 pool->base.hubps[i] = NULL;
892 if (pool->base.irqs != NULL) {
893 dal_irq_service_destroy(&pool->base.irqs);
896 if (pool->base.timing_generators[i] != NULL) {
897 kfree(DCN10TG_FROM_TG(pool->base.timing_generators[i]));
898 pool->base.timing_generators[i] = NULL;
901 if (pool->base.engines[i] != NULL)
902 pool->base.engines[i]->funcs->destroy_engine(&pool->base.engines[i]);
903 if (pool->base.hw_i2cs[i] != NULL) {
904 kfree(pool->base.hw_i2cs[i]);
905 pool->base.hw_i2cs[i] = NULL;
907 if (pool->base.sw_i2cs[i] != NULL) {
908 kfree(pool->base.sw_i2cs[i]);
909 pool->base.sw_i2cs[i] = NULL;
913 for (i = 0; i < pool->base.stream_enc_count; i++)
914 kfree(pool->base.stream_enc[i]);
916 for (i = 0; i < pool->base.audio_count; i++) {
917 if (pool->base.audios[i])
918 dce_aud_destroy(&pool->base.audios[i]);
921 for (i = 0; i < pool->base.clk_src_count; i++) {
922 if (pool->base.clock_sources[i] != NULL) {
923 dcn10_clock_source_destroy(&pool->base.clock_sources[i]);
924 pool->base.clock_sources[i] = NULL;
928 if (pool->base.dp_clock_source != NULL) {
929 dcn10_clock_source_destroy(&pool->base.dp_clock_source);
930 pool->base.dp_clock_source = NULL;
933 if (pool->base.abm != NULL)
934 dce_abm_destroy(&pool->base.abm);
936 if (pool->base.dmcu != NULL)
937 dce_dmcu_destroy(&pool->base.dmcu);
939 if (pool->base.dccg != NULL)
940 dce_dccg_destroy(&pool->base.dccg);
942 kfree(pool->base.pp_smu);
945 static struct hubp *dcn10_hubp_create(
946 struct dc_context *ctx,
949 struct dcn10_hubp *hubp1 =
950 kzalloc(sizeof(struct dcn10_hubp), GFP_KERNEL);
955 dcn10_hubp_construct(hubp1, ctx, inst,
956 &hubp_regs[inst], &hubp_shift, &hubp_mask);
960 static void get_pixel_clock_parameters(
961 const struct pipe_ctx *pipe_ctx,
962 struct pixel_clk_params *pixel_clk_params)
964 const struct dc_stream_state *stream = pipe_ctx->stream;
965 pixel_clk_params->requested_pix_clk = stream->timing.pix_clk_khz;
966 pixel_clk_params->encoder_object_id = stream->sink->link->link_enc->id;
967 pixel_clk_params->signal_type = pipe_ctx->stream->signal;
968 pixel_clk_params->controller_id = pipe_ctx->stream_res.tg->inst + 1;
969 /* TODO: un-hardcode*/
970 pixel_clk_params->requested_sym_clk = LINK_RATE_LOW *
971 LINK_RATE_REF_FREQ_IN_KHZ;
972 pixel_clk_params->flags.ENABLE_SS = 0;
973 pixel_clk_params->color_depth =
974 stream->timing.display_color_depth;
975 pixel_clk_params->flags.DISPLAY_BLANKED = 1;
976 pixel_clk_params->pixel_encoding = stream->timing.pixel_encoding;
978 if (stream->timing.pixel_encoding == PIXEL_ENCODING_YCBCR422)
979 pixel_clk_params->color_depth = COLOR_DEPTH_888;
981 if (stream->timing.pixel_encoding == PIXEL_ENCODING_YCBCR420)
982 pixel_clk_params->requested_pix_clk /= 2;
983 if (stream->timing.timing_3d_format == TIMING_3D_FORMAT_HW_FRAME_PACKING)
984 pixel_clk_params->requested_pix_clk *= 2;
988 static void build_clamping_params(struct dc_stream_state *stream)
990 stream->clamping.clamping_level = CLAMPING_FULL_RANGE;
991 stream->clamping.c_depth = stream->timing.display_color_depth;
992 stream->clamping.pixel_encoding = stream->timing.pixel_encoding;
995 static void build_pipe_hw_param(struct pipe_ctx *pipe_ctx)
998 get_pixel_clock_parameters(pipe_ctx, &pipe_ctx->stream_res.pix_clk_params);
1000 pipe_ctx->clock_source->funcs->get_pix_clk_dividers(
1001 pipe_ctx->clock_source,
1002 &pipe_ctx->stream_res.pix_clk_params,
1003 &pipe_ctx->pll_settings);
1005 pipe_ctx->stream->clamping.pixel_encoding = pipe_ctx->stream->timing.pixel_encoding;
1007 resource_build_bit_depth_reduction_params(pipe_ctx->stream,
1008 &pipe_ctx->stream->bit_depth_params);
1009 build_clamping_params(pipe_ctx->stream);
1012 static enum dc_status build_mapped_resource(
1013 const struct dc *dc,
1014 struct dc_state *context,
1015 struct dc_stream_state *stream)
1017 struct pipe_ctx *pipe_ctx = resource_get_head_pipe_for_stream(&context->res_ctx, stream);
1019 /*TODO Seems unneeded anymore */
1020 /* if (old_context && resource_is_stream_unchanged(old_context, stream)) {
1021 if (stream != NULL && old_context->streams[i] != NULL) {
1022 todo: shouldn't have to copy missing parameter here
1023 resource_build_bit_depth_reduction_params(stream,
1024 &stream->bit_depth_params);
1025 stream->clamping.pixel_encoding =
1026 stream->timing.pixel_encoding;
1028 resource_build_bit_depth_reduction_params(stream,
1029 &stream->bit_depth_params);
1030 build_clamping_params(stream);
1038 return DC_ERROR_UNEXPECTED;
1040 build_pipe_hw_param(pipe_ctx);
1044 enum dc_status dcn10_add_stream_to_ctx(
1046 struct dc_state *new_ctx,
1047 struct dc_stream_state *dc_stream)
1049 enum dc_status result = DC_ERROR_UNEXPECTED;
1051 result = resource_map_pool_resources(dc, new_ctx, dc_stream);
1053 if (result == DC_OK)
1054 result = resource_map_phy_clock_resources(dc, new_ctx, dc_stream);
1057 if (result == DC_OK)
1058 result = build_mapped_resource(dc, new_ctx, dc_stream);
1063 static struct pipe_ctx *dcn10_acquire_idle_pipe_for_layer(
1064 struct dc_state *context,
1065 const struct resource_pool *pool,
1066 struct dc_stream_state *stream)
1068 struct resource_context *res_ctx = &context->res_ctx;
1069 struct pipe_ctx *head_pipe = resource_get_head_pipe_for_stream(res_ctx, stream);
1070 struct pipe_ctx *idle_pipe = find_idle_secondary_pipe(res_ctx, pool);
1080 idle_pipe->stream = head_pipe->stream;
1081 idle_pipe->stream_res.tg = head_pipe->stream_res.tg;
1082 idle_pipe->stream_res.abm = head_pipe->stream_res.abm;
1083 idle_pipe->stream_res.opp = head_pipe->stream_res.opp;
1085 idle_pipe->plane_res.hubp = pool->hubps[idle_pipe->pipe_idx];
1086 idle_pipe->plane_res.ipp = pool->ipps[idle_pipe->pipe_idx];
1087 idle_pipe->plane_res.dpp = pool->dpps[idle_pipe->pipe_idx];
1088 idle_pipe->plane_res.mpcc_inst = pool->dpps[idle_pipe->pipe_idx]->inst;
1093 static bool dcn10_get_dcc_compression_cap(const struct dc *dc,
1094 const struct dc_dcc_surface_param *input,
1095 struct dc_surface_dcc_cap *output)
1097 return dc->res_pool->hubbub->funcs->get_dcc_compression_cap(
1098 dc->res_pool->hubbub,
1103 static void dcn10_destroy_resource_pool(struct resource_pool **pool)
1105 struct dcn10_resource_pool *dcn10_pool = TO_DCN10_RES_POOL(*pool);
1107 destruct(dcn10_pool);
1112 static enum dc_status dcn10_validate_plane(const struct dc_plane_state *plane_state, struct dc_caps *caps)
1114 if (plane_state->format >= SURFACE_PIXEL_FORMAT_VIDEO_BEGIN
1115 && caps->max_video_width != 0
1116 && plane_state->src_rect.width > caps->max_video_width)
1117 return DC_FAIL_SURFACE_VALIDATE;
1122 static const struct dc_cap_funcs cap_funcs = {
1123 .get_dcc_compression_cap = dcn10_get_dcc_compression_cap
1126 static const struct resource_funcs dcn10_res_pool_funcs = {
1127 .destroy = dcn10_destroy_resource_pool,
1128 .link_enc_create = dcn10_link_encoder_create,
1129 .validate_bandwidth = dcn_validate_bandwidth,
1130 .acquire_idle_pipe_for_layer = dcn10_acquire_idle_pipe_for_layer,
1131 .validate_plane = dcn10_validate_plane,
1132 .add_stream_to_ctx = dcn10_add_stream_to_ctx
1135 static uint32_t read_pipe_fuses(struct dc_context *ctx)
1137 uint32_t value = dm_read_reg_soc15(ctx, mmCC_DC_PIPE_DIS, 0);
1138 /* RV1 support max 4 pipes */
1139 value = value & 0xf;
1143 static bool construct(
1144 uint8_t num_virtual_links,
1146 struct dcn10_resource_pool *pool)
1150 struct dc_context *ctx = dc->ctx;
1151 uint32_t pipe_fuses = read_pipe_fuses(ctx);
1153 ctx->dc_bios->regs = &bios_regs;
1155 pool->base.res_cap = &res_cap;
1156 pool->base.funcs = &dcn10_res_pool_funcs;
1159 * TODO fill in from actual raven resource when we create
1160 * more than virtual encoder
1163 /*************************************************
1164 * Resource + asic cap harcoding *
1165 *************************************************/
1166 pool->base.underlay_pipe_index = NO_UNDERLAY_PIPE;
1168 /* max pipe num for ASIC before check pipe fuses */
1169 pool->base.pipe_count = pool->base.res_cap->num_timing_generator;
1171 #if defined(CONFIG_DRM_AMD_DC_DCN1_01)
1172 if (dc->ctx->dce_version == DCN_VERSION_1_01)
1173 pool->base.pipe_count = 3;
1175 dc->caps.max_video_width = 3840;
1176 dc->caps.max_downscale_ratio = 200;
1177 dc->caps.i2c_speed_in_khz = 100;
1178 dc->caps.max_cursor_size = 256;
1179 dc->caps.max_slave_planes = 1;
1180 dc->caps.is_apu = true;
1181 dc->caps.post_blend_color_processing = false;
1182 /* Raven DP PHY HBR2 eye diagram pattern is not stable. Use TP4 */
1183 dc->caps.force_dp_tps4_for_cp2520 = true;
1185 if (dc->ctx->dce_environment == DCE_ENV_PRODUCTION_DRV)
1186 dc->debug = debug_defaults_drv;
1188 dc->debug = debug_defaults_diags;
1190 /*************************************************
1191 * Create resources *
1192 *************************************************/
1194 pool->base.clock_sources[DCN10_CLK_SRC_PLL0] =
1195 dcn10_clock_source_create(ctx, ctx->dc_bios,
1196 CLOCK_SOURCE_COMBO_PHY_PLL0,
1197 &clk_src_regs[0], false);
1198 pool->base.clock_sources[DCN10_CLK_SRC_PLL1] =
1199 dcn10_clock_source_create(ctx, ctx->dc_bios,
1200 CLOCK_SOURCE_COMBO_PHY_PLL1,
1201 &clk_src_regs[1], false);
1202 pool->base.clock_sources[DCN10_CLK_SRC_PLL2] =
1203 dcn10_clock_source_create(ctx, ctx->dc_bios,
1204 CLOCK_SOURCE_COMBO_PHY_PLL2,
1205 &clk_src_regs[2], false);
1207 #ifdef CONFIG_DRM_AMD_DC_DCN1_01
1208 if (dc->ctx->dce_version == DCN_VERSION_1_0) {
1209 pool->base.clock_sources[DCN10_CLK_SRC_PLL3] =
1210 dcn10_clock_source_create(ctx, ctx->dc_bios,
1211 CLOCK_SOURCE_COMBO_PHY_PLL3,
1212 &clk_src_regs[3], false);
1215 pool->base.clock_sources[DCN10_CLK_SRC_PLL3] =
1216 dcn10_clock_source_create(ctx, ctx->dc_bios,
1217 CLOCK_SOURCE_COMBO_PHY_PLL3,
1218 &clk_src_regs[3], false);
1221 pool->base.clk_src_count = DCN10_CLK_SRC_TOTAL;
1223 #if defined(CONFIG_DRM_AMD_DC_DCN1_01)
1224 if (dc->ctx->dce_version == DCN_VERSION_1_01)
1225 pool->base.clk_src_count = DCN101_CLK_SRC_TOTAL;
1228 pool->base.dp_clock_source =
1229 dcn10_clock_source_create(ctx, ctx->dc_bios,
1230 CLOCK_SOURCE_ID_DP_DTO,
1231 /* todo: not reuse phy_pll registers */
1232 &clk_src_regs[0], true);
1234 for (i = 0; i < pool->base.clk_src_count; i++) {
1235 if (pool->base.clock_sources[i] == NULL) {
1236 dm_error("DC: failed to create clock sources!\n");
1237 BREAK_TO_DEBUGGER();
1242 pool->base.dccg = dcn1_dccg_create(ctx);
1243 if (pool->base.dccg == NULL) {
1244 dm_error("DC: failed to create display clock!\n");
1245 BREAK_TO_DEBUGGER();
1249 pool->base.dmcu = dcn10_dmcu_create(ctx,
1253 if (pool->base.dmcu == NULL) {
1254 dm_error("DC: failed to create dmcu!\n");
1255 BREAK_TO_DEBUGGER();
1259 pool->base.abm = dce_abm_create(ctx,
1263 if (pool->base.abm == NULL) {
1264 dm_error("DC: failed to create abm!\n");
1265 BREAK_TO_DEBUGGER();
1269 dml_init_instance(&dc->dml, DML_PROJECT_RAVEN1);
1270 memcpy(dc->dcn_ip, &dcn10_ip_defaults, sizeof(dcn10_ip_defaults));
1271 memcpy(dc->dcn_soc, &dcn10_soc_defaults, sizeof(dcn10_soc_defaults));
1273 #if defined(CONFIG_DRM_AMD_DC_DCN1_01)
1274 if (dc->ctx->dce_version == DCN_VERSION_1_01) {
1275 struct dcn_soc_bounding_box *dcn_soc = dc->dcn_soc;
1276 struct dcn_ip_params *dcn_ip = dc->dcn_ip;
1277 struct display_mode_lib *dml = &dc->dml;
1279 dml->ip.max_num_dpp = 3;
1280 /* TODO how to handle 23.84? */
1281 dcn_soc->dram_clock_change_latency = 23;
1282 dcn_ip->max_num_dpp = 3;
1285 if (ASICREV_IS_RV1_F0(dc->ctx->asic_id.hw_internal_rev)) {
1286 dc->dcn_soc->urgent_latency = 3;
1287 dc->debug.disable_dmcu = true;
1288 dc->dcn_soc->fabric_and_dram_bandwidth_vmax0p9 = 41.60f;
1292 dc->dcn_soc->number_of_channels = dc->ctx->asic_id.vram_width / ddr4_dram_width;
1293 ASSERT(dc->dcn_soc->number_of_channels < 3);
1294 if (dc->dcn_soc->number_of_channels == 0)/*old sbios bug*/
1295 dc->dcn_soc->number_of_channels = 2;
1297 if (dc->dcn_soc->number_of_channels == 1) {
1298 dc->dcn_soc->fabric_and_dram_bandwidth_vmax0p9 = 19.2f;
1299 dc->dcn_soc->fabric_and_dram_bandwidth_vnom0p8 = 17.066f;
1300 dc->dcn_soc->fabric_and_dram_bandwidth_vmid0p72 = 14.933f;
1301 dc->dcn_soc->fabric_and_dram_bandwidth_vmin0p65 = 12.8f;
1302 if (ASICREV_IS_RV1_F0(dc->ctx->asic_id.hw_internal_rev)) {
1303 dc->dcn_soc->fabric_and_dram_bandwidth_vmax0p9 = 20.80f;
1307 pool->base.pp_smu = dcn10_pp_smu_create(ctx);
1309 if (!dc->debug.disable_pplib_clock_request)
1310 dcn_bw_update_from_pplib(dc);
1311 dcn_bw_sync_calcs_and_dml(dc);
1312 if (!dc->debug.disable_pplib_wm_range) {
1313 dc->res_pool = &pool->base;
1314 dcn_bw_notify_pplib_of_wm_ranges(dc);
1318 struct irq_service_init_data init_data;
1319 init_data.ctx = dc->ctx;
1320 pool->base.irqs = dal_irq_service_dcn10_create(&init_data);
1321 if (!pool->base.irqs)
1325 /* index to valid pipe resource */
1327 /* mem input -> ipp -> dpp -> opp -> TG */
1328 for (i = 0; i < pool->base.pipe_count; i++) {
1329 /* if pipe is disabled, skip instance of HW pipe,
1330 * i.e, skip ASIC register instance
1332 if ((pipe_fuses & (1 << i)) != 0)
1335 pool->base.hubps[j] = dcn10_hubp_create(ctx, i);
1336 if (pool->base.hubps[j] == NULL) {
1337 BREAK_TO_DEBUGGER();
1339 "DC: failed to create memory input!\n");
1343 pool->base.ipps[j] = dcn10_ipp_create(ctx, i);
1344 if (pool->base.ipps[j] == NULL) {
1345 BREAK_TO_DEBUGGER();
1347 "DC: failed to create input pixel processor!\n");
1351 pool->base.dpps[j] = dcn10_dpp_create(ctx, i);
1352 if (pool->base.dpps[j] == NULL) {
1353 BREAK_TO_DEBUGGER();
1355 "DC: failed to create dpp!\n");
1359 pool->base.opps[j] = dcn10_opp_create(ctx, i);
1360 if (pool->base.opps[j] == NULL) {
1361 BREAK_TO_DEBUGGER();
1363 "DC: failed to create output pixel processor!\n");
1367 pool->base.timing_generators[j] = dcn10_timing_generator_create(
1369 if (pool->base.timing_generators[j] == NULL) {
1370 BREAK_TO_DEBUGGER();
1371 dm_error("DC: failed to create tg!\n");
1374 /* check next valid pipe */
1378 for (i = 0; i < pool->base.res_cap->num_ddc; i++) {
1379 pool->base.engines[i] = dcn10_aux_engine_create(ctx, i);
1380 if (pool->base.engines[i] == NULL) {
1381 BREAK_TO_DEBUGGER();
1383 "DC:failed to create aux engine!!\n");
1386 pool->base.hw_i2cs[i] = dcn10_i2c_hw_create(ctx, i);
1387 if (pool->base.hw_i2cs[i] == NULL) {
1388 BREAK_TO_DEBUGGER();
1390 "DC:failed to create hw i2c!!\n");
1393 pool->base.sw_i2cs[i] = NULL;
1396 /* valid pipe num */
1397 pool->base.pipe_count = j;
1398 pool->base.timing_generator_count = j;
1400 /* within dml lib, it is hard code to 4. If ASIC pipe is fused,
1401 * the value may be changed
1403 dc->dml.ip.max_num_dpp = pool->base.pipe_count;
1404 dc->dcn_ip->max_num_dpp = pool->base.pipe_count;
1406 pool->base.mpc = dcn10_mpc_create(ctx);
1407 if (pool->base.mpc == NULL) {
1408 BREAK_TO_DEBUGGER();
1409 dm_error("DC: failed to create mpc!\n");
1413 pool->base.hubbub = dcn10_hubbub_create(ctx);
1414 if (pool->base.hubbub == NULL) {
1415 BREAK_TO_DEBUGGER();
1416 dm_error("DC: failed to create hubbub!\n");
1420 if (!resource_construct(num_virtual_links, dc, &pool->base,
1421 (!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment) ?
1422 &res_create_funcs : &res_create_maximus_funcs)))
1425 dcn10_hw_sequencer_construct(dc);
1426 dc->caps.max_planes = pool->base.pipe_count;
1428 dc->cap_funcs = cap_funcs;
1439 struct resource_pool *dcn10_create_resource_pool(
1440 uint8_t num_virtual_links,
1443 struct dcn10_resource_pool *pool =
1444 kzalloc(sizeof(struct dcn10_resource_pool), GFP_KERNEL);
1449 if (construct(num_virtual_links, dc, pool))
1452 BREAK_TO_DEBUGGER();